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authorYi Li <yi.li@analog.com>2009-01-07 10:14:39 -0500
committerBryan Wu <cooloney@kernel.org>2009-01-07 10:14:39 -0500
commit6a01f230339321292cf065551f8cf55361052461 (patch)
tree7ac2ac8fc9f05a7315ef6a7f6f0a387433c62c14 /arch/blackfin/include/asm
parent5105432a3201e3f0e6c219cd0a74feee1e5e262b (diff)
Blackfin arch: merge adeos blackfin part to arch/blackfin/
[Mike Frysinger <vapier.adi@gmail.com>: - handle bf531/bf532/bf534/bf536 variants in ipipe.h - cleanup IPIPE logic for bfin_set_irq_handler() - cleanup ipipe asm code a bit and add missing ENDPROC() - simplify IPIPE code in trap_c - unify some of the IPIPE code and fix style - simplify DO_IRQ_L1 handling with ipipe code - revert IRQ_SW_INT# addition from ipipe merge - remove duplicate get_{c,s}clk() prototypes ] Signed-off-by: Yi Li <yi.li@analog.com> Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/include/asm')
-rw-r--r--arch/blackfin/include/asm/atomic.h32
-rw-r--r--arch/blackfin/include/asm/bitops.h24
-rw-r--r--arch/blackfin/include/asm/entry.h9
-rw-r--r--arch/blackfin/include/asm/ipipe.h278
-rw-r--r--arch/blackfin/include/asm/ipipe_base.h80
-rw-r--r--arch/blackfin/include/asm/irq.h223
-rw-r--r--arch/blackfin/include/asm/system.h4
7 files changed, 593 insertions, 57 deletions
diff --git a/arch/blackfin/include/asm/atomic.h b/arch/blackfin/include/asm/atomic.h
index d76275e5638c..94b2a9b19451 100644
--- a/arch/blackfin/include/asm/atomic.h
+++ b/arch/blackfin/include/asm/atomic.h
@@ -92,18 +92,18 @@ static inline void atomic_add(int i, atomic_t *v)
92{ 92{
93 long flags; 93 long flags;
94 94
95 local_irq_save(flags); 95 local_irq_save_hw(flags);
96 v->counter += i; 96 v->counter += i;
97 local_irq_restore(flags); 97 local_irq_restore_hw(flags);
98} 98}
99 99
100static inline void atomic_sub(int i, atomic_t *v) 100static inline void atomic_sub(int i, atomic_t *v)
101{ 101{
102 long flags; 102 long flags;
103 103
104 local_irq_save(flags); 104 local_irq_save_hw(flags);
105 v->counter -= i; 105 v->counter -= i;
106 local_irq_restore(flags); 106 local_irq_restore_hw(flags);
107 107
108} 108}
109 109
@@ -112,10 +112,10 @@ static inline int atomic_add_return(int i, atomic_t *v)
112 int __temp = 0; 112 int __temp = 0;
113 long flags; 113 long flags;
114 114
115 local_irq_save(flags); 115 local_irq_save_hw(flags);
116 v->counter += i; 116 v->counter += i;
117 __temp = v->counter; 117 __temp = v->counter;
118 local_irq_restore(flags); 118 local_irq_restore_hw(flags);
119 119
120 120
121 return __temp; 121 return __temp;
@@ -126,10 +126,10 @@ static inline int atomic_sub_return(int i, atomic_t *v)
126 int __temp = 0; 126 int __temp = 0;
127 long flags; 127 long flags;
128 128
129 local_irq_save(flags); 129 local_irq_save_hw(flags);
130 v->counter -= i; 130 v->counter -= i;
131 __temp = v->counter; 131 __temp = v->counter;
132 local_irq_restore(flags); 132 local_irq_restore_hw(flags);
133 133
134 return __temp; 134 return __temp;
135} 135}
@@ -138,36 +138,36 @@ static inline void atomic_inc(volatile atomic_t *v)
138{ 138{
139 long flags; 139 long flags;
140 140
141 local_irq_save(flags); 141 local_irq_save_hw(flags);
142 v->counter++; 142 v->counter++;
143 local_irq_restore(flags); 143 local_irq_restore_hw(flags);
144} 144}
145 145
146static inline void atomic_dec(volatile atomic_t *v) 146static inline void atomic_dec(volatile atomic_t *v)
147{ 147{
148 long flags; 148 long flags;
149 149
150 local_irq_save(flags); 150 local_irq_save_hw(flags);
151 v->counter--; 151 v->counter--;
152 local_irq_restore(flags); 152 local_irq_restore_hw(flags);
153} 153}
154 154
155static inline void atomic_clear_mask(unsigned int mask, atomic_t *v) 155static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
156{ 156{
157 long flags; 157 long flags;
158 158
159 local_irq_save(flags); 159 local_irq_save_hw(flags);
160 v->counter &= ~mask; 160 v->counter &= ~mask;
161 local_irq_restore(flags); 161 local_irq_restore_hw(flags);
162} 162}
163 163
164static inline void atomic_set_mask(unsigned int mask, atomic_t *v) 164static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
165{ 165{
166 long flags; 166 long flags;
167 167
168 local_irq_save(flags); 168 local_irq_save_hw(flags);
169 v->counter |= mask; 169 v->counter |= mask;
170 local_irq_restore(flags); 170 local_irq_restore_hw(flags);
171} 171}
172 172
173/* Atomic operations are already serializing */ 173/* Atomic operations are already serializing */
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h
index 9964e17232e9..21b036eadab1 100644
--- a/arch/blackfin/include/asm/bitops.h
+++ b/arch/blackfin/include/asm/bitops.h
@@ -90,9 +90,9 @@ static inline void set_bit(int nr, volatile unsigned long *addr)
90 unsigned long flags; 90 unsigned long flags;
91 a += nr >> 5; 91 a += nr >> 5;
92 mask = 1 << (nr & 0x1f); 92 mask = 1 << (nr & 0x1f);
93 local_irq_save(flags); 93 local_irq_save_hw(flags);
94 *a |= mask; 94 *a |= mask;
95 local_irq_restore(flags); 95 local_irq_restore_hw(flags);
96} 96}
97 97
98static inline void clear_bit(int nr, volatile unsigned long *addr) 98static inline void clear_bit(int nr, volatile unsigned long *addr)
@@ -102,9 +102,9 @@ static inline void clear_bit(int nr, volatile unsigned long *addr)
102 unsigned long flags; 102 unsigned long flags;
103 a += nr >> 5; 103 a += nr >> 5;
104 mask = 1 << (nr & 0x1f); 104 mask = 1 << (nr & 0x1f);
105 local_irq_save(flags); 105 local_irq_save_hw(flags);
106 *a &= ~mask; 106 *a &= ~mask;
107 local_irq_restore(flags); 107 local_irq_restore_hw(flags);
108} 108}
109 109
110static inline void change_bit(int nr, volatile unsigned long *addr) 110static inline void change_bit(int nr, volatile unsigned long *addr)
@@ -114,9 +114,9 @@ static inline void change_bit(int nr, volatile unsigned long *addr)
114 114
115 ADDR += nr >> 5; 115 ADDR += nr >> 5;
116 mask = 1 << (nr & 31); 116 mask = 1 << (nr & 31);
117 local_irq_save(flags); 117 local_irq_save_hw(flags);
118 *ADDR ^= mask; 118 *ADDR ^= mask;
119 local_irq_restore(flags); 119 local_irq_restore_hw(flags);
120} 120}
121 121
122static inline int test_and_set_bit(int nr, volatile unsigned long *addr) 122static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
@@ -127,10 +127,10 @@ static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
127 127
128 a += nr >> 5; 128 a += nr >> 5;
129 mask = 1 << (nr & 0x1f); 129 mask = 1 << (nr & 0x1f);
130 local_irq_save(flags); 130 local_irq_save_hw(flags);
131 retval = (mask & *a) != 0; 131 retval = (mask & *a) != 0;
132 *a |= mask; 132 *a |= mask;
133 local_irq_restore(flags); 133 local_irq_restore_hw(flags);
134 134
135 return retval; 135 return retval;
136} 136}
@@ -143,10 +143,10 @@ static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
143 143
144 a += nr >> 5; 144 a += nr >> 5;
145 mask = 1 << (nr & 0x1f); 145 mask = 1 << (nr & 0x1f);
146 local_irq_save(flags); 146 local_irq_save_hw(flags);
147 retval = (mask & *a) != 0; 147 retval = (mask & *a) != 0;
148 *a &= ~mask; 148 *a &= ~mask;
149 local_irq_restore(flags); 149 local_irq_restore_hw(flags);
150 150
151 return retval; 151 return retval;
152} 152}
@@ -159,10 +159,10 @@ static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
159 159
160 a += nr >> 5; 160 a += nr >> 5;
161 mask = 1 << (nr & 0x1f); 161 mask = 1 << (nr & 0x1f);
162 local_irq_save(flags); 162 local_irq_save_hw(flags);
163 retval = (mask & *a) != 0; 163 retval = (mask & *a) != 0;
164 *a ^= mask; 164 *a ^= mask;
165 local_irq_restore(flags); 165 local_irq_restore_hw(flags);
166 return retval; 166 return retval;
167} 167}
168 168
diff --git a/arch/blackfin/include/asm/entry.h b/arch/blackfin/include/asm/entry.h
index d94e4f5139d2..b30a2968e274 100644
--- a/arch/blackfin/include/asm/entry.h
+++ b/arch/blackfin/include/asm/entry.h
@@ -27,6 +27,14 @@
27#define SAVE_ALL_SYS save_context_no_interrupts 27#define SAVE_ALL_SYS save_context_no_interrupts
28/* This is used for all normal interrupts. It saves a minimum of registers 28/* This is used for all normal interrupts. It saves a minimum of registers
29 to the stack, loads the IRQ number, and jumps to common code. */ 29 to the stack, loads the IRQ number, and jumps to common code. */
30#ifdef CONFIG_IPIPE
31# define LOAD_IPIPE_IPEND \
32 P0.l = lo(IPEND); \
33 P0.h = hi(IPEND); \
34 R1 = [P0];
35#else
36# define LOAD_IPIPE_IPEND
37#endif
30#define INTERRUPT_ENTRY(N) \ 38#define INTERRUPT_ENTRY(N) \
31 [--sp] = SYSCFG; \ 39 [--sp] = SYSCFG; \
32 \ 40 \
@@ -34,6 +42,7 @@
34 [--sp] = R0; /*orig_r0*/ \ 42 [--sp] = R0; /*orig_r0*/ \
35 [--sp] = (R7:0,P5:0); \ 43 [--sp] = (R7:0,P5:0); \
36 R0 = (N); \ 44 R0 = (N); \
45 LOAD_IPIPE_IPEND \
37 jump __common_int_entry; 46 jump __common_int_entry;
38 47
39/* For timer interrupts, we need to save IPEND, since the user_mode 48/* For timer interrupts, we need to save IPEND, since the user_mode
diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h
new file mode 100644
index 000000000000..76f53d8b9a0d
--- /dev/null
+++ b/arch/blackfin/include/asm/ipipe.h
@@ -0,0 +1,278 @@
1/* -*- linux-c -*-
2 * include/asm-blackfin/ipipe.h
3 *
4 * Copyright (C) 2002-2007 Philippe Gerum.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
9 * USA; either version 2 of the License, or (at your option) any later
10 * version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef __ASM_BLACKFIN_IPIPE_H
23#define __ASM_BLACKFIN_IPIPE_H
24
25#ifdef CONFIG_IPIPE
26
27#include <linux/cpumask.h>
28#include <linux/list.h>
29#include <linux/threads.h>
30#include <linux/irq.h>
31#include <linux/ipipe_percpu.h>
32#include <asm/ptrace.h>
33#include <asm/irq.h>
34#include <asm/bitops.h>
35#include <asm/atomic.h>
36#include <asm/traps.h>
37
38#define IPIPE_ARCH_STRING "1.8-00"
39#define IPIPE_MAJOR_NUMBER 1
40#define IPIPE_MINOR_NUMBER 8
41#define IPIPE_PATCH_NUMBER 0
42
43#ifdef CONFIG_SMP
44#error "I-pipe/blackfin: SMP not implemented"
45#else /* !CONFIG_SMP */
46#define ipipe_processor_id() 0
47#endif /* CONFIG_SMP */
48
49#define prepare_arch_switch(next) \
50do { \
51 ipipe_schedule_notify(current, next); \
52 local_irq_disable_hw(); \
53} while (0)
54
55#define task_hijacked(p) \
56 ({ \
57 int __x__ = ipipe_current_domain != ipipe_root_domain; \
58 /* We would need to clear the SYNC flag for the root domain */ \
59 /* over the current processor in SMP mode. */ \
60 local_irq_enable_hw(); __x__; \
61 })
62
63struct ipipe_domain;
64
65struct ipipe_sysinfo {
66
67 int ncpus; /* Number of CPUs on board */
68 u64 cpufreq; /* CPU frequency (in Hz) */
69
70 /* Arch-dependent block */
71
72 struct {
73 unsigned tmirq; /* Timer tick IRQ */
74 u64 tmfreq; /* Timer frequency */
75 } archdep;
76};
77
78#define ipipe_read_tsc(t) \
79 ({ \
80 unsigned long __cy2; \
81 __asm__ __volatile__ ("1: %0 = CYCLES2\n" \
82 "%1 = CYCLES\n" \
83 "%2 = CYCLES2\n" \
84 "CC = %2 == %0\n" \
85 "if ! CC jump 1b\n" \
86 : "=r" (((unsigned long *)&t)[1]), \
87 "=r" (((unsigned long *)&t)[0]), \
88 "=r" (__cy2) \
89 : /*no input*/ : "CC"); \
90 t; \
91 })
92
93#define ipipe_cpu_freq() __ipipe_core_clock
94#define ipipe_tsc2ns(_t) (((unsigned long)(_t)) * __ipipe_freq_scale)
95#define ipipe_tsc2us(_t) (ipipe_tsc2ns(_t) / 1000 + 1)
96
97/* Private interface -- Internal use only */
98
99#define __ipipe_check_platform() do { } while (0)
100
101#define __ipipe_init_platform() do { } while (0)
102
103extern atomic_t __ipipe_irq_lvdepth[IVG15 + 1];
104
105extern unsigned long __ipipe_irq_lvmask;
106
107extern struct ipipe_domain ipipe_root;
108
109/* enable/disable_irqdesc _must_ be used in pairs. */
110
111void __ipipe_enable_irqdesc(struct ipipe_domain *ipd,
112 unsigned irq);
113
114void __ipipe_disable_irqdesc(struct ipipe_domain *ipd,
115 unsigned irq);
116
117#define __ipipe_enable_irq(irq) (irq_desc[irq].chip->unmask(irq))
118
119#define __ipipe_disable_irq(irq) (irq_desc[irq].chip->mask(irq))
120
121#define __ipipe_lock_root() \
122 set_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags)
123
124#define __ipipe_unlock_root() \
125 clear_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags)
126
127void __ipipe_enable_pipeline(void);
128
129#define __ipipe_hook_critical_ipi(ipd) do { } while (0)
130
131#define __ipipe_sync_pipeline(syncmask) \
132 do { \
133 struct ipipe_domain *ipd = ipipe_current_domain; \
134 if (likely(ipd != ipipe_root_domain || !test_bit(IPIPE_ROOTLOCK_FLAG, &ipd->flags))) \
135 __ipipe_sync_stage(syncmask); \
136 } while (0)
137
138void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs);
139
140int __ipipe_get_irq_priority(unsigned irq);
141
142int __ipipe_get_irqthread_priority(unsigned irq);
143
144void __ipipe_stall_root_raw(void);
145
146void __ipipe_unstall_root_raw(void);
147
148void __ipipe_serial_debug(const char *fmt, ...);
149
150DECLARE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
151
152extern unsigned long __ipipe_core_clock;
153
154extern unsigned long __ipipe_freq_scale;
155
156extern unsigned long __ipipe_irq_tail_hook;
157
158static inline unsigned long __ipipe_ffnz(unsigned long ul)
159{
160 return ffs(ul) - 1;
161}
162
163#define __ipipe_run_irqtail() /* Must be a macro */ \
164 do { \
165 asmlinkage void __ipipe_call_irqtail(void); \
166 unsigned long __pending; \
167 CSYNC(); \
168 __pending = bfin_read_IPEND(); \
169 if (__pending & 0x8000) { \
170 __pending &= ~0x8010; \
171 if (__pending && (__pending & (__pending - 1)) == 0) \
172 __ipipe_call_irqtail(); \
173 } \
174 } while (0)
175
176#define __ipipe_run_isr(ipd, irq) \
177 do { \
178 if (ipd == ipipe_root_domain) { \
179 /* \
180 * Note: the I-pipe implements a threaded interrupt model on \
181 * this arch for Linux external IRQs. The interrupt handler we \
182 * call here only wakes up the associated IRQ thread. \
183 */ \
184 if (ipipe_virtual_irq_p(irq)) { \
185 /* No irqtail here; virtual interrupts have no effect \
186 on IPEND so there is no need for processing \
187 deferral. */ \
188 local_irq_enable_nohead(ipd); \
189 ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \
190 local_irq_disable_nohead(ipd); \
191 } else \
192 /* \
193 * No need to run the irqtail here either; \
194 * we can't be preempted by hw IRQs, so \
195 * non-Linux IRQs cannot stack over the short \
196 * thread wakeup code. Which in turn means \
197 * that no irqtail condition could be pending \
198 * for domains above Linux in the pipeline. \
199 */ \
200 ipd->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); \
201 } else { \
202 __clear_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \
203 local_irq_enable_nohead(ipd); \
204 ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \
205 /* Attempt to exit the outer interrupt level before \
206 * starting the deferred IRQ processing. */ \
207 local_irq_disable_nohead(ipd); \
208 __ipipe_run_irqtail(); \
209 __set_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \
210 } \
211 } while (0)
212
213#define __ipipe_syscall_watched_p(p, sc) \
214 (((p)->flags & PF_EVNOTIFY) || (unsigned long)sc >= NR_syscalls)
215
216void ipipe_init_irq_threads(void);
217
218int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
219
220#define IS_SYSIRQ(irq) ((irq) > IRQ_CORETMR && (irq) <= SYS_IRQS)
221#define IS_GPIOIRQ(irq) ((irq) >= GPIO_IRQ_BASE && (irq) < NR_IRQS)
222
223#define IRQ_SYSTMR IRQ_TIMER0
224#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0
225
226#if defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533)
227#define PRIO_GPIODEMUX(irq) CONFIG_PFA
228#elif defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537)
229#define PRIO_GPIODEMUX(irq) CONFIG_IRQ_PROG_INTA
230#elif defined(CONFIG_BF52x)
231#define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PORTF_INTA ? CONFIG_IRQ_PORTF_INTA : \
232 (irq) == IRQ_PORTG_INTA ? CONFIG_IRQ_PORTG_INTA : \
233 (irq) == IRQ_PORTH_INTA ? CONFIG_IRQ_PORTH_INTA : \
234 -1)
235#elif defined(CONFIG_BF561)
236#define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PROG0_INTA ? CONFIG_IRQ_PROG0_INTA : \
237 (irq) == IRQ_PROG1_INTA ? CONFIG_IRQ_PROG1_INTA : \
238 (irq) == IRQ_PROG2_INTA ? CONFIG_IRQ_PROG2_INTA : \
239 -1)
240#define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val)
241#define bfin_write_TIMER_ENABLE(val) bfin_write_TMRS8_ENABLE(val)
242#define bfin_write_TIMER_STATUS(val) bfin_write_TMRS8_STATUS(val)
243#define bfin_read_TIMER_STATUS() bfin_read_TMRS8_STATUS()
244#elif defined(CONFIG_BF54x)
245#define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PINT0 ? CONFIG_IRQ_PINT0 : \
246 (irq) == IRQ_PINT1 ? CONFIG_IRQ_PINT1 : \
247 (irq) == IRQ_PINT2 ? CONFIG_IRQ_PINT2 : \
248 (irq) == IRQ_PINT3 ? CONFIG_IRQ_PINT3 : \
249 -1)
250#define bfin_write_TIMER_DISABLE(val) bfin_write_TIMER_DISABLE0(val)
251#define bfin_write_TIMER_ENABLE(val) bfin_write_TIMER_ENABLE0(val)
252#define bfin_write_TIMER_STATUS(val) bfin_write_TIMER_STATUS0(val)
253#define bfin_read_TIMER_STATUS(val) bfin_read_TIMER_STATUS0(val)
254#else
255# error "no PRIO_GPIODEMUX() for this part"
256#endif
257
258#define __ipipe_root_tick_p(regs) ((regs->ipend & 0x10) != 0)
259
260#else /* !CONFIG_IPIPE */
261
262#define task_hijacked(p) 0
263#define ipipe_trap_notify(t, r) 0
264
265#define __ipipe_stall_root_raw() do { } while (0)
266#define __ipipe_unstall_root_raw() do { } while (0)
267
268#define ipipe_init_irq_threads() do { } while (0)
269#define ipipe_start_irq_thread(irq, desc) 0
270
271#define IRQ_SYSTMR IRQ_CORETMR
272#define IRQ_PRIOTMR IRQ_CORETMR
273
274#define __ipipe_root_tick_p(regs) 1
275
276#endif /* !CONFIG_IPIPE */
277
278#endif /* !__ASM_BLACKFIN_IPIPE_H */
diff --git a/arch/blackfin/include/asm/ipipe_base.h b/arch/blackfin/include/asm/ipipe_base.h
new file mode 100644
index 000000000000..cb1025aeabcf
--- /dev/null
+++ b/arch/blackfin/include/asm/ipipe_base.h
@@ -0,0 +1,80 @@
1/* -*- linux-c -*-
2 * include/asm-blackfin/_baseipipe.h
3 *
4 * Copyright (C) 2007 Philippe Gerum.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
9 * USA; either version 2 of the License, or (at your option) any later
10 * version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef __ASM_BLACKFIN_IPIPE_BASE_H
23#define __ASM_BLACKFIN_IPIPE_BASE_H
24
25#ifdef CONFIG_IPIPE
26
27#define IPIPE_NR_XIRQS NR_IRQS
28#define IPIPE_IRQ_ISHIFT 5 /* 2^5 for 32bits arch. */
29
30/* Blackfin-specific, global domain flags */
31#define IPIPE_ROOTLOCK_FLAG 1 /* Lock pipeline for root */
32
33 /* Blackfin traps -- i.e. exception vector numbers */
34#define IPIPE_NR_FAULTS 52 /* We leave a gap after VEC_ILL_RES. */
35/* Pseudo-vectors used for kernel events */
36#define IPIPE_FIRST_EVENT IPIPE_NR_FAULTS
37#define IPIPE_EVENT_SYSCALL (IPIPE_FIRST_EVENT)
38#define IPIPE_EVENT_SCHEDULE (IPIPE_FIRST_EVENT + 1)
39#define IPIPE_EVENT_SIGWAKE (IPIPE_FIRST_EVENT + 2)
40#define IPIPE_EVENT_SETSCHED (IPIPE_FIRST_EVENT + 3)
41#define IPIPE_EVENT_INIT (IPIPE_FIRST_EVENT + 4)
42#define IPIPE_EVENT_EXIT (IPIPE_FIRST_EVENT + 5)
43#define IPIPE_EVENT_CLEANUP (IPIPE_FIRST_EVENT + 6)
44#define IPIPE_LAST_EVENT IPIPE_EVENT_CLEANUP
45#define IPIPE_NR_EVENTS (IPIPE_LAST_EVENT + 1)
46
47#define IPIPE_TIMER_IRQ IRQ_CORETMR
48
49#ifndef __ASSEMBLY__
50
51#include <linux/bitops.h>
52
53extern int test_bit(int nr, const void *addr);
54
55
56extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */
57
58static inline void __ipipe_stall_root(void)
59{
60 volatile unsigned long *p = &__ipipe_root_status;
61 set_bit(0, p);
62}
63
64static inline unsigned long __ipipe_test_and_stall_root(void)
65{
66 volatile unsigned long *p = &__ipipe_root_status;
67 return test_and_set_bit(0, p);
68}
69
70static inline unsigned long __ipipe_test_root(void)
71{
72 const unsigned long *p = &__ipipe_root_status;
73 return test_bit(0, p);
74}
75
76#endif /* !__ASSEMBLY__ */
77
78#endif /* CONFIG_IPIPE */
79
80#endif /* !__ASM_BLACKFIN_IPIPE_BASE_H */
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h
index 21e25f778a63..3d977909ce7d 100644
--- a/arch/blackfin/include/asm/irq.h
+++ b/arch/blackfin/include/asm/irq.h
@@ -22,11 +22,176 @@
22#include <asm/pda.h> 22#include <asm/pda.h>
23#include <asm/processor.h> 23#include <asm/processor.h>
24 24
25static __inline__ int irq_canonicalize(int irq) 25#ifdef CONFIG_SMP
26/* Forward decl needed due to cdef inter dependencies */
27static inline uint32_t __pure bfin_dspid(void);
28# define blackfin_core_id() (bfin_dspid() & 0xff)
29# define bfin_irq_flags cpu_pda[blackfin_core_id()].imask
30#else
31extern unsigned long bfin_irq_flags;
32#endif
33
34#ifdef CONFIG_IPIPE
35
36#include <linux/ipipe_trace.h>
37
38void __ipipe_unstall_root(void);
39
40void __ipipe_restore_root(unsigned long flags);
41
42#ifdef CONFIG_DEBUG_HWERR
43# define __all_masked_irq_flags 0x3f
44# define __save_and_cli_hw(x) \
45 __asm__ __volatile__( \
46 "cli %0;" \
47 "sti %1;" \
48 : "=&d"(x) \
49 : "d" (0x3F) \
50 )
51#else
52# define __all_masked_irq_flags 0x1f
53# define __save_and_cli_hw(x) \
54 __asm__ __volatile__( \
55 "cli %0;" \
56 : "=&d"(x) \
57 )
58#endif
59
60#define irqs_enabled_from_flags_hw(x) ((x) != __all_masked_irq_flags)
61#define raw_irqs_disabled_flags(flags) (!irqs_enabled_from_flags_hw(flags))
62#define local_test_iflag_hw(x) irqs_enabled_from_flags_hw(x)
63
64#define local_save_flags(x) \
65 do { \
66 (x) = __ipipe_test_root() ? \
67 __all_masked_irq_flags : bfin_irq_flags; \
68 } while (0)
69
70#define local_irq_save(x) \
71 do { \
72 (x) = __ipipe_test_and_stall_root(); \
73 } while (0)
74
75#define local_irq_restore(x) __ipipe_restore_root(x)
76#define local_irq_disable() __ipipe_stall_root()
77#define local_irq_enable() __ipipe_unstall_root()
78#define irqs_disabled() __ipipe_test_root()
79
80#define local_save_flags_hw(x) \
81 __asm__ __volatile__( \
82 "cli %0;" \
83 "sti %0;" \
84 : "=d"(x) \
85 )
86
87#define irqs_disabled_hw() \
88 ({ \
89 unsigned long flags; \
90 local_save_flags_hw(flags); \
91 !irqs_enabled_from_flags_hw(flags); \
92 })
93
94static inline unsigned long raw_mangle_irq_bits(int virt, unsigned long real)
26{ 95{
27 return irq; 96 /* Merge virtual and real interrupt mask bits into a single
97 32bit word. */
98 return (real & ~(1 << 31)) | ((virt != 0) << 31);
28} 99}
29 100
101static inline int raw_demangle_irq_bits(unsigned long *x)
102{
103 int virt = (*x & (1 << 31)) != 0;
104 *x &= ~(1L << 31);
105 return virt;
106}
107
108#ifdef CONFIG_IPIPE_TRACE_IRQSOFF
109
110#define local_irq_disable_hw() \
111 do { \
112 int _tmp_dummy; \
113 if (!irqs_disabled_hw()) \
114 ipipe_trace_begin(0x80000000); \
115 __asm__ __volatile__ ("cli %0;" : "=d" (_tmp_dummy) : ); \
116 } while (0)
117
118#define local_irq_enable_hw() \
119 do { \
120 if (irqs_disabled_hw()) \
121 ipipe_trace_end(0x80000000); \
122 __asm__ __volatile__ ("sti %0;" : : "d"(bfin_irq_flags)); \
123 } while (0)
124
125#define local_irq_save_hw(x) \
126 do { \
127 __save_and_cli_hw(x); \
128 if (local_test_iflag_hw(x)) \
129 ipipe_trace_begin(0x80000001); \
130 } while (0)
131
132#define local_irq_restore_hw(x) \
133 do { \
134 if (local_test_iflag_hw(x)) { \
135 ipipe_trace_end(0x80000001); \
136 local_irq_enable_hw_notrace(); \
137 } \
138 } while (0)
139
140#define local_irq_disable_hw_notrace() \
141 do { \
142 int _tmp_dummy; \
143 __asm__ __volatile__ ("cli %0;" : "=d" (_tmp_dummy) : ); \
144 } while (0)
145
146#define local_irq_enable_hw_notrace() \
147 __asm__ __volatile__( \
148 "sti %0;" \
149 : \
150 : "d"(bfin_irq_flags) \
151 )
152
153#define local_irq_save_hw_notrace(x) __save_and_cli_hw(x)
154
155#define local_irq_restore_hw_notrace(x) \
156 do { \
157 if (local_test_iflag_hw(x)) \
158 local_irq_enable_hw_notrace(); \
159 } while (0)
160
161#else /* CONFIG_IPIPE_TRACE_IRQSOFF */
162
163#define local_irq_enable_hw() \
164 __asm__ __volatile__( \
165 "sti %0;" \
166 : \
167 : "d"(bfin_irq_flags) \
168 )
169
170#define local_irq_disable_hw() \
171 do { \
172 int _tmp_dummy; \
173 __asm__ __volatile__ ( \
174 "cli %0;" \
175 : "=d" (_tmp_dummy)); \
176 } while (0)
177
178#define local_irq_restore_hw(x) \
179 do { \
180 if (irqs_enabled_from_flags_hw(x)) \
181 local_irq_enable_hw(); \
182 } while (0)
183
184#define local_irq_save_hw(x) __save_and_cli_hw(x)
185
186#define local_irq_disable_hw_notrace() local_irq_disable_hw()
187#define local_irq_enable_hw_notrace() local_irq_enable_hw()
188#define local_irq_save_hw_notrace(x) local_irq_save_hw(x)
189#define local_irq_restore_hw_notrace(x) local_irq_restore_hw(x)
190
191#endif /* CONFIG_IPIPE_TRACE_IRQSOFF */
192
193#else /* !CONFIG_IPIPE */
194
30/* 195/*
31 * Interrupt configuring macros. 196 * Interrupt configuring macros.
32 */ 197 */
@@ -39,21 +204,6 @@ static __inline__ int irq_canonicalize(int irq)
39 ); \ 204 ); \
40 } while (0) 205 } while (0)
41 206
42#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
43# define NOP_PAD_ANOMALY_05000244 "nop; nop;"
44#else
45# define NOP_PAD_ANOMALY_05000244
46#endif
47
48#ifdef CONFIG_SMP
49/* Forward decl needed due to cdef inter dependencies */
50static inline uint32_t __pure bfin_dspid(void);
51# define blackfin_core_id() (bfin_dspid() & 0xff)
52# define bfin_irq_flags cpu_pda[blackfin_core_id()].imask
53#else
54extern unsigned long bfin_irq_flags;
55#endif
56
57#define local_irq_enable() \ 207#define local_irq_enable() \
58 __asm__ __volatile__( \ 208 __asm__ __volatile__( \
59 "sti %0;" \ 209 "sti %0;" \
@@ -61,16 +211,6 @@ extern unsigned long bfin_irq_flags;
61 : "d" (bfin_irq_flags) \ 211 : "d" (bfin_irq_flags) \
62 ) 212 )
63 213
64#define idle_with_irq_disabled() \
65 __asm__ __volatile__( \
66 NOP_PAD_ANOMALY_05000244 \
67 ".align 8;" \
68 "sti %0;" \
69 "idle;" \
70 : \
71 : "d" (bfin_irq_flags) \
72 )
73
74#ifdef CONFIG_DEBUG_HWERR 214#ifdef CONFIG_DEBUG_HWERR
75# define __save_and_cli(x) \ 215# define __save_and_cli(x) \
76 __asm__ __volatile__( \ 216 __asm__ __volatile__( \
@@ -116,4 +256,33 @@ extern unsigned long bfin_irq_flags;
116 !irqs_enabled_from_flags(flags); \ 256 !irqs_enabled_from_flags(flags); \
117}) 257})
118 258
259#define local_irq_save_hw(x) local_irq_save(x)
260#define local_irq_restore_hw(x) local_irq_restore(x)
261#define local_irq_enable_hw() local_irq_enable()
262#define local_irq_disable_hw() local_irq_disable()
263#define irqs_disabled_hw() irqs_disabled()
264
265#endif /* !CONFIG_IPIPE */
266
267#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
268# define NOP_PAD_ANOMALY_05000244 "nop; nop;"
269#else
270# define NOP_PAD_ANOMALY_05000244
271#endif
272
273#define idle_with_irq_disabled() \
274 __asm__ __volatile__( \
275 NOP_PAD_ANOMALY_05000244 \
276 ".align 8;" \
277 "sti %0;" \
278 "idle;" \
279 : \
280 : "d" (bfin_irq_flags) \
281 )
282
283static inline int irq_canonicalize(int irq)
284{
285 return irq;
286}
287
119#endif /* _BFIN_IRQ_H_ */ 288#endif /* _BFIN_IRQ_H_ */
diff --git a/arch/blackfin/include/asm/system.h b/arch/blackfin/include/asm/system.h
index 812e6e6e2cee..a4c8254bec55 100644
--- a/arch/blackfin/include/asm/system.h
+++ b/arch/blackfin/include/asm/system.h
@@ -141,7 +141,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
141 unsigned long tmp = 0; 141 unsigned long tmp = 0;
142 unsigned long flags = 0; 142 unsigned long flags = 0;
143 143
144 local_irq_save(flags); 144 local_irq_save_hw(flags);
145 145
146 switch (size) { 146 switch (size) {
147 case 1: 147 case 1:
@@ -163,7 +163,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
163 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); 163 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
164 break; 164 break;
165 } 165 }
166 local_irq_restore(flags); 166 local_irq_restore_hw(flags);
167 return tmp; 167 return tmp;
168} 168}
169 169
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 17:21:28 -0500