diff options
author | Mike Frysinger <vapier@gentoo.org> | 2009-06-17 11:25:06 -0400 |
---|---|---|
committer | Mike Frysinger <vapier@gentoo.org> | 2009-06-22 21:16:07 -0400 |
commit | fa48f84a8cc722ca48b32fa0c338b6c3b358717d (patch) | |
tree | aa2d2d5f1ec674b2d4c70b506ef9cd0249715e14 /arch/blackfin/include/asm/mem_map.h | |
parent | 985895bd8d1e41079b41da32cdc57876a4a74126 (diff) |
Blackfin: unify memory map headers
Many aspects of the Blackfin memory map is exactly the same across all
variants. Rather than copy and paste all of these duplicated values in
each header, unify all of these into the common Blackfin memory map header
file. In the process, push down BF561 SMP specific stuff to the BF561
specific header to keep the noise down.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/include/asm/mem_map.h')
-rw-r--r-- | arch/blackfin/include/asm/mem_map.h | 97 |
1 files changed, 47 insertions, 50 deletions
diff --git a/arch/blackfin/include/asm/mem_map.h b/arch/blackfin/include/asm/mem_map.h index e92b31051bb7..5e21627c9ba2 100644 --- a/arch/blackfin/include/asm/mem_map.h +++ b/arch/blackfin/include/asm/mem_map.h | |||
@@ -1,87 +1,84 @@ | |||
1 | /* | 1 | /* |
2 | * mem_map.h | 2 | * Common Blackfin memory map |
3 | * Common header file for blackfin family of processors. | ||
4 | * | 3 | * |
4 | * Copyright 2004-2009 Analog Devices Inc. | ||
5 | * Licensed under the GPL-2 or later. | ||
5 | */ | 6 | */ |
6 | 7 | ||
7 | #ifndef _MEM_MAP_H_ | 8 | #ifndef __BFIN_MEM_MAP_H__ |
8 | #define _MEM_MAP_H_ | 9 | #define __BFIN_MEM_MAP_H__ |
9 | 10 | ||
10 | #include <mach/mem_map.h> | 11 | #include <mach/mem_map.h> |
11 | 12 | ||
12 | #ifndef __ASSEMBLY__ | 13 | /* Every Blackfin so far has MMRs like this */ |
14 | #ifndef COREMMR_BASE | ||
15 | # define COREMMR_BASE 0xFFE00000 | ||
16 | #endif | ||
17 | #ifndef SYSMMR_BASE | ||
18 | # define SYSMMR_BASE 0xFFC00000 | ||
19 | #endif | ||
13 | 20 | ||
14 | #ifdef CONFIG_SMP | 21 | /* Every Blackfin so far has on-chip Scratch Pad SRAM like this */ |
15 | static inline ulong get_l1_scratch_start_cpu(int cpu) | 22 | #ifndef L1_SCRATCH_START |
16 | { | 23 | # define L1_SCRATCH_START 0xFFB00000 |
17 | return (cpu) ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START; | 24 | # define L1_SCRATCH_LENGTH 0x1000 |
18 | } | 25 | #endif |
19 | static inline ulong get_l1_code_start_cpu(int cpu) | ||
20 | { | ||
21 | return (cpu) ? COREB_L1_CODE_START : COREA_L1_CODE_START; | ||
22 | } | ||
23 | static inline ulong get_l1_data_a_start_cpu(int cpu) | ||
24 | { | ||
25 | return (cpu) ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START; | ||
26 | } | ||
27 | static inline ulong get_l1_data_b_start_cpu(int cpu) | ||
28 | { | ||
29 | return (cpu) ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START; | ||
30 | } | ||
31 | 26 | ||
32 | static inline ulong get_l1_scratch_start(void) | 27 | /* Most parts lack on-chip L2 SRAM */ |
33 | { | 28 | #ifndef L2_START |
34 | return get_l1_scratch_start_cpu(blackfin_core_id()); | 29 | # define L2_START 0 |
35 | } | 30 | # define L2_LENGTH 0 |
36 | static inline ulong get_l1_code_start(void) | 31 | #endif |
37 | { | 32 | |
38 | return get_l1_code_start_cpu(blackfin_core_id()); | 33 | /* Most parts lack on-chip L1 ROM */ |
39 | } | 34 | #ifndef L1_ROM_START |
40 | static inline ulong get_l1_data_a_start(void) | 35 | # define L1_ROM_START 0 |
41 | { | 36 | # define L1_ROM_LENGTH 0 |
42 | return get_l1_data_a_start_cpu(blackfin_core_id()); | 37 | #endif |
43 | } | 38 | |
44 | static inline ulong get_l1_data_b_start(void) | 39 | /* Allow wonky SMP ports to override this */ |
45 | { | 40 | #ifndef GET_PDA_SAFE |
46 | return get_l1_data_b_start_cpu(blackfin_core_id()); | 41 | # define GET_PDA_SAFE(preg) \ |
47 | } | 42 | preg.l = _cpu_pda; \ |
43 | preg.h = _cpu_pda; | ||
44 | # define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) | ||
48 | 45 | ||
49 | #else /* !CONFIG_SMP */ | 46 | # ifndef __ASSEMBLY__ |
50 | 47 | ||
51 | static inline ulong get_l1_scratch_start_cpu(int cpu) | 48 | static inline unsigned long get_l1_scratch_start_cpu(int cpu) |
52 | { | 49 | { |
53 | return L1_SCRATCH_START; | 50 | return L1_SCRATCH_START; |
54 | } | 51 | } |
55 | static inline ulong get_l1_code_start_cpu(int cpu) | 52 | static inline unsigned long get_l1_code_start_cpu(int cpu) |
56 | { | 53 | { |
57 | return L1_CODE_START; | 54 | return L1_CODE_START; |
58 | } | 55 | } |
59 | static inline ulong get_l1_data_a_start_cpu(int cpu) | 56 | static inline unsigned long get_l1_data_a_start_cpu(int cpu) |
60 | { | 57 | { |
61 | return L1_DATA_A_START; | 58 | return L1_DATA_A_START; |
62 | } | 59 | } |
63 | static inline ulong get_l1_data_b_start_cpu(int cpu) | 60 | static inline unsigned long get_l1_data_b_start_cpu(int cpu) |
64 | { | 61 | { |
65 | return L1_DATA_B_START; | 62 | return L1_DATA_B_START; |
66 | } | 63 | } |
67 | static inline ulong get_l1_scratch_start(void) | 64 | static inline unsigned long get_l1_scratch_start(void) |
68 | { | 65 | { |
69 | return get_l1_scratch_start_cpu(0); | 66 | return get_l1_scratch_start_cpu(0); |
70 | } | 67 | } |
71 | static inline ulong get_l1_code_start(void) | 68 | static inline unsigned long get_l1_code_start(void) |
72 | { | 69 | { |
73 | return get_l1_code_start_cpu(0); | 70 | return get_l1_code_start_cpu(0); |
74 | } | 71 | } |
75 | static inline ulong get_l1_data_a_start(void) | 72 | static inline unsigned long get_l1_data_a_start(void) |
76 | { | 73 | { |
77 | return get_l1_data_a_start_cpu(0); | 74 | return get_l1_data_a_start_cpu(0); |
78 | } | 75 | } |
79 | static inline ulong get_l1_data_b_start(void) | 76 | static inline unsigned long get_l1_data_b_start(void) |
80 | { | 77 | { |
81 | return get_l1_data_b_start_cpu(0); | 78 | return get_l1_data_b_start_cpu(0); |
82 | } | 79 | } |
83 | 80 | ||
84 | #endif /* CONFIG_SMP */ | 81 | # endif /* __ASSEMBLY__ */ |
85 | #endif /* __ASSEMBLY__ */ | 82 | #endif /* !GET_PDA_SAFE */ |
86 | 83 | ||
87 | #endif /* _MEM_MAP_H_ */ | 84 | #endif |