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authorJie Zhang <jie.zhang@analog.com>2009-06-16 05:48:33 -0400
committerMike Frysinger <vapier@gentoo.org>2009-06-22 21:15:59 -0400
commit41ba653f24a39a0e6a4afe9b2763a95a57e042c2 (patch)
tree43eb086046d4eef764878e04512ddd215ca8845b /arch/blackfin/include/asm/cacheflush.h
parent7c039a90f02c3fdcab8d3ca170c05ad37014189e (diff)
Blackfin: decouple unrelated cache settings to get exact behavior
The current cache options don't really represent the hardware features. They end up setting different aspects of the hardware so that the end result is to turn on/off the cache. Unfortunately, when we hit cache problems with the hardware, it's difficult to test different settings to root cause the problem. The current settings also don't cleanly allow for different caching behaviors with different regions of memory. So split the configure options such that they properly reflect the settings that are applied to the hardware. Signed-off-by: Jie Zhang <jie.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/include/asm/cacheflush.h')
-rw-r--r--arch/blackfin/include/asm/cacheflush.h10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h
index 5c17dee53b5d..7e55549e180f 100644
--- a/arch/blackfin/include/asm/cacheflush.h
+++ b/arch/blackfin/include/asm/cacheflush.h
@@ -56,7 +56,7 @@ extern void blackfin_invalidate_entire_icache(void);
56 56
57static inline void flush_icache_range(unsigned start, unsigned end) 57static inline void flush_icache_range(unsigned start, unsigned end)
58{ 58{
59#if defined(CONFIG_BFIN_WB) 59#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
60 blackfin_dcache_flush_range(start, end); 60 blackfin_dcache_flush_range(start, end);
61#endif 61#endif
62 62
@@ -87,9 +87,9 @@ do { memcpy(dst, src, len); \
87#else 87#else
88# define invalidate_dcache_range(start,end) do { } while (0) 88# define invalidate_dcache_range(start,end) do { } while (0)
89#endif 89#endif
90#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_WB) 90#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
91# define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end)) 91# define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end))
92# define flush_dcache_page(page) blackfin_dflush_page(page_address(page)) 92# define flush_dcache_page(page) blackfin_dflush_page(page_address(page))
93#else 93#else
94# define flush_dcache_range(start,end) do { } while (0) 94# define flush_dcache_range(start,end) do { } while (0)
95# define flush_dcache_page(page) do { } while (0) 95# define flush_dcache_page(page) do { } while (0)
@@ -100,7 +100,7 @@ extern unsigned long reserved_mem_icache_on;
100 100
101static inline int bfin_addr_dcacheable(unsigned long addr) 101static inline int bfin_addr_dcacheable(unsigned long addr)
102{ 102{
103#ifdef CONFIG_BFIN_DCACHE 103#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
104 if (addr < (_ramend - DMA_UNCACHED_REGION)) 104 if (addr < (_ramend - DMA_UNCACHED_REGION))
105 return 1; 105 return 1;
106#endif 106#endif
@@ -109,7 +109,7 @@ static inline int bfin_addr_dcacheable(unsigned long addr)
109 addr >= _ramend && addr < physical_mem_end) 109 addr >= _ramend && addr < physical_mem_end)
110 return 1; 110 return 1;
111 111
112#ifndef CONFIG_BFIN_L2_NOT_CACHED 112#ifdef CONFIG_BFIN_L2_DCACHEABLE
113 if (addr >= L2_START && addr < L2_START + L2_LENGTH) 113 if (addr >= L2_START && addr < L2_START + L2_LENGTH)
114 return 1; 114 return 1;
115#endif 115#endif