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authorLinus Torvalds <torvalds@linux-foundation.org>2009-06-23 00:49:16 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-06-23 00:49:16 -0400
commitd888a4c76c51092993643f8992bf55b3c28da483 (patch)
tree62cb91e0668c00cd60b4f48aecfbded960ee79c3 /arch/blackfin/include/asm/cache.h
parent687d680985b1438360a9ba470ece8b57cd205c3b (diff)
parent42b86e06c7db365f1947dda9b75317cbb3c9fb5b (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: (27 commits) Blackfin: fix dma-mapping build errors Blackfin: hook up new perf_counter_open syscall Blackfin: drop BF535-specific text for exception 0x2A (unaligned instruction) Blackfin: fix early crash when booting on wrong cpu Blackfin: fix GPTMR0_CLOCKSOURCE dependency on BFIN_GPTIMERS Blackfin: drop unused ISP1760 port1_disable from board resources Blackfin: bf526-ezbrd: handle different SDRAM chips Blackfin: fix typo in TRAS define in mem_init.h header Blackfin: unify memory map headers Blackfin: stick the CPU name into boot image name Blackfin: update defconfigs Blackfin: decouple unrelated cache settings to get exact behavior Blackfin: update I-pipe patch level Blackfin: remove obsolete mcount support from I-pipe code Blackfin: allow CONFIG_TICKSOURCE_GPTMR0 with interrupt pipeline Blackfin: convert interrupt pipeline to irqflags Blackfin: allow people to select BF51x-0.1 silicon rev Blackfin: bf526-ezbrd: set SPI flash resources to SST device Blackfin: fix accidental reset in some boot modes Blackfin: abstract irq14 lowering in do_irq ...
Diffstat (limited to 'arch/blackfin/include/asm/cache.h')
-rw-r--r--arch/blackfin/include/asm/cache.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h
index 2ef669ed9222..477050ad5c53 100644
--- a/arch/blackfin/include/asm/cache.h
+++ b/arch/blackfin/include/asm/cache.h
@@ -35,10 +35,10 @@
35 35
36#if defined(CONFIG_SMP) && \ 36#if defined(CONFIG_SMP) && \
37 !defined(CONFIG_BFIN_CACHE_COHERENT) 37 !defined(CONFIG_BFIN_CACHE_COHERENT)
38# if defined(CONFIG_BFIN_ICACHE) 38# if defined(CONFIG_BFIN_ICACHEABLE) || defined(CONFIG_BFIN_L2_ICACHEABLE)
39# define __ARCH_SYNC_CORE_ICACHE 39# define __ARCH_SYNC_CORE_ICACHE
40# endif 40# endif
41# if defined(CONFIG_BFIN_DCACHE) 41# if defined(CONFIG_BFIN_DCACHEABLE) || defined(CONFIG_BFIN_L2_DCACHEABLE)
42# define __ARCH_SYNC_CORE_DCACHE 42# define __ARCH_SYNC_CORE_DCACHE
43# endif 43# endif
44#ifndef __ASSEMBLY__ 44#ifndef __ASSEMBLY__