aboutsummaryrefslogtreecommitdiffstats
path: root/arch/blackfin/Kconfig
diff options
context:
space:
mode:
authorMichael Hennerich <michael.hennerich@analog.com>2009-01-07 10:14:39 -0500
committerBryan Wu <cooloney@kernel.org>2009-01-07 10:14:39 -0500
commit73feb5c09dcf0d64beb67aa5e1f79e11a388e0ff (patch)
tree09fa1f153a2ca810ad72978736f85359205d64a3 /arch/blackfin/Kconfig
parentc97618d3b7b8ef86a966c4b67b54e5ca15814905 (diff)
Blackfin arch: fix bugs and unify BFIN_KERNEL_CLOCK option
- remove duplicated code and headers - add option allowing arbitrary SDRAM/DDR Timing parameters. - mark automatically calculated timings as EXPERIMENTAL - fix comment header block Related to BUGs: - kernel boot up fails with CONFIG_BFIN_KERNEL_CLOCK item on. - kernel does not boot if re-program clocks [ Mike Frysinger <vapier.adi@gmail.com> - fix comment header - mark do_sync static - document the DMA shutdown - simplify SIC_IWR handling - fix ANOMALY_05000265 handling to work as intended ] Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/Kconfig')
-rw-r--r--arch/blackfin/Kconfig59
1 files changed, 57 insertions, 2 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index f8edfbe5faed..5f09d9349322 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -473,6 +473,61 @@ config MEM_MT46V32M16_5B
473 bool "MT46V32M16_5B" 473 bool "MT46V32M16_5B"
474endchoice 474endchoice
475 475
476choice
477 prompt "DDR/SDRAM Timing"
478 depends on BFIN_KERNEL_CLOCK
479 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
480 help
481 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
482 The calculated SDRAM timing parameters may not be 100%
483 accurate - This option is therefore marked experimental.
484
485config BFIN_KERNEL_CLOCK_MEMINIT_CALC
486 bool "Calculate Timings (EXPERIMENTAL)"
487 depends on EXPERIMENTAL
488
489config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
490 bool "Provide accurate Timings based on target SCLK"
491 help
492 Please consult the Blackfin Hardware Reference Manuals as well
493 as the memory device datasheet.
494 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
495endchoice
496
497menu "Memory Init Control"
498 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
499
500config MEM_DDRCTL0
501 depends on BF54x
502 hex "DDRCTL0"
503 default 0x0
504
505config MEM_DDRCTL1
506 depends on BF54x
507 hex "DDRCTL1"
508 default 0x0
509
510config MEM_DDRCTL2
511 depends on BF54x
512 hex "DDRCTL2"
513 default 0x0
514
515config MEM_EBIU_DDRQUE
516 depends on BF54x
517 hex "DDRQUE"
518 default 0x0
519
520config MEM_SDRRC
521 depends on !BF54x
522 hex "SDRRC"
523 default 0x0
524
525config MEM_SDGCTL
526 depends on !BF54x
527 hex "SDGCTL"
528 default 0x0
529endmenu
530
476config MAX_MEM_SIZE 531config MAX_MEM_SIZE
477 int "Max SDRAM Memory Size in MBytes" 532 int "Max SDRAM Memory Size in MBytes"
478 depends on !MPU 533 depends on !MPU
@@ -1104,13 +1159,13 @@ config BFIN_CPU_FREQ
1104 1159
1105config CPU_VOLTAGE 1160config CPU_VOLTAGE
1106 bool "CPU Voltage scaling" 1161 bool "CPU Voltage scaling"
1107 depends on EXPERIMENTAL 1162 depends on EXPERIMENTAL
1108 depends on CPU_FREQ 1163 depends on CPU_FREQ
1109 default n 1164 default n
1110 help 1165 help
1111 Say Y here if you want CPU voltage scaling according to the CPU frequency. 1166 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1112 This option violates the PLL BYPASS recommendation in the Blackfin Processor 1167 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1113 manuals. There is a theoretical risk that during VDDINT transitions 1168 manuals. There is a theoretical risk that during VDDINT transitions
1114 the PLL may unlock. 1169 the PLL may unlock.
1115 1170
1116endmenu 1171endmenu