aboutsummaryrefslogtreecommitdiffstats
path: root/arch/avr32
diff options
context:
space:
mode:
authorKristoffer Nyborg Gregertsen <kngregertsen@norway.atmel.com>2007-08-17 10:59:57 -0400
committerHaavard Skinnemoen <hskinnemoen@atmel.com>2007-10-11 07:32:49 -0400
commitaf8184718a322ae589efa583aa69ffdae61bf266 (patch)
tree7324ba9e6a14e78b89b703bea7d0594a0ae9ef6e /arch/avr32
parent193fdd1a99db8623697cb18a13dbcaa4eadbb1f2 (diff)
[AVR32] SMC configuration in clock cycles
This patch makes the SMC configuration take timings in clock cycles instead of nanoseconds. A function to calculate timings in clock cycles is added. This patch removes the rounding troubles of the previous SMC configuration method. [hskinnemoen@atmel.com: fix atstk1002/atngw100 flash config] Signed-off-by: Kristoffer Nyborg Gregertsen <gregerts@stud.ntnu.no> Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Diffstat (limited to 'arch/avr32')
-rw-r--r--arch/avr32/boards/atngw100/flash.c5
-rw-r--r--arch/avr32/boards/atstk1000/flash.c5
-rw-r--r--arch/avr32/mach-at32ap/hsmc.c129
3 files changed, 120 insertions, 19 deletions
diff --git a/arch/avr32/boards/atngw100/flash.c b/arch/avr32/boards/atngw100/flash.c
index f9b32a8eab9b..b07ae63aa548 100644
--- a/arch/avr32/boards/atngw100/flash.c
+++ b/arch/avr32/boards/atngw100/flash.c
@@ -15,7 +15,7 @@
15 15
16#include <asm/arch/smc.h> 16#include <asm/arch/smc.h>
17 17
18static struct smc_config flash_config __initdata = { 18static struct smc_timing flash_timing __initdata = {
19 .ncs_read_setup = 0, 19 .ncs_read_setup = 0,
20 .nrd_setup = 40, 20 .nrd_setup = 40,
21 .ncs_write_setup = 0, 21 .ncs_write_setup = 0,
@@ -28,7 +28,9 @@ static struct smc_config flash_config __initdata = {
28 28
29 .read_cycle = 120, 29 .read_cycle = 120,
30 .write_cycle = 120, 30 .write_cycle = 120,
31};
31 32
33static struct smc_config flash_config __initdata = {
32 .bus_width = 2, 34 .bus_width = 2,
33 .nrd_controlled = 1, 35 .nrd_controlled = 1,
34 .nwe_controlled = 1, 36 .nwe_controlled = 1,
@@ -82,6 +84,7 @@ static int __init atngw100_flash_init(void)
82{ 84{
83 int ret; 85 int ret;
84 86
87 smc_set_timing(&flash_config, &flash_timing);
85 ret = smc_set_configuration(0, &flash_config); 88 ret = smc_set_configuration(0, &flash_config);
86 if (ret < 0) { 89 if (ret < 0) {
87 printk(KERN_ERR "atngw100: failed to set NOR flash timing\n"); 90 printk(KERN_ERR "atngw100: failed to set NOR flash timing\n");
diff --git a/arch/avr32/boards/atstk1000/flash.c b/arch/avr32/boards/atstk1000/flash.c
index aac4300cca12..3d0a102ad45e 100644
--- a/arch/avr32/boards/atstk1000/flash.c
+++ b/arch/avr32/boards/atstk1000/flash.c
@@ -15,7 +15,7 @@
15 15
16#include <asm/arch/smc.h> 16#include <asm/arch/smc.h>
17 17
18static struct smc_config flash_config __initdata = { 18static struct smc_timing flash_timing __initdata = {
19 .ncs_read_setup = 0, 19 .ncs_read_setup = 0,
20 .nrd_setup = 40, 20 .nrd_setup = 40,
21 .ncs_write_setup = 0, 21 .ncs_write_setup = 0,
@@ -28,7 +28,9 @@ static struct smc_config flash_config __initdata = {
28 28
29 .read_cycle = 120, 29 .read_cycle = 120,
30 .write_cycle = 120, 30 .write_cycle = 120,
31};
31 32
33static struct smc_config flash_config __initdata = {
32 .bus_width = 2, 34 .bus_width = 2,
33 .nrd_controlled = 1, 35 .nrd_controlled = 1,
34 .nwe_controlled = 1, 36 .nwe_controlled = 1,
@@ -82,6 +84,7 @@ static int __init atstk1000_flash_init(void)
82{ 84{
83 int ret; 85 int ret;
84 86
87 smc_set_timing(&flash_config, &flash_timing);
85 ret = smc_set_configuration(0, &flash_config); 88 ret = smc_set_configuration(0, &flash_config);
86 if (ret < 0) { 89 if (ret < 0) {
87 printk(KERN_ERR "atstk1000: failed to set NOR flash timing\n"); 90 printk(KERN_ERR "atstk1000: failed to set NOR flash timing\n");
diff --git a/arch/avr32/mach-at32ap/hsmc.c b/arch/avr32/mach-at32ap/hsmc.c
index 5e22a750632b..704607fbcc69 100644
--- a/arch/avr32/mach-at32ap/hsmc.c
+++ b/arch/avr32/mach-at32ap/hsmc.c
@@ -29,16 +29,25 @@ struct hsmc {
29 29
30static struct hsmc *hsmc; 30static struct hsmc *hsmc;
31 31
32int smc_set_configuration(int cs, const struct smc_config *config) 32void smc_set_timing(struct smc_config *config,
33 const struct smc_timing *timing)
33{ 34{
35 int recover;
36 int cycle;
37
34 unsigned long mul; 38 unsigned long mul;
35 unsigned long offset;
36 u32 setup, pulse, cycle, mode;
37 39
38 if (!hsmc) 40 /* Reset all SMC timings */
39 return -ENODEV; 41 config->ncs_read_setup = 0;
40 if (cs >= NR_CHIP_SELECTS) 42 config->nrd_setup = 0;
41 return -EINVAL; 43 config->ncs_write_setup = 0;
44 config->nwe_setup = 0;
45 config->ncs_read_pulse = 0;
46 config->nrd_pulse = 0;
47 config->ncs_write_pulse = 0;
48 config->nwe_pulse = 0;
49 config->read_cycle = 0;
50 config->write_cycle = 0;
42 51
43 /* 52 /*
44 * cycles = x / T = x * f 53 * cycles = x / T = x * f
@@ -50,16 +59,102 @@ int smc_set_configuration(int cs, const struct smc_config *config)
50 59
51#define ns2cyc(x) ((((x) * mul) + 65535) >> 16) 60#define ns2cyc(x) ((((x) * mul) + 65535) >> 16)
52 61
53 setup = (HSMC_BF(NWE_SETUP, ns2cyc(config->nwe_setup)) 62 if (timing->ncs_read_setup > 0)
54 | HSMC_BF(NCS_WR_SETUP, ns2cyc(config->ncs_write_setup)) 63 config->ncs_read_setup = ns2cyc(timing->ncs_read_setup);
55 | HSMC_BF(NRD_SETUP, ns2cyc(config->nrd_setup)) 64
56 | HSMC_BF(NCS_RD_SETUP, ns2cyc(config->ncs_read_setup))); 65 if (timing->nrd_setup > 0)
57 pulse = (HSMC_BF(NWE_PULSE, ns2cyc(config->nwe_pulse)) 66 config->nrd_setup = ns2cyc(timing->nrd_setup);
58 | HSMC_BF(NCS_WR_PULSE, ns2cyc(config->ncs_write_pulse)) 67
59 | HSMC_BF(NRD_PULSE, ns2cyc(config->nrd_pulse)) 68 if (timing->ncs_write_setup > 0)
60 | HSMC_BF(NCS_RD_PULSE, ns2cyc(config->ncs_read_pulse))); 69 config->ncs_write_setup = ns2cyc(timing->ncs_write_setup);
61 cycle = (HSMC_BF(NWE_CYCLE, ns2cyc(config->write_cycle)) 70
62 | HSMC_BF(NRD_CYCLE, ns2cyc(config->read_cycle))); 71 if (timing->nwe_setup > 0)
72 config->nwe_setup = ns2cyc(timing->nwe_setup);
73
74 if (timing->ncs_read_pulse > 0)
75 config->ncs_read_pulse = ns2cyc(timing->ncs_read_pulse);
76
77 if (timing->nrd_pulse > 0)
78 config->nrd_pulse = ns2cyc(timing->nrd_pulse);
79
80 if (timing->ncs_write_pulse > 0)
81 config->ncs_write_pulse = ns2cyc(timing->ncs_write_pulse);
82
83 if (timing->nwe_pulse > 0)
84 config->nwe_pulse = ns2cyc(timing->nwe_pulse);
85
86 if (timing->read_cycle > 0)
87 config->read_cycle = ns2cyc(timing->read_cycle);
88
89 if (timing->write_cycle > 0)
90 config->write_cycle = ns2cyc(timing->write_cycle);
91
92 /* Extend read cycle in needed */
93 if (timing->ncs_read_recover > 0)
94 recover = ns2cyc(timing->ncs_read_recover);
95 else
96 recover = 1;
97
98 cycle = config->ncs_read_setup + config->ncs_read_pulse + recover;
99
100 if (config->read_cycle < cycle)
101 config->read_cycle = cycle;
102
103 /* Extend read cycle in needed */
104 if (timing->nrd_recover > 0)
105 recover = ns2cyc(timing->nrd_recover);
106 else
107 recover = 1;
108
109 cycle = config->nrd_setup + config->nrd_pulse + recover;
110
111 if (config->read_cycle < cycle)
112 config->read_cycle = cycle;
113
114 /* Extend write cycle in needed */
115 if (timing->ncs_write_recover > 0)
116 recover = ns2cyc(timing->ncs_write_recover);
117 else
118 recover = 1;
119
120 cycle = config->ncs_write_setup + config->ncs_write_pulse + recover;
121
122 if (config->write_cycle < cycle)
123 config->write_cycle = cycle;
124
125 /* Extend write cycle in needed */
126 if (timing->nwe_recover > 0)
127 recover = ns2cyc(timing->nwe_recover);
128 else
129 recover = 1;
130
131 cycle = config->nwe_setup + config->nwe_pulse + recover;
132
133 if (config->write_cycle < cycle)
134 config->write_cycle = cycle;
135}
136EXPORT_SYMBOL(smc_set_timing);
137
138int smc_set_configuration(int cs, const struct smc_config *config)
139{
140 unsigned long offset;
141 u32 setup, pulse, cycle, mode;
142
143 if (!hsmc)
144 return -ENODEV;
145 if (cs >= NR_CHIP_SELECTS)
146 return -EINVAL;
147
148 setup = (HSMC_BF(NWE_SETUP, config->nwe_setup)
149 | HSMC_BF(NCS_WR_SETUP, config->ncs_write_setup)
150 | HSMC_BF(NRD_SETUP, config->nrd_setup)
151 | HSMC_BF(NCS_RD_SETUP, config->ncs_read_setup));
152 pulse = (HSMC_BF(NWE_PULSE, config->nwe_pulse)
153 | HSMC_BF(NCS_WR_PULSE, config->ncs_write_pulse)
154 | HSMC_BF(NRD_PULSE, config->nrd_pulse)
155 | HSMC_BF(NCS_RD_PULSE, config->ncs_read_pulse));
156 cycle = (HSMC_BF(NWE_CYCLE, config->write_cycle)
157 | HSMC_BF(NRD_CYCLE, config->read_cycle));
63 158
64 switch (config->bus_width) { 159 switch (config->bus_width) {
65 case 1: 160 case 1: