diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-03-25 23:24:05 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-03-25 23:24:05 -0400 |
commit | 0dd61be7ec1be1b6820af978f901b9ae2c244dc6 (patch) | |
tree | 1f49edaa21351034e7d1dff6511424e9a949cf6b /arch/avr32 | |
parent | 8dd90265ac0754da0df47d9c597f25187bb1c947 (diff) | |
parent | ab7798ffcf98b11a9525cf65bacdae3fd58d357f (diff) |
Merge branch 'irq-cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'irq-cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (23 commits)
genirq: Expand generic show_interrupts()
gpio: Fold irq_set_chip/irq_set_handler to irq_set_chip_and_handler
gpio: Cleanup genirq namespace
arm: ep93xx: Add basic interrupt info
arm/gpio: Remove three copies of broken and racy debug code
xtensa: Use generic show_interrupts()
xtensa: Convert genirq namespace
xtensa: Use generic IRQ Kconfig and set GENERIC_HARDIRQS_NO_DEPRECATED
xtensa: Convert s6000 gpio irq_chip to new functions
xtensa: Convert main irq_chip to new functions
um: Use generic show_interrupts()
um: Convert genirq namespace
m32r: Use generic show_interrupts()
m32r: Convert genirq namespace
h8300: Use generic show_interrupts()
h8300: Convert genirq namespace
avr32: Cleanup eic_set_irq_type()
avr32: Use generic show_interrupts()
avr: Cleanup genirq namespace
avr32: Use generic IRQ config, enable GENERIC_HARDIRQS_NO_DEPRECATED
...
Fix up trivial conflict in drivers/gpio/timbgpio.c
Diffstat (limited to 'arch/avr32')
-rw-r--r-- | arch/avr32/Kconfig | 14 | ||||
-rw-r--r-- | arch/avr32/boards/atngw100/mrmt.c | 2 | ||||
-rw-r--r-- | arch/avr32/boards/atngw100/setup.c | 2 | ||||
-rw-r--r-- | arch/avr32/kernel/irq.c | 37 | ||||
-rw-r--r-- | arch/avr32/mach-at32ap/extint.c | 82 | ||||
-rw-r--r-- | arch/avr32/mach-at32ap/intc.c | 14 | ||||
-rw-r--r-- | arch/avr32/mach-at32ap/pio.c | 37 |
7 files changed, 67 insertions, 121 deletions
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig index cd2062fe0f61..49642b59f73d 100644 --- a/arch/avr32/Kconfig +++ b/arch/avr32/Kconfig | |||
@@ -6,6 +6,11 @@ config AVR32 | |||
6 | select HAVE_CLK | 6 | select HAVE_CLK |
7 | select HAVE_OPROFILE | 7 | select HAVE_OPROFILE |
8 | select HAVE_KPROBES | 8 | select HAVE_KPROBES |
9 | select HAVE_GENERIC_HARDIRQS | ||
10 | select GENERIC_IRQ_PROBE | ||
11 | select HARDIRQS_SW_RESEND | ||
12 | select GENERIC_IRQ_SHOW | ||
13 | select GENERIC_HARDIRQS_NO_DEPRECATED | ||
9 | help | 14 | help |
10 | AVR32 is a high-performance 32-bit RISC microprocessor core, | 15 | AVR32 is a high-performance 32-bit RISC microprocessor core, |
11 | designed for cost-sensitive embedded applications, with particular | 16 | designed for cost-sensitive embedded applications, with particular |
@@ -17,9 +22,6 @@ config AVR32 | |||
17 | config GENERIC_GPIO | 22 | config GENERIC_GPIO |
18 | def_bool y | 23 | def_bool y |
19 | 24 | ||
20 | config GENERIC_HARDIRQS | ||
21 | def_bool y | ||
22 | |||
23 | config STACKTRACE_SUPPORT | 25 | config STACKTRACE_SUPPORT |
24 | def_bool y | 26 | def_bool y |
25 | 27 | ||
@@ -29,12 +31,6 @@ config LOCKDEP_SUPPORT | |||
29 | config TRACE_IRQFLAGS_SUPPORT | 31 | config TRACE_IRQFLAGS_SUPPORT |
30 | def_bool y | 32 | def_bool y |
31 | 33 | ||
32 | config HARDIRQS_SW_RESEND | ||
33 | def_bool y | ||
34 | |||
35 | config GENERIC_IRQ_PROBE | ||
36 | def_bool y | ||
37 | |||
38 | config RWSEM_GENERIC_SPINLOCK | 34 | config RWSEM_GENERIC_SPINLOCK |
39 | def_bool y | 35 | def_bool y |
40 | 36 | ||
diff --git a/arch/avr32/boards/atngw100/mrmt.c b/arch/avr32/boards/atngw100/mrmt.c index 7919be311f4a..f91431963452 100644 --- a/arch/avr32/boards/atngw100/mrmt.c +++ b/arch/avr32/boards/atngw100/mrmt.c | |||
@@ -301,7 +301,7 @@ static int __init mrmt1_init(void) | |||
301 | /* Select the Touchscreen interrupt pin mode */ | 301 | /* Select the Touchscreen interrupt pin mode */ |
302 | at32_select_periph( GPIO_PIOB_BASE, 1 << (PB_EXTINT_BASE+TS_IRQ), | 302 | at32_select_periph( GPIO_PIOB_BASE, 1 << (PB_EXTINT_BASE+TS_IRQ), |
303 | GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH); | 303 | GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH); |
304 | set_irq_type( AT32_EXTINT(TS_IRQ), IRQ_TYPE_EDGE_FALLING ); | 304 | irq_set_irq_type(AT32_EXTINT(TS_IRQ), IRQ_TYPE_EDGE_FALLING); |
305 | at32_spi_setup_slaves(0,spi01_board_info,ARRAY_SIZE(spi01_board_info)); | 305 | at32_spi_setup_slaves(0,spi01_board_info,ARRAY_SIZE(spi01_board_info)); |
306 | spi_register_board_info(spi01_board_info,ARRAY_SIZE(spi01_board_info)); | 306 | spi_register_board_info(spi01_board_info,ARRAY_SIZE(spi01_board_info)); |
307 | #endif | 307 | #endif |
diff --git a/arch/avr32/boards/atngw100/setup.c b/arch/avr32/boards/atngw100/setup.c index 659d119ce712..fafed4c38fd2 100644 --- a/arch/avr32/boards/atngw100/setup.c +++ b/arch/avr32/boards/atngw100/setup.c | |||
@@ -322,6 +322,6 @@ static int __init atngw100_arch_init(void) | |||
322 | /* set_irq_type() after the arch_initcall for EIC has run, and | 322 | /* set_irq_type() after the arch_initcall for EIC has run, and |
323 | * before the I2C subsystem could try using this IRQ. | 323 | * before the I2C subsystem could try using this IRQ. |
324 | */ | 324 | */ |
325 | return set_irq_type(AT32_EXTINT(3), IRQ_TYPE_EDGE_FALLING); | 325 | return irq_set_irq_type(AT32_EXTINT(3), IRQ_TYPE_EDGE_FALLING); |
326 | } | 326 | } |
327 | arch_initcall(atngw100_arch_init); | 327 | arch_initcall(atngw100_arch_init); |
diff --git a/arch/avr32/kernel/irq.c b/arch/avr32/kernel/irq.c index 9604f7758f9a..bc3aa18293df 100644 --- a/arch/avr32/kernel/irq.c +++ b/arch/avr32/kernel/irq.c | |||
@@ -26,40 +26,3 @@ void __weak nmi_disable(void) | |||
26 | { | 26 | { |
27 | 27 | ||
28 | } | 28 | } |
29 | |||
30 | #ifdef CONFIG_PROC_FS | ||
31 | int show_interrupts(struct seq_file *p, void *v) | ||
32 | { | ||
33 | int i = *(loff_t *)v, cpu; | ||
34 | struct irqaction *action; | ||
35 | unsigned long flags; | ||
36 | |||
37 | if (i == 0) { | ||
38 | seq_puts(p, " "); | ||
39 | for_each_online_cpu(cpu) | ||
40 | seq_printf(p, "CPU%d ", cpu); | ||
41 | seq_putc(p, '\n'); | ||
42 | } | ||
43 | |||
44 | if (i < NR_IRQS) { | ||
45 | raw_spin_lock_irqsave(&irq_desc[i].lock, flags); | ||
46 | action = irq_desc[i].action; | ||
47 | if (!action) | ||
48 | goto unlock; | ||
49 | |||
50 | seq_printf(p, "%3d: ", i); | ||
51 | for_each_online_cpu(cpu) | ||
52 | seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu)); | ||
53 | seq_printf(p, " %8s", irq_desc[i].chip->name ? : "-"); | ||
54 | seq_printf(p, " %s", action->name); | ||
55 | for (action = action->next; action; action = action->next) | ||
56 | seq_printf(p, ", %s", action->name); | ||
57 | |||
58 | seq_putc(p, '\n'); | ||
59 | unlock: | ||
60 | raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); | ||
61 | } | ||
62 | |||
63 | return 0; | ||
64 | } | ||
65 | #endif | ||
diff --git a/arch/avr32/mach-at32ap/extint.c b/arch/avr32/mach-at32ap/extint.c index e9d12058ffd3..47ba4b9b6db1 100644 --- a/arch/avr32/mach-at32ap/extint.c +++ b/arch/avr32/mach-at32ap/extint.c | |||
@@ -61,45 +61,42 @@ struct eic { | |||
61 | static struct eic *nmi_eic; | 61 | static struct eic *nmi_eic; |
62 | static bool nmi_enabled; | 62 | static bool nmi_enabled; |
63 | 63 | ||
64 | static void eic_ack_irq(unsigned int irq) | 64 | static void eic_ack_irq(struct irq_chip *d) |
65 | { | 65 | { |
66 | struct eic *eic = get_irq_chip_data(irq); | 66 | struct eic *eic = irq_data_get_irq_chip_data(data); |
67 | eic_writel(eic, ICR, 1 << (irq - eic->first_irq)); | 67 | eic_writel(eic, ICR, 1 << (d->irq - eic->first_irq)); |
68 | } | 68 | } |
69 | 69 | ||
70 | static void eic_mask_irq(unsigned int irq) | 70 | static void eic_mask_irq(struct irq_chip *d) |
71 | { | 71 | { |
72 | struct eic *eic = get_irq_chip_data(irq); | 72 | struct eic *eic = irq_data_get_irq_chip_data(data); |
73 | eic_writel(eic, IDR, 1 << (irq - eic->first_irq)); | 73 | eic_writel(eic, IDR, 1 << (d->irq - eic->first_irq)); |
74 | } | 74 | } |
75 | 75 | ||
76 | static void eic_mask_ack_irq(unsigned int irq) | 76 | static void eic_mask_ack_irq(struct irq_chip *d) |
77 | { | 77 | { |
78 | struct eic *eic = get_irq_chip_data(irq); | 78 | struct eic *eic = irq_data_get_irq_chip_data(data); |
79 | eic_writel(eic, ICR, 1 << (irq - eic->first_irq)); | 79 | eic_writel(eic, ICR, 1 << (d->irq - eic->first_irq)); |
80 | eic_writel(eic, IDR, 1 << (irq - eic->first_irq)); | 80 | eic_writel(eic, IDR, 1 << (d->irq - eic->first_irq)); |
81 | } | 81 | } |
82 | 82 | ||
83 | static void eic_unmask_irq(unsigned int irq) | 83 | static void eic_unmask_irq(struct irq_chip *d) |
84 | { | 84 | { |
85 | struct eic *eic = get_irq_chip_data(irq); | 85 | struct eic *eic = irq_data_get_irq_chip_data(data); |
86 | eic_writel(eic, IER, 1 << (irq - eic->first_irq)); | 86 | eic_writel(eic, IER, 1 << (d->irq - eic->first_irq)); |
87 | } | 87 | } |
88 | 88 | ||
89 | static int eic_set_irq_type(unsigned int irq, unsigned int flow_type) | 89 | static int eic_set_irq_type(struct irq_chip *d, unsigned int flow_type) |
90 | { | 90 | { |
91 | struct eic *eic = get_irq_chip_data(irq); | 91 | struct eic *eic = irq_data_get_irq_chip_data(data); |
92 | struct irq_desc *desc; | 92 | unsigned int irq = d->irq; |
93 | unsigned int i = irq - eic->first_irq; | 93 | unsigned int i = irq - eic->first_irq; |
94 | u32 mode, edge, level; | 94 | u32 mode, edge, level; |
95 | int ret = 0; | ||
96 | 95 | ||
97 | flow_type &= IRQ_TYPE_SENSE_MASK; | 96 | flow_type &= IRQ_TYPE_SENSE_MASK; |
98 | if (flow_type == IRQ_TYPE_NONE) | 97 | if (flow_type == IRQ_TYPE_NONE) |
99 | flow_type = IRQ_TYPE_LEVEL_LOW; | 98 | flow_type = IRQ_TYPE_LEVEL_LOW; |
100 | 99 | ||
101 | desc = &irq_desc[irq]; | ||
102 | |||
103 | mode = eic_readl(eic, MODE); | 100 | mode = eic_readl(eic, MODE); |
104 | edge = eic_readl(eic, EDGE); | 101 | edge = eic_readl(eic, EDGE); |
105 | level = eic_readl(eic, LEVEL); | 102 | level = eic_readl(eic, LEVEL); |
@@ -122,39 +119,34 @@ static int eic_set_irq_type(unsigned int irq, unsigned int flow_type) | |||
122 | edge &= ~(1 << i); | 119 | edge &= ~(1 << i); |
123 | break; | 120 | break; |
124 | default: | 121 | default: |
125 | ret = -EINVAL; | 122 | return -EINVAL; |
126 | break; | ||
127 | } | 123 | } |
128 | 124 | ||
129 | if (ret == 0) { | 125 | eic_writel(eic, MODE, mode); |
130 | eic_writel(eic, MODE, mode); | 126 | eic_writel(eic, EDGE, edge); |
131 | eic_writel(eic, EDGE, edge); | 127 | eic_writel(eic, LEVEL, level); |
132 | eic_writel(eic, LEVEL, level); | ||
133 | |||
134 | if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) { | ||
135 | flow_type |= IRQ_LEVEL; | ||
136 | __set_irq_handler_unlocked(irq, handle_level_irq); | ||
137 | } else | ||
138 | __set_irq_handler_unlocked(irq, handle_edge_irq); | ||
139 | desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); | ||
140 | desc->status |= flow_type; | ||
141 | } | ||
142 | 128 | ||
143 | return ret; | 129 | irqd_set_trigger_type(d, flow_type); |
130 | if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | ||
131 | __irq_set_handler_locked(irq, handle_level_irq); | ||
132 | else | ||
133 | __irq_set_handler_locked(irq, handle_edge_irq); | ||
134 | |||
135 | return IRQ_SET_MASK_OK_NOCOPY; | ||
144 | } | 136 | } |
145 | 137 | ||
146 | static struct irq_chip eic_chip = { | 138 | static struct irq_chip eic_chip = { |
147 | .name = "eic", | 139 | .name = "eic", |
148 | .ack = eic_ack_irq, | 140 | .irq_ack = eic_ack_irq, |
149 | .mask = eic_mask_irq, | 141 | .irq_mask = eic_mask_irq, |
150 | .mask_ack = eic_mask_ack_irq, | 142 | .irq_mask_ack = eic_mask_ack_irq, |
151 | .unmask = eic_unmask_irq, | 143 | .irq_unmask = eic_unmask_irq, |
152 | .set_type = eic_set_irq_type, | 144 | .irq_set_type = eic_set_irq_type, |
153 | }; | 145 | }; |
154 | 146 | ||
155 | static void demux_eic_irq(unsigned int irq, struct irq_desc *desc) | 147 | static void demux_eic_irq(unsigned int irq, struct irq_desc *desc) |
156 | { | 148 | { |
157 | struct eic *eic = desc->handler_data; | 149 | struct eic *eic = irq_desc_get_handler_data(desc); |
158 | unsigned long status, pending; | 150 | unsigned long status, pending; |
159 | unsigned int i; | 151 | unsigned int i; |
160 | 152 | ||
@@ -234,13 +226,13 @@ static int __init eic_probe(struct platform_device *pdev) | |||
234 | eic->chip = &eic_chip; | 226 | eic->chip = &eic_chip; |
235 | 227 | ||
236 | for (i = 0; i < nr_of_irqs; i++) { | 228 | for (i = 0; i < nr_of_irqs; i++) { |
237 | set_irq_chip_and_handler(eic->first_irq + i, &eic_chip, | 229 | irq_set_chip_and_handler(eic->first_irq + i, &eic_chip, |
238 | handle_level_irq); | 230 | handle_level_irq); |
239 | set_irq_chip_data(eic->first_irq + i, eic); | 231 | irq_set_chip_data(eic->first_irq + i, eic); |
240 | } | 232 | } |
241 | 233 | ||
242 | set_irq_chained_handler(int_irq, demux_eic_irq); | 234 | irq_set_chained_handler(int_irq, demux_eic_irq); |
243 | set_irq_data(int_irq, eic); | 235 | irq_set_handler_data(int_irq, eic); |
244 | 236 | ||
245 | if (pdev->id == 0) { | 237 | if (pdev->id == 0) { |
246 | nmi_eic = eic; | 238 | nmi_eic = eic; |
diff --git a/arch/avr32/mach-at32ap/intc.c b/arch/avr32/mach-at32ap/intc.c index 994c4545e2b7..21ce35f33aa5 100644 --- a/arch/avr32/mach-at32ap/intc.c +++ b/arch/avr32/mach-at32ap/intc.c | |||
@@ -34,12 +34,12 @@ extern struct platform_device at32_intc0_device; | |||
34 | * TODO: We may be able to implement mask/unmask by setting IxM flags | 34 | * TODO: We may be able to implement mask/unmask by setting IxM flags |
35 | * in the status register. | 35 | * in the status register. |
36 | */ | 36 | */ |
37 | static void intc_mask_irq(unsigned int irq) | 37 | static void intc_mask_irq(struct irq_data *d) |
38 | { | 38 | { |
39 | 39 | ||
40 | } | 40 | } |
41 | 41 | ||
42 | static void intc_unmask_irq(unsigned int irq) | 42 | static void intc_unmask_irq(struct irq_data *d) |
43 | { | 43 | { |
44 | 44 | ||
45 | } | 45 | } |
@@ -47,8 +47,8 @@ static void intc_unmask_irq(unsigned int irq) | |||
47 | static struct intc intc0 = { | 47 | static struct intc intc0 = { |
48 | .chip = { | 48 | .chip = { |
49 | .name = "intc", | 49 | .name = "intc", |
50 | .mask = intc_mask_irq, | 50 | .irq_mask = intc_mask_irq, |
51 | .unmask = intc_unmask_irq, | 51 | .irq_unmask = intc_unmask_irq, |
52 | }, | 52 | }, |
53 | }; | 53 | }; |
54 | 54 | ||
@@ -57,7 +57,6 @@ static struct intc intc0 = { | |||
57 | */ | 57 | */ |
58 | asmlinkage void do_IRQ(int level, struct pt_regs *regs) | 58 | asmlinkage void do_IRQ(int level, struct pt_regs *regs) |
59 | { | 59 | { |
60 | struct irq_desc *desc; | ||
61 | struct pt_regs *old_regs; | 60 | struct pt_regs *old_regs; |
62 | unsigned int irq; | 61 | unsigned int irq; |
63 | unsigned long status_reg; | 62 | unsigned long status_reg; |
@@ -69,8 +68,7 @@ asmlinkage void do_IRQ(int level, struct pt_regs *regs) | |||
69 | irq_enter(); | 68 | irq_enter(); |
70 | 69 | ||
71 | irq = intc_readl(&intc0, INTCAUSE0 - 4 * level); | 70 | irq = intc_readl(&intc0, INTCAUSE0 - 4 * level); |
72 | desc = irq_desc + irq; | 71 | generic_handle_irq(irq); |
73 | desc->handle_irq(irq, desc); | ||
74 | 72 | ||
75 | /* | 73 | /* |
76 | * Clear all interrupt level masks so that we may handle | 74 | * Clear all interrupt level masks so that we may handle |
@@ -128,7 +126,7 @@ void __init init_IRQ(void) | |||
128 | intc_writel(&intc0, INTPR0 + 4 * i, offset); | 126 | intc_writel(&intc0, INTPR0 + 4 * i, offset); |
129 | readback = intc_readl(&intc0, INTPR0 + 4 * i); | 127 | readback = intc_readl(&intc0, INTPR0 + 4 * i); |
130 | if (readback == offset) | 128 | if (readback == offset) |
131 | set_irq_chip_and_handler(i, &intc0.chip, | 129 | irq_set_chip_and_handler(i, &intc0.chip, |
132 | handle_simple_irq); | 130 | handle_simple_irq); |
133 | } | 131 | } |
134 | 132 | ||
diff --git a/arch/avr32/mach-at32ap/pio.c b/arch/avr32/mach-at32ap/pio.c index 09a274c9d0b7..37534103574e 100644 --- a/arch/avr32/mach-at32ap/pio.c +++ b/arch/avr32/mach-at32ap/pio.c | |||
@@ -249,23 +249,23 @@ static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |||
249 | 249 | ||
250 | /* GPIO IRQ support */ | 250 | /* GPIO IRQ support */ |
251 | 251 | ||
252 | static void gpio_irq_mask(unsigned irq) | 252 | static void gpio_irq_mask(struct irq_data *d) |
253 | { | 253 | { |
254 | unsigned gpio = irq_to_gpio(irq); | 254 | unsigned gpio = irq_to_gpio(d->irq); |
255 | struct pio_device *pio = &pio_dev[gpio >> 5]; | 255 | struct pio_device *pio = &pio_dev[gpio >> 5]; |
256 | 256 | ||
257 | pio_writel(pio, IDR, 1 << (gpio & 0x1f)); | 257 | pio_writel(pio, IDR, 1 << (gpio & 0x1f)); |
258 | } | 258 | } |
259 | 259 | ||
260 | static void gpio_irq_unmask(unsigned irq) | 260 | static void gpio_irq_unmask(struct irq_data *d)) |
261 | { | 261 | { |
262 | unsigned gpio = irq_to_gpio(irq); | 262 | unsigned gpio = irq_to_gpio(d->irq); |
263 | struct pio_device *pio = &pio_dev[gpio >> 5]; | 263 | struct pio_device *pio = &pio_dev[gpio >> 5]; |
264 | 264 | ||
265 | pio_writel(pio, IER, 1 << (gpio & 0x1f)); | 265 | pio_writel(pio, IER, 1 << (gpio & 0x1f)); |
266 | } | 266 | } |
267 | 267 | ||
268 | static int gpio_irq_type(unsigned irq, unsigned type) | 268 | static int gpio_irq_type(struct irq_data *d, unsigned type) |
269 | { | 269 | { |
270 | if (type != IRQ_TYPE_EDGE_BOTH && type != IRQ_TYPE_NONE) | 270 | if (type != IRQ_TYPE_EDGE_BOTH && type != IRQ_TYPE_NONE) |
271 | return -EINVAL; | 271 | return -EINVAL; |
@@ -275,20 +275,19 @@ static int gpio_irq_type(unsigned irq, unsigned type) | |||
275 | 275 | ||
276 | static struct irq_chip gpio_irqchip = { | 276 | static struct irq_chip gpio_irqchip = { |
277 | .name = "gpio", | 277 | .name = "gpio", |
278 | .mask = gpio_irq_mask, | 278 | .irq_mask = gpio_irq_mask, |
279 | .unmask = gpio_irq_unmask, | 279 | .irq_unmask = gpio_irq_unmask, |
280 | .set_type = gpio_irq_type, | 280 | .irq_set_type = gpio_irq_type, |
281 | }; | 281 | }; |
282 | 282 | ||
283 | static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) | 283 | static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) |
284 | { | 284 | { |
285 | struct pio_device *pio = get_irq_chip_data(irq); | 285 | struct pio_device *pio = get_irq_desc_chip_data(desc); |
286 | unsigned gpio_irq; | 286 | unsigned gpio_irq; |
287 | 287 | ||
288 | gpio_irq = (unsigned) get_irq_data(irq); | 288 | gpio_irq = (unsigned) irq_get_handler_data(irq); |
289 | for (;;) { | 289 | for (;;) { |
290 | u32 isr; | 290 | u32 isr; |
291 | struct irq_desc *d; | ||
292 | 291 | ||
293 | /* ack pending GPIO interrupts */ | 292 | /* ack pending GPIO interrupts */ |
294 | isr = pio_readl(pio, ISR) & pio_readl(pio, IMR); | 293 | isr = pio_readl(pio, ISR) & pio_readl(pio, IMR); |
@@ -301,9 +300,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |||
301 | isr &= ~(1 << i); | 300 | isr &= ~(1 << i); |
302 | 301 | ||
303 | i += gpio_irq; | 302 | i += gpio_irq; |
304 | d = &irq_desc[i]; | 303 | generic_handle_irq(i); |
305 | |||
306 | d->handle_irq(i, d); | ||
307 | } while (isr); | 304 | } while (isr); |
308 | } | 305 | } |
309 | } | 306 | } |
@@ -313,16 +310,16 @@ gpio_irq_setup(struct pio_device *pio, int irq, int gpio_irq) | |||
313 | { | 310 | { |
314 | unsigned i; | 311 | unsigned i; |
315 | 312 | ||
316 | set_irq_chip_data(irq, pio); | 313 | irq_set_chip_data(irq, pio); |
317 | set_irq_data(irq, (void *) gpio_irq); | 314 | irq_set_handler_data(irq, (void *)gpio_irq); |
318 | 315 | ||
319 | for (i = 0; i < 32; i++, gpio_irq++) { | 316 | for (i = 0; i < 32; i++, gpio_irq++) { |
320 | set_irq_chip_data(gpio_irq, pio); | 317 | irq_set_chip_data(gpio_irq, pio); |
321 | set_irq_chip_and_handler(gpio_irq, &gpio_irqchip, | 318 | irq_set_chip_and_handler(gpio_irq, &gpio_irqchip, |
322 | handle_simple_irq); | 319 | handle_simple_irq); |
323 | } | 320 | } |
324 | 321 | ||
325 | set_irq_chained_handler(irq, gpio_irq_handler); | 322 | irq_set_chained_handler(irq, gpio_irq_handler); |
326 | } | 323 | } |
327 | 324 | ||
328 | /*--------------------------------------------------------------------------*/ | 325 | /*--------------------------------------------------------------------------*/ |