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authorHaavard Skinnemoen <hskinnemoen@atmel.com>2007-06-04 06:58:30 -0400
committerHaavard Skinnemoen <hskinnemoen@atmel.com>2007-07-18 14:45:51 -0400
commit7a5b80590772c29bba1d54d3685622177d6fe39f (patch)
treed643198d28f6578febc2bcc0317a0681f951e62b /arch/avr32/mach-at32ap
parentc6083cd61b5a64a1c73d1634744382f54cb99595 (diff)
[AVR32] Split SM device into PM, RTC, WDT and EIC
Split the SM platform device into separate platform devices for PM, RTC, WDT and EIC. This is more correct according to the documentation and allows us to simplify the code a little. Also turn the EIC driver into a real platform driver. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Acked-by: Hans-Christian Egtvedt <hcegtvedt@atmel.com>
Diffstat (limited to 'arch/avr32/mach-at32ap')
-rw-r--r--arch/avr32/mach-at32ap/at32ap.c31
-rw-r--r--arch/avr32/mach-at32ap/at32ap7000.c213
-rw-r--r--arch/avr32/mach-at32ap/extint.c200
-rw-r--r--arch/avr32/mach-at32ap/pm.h112
-rw-r--r--arch/avr32/mach-at32ap/sm.h242
5 files changed, 372 insertions, 426 deletions
diff --git a/arch/avr32/mach-at32ap/at32ap.c b/arch/avr32/mach-at32ap/at32ap.c
index 90f207e8e96d..7c4987f3287a 100644
--- a/arch/avr32/mach-at32ap/at32ap.c
+++ b/arch/avr32/mach-at32ap/at32ap.c
@@ -11,41 +11,10 @@
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/platform_device.h> 12#include <linux/platform_device.h>
13 13
14#include <asm/io.h>
15
16#include <asm/arch/init.h> 14#include <asm/arch/init.h>
17#include <asm/arch/sm.h>
18
19struct at32_sm system_manager;
20
21static int __init at32_sm_init(void)
22{
23 struct resource *regs;
24 struct at32_sm *sm = &system_manager;
25 int ret = -ENXIO;
26
27 regs = platform_get_resource(&at32_sm_device, IORESOURCE_MEM, 0);
28 if (!regs)
29 goto fail;
30
31 spin_lock_init(&sm->lock);
32 sm->pdev = &at32_sm_device;
33
34 ret = -ENOMEM;
35 sm->regs = ioremap(regs->start, regs->end - regs->start + 1);
36 if (!sm->regs)
37 goto fail;
38
39 return 0;
40
41fail:
42 printk(KERN_ERR "Failed to initialize System Manager: %d\n", ret);
43 return ret;
44}
45 15
46void __init setup_platform(void) 16void __init setup_platform(void)
47{ 17{
48 at32_sm_init();
49 at32_clock_init(); 18 at32_clock_init();
50 at32_portmux_init(); 19 at32_portmux_init();
51} 20}
diff --git a/arch/avr32/mach-at32ap/at32ap7000.c b/arch/avr32/mach-at32ap/at32ap7000.c
index 4dda42d3f6d5..5faa97e5ab16 100644
--- a/arch/avr32/mach-at32ap/at32ap7000.c
+++ b/arch/avr32/mach-at32ap/at32ap7000.c
@@ -17,14 +17,20 @@
17#include <asm/arch/at32ap7000.h> 17#include <asm/arch/at32ap7000.h>
18#include <asm/arch/board.h> 18#include <asm/arch/board.h>
19#include <asm/arch/portmux.h> 19#include <asm/arch/portmux.h>
20#include <asm/arch/sm.h>
21 20
22#include <video/atmel_lcdc.h> 21#include <video/atmel_lcdc.h>
23 22
24#include "clock.h" 23#include "clock.h"
25#include "hmatrix.h" 24#include "hmatrix.h"
26#include "pio.h" 25#include "pio.h"
27#include "sm.h" 26#include "pm.h"
27
28/*
29 * We can reduce the code size a bit by using a constant here. Since
30 * this file is completely chip-specific, it's safe to not use
31 * ioremap. Generic drivers should of course never do this.
32 */
33#define AT32_PM_BASE 0xfff00000
28 34
29#define PBMEM(base) \ 35#define PBMEM(base) \
30 { \ 36 { \
@@ -88,6 +94,8 @@ static struct clk devname##_##_name = { \
88 .index = _index, \ 94 .index = _index, \
89} 95}
90 96
97static DEFINE_SPINLOCK(pm_lock);
98
91unsigned long at32ap7000_osc_rates[3] = { 99unsigned long at32ap7000_osc_rates[3] = {
92 [0] = 32768, 100 [0] = 32768,
93 /* FIXME: these are ATSTK1002-specific */ 101 /* FIXME: these are ATSTK1002-specific */
@@ -104,11 +112,11 @@ static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
104{ 112{
105 unsigned long div, mul, rate; 113 unsigned long div, mul, rate;
106 114
107 if (!(control & SM_BIT(PLLEN))) 115 if (!(control & PM_BIT(PLLEN)))
108 return 0; 116 return 0;
109 117
110 div = SM_BFEXT(PLLDIV, control) + 1; 118 div = PM_BFEXT(PLLDIV, control) + 1;
111 mul = SM_BFEXT(PLLMUL, control) + 1; 119 mul = PM_BFEXT(PLLMUL, control) + 1;
112 120
113 rate = clk->parent->get_rate(clk->parent); 121 rate = clk->parent->get_rate(clk->parent);
114 rate = (rate + div / 2) / div; 122 rate = (rate + div / 2) / div;
@@ -121,7 +129,7 @@ static unsigned long pll0_get_rate(struct clk *clk)
121{ 129{
122 u32 control; 130 u32 control;
123 131
124 control = sm_readl(&system_manager, PM_PLL0); 132 control = pm_readl(PLL0);
125 133
126 return pll_get_rate(clk, control); 134 return pll_get_rate(clk, control);
127} 135}
@@ -130,7 +138,7 @@ static unsigned long pll1_get_rate(struct clk *clk)
130{ 138{
131 u32 control; 139 u32 control;
132 140
133 control = sm_readl(&system_manager, PM_PLL1); 141 control = pm_readl(PLL1);
134 142
135 return pll_get_rate(clk, control); 143 return pll_get_rate(clk, control);
136} 144}
@@ -187,108 +195,104 @@ static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
187 195
188static void cpu_clk_mode(struct clk *clk, int enabled) 196static void cpu_clk_mode(struct clk *clk, int enabled)
189{ 197{
190 struct at32_sm *sm = &system_manager;
191 unsigned long flags; 198 unsigned long flags;
192 u32 mask; 199 u32 mask;
193 200
194 spin_lock_irqsave(&sm->lock, flags); 201 spin_lock_irqsave(&pm_lock, flags);
195 mask = sm_readl(sm, PM_CPU_MASK); 202 mask = pm_readl(CPU_MASK);
196 if (enabled) 203 if (enabled)
197 mask |= 1 << clk->index; 204 mask |= 1 << clk->index;
198 else 205 else
199 mask &= ~(1 << clk->index); 206 mask &= ~(1 << clk->index);
200 sm_writel(sm, PM_CPU_MASK, mask); 207 pm_writel(CPU_MASK, mask);
201 spin_unlock_irqrestore(&sm->lock, flags); 208 spin_unlock_irqrestore(&pm_lock, flags);
202} 209}
203 210
204static unsigned long cpu_clk_get_rate(struct clk *clk) 211static unsigned long cpu_clk_get_rate(struct clk *clk)
205{ 212{
206 unsigned long cksel, shift = 0; 213 unsigned long cksel, shift = 0;
207 214
208 cksel = sm_readl(&system_manager, PM_CKSEL); 215 cksel = pm_readl(CKSEL);
209 if (cksel & SM_BIT(CPUDIV)) 216 if (cksel & PM_BIT(CPUDIV))
210 shift = SM_BFEXT(CPUSEL, cksel) + 1; 217 shift = PM_BFEXT(CPUSEL, cksel) + 1;
211 218
212 return bus_clk_get_rate(clk, shift); 219 return bus_clk_get_rate(clk, shift);
213} 220}
214 221
215static void hsb_clk_mode(struct clk *clk, int enabled) 222static void hsb_clk_mode(struct clk *clk, int enabled)
216{ 223{
217 struct at32_sm *sm = &system_manager;
218 unsigned long flags; 224 unsigned long flags;
219 u32 mask; 225 u32 mask;
220 226
221 spin_lock_irqsave(&sm->lock, flags); 227 spin_lock_irqsave(&pm_lock, flags);
222 mask = sm_readl(sm, PM_HSB_MASK); 228 mask = pm_readl(HSB_MASK);
223 if (enabled) 229 if (enabled)
224 mask |= 1 << clk->index; 230 mask |= 1 << clk->index;
225 else 231 else
226 mask &= ~(1 << clk->index); 232 mask &= ~(1 << clk->index);
227 sm_writel(sm, PM_HSB_MASK, mask); 233 pm_writel(HSB_MASK, mask);
228 spin_unlock_irqrestore(&sm->lock, flags); 234 spin_unlock_irqrestore(&pm_lock, flags);
229} 235}
230 236
231static unsigned long hsb_clk_get_rate(struct clk *clk) 237static unsigned long hsb_clk_get_rate(struct clk *clk)
232{ 238{
233 unsigned long cksel, shift = 0; 239 unsigned long cksel, shift = 0;
234 240
235 cksel = sm_readl(&system_manager, PM_CKSEL); 241 cksel = pm_readl(CKSEL);
236 if (cksel & SM_BIT(HSBDIV)) 242 if (cksel & PM_BIT(HSBDIV))
237 shift = SM_BFEXT(HSBSEL, cksel) + 1; 243 shift = PM_BFEXT(HSBSEL, cksel) + 1;
238 244
239 return bus_clk_get_rate(clk, shift); 245 return bus_clk_get_rate(clk, shift);
240} 246}
241 247
242static void pba_clk_mode(struct clk *clk, int enabled) 248static void pba_clk_mode(struct clk *clk, int enabled)
243{ 249{
244 struct at32_sm *sm = &system_manager;
245 unsigned long flags; 250 unsigned long flags;
246 u32 mask; 251 u32 mask;
247 252
248 spin_lock_irqsave(&sm->lock, flags); 253 spin_lock_irqsave(&pm_lock, flags);
249 mask = sm_readl(sm, PM_PBA_MASK); 254 mask = pm_readl(PBA_MASK);
250 if (enabled) 255 if (enabled)
251 mask |= 1 << clk->index; 256 mask |= 1 << clk->index;
252 else 257 else
253 mask &= ~(1 << clk->index); 258 mask &= ~(1 << clk->index);
254 sm_writel(sm, PM_PBA_MASK, mask); 259 pm_writel(PBA_MASK, mask);
255 spin_unlock_irqrestore(&sm->lock, flags); 260 spin_unlock_irqrestore(&pm_lock, flags);
256} 261}
257 262
258static unsigned long pba_clk_get_rate(struct clk *clk) 263static unsigned long pba_clk_get_rate(struct clk *clk)
259{ 264{
260 unsigned long cksel, shift = 0; 265 unsigned long cksel, shift = 0;
261 266
262 cksel = sm_readl(&system_manager, PM_CKSEL); 267 cksel = pm_readl(CKSEL);
263 if (cksel & SM_BIT(PBADIV)) 268 if (cksel & PM_BIT(PBADIV))
264 shift = SM_BFEXT(PBASEL, cksel) + 1; 269 shift = PM_BFEXT(PBASEL, cksel) + 1;
265 270
266 return bus_clk_get_rate(clk, shift); 271 return bus_clk_get_rate(clk, shift);
267} 272}
268 273
269static void pbb_clk_mode(struct clk *clk, int enabled) 274static void pbb_clk_mode(struct clk *clk, int enabled)
270{ 275{
271 struct at32_sm *sm = &system_manager;
272 unsigned long flags; 276 unsigned long flags;
273 u32 mask; 277 u32 mask;
274 278
275 spin_lock_irqsave(&sm->lock, flags); 279 spin_lock_irqsave(&pm_lock, flags);
276 mask = sm_readl(sm, PM_PBB_MASK); 280 mask = pm_readl(PBB_MASK);
277 if (enabled) 281 if (enabled)
278 mask |= 1 << clk->index; 282 mask |= 1 << clk->index;
279 else 283 else
280 mask &= ~(1 << clk->index); 284 mask &= ~(1 << clk->index);
281 sm_writel(sm, PM_PBB_MASK, mask); 285 pm_writel(PBB_MASK, mask);
282 spin_unlock_irqrestore(&sm->lock, flags); 286 spin_unlock_irqrestore(&pm_lock, flags);
283} 287}
284 288
285static unsigned long pbb_clk_get_rate(struct clk *clk) 289static unsigned long pbb_clk_get_rate(struct clk *clk)
286{ 290{
287 unsigned long cksel, shift = 0; 291 unsigned long cksel, shift = 0;
288 292
289 cksel = sm_readl(&system_manager, PM_CKSEL); 293 cksel = pm_readl(CKSEL);
290 if (cksel & SM_BIT(PBBDIV)) 294 if (cksel & PM_BIT(PBBDIV))
291 shift = SM_BFEXT(PBBSEL, cksel) + 1; 295 shift = PM_BFEXT(PBBSEL, cksel) + 1;
292 296
293 return bus_clk_get_rate(clk, shift); 297 return bus_clk_get_rate(clk, shift);
294} 298}
@@ -327,12 +331,12 @@ static void genclk_mode(struct clk *clk, int enabled)
327{ 331{
328 u32 control; 332 u32 control;
329 333
330 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index); 334 control = pm_readl(GCCTRL(clk->index));
331 if (enabled) 335 if (enabled)
332 control |= SM_BIT(CEN); 336 control |= PM_BIT(CEN);
333 else 337 else
334 control &= ~SM_BIT(CEN); 338 control &= ~PM_BIT(CEN);
335 sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control); 339 pm_writel(GCCTRL(clk->index), control);
336} 340}
337 341
338static unsigned long genclk_get_rate(struct clk *clk) 342static unsigned long genclk_get_rate(struct clk *clk)
@@ -340,9 +344,9 @@ static unsigned long genclk_get_rate(struct clk *clk)
340 u32 control; 344 u32 control;
341 unsigned long div = 1; 345 unsigned long div = 1;
342 346
343 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index); 347 control = pm_readl(GCCTRL(clk->index));
344 if (control & SM_BIT(DIVEN)) 348 if (control & PM_BIT(DIVEN))
345 div = 2 * (SM_BFEXT(DIV, control) + 1); 349 div = 2 * (PM_BFEXT(DIV, control) + 1);
346 350
347 return clk->parent->get_rate(clk->parent) / div; 351 return clk->parent->get_rate(clk->parent) / div;
348} 352}
@@ -353,23 +357,22 @@ static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
353 unsigned long parent_rate, actual_rate, div; 357 unsigned long parent_rate, actual_rate, div;
354 358
355 parent_rate = clk->parent->get_rate(clk->parent); 359 parent_rate = clk->parent->get_rate(clk->parent);
356 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index); 360 control = pm_readl(GCCTRL(clk->index));
357 361
358 if (rate > 3 * parent_rate / 4) { 362 if (rate > 3 * parent_rate / 4) {
359 actual_rate = parent_rate; 363 actual_rate = parent_rate;
360 control &= ~SM_BIT(DIVEN); 364 control &= ~PM_BIT(DIVEN);
361 } else { 365 } else {
362 div = (parent_rate + rate) / (2 * rate) - 1; 366 div = (parent_rate + rate) / (2 * rate) - 1;
363 control = SM_BFINS(DIV, div, control) | SM_BIT(DIVEN); 367 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
364 actual_rate = parent_rate / (2 * (div + 1)); 368 actual_rate = parent_rate / (2 * (div + 1));
365 } 369 }
366 370
367 printk("clk %s: new rate %lu (actual rate %lu)\n", 371 dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
368 clk->name, rate, actual_rate); 372 clk->name, rate, actual_rate);
369 373
370 if (apply) 374 if (apply)
371 sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, 375 pm_writel(GCCTRL(clk->index), control);
372 control);
373 376
374 return actual_rate; 377 return actual_rate;
375} 378}
@@ -378,24 +381,24 @@ int genclk_set_parent(struct clk *clk, struct clk *parent)
378{ 381{
379 u32 control; 382 u32 control;
380 383
381 printk("clk %s: new parent %s (was %s)\n", 384 dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
382 clk->name, parent->name, clk->parent->name); 385 clk->name, parent->name, clk->parent->name);
383 386
384 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index); 387 control = pm_readl(GCCTRL(clk->index));
385 388
386 if (parent == &osc1 || parent == &pll1) 389 if (parent == &osc1 || parent == &pll1)
387 control |= SM_BIT(OSCSEL); 390 control |= PM_BIT(OSCSEL);
388 else if (parent == &osc0 || parent == &pll0) 391 else if (parent == &osc0 || parent == &pll0)
389 control &= ~SM_BIT(OSCSEL); 392 control &= ~PM_BIT(OSCSEL);
390 else 393 else
391 return -EINVAL; 394 return -EINVAL;
392 395
393 if (parent == &pll0 || parent == &pll1) 396 if (parent == &pll0 || parent == &pll1)
394 control |= SM_BIT(PLLSEL); 397 control |= PM_BIT(PLLSEL);
395 else 398 else
396 control &= ~SM_BIT(PLLSEL); 399 control &= ~PM_BIT(PLLSEL);
397 400
398 sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control); 401 pm_writel(GCCTRL(clk->index), control);
399 clk->parent = parent; 402 clk->parent = parent;
400 403
401 return 0; 404 return 0;
@@ -408,11 +411,11 @@ static void __init genclk_init_parent(struct clk *clk)
408 411
409 BUG_ON(clk->index > 7); 412 BUG_ON(clk->index > 7);
410 413
411 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index); 414 control = pm_readl(GCCTRL(clk->index));
412 if (control & SM_BIT(OSCSEL)) 415 if (control & PM_BIT(OSCSEL))
413 parent = (control & SM_BIT(PLLSEL)) ? &pll1 : &osc1; 416 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
414 else 417 else
415 parent = (control & SM_BIT(PLLSEL)) ? &pll0 : &osc0; 418 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
416 419
417 clk->parent = parent; 420 clk->parent = parent;
418} 421}
@@ -420,21 +423,53 @@ static void __init genclk_init_parent(struct clk *clk)
420/* -------------------------------------------------------------------- 423/* --------------------------------------------------------------------
421 * System peripherals 424 * System peripherals
422 * -------------------------------------------------------------------- */ 425 * -------------------------------------------------------------------- */
423static struct resource sm_resource[] = { 426static struct resource at32_pm0_resource[] = {
424 PBMEM(0xfff00000), 427 {
425 NAMED_IRQ(19, "eim"), 428 .start = 0xfff00000,
426 NAMED_IRQ(20, "pm"), 429 .end = 0xfff0007f,
427 NAMED_IRQ(21, "rtc"), 430 .flags = IORESOURCE_MEM,
431 },
432 IRQ(20),
428}; 433};
429struct platform_device at32_sm_device = { 434
430 .name = "sm", 435static struct resource at32ap700x_rtc0_resource[] = {
431 .id = 0, 436 {
432 .resource = sm_resource, 437 .start = 0xfff00080,
433 .num_resources = ARRAY_SIZE(sm_resource), 438 .end = 0xfff000af,
439 .flags = IORESOURCE_MEM,
440 },
441 IRQ(21),
434}; 442};
435static struct clk at32_sm_pclk = { 443
444static struct resource at32_wdt0_resource[] = {
445 {
446 .start = 0xfff000b0,
447 .end = 0xfff000bf,
448 .flags = IORESOURCE_MEM,
449 },
450};
451
452static struct resource at32_eic0_resource[] = {
453 {
454 .start = 0xfff00100,
455 .end = 0xfff0013f,
456 .flags = IORESOURCE_MEM,
457 },
458 IRQ(19),
459};
460
461DEFINE_DEV(at32_pm, 0);
462DEFINE_DEV(at32ap700x_rtc, 0);
463DEFINE_DEV(at32_wdt, 0);
464DEFINE_DEV(at32_eic, 0);
465
466/*
467 * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
468 * is always running.
469 */
470static struct clk at32_pm_pclk = {
436 .name = "pclk", 471 .name = "pclk",
437 .dev = &at32_sm_device.dev, 472 .dev = &at32_pm0_device.dev,
438 .parent = &pbb_clk, 473 .parent = &pbb_clk,
439 .mode = pbb_clk_mode, 474 .mode = pbb_clk_mode,
440 .get_rate = pbb_clk_get_rate, 475 .get_rate = pbb_clk_get_rate,
@@ -583,10 +618,11 @@ DEV_CLK(mck, pio4, pba, 14);
583 618
584void __init at32_add_system_devices(void) 619void __init at32_add_system_devices(void)
585{ 620{
586 system_manager.eim_first_irq = EIM_IRQ_BASE; 621 platform_device_register(&at32_pm0_device);
587
588 platform_device_register(&at32_sm_device);
589 platform_device_register(&at32_intc0_device); 622 platform_device_register(&at32_intc0_device);
623 platform_device_register(&at32ap700x_rtc0_device);
624 platform_device_register(&at32_wdt0_device);
625 platform_device_register(&at32_eic0_device);
590 platform_device_register(&smc0_device); 626 platform_device_register(&smc0_device);
591 platform_device_register(&pdc_device); 627 platform_device_register(&pdc_device);
592 628
@@ -1066,7 +1102,7 @@ struct clk *at32_clock_list[] = {
1066 &hsb_clk, 1102 &hsb_clk,
1067 &pba_clk, 1103 &pba_clk,
1068 &pbb_clk, 1104 &pbb_clk,
1069 &at32_sm_pclk, 1105 &at32_pm_pclk,
1070 &at32_intc0_pclk, 1106 &at32_intc0_pclk,
1071 &hmatrix_clk, 1107 &hmatrix_clk,
1072 &ebi_clk, 1108 &ebi_clk,
@@ -1113,18 +1149,17 @@ void __init at32_portmux_init(void)
1113 1149
1114void __init at32_clock_init(void) 1150void __init at32_clock_init(void)
1115{ 1151{
1116 struct at32_sm *sm = &system_manager;
1117 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0; 1152 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
1118 int i; 1153 int i;
1119 1154
1120 if (sm_readl(sm, PM_MCCTRL) & SM_BIT(PLLSEL)) 1155 if (pm_readl(MCCTRL) & PM_BIT(PLLSEL))
1121 main_clock = &pll0; 1156 main_clock = &pll0;
1122 else 1157 else
1123 main_clock = &osc0; 1158 main_clock = &osc0;
1124 1159
1125 if (sm_readl(sm, PM_PLL0) & SM_BIT(PLLOSC)) 1160 if (pm_readl(PLL0) & PM_BIT(PLLOSC))
1126 pll0.parent = &osc1; 1161 pll0.parent = &osc1;
1127 if (sm_readl(sm, PM_PLL1) & SM_BIT(PLLOSC)) 1162 if (pm_readl(PLL1) & PM_BIT(PLLOSC))
1128 pll1.parent = &osc1; 1163 pll1.parent = &osc1;
1129 1164
1130 genclk_init_parent(&gclk0); 1165 genclk_init_parent(&gclk0);
@@ -1157,8 +1192,8 @@ void __init at32_clock_init(void)
1157 pbb_mask |= 1 << clk->index; 1192 pbb_mask |= 1 << clk->index;
1158 } 1193 }
1159 1194
1160 sm_writel(sm, PM_CPU_MASK, cpu_mask); 1195 pm_writel(CPU_MASK, cpu_mask);
1161 sm_writel(sm, PM_HSB_MASK, hsb_mask); 1196 pm_writel(HSB_MASK, hsb_mask);
1162 sm_writel(sm, PM_PBA_MASK, pba_mask); 1197 pm_writel(PBA_MASK, pba_mask);
1163 sm_writel(sm, PM_PBB_MASK, pbb_mask); 1198 pm_writel(PBB_MASK, pbb_mask);
1164} 1199}
diff --git a/arch/avr32/mach-at32ap/extint.c b/arch/avr32/mach-at32ap/extint.c
index 4a60eccfebd2..8acd01090031 100644
--- a/arch/avr32/mach-at32ap/extint.c
+++ b/arch/avr32/mach-at32ap/extint.c
@@ -17,42 +17,83 @@
17 17
18#include <asm/io.h> 18#include <asm/io.h>
19 19
20#include <asm/arch/sm.h> 20/* EIC register offsets */
21 21#define EIC_IER 0x0000
22#include "sm.h" 22#define EIC_IDR 0x0004
23#define EIC_IMR 0x0008
24#define EIC_ISR 0x000c
25#define EIC_ICR 0x0010
26#define EIC_MODE 0x0014
27#define EIC_EDGE 0x0018
28#define EIC_LEVEL 0x001c
29#define EIC_TEST 0x0020
30#define EIC_NMIC 0x0024
31
32/* Bitfields in TEST */
33#define EIC_TESTEN_OFFSET 31
34#define EIC_TESTEN_SIZE 1
35
36/* Bitfields in NMIC */
37#define EIC_EN_OFFSET 0
38#define EIC_EN_SIZE 1
39
40/* Bit manipulation macros */
41#define EIC_BIT(name) \
42 (1 << EIC_##name##_OFFSET)
43#define EIC_BF(name,value) \
44 (((value) & ((1 << EIC_##name##_SIZE) - 1)) \
45 << EIC_##name##_OFFSET)
46#define EIC_BFEXT(name,value) \
47 (((value) >> EIC_##name##_OFFSET) \
48 & ((1 << EIC_##name##_SIZE) - 1))
49#define EIC_BFINS(name,value,old) \
50 (((old) & ~(((1 << EIC_##name##_SIZE) - 1) \
51 << EIC_##name##_OFFSET)) \
52 | EIC_BF(name,value))
53
54/* Register access macros */
55#define eic_readl(port,reg) \
56 __raw_readl((port)->regs + EIC_##reg)
57#define eic_writel(port,reg,value) \
58 __raw_writel((value), (port)->regs + EIC_##reg)
59
60struct eic {
61 void __iomem *regs;
62 struct irq_chip *chip;
63 unsigned int first_irq;
64};
23 65
24static void eim_ack_irq(unsigned int irq) 66static void eic_ack_irq(unsigned int irq)
25{ 67{
26 struct at32_sm *sm = get_irq_chip_data(irq); 68 struct eic *eic = get_irq_chip_data(irq);
27 sm_writel(sm, EIM_ICR, 1 << (irq - sm->eim_first_irq)); 69 eic_writel(eic, ICR, 1 << (irq - eic->first_irq));
28} 70}
29 71
30static void eim_mask_irq(unsigned int irq) 72static void eic_mask_irq(unsigned int irq)
31{ 73{
32 struct at32_sm *sm = get_irq_chip_data(irq); 74 struct eic *eic = get_irq_chip_data(irq);
33 sm_writel(sm, EIM_IDR, 1 << (irq - sm->eim_first_irq)); 75 eic_writel(eic, IDR, 1 << (irq - eic->first_irq));
34} 76}
35 77
36static void eim_mask_ack_irq(unsigned int irq) 78static void eic_mask_ack_irq(unsigned int irq)
37{ 79{
38 struct at32_sm *sm = get_irq_chip_data(irq); 80 struct eic *eic = get_irq_chip_data(irq);
39 sm_writel(sm, EIM_ICR, 1 << (irq - sm->eim_first_irq)); 81 eic_writel(eic, ICR, 1 << (irq - eic->first_irq));
40 sm_writel(sm, EIM_IDR, 1 << (irq - sm->eim_first_irq)); 82 eic_writel(eic, IDR, 1 << (irq - eic->first_irq));
41} 83}
42 84
43static void eim_unmask_irq(unsigned int irq) 85static void eic_unmask_irq(unsigned int irq)
44{ 86{
45 struct at32_sm *sm = get_irq_chip_data(irq); 87 struct eic *eic = get_irq_chip_data(irq);
46 sm_writel(sm, EIM_IER, 1 << (irq - sm->eim_first_irq)); 88 eic_writel(eic, IER, 1 << (irq - eic->first_irq));
47} 89}
48 90
49static int eim_set_irq_type(unsigned int irq, unsigned int flow_type) 91static int eic_set_irq_type(unsigned int irq, unsigned int flow_type)
50{ 92{
51 struct at32_sm *sm = get_irq_chip_data(irq); 93 struct eic *eic = get_irq_chip_data(irq);
52 struct irq_desc *desc; 94 struct irq_desc *desc;
53 unsigned int i = irq - sm->eim_first_irq; 95 unsigned int i = irq - eic->first_irq;
54 u32 mode, edge, level; 96 u32 mode, edge, level;
55 unsigned long flags;
56 int ret = 0; 97 int ret = 0;
57 98
58 flow_type &= IRQ_TYPE_SENSE_MASK; 99 flow_type &= IRQ_TYPE_SENSE_MASK;
@@ -60,11 +101,10 @@ static int eim_set_irq_type(unsigned int irq, unsigned int flow_type)
60 flow_type = IRQ_TYPE_LEVEL_LOW; 101 flow_type = IRQ_TYPE_LEVEL_LOW;
61 102
62 desc = &irq_desc[irq]; 103 desc = &irq_desc[irq];
63 spin_lock_irqsave(&sm->lock, flags);
64 104
65 mode = sm_readl(sm, EIM_MODE); 105 mode = eic_readl(eic, MODE);
66 edge = sm_readl(sm, EIM_EDGE); 106 edge = eic_readl(eic, EDGE);
67 level = sm_readl(sm, EIM_LEVEL); 107 level = eic_readl(eic, LEVEL);
68 108
69 switch (flow_type) { 109 switch (flow_type) {
70 case IRQ_TYPE_LEVEL_LOW: 110 case IRQ_TYPE_LEVEL_LOW:
@@ -89,9 +129,9 @@ static int eim_set_irq_type(unsigned int irq, unsigned int flow_type)
89 } 129 }
90 130
91 if (ret == 0) { 131 if (ret == 0) {
92 sm_writel(sm, EIM_MODE, mode); 132 eic_writel(eic, MODE, mode);
93 sm_writel(sm, EIM_EDGE, edge); 133 eic_writel(eic, EDGE, edge);
94 sm_writel(sm, EIM_LEVEL, level); 134 eic_writel(eic, LEVEL, level);
95 135
96 if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 136 if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
97 flow_type |= IRQ_LEVEL; 137 flow_type |= IRQ_LEVEL;
@@ -99,35 +139,33 @@ static int eim_set_irq_type(unsigned int irq, unsigned int flow_type)
99 desc->status |= flow_type; 139 desc->status |= flow_type;
100 } 140 }
101 141
102 spin_unlock_irqrestore(&sm->lock, flags);
103
104 return ret; 142 return ret;
105} 143}
106 144
107struct irq_chip eim_chip = { 145struct irq_chip eic_chip = {
108 .name = "eim", 146 .name = "eic",
109 .ack = eim_ack_irq, 147 .ack = eic_ack_irq,
110 .mask = eim_mask_irq, 148 .mask = eic_mask_irq,
111 .mask_ack = eim_mask_ack_irq, 149 .mask_ack = eic_mask_ack_irq,
112 .unmask = eim_unmask_irq, 150 .unmask = eic_unmask_irq,
113 .set_type = eim_set_irq_type, 151 .set_type = eic_set_irq_type,
114}; 152};
115 153
116static void demux_eim_irq(unsigned int irq, struct irq_desc *desc) 154static void demux_eic_irq(unsigned int irq, struct irq_desc *desc)
117{ 155{
118 struct at32_sm *sm = desc->handler_data; 156 struct eic *eic = desc->handler_data;
119 struct irq_desc *ext_desc; 157 struct irq_desc *ext_desc;
120 unsigned long status, pending; 158 unsigned long status, pending;
121 unsigned int i, ext_irq; 159 unsigned int i, ext_irq;
122 160
123 status = sm_readl(sm, EIM_ISR); 161 status = eic_readl(eic, ISR);
124 pending = status & sm_readl(sm, EIM_IMR); 162 pending = status & eic_readl(eic, IMR);
125 163
126 while (pending) { 164 while (pending) {
127 i = fls(pending) - 1; 165 i = fls(pending) - 1;
128 pending &= ~(1 << i); 166 pending &= ~(1 << i);
129 167
130 ext_irq = i + sm->eim_first_irq; 168 ext_irq = i + eic->first_irq;
131 ext_desc = irq_desc + ext_irq; 169 ext_desc = irq_desc + ext_irq;
132 if (ext_desc->status & IRQ_LEVEL) 170 if (ext_desc->status & IRQ_LEVEL)
133 handle_level_irq(ext_irq, ext_desc); 171 handle_level_irq(ext_irq, ext_desc);
@@ -136,51 +174,85 @@ static void demux_eim_irq(unsigned int irq, struct irq_desc *desc)
136 } 174 }
137} 175}
138 176
139static int __init eim_init(void) 177static int __init eic_probe(struct platform_device *pdev)
140{ 178{
141 struct at32_sm *sm = &system_manager; 179 struct eic *eic;
180 struct resource *regs;
142 unsigned int i; 181 unsigned int i;
143 unsigned int nr_irqs; 182 unsigned int nr_irqs;
144 unsigned int int_irq; 183 unsigned int int_irq;
184 int ret;
145 u32 pattern; 185 u32 pattern;
146 186
147 /* 187 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
148 * The EIM is really the same module as SM, so register 188 int_irq = platform_get_irq(pdev, 0);
149 * mapping, etc. has been taken care of already. 189 if (!regs || !int_irq) {
150 */ 190 dev_dbg(&pdev->dev, "missing regs and/or irq resource\n");
191 return -ENXIO;
192 }
193
194 ret = -ENOMEM;
195 eic = kzalloc(sizeof(struct eic), GFP_KERNEL);
196 if (!eic) {
197 dev_dbg(&pdev->dev, "no memory for eic structure\n");
198 goto err_kzalloc;
199 }
200
201 eic->first_irq = EIM_IRQ_BASE + 32 * pdev->id;
202 eic->regs = ioremap(regs->start, regs->end - regs->start + 1);
203 if (!eic->regs) {
204 dev_dbg(&pdev->dev, "failed to map regs\n");
205 goto err_ioremap;
206 }
151 207
152 /* 208 /*
153 * Find out how many interrupt lines that are actually 209 * Find out how many interrupt lines that are actually
154 * implemented in hardware. 210 * implemented in hardware.
155 */ 211 */
156 sm_writel(sm, EIM_IDR, ~0UL); 212 eic_writel(eic, IDR, ~0UL);
157 sm_writel(sm, EIM_MODE, ~0UL); 213 eic_writel(eic, MODE, ~0UL);
158 pattern = sm_readl(sm, EIM_MODE); 214 pattern = eic_readl(eic, MODE);
159 nr_irqs = fls(pattern); 215 nr_irqs = fls(pattern);
160 216
161 /* Trigger on falling edge unless overridden by driver */ 217 /* Trigger on falling edge unless overridden by driver */
162 sm_writel(sm, EIM_MODE, 0UL); 218 eic_writel(eic, MODE, 0UL);
163 sm_writel(sm, EIM_EDGE, 0UL); 219 eic_writel(eic, EDGE, 0UL);
164 220
165 sm->eim_chip = &eim_chip; 221 eic->chip = &eic_chip;
166 222
167 for (i = 0; i < nr_irqs; i++) { 223 for (i = 0; i < nr_irqs; i++) {
168 /* NOTE the handler we set here is ignored by the demux */ 224 /* NOTE the handler we set here is ignored by the demux */
169 set_irq_chip_and_handler(sm->eim_first_irq + i, &eim_chip, 225 set_irq_chip_and_handler(eic->first_irq + i, &eic_chip,
170 handle_level_irq); 226 handle_level_irq);
171 set_irq_chip_data(sm->eim_first_irq + i, sm); 227 set_irq_chip_data(eic->first_irq + i, eic);
172 } 228 }
173 229
174 int_irq = platform_get_irq_byname(sm->pdev, "eim"); 230 set_irq_chained_handler(int_irq, demux_eic_irq);
175 231 set_irq_data(int_irq, eic);
176 set_irq_chained_handler(int_irq, demux_eim_irq);
177 set_irq_data(int_irq, sm);
178 232
179 printk("EIM: External Interrupt Module at 0x%p, IRQ %u\n", 233 dev_info(&pdev->dev,
180 sm->regs, int_irq); 234 "External Interrupt Controller at 0x%p, IRQ %u\n",
181 printk("EIM: Handling %u external IRQs, starting with IRQ %u\n", 235 eic->regs, int_irq);
182 nr_irqs, sm->eim_first_irq); 236 dev_info(&pdev->dev,
237 "Handling %u external IRQs, starting with IRQ %u\n",
238 nr_irqs, eic->first_irq);
183 239
184 return 0; 240 return 0;
241
242err_ioremap:
243 kfree(eic);
244err_kzalloc:
245 return ret;
246}
247
248static struct platform_driver eic_driver = {
249 .driver = {
250 .name = "at32_eic",
251 },
252};
253
254static int __init eic_init(void)
255{
256 return platform_driver_probe(&eic_driver, eic_probe);
185} 257}
186arch_initcall(eim_init); 258arch_initcall(eic_init);
diff --git a/arch/avr32/mach-at32ap/pm.h b/arch/avr32/mach-at32ap/pm.h
new file mode 100644
index 000000000000..a1f8aced0a8c
--- /dev/null
+++ b/arch/avr32/mach-at32ap/pm.h
@@ -0,0 +1,112 @@
1/*
2 * Register definitions for the Power Manager (PM)
3 */
4#ifndef __ARCH_AVR32_MACH_AT32AP_PM_H__
5#define __ARCH_AVR32_MACH_AT32AP_PM_H__
6
7/* PM register offsets */
8#define PM_MCCTRL 0x0000
9#define PM_CKSEL 0x0004
10#define PM_CPU_MASK 0x0008
11#define PM_HSB_MASK 0x000c
12#define PM_PBA_MASK 0x0010
13#define PM_PBB_MASK 0x0014
14#define PM_PLL0 0x0020
15#define PM_PLL1 0x0024
16#define PM_IER 0x0040
17#define PM_IDR 0x0044
18#define PM_IMR 0x0048
19#define PM_ISR 0x004c
20#define PM_ICR 0x0050
21#define PM_GCCTRL(x) (0x0060 + 4 * (x))
22#define PM_RCAUSE 0x00c0
23
24/* Bitfields in CKSEL */
25#define PM_CPUSEL_OFFSET 0
26#define PM_CPUSEL_SIZE 3
27#define PM_CPUDIV_OFFSET 7
28#define PM_CPUDIV_SIZE 1
29#define PM_HSBSEL_OFFSET 8
30#define PM_HSBSEL_SIZE 3
31#define PM_HSBDIV_OFFSET 15
32#define PM_HSBDIV_SIZE 1
33#define PM_PBASEL_OFFSET 16
34#define PM_PBASEL_SIZE 3
35#define PM_PBADIV_OFFSET 23
36#define PM_PBADIV_SIZE 1
37#define PM_PBBSEL_OFFSET 24
38#define PM_PBBSEL_SIZE 3
39#define PM_PBBDIV_OFFSET 31
40#define PM_PBBDIV_SIZE 1
41
42/* Bitfields in PLL0 */
43#define PM_PLLEN_OFFSET 0
44#define PM_PLLEN_SIZE 1
45#define PM_PLLOSC_OFFSET 1
46#define PM_PLLOSC_SIZE 1
47#define PM_PLLOPT_OFFSET 2
48#define PM_PLLOPT_SIZE 3
49#define PM_PLLDIV_OFFSET 8
50#define PM_PLLDIV_SIZE 8
51#define PM_PLLMUL_OFFSET 16
52#define PM_PLLMUL_SIZE 8
53#define PM_PLLCOUNT_OFFSET 24
54#define PM_PLLCOUNT_SIZE 6
55#define PM_PLLTEST_OFFSET 31
56#define PM_PLLTEST_SIZE 1
57
58/* Bitfields in ICR */
59#define PM_LOCK0_OFFSET 0
60#define PM_LOCK0_SIZE 1
61#define PM_LOCK1_OFFSET 1
62#define PM_LOCK1_SIZE 1
63#define PM_WAKE_OFFSET 2
64#define PM_WAKE_SIZE 1
65#define PM_CKRDY_OFFSET 5
66#define PM_CKRDY_SIZE 1
67#define PM_MSKRDY_OFFSET 6
68#define PM_MSKRDY_SIZE 1
69
70/* Bitfields in GCCTRL0 */
71#define PM_OSCSEL_OFFSET 0
72#define PM_OSCSEL_SIZE 1
73#define PM_PLLSEL_OFFSET 1
74#define PM_PLLSEL_SIZE 1
75#define PM_CEN_OFFSET 2
76#define PM_CEN_SIZE 1
77#define PM_DIVEN_OFFSET 4
78#define PM_DIVEN_SIZE 1
79#define PM_DIV_OFFSET 8
80#define PM_DIV_SIZE 8
81
82/* Bitfields in RCAUSE */
83#define PM_POR_OFFSET 0
84#define PM_POR_SIZE 1
85#define PM_EXT_OFFSET 2
86#define PM_EXT_SIZE 1
87#define PM_WDT_OFFSET 3
88#define PM_WDT_SIZE 1
89#define PM_NTAE_OFFSET 4
90#define PM_NTAE_SIZE 1
91
92/* Bit manipulation macros */
93#define PM_BIT(name) \
94 (1 << PM_##name##_OFFSET)
95#define PM_BF(name,value) \
96 (((value) & ((1 << PM_##name##_SIZE) - 1)) \
97 << PM_##name##_OFFSET)
98#define PM_BFEXT(name,value) \
99 (((value) >> PM_##name##_OFFSET) \
100 & ((1 << PM_##name##_SIZE) - 1))
101#define PM_BFINS(name,value,old)\
102 (((old) & ~(((1 << PM_##name##_SIZE) - 1) \
103 << PM_##name##_OFFSET)) \
104 | PM_BF(name,value))
105
106/* Register access macros */
107#define pm_readl(reg) \
108 __raw_readl((void __iomem *)AT32_PM_BASE + PM_##reg)
109#define pm_writel(reg,value) \
110 __raw_writel((value), (void __iomem *)AT32_PM_BASE + PM_##reg)
111
112#endif /* __ARCH_AVR32_MACH_AT32AP_PM_H__ */
diff --git a/arch/avr32/mach-at32ap/sm.h b/arch/avr32/mach-at32ap/sm.h
deleted file mode 100644
index cad02b512bcb..000000000000
--- a/arch/avr32/mach-at32ap/sm.h
+++ /dev/null
@@ -1,242 +0,0 @@
1/*
2 * Register definitions for SM
3 *
4 * System Manager
5 */
6#ifndef __ASM_AVR32_SM_H__
7#define __ASM_AVR32_SM_H__
8
9/* SM register offsets */
10#define SM_PM_MCCTRL 0x0000
11#define SM_PM_CKSEL 0x0004
12#define SM_PM_CPU_MASK 0x0008
13#define SM_PM_HSB_MASK 0x000c
14#define SM_PM_PBA_MASK 0x0010
15#define SM_PM_PBB_MASK 0x0014
16#define SM_PM_PLL0 0x0020
17#define SM_PM_PLL1 0x0024
18#define SM_PM_VCTRL 0x0030
19#define SM_PM_VMREF 0x0034
20#define SM_PM_VMV 0x0038
21#define SM_PM_IER 0x0040
22#define SM_PM_IDR 0x0044
23#define SM_PM_IMR 0x0048
24#define SM_PM_ISR 0x004c
25#define SM_PM_ICR 0x0050
26#define SM_PM_GCCTRL 0x0060
27#define SM_RTC_CTRL 0x0080
28#define SM_RTC_VAL 0x0084
29#define SM_RTC_TOP 0x0088
30#define SM_RTC_IER 0x0090
31#define SM_RTC_IDR 0x0094
32#define SM_RTC_IMR 0x0098
33#define SM_RTC_ISR 0x009c
34#define SM_RTC_ICR 0x00a0
35#define SM_WDT_CTRL 0x00b0
36#define SM_WDT_CLR 0x00b4
37#define SM_WDT_EXT 0x00b8
38#define SM_RC_RCAUSE 0x00c0
39#define SM_EIM_IER 0x0100
40#define SM_EIM_IDR 0x0104
41#define SM_EIM_IMR 0x0108
42#define SM_EIM_ISR 0x010c
43#define SM_EIM_ICR 0x0110
44#define SM_EIM_MODE 0x0114
45#define SM_EIM_EDGE 0x0118
46#define SM_EIM_LEVEL 0x011c
47#define SM_EIM_TEST 0x0120
48#define SM_EIM_NMIC 0x0124
49
50/* Bitfields in PM_MCCTRL */
51
52/* Bitfields in PM_CKSEL */
53#define SM_CPUSEL_OFFSET 0
54#define SM_CPUSEL_SIZE 3
55#define SM_CPUDIV_OFFSET 7
56#define SM_CPUDIV_SIZE 1
57#define SM_HSBSEL_OFFSET 8
58#define SM_HSBSEL_SIZE 3
59#define SM_HSBDIV_OFFSET 15
60#define SM_HSBDIV_SIZE 1
61#define SM_PBASEL_OFFSET 16
62#define SM_PBASEL_SIZE 3
63#define SM_PBADIV_OFFSET 23
64#define SM_PBADIV_SIZE 1
65#define SM_PBBSEL_OFFSET 24
66#define SM_PBBSEL_SIZE 3
67#define SM_PBBDIV_OFFSET 31
68#define SM_PBBDIV_SIZE 1
69
70/* Bitfields in PM_CPU_MASK */
71
72/* Bitfields in PM_HSB_MASK */
73
74/* Bitfields in PM_PBA_MASK */
75
76/* Bitfields in PM_PBB_MASK */
77
78/* Bitfields in PM_PLL0 */
79#define SM_PLLEN_OFFSET 0
80#define SM_PLLEN_SIZE 1
81#define SM_PLLOSC_OFFSET 1
82#define SM_PLLOSC_SIZE 1
83#define SM_PLLOPT_OFFSET 2
84#define SM_PLLOPT_SIZE 3
85#define SM_PLLDIV_OFFSET 8
86#define SM_PLLDIV_SIZE 8
87#define SM_PLLMUL_OFFSET 16
88#define SM_PLLMUL_SIZE 8
89#define SM_PLLCOUNT_OFFSET 24
90#define SM_PLLCOUNT_SIZE 6
91#define SM_PLLTEST_OFFSET 31
92#define SM_PLLTEST_SIZE 1
93
94/* Bitfields in PM_PLL1 */
95
96/* Bitfields in PM_VCTRL */
97#define SM_VAUTO_OFFSET 0
98#define SM_VAUTO_SIZE 1
99#define SM_PM_VCTRL_VAL_OFFSET 8
100#define SM_PM_VCTRL_VAL_SIZE 7
101
102/* Bitfields in PM_VMREF */
103#define SM_REFSEL_OFFSET 0
104#define SM_REFSEL_SIZE 4
105
106/* Bitfields in PM_VMV */
107#define SM_PM_VMV_VAL_OFFSET 0
108#define SM_PM_VMV_VAL_SIZE 8
109
110/* Bitfields in PM_IER */
111
112/* Bitfields in PM_IDR */
113
114/* Bitfields in PM_IMR */
115
116/* Bitfields in PM_ISR */
117
118/* Bitfields in PM_ICR */
119#define SM_LOCK0_OFFSET 0
120#define SM_LOCK0_SIZE 1
121#define SM_LOCK1_OFFSET 1
122#define SM_LOCK1_SIZE 1
123#define SM_WAKE_OFFSET 2
124#define SM_WAKE_SIZE 1
125#define SM_VOK_OFFSET 3
126#define SM_VOK_SIZE 1
127#define SM_VMRDY_OFFSET 4
128#define SM_VMRDY_SIZE 1
129#define SM_CKRDY_OFFSET 5
130#define SM_CKRDY_SIZE 1
131
132/* Bitfields in PM_GCCTRL */
133#define SM_OSCSEL_OFFSET 0
134#define SM_OSCSEL_SIZE 1
135#define SM_PLLSEL_OFFSET 1
136#define SM_PLLSEL_SIZE 1
137#define SM_CEN_OFFSET 2
138#define SM_CEN_SIZE 1
139#define SM_CPC_OFFSET 3
140#define SM_CPC_SIZE 1
141#define SM_DIVEN_OFFSET 4
142#define SM_DIVEN_SIZE 1
143#define SM_DIV_OFFSET 8
144#define SM_DIV_SIZE 8
145
146/* Bitfields in RTC_CTRL */
147#define SM_PCLR_OFFSET 1
148#define SM_PCLR_SIZE 1
149#define SM_TOPEN_OFFSET 2
150#define SM_TOPEN_SIZE 1
151#define SM_CLKEN_OFFSET 3
152#define SM_CLKEN_SIZE 1
153#define SM_PSEL_OFFSET 8
154#define SM_PSEL_SIZE 16
155
156/* Bitfields in RTC_VAL */
157#define SM_RTC_VAL_VAL_OFFSET 0
158#define SM_RTC_VAL_VAL_SIZE 31
159
160/* Bitfields in RTC_TOP */
161#define SM_RTC_TOP_VAL_OFFSET 0
162#define SM_RTC_TOP_VAL_SIZE 32
163
164/* Bitfields in RTC_IER */
165
166/* Bitfields in RTC_IDR */
167
168/* Bitfields in RTC_IMR */
169
170/* Bitfields in RTC_ISR */
171
172/* Bitfields in RTC_ICR */
173#define SM_TOPI_OFFSET 0
174#define SM_TOPI_SIZE 1
175
176/* Bitfields in WDT_CTRL */
177#define SM_KEY_OFFSET 24
178#define SM_KEY_SIZE 8
179
180/* Bitfields in WDT_CLR */
181
182/* Bitfields in WDT_EXT */
183
184/* Bitfields in RC_RCAUSE */
185#define SM_POR_OFFSET 0
186#define SM_POR_SIZE 1
187#define SM_BOD_OFFSET 1
188#define SM_BOD_SIZE 1
189#define SM_EXT_OFFSET 2
190#define SM_EXT_SIZE 1
191#define SM_WDT_OFFSET 3
192#define SM_WDT_SIZE 1
193#define SM_NTAE_OFFSET 4
194#define SM_NTAE_SIZE 1
195#define SM_SERP_OFFSET 5
196#define SM_SERP_SIZE 1
197
198/* Bitfields in EIM_IER */
199
200/* Bitfields in EIM_IDR */
201
202/* Bitfields in EIM_IMR */
203
204/* Bitfields in EIM_ISR */
205
206/* Bitfields in EIM_ICR */
207
208/* Bitfields in EIM_MODE */
209
210/* Bitfields in EIM_EDGE */
211#define SM_INT0_OFFSET 0
212#define SM_INT0_SIZE 1
213#define SM_INT1_OFFSET 1
214#define SM_INT1_SIZE 1
215#define SM_INT2_OFFSET 2
216#define SM_INT2_SIZE 1
217#define SM_INT3_OFFSET 3
218#define SM_INT3_SIZE 1
219
220/* Bitfields in EIM_LEVEL */
221
222/* Bitfields in EIM_TEST */
223#define SM_TESTEN_OFFSET 31
224#define SM_TESTEN_SIZE 1
225
226/* Bitfields in EIM_NMIC */
227#define SM_EN_OFFSET 0
228#define SM_EN_SIZE 1
229
230/* Bit manipulation macros */
231#define SM_BIT(name) (1 << SM_##name##_OFFSET)
232#define SM_BF(name,value) (((value) & ((1 << SM_##name##_SIZE) - 1)) << SM_##name##_OFFSET)
233#define SM_BFEXT(name,value) (((value) >> SM_##name##_OFFSET) & ((1 << SM_##name##_SIZE) - 1))
234#define SM_BFINS(name,value,old) (((old) & ~(((1 << SM_##name##_SIZE) - 1) << SM_##name##_OFFSET)) | SM_BF(name,value))
235
236/* Register access macros */
237#define sm_readl(port,reg) \
238 __raw_readl((port)->regs + SM_##reg)
239#define sm_writel(port,reg,value) \
240 __raw_writel((value), (port)->regs + SM_##reg)
241
242#endif /* __ASM_AVR32_SM_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 09:36:46 -0500