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authorDavid Woodhouse <David.Woodhouse@intel.com>2008-07-25 10:40:14 -0400
committerDavid Woodhouse <David.Woodhouse@intel.com>2008-07-25 10:40:14 -0400
commitff877ea80efa2015b6263766f78ee42c2a1b32f9 (patch)
tree85205005c611ab774702148558321c6fb92f1ccd /arch/avr32/mach-at32ap
parent30821fee4f0cb3e6d241d9f7ddc37742212e3eb7 (diff)
parentd37e6bf68fc1eb34a4ad21d9ae8890ed37ea80e7 (diff)
Merge branch 'linux-next' of git://git.infradead.org/~dedekind/ubi-2.6
Diffstat (limited to 'arch/avr32/mach-at32ap')
-rw-r--r--arch/avr32/mach-at32ap/Makefile7
-rw-r--r--arch/avr32/mach-at32ap/at32ap700x.c309
-rw-r--r--arch/avr32/mach-at32ap/intc.c80
-rw-r--r--arch/avr32/mach-at32ap/pdc.c (renamed from arch/avr32/mach-at32ap/at32ap.c)8
-rw-r--r--arch/avr32/mach-at32ap/pio.c2
-rw-r--r--arch/avr32/mach-at32ap/pio.h2
-rw-r--r--arch/avr32/mach-at32ap/pm-at32ap700x.S108
-rw-r--r--arch/avr32/mach-at32ap/pm.c245
-rw-r--r--arch/avr32/mach-at32ap/sdramc.h76
9 files changed, 753 insertions, 84 deletions
diff --git a/arch/avr32/mach-at32ap/Makefile b/arch/avr32/mach-at32ap/Makefile
index e89009439e4a..d5018e2eed25 100644
--- a/arch/avr32/mach-at32ap/Makefile
+++ b/arch/avr32/mach-at32ap/Makefile
@@ -1,3 +1,8 @@
1obj-y += at32ap.o clock.o intc.o extint.o pio.o hsmc.o 1obj-y += pdc.o clock.o intc.o extint.o pio.o hsmc.o
2obj-$(CONFIG_CPU_AT32AP700X) += at32ap700x.o pm-at32ap700x.o 2obj-$(CONFIG_CPU_AT32AP700X) += at32ap700x.o pm-at32ap700x.o
3obj-$(CONFIG_CPU_FREQ_AT32AP) += cpufreq.o 3obj-$(CONFIG_CPU_FREQ_AT32AP) += cpufreq.o
4obj-$(CONFIG_PM) += pm.o
5
6ifeq ($(CONFIG_PM_DEBUG),y)
7CFLAGS_pm.o += -DDEBUG
8endif
diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
index b65d3e0667a8..351e1b42f937 100644
--- a/arch/avr32/mach-at32ap/at32ap700x.c
+++ b/arch/avr32/mach-at32ap/at32ap700x.c
@@ -7,6 +7,7 @@
7 */ 7 */
8#include <linux/clk.h> 8#include <linux/clk.h>
9#include <linux/delay.h> 9#include <linux/delay.h>
10#include <linux/dw_dmac.h>
10#include <linux/fb.h> 11#include <linux/fb.h>
11#include <linux/init.h> 12#include <linux/init.h>
12#include <linux/platform_device.h> 13#include <linux/platform_device.h>
@@ -14,12 +15,14 @@
14#include <linux/spi/spi.h> 15#include <linux/spi/spi.h>
15#include <linux/usb/atmel_usba_udc.h> 16#include <linux/usb/atmel_usba_udc.h>
16 17
18#include <asm/atmel-mci.h>
17#include <asm/io.h> 19#include <asm/io.h>
18#include <asm/irq.h> 20#include <asm/irq.h>
19 21
20#include <asm/arch/at32ap700x.h> 22#include <asm/arch/at32ap700x.h>
21#include <asm/arch/board.h> 23#include <asm/arch/board.h>
22#include <asm/arch/portmux.h> 24#include <asm/arch/portmux.h>
25#include <asm/arch/sram.h>
23 26
24#include <video/atmel_lcdc.h> 27#include <video/atmel_lcdc.h>
25 28
@@ -93,19 +96,12 @@ static struct clk devname##_##_name = { \
93 96
94static DEFINE_SPINLOCK(pm_lock); 97static DEFINE_SPINLOCK(pm_lock);
95 98
96unsigned long at32ap7000_osc_rates[3] = {
97 [0] = 32768,
98 /* FIXME: these are ATSTK1002-specific */
99 [1] = 20000000,
100 [2] = 12000000,
101};
102
103static struct clk osc0; 99static struct clk osc0;
104static struct clk osc1; 100static struct clk osc1;
105 101
106static unsigned long osc_get_rate(struct clk *clk) 102static unsigned long osc_get_rate(struct clk *clk)
107{ 103{
108 return at32ap7000_osc_rates[clk->index]; 104 return at32_board_osc_rates[clk->index];
109} 105}
110 106
111static unsigned long pll_get_rate(struct clk *clk, unsigned long control) 107static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
@@ -599,6 +595,17 @@ static void __init genclk_init_parent(struct clk *clk)
599 clk->parent = parent; 595 clk->parent = parent;
600} 596}
601 597
598static struct dw_dma_platform_data dw_dmac0_data = {
599 .nr_channels = 3,
600};
601
602static struct resource dw_dmac0_resource[] = {
603 PBMEM(0xff200000),
604 IRQ(2),
605};
606DEFINE_DEV_DATA(dw_dmac, 0);
607DEV_CLK(hclk, dw_dmac0, hsb, 10);
608
602/* -------------------------------------------------------------------- 609/* --------------------------------------------------------------------
603 * System peripherals 610 * System peripherals
604 * -------------------------------------------------------------------- */ 611 * -------------------------------------------------------------------- */
@@ -682,6 +689,14 @@ static struct clk hramc_clk = {
682 .users = 1, 689 .users = 1,
683 .index = 3, 690 .index = 3,
684}; 691};
692static struct clk sdramc_clk = {
693 .name = "sdramc_clk",
694 .parent = &pbb_clk,
695 .mode = pbb_clk_mode,
696 .get_rate = pbb_clk_get_rate,
697 .users = 1,
698 .index = 14,
699};
685 700
686static struct resource smc0_resource[] = { 701static struct resource smc0_resource[] = {
687 PBMEM(0xfff03400), 702 PBMEM(0xfff03400),
@@ -705,17 +720,6 @@ static struct clk pico_clk = {
705 .users = 1, 720 .users = 1,
706}; 721};
707 722
708static struct resource dmaca0_resource[] = {
709 {
710 .start = 0xff200000,
711 .end = 0xff20ffff,
712 .flags = IORESOURCE_MEM,
713 },
714 IRQ(2),
715};
716DEFINE_DEV(dmaca, 0);
717DEV_CLK(hclk, dmaca0, hsb, 10);
718
719/* -------------------------------------------------------------------- 723/* --------------------------------------------------------------------
720 * HMATRIX 724 * HMATRIX
721 * -------------------------------------------------------------------- */ 725 * -------------------------------------------------------------------- */
@@ -828,7 +832,7 @@ void __init at32_add_system_devices(void)
828 platform_device_register(&at32_eic0_device); 832 platform_device_register(&at32_eic0_device);
829 platform_device_register(&smc0_device); 833 platform_device_register(&smc0_device);
830 platform_device_register(&pdc_device); 834 platform_device_register(&pdc_device);
831 platform_device_register(&dmaca0_device); 835 platform_device_register(&dw_dmac0_device);
832 836
833 platform_device_register(&at32_tcb0_device); 837 platform_device_register(&at32_tcb0_device);
834 platform_device_register(&at32_tcb1_device); 838 platform_device_register(&at32_tcb1_device);
@@ -841,6 +845,81 @@ void __init at32_add_system_devices(void)
841} 845}
842 846
843/* -------------------------------------------------------------------- 847/* --------------------------------------------------------------------
848 * PSIF
849 * -------------------------------------------------------------------- */
850static struct resource atmel_psif0_resource[] __initdata = {
851 {
852 .start = 0xffe03c00,
853 .end = 0xffe03cff,
854 .flags = IORESOURCE_MEM,
855 },
856 IRQ(18),
857};
858static struct clk atmel_psif0_pclk = {
859 .name = "pclk",
860 .parent = &pba_clk,
861 .mode = pba_clk_mode,
862 .get_rate = pba_clk_get_rate,
863 .index = 15,
864};
865
866static struct resource atmel_psif1_resource[] __initdata = {
867 {
868 .start = 0xffe03d00,
869 .end = 0xffe03dff,
870 .flags = IORESOURCE_MEM,
871 },
872 IRQ(18),
873};
874static struct clk atmel_psif1_pclk = {
875 .name = "pclk",
876 .parent = &pba_clk,
877 .mode = pba_clk_mode,
878 .get_rate = pba_clk_get_rate,
879 .index = 15,
880};
881
882struct platform_device *__init at32_add_device_psif(unsigned int id)
883{
884 struct platform_device *pdev;
885
886 if (!(id == 0 || id == 1))
887 return NULL;
888
889 pdev = platform_device_alloc("atmel_psif", id);
890 if (!pdev)
891 return NULL;
892
893 switch (id) {
894 case 0:
895 if (platform_device_add_resources(pdev, atmel_psif0_resource,
896 ARRAY_SIZE(atmel_psif0_resource)))
897 goto err_add_resources;
898 atmel_psif0_pclk.dev = &pdev->dev;
899 select_peripheral(PA(8), PERIPH_A, 0); /* CLOCK */
900 select_peripheral(PA(9), PERIPH_A, 0); /* DATA */
901 break;
902 case 1:
903 if (platform_device_add_resources(pdev, atmel_psif1_resource,
904 ARRAY_SIZE(atmel_psif1_resource)))
905 goto err_add_resources;
906 atmel_psif1_pclk.dev = &pdev->dev;
907 select_peripheral(PB(11), PERIPH_A, 0); /* CLOCK */
908 select_peripheral(PB(12), PERIPH_A, 0); /* DATA */
909 break;
910 default:
911 return NULL;
912 }
913
914 platform_device_add(pdev);
915 return pdev;
916
917err_add_resources:
918 platform_device_put(pdev);
919 return NULL;
920}
921
922/* --------------------------------------------------------------------
844 * USART 923 * USART
845 * -------------------------------------------------------------------- */ 924 * -------------------------------------------------------------------- */
846 925
@@ -1113,7 +1192,8 @@ at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1113 switch (id) { 1192 switch (id) {
1114 case 0: 1193 case 0:
1115 pdev = &atmel_spi0_device; 1194 pdev = &atmel_spi0_device;
1116 select_peripheral(PA(0), PERIPH_A, 0); /* MISO */ 1195 /* pullup MISO so a level is always defined */
1196 select_peripheral(PA(0), PERIPH_A, AT32_GPIOF_PULLUP);
1117 select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */ 1197 select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */
1118 select_peripheral(PA(2), PERIPH_A, 0); /* SCK */ 1198 select_peripheral(PA(2), PERIPH_A, 0); /* SCK */
1119 at32_spi_setup_slaves(0, b, n, spi0_pins); 1199 at32_spi_setup_slaves(0, b, n, spi0_pins);
@@ -1121,7 +1201,8 @@ at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1121 1201
1122 case 1: 1202 case 1:
1123 pdev = &atmel_spi1_device; 1203 pdev = &atmel_spi1_device;
1124 select_peripheral(PB(0), PERIPH_B, 0); /* MISO */ 1204 /* pullup MISO so a level is always defined */
1205 select_peripheral(PB(0), PERIPH_B, AT32_GPIOF_PULLUP);
1125 select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */ 1206 select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */
1126 select_peripheral(PB(5), PERIPH_B, 0); /* SCK */ 1207 select_peripheral(PB(5), PERIPH_B, 0); /* SCK */
1127 at32_spi_setup_slaves(1, b, n, spi1_pins); 1208 at32_spi_setup_slaves(1, b, n, spi1_pins);
@@ -1199,20 +1280,32 @@ static struct clk atmel_mci0_pclk = {
1199 .index = 9, 1280 .index = 9,
1200}; 1281};
1201 1282
1202struct platform_device *__init at32_add_device_mci(unsigned int id) 1283struct platform_device *__init
1284at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1203{ 1285{
1204 struct platform_device *pdev; 1286 struct mci_platform_data _data;
1287 struct platform_device *pdev;
1288 struct dw_dma_slave *dws;
1205 1289
1206 if (id != 0) 1290 if (id != 0)
1207 return NULL; 1291 return NULL;
1208 1292
1209 pdev = platform_device_alloc("atmel_mci", id); 1293 pdev = platform_device_alloc("atmel_mci", id);
1210 if (!pdev) 1294 if (!pdev)
1211 return NULL; 1295 goto fail;
1212 1296
1213 if (platform_device_add_resources(pdev, atmel_mci0_resource, 1297 if (platform_device_add_resources(pdev, atmel_mci0_resource,
1214 ARRAY_SIZE(atmel_mci0_resource))) 1298 ARRAY_SIZE(atmel_mci0_resource)))
1215 goto err_add_resources; 1299 goto fail;
1300
1301 if (!data) {
1302 data = &_data;
1303 memset(data, 0, sizeof(struct mci_platform_data));
1304 }
1305
1306 if (platform_device_add_data(pdev, data,
1307 sizeof(struct mci_platform_data)))
1308 goto fail;
1216 1309
1217 select_peripheral(PA(10), PERIPH_A, 0); /* CLK */ 1310 select_peripheral(PA(10), PERIPH_A, 0); /* CLK */
1218 select_peripheral(PA(11), PERIPH_A, 0); /* CMD */ 1311 select_peripheral(PA(11), PERIPH_A, 0); /* CMD */
@@ -1221,12 +1314,19 @@ struct platform_device *__init at32_add_device_mci(unsigned int id)
1221 select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */ 1314 select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
1222 select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */ 1315 select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
1223 1316
1317 if (data) {
1318 if (data->detect_pin != GPIO_PIN_NONE)
1319 at32_select_gpio(data->detect_pin, 0);
1320 if (data->wp_pin != GPIO_PIN_NONE)
1321 at32_select_gpio(data->wp_pin, 0);
1322 }
1323
1224 atmel_mci0_pclk.dev = &pdev->dev; 1324 atmel_mci0_pclk.dev = &pdev->dev;
1225 1325
1226 platform_device_add(pdev); 1326 platform_device_add(pdev);
1227 return pdev; 1327 return pdev;
1228 1328
1229err_add_resources: 1329fail:
1230 platform_device_put(pdev); 1330 platform_device_put(pdev);
1231 return NULL; 1331 return NULL;
1232} 1332}
@@ -1264,7 +1364,8 @@ static struct clk atmel_lcdfb0_pixclk = {
1264 1364
1265struct platform_device *__init 1365struct platform_device *__init
1266at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data, 1366at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1267 unsigned long fbmem_start, unsigned long fbmem_len) 1367 unsigned long fbmem_start, unsigned long fbmem_len,
1368 unsigned int pin_config)
1268{ 1369{
1269 struct platform_device *pdev; 1370 struct platform_device *pdev;
1270 struct atmel_lcdfb_info *info; 1371 struct atmel_lcdfb_info *info;
@@ -1291,37 +1392,77 @@ at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1291 switch (id) { 1392 switch (id) {
1292 case 0: 1393 case 0:
1293 pdev = &atmel_lcdfb0_device; 1394 pdev = &atmel_lcdfb0_device;
1294 select_peripheral(PC(19), PERIPH_A, 0); /* CC */ 1395
1295 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */ 1396 switch (pin_config) {
1296 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */ 1397 case 0:
1297 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */ 1398 select_peripheral(PC(19), PERIPH_A, 0); /* CC */
1298 select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */ 1399 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
1299 select_peripheral(PC(24), PERIPH_A, 0); /* MODE */ 1400 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
1300 select_peripheral(PC(25), PERIPH_A, 0); /* PWR */ 1401 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
1301 select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */ 1402 select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */
1302 select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */ 1403 select_peripheral(PC(24), PERIPH_A, 0); /* MODE */
1303 select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */ 1404 select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
1304 select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */ 1405 select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */
1305 select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */ 1406 select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */
1306 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */ 1407 select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */
1307 select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */ 1408 select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */
1308 select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */ 1409 select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */
1309 select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */ 1410 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
1310 select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */ 1411 select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
1311 select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */ 1412 select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
1312 select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */ 1413 select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
1313 select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */ 1414 select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
1314 select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */ 1415 select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
1315 select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */ 1416 select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
1316 select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */ 1417 select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
1317 select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */ 1418 select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
1318 select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */ 1419 select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
1319 select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */ 1420 select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
1320 select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */ 1421 select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
1321 select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */ 1422 select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
1322 select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */ 1423 select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
1323 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */ 1424 select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
1324 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */ 1425 select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
1426 select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
1427 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1428 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1429 break;
1430 case 1:
1431 select_peripheral(PE(0), PERIPH_B, 0); /* CC */
1432 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
1433 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
1434 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
1435 select_peripheral(PE(1), PERIPH_B, 0); /* DVAL */
1436 select_peripheral(PE(2), PERIPH_B, 0); /* MODE */
1437 select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
1438 select_peripheral(PE(3), PERIPH_B, 0); /* DATA0 */
1439 select_peripheral(PE(4), PERIPH_B, 0); /* DATA1 */
1440 select_peripheral(PE(5), PERIPH_B, 0); /* DATA2 */
1441 select_peripheral(PE(6), PERIPH_B, 0); /* DATA3 */
1442 select_peripheral(PE(7), PERIPH_B, 0); /* DATA4 */
1443 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
1444 select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
1445 select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
1446 select_peripheral(PE(8), PERIPH_B, 0); /* DATA8 */
1447 select_peripheral(PE(9), PERIPH_B, 0); /* DATA9 */
1448 select_peripheral(PE(10), PERIPH_B, 0); /* DATA10 */
1449 select_peripheral(PE(11), PERIPH_B, 0); /* DATA11 */
1450 select_peripheral(PE(12), PERIPH_B, 0); /* DATA12 */
1451 select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
1452 select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
1453 select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
1454 select_peripheral(PE(13), PERIPH_B, 0); /* DATA16 */
1455 select_peripheral(PE(14), PERIPH_B, 0); /* DATA17 */
1456 select_peripheral(PE(15), PERIPH_B, 0); /* DATA18 */
1457 select_peripheral(PE(16), PERIPH_B, 0); /* DATA19 */
1458 select_peripheral(PE(17), PERIPH_B, 0); /* DATA20 */
1459 select_peripheral(PE(18), PERIPH_B, 0); /* DATA21 */
1460 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1461 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1462 break;
1463 default:
1464 goto err_invalid_id;
1465 }
1325 1466
1326 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0); 1467 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1327 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0)); 1468 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
@@ -1360,7 +1501,7 @@ static struct resource atmel_pwm0_resource[] __initdata = {
1360 IRQ(24), 1501 IRQ(24),
1361}; 1502};
1362static struct clk atmel_pwm0_mck = { 1503static struct clk atmel_pwm0_mck = {
1363 .name = "mck", 1504 .name = "pwm_clk",
1364 .parent = &pbb_clk, 1505 .parent = &pbb_clk,
1365 .mode = pbb_clk_mode, 1506 .mode = pbb_clk_mode,
1366 .get_rate = pbb_clk_get_rate, 1507 .get_rate = pbb_clk_get_rate,
@@ -1939,11 +2080,12 @@ struct clk *at32_clock_list[] = {
1939 &hmatrix_clk, 2080 &hmatrix_clk,
1940 &ebi_clk, 2081 &ebi_clk,
1941 &hramc_clk, 2082 &hramc_clk,
2083 &sdramc_clk,
1942 &smc0_pclk, 2084 &smc0_pclk,
1943 &smc0_mck, 2085 &smc0_mck,
1944 &pdc_hclk, 2086 &pdc_hclk,
1945 &pdc_pclk, 2087 &pdc_pclk,
1946 &dmaca0_hclk, 2088 &dw_dmac0_hclk,
1947 &pico_clk, 2089 &pico_clk,
1948 &pio0_mck, 2090 &pio0_mck,
1949 &pio1_mck, 2091 &pio1_mck,
@@ -1952,6 +2094,8 @@ struct clk *at32_clock_list[] = {
1952 &pio4_mck, 2094 &pio4_mck,
1953 &at32_tcb0_t0_clk, 2095 &at32_tcb0_t0_clk,
1954 &at32_tcb1_t0_clk, 2096 &at32_tcb1_t0_clk,
2097 &atmel_psif0_pclk,
2098 &atmel_psif1_pclk,
1955 &atmel_usart0_usart, 2099 &atmel_usart0_usart,
1956 &atmel_usart1_usart, 2100 &atmel_usart1_usart,
1957 &atmel_usart2_usart, 2101 &atmel_usart2_usart,
@@ -1987,16 +2131,7 @@ struct clk *at32_clock_list[] = {
1987}; 2131};
1988unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list); 2132unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
1989 2133
1990void __init at32_portmux_init(void) 2134void __init setup_platform(void)
1991{
1992 at32_init_pio(&pio0_device);
1993 at32_init_pio(&pio1_device);
1994 at32_init_pio(&pio2_device);
1995 at32_init_pio(&pio3_device);
1996 at32_init_pio(&pio4_device);
1997}
1998
1999void __init at32_clock_init(void)
2000{ 2135{
2001 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0; 2136 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2002 int i; 2137 int i;
@@ -2051,4 +2186,36 @@ void __init at32_clock_init(void)
2051 pm_writel(HSB_MASK, hsb_mask); 2186 pm_writel(HSB_MASK, hsb_mask);
2052 pm_writel(PBA_MASK, pba_mask); 2187 pm_writel(PBA_MASK, pba_mask);
2053 pm_writel(PBB_MASK, pbb_mask); 2188 pm_writel(PBB_MASK, pbb_mask);
2189
2190 /* Initialize the port muxes */
2191 at32_init_pio(&pio0_device);
2192 at32_init_pio(&pio1_device);
2193 at32_init_pio(&pio2_device);
2194 at32_init_pio(&pio3_device);
2195 at32_init_pio(&pio4_device);
2196}
2197
2198struct gen_pool *sram_pool;
2199
2200static int __init sram_init(void)
2201{
2202 struct gen_pool *pool;
2203
2204 /* 1KiB granularity */
2205 pool = gen_pool_create(10, -1);
2206 if (!pool)
2207 goto fail;
2208
2209 if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
2210 goto err_pool_add;
2211
2212 sram_pool = pool;
2213 return 0;
2214
2215err_pool_add:
2216 gen_pool_destroy(pool);
2217fail:
2218 pr_err("Failed to create SRAM pool\n");
2219 return -ENOMEM;
2054} 2220}
2221core_initcall(sram_init);
diff --git a/arch/avr32/mach-at32ap/intc.c b/arch/avr32/mach-at32ap/intc.c
index 097cf4e84052..994c4545e2b7 100644
--- a/arch/avr32/mach-at32ap/intc.c
+++ b/arch/avr32/mach-at32ap/intc.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2006 Atmel Corporation 2 * Copyright (C) 2006, 2008 Atmel Corporation
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
@@ -12,14 +12,20 @@
12#include <linux/interrupt.h> 12#include <linux/interrupt.h>
13#include <linux/irq.h> 13#include <linux/irq.h>
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/sysdev.h>
15 16
16#include <asm/io.h> 17#include <asm/io.h>
17 18
18#include "intc.h" 19#include "intc.h"
19 20
20struct intc { 21struct intc {
21 void __iomem *regs; 22 void __iomem *regs;
22 struct irq_chip chip; 23 struct irq_chip chip;
24 struct sys_device sysdev;
25#ifdef CONFIG_PM
26 unsigned long suspend_ipr;
27 unsigned long saved_ipr[64];
28#endif
23}; 29};
24 30
25extern struct platform_device at32_intc0_device; 31extern struct platform_device at32_intc0_device;
@@ -136,6 +142,74 @@ fail:
136 panic("Interrupt controller initialization failed!\n"); 142 panic("Interrupt controller initialization failed!\n");
137} 143}
138 144
145#ifdef CONFIG_PM
146void intc_set_suspend_handler(unsigned long offset)
147{
148 intc0.suspend_ipr = offset;
149}
150
151static int intc_suspend(struct sys_device *sdev, pm_message_t state)
152{
153 struct intc *intc = container_of(sdev, struct intc, sysdev);
154 int i;
155
156 if (unlikely(!irqs_disabled())) {
157 pr_err("intc_suspend: called with interrupts enabled\n");
158 return -EINVAL;
159 }
160
161 if (unlikely(!intc->suspend_ipr)) {
162 pr_err("intc_suspend: suspend_ipr not initialized\n");
163 return -EINVAL;
164 }
165
166 for (i = 0; i < 64; i++) {
167 intc->saved_ipr[i] = intc_readl(intc, INTPR0 + 4 * i);
168 intc_writel(intc, INTPR0 + 4 * i, intc->suspend_ipr);
169 }
170
171 return 0;
172}
173
174static int intc_resume(struct sys_device *sdev)
175{
176 struct intc *intc = container_of(sdev, struct intc, sysdev);
177 int i;
178
179 WARN_ON(!irqs_disabled());
180
181 for (i = 0; i < 64; i++)
182 intc_writel(intc, INTPR0 + 4 * i, intc->saved_ipr[i]);
183
184 return 0;
185}
186#else
187#define intc_suspend NULL
188#define intc_resume NULL
189#endif
190
191static struct sysdev_class intc_class = {
192 .name = "intc",
193 .suspend = intc_suspend,
194 .resume = intc_resume,
195};
196
197static int __init intc_init_sysdev(void)
198{
199 int ret;
200
201 ret = sysdev_class_register(&intc_class);
202 if (ret)
203 return ret;
204
205 intc0.sysdev.id = 0;
206 intc0.sysdev.cls = &intc_class;
207 ret = sysdev_register(&intc0.sysdev);
208
209 return ret;
210}
211device_initcall(intc_init_sysdev);
212
139unsigned long intc_get_pending(unsigned int group) 213unsigned long intc_get_pending(unsigned int group)
140{ 214{
141 return intc_readl(&intc0, INTREQ0 + 4 * group); 215 return intc_readl(&intc0, INTREQ0 + 4 * group);
diff --git a/arch/avr32/mach-at32ap/at32ap.c b/arch/avr32/mach-at32ap/pdc.c
index 7c4987f3287a..1040bda4fda7 100644
--- a/arch/avr32/mach-at32ap/at32ap.c
+++ b/arch/avr32/mach-at32ap/pdc.c
@@ -11,14 +11,6 @@
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/platform_device.h> 12#include <linux/platform_device.h>
13 13
14#include <asm/arch/init.h>
15
16void __init setup_platform(void)
17{
18 at32_clock_init();
19 at32_portmux_init();
20}
21
22static int __init pdc_probe(struct platform_device *pdev) 14static int __init pdc_probe(struct platform_device *pdev)
23{ 15{
24 struct clk *pclk, *hclk; 16 struct clk *pclk, *hclk;
diff --git a/arch/avr32/mach-at32ap/pio.c b/arch/avr32/mach-at32ap/pio.c
index 38a8fa31c0b5..60da03ba7117 100644
--- a/arch/avr32/mach-at32ap/pio.c
+++ b/arch/avr32/mach-at32ap/pio.c
@@ -318,6 +318,8 @@ static void pio_bank_show(struct seq_file *s, struct gpio_chip *chip)
318 const char *label; 318 const char *label;
319 319
320 label = gpiochip_is_requested(chip, i); 320 label = gpiochip_is_requested(chip, i);
321 if (!label && (imr & mask))
322 label = "[irq]";
321 if (!label) 323 if (!label)
322 continue; 324 continue;
323 325
diff --git a/arch/avr32/mach-at32ap/pio.h b/arch/avr32/mach-at32ap/pio.h
index 7795116a483a..9484dfcc08f2 100644
--- a/arch/avr32/mach-at32ap/pio.h
+++ b/arch/avr32/mach-at32ap/pio.h
@@ -57,7 +57,7 @@
57 57
58/* Bitfields in IFDR */ 58/* Bitfields in IFDR */
59 59
60/* Bitfields in ISFR */ 60/* Bitfields in IFSR */
61 61
62/* Bitfields in SODR */ 62/* Bitfields in SODR */
63 63
diff --git a/arch/avr32/mach-at32ap/pm-at32ap700x.S b/arch/avr32/mach-at32ap/pm-at32ap700x.S
index 949e2485e278..0a53ad314ff4 100644
--- a/arch/avr32/mach-at32ap/pm-at32ap700x.S
+++ b/arch/avr32/mach-at32ap/pm-at32ap700x.S
@@ -12,6 +12,12 @@
12#include <asm/thread_info.h> 12#include <asm/thread_info.h>
13#include <asm/arch/pm.h> 13#include <asm/arch/pm.h>
14 14
15#include "pm.h"
16#include "sdramc.h"
17
18/* Same as 0xfff00000 but fits in a 21 bit signed immediate */
19#define PM_BASE -0x100000
20
15 .section .bss, "wa", @nobits 21 .section .bss, "wa", @nobits
16 .global disable_idle_sleep 22 .global disable_idle_sleep
17 .type disable_idle_sleep, @object 23 .type disable_idle_sleep, @object
@@ -64,3 +70,105 @@ cpu_idle_skip_sleep:
64 unmask_interrupts 70 unmask_interrupts
65 retal r12 71 retal r12
66 .size cpu_idle_skip_sleep, . - cpu_idle_skip_sleep 72 .size cpu_idle_skip_sleep, . - cpu_idle_skip_sleep
73
74#ifdef CONFIG_PM
75 .section .init.text, "ax", @progbits
76
77 .global pm_exception
78 .type pm_exception, @function
79pm_exception:
80 /*
81 * Exceptions are masked when we switch to this handler, so
82 * we'll only get "unrecoverable" exceptions (offset 0.)
83 */
84 sub r12, pc, . - .Lpanic_msg
85 lddpc pc, .Lpanic_addr
86
87 .align 2
88.Lpanic_addr:
89 .long panic
90.Lpanic_msg:
91 .asciz "Unrecoverable exception during suspend\n"
92 .size pm_exception, . - pm_exception
93
94 .global pm_irq0
95 .type pm_irq0, @function
96pm_irq0:
97 /* Disable interrupts and return after the sleep instruction */
98 mfsr r9, SYSREG_RSR_INT0
99 mtsr SYSREG_RAR_INT0, r8
100 sbr r9, SYSREG_GM_OFFSET
101 mtsr SYSREG_RSR_INT0, r9
102 rete
103
104 /*
105 * void cpu_enter_standby(unsigned long sdramc_base)
106 *
107 * Enter PM_SUSPEND_STANDBY mode. At this point, all drivers
108 * are suspended and interrupts are disabled. Interrupts
109 * marked as 'wakeup' event sources may still come along and
110 * get us out of here.
111 *
112 * The SDRAM will be put into self-refresh mode (which does
113 * not require a clock from the CPU), and the CPU will be put
114 * into "frozen" mode (HSB bus stopped). The SDRAM controller
115 * will automatically bring the SDRAM into normal mode on the
116 * first access, and the power manager will automatically
117 * start the HSB and CPU clocks upon a wakeup event.
118 *
119 * This code uses the same "skip sleep" technique as above.
120 * It is very important that we jump directly to
121 * cpu_after_sleep after the sleep instruction since that's
122 * where we'll end up if the interrupt handler decides that we
123 * need to skip the sleep instruction.
124 */
125 .global pm_standby
126 .type pm_standby, @function
127pm_standby:
128 /*
129 * interrupts are already masked at this point, and EVBA
130 * points to pm_exception above.
131 */
132 ld.w r10, r12[SDRAMC_LPR]
133 sub r8, pc, . - 1f /* return address for irq handler */
134 mov r11, SDRAMC_LPR_LPCB_SELF_RFR
135 bfins r10, r11, 0, 2 /* LPCB <- self Refresh */
136 sync 0 /* flush write buffer */
137 st.w r12[SDRAMC_LPR], r11 /* put SDRAM in self-refresh mode */
138 ld.w r11, r12[SDRAMC_LPR]
139 unmask_interrupts
140 sleep CPU_SLEEP_FROZEN
1411: mask_interrupts
142 retal r12
143 .size pm_standby, . - pm_standby
144
145 .global pm_suspend_to_ram
146 .type pm_suspend_to_ram, @function
147pm_suspend_to_ram:
148 /*
149 * interrupts are already masked at this point, and EVBA
150 * points to pm_exception above.
151 */
152 mov r11, 0
153 cache r11[2], 8 /* clean all dcache lines */
154 sync 0 /* flush write buffer */
155 ld.w r10, r12[SDRAMC_LPR]
156 sub r8, pc, . - 1f /* return address for irq handler */
157 mov r11, SDRAMC_LPR_LPCB_SELF_RFR
158 bfins r10, r11, 0, 2 /* LPCB <- self refresh */
159 st.w r12[SDRAMC_LPR], r10 /* put SDRAM in self-refresh mode */
160 ld.w r11, r12[SDRAMC_LPR]
161
162 unmask_interrupts
163 sleep CPU_SLEEP_STOP
1641: mask_interrupts
165
166 retal r12
167 .size pm_suspend_to_ram, . - pm_suspend_to_ram
168
169 .global pm_sram_end
170 .type pm_sram_end, @function
171pm_sram_end:
172 .size pm_sram_end, 0
173
174#endif /* CONFIG_PM */
diff --git a/arch/avr32/mach-at32ap/pm.c b/arch/avr32/mach-at32ap/pm.c
new file mode 100644
index 000000000000..0b764320135d
--- /dev/null
+++ b/arch/avr32/mach-at32ap/pm.c
@@ -0,0 +1,245 @@
1/*
2 * AVR32 AP Power Management
3 *
4 * Copyright (C) 2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 */
10#include <linux/io.h>
11#include <linux/suspend.h>
12#include <linux/vmalloc.h>
13
14#include <asm/cacheflush.h>
15#include <asm/sysreg.h>
16
17#include <asm/arch/pm.h>
18#include <asm/arch/sram.h>
19
20/* FIXME: This is only valid for AP7000 */
21#define SDRAMC_BASE 0xfff03800
22
23#include "sdramc.h"
24
25#define SRAM_PAGE_FLAGS (SYSREG_BIT(TLBELO_D) | SYSREG_BF(SZ, 1) \
26 | SYSREG_BF(AP, 3) | SYSREG_BIT(G))
27
28
29static unsigned long pm_sram_start;
30static size_t pm_sram_size;
31static struct vm_struct *pm_sram_area;
32
33static void (*avr32_pm_enter_standby)(unsigned long sdramc_base);
34static void (*avr32_pm_enter_str)(unsigned long sdramc_base);
35
36/*
37 * Must be called with interrupts disabled. Exceptions will be masked
38 * on return (i.e. all exceptions will be "unrecoverable".)
39 */
40static void *avr32_pm_map_sram(void)
41{
42 unsigned long vaddr;
43 unsigned long page_addr;
44 u32 tlbehi;
45 u32 mmucr;
46
47 vaddr = (unsigned long)pm_sram_area->addr;
48 page_addr = pm_sram_start & PAGE_MASK;
49
50 /*
51 * Mask exceptions and grab the first TLB entry. We won't be
52 * needing it while sleeping.
53 */
54 asm volatile("ssrf %0" : : "i"(SYSREG_EM_OFFSET) : "memory");
55
56 mmucr = sysreg_read(MMUCR);
57 tlbehi = sysreg_read(TLBEHI);
58 sysreg_write(MMUCR, SYSREG_BFINS(DRP, 0, mmucr));
59
60 tlbehi = SYSREG_BF(ASID, SYSREG_BFEXT(ASID, tlbehi));
61 tlbehi |= vaddr & PAGE_MASK;
62 tlbehi |= SYSREG_BIT(TLBEHI_V);
63
64 sysreg_write(TLBELO, page_addr | SRAM_PAGE_FLAGS);
65 sysreg_write(TLBEHI, tlbehi);
66 __builtin_tlbw();
67
68 return (void *)(vaddr + pm_sram_start - page_addr);
69}
70
71/*
72 * Must be called with interrupts disabled. Exceptions will be
73 * unmasked on return.
74 */
75static void avr32_pm_unmap_sram(void)
76{
77 u32 mmucr;
78 u32 tlbehi;
79 u32 tlbarlo;
80
81 /* Going to update TLB entry at index 0 */
82 mmucr = sysreg_read(MMUCR);
83 tlbehi = sysreg_read(TLBEHI);
84 sysreg_write(MMUCR, SYSREG_BFINS(DRP, 0, mmucr));
85
86 /* Clear the "valid" bit */
87 tlbehi = SYSREG_BF(ASID, SYSREG_BFEXT(ASID, tlbehi));
88 sysreg_write(TLBEHI, tlbehi);
89
90 /* Mark it as "not accessed" */
91 tlbarlo = sysreg_read(TLBARLO);
92 sysreg_write(TLBARLO, tlbarlo | 0x80000000U);
93
94 /* Update the TLB */
95 __builtin_tlbw();
96
97 /* Unmask exceptions */
98 asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET) : "memory");
99}
100
101static int avr32_pm_valid_state(suspend_state_t state)
102{
103 switch (state) {
104 case PM_SUSPEND_ON:
105 case PM_SUSPEND_STANDBY:
106 case PM_SUSPEND_MEM:
107 return 1;
108
109 default:
110 return 0;
111 }
112}
113
114static int avr32_pm_enter(suspend_state_t state)
115{
116 u32 lpr_saved;
117 u32 evba_saved;
118 void *sram;
119
120 switch (state) {
121 case PM_SUSPEND_STANDBY:
122 sram = avr32_pm_map_sram();
123
124 /* Switch to in-sram exception handlers */
125 evba_saved = sysreg_read(EVBA);
126 sysreg_write(EVBA, (unsigned long)sram);
127
128 /*
129 * Save the LPR register so that we can re-enable
130 * SDRAM Low Power mode on resume.
131 */
132 lpr_saved = sdramc_readl(LPR);
133 pr_debug("%s: Entering standby...\n", __func__);
134 avr32_pm_enter_standby(SDRAMC_BASE);
135 sdramc_writel(LPR, lpr_saved);
136
137 /* Switch back to regular exception handlers */
138 sysreg_write(EVBA, evba_saved);
139
140 avr32_pm_unmap_sram();
141 break;
142
143 case PM_SUSPEND_MEM:
144 sram = avr32_pm_map_sram();
145
146 /* Switch to in-sram exception handlers */
147 evba_saved = sysreg_read(EVBA);
148 sysreg_write(EVBA, (unsigned long)sram);
149
150 /*
151 * Save the LPR register so that we can re-enable
152 * SDRAM Low Power mode on resume.
153 */
154 lpr_saved = sdramc_readl(LPR);
155 pr_debug("%s: Entering suspend-to-ram...\n", __func__);
156 avr32_pm_enter_str(SDRAMC_BASE);
157 sdramc_writel(LPR, lpr_saved);
158
159 /* Switch back to regular exception handlers */
160 sysreg_write(EVBA, evba_saved);
161
162 avr32_pm_unmap_sram();
163 break;
164
165 case PM_SUSPEND_ON:
166 pr_debug("%s: Entering idle...\n", __func__);
167 cpu_enter_idle();
168 break;
169
170 default:
171 pr_debug("%s: Invalid suspend state %d\n", __func__, state);
172 goto out;
173 }
174
175 pr_debug("%s: wakeup\n", __func__);
176
177out:
178 return 0;
179}
180
181static struct platform_suspend_ops avr32_pm_ops = {
182 .valid = avr32_pm_valid_state,
183 .enter = avr32_pm_enter,
184};
185
186static unsigned long avr32_pm_offset(void *symbol)
187{
188 extern u8 pm_exception[];
189
190 return (unsigned long)symbol - (unsigned long)pm_exception;
191}
192
193static int __init avr32_pm_init(void)
194{
195 extern u8 pm_exception[];
196 extern u8 pm_irq0[];
197 extern u8 pm_standby[];
198 extern u8 pm_suspend_to_ram[];
199 extern u8 pm_sram_end[];
200 void *dst;
201
202 /*
203 * To keep things simple, we depend on not needing more than a
204 * single page.
205 */
206 pm_sram_size = avr32_pm_offset(pm_sram_end);
207 if (pm_sram_size > PAGE_SIZE)
208 goto err;
209
210 pm_sram_start = sram_alloc(pm_sram_size);
211 if (!pm_sram_start)
212 goto err_alloc_sram;
213
214 /* Grab a virtual area we can use later on. */
215 pm_sram_area = get_vm_area(pm_sram_size, VM_IOREMAP);
216 if (!pm_sram_area)
217 goto err_vm_area;
218 pm_sram_area->phys_addr = pm_sram_start;
219
220 local_irq_disable();
221 dst = avr32_pm_map_sram();
222 memcpy(dst, pm_exception, pm_sram_size);
223 flush_dcache_region(dst, pm_sram_size);
224 invalidate_icache_region(dst, pm_sram_size);
225 avr32_pm_unmap_sram();
226 local_irq_enable();
227
228 avr32_pm_enter_standby = dst + avr32_pm_offset(pm_standby);
229 avr32_pm_enter_str = dst + avr32_pm_offset(pm_suspend_to_ram);
230 intc_set_suspend_handler(avr32_pm_offset(pm_irq0));
231
232 suspend_set_ops(&avr32_pm_ops);
233
234 printk("AVR32 AP Power Management enabled\n");
235
236 return 0;
237
238err_vm_area:
239 sram_free(pm_sram_start, pm_sram_size);
240err_alloc_sram:
241err:
242 pr_err("AVR32 Power Management initialization failed\n");
243 return -ENOMEM;
244}
245arch_initcall(avr32_pm_init);
diff --git a/arch/avr32/mach-at32ap/sdramc.h b/arch/avr32/mach-at32ap/sdramc.h
new file mode 100644
index 000000000000..66eeaed49073
--- /dev/null
+++ b/arch/avr32/mach-at32ap/sdramc.h
@@ -0,0 +1,76 @@
1/*
2 * Register definitions for the AT32AP SDRAM Controller
3 *
4 * Copyright (C) 2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 */
10
11/* Register offsets */
12#define SDRAMC_MR 0x0000
13#define SDRAMC_TR 0x0004
14#define SDRAMC_CR 0x0008
15#define SDRAMC_HSR 0x000c
16#define SDRAMC_LPR 0x0010
17#define SDRAMC_IER 0x0014
18#define SDRAMC_IDR 0x0018
19#define SDRAMC_IMR 0x001c
20#define SDRAMC_ISR 0x0020
21#define SDRAMC_MDR 0x0024
22
23/* MR - Mode Register */
24#define SDRAMC_MR_MODE_NORMAL ( 0 << 0)
25#define SDRAMC_MR_MODE_NOP ( 1 << 0)
26#define SDRAMC_MR_MODE_BANKS_PRECHARGE ( 2 << 0)
27#define SDRAMC_MR_MODE_LOAD_MODE ( 3 << 0)
28#define SDRAMC_MR_MODE_AUTO_REFRESH ( 4 << 0)
29#define SDRAMC_MR_MODE_EXT_LOAD_MODE ( 5 << 0)
30#define SDRAMC_MR_MODE_POWER_DOWN ( 6 << 0)
31
32/* CR - Configuration Register */
33#define SDRAMC_CR_NC_8_BITS ( 0 << 0)
34#define SDRAMC_CR_NC_9_BITS ( 1 << 0)
35#define SDRAMC_CR_NC_10_BITS ( 2 << 0)
36#define SDRAMC_CR_NC_11_BITS ( 3 << 0)
37#define SDRAMC_CR_NR_11_BITS ( 0 << 2)
38#define SDRAMC_CR_NR_12_BITS ( 1 << 2)
39#define SDRAMC_CR_NR_13_BITS ( 2 << 2)
40#define SDRAMC_CR_NB_2_BANKS ( 0 << 4)
41#define SDRAMC_CR_NB_4_BANKS ( 1 << 4)
42#define SDRAMC_CR_CAS(x) ((x) << 5)
43#define SDRAMC_CR_DBW_32_BITS ( 0 << 7)
44#define SDRAMC_CR_DBW_16_BITS ( 1 << 7)
45#define SDRAMC_CR_TWR(x) ((x) << 8)
46#define SDRAMC_CR_TRC(x) ((x) << 12)
47#define SDRAMC_CR_TRP(x) ((x) << 16)
48#define SDRAMC_CR_TRCD(x) ((x) << 20)
49#define SDRAMC_CR_TRAS(x) ((x) << 24)
50#define SDRAMC_CR_TXSR(x) ((x) << 28)
51
52/* HSR - High Speed Register */
53#define SDRAMC_HSR_DA ( 1 << 0)
54
55/* LPR - Low Power Register */
56#define SDRAMC_LPR_LPCB_INHIBIT ( 0 << 0)
57#define SDRAMC_LPR_LPCB_SELF_RFR ( 1 << 0)
58#define SDRAMC_LPR_LPCB_PDOWN ( 2 << 0)
59#define SDRAMC_LPR_LPCB_DEEP_PDOWN ( 3 << 0)
60#define SDRAMC_LPR_PASR(x) ((x) << 4)
61#define SDRAMC_LPR_TCSR(x) ((x) << 8)
62#define SDRAMC_LPR_DS(x) ((x) << 10)
63#define SDRAMC_LPR_TIMEOUT(x) ((x) << 12)
64
65/* IER/IDR/IMR/ISR - Interrupt Enable/Disable/Mask/Status Register */
66#define SDRAMC_ISR_RES ( 1 << 0)
67
68/* MDR - Memory Device Register */
69#define SDRAMC_MDR_MD_SDRAM ( 0 << 0)
70#define SDRAMC_MDR_MD_LOW_PWR_SDRAM ( 1 << 0)
71
72/* Register access macros */
73#define sdramc_readl(reg) \
74 __raw_readl((void __iomem __force *)SDRAMC_BASE + SDRAMC_##reg)
75#define sdramc_writel(reg, value) \
76 __raw_writel(value, (void __iomem __force *)SDRAMC_BASE + SDRAMC_##reg)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-06 19:37:39 -0500