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authorHaavard Skinnemoen <hskinnemoen@atmel.com>2006-09-26 02:32:13 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-09-26 11:48:54 -0400
commit5f97f7f9400de47ae837170bb274e90ad3934386 (patch)
tree514451e6dc6b46253293a00035d375e77b1c65ed /arch/avr32/mach-at32ap/pio.h
parent53e62d3aaa60590d4a69b4e07c29f448b5151047 (diff)
[PATCH] avr32 architecture
This adds support for the Atmel AVR32 architecture as well as the AT32AP7000 CPU and the AT32STK1000 development board. AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption and high code density. The AVR32 architecture is not binary compatible with earlier 8-bit AVR architectures. The AVR32 architecture, including the instruction set, is described by the AVR32 Architecture Manual, available from http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf The Atmel AT32AP7000 is the first CPU implementing the AVR32 architecture. It features a 7-stage pipeline, 16KB instruction and data caches and a full Memory Management Unit. It also comes with a large set of integrated peripherals, many of which are shared with the AT91 ARM-based controllers from Atmel. Full data sheet is available from http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf while the CPU core implementation including caches and MMU is documented by the AVR32 AP Technical Reference, available from http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf Information about the AT32STK1000 development board can be found at http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3918 including a BSP CD image with an earlier version of this patch, development tools (binaries and source/patches) and a root filesystem image suitable for booting from SD card. Alternatively, there's a preliminary "getting started" guide available at http://avr32linux.org/twiki/bin/view/Main/GettingStarted which provides links to the sources and patches you will need in order to set up a cross-compiling environment for avr32-linux. This patch, as well as the other patches included with the BSP and the toolchain patches, is actively supported by Atmel Corporation. [dmccr@us.ibm.com: Fix more pxx_page macro locations] [bunk@stusta.de: fix `make defconfig'] Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: Dave McCracken <dmccr@us.ibm.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/avr32/mach-at32ap/pio.h')
-rw-r--r--arch/avr32/mach-at32ap/pio.h178
1 files changed, 178 insertions, 0 deletions
diff --git a/arch/avr32/mach-at32ap/pio.h b/arch/avr32/mach-at32ap/pio.h
new file mode 100644
index 000000000000..cfea12351599
--- /dev/null
+++ b/arch/avr32/mach-at32ap/pio.h
@@ -0,0 +1,178 @@
1/*
2 * Atmel PIO2 Port Multiplexer support
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef __ARCH_AVR32_AT32AP_PIO_H__
11#define __ARCH_AVR32_AT32AP_PIO_H__
12
13/* PIO register offsets */
14#define PIO_PER 0x0000
15#define PIO_PDR 0x0004
16#define PIO_PSR 0x0008
17#define PIO_OER 0x0010
18#define PIO_ODR 0x0014
19#define PIO_OSR 0x0018
20#define PIO_IFER 0x0020
21#define PIO_IFDR 0x0024
22#define PIO_ISFR 0x0028
23#define PIO_SODR 0x0030
24#define PIO_CODR 0x0034
25#define PIO_ODSR 0x0038
26#define PIO_PDSR 0x003c
27#define PIO_IER 0x0040
28#define PIO_IDR 0x0044
29#define PIO_IMR 0x0048
30#define PIO_ISR 0x004c
31#define PIO_MDER 0x0050
32#define PIO_MDDR 0x0054
33#define PIO_MDSR 0x0058
34#define PIO_PUDR 0x0060
35#define PIO_PUER 0x0064
36#define PIO_PUSR 0x0068
37#define PIO_ASR 0x0070
38#define PIO_BSR 0x0074
39#define PIO_ABSR 0x0078
40#define PIO_OWER 0x00a0
41#define PIO_OWDR 0x00a4
42#define PIO_OWSR 0x00a8
43
44/* Bitfields in PER */
45
46/* Bitfields in PDR */
47
48/* Bitfields in PSR */
49
50/* Bitfields in OER */
51
52/* Bitfields in ODR */
53
54/* Bitfields in OSR */
55
56/* Bitfields in IFER */
57
58/* Bitfields in IFDR */
59
60/* Bitfields in ISFR */
61
62/* Bitfields in SODR */
63
64/* Bitfields in CODR */
65
66/* Bitfields in ODSR */
67
68/* Bitfields in PDSR */
69
70/* Bitfields in IER */
71
72/* Bitfields in IDR */
73
74/* Bitfields in IMR */
75
76/* Bitfields in ISR */
77
78/* Bitfields in MDER */
79
80/* Bitfields in MDDR */
81
82/* Bitfields in MDSR */
83
84/* Bitfields in PUDR */
85
86/* Bitfields in PUER */
87
88/* Bitfields in PUSR */
89
90/* Bitfields in ASR */
91
92/* Bitfields in BSR */
93
94/* Bitfields in ABSR */
95#define PIO_P0_OFFSET 0
96#define PIO_P0_SIZE 1
97#define PIO_P1_OFFSET 1
98#define PIO_P1_SIZE 1
99#define PIO_P2_OFFSET 2
100#define PIO_P2_SIZE 1
101#define PIO_P3_OFFSET 3
102#define PIO_P3_SIZE 1
103#define PIO_P4_OFFSET 4
104#define PIO_P4_SIZE 1
105#define PIO_P5_OFFSET 5
106#define PIO_P5_SIZE 1
107#define PIO_P6_OFFSET 6
108#define PIO_P6_SIZE 1
109#define PIO_P7_OFFSET 7
110#define PIO_P7_SIZE 1
111#define PIO_P8_OFFSET 8
112#define PIO_P8_SIZE 1
113#define PIO_P9_OFFSET 9
114#define PIO_P9_SIZE 1
115#define PIO_P10_OFFSET 10
116#define PIO_P10_SIZE 1
117#define PIO_P11_OFFSET 11
118#define PIO_P11_SIZE 1
119#define PIO_P12_OFFSET 12
120#define PIO_P12_SIZE 1
121#define PIO_P13_OFFSET 13
122#define PIO_P13_SIZE 1
123#define PIO_P14_OFFSET 14
124#define PIO_P14_SIZE 1
125#define PIO_P15_OFFSET 15
126#define PIO_P15_SIZE 1
127#define PIO_P16_OFFSET 16
128#define PIO_P16_SIZE 1
129#define PIO_P17_OFFSET 17
130#define PIO_P17_SIZE 1
131#define PIO_P18_OFFSET 18
132#define PIO_P18_SIZE 1
133#define PIO_P19_OFFSET 19
134#define PIO_P19_SIZE 1
135#define PIO_P20_OFFSET 20
136#define PIO_P20_SIZE 1
137#define PIO_P21_OFFSET 21
138#define PIO_P21_SIZE 1
139#define PIO_P22_OFFSET 22
140#define PIO_P22_SIZE 1
141#define PIO_P23_OFFSET 23
142#define PIO_P23_SIZE 1
143#define PIO_P24_OFFSET 24
144#define PIO_P24_SIZE 1
145#define PIO_P25_OFFSET 25
146#define PIO_P25_SIZE 1
147#define PIO_P26_OFFSET 26
148#define PIO_P26_SIZE 1
149#define PIO_P27_OFFSET 27
150#define PIO_P27_SIZE 1
151#define PIO_P28_OFFSET 28
152#define PIO_P28_SIZE 1
153#define PIO_P29_OFFSET 29
154#define PIO_P29_SIZE 1
155#define PIO_P30_OFFSET 30
156#define PIO_P30_SIZE 1
157#define PIO_P31_OFFSET 31
158#define PIO_P31_SIZE 1
159
160/* Bitfields in OWER */
161
162/* Bitfields in OWDR */
163
164/* Bitfields in OWSR */
165
166/* Bit manipulation macros */
167#define PIO_BIT(name) (1 << PIO_##name##_OFFSET)
168#define PIO_BF(name,value) (((value) & ((1 << PIO_##name##_SIZE) - 1)) << PIO_##name##_OFFSET)
169#define PIO_BFEXT(name,value) (((value) >> PIO_##name##_OFFSET) & ((1 << PIO_##name##_SIZE) - 1))
170#define PIO_BFINS(name,value,old) (((old) & ~(((1 << PIO_##name##_SIZE) - 1) << PIO_##name##_OFFSET)) | PIO_BF(name,value))
171
172/* Register access macros */
173#define pio_readl(port,reg) readl((port)->regs + PIO_##reg)
174#define pio_writel(port,reg,value) writel((value), (port)->regs + PIO_##reg)
175
176void at32_init_pio(struct platform_device *pdev);
177
178#endif /* __ARCH_AVR32_AT32AP_PIO_H__ */