[PATCH] avr32 architecture

This adds support for the Atmel AVR32 architecture as well as the AT32AP7000
CPU and the AT32STK1000 development board.

AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for
cost-sensitive embedded applications, with particular emphasis on low power
consumption and high code density.  The AVR32 architecture is not binary
compatible with earlier 8-bit AVR architectures.

The AVR32 architecture, including the instruction set, is described by the
AVR32 Architecture Manual, available from

http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf

The Atmel AT32AP7000 is the first CPU implementing the AVR32 architecture.  It
features a 7-stage pipeline, 16KB instruction and data caches and a full
Memory Management Unit.  It also comes with a large set of integrated
peripherals, many of which are shared with the AT91 ARM-based controllers from
Atmel.

Full data sheet is available from

http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf

while the CPU core implementation including caches and MMU is documented by
the AVR32 AP Technical Reference, available from

http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf

Information about the AT32STK1000 development board can be found at

http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3918

including a BSP CD image with an earlier version of this patch, development
tools (binaries and source/patches) and a root filesystem image suitable for
booting from SD card.

Alternatively, there's a preliminary "getting started" guide available at
http://avr32linux.org/twiki/bin/view/Main/GettingStarted which provides links
to the sources and patches you will need in order to set up a cross-compiling
environment for avr32-linux.

This patch, as well as the other patches included with the BSP and the
toolchain patches, is actively supported by Atmel Corporation.

[dmccr@us.ibm.com: Fix more pxx_page macro locations]
[bunk@stusta.de: fix `make defconfig']
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
Signed-off-by: Dave McCracken <dmccr@us.ibm.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

1 files changed, 133 insertions, 0 deletions

diff --git a/arch/avr32/mach-at32ap/intc.c b/arch/avr32/mach-at32ap/intc.c
new file mode 100644
index 000000000000..74f8c9f2f03d
--- /dev/null
+++ b/arch/avr32/mach-at32ap/intc.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+
+#include <asm/io.h>
+
+#include "intc.h"
+
+struct intc {
+        void __iomem    *regs;
+        struct irq_chip chip;
+};
+
+extern struct platform_device at32_intc0_device;
+
+/*
+ * TODO: We may be able to implement mask/unmask by setting IxM flags
+ * in the status register.
+ */
+static void intc_mask_irq(unsigned int irq)
+{
+
+}
+
+static void intc_unmask_irq(unsigned int irq)
+{
+
+}
+
+static struct intc intc0 = {
+        .chip = {
+                .name           = "intc",
+                .mask           = intc_mask_irq,
+                .unmask         = intc_unmask_irq,
+        },
+};
+
+/*
+ * All interrupts go via intc at some point.
+ */
+asmlinkage void do_IRQ(int level, struct pt_regs *regs)
+{
+        struct irq_desc *desc;
+        unsigned int irq;
+        unsigned long status_reg;
+
+        local_irq_disable();
+
+        irq_enter();
+
+        irq = intc_readl(&intc0, INTCAUSE0 - 4 * level);
+        desc = irq_desc + irq;
+        desc->handle_irq(irq, desc, regs);
+
+        /*
+         * Clear all interrupt level masks so that we may handle
+         * interrupts during softirq processing.  If this is a nested
+         * interrupt, interrupts must stay globally disabled until we
+         * return.
+         */
+        status_reg = sysreg_read(SR);
+        status_reg &= ~(SYSREG_BIT(I0M) | SYSREG_BIT(I1M)
+                        | SYSREG_BIT(I2M) | SYSREG_BIT(I3M));
+        sysreg_write(SR, status_reg);
+
+        irq_exit();
+}
+
+void __init init_IRQ(void)
+{
+        extern void _evba(void);
+        extern void irq_level0(void);
+        struct resource *regs;
+        struct clk *pclk;
+        unsigned int i;
+        u32 offset, readback;
+
+        regs = platform_get_resource(&at32_intc0_device, IORESOURCE_MEM, 0);
+        if (!regs) {
+                printk(KERN_EMERG "intc: no mmio resource defined\n");
+                goto fail;
+        }
+        pclk = clk_get(&at32_intc0_device.dev, "pclk");
+        if (IS_ERR(pclk)) {
+                printk(KERN_EMERG "intc: no clock defined\n");
+                goto fail;
+        }
+
+        clk_enable(pclk);
+
+        intc0.regs = ioremap(regs->start, regs->end - regs->start + 1);
+        if (!intc0.regs) {
+                printk(KERN_EMERG "intc: failed to map registers (0x%08lx)\n",
+                       (unsigned long)regs->start);
+                goto fail;
+        }
+
+        /*
+         * Initialize all interrupts to level 0 (lowest priority). The
+         * priority level may be changed by calling
+         * irq_set_priority().
+         *
+         */
+        offset = (unsigned long)&irq_level0 - (unsigned long)&_evba;
+        for (i = 0; i < NR_INTERNAL_IRQS; i++) {
+                intc_writel(&intc0, INTPR0 + 4 * i, offset);
+                readback = intc_readl(&intc0, INTPR0 + 4 * i);
+                if (readback == offset)
+                        set_irq_chip_and_handler(i, &intc0.chip,
+                                                 handle_simple_irq);
+        }
+
+        /* Unmask all interrupt levels */
+        sysreg_write(SR, (sysreg_read(SR)
+                          & ~(SR_I3M | SR_I2M | SR_I1M | SR_I0M)));
+
+        return;
+
+fail:
+        panic("Interrupt controller initialization failed!\n");
+}
+