[PATCH] avr32 architecture

This adds support for the Atmel AVR32 architecture as well as the AT32AP7000
CPU and the AT32STK1000 development board.

AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for
cost-sensitive embedded applications, with particular emphasis on low power
consumption and high code density.  The AVR32 architecture is not binary
compatible with earlier 8-bit AVR architectures.

The AVR32 architecture, including the instruction set, is described by the
AVR32 Architecture Manual, available from

http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf

The Atmel AT32AP7000 is the first CPU implementing the AVR32 architecture.  It
features a 7-stage pipeline, 16KB instruction and data caches and a full
Memory Management Unit.  It also comes with a large set of integrated
peripherals, many of which are shared with the AT91 ARM-based controllers from
Atmel.

Full data sheet is available from

http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf

while the CPU core implementation including caches and MMU is documented by
the AVR32 AP Technical Reference, available from

http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf

Information about the AT32STK1000 development board can be found at

http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3918

including a BSP CD image with an earlier version of this patch, development
tools (binaries and source/patches) and a root filesystem image suitable for
booting from SD card.

Alternatively, there's a preliminary "getting started" guide available at
http://avr32linux.org/twiki/bin/view/Main/GettingStarted which provides links
to the sources and patches you will need in order to set up a cross-compiling
environment for avr32-linux.

This patch, as well as the other patches included with the BSP and the
toolchain patches, is actively supported by Atmel Corporation.

[dmccr@us.ibm.com: Fix more pxx_page macro locations]
[bunk@stusta.de: fix `make defconfig']
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
Signed-off-by: Dave McCracken <dmccr@us.ibm.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

1 files changed, 171 insertions, 0 deletions

diff --git a/arch/avr32/mach-at32ap/extint.c b/arch/avr32/mach-at32ap/extint.c
new file mode 100644
index 000000000000..7da9c5f7a0eb
--- /dev/null
+++ b/arch/avr32/mach-at32ap/extint.c
@@ -0,0 +1,171 @@
+/*
+ * External interrupt handling for AT32AP CPUs
+ *
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/random.h>
+
+#include <asm/io.h>
+
+#include <asm/arch/sm.h>
+
+#include "sm.h"
+
+static void eim_ack_irq(unsigned int irq)
+{
+        struct at32_sm *sm = get_irq_chip_data(irq);
+        sm_writel(sm, EIM_ICR, 1 << (irq - sm->eim_first_irq));
+}
+
+static void eim_mask_irq(unsigned int irq)
+{
+        struct at32_sm *sm = get_irq_chip_data(irq);
+        sm_writel(sm, EIM_IDR, 1 << (irq - sm->eim_first_irq));
+}
+
+static void eim_mask_ack_irq(unsigned int irq)
+{
+        struct at32_sm *sm = get_irq_chip_data(irq);
+        sm_writel(sm, EIM_ICR, 1 << (irq - sm->eim_first_irq));
+        sm_writel(sm, EIM_IDR, 1 << (irq - sm->eim_first_irq));
+}
+
+static void eim_unmask_irq(unsigned int irq)
+{
+        struct at32_sm *sm = get_irq_chip_data(irq);
+        sm_writel(sm, EIM_IER, 1 << (irq - sm->eim_first_irq));
+}
+
+static int eim_set_irq_type(unsigned int irq, unsigned int flow_type)
+{
+        struct at32_sm *sm = get_irq_chip_data(irq);
+        unsigned int i = irq - sm->eim_first_irq;
+        u32 mode, edge, level;
+        unsigned long flags;
+        int ret = 0;
+
+        flow_type &= IRQ_TYPE_SENSE_MASK;
+
+        spin_lock_irqsave(&sm->lock, flags);
+
+        mode = sm_readl(sm, EIM_MODE);
+        edge = sm_readl(sm, EIM_EDGE);
+        level = sm_readl(sm, EIM_LEVEL);
+
+        switch (flow_type) {
+        case IRQ_TYPE_LEVEL_LOW:
+                mode |= 1 << i;
+                level &= ~(1 << i);
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                mode |= 1 << i;
+                level |= 1 << i;
+                break;
+        case IRQ_TYPE_EDGE_RISING:
+                mode &= ~(1 << i);
+                edge |= 1 << i;
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                mode &= ~(1 << i);
+                edge &= ~(1 << i);
+                break;
+        default:
+                ret = -EINVAL;
+                break;
+        }
+
+        sm_writel(sm, EIM_MODE, mode);
+        sm_writel(sm, EIM_EDGE, edge);
+        sm_writel(sm, EIM_LEVEL, level);
+
+        spin_unlock_irqrestore(&sm->lock, flags);
+
+        return ret;
+}
+
+struct irq_chip eim_chip = {
+        .name           = "eim",
+        .ack            = eim_ack_irq,
+        .mask           = eim_mask_irq,
+        .mask_ack       = eim_mask_ack_irq,
+        .unmask         = eim_unmask_irq,
+        .set_type       = eim_set_irq_type,
+};
+
+static void demux_eim_irq(unsigned int irq, struct irq_desc *desc,
+                          struct pt_regs *regs)
+{
+        struct at32_sm *sm = desc->handler_data;
+        struct irq_desc *ext_desc;
+        unsigned long status, pending;
+        unsigned int i, ext_irq;
+
+        spin_lock(&sm->lock);
+
+        status = sm_readl(sm, EIM_ISR);
+        pending = status & sm_readl(sm, EIM_IMR);
+
+        while (pending) {
+                i = fls(pending) - 1;
+                pending &= ~(1 << i);
+
+                ext_irq = i + sm->eim_first_irq;
+                ext_desc = irq_desc + ext_irq;
+                ext_desc->handle_irq(ext_irq, ext_desc, regs);
+        }
+
+        spin_unlock(&sm->lock);
+}
+
+static int __init eim_init(void)
+{
+        struct at32_sm *sm = &system_manager;
+        unsigned int i;
+        unsigned int nr_irqs;
+        unsigned int int_irq;
+        u32 pattern;
+
+        /*
+         * The EIM is really the same module as SM, so register
+         * mapping, etc. has been taken care of already.
+         */
+
+        /*
+         * Find out how many interrupt lines that are actually
+         * implemented in hardware.
+         */
+        sm_writel(sm, EIM_IDR, ~0UL);
+        sm_writel(sm, EIM_MODE, ~0UL);
+        pattern = sm_readl(sm, EIM_MODE);
+        nr_irqs = fls(pattern);
+
+        sm->eim_chip = &eim_chip;
+
+        for (i = 0; i < nr_irqs; i++) {
+                set_irq_chip(sm->eim_first_irq + i, &eim_chip);
+                set_irq_chip_data(sm->eim_first_irq + i, sm);
+        }
+
+        int_irq = platform_get_irq_byname(sm->pdev, "eim");
+
+        set_irq_chained_handler(int_irq, demux_eim_irq);
+        set_irq_data(int_irq, sm);
+
+        printk("EIM: External Interrupt Module at 0x%p, IRQ %u\n",
+               sm->regs, int_irq);
+        printk("EIM: Handling %u external IRQs, starting with IRQ %u\n",
+               nr_irqs, sm->eim_first_irq);
+
+        return 0;
+}
+arch_initcall(eim_init);