avr32: Store virtual addresses in the PGD

Instead of storing physical addresses along with page flags in the
PGD, store virtual addresses and use NULL to indicate a not present
second-level page table. A non-page-aligned page table indicates a bad
PMD.

This simplifies the TLB miss handler since it no longer has to check
the Present bit and no longer has to convert the PGD entry from
physical to virtual address. Instead, it has to check for a NULL
entry, which is slightly cheaper than either.

Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>

2 files changed, 24 insertions, 25 deletions

diff --git a/arch/avr32/kernel/entry-avr32b.S b/arch/avr32/kernel/entry-avr32b.S
index 050c006a7f0c..3cdd7071f35e 100644
--- a/arch/avr32/kernel/entry-avr32b.S
+++ b/arch/avr32/kernel/entry-avr32b.S
@@ -74,12 +74,6 @@ exception_vectors:
         .align  2
         bral    do_dtlb_modified
 
-        /*
-         * r0 : PGD/PT/PTE
-         * r1 : Offending address
-         * r2 : Scratch register
-         * r3 : Cause (5, 12 or 13)
-         */
 #define tlbmiss_save    pushm   r0-r3
 #define tlbmiss_restore popm    r0-r3
 
@@ -108,17 +102,17 @@ tlb_miss_common:
         bld     r0, 31
         brcs    handle_vmalloc_miss
 
-        /* First level lookup */
+        /*
+         * First level lookup: The PGD contains virtual pointers to
+         * the second-level page tables, but they may be NULL if not
+         * present.
+         */
 pgtbl_lookup:
         lsr     r2, r0, PGDIR_SHIFT
         ld.w    r3, r1[r2 << 2]
         bfextu  r1, r0, PAGE_SHIFT, PGDIR_SHIFT - PAGE_SHIFT
-        bld     r3, _PAGE_BIT_PRESENT
-        brcc    page_table_not_present
-
-        /* Translate to virtual address in P1. */
-        andl    r3, 0xf000
-        sbr     r3, 31
+        cp.w    r3, 0
+        breq    page_table_not_present
 
         /* Second level lookup */
         ld.w    r2, r3[r1 << 2]
@@ -155,6 +149,19 @@ handle_vmalloc_miss:
         orh     r1, hi(swapper_pg_dir)
         rjmp    pgtbl_lookup
 
+        /* The slow path of the TLB miss handler */
+        .align  2
+page_table_not_present:
+page_not_present:
+        tlbmiss_restore
+        sub     sp, 4
+        stmts   --sp, r0-lr
+        rcall   save_full_context_ex
+        mfsr    r12, SYSREG_ECR
+        mov     r11, sp
+        rcall   do_page_fault
+        rjmp    ret_from_exception
+
 
         /* ---                    System Call                    --- */
 
@@ -267,18 +274,6 @@ syscall_exit_work:
         brcc    syscall_exit_cont
         rjmp    enter_monitor_mode
 
-        /* The slow path of the TLB miss handler */
-page_table_not_present:
-page_not_present:
-        tlbmiss_restore
-        sub     sp, 4
-        stmts   --sp, r0-lr
-        rcall   save_full_context_ex
-        mfsr    r12, SYSREG_ECR
-        mov     r11, sp
-        rcall   do_page_fault
-        rjmp    ret_from_exception
-
         /* This function expects to find offending PC in SYSREG_RAR_EX */
         .type   save_full_context_ex, @function
         .align  2
diff --git a/arch/avr32/kernel/vmlinux.lds.S b/arch/avr32/kernel/vmlinux.lds.S
index 033dd46bfa62..5d25d8eeb750 100644
--- a/arch/avr32/kernel/vmlinux.lds.S
+++ b/arch/avr32/kernel/vmlinux.lds.S
@@ -99,6 +99,10 @@ SECTIONS
                  */
                 *(.data.init_task)
 
+                /* Then, the page-aligned data */
+                . = ALIGN(PAGE_SIZE);
+                *(.data.page_aligned)
+
                 /* Then, the cacheline aligned data */
                 . = ALIGN(L1_CACHE_BYTES);
                 *(.data.cacheline_aligned)