Merge git://git.kernel.org/pub/scm/linux/kernel/git/hskinnemoen/avr32-2.6

* git://git.kernel.org/pub/scm/linux/kernel/git/hskinnemoen/avr32-2.6: (31 commits)
  avr32: Fix typo of IFSR in a comment in the PIO header file
  avr32: Power Management support ("standby" and "mem" modes)
  avr32: Add system device for the internal interrupt controller (intc)
  avr32: Add simple SRAM allocator
  avr32: Enable SDRAMC clock at startup
  rtc-at32ap700x: Enable wakeup
  macb: Basic suspend/resume support
  atmel_serial: Drain console TX shifter before suspending
  atmel_serial: Fix build on avr32 with CONFIG_PM enabled
  avr32: Use a quicklist for PTE allocation as well
  avr32: Use a quicklist for PGD allocation
  avr32: Cover the kernel page tables in the user PGDs
  avr32: Store virtual addresses in the PGD
  avr32: Remove useless zeroing of swapper_pg_dir at startup
  avr32: Clean up and optimize the TLB operations
  avr32: Rename at32ap.c -> pdc.c
  avr32: Move setup_platform() into chip-specific file
  avr32: Kill special exception handler sections
  avr32: Kill unneeded #include <asm/pgalloc.h> from asm/mmu_context.h
  avr32: Clean up time.c #includes
  ...

1 files changed, 4 insertions, 8 deletions

diff --git a/arch/avr32/kernel/vmlinux.lds.S b/arch/avr32/kernel/vmlinux.lds.S
index 481cfd40c053..5d25d8eeb750 100644
--- a/arch/avr32/kernel/vmlinux.lds.S
+++ b/arch/avr32/kernel/vmlinux.lds.S
@@ -68,14 +68,6 @@ SECTIONS
                 _evba = .;
                 _text = .;
                 *(.ex.text)
-                . = 0x50;
-                *(.tlbx.ex.text)
-                . = 0x60;
-                *(.tlbr.ex.text)
-                . = 0x70;
-                *(.tlbw.ex.text)
-                . = 0x100;
-                *(.scall.text)
                 *(.irq.text)
                 KPROBES_TEXT
                 TEXT_TEXT
@@ -107,6 +99,10 @@ SECTIONS
                  */
                 *(.data.init_task)
 
+                /* Then, the page-aligned data */
+                . = ALIGN(PAGE_SIZE);
+                *(.data.page_aligned)
+
                 /* Then, the cacheline aligned data */
                 . = ALIGN(L1_CACHE_BYTES);
                 *(.data.cacheline_aligned)