avr32: Store virtual addresses in the PGD

Instead of storing physical addresses along with page flags in the
PGD, store virtual addresses and use NULL to indicate a not present
second-level page table. A non-page-aligned page table indicates a bad
PMD.

This simplifies the TLB miss handler since it no longer has to check
the Present bit and no longer has to convert the PGD entry from
physical to virtual address. Instead, it has to check for a NULL
entry, which is slightly cheaper than either.

Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>

1 files changed, 4 insertions, 0 deletions

diff --git a/arch/avr32/kernel/vmlinux.lds.S b/arch/avr32/kernel/vmlinux.lds.S
index 033dd46bfa62..5d25d8eeb750 100644
--- a/arch/avr32/kernel/vmlinux.lds.S
+++ b/arch/avr32/kernel/vmlinux.lds.S
@@ -99,6 +99,10 @@ SECTIONS
                  */
                 *(.data.init_task)
 
+                /* Then, the page-aligned data */
+                . = ALIGN(PAGE_SIZE);
+                *(.data.page_aligned)
+
                 /* Then, the cacheline aligned data */
                 . = ALIGN(L1_CACHE_BYTES);
                 *(.data.cacheline_aligned)