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authorAlex Raimondi <mailinglist@miromico.ch>2008-12-09 10:17:13 -0500
committerHaavard Skinnemoen <haavard.skinnemoen@atmel.com>2009-01-05 09:52:04 -0500
commitdd5e1339e528197abdb7827663ff0673797fa088 (patch)
tree0cd6eeffbd2c817020a9ef1f1795a31f5c7328d9 /arch/avr32/Kconfig
parentbc08969fe638bb164915aadd1dc1a21194847000 (diff)
avr32: Hammerhead board support
The Hammerhead platform is built around a AVR32 32-bit microcontroller from Atmel. It offers versatile peripherals, such as ethernet, usb device, usb host etc. The board also incooperates a power supply and is a Power over Ethernet (PoE) Powered Device (PD). Additonally, a Cyclone III FPGA from Altera is integrated on the board. The FPGA is mapped into the 32-bit AVR memory bus. The FPGA offers two DDR2 SDRAM interfaces, which will cover even the most exceptional need of memory bandwidth. Together with the onboard video decoder the board is ready for video processing. This patch does include the basic support for the fpga device driver, but not the device driver itself. Signed-off-by: Alex Raimondi <mailinglist@miromico.ch> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Diffstat (limited to 'arch/avr32/Kconfig')
-rw-r--r--arch/avr32/Kconfig19
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
index 26eca87f6735..b189680d18b0 100644
--- a/arch/avr32/Kconfig
+++ b/arch/avr32/Kconfig
@@ -122,6 +122,24 @@ config BOARD_ATNGW100
122 bool "ATNGW100 Network Gateway" 122 bool "ATNGW100 Network Gateway"
123 select CPU_AT32AP7000 123 select CPU_AT32AP7000
124 124
125config BOARD_HAMMERHEAD
126 bool "Hammerhead board"
127 select CPU_AT32AP7000
128 select USB_ARCH_HAS_HCD
129 help
130 The Hammerhead platform is built around a AVR32 32-bit microcontroller from Atmel.
131 It offers versatile peripherals, such as ethernet, usb device, usb host etc.
132
133 The board also incooperates a power supply and is a Power over Ethernet (PoE) Powered
134 Device (PD).
135
136 Additonally, a Cyclone III FPGA from Altera is integrated on the board. The FPGA is
137 mapped into the 32-bit AVR memory bus. The FPGA offers two DDR2 SDRAM interfaces, which
138 will cover even the most exceptional need of memory bandwidth. Together with the onboard
139 video decoder the board is ready for video processing.
140
141 For more information see: http://www.miromico.com/hammerhead
142
125config BOARD_FAVR_32 143config BOARD_FAVR_32
126 bool "Favr-32 LCD-board" 144 bool "Favr-32 LCD-board"
127 select CPU_AT32AP7000 145 select CPU_AT32AP7000
@@ -133,6 +151,7 @@ endchoice
133 151
134source "arch/avr32/boards/atstk1000/Kconfig" 152source "arch/avr32/boards/atstk1000/Kconfig"
135source "arch/avr32/boards/atngw100/Kconfig" 153source "arch/avr32/boards/atngw100/Kconfig"
154source "arch/avr32/boards/hammerhead/Kconfig"
136source "arch/avr32/boards/favr-32/Kconfig" 155source "arch/avr32/boards/favr-32/Kconfig"
137 156
138choice 157choice