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authorOlof Johansson <olof@lixom.net>2014-07-19 18:03:08 -0400
committerOlof Johansson <olof@lixom.net>2014-07-19 18:03:08 -0400
commitf37ac9e5a47d72eab5185b0ddc14dfc943cc9589 (patch)
tree53577aa529e3bbe718459d0626fc6d45ada3dcdd /arch/arm
parent4338925434e4bf5ff714055713f3fb9b5fae9037 (diff)
parentfc2cac41ebbfb16da8b036cba6ec6714ab780a6d (diff)
Merge tag 'exynos-cpuidle' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc
Merge "Samsung exynos cpuidle update for v3.17" from Kukjin Kim: - add callbacks exynos_suspend() and exynos_powered_up() for support cpuidle through mcpm - skip exynos_cpuidle for exynos5420 because is uses cpuidle-big-liggle generic cpuidle driver - add generic functions to calculate cpu number is used for pmu and this is required for exynos5420 multi-cluster - add of_device_id structure for big.LITTLE cpuidle and add "samsung,exynos5420" compatible string for exynos5420 * tag 'exynos-cpuidle' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: EXYNOS: populate suspend and powered_up callbacks for mcpm ARM: EXYNOS: do not allow cpuidle registration for exynos5420 cpuidle: big.LITTLE: init driver for exynos5420 cpuidle: big.LITTLE: Add ARCH_EXYNOS entry in config ARM: EXYNOS: add generic function to calculate cpu number cpuidle: big.LITTLE: add of_device_id structure + Linux 3.16-rc5 Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/am335x-evm.dts4
-rw-r--r--arch/arm/boot/dts/am335x-evmsk.dts4
-rw-r--r--arch/arm/boot/dts/am335x-igep0033.dtsi6
-rw-r--r--arch/arm/boot/dts/am43x-epos-evm.dts4
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi2
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts1
-rw-r--r--arch/arm/boot/dts/dra7.dtsi12
-rw-r--r--arch/arm/boot/dts/dra7xx-clocks.dtsi26
-rw-r--r--arch/arm/boot/dts/exynos4.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi5
-rw-r--r--arch/arm/boot/dts/omap3-beagle-xm.dts6
-rw-r--r--arch/arm/boot/dts/omap3-evm-common.dtsi7
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts5
-rw-r--r--arch/arm/boot/dts/omap5.dtsi1
-rw-r--r--arch/arm/configs/bcm_defconfig2
-rw-r--r--arch/arm/configs/multi_v7_defconfig3
-rw-r--r--arch/arm/kernel/kprobes-test-arm.c30
-rw-r--r--arch/arm/kernel/kprobes-test.c10
-rw-r--r--arch/arm/kernel/probes-arm.c6
-rw-r--r--arch/arm/mach-exynos/exynos.c12
-rw-r--r--arch/arm/mach-exynos/firmware.c9
-rw-r--r--arch/arm/mach-exynos/mcpm-exynos.c36
-rw-r--r--arch/arm/mach-exynos/pm_domains.c61
-rw-r--r--arch/arm/mach-exynos/regs-pmu.h9
-rw-r--r--arch/arm/mach-imx/clk-gate2.c31
-rw-r--r--arch/arm/mach-mvebu/Makefile2
-rw-r--r--arch/arm/mach-mvebu/board-v7.c29
-rw-r--r--arch/arm/mach-mvebu/pmsu.c9
-rw-r--r--arch/arm/mach-mvebu/pmsu_ll.S25
-rw-r--r--arch/arm/mach-omap2/Makefile6
-rw-r--r--arch/arm/mach-omap2/clkt_dpll.c2
-rw-r--r--arch/arm/mach-omap2/cm-regbits-34xx.h3
-rw-r--r--arch/arm/mach-omap2/cm33xx.h2
-rw-r--r--arch/arm/mach-omap2/common.h4
-rw-r--r--arch/arm/mach-omap2/devices.c28
-rw-r--r--arch/arm/mach-omap2/dsp.c10
-rw-r--r--arch/arm/mach-omap2/gpmc.c2
-rw-r--r--arch/arm/mach-omap2/id.c12
-rw-r--r--arch/arm/mach-omap2/mux.c6
-rw-r--r--arch/arm/mach-omap2/omap4-common.c20
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c6
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_54xx_data.c73
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_7xx_data.c18
-rw-r--r--arch/arm/mach-omap2/prm-regbits-34xx.h6
-rw-r--r--arch/arm/mach-omap2/soc.h1
-rw-r--r--arch/arm/mach-sunxi/sunxi.c77
-rw-r--r--arch/arm/mm/cache-l2x0.c2
47 files changed, 501 insertions, 136 deletions
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index ecb267767cf5..e2156a583de7 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -529,8 +529,8 @@
529 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 529 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
530 0 0 1 2 530 0 0 1 2
531 >; 531 >;
532 tx-num-evt = <1>; 532 tx-num-evt = <32>;
533 rx-num-evt = <1>; 533 rx-num-evt = <32>;
534}; 534};
535 535
536&tps { 536&tps {
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index ab9a34ce524c..80a3b215e7d6 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -560,8 +560,8 @@
560 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 560 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
561 0 0 1 2 561 0 0 1 2
562 >; 562 >;
563 tx-num-evt = <1>; 563 tx-num-evt = <32>;
564 rx-num-evt = <1>; 564 rx-num-evt = <32>;
565}; 565};
566 566
567&tscadc { 567&tscadc {
diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi
index 8a0a72dc7dd7..a1a0cc5eb35c 100644
--- a/arch/arm/boot/dts/am335x-igep0033.dtsi
+++ b/arch/arm/boot/dts/am335x-igep0033.dtsi
@@ -105,10 +105,16 @@
105 105
106&cpsw_emac0 { 106&cpsw_emac0 {
107 phy_id = <&davinci_mdio>, <0>; 107 phy_id = <&davinci_mdio>, <0>;
108 phy-mode = "rmii";
108}; 109};
109 110
110&cpsw_emac1 { 111&cpsw_emac1 {
111 phy_id = <&davinci_mdio>, <1>; 112 phy_id = <&davinci_mdio>, <1>;
113 phy-mode = "rmii";
114};
115
116&phy_sel {
117 rmii-clock-ext;
112}; 118};
113 119
114&elm { 120&elm {
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index 19f1f7e87597..90098f98a5c8 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -319,6 +319,10 @@
319 phy-mode = "rmii"; 319 phy-mode = "rmii";
320}; 320};
321 321
322&phy_sel {
323 rmii-clock-ext;
324};
325
322&i2c0 { 326&i2c0 {
323 status = "okay"; 327 status = "okay";
324 pinctrl-names = "default"; 328 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index d6133f497207..2ebc42140ea6 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -1045,6 +1045,8 @@
1045 reg = <0x00500000 0x80000 1045 reg = <0x00500000 0x80000
1046 0xf803c000 0x400>; 1046 0xf803c000 0x400>;
1047 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; 1047 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
1048 clocks = <&usb>, <&udphs_clk>;
1049 clock-names = "hclk", "pclk";
1048 status = "disabled"; 1050 status = "disabled";
1049 1051
1050 ep0 { 1052 ep0 {
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 4adc28039c30..83089540e324 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -240,6 +240,7 @@
240 regulator-name = "ldo3"; 240 regulator-name = "ldo3";
241 regulator-min-microvolt = <1800000>; 241 regulator-min-microvolt = <1800000>;
242 regulator-max-microvolt = <1800000>; 242 regulator-max-microvolt = <1800000>;
243 regulator-always-on;
243 regulator-boot-on; 244 regulator-boot-on;
244 }; 245 };
245 246
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index c29945e07c5a..80127638b379 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -773,7 +773,6 @@
773 clocks = <&qspi_gfclk_div>; 773 clocks = <&qspi_gfclk_div>;
774 clock-names = "fck"; 774 clock-names = "fck";
775 num-cs = <4>; 775 num-cs = <4>;
776 interrupts = <0 343 0x4>;
777 status = "disabled"; 776 status = "disabled";
778 }; 777 };
779 778
@@ -984,6 +983,17 @@
984 #size-cells = <1>; 983 #size-cells = <1>;
985 status = "disabled"; 984 status = "disabled";
986 }; 985 };
986
987 atl: atl@4843c000 {
988 compatible = "ti,dra7-atl";
989 reg = <0x4843c000 0x3ff>;
990 ti,hwmods = "atl";
991 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
992 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
993 clocks = <&atl_gfclk_mux>;
994 clock-names = "fck";
995 status = "disabled";
996 };
987 }; 997 };
988}; 998};
989 999
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index b03cfe49d22b..dc7a292fe939 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -10,26 +10,26 @@
10&cm_core_aon_clocks { 10&cm_core_aon_clocks {
11 atl_clkin0_ck: atl_clkin0_ck { 11 atl_clkin0_ck: atl_clkin0_ck {
12 #clock-cells = <0>; 12 #clock-cells = <0>;
13 compatible = "fixed-clock"; 13 compatible = "ti,dra7-atl-clock";
14 clock-frequency = <0>; 14 clocks = <&atl_gfclk_mux>;
15 }; 15 };
16 16
17 atl_clkin1_ck: atl_clkin1_ck { 17 atl_clkin1_ck: atl_clkin1_ck {
18 #clock-cells = <0>; 18 #clock-cells = <0>;
19 compatible = "fixed-clock"; 19 compatible = "ti,dra7-atl-clock";
20 clock-frequency = <0>; 20 clocks = <&atl_gfclk_mux>;
21 }; 21 };
22 22
23 atl_clkin2_ck: atl_clkin2_ck { 23 atl_clkin2_ck: atl_clkin2_ck {
24 #clock-cells = <0>; 24 #clock-cells = <0>;
25 compatible = "fixed-clock"; 25 compatible = "ti,dra7-atl-clock";
26 clock-frequency = <0>; 26 clocks = <&atl_gfclk_mux>;
27 }; 27 };
28 28
29 atl_clkin3_ck: atl_clkin3_ck { 29 atl_clkin3_ck: atl_clkin3_ck {
30 #clock-cells = <0>; 30 #clock-cells = <0>;
31 compatible = "fixed-clock"; 31 compatible = "ti,dra7-atl-clock";
32 clock-frequency = <0>; 32 clocks = <&atl_gfclk_mux>;
33 }; 33 };
34 34
35 hdmi_clkin_ck: hdmi_clkin_ck { 35 hdmi_clkin_ck: hdmi_clkin_ck {
@@ -673,10 +673,12 @@
673 673
674 l3_iclk_div: l3_iclk_div { 674 l3_iclk_div: l3_iclk_div {
675 #clock-cells = <0>; 675 #clock-cells = <0>;
676 compatible = "fixed-factor-clock"; 676 compatible = "ti,divider-clock";
677 ti,max-div = <2>;
678 ti,bit-shift = <4>;
679 reg = <0x0100>;
677 clocks = <&dpll_core_h12x2_ck>; 680 clocks = <&dpll_core_h12x2_ck>;
678 clock-mult = <1>; 681 ti,index-power-of-two;
679 clock-div = <1>;
680 }; 682 };
681 683
682 l4_root_clk_div: l4_root_clk_div { 684 l4_root_clk_div: l4_root_clk_div {
@@ -684,7 +686,7 @@
684 compatible = "fixed-factor-clock"; 686 compatible = "fixed-factor-clock";
685 clocks = <&l3_iclk_div>; 687 clocks = <&l3_iclk_div>;
686 clock-mult = <1>; 688 clock-mult = <1>;
687 clock-div = <1>; 689 clock-div = <2>;
688 }; 690 };
689 691
690 video1_clk2_div: video1_clk2_div { 692 video1_clk2_div: video1_clk2_div {
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index fbaf426d2daa..17b22e9cc2aa 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -554,7 +554,7 @@
554 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>; 554 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
555 clocks = <&clock CLK_PWM>; 555 clocks = <&clock CLK_PWM>;
556 clock-names = "timers"; 556 clock-names = "timers";
557 #pwm-cells = <2>; 557 #pwm-cells = <3>;
558 status = "disabled"; 558 status = "disabled";
559 }; 559 };
560 560
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index e38532271ef9..15957227ffda 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -167,7 +167,7 @@
167 compatible = "samsung,exynos5420-audss-clock"; 167 compatible = "samsung,exynos5420-audss-clock";
168 reg = <0x03810000 0x0C>; 168 reg = <0x03810000 0x0C>;
169 #clock-cells = <1>; 169 #clock-cells = <1>;
170 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, 170 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
171 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; 171 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
172 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; 172 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
173 }; 173 };
@@ -260,6 +260,9 @@
260 mfc_pd: power-domain@10044060 { 260 mfc_pd: power-domain@10044060 {
261 compatible = "samsung,exynos4210-pd"; 261 compatible = "samsung,exynos4210-pd";
262 reg = <0x10044060 0x20>; 262 reg = <0x10044060 0x20>;
263 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
264 <&clock CLK_MOUT_USER_ACLK333>;
265 clock-names = "oscclk", "pclk0", "clk0";
263 }; 266 };
264 267
265 disp_pd: power-domain@100440C0 { 268 disp_pd: power-domain@100440C0 {
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index cf0be662297e..1becefce821b 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -251,6 +251,11 @@
251 codec { 251 codec {
252 }; 252 };
253 }; 253 };
254
255 twl_power: power {
256 compatible = "ti,twl4030-power-beagleboard-xm", "ti,twl4030-power-idle-osc-off";
257 ti,use_poweroff;
258 };
254 }; 259 };
255}; 260};
256 261
@@ -301,6 +306,7 @@
301}; 306};
302 307
303&uart3 { 308&uart3 {
309 interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
304 pinctrl-names = "default"; 310 pinctrl-names = "default";
305 pinctrl-0 = <&uart3_pins>; 311 pinctrl-0 = <&uart3_pins>;
306}; 312};
diff --git a/arch/arm/boot/dts/omap3-evm-common.dtsi b/arch/arm/boot/dts/omap3-evm-common.dtsi
index 8ae8f007c8ad..c8747c7f1cc8 100644
--- a/arch/arm/boot/dts/omap3-evm-common.dtsi
+++ b/arch/arm/boot/dts/omap3-evm-common.dtsi
@@ -50,6 +50,13 @@
50 gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; 50 gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>;
51}; 51};
52 52
53&twl {
54 twl_power: power {
55 compatible = "ti,twl4030-power-omap3-evm", "ti,twl4030-power-idle";
56 ti,use_poweroff;
57 };
58};
59
53&i2c2 { 60&i2c2 {
54 clock-frequency = <400000>; 61 clock-frequency = <400000>;
55}; 62};
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index ae8ae3f4f9bf..1fe45d1f75ec 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -351,6 +351,11 @@
351 compatible = "ti,twl4030-audio"; 351 compatible = "ti,twl4030-audio";
352 ti,enable-vibra = <1>; 352 ti,enable-vibra = <1>;
353 }; 353 };
354
355 twl_power: power {
356 compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off";
357 ti,use_poweroff;
358 };
354}; 359};
355 360
356&twl_keypad { 361&twl_keypad {
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 3bfda16c8b52..a4ed54988866 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -45,7 +45,6 @@
45 45
46 operating-points = < 46 operating-points = <
47 /* kHz uV */ 47 /* kHz uV */
48 500000 880000
49 1000000 1060000 48 1000000 1060000
50 1500000 1250000 49 1500000 1250000
51 >; 50 >;
diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
index 9d13dae99125..4bf72264b175 100644
--- a/arch/arm/configs/bcm_defconfig
+++ b/arch/arm/configs/bcm_defconfig
@@ -94,10 +94,10 @@ CONFIG_BACKLIGHT_CLASS_DEVICE=y
94CONFIG_BACKLIGHT_PWM=y 94CONFIG_BACKLIGHT_PWM=y
95# CONFIG_USB_SUPPORT is not set 95# CONFIG_USB_SUPPORT is not set
96CONFIG_MMC=y 96CONFIG_MMC=y
97CONFIG_MMC_UNSAFE_RESUME=y
98CONFIG_MMC_BLOCK_MINORS=32 97CONFIG_MMC_BLOCK_MINORS=32
99CONFIG_MMC_TEST=y 98CONFIG_MMC_TEST=y
100CONFIG_MMC_SDHCI=y 99CONFIG_MMC_SDHCI=y
100CONFIG_MMC_SDHCI_PLTFM=y
101CONFIG_MMC_SDHCI_BCM_KONA=y 101CONFIG_MMC_SDHCI_BCM_KONA=y
102CONFIG_NEW_LEDS=y 102CONFIG_NEW_LEDS=y
103CONFIG_LEDS_CLASS=y 103CONFIG_LEDS_CLASS=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 9a1e7b0c3bea..f70ea2116fec 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -223,12 +223,12 @@ CONFIG_POWER_RESET_GPIO=y
223CONFIG_POWER_RESET_SUN6I=y 223CONFIG_POWER_RESET_SUN6I=y
224CONFIG_SENSORS_LM90=y 224CONFIG_SENSORS_LM90=y
225CONFIG_THERMAL=y 225CONFIG_THERMAL=y
226CONFIG_DOVE_THERMAL=y
227CONFIG_ARMADA_THERMAL=y 226CONFIG_ARMADA_THERMAL=y
228CONFIG_WATCHDOG=y 227CONFIG_WATCHDOG=y
229CONFIG_ORION_WATCHDOG=y 228CONFIG_ORION_WATCHDOG=y
230CONFIG_SUNXI_WATCHDOG=y 229CONFIG_SUNXI_WATCHDOG=y
231CONFIG_MFD_AS3722=y 230CONFIG_MFD_AS3722=y
231CONFIG_MFD_BCM590XX=y
232CONFIG_MFD_CROS_EC=y 232CONFIG_MFD_CROS_EC=y
233CONFIG_MFD_CROS_EC_SPI=y 233CONFIG_MFD_CROS_EC_SPI=y
234CONFIG_MFD_MAX8907=y 234CONFIG_MFD_MAX8907=y
@@ -240,6 +240,7 @@ CONFIG_MFD_TPS65910=y
240CONFIG_REGULATOR_VIRTUAL_CONSUMER=y 240CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
241CONFIG_REGULATOR_AB8500=y 241CONFIG_REGULATOR_AB8500=y
242CONFIG_REGULATOR_AS3722=y 242CONFIG_REGULATOR_AS3722=y
243CONFIG_REGULATOR_BCM590XX=y
243CONFIG_REGULATOR_GPIO=y 244CONFIG_REGULATOR_GPIO=y
244CONFIG_REGULATOR_MAX8907=y 245CONFIG_REGULATOR_MAX8907=y
245CONFIG_REGULATOR_PALMAS=y 246CONFIG_REGULATOR_PALMAS=y
diff --git a/arch/arm/kernel/kprobes-test-arm.c b/arch/arm/kernel/kprobes-test-arm.c
index 9db4b659d03e..cb1424240ff6 100644
--- a/arch/arm/kernel/kprobes-test-arm.c
+++ b/arch/arm/kernel/kprobes-test-arm.c
@@ -74,8 +74,6 @@ void kprobe_arm_test_cases(void)
74 TEST_RRR( op "lt" s " r11, r",11,VAL1,", r",14,N(val),", asr r",7, 6,"")\ 74 TEST_RRR( op "lt" s " r11, r",11,VAL1,", r",14,N(val),", asr r",7, 6,"")\
75 TEST_RR( op "gt" s " r12, r13" ", r",14,val, ", ror r",14,7,"")\ 75 TEST_RR( op "gt" s " r12, r13" ", r",14,val, ", ror r",14,7,"")\
76 TEST_RR( op "le" s " r14, r",0, val, ", r13" ", lsl r",14,8,"")\ 76 TEST_RR( op "le" s " r14, r",0, val, ", r13" ", lsl r",14,8,"")\
77 TEST_RR( op s " r12, pc" ", r",14,val, ", ror r",14,7,"")\
78 TEST_RR( op s " r14, r",0, val, ", pc" ", lsl r",14,8,"")\
79 TEST_R( op "eq" s " r0, r",11,VAL1,", #0xf5") \ 77 TEST_R( op "eq" s " r0, r",11,VAL1,", #0xf5") \
80 TEST_R( op "ne" s " r11, r",0, VAL1,", #0xf5000000") \ 78 TEST_R( op "ne" s " r11, r",0, VAL1,", #0xf5000000") \
81 TEST_R( op s " r7, r",8, VAL2,", #0x000af000") \ 79 TEST_R( op s " r7, r",8, VAL2,", #0x000af000") \
@@ -103,8 +101,6 @@ void kprobe_arm_test_cases(void)
103 TEST_RRR( op "ge r",11,VAL1,", r",14,N(val),", asr r",7, 6,"") \ 101 TEST_RRR( op "ge r",11,VAL1,", r",14,N(val),", asr r",7, 6,"") \
104 TEST_RR( op "le r13" ", r",14,val, ", ror r",14,7,"") \ 102 TEST_RR( op "le r13" ", r",14,val, ", ror r",14,7,"") \
105 TEST_RR( op "gt r",0, val, ", r13" ", lsl r",14,8,"") \ 103 TEST_RR( op "gt r",0, val, ", r13" ", lsl r",14,8,"") \
106 TEST_RR( op " pc" ", r",14,val, ", ror r",14,7,"") \
107 TEST_RR( op " r",0, val, ", pc" ", lsl r",14,8,"") \
108 TEST_R( op "eq r",11,VAL1,", #0xf5") \ 104 TEST_R( op "eq r",11,VAL1,", #0xf5") \
109 TEST_R( op "ne r",0, VAL1,", #0xf5000000") \ 105 TEST_R( op "ne r",0, VAL1,", #0xf5000000") \
110 TEST_R( op " r",8, VAL2,", #0x000af000") 106 TEST_R( op " r",8, VAL2,", #0x000af000")
@@ -125,7 +121,6 @@ void kprobe_arm_test_cases(void)
125 TEST_RR( op "ge" s " r11, r",11,N(val),", asr r",7, 6,"") \ 121 TEST_RR( op "ge" s " r11, r",11,N(val),", asr r",7, 6,"") \
126 TEST_RR( op "lt" s " r12, r",11,val, ", ror r",14,7,"") \ 122 TEST_RR( op "lt" s " r12, r",11,val, ", ror r",14,7,"") \
127 TEST_R( op "gt" s " r14, r13" ", lsl r",14,8,"") \ 123 TEST_R( op "gt" s " r14, r13" ", lsl r",14,8,"") \
128 TEST_R( op "le" s " r14, pc" ", lsl r",14,8,"") \
129 TEST( op "eq" s " r0, #0xf5") \ 124 TEST( op "eq" s " r0, #0xf5") \
130 TEST( op "ne" s " r11, #0xf5000000") \ 125 TEST( op "ne" s " r11, #0xf5000000") \
131 TEST( op s " r7, #0x000af000") \ 126 TEST( op s " r7, #0x000af000") \
@@ -159,12 +154,19 @@ void kprobe_arm_test_cases(void)
159 TEST_SUPPORTED("cmp pc, #0x1000"); 154 TEST_SUPPORTED("cmp pc, #0x1000");
160 TEST_SUPPORTED("cmp sp, #0x1000"); 155 TEST_SUPPORTED("cmp sp, #0x1000");
161 156
162 /* Data-processing with PC as shift*/ 157 /* Data-processing with PC and a shift count in a register */
163 TEST_UNSUPPORTED(__inst_arm(0xe15c0f1e) " @ cmp r12, r14, asl pc") 158 TEST_UNSUPPORTED(__inst_arm(0xe15c0f1e) " @ cmp r12, r14, asl pc")
164 TEST_UNSUPPORTED(__inst_arm(0xe1a0cf1e) " @ mov r12, r14, asl pc") 159 TEST_UNSUPPORTED(__inst_arm(0xe1a0cf1e) " @ mov r12, r14, asl pc")
165 TEST_UNSUPPORTED(__inst_arm(0xe08caf1e) " @ add r10, r12, r14, asl pc") 160 TEST_UNSUPPORTED(__inst_arm(0xe08caf1e) " @ add r10, r12, r14, asl pc")
166 161 TEST_UNSUPPORTED(__inst_arm(0xe151021f) " @ cmp r1, pc, lsl r2")
167 /* Data-processing with PC as shift*/ 162 TEST_UNSUPPORTED(__inst_arm(0xe17f0211) " @ cmn pc, r1, lsl r2")
163 TEST_UNSUPPORTED(__inst_arm(0xe1a0121f) " @ mov r1, pc, lsl r2")
164 TEST_UNSUPPORTED(__inst_arm(0xe1a0f211) " @ mov pc, r1, lsl r2")
165 TEST_UNSUPPORTED(__inst_arm(0xe042131f) " @ sub r1, r2, pc, lsl r3")
166 TEST_UNSUPPORTED(__inst_arm(0xe1cf1312) " @ bic r1, pc, r2, lsl r3")
167 TEST_UNSUPPORTED(__inst_arm(0xe081f312) " @ add pc, r1, r2, lsl r3")
168
169 /* Data-processing with PC as a target and status registers updated */
168 TEST_UNSUPPORTED("movs pc, r1") 170 TEST_UNSUPPORTED("movs pc, r1")
169 TEST_UNSUPPORTED("movs pc, r1, lsl r2") 171 TEST_UNSUPPORTED("movs pc, r1, lsl r2")
170 TEST_UNSUPPORTED("movs pc, #0x10000") 172 TEST_UNSUPPORTED("movs pc, #0x10000")
@@ -187,14 +189,14 @@ void kprobe_arm_test_cases(void)
187 TEST_BF_R ("add pc, pc, r",14,2f-1f-8,"") 189 TEST_BF_R ("add pc, pc, r",14,2f-1f-8,"")
188 TEST_BF_R ("add pc, r",14,2f-1f-8,", pc") 190 TEST_BF_R ("add pc, r",14,2f-1f-8,", pc")
189 TEST_BF_R ("mov pc, r",0,2f,"") 191 TEST_BF_R ("mov pc, r",0,2f,"")
190 TEST_BF_RR("mov pc, r",0,2f,", asl r",1,0,"") 192 TEST_BF_R ("add pc, pc, r",14,(2f-1f-8)*2,", asr #1")
191 TEST_BB( "sub pc, pc, #1b-2b+8") 193 TEST_BB( "sub pc, pc, #1b-2b+8")
192#if __LINUX_ARM_ARCH__ == 6 && !defined(CONFIG_CPU_V7) 194#if __LINUX_ARM_ARCH__ == 6 && !defined(CONFIG_CPU_V7)
193 TEST_BB( "sub pc, pc, #1b-2b+8-2") /* UNPREDICTABLE before and after ARMv6 */ 195 TEST_BB( "sub pc, pc, #1b-2b+8-2") /* UNPREDICTABLE before and after ARMv6 */
194#endif 196#endif
195 TEST_BB_R( "sub pc, pc, r",14, 1f-2f+8,"") 197 TEST_BB_R( "sub pc, pc, r",14, 1f-2f+8,"")
196 TEST_BB_R( "rsb pc, r",14,1f-2f+8,", pc") 198 TEST_BB_R( "rsb pc, r",14,1f-2f+8,", pc")
197 TEST_RR( "add pc, pc, r",10,-2,", asl r",11,1,"") 199 TEST_R( "add pc, pc, r",10,-2,", asl #1")
198#ifdef CONFIG_THUMB2_KERNEL 200#ifdef CONFIG_THUMB2_KERNEL
199 TEST_ARM_TO_THUMB_INTERWORK_R("add pc, pc, r",0,3f-1f-8+1,"") 201 TEST_ARM_TO_THUMB_INTERWORK_R("add pc, pc, r",0,3f-1f-8+1,"")
200 TEST_ARM_TO_THUMB_INTERWORK_R("sub pc, r",0,3f+8+1,", #8") 202 TEST_ARM_TO_THUMB_INTERWORK_R("sub pc, r",0,3f+8+1,", #8")
@@ -216,6 +218,7 @@ void kprobe_arm_test_cases(void)
216 TEST_BB_R("bx r",7,2f,"") 218 TEST_BB_R("bx r",7,2f,"")
217 TEST_BF_R("bxeq r",14,2f,"") 219 TEST_BF_R("bxeq r",14,2f,"")
218 220
221#if __LINUX_ARM_ARCH__ >= 5
219 TEST_R("clz r0, r",0, 0x0,"") 222 TEST_R("clz r0, r",0, 0x0,"")
220 TEST_R("clzeq r7, r",14,0x1,"") 223 TEST_R("clzeq r7, r",14,0x1,"")
221 TEST_R("clz lr, r",7, 0xffffffff,"") 224 TEST_R("clz lr, r",7, 0xffffffff,"")
@@ -337,6 +340,7 @@ void kprobe_arm_test_cases(void)
337 TEST_UNSUPPORTED(__inst_arm(0xe16f02e1) " @ smultt pc, r1, r2") 340 TEST_UNSUPPORTED(__inst_arm(0xe16f02e1) " @ smultt pc, r1, r2")
338 TEST_UNSUPPORTED(__inst_arm(0xe16002ef) " @ smultt r0, pc, r2") 341 TEST_UNSUPPORTED(__inst_arm(0xe16002ef) " @ smultt r0, pc, r2")
339 TEST_UNSUPPORTED(__inst_arm(0xe1600fe1) " @ smultt r0, r1, pc") 342 TEST_UNSUPPORTED(__inst_arm(0xe1600fe1) " @ smultt r0, r1, pc")
343#endif
340 344
341 TEST_GROUP("Multiply and multiply-accumulate") 345 TEST_GROUP("Multiply and multiply-accumulate")
342 346
@@ -559,6 +563,7 @@ void kprobe_arm_test_cases(void)
559 TEST_UNSUPPORTED("ldrsht r1, [r2], #48") 563 TEST_UNSUPPORTED("ldrsht r1, [r2], #48")
560#endif 564#endif
561 565
566#if __LINUX_ARM_ARCH__ >= 5
562 TEST_RPR( "strd r",0, VAL1,", [r",1, 48,", -r",2,24,"]") 567 TEST_RPR( "strd r",0, VAL1,", [r",1, 48,", -r",2,24,"]")
563 TEST_RPR( "strccd r",8, VAL2,", [r",13,0, ", r",12,48,"]") 568 TEST_RPR( "strccd r",8, VAL2,", [r",13,0, ", r",12,48,"]")
564 TEST_RPR( "strd r",4, VAL1,", [r",2, 24,", r",3, 48,"]!") 569 TEST_RPR( "strd r",4, VAL1,", [r",2, 24,", r",3, 48,"]!")
@@ -595,6 +600,7 @@ void kprobe_arm_test_cases(void)
595 TEST_UNSUPPORTED(__inst_arm(0xe1efc3d0) " @ ldrd r12, [pc, #48]!") 600 TEST_UNSUPPORTED(__inst_arm(0xe1efc3d0) " @ ldrd r12, [pc, #48]!")
596 TEST_UNSUPPORTED(__inst_arm(0xe0c9f3d0) " @ ldrd pc, [r9], #48") 601 TEST_UNSUPPORTED(__inst_arm(0xe0c9f3d0) " @ ldrd pc, [r9], #48")
597 TEST_UNSUPPORTED(__inst_arm(0xe0c9e3d0) " @ ldrd lr, [r9], #48") 602 TEST_UNSUPPORTED(__inst_arm(0xe0c9e3d0) " @ ldrd lr, [r9], #48")
603#endif
598 604
599 TEST_GROUP("Miscellaneous") 605 TEST_GROUP("Miscellaneous")
600 606
@@ -1227,7 +1233,9 @@ void kprobe_arm_test_cases(void)
1227 TEST_COPROCESSOR( "mrc"two" 0, 0, r0, cr0, cr0, 0") 1233 TEST_COPROCESSOR( "mrc"two" 0, 0, r0, cr0, cr0, 0")
1228 1234
1229 COPROCESSOR_INSTRUCTIONS_ST_LD("",e) 1235 COPROCESSOR_INSTRUCTIONS_ST_LD("",e)
1236#if __LINUX_ARM_ARCH__ >= 5
1230 COPROCESSOR_INSTRUCTIONS_MC_MR("",e) 1237 COPROCESSOR_INSTRUCTIONS_MC_MR("",e)
1238#endif
1231 TEST_UNSUPPORTED("svc 0") 1239 TEST_UNSUPPORTED("svc 0")
1232 TEST_UNSUPPORTED("svc 0xffffff") 1240 TEST_UNSUPPORTED("svc 0xffffff")
1233 1241
@@ -1287,7 +1295,9 @@ void kprobe_arm_test_cases(void)
1287 TEST( "blx __dummy_thumb_subroutine_odd") 1295 TEST( "blx __dummy_thumb_subroutine_odd")
1288#endif /* __LINUX_ARM_ARCH__ >= 6 */ 1296#endif /* __LINUX_ARM_ARCH__ >= 6 */
1289 1297
1298#if __LINUX_ARM_ARCH__ >= 5
1290 COPROCESSOR_INSTRUCTIONS_ST_LD("2",f) 1299 COPROCESSOR_INSTRUCTIONS_ST_LD("2",f)
1300#endif
1291#if __LINUX_ARM_ARCH__ >= 6 1301#if __LINUX_ARM_ARCH__ >= 6
1292 COPROCESSOR_INSTRUCTIONS_MC_MR("2",f) 1302 COPROCESSOR_INSTRUCTIONS_MC_MR("2",f)
1293#endif 1303#endif
diff --git a/arch/arm/kernel/kprobes-test.c b/arch/arm/kernel/kprobes-test.c
index 379639998d5a..08d731294bcd 100644
--- a/arch/arm/kernel/kprobes-test.c
+++ b/arch/arm/kernel/kprobes-test.c
@@ -225,6 +225,7 @@ static int pre_handler_called;
225static int post_handler_called; 225static int post_handler_called;
226static int jprobe_func_called; 226static int jprobe_func_called;
227static int kretprobe_handler_called; 227static int kretprobe_handler_called;
228static int tests_failed;
228 229
229#define FUNC_ARG1 0x12345678 230#define FUNC_ARG1 0x12345678
230#define FUNC_ARG2 0xabcdef 231#define FUNC_ARG2 0xabcdef
@@ -461,6 +462,13 @@ static int run_api_tests(long (*func)(long, long))
461 462
462 pr_info(" jprobe\n"); 463 pr_info(" jprobe\n");
463 ret = test_jprobe(func); 464 ret = test_jprobe(func);
465#if defined(CONFIG_THUMB2_KERNEL) && !defined(MODULE)
466 if (ret == -EINVAL) {
467 pr_err("FAIL: Known longtime bug with jprobe on Thumb kernels\n");
468 tests_failed = ret;
469 ret = 0;
470 }
471#endif
464 if (ret < 0) 472 if (ret < 0)
465 return ret; 473 return ret;
466 474
@@ -1672,6 +1680,8 @@ static int __init run_all_tests(void)
1672 1680
1673out: 1681out:
1674 if (ret == 0) 1682 if (ret == 0)
1683 ret = tests_failed;
1684 if (ret == 0)
1675 pr_info("Finished kprobe tests OK\n"); 1685 pr_info("Finished kprobe tests OK\n");
1676 else 1686 else
1677 pr_err("kprobe tests failed\n"); 1687 pr_err("kprobe tests failed\n");
diff --git a/arch/arm/kernel/probes-arm.c b/arch/arm/kernel/probes-arm.c
index 51a13a027989..8eaef81d8344 100644
--- a/arch/arm/kernel/probes-arm.c
+++ b/arch/arm/kernel/probes-arm.c
@@ -341,12 +341,12 @@ static const union decode_item arm_cccc_000x_table[] = {
341 /* CMP (reg-shift reg) cccc 0001 0101 xxxx xxxx xxxx 0xx1 xxxx */ 341 /* CMP (reg-shift reg) cccc 0001 0101 xxxx xxxx xxxx 0xx1 xxxx */
342 /* CMN (reg-shift reg) cccc 0001 0111 xxxx xxxx xxxx 0xx1 xxxx */ 342 /* CMN (reg-shift reg) cccc 0001 0111 xxxx xxxx xxxx 0xx1 xxxx */
343 DECODE_EMULATEX (0x0f900090, 0x01100010, PROBES_DATA_PROCESSING_REG, 343 DECODE_EMULATEX (0x0f900090, 0x01100010, PROBES_DATA_PROCESSING_REG,
344 REGS(ANY, 0, NOPC, 0, ANY)), 344 REGS(NOPC, 0, NOPC, 0, NOPC)),
345 345
346 /* MOV (reg-shift reg) cccc 0001 101x xxxx xxxx xxxx 0xx1 xxxx */ 346 /* MOV (reg-shift reg) cccc 0001 101x xxxx xxxx xxxx 0xx1 xxxx */
347 /* MVN (reg-shift reg) cccc 0001 111x xxxx xxxx xxxx 0xx1 xxxx */ 347 /* MVN (reg-shift reg) cccc 0001 111x xxxx xxxx xxxx 0xx1 xxxx */
348 DECODE_EMULATEX (0x0fa00090, 0x01a00010, PROBES_DATA_PROCESSING_REG, 348 DECODE_EMULATEX (0x0fa00090, 0x01a00010, PROBES_DATA_PROCESSING_REG,
349 REGS(0, ANY, NOPC, 0, ANY)), 349 REGS(0, NOPC, NOPC, 0, NOPC)),
350 350
351 /* AND (reg-shift reg) cccc 0000 000x xxxx xxxx xxxx 0xx1 xxxx */ 351 /* AND (reg-shift reg) cccc 0000 000x xxxx xxxx xxxx 0xx1 xxxx */
352 /* EOR (reg-shift reg) cccc 0000 001x xxxx xxxx xxxx 0xx1 xxxx */ 352 /* EOR (reg-shift reg) cccc 0000 001x xxxx xxxx xxxx 0xx1 xxxx */
@@ -359,7 +359,7 @@ static const union decode_item arm_cccc_000x_table[] = {
359 /* ORR (reg-shift reg) cccc 0001 100x xxxx xxxx xxxx 0xx1 xxxx */ 359 /* ORR (reg-shift reg) cccc 0001 100x xxxx xxxx xxxx 0xx1 xxxx */
360 /* BIC (reg-shift reg) cccc 0001 110x xxxx xxxx xxxx 0xx1 xxxx */ 360 /* BIC (reg-shift reg) cccc 0001 110x xxxx xxxx xxxx 0xx1 xxxx */
361 DECODE_EMULATEX (0x0e000090, 0x00000010, PROBES_DATA_PROCESSING_REG, 361 DECODE_EMULATEX (0x0e000090, 0x00000010, PROBES_DATA_PROCESSING_REG,
362 REGS(ANY, ANY, NOPC, 0, ANY)), 362 REGS(NOPC, NOPC, NOPC, 0, NOPC)),
363 363
364 DECODE_END 364 DECODE_END
365}; 365};
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index f38cf7c110cc..c7d960aa95a8 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -173,10 +173,8 @@ static struct platform_device exynos_cpuidle = {
173 173
174void __init exynos_cpuidle_init(void) 174void __init exynos_cpuidle_init(void)
175{ 175{
176 if (soc_is_exynos5440()) 176 if (soc_is_exynos4210() || soc_is_exynos5250())
177 return; 177 platform_device_register(&exynos_cpuidle);
178
179 platform_device_register(&exynos_cpuidle);
180} 178}
181 179
182void __init exynos_cpufreq_init(void) 180void __init exynos_cpufreq_init(void)
@@ -297,10 +295,12 @@ static void __init exynos_dt_machine_init(void)
297 * This is called from smp_prepare_cpus if we've built for SMP, but 295 * This is called from smp_prepare_cpus if we've built for SMP, but
298 * we still need to set it up for PM and firmware ops if not. 296 * we still need to set it up for PM and firmware ops if not.
299 */ 297 */
300 if (!IS_ENABLED(SMP)) 298 if (!IS_ENABLED(CONFIG_SMP))
301 exynos_sysram_init(); 299 exynos_sysram_init();
302 300
303 exynos_cpuidle_init(); 301 if (!of_machine_is_compatible("samsung,exynos5420"))
302 exynos_cpuidle_init();
303
304 exynos_cpufreq_init(); 304 exynos_cpufreq_init();
305 305
306 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 306 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index eb91d2350f8c..e8797bb78871 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -57,8 +57,13 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
57 57
58 boot_reg = sysram_ns_base_addr + 0x1c; 58 boot_reg = sysram_ns_base_addr + 0x1c;
59 59
60 if (!soc_is_exynos4212() && !soc_is_exynos3250()) 60 /*
61 boot_reg += 4*cpu; 61 * Almost all Exynos-series of SoCs that run in secure mode don't need
62 * additional offset for every CPU, with Exynos4412 being the only
63 * exception.
64 */
65 if (soc_is_exynos4412())
66 boot_reg += 4 * cpu;
62 67
63 __raw_writel(boot_addr, boot_reg); 68 __raw_writel(boot_addr, boot_reg);
64 return 0; 69 return 0;
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
index ace0ed617476..13a210865c6f 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -257,10 +257,46 @@ static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
257 return -ETIMEDOUT; /* timeout */ 257 return -ETIMEDOUT; /* timeout */
258} 258}
259 259
260static void exynos_powered_up(void)
261{
262 unsigned int mpidr, cpu, cluster;
263
264 mpidr = read_cpuid_mpidr();
265 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
266 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
267
268 arch_spin_lock(&exynos_mcpm_lock);
269 if (cpu_use_count[cpu][cluster] == 0)
270 cpu_use_count[cpu][cluster] = 1;
271 arch_spin_unlock(&exynos_mcpm_lock);
272}
273
274static void exynos_suspend(u64 residency)
275{
276 unsigned int mpidr, cpunr;
277
278 exynos_power_down();
279
280 /*
281 * Execution reaches here only if cpu did not power down.
282 * Hence roll back the changes done in exynos_power_down function.
283 *
284 * CAUTION: "This function requires the stack data to be visible through
285 * power down and can only be executed on processors like A15 and A7
286 * that hit the cache with the C bit clear in the SCTLR register."
287 */
288 mpidr = read_cpuid_mpidr();
289 cpunr = exynos_pmu_cpunr(mpidr);
290
291 exynos_cpu_power_up(cpunr);
292}
293
260static const struct mcpm_platform_ops exynos_power_ops = { 294static const struct mcpm_platform_ops exynos_power_ops = {
261 .power_up = exynos_power_up, 295 .power_up = exynos_power_up,
262 .power_down = exynos_power_down, 296 .power_down = exynos_power_down,
263 .wait_for_powerdown = exynos_wait_for_powerdown, 297 .wait_for_powerdown = exynos_wait_for_powerdown,
298 .suspend = exynos_suspend,
299 .powered_up = exynos_powered_up,
264}; 300};
265 301
266static void __init exynos_mcpm_usage_count_init(void) 302static void __init exynos_mcpm_usage_count_init(void)
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index fe6570ebbdde..797cb134bfff 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -17,6 +17,7 @@
17#include <linux/err.h> 17#include <linux/err.h>
18#include <linux/slab.h> 18#include <linux/slab.h>
19#include <linux/pm_domain.h> 19#include <linux/pm_domain.h>
20#include <linux/clk.h>
20#include <linux/delay.h> 21#include <linux/delay.h>
21#include <linux/of_address.h> 22#include <linux/of_address.h>
22#include <linux/of_platform.h> 23#include <linux/of_platform.h>
@@ -24,6 +25,8 @@
24 25
25#include "regs-pmu.h" 26#include "regs-pmu.h"
26 27
28#define MAX_CLK_PER_DOMAIN 4
29
27/* 30/*
28 * Exynos specific wrapper around the generic power domain 31 * Exynos specific wrapper around the generic power domain
29 */ 32 */
@@ -32,6 +35,9 @@ struct exynos_pm_domain {
32 char const *name; 35 char const *name;
33 bool is_off; 36 bool is_off;
34 struct generic_pm_domain pd; 37 struct generic_pm_domain pd;
38 struct clk *oscclk;
39 struct clk *clk[MAX_CLK_PER_DOMAIN];
40 struct clk *pclk[MAX_CLK_PER_DOMAIN];
35}; 41};
36 42
37static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) 43static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
@@ -44,6 +50,19 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
44 pd = container_of(domain, struct exynos_pm_domain, pd); 50 pd = container_of(domain, struct exynos_pm_domain, pd);
45 base = pd->base; 51 base = pd->base;
46 52
53 /* Set oscclk before powering off a domain*/
54 if (!power_on) {
55 int i;
56
57 for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
58 if (IS_ERR(pd->clk[i]))
59 break;
60 if (clk_set_parent(pd->clk[i], pd->oscclk))
61 pr_err("%s: error setting oscclk as parent to clock %d\n",
62 pd->name, i);
63 }
64 }
65
47 pwr = power_on ? S5P_INT_LOCAL_PWR_EN : 0; 66 pwr = power_on ? S5P_INT_LOCAL_PWR_EN : 0;
48 __raw_writel(pwr, base); 67 __raw_writel(pwr, base);
49 68
@@ -60,6 +79,20 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
60 cpu_relax(); 79 cpu_relax();
61 usleep_range(80, 100); 80 usleep_range(80, 100);
62 } 81 }
82
83 /* Restore clocks after powering on a domain*/
84 if (power_on) {
85 int i;
86
87 for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
88 if (IS_ERR(pd->clk[i]))
89 break;
90 if (clk_set_parent(pd->clk[i], pd->pclk[i]))
91 pr_err("%s: error setting parent to clock%d\n",
92 pd->name, i);
93 }
94 }
95
63 return 0; 96 return 0;
64} 97}
65 98
@@ -152,9 +185,11 @@ static __init int exynos4_pm_init_power_domain(void)
152 185
153 for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") { 186 for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
154 struct exynos_pm_domain *pd; 187 struct exynos_pm_domain *pd;
155 int on; 188 int on, i;
189 struct device *dev;
156 190
157 pdev = of_find_device_by_node(np); 191 pdev = of_find_device_by_node(np);
192 dev = &pdev->dev;
158 193
159 pd = kzalloc(sizeof(*pd), GFP_KERNEL); 194 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
160 if (!pd) { 195 if (!pd) {
@@ -170,6 +205,30 @@ static __init int exynos4_pm_init_power_domain(void)
170 pd->pd.power_on = exynos_pd_power_on; 205 pd->pd.power_on = exynos_pd_power_on;
171 pd->pd.of_node = np; 206 pd->pd.of_node = np;
172 207
208 pd->oscclk = clk_get(dev, "oscclk");
209 if (IS_ERR(pd->oscclk))
210 goto no_clk;
211
212 for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
213 char clk_name[8];
214
215 snprintf(clk_name, sizeof(clk_name), "clk%d", i);
216 pd->clk[i] = clk_get(dev, clk_name);
217 if (IS_ERR(pd->clk[i]))
218 break;
219 snprintf(clk_name, sizeof(clk_name), "pclk%d", i);
220 pd->pclk[i] = clk_get(dev, clk_name);
221 if (IS_ERR(pd->pclk[i])) {
222 clk_put(pd->clk[i]);
223 pd->clk[i] = ERR_PTR(-EINVAL);
224 break;
225 }
226 }
227
228 if (IS_ERR(pd->clk[0]))
229 clk_put(pd->oscclk);
230
231no_clk:
173 platform_set_drvdata(pdev, pd); 232 platform_set_drvdata(pdev, pd);
174 233
175 on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN; 234 on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN;
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 1d13b08708f0..aff23bd395e6 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -323,4 +323,13 @@
323 323
324#define EXYNOS5420_SWRESET_KFC_SEL 0x3 324#define EXYNOS5420_SWRESET_KFC_SEL 0x3
325 325
326#include <asm/cputype.h>
327#define MAX_CPUS_IN_CLUSTER 4
328
329static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
330{
331 return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER)
332 + MPIDR_AFFINITY_LEVEL(mpidr, 0));
333}
334
326#endif /* __ASM_ARCH_REGS_PMU_H */ 335#endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c
index 4ba587da89d2..84acdfd1d715 100644
--- a/arch/arm/mach-imx/clk-gate2.c
+++ b/arch/arm/mach-imx/clk-gate2.c
@@ -67,8 +67,12 @@ static void clk_gate2_disable(struct clk_hw *hw)
67 67
68 spin_lock_irqsave(gate->lock, flags); 68 spin_lock_irqsave(gate->lock, flags);
69 69
70 if (gate->share_count && --(*gate->share_count) > 0) 70 if (gate->share_count) {
71 goto out; 71 if (WARN_ON(*gate->share_count == 0))
72 goto out;
73 else if (--(*gate->share_count) > 0)
74 goto out;
75 }
72 76
73 reg = readl(gate->reg); 77 reg = readl(gate->reg);
74 reg &= ~(3 << gate->bit_idx); 78 reg &= ~(3 << gate->bit_idx);
@@ -78,19 +82,26 @@ out:
78 spin_unlock_irqrestore(gate->lock, flags); 82 spin_unlock_irqrestore(gate->lock, flags);
79} 83}
80 84
81static int clk_gate2_is_enabled(struct clk_hw *hw) 85static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx)
82{ 86{
83 u32 reg; 87 u32 val = readl(reg);
84 struct clk_gate2 *gate = to_clk_gate2(hw);
85 88
86 reg = readl(gate->reg); 89 if (((val >> bit_idx) & 1) == 1)
87
88 if (((reg >> gate->bit_idx) & 1) == 1)
89 return 1; 90 return 1;
90 91
91 return 0; 92 return 0;
92} 93}
93 94
95static int clk_gate2_is_enabled(struct clk_hw *hw)
96{
97 struct clk_gate2 *gate = to_clk_gate2(hw);
98
99 if (gate->share_count)
100 return !!(*gate->share_count);
101 else
102 return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx);
103}
104
94static struct clk_ops clk_gate2_ops = { 105static struct clk_ops clk_gate2_ops = {
95 .enable = clk_gate2_enable, 106 .enable = clk_gate2_enable,
96 .disable = clk_gate2_disable, 107 .disable = clk_gate2_disable,
@@ -116,6 +127,10 @@ struct clk *clk_register_gate2(struct device *dev, const char *name,
116 gate->bit_idx = bit_idx; 127 gate->bit_idx = bit_idx;
117 gate->flags = clk_gate2_flags; 128 gate->flags = clk_gate2_flags;
118 gate->lock = lock; 129 gate->lock = lock;
130
131 /* Initialize share_count per hardware state */
132 if (share_count)
133 *share_count = clk_gate2_reg_is_enabled(reg, bit_idx) ? 1 : 0;
119 gate->share_count = share_count; 134 gate->share_count = share_count;
120 135
121 init.name = name; 136 init.name = name;
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 90bcd5327312..bc7689e530a4 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -7,7 +7,7 @@ CFLAGS_pmsu.o := -march=armv7-a
7obj-y += system-controller.o mvebu-soc-id.o 7obj-y += system-controller.o mvebu-soc-id.o
8 8
9ifeq ($(CONFIG_MACH_MVEBU_V7),y) 9ifeq ($(CONFIG_MACH_MVEBU_V7),y)
10obj-y += cpu-reset.o board-v7.o coherency.o coherency_ll.o pmsu.o 10obj-y += cpu-reset.o board-v7.o coherency.o coherency_ll.o pmsu.o pmsu_ll.o
11obj-$(CONFIG_SMP) += platsmp.o headsmp.o platsmp-a9.o headsmp-a9.o 11obj-$(CONFIG_SMP) += platsmp.o headsmp.o platsmp-a9.o headsmp-a9.o
12endif 12endif
13 13
diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c
index a04675e2ec99..f244622ffc00 100644
--- a/arch/arm/mach-mvebu/board-v7.c
+++ b/arch/arm/mach-mvebu/board-v7.c
@@ -23,6 +23,7 @@
23#include <linux/mbus.h> 23#include <linux/mbus.h>
24#include <linux/signal.h> 24#include <linux/signal.h>
25#include <linux/slab.h> 25#include <linux/slab.h>
26#include <linux/irqchip.h>
26#include <asm/hardware/cache-l2x0.h> 27#include <asm/hardware/cache-l2x0.h>
27#include <asm/mach/arch.h> 28#include <asm/mach/arch.h>
28#include <asm/mach/map.h> 29#include <asm/mach/map.h>
@@ -71,17 +72,23 @@ static int armada_375_external_abort_wa(unsigned long addr, unsigned int fsr,
71 return 1; 72 return 1;
72} 73}
73 74
74static void __init mvebu_timer_and_clk_init(void) 75static void __init mvebu_init_irq(void)
75{ 76{
76 of_clk_init(NULL); 77 irqchip_init();
77 clocksource_of_init();
78 mvebu_scu_enable(); 78 mvebu_scu_enable();
79 coherency_init(); 79 coherency_init();
80 BUG_ON(mvebu_mbus_dt_init(coherency_available())); 80 BUG_ON(mvebu_mbus_dt_init(coherency_available()));
81}
82
83static void __init external_abort_quirk(void)
84{
85 u32 dev, rev;
81 86
82 if (of_machine_is_compatible("marvell,armada375")) 87 if (mvebu_get_soc_id(&dev, &rev) == 0 && rev > ARMADA_375_Z1_REV)
83 hook_fault_code(16 + 6, armada_375_external_abort_wa, SIGBUS, 0, 88 return;
84 "imprecise external abort"); 89
90 hook_fault_code(16 + 6, armada_375_external_abort_wa, SIGBUS, 0,
91 "imprecise external abort");
85} 92}
86 93
87static void __init i2c_quirk(void) 94static void __init i2c_quirk(void)
@@ -178,8 +185,10 @@ static void __init mvebu_dt_init(void)
178{ 185{
179 if (of_machine_is_compatible("plathome,openblocks-ax3-4")) 186 if (of_machine_is_compatible("plathome,openblocks-ax3-4"))
180 i2c_quirk(); 187 i2c_quirk();
181 if (of_machine_is_compatible("marvell,a375-db")) 188 if (of_machine_is_compatible("marvell,a375-db")) {
189 external_abort_quirk();
182 thermal_quirk(); 190 thermal_quirk();
191 }
183 192
184 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 193 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
185} 194}
@@ -194,7 +203,7 @@ DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)")
194 .l2c_aux_mask = ~0, 203 .l2c_aux_mask = ~0,
195 .smp = smp_ops(armada_xp_smp_ops), 204 .smp = smp_ops(armada_xp_smp_ops),
196 .init_machine = mvebu_dt_init, 205 .init_machine = mvebu_dt_init,
197 .init_time = mvebu_timer_and_clk_init, 206 .init_irq = mvebu_init_irq,
198 .restart = mvebu_restart, 207 .restart = mvebu_restart,
199 .dt_compat = armada_370_xp_dt_compat, 208 .dt_compat = armada_370_xp_dt_compat,
200MACHINE_END 209MACHINE_END
@@ -207,7 +216,7 @@ static const char * const armada_375_dt_compat[] = {
207DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)") 216DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)")
208 .l2c_aux_val = 0, 217 .l2c_aux_val = 0,
209 .l2c_aux_mask = ~0, 218 .l2c_aux_mask = ~0,
210 .init_time = mvebu_timer_and_clk_init, 219 .init_irq = mvebu_init_irq,
211 .init_machine = mvebu_dt_init, 220 .init_machine = mvebu_dt_init,
212 .restart = mvebu_restart, 221 .restart = mvebu_restart,
213 .dt_compat = armada_375_dt_compat, 222 .dt_compat = armada_375_dt_compat,
@@ -222,7 +231,7 @@ static const char * const armada_38x_dt_compat[] = {
222DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)") 231DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)")
223 .l2c_aux_val = 0, 232 .l2c_aux_val = 0,
224 .l2c_aux_mask = ~0, 233 .l2c_aux_mask = ~0,
225 .init_time = mvebu_timer_and_clk_init, 234 .init_irq = mvebu_init_irq,
226 .restart = mvebu_restart, 235 .restart = mvebu_restart,
227 .dt_compat = armada_38x_dt_compat, 236 .dt_compat = armada_38x_dt_compat,
228MACHINE_END 237MACHINE_END
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index 9c819d65b337..34f173e7267d 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -66,6 +66,8 @@ static void __iomem *pmsu_mp_base;
66extern void ll_disable_coherency(void); 66extern void ll_disable_coherency(void);
67extern void ll_enable_coherency(void); 67extern void ll_enable_coherency(void);
68 68
69extern void armada_370_xp_cpu_resume(void);
70
69static struct platform_device armada_xp_cpuidle_device = { 71static struct platform_device armada_xp_cpuidle_device = {
70 .name = "cpuidle-armada-370-xp", 72 .name = "cpuidle-armada-370-xp",
71}; 73};
@@ -140,13 +142,6 @@ static void armada_370_xp_pmsu_enable_l2_powerdown_onidle(void)
140 writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL); 142 writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL);
141} 143}
142 144
143static void armada_370_xp_cpu_resume(void)
144{
145 asm volatile("bl ll_add_cpu_to_smp_group\n\t"
146 "bl ll_enable_coherency\n\t"
147 "b cpu_resume\n\t");
148}
149
150/* No locking is needed because we only access per-CPU registers */ 145/* No locking is needed because we only access per-CPU registers */
151int armada_370_xp_pmsu_idle_enter(unsigned long deepidle) 146int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
152{ 147{
diff --git a/arch/arm/mach-mvebu/pmsu_ll.S b/arch/arm/mach-mvebu/pmsu_ll.S
new file mode 100644
index 000000000000..fc3de68d8c54
--- /dev/null
+++ b/arch/arm/mach-mvebu/pmsu_ll.S
@@ -0,0 +1,25 @@
1/*
2 * Copyright (C) 2014 Marvell
3 *
4 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
5 * Gregory Clement <gregory.clement@free-electrons.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/linkage.h>
13#include <asm/assembler.h>
14
15/*
16 * This is the entry point through which CPUs exiting cpuidle deep
17 * idle state are going.
18 */
19ENTRY(armada_370_xp_cpu_resume)
20ARM_BE8(setend be ) @ go BE8 if entered LE
21 bl ll_add_cpu_to_smp_group
22 bl ll_enable_coherency
23 b cpu_resume
24ENDPROC(armada_370_xp_cpu_resume)
25
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 8421f38cf445..8ca99e9321e3 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -110,14 +110,16 @@ obj-y += prm_common.o cm_common.o
110obj-$(CONFIG_ARCH_OMAP2) += prm2xxx_3xxx.o prm2xxx.o cm2xxx.o 110obj-$(CONFIG_ARCH_OMAP2) += prm2xxx_3xxx.o prm2xxx.o cm2xxx.o
111obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o 111obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o
112obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o 112obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
113obj-$(CONFIG_SOC_AM33XX) += prm33xx.o cm33xx.o
114omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \ 113omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \
115 prcm_mpu44xx.o prminst44xx.o \ 114 prcm_mpu44xx.o prminst44xx.o \
116 vc44xx_data.o vp44xx_data.o 115 vc44xx_data.o vp44xx_data.o
117obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) 116obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common)
118obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common) 117obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common)
119obj-$(CONFIG_SOC_DRA7XX) += $(omap-prcm-4-5-common) 118obj-$(CONFIG_SOC_DRA7XX) += $(omap-prcm-4-5-common)
120obj-$(CONFIG_SOC_AM43XX) += $(omap-prcm-4-5-common) 119am33xx-43xx-prcm-common += prm33xx.o cm33xx.o
120obj-$(CONFIG_SOC_AM33XX) += $(am33xx-43xx-prcm-common)
121obj-$(CONFIG_SOC_AM43XX) += $(omap-prcm-4-5-common) \
122 $(am33xx-43xx-prcm-common)
121 123
122# OMAP voltage domains 124# OMAP voltage domains
123voltagedomain-common := voltage.o vc.o vp.o 125voltagedomain-common := voltage.o vc.o vp.o
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 332af927f4d3..67fd26a18441 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -76,7 +76,7 @@
76 * (assuming that it is counting N upwards), or -2 if the enclosing loop 76 * (assuming that it is counting N upwards), or -2 if the enclosing loop
77 * should skip to the next iteration (again assuming N is increasing). 77 * should skip to the next iteration (again assuming N is increasing).
78 */ 78 */
79static int _dpll_test_fint(struct clk_hw_omap *clk, u8 n) 79static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n)
80{ 80{
81 struct dpll_data *dd; 81 struct dpll_data *dd;
82 long fint, fint_min, fint_max; 82 long fint, fint_min, fint_max;
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 04dab2fcf862..ee6c784cd6b7 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -26,11 +26,14 @@
26#define OMAP3430_EN_WDT3_SHIFT 12 26#define OMAP3430_EN_WDT3_SHIFT 12
27#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0) 27#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0)
28#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 28#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0
29#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4
29#define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4) 30#define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4)
30#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3 31#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3
32#define OMAP3430_EN_IVA2_DPLL_SHIFT 0
31#define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) 33#define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0)
32#define OMAP3430_ST_IVA2_SHIFT 0 34#define OMAP3430_ST_IVA2_SHIFT 0
33#define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) 35#define OMAP3430_ST_IVA2_CLK_MASK (1 << 0)
36#define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0
34#define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0) 37#define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0)
35#define OMAP3430_IVA2_CLK_SRC_SHIFT 19 38#define OMAP3430_IVA2_CLK_SRC_SHIFT 19
36#define OMAP3430_IVA2_CLK_SRC_WIDTH 3 39#define OMAP3430_IVA2_CLK_SRC_WIDTH 3
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index 15a778ce7707..bd2441790779 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -380,7 +380,7 @@ void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs);
380void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs); 380void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs);
381void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs); 381void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs);
382 382
383#ifdef CONFIG_SOC_AM33XX 383#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
384extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, 384extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
385 u16 clkctrl_offs); 385 u16 clkctrl_offs);
386extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, 386extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index a373d508799a..dc571f1d3b8a 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -162,7 +162,8 @@ static inline void omap3xxx_restart(enum reboot_mode mode, const char *cmd)
162} 162}
163#endif 163#endif
164 164
165#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) 165#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
166 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX)
166void omap44xx_restart(enum reboot_mode mode, const char *cmd); 167void omap44xx_restart(enum reboot_mode mode, const char *cmd);
167#else 168#else
168static inline void omap44xx_restart(enum reboot_mode mode, const char *cmd) 169static inline void omap44xx_restart(enum reboot_mode mode, const char *cmd)
@@ -248,7 +249,6 @@ static inline void __iomem *omap4_get_scu_base(void)
248} 249}
249#endif 250#endif
250 251
251extern void __init gic_init_irq(void);
252extern void gic_dist_disable(void); 252extern void gic_dist_disable(void);
253extern void gic_dist_enable(void); 253extern void gic_dist_enable(void);
254extern bool gic_dist_disabled(void); 254extern bool gic_dist_disabled(void);
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 592ba0a0ecf3..b6f8f348296e 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -297,33 +297,6 @@ static void omap_init_audio(void)
297static inline void omap_init_audio(void) {} 297static inline void omap_init_audio(void) {}
298#endif 298#endif
299 299
300#if defined(CONFIG_SND_OMAP_SOC_OMAP_HDMI) || \
301 defined(CONFIG_SND_OMAP_SOC_OMAP_HDMI_MODULE)
302
303static struct platform_device omap_hdmi_audio = {
304 .name = "omap-hdmi-audio",
305 .id = -1,
306};
307
308static void __init omap_init_hdmi_audio(void)
309{
310 struct omap_hwmod *oh;
311 struct platform_device *pdev;
312
313 oh = omap_hwmod_lookup("dss_hdmi");
314 if (!oh)
315 return;
316
317 pdev = omap_device_build("omap-hdmi-audio-dai", -1, oh, NULL, 0);
318 WARN(IS_ERR(pdev),
319 "Can't build omap_device for omap-hdmi-audio-dai.\n");
320
321 platform_device_register(&omap_hdmi_audio);
322}
323#else
324static inline void omap_init_hdmi_audio(void) {}
325#endif
326
327#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) 300#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
328 301
329#include <linux/platform_data/spi-omap2-mcspi.h> 302#include <linux/platform_data/spi-omap2-mcspi.h>
@@ -459,7 +432,6 @@ static int __init omap2_init_devices(void)
459 */ 432 */
460 omap_init_audio(); 433 omap_init_audio();
461 omap_init_camera(); 434 omap_init_camera();
462 omap_init_hdmi_audio();
463 omap_init_mbox(); 435 omap_init_mbox();
464 /* If dtb is there, the devices will be created dynamically */ 436 /* If dtb is there, the devices will be created dynamically */
465 if (!of_have_populated_dt()) { 437 if (!of_have_populated_dt()) {
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
index b8208b4b1bd9..f7492df1cbba 100644
--- a/arch/arm/mach-omap2/dsp.c
+++ b/arch/arm/mach-omap2/dsp.c
@@ -29,6 +29,7 @@
29#ifdef CONFIG_TIDSPBRIDGE_DVFS 29#ifdef CONFIG_TIDSPBRIDGE_DVFS
30#include "omap-pm.h" 30#include "omap-pm.h"
31#endif 31#endif
32#include "soc.h"
32 33
33#include <linux/platform_data/dsp-omap.h> 34#include <linux/platform_data/dsp-omap.h>
34 35
@@ -59,6 +60,9 @@ void __init omap_dsp_reserve_sdram_memblock(void)
59 phys_addr_t size = CONFIG_TIDSPBRIDGE_MEMPOOL_SIZE; 60 phys_addr_t size = CONFIG_TIDSPBRIDGE_MEMPOOL_SIZE;
60 phys_addr_t paddr; 61 phys_addr_t paddr;
61 62
63 if (!cpu_is_omap34xx())
64 return;
65
62 if (!size) 66 if (!size)
63 return; 67 return;
64 68
@@ -83,6 +87,9 @@ static int __init omap_dsp_init(void)
83 int err = -ENOMEM; 87 int err = -ENOMEM;
84 struct omap_dsp_platform_data *pdata = &omap_dsp_pdata; 88 struct omap_dsp_platform_data *pdata = &omap_dsp_pdata;
85 89
90 if (!cpu_is_omap34xx())
91 return 0;
92
86 pdata->phys_mempool_base = omap_dsp_get_mempool_base(); 93 pdata->phys_mempool_base = omap_dsp_get_mempool_base();
87 94
88 if (pdata->phys_mempool_base) { 95 if (pdata->phys_mempool_base) {
@@ -115,6 +122,9 @@ module_init(omap_dsp_init);
115 122
116static void __exit omap_dsp_exit(void) 123static void __exit omap_dsp_exit(void)
117{ 124{
125 if (!cpu_is_omap34xx())
126 return;
127
118 platform_device_unregister(omap_dsp_pdev); 128 platform_device_unregister(omap_dsp_pdev);
119} 129}
120module_exit(omap_dsp_exit); 130module_exit(omap_dsp_exit);
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 2c0c2816900f..8bc13380f0a0 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -1615,7 +1615,7 @@ static int gpmc_probe_dt(struct platform_device *pdev)
1615 return ret; 1615 return ret;
1616 } 1616 }
1617 1617
1618 for_each_child_of_node(pdev->dev.of_node, child) { 1618 for_each_available_child_of_node(pdev->dev.of_node, child) {
1619 1619
1620 if (!child->name) 1620 if (!child->name)
1621 continue; 1621 continue;
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 43969da5d50b..d42022f2a71e 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -649,6 +649,18 @@ void __init dra7xxx_check_revision(void)
649 } 649 }
650 break; 650 break;
651 651
652 case 0xb9bc:
653 switch (rev) {
654 case 0:
655 omap_revision = DRA722_REV_ES1_0;
656 break;
657 default:
658 /* If we have no new revisions */
659 omap_revision = DRA722_REV_ES1_0;
660 break;
661 }
662 break;
663
652 default: 664 default:
653 /* Unknown default to latest silicon rev as default*/ 665 /* Unknown default to latest silicon rev as default*/
654 pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%d)\n", 666 pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%d)\n",
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index fd88edeb027f..f62f7537d899 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -183,8 +183,10 @@ static int __init _omap_mux_get_by_name(struct omap_mux_partition *partition,
183 m0_entry = mux->muxnames[0]; 183 m0_entry = mux->muxnames[0];
184 184
185 /* First check for full name in mode0.muxmode format */ 185 /* First check for full name in mode0.muxmode format */
186 if (mode0_len && strncmp(muxname, m0_entry, mode0_len)) 186 if (mode0_len)
187 continue; 187 if (strncmp(muxname, m0_entry, mode0_len) ||
188 (strlen(m0_entry) != mode0_len))
189 continue;
188 190
189 /* Then check for muxmode only */ 191 /* Then check for muxmode only */
190 for (i = 0; i < OMAP_MUX_NR_MODES; i++) { 192 for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 326cd982a3cb..539e8106eb96 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -102,26 +102,6 @@ void __init omap_barriers_init(void)
102{} 102{}
103#endif 103#endif
104 104
105void __init gic_init_irq(void)
106{
107 void __iomem *omap_irq_base;
108
109 /* Static mapping, never released */
110 gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
111 BUG_ON(!gic_dist_base_addr);
112
113 twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_4K);
114 BUG_ON(!twd_base);
115
116 /* Static mapping, never released */
117 omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
118 BUG_ON(!omap_irq_base);
119
120 omap_wakeupgen_init();
121
122 gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
123}
124
125void gic_dist_disable(void) 105void gic_dist_disable(void)
126{ 106{
127 if (gic_dist_base_addr) 107 if (gic_dist_base_addr)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index f7bb435bb543..6c074f37cdd2 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -4251,9 +4251,9 @@ void __init omap_hwmod_init(void)
4251 soc_ops.enable_module = _omap4_enable_module; 4251 soc_ops.enable_module = _omap4_enable_module;
4252 soc_ops.disable_module = _omap4_disable_module; 4252 soc_ops.disable_module = _omap4_disable_module;
4253 soc_ops.wait_target_ready = _omap4_wait_target_ready; 4253 soc_ops.wait_target_ready = _omap4_wait_target_ready;
4254 soc_ops.assert_hardreset = _omap4_assert_hardreset; 4254 soc_ops.assert_hardreset = _am33xx_assert_hardreset;
4255 soc_ops.deassert_hardreset = _omap4_deassert_hardreset; 4255 soc_ops.deassert_hardreset = _am33xx_deassert_hardreset;
4256 soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; 4256 soc_ops.is_hardreset_asserted = _am33xx_is_hardreset_asserted;
4257 soc_ops.init_clkdm = _init_clkdm; 4257 soc_ops.init_clkdm = _init_clkdm;
4258 } else if (soc_is_am33xx()) { 4258 } else if (soc_is_am33xx()) {
4259 soc_ops.enable_module = _am33xx_enable_module; 4259 soc_ops.enable_module = _am33xx_enable_module;
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
index 290213f2cbe3..1103aa0e0d29 100644
--- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -2020,6 +2020,77 @@ static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
2020 }, 2020 },
2021}; 2021};
2022 2022
2023/*
2024 * 'ocp2scp' class
2025 * bridge to transform ocp interface protocol to scp (serial control port)
2026 * protocol
2027 */
2028/* ocp2scp3 */
2029static struct omap_hwmod omap54xx_ocp2scp3_hwmod;
2030/* l4_cfg -> ocp2scp3 */
2031static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3 = {
2032 .master = &omap54xx_l4_cfg_hwmod,
2033 .slave = &omap54xx_ocp2scp3_hwmod,
2034 .clk = "l4_root_clk_div",
2035 .user = OCP_USER_MPU | OCP_USER_SDMA,
2036};
2037
2038static struct omap_hwmod omap54xx_ocp2scp3_hwmod = {
2039 .name = "ocp2scp3",
2040 .class = &omap54xx_ocp2scp_hwmod_class,
2041 .clkdm_name = "l3init_clkdm",
2042 .prcm = {
2043 .omap4 = {
2044 .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
2045 .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
2046 .modulemode = MODULEMODE_HWCTRL,
2047 },
2048 },
2049};
2050
2051/*
2052 * 'sata' class
2053 * sata: serial ata interface gen2 compliant ( 1 rx/ 1 tx)
2054 */
2055
2056static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
2057 .sysc_offs = 0x0000,
2058 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2059 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2060 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2061 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2062 .sysc_fields = &omap_hwmod_sysc_type2,
2063};
2064
2065static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
2066 .name = "sata",
2067 .sysc = &omap54xx_sata_sysc,
2068};
2069
2070/* sata */
2071static struct omap_hwmod omap54xx_sata_hwmod = {
2072 .name = "sata",
2073 .class = &omap54xx_sata_hwmod_class,
2074 .clkdm_name = "l3init_clkdm",
2075 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2076 .main_clk = "func_48m_fclk",
2077 .mpu_rt_idx = 1,
2078 .prcm = {
2079 .omap4 = {
2080 .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2081 .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2082 .modulemode = MODULEMODE_SWCTRL,
2083 },
2084 },
2085};
2086
2087/* l4_cfg -> sata */
2088static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
2089 .master = &omap54xx_l4_cfg_hwmod,
2090 .slave = &omap54xx_sata_hwmod,
2091 .clk = "l3_iclk_div",
2092 .user = OCP_USER_MPU | OCP_USER_SDMA,
2093};
2023 2094
2024/* 2095/*
2025 * Interfaces 2096 * Interfaces
@@ -2765,6 +2836,8 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
2765 &omap54xx_l4_cfg__usb_tll_hs, 2836 &omap54xx_l4_cfg__usb_tll_hs,
2766 &omap54xx_l4_cfg__usb_otg_ss, 2837 &omap54xx_l4_cfg__usb_otg_ss,
2767 &omap54xx_l4_wkup__wd_timer2, 2838 &omap54xx_l4_wkup__wd_timer2,
2839 &omap54xx_l4_cfg__ocp2scp3,
2840 &omap54xx_l4_cfg__sata,
2768 NULL, 2841 NULL,
2769}; 2842};
2770 2843
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 20b4398cec05..284324f2b98a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1268,9 +1268,6 @@ static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1268}; 1268};
1269 1269
1270/* sata */ 1270/* sata */
1271static struct omap_hwmod_opt_clk sata_opt_clks[] = {
1272 { .role = "ref_clk", .clk = "sata_ref_clk" },
1273};
1274 1271
1275static struct omap_hwmod dra7xx_sata_hwmod = { 1272static struct omap_hwmod dra7xx_sata_hwmod = {
1276 .name = "sata", 1273 .name = "sata",
@@ -1278,6 +1275,7 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
1278 .clkdm_name = "l3init_clkdm", 1275 .clkdm_name = "l3init_clkdm",
1279 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, 1276 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1280 .main_clk = "func_48m_fclk", 1277 .main_clk = "func_48m_fclk",
1278 .mpu_rt_idx = 1,
1281 .prcm = { 1279 .prcm = {
1282 .omap4 = { 1280 .omap4 = {
1283 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET, 1281 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
@@ -1285,8 +1283,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
1285 .modulemode = MODULEMODE_SWCTRL, 1283 .modulemode = MODULEMODE_SWCTRL,
1286 }, 1284 },
1287 }, 1285 },
1288 .opt_clks = sata_opt_clks,
1289 .opt_clks_cnt = ARRAY_SIZE(sata_opt_clks),
1290}; 1286};
1291 1287
1292/* 1288/*
@@ -1731,8 +1727,20 @@ static struct omap_hwmod dra7xx_uart6_hwmod = {
1731 * 1727 *
1732 */ 1728 */
1733 1729
1730static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
1731 .rev_offs = 0x0000,
1732 .sysc_offs = 0x0010,
1733 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
1734 SYSC_HAS_SIDLEMODE),
1735 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1736 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1737 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1738 .sysc_fields = &omap_hwmod_sysc_type2,
1739};
1740
1734static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = { 1741static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
1735 .name = "usb_otg_ss", 1742 .name = "usb_otg_ss",
1743 .sysc = &dra7xx_usb_otg_ss_sysc,
1736}; 1744};
1737 1745
1738/* usb_otg_ss1 */ 1746/* usb_otg_ss1 */
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index 106132db532b..cbefbd7cfdb5 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -35,6 +35,8 @@
35#define OMAP3430_LOGICSTATEST_MASK (1 << 2) 35#define OMAP3430_LOGICSTATEST_MASK (1 << 2)
36#define OMAP3430_LASTLOGICSTATEENTERED_MASK (1 << 2) 36#define OMAP3430_LASTLOGICSTATEENTERED_MASK (1 << 2)
37#define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0) 37#define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0)
38#define OMAP3430_GRPSEL_MCBSP5_MASK (1 << 10)
39#define OMAP3430_GRPSEL_MCBSP1_MASK (1 << 9)
38#define OMAP3630_GRPSEL_UART4_MASK (1 << 18) 40#define OMAP3630_GRPSEL_UART4_MASK (1 << 18)
39#define OMAP3430_GRPSEL_GPIO6_MASK (1 << 17) 41#define OMAP3430_GRPSEL_GPIO6_MASK (1 << 17)
40#define OMAP3430_GRPSEL_GPIO5_MASK (1 << 16) 42#define OMAP3430_GRPSEL_GPIO5_MASK (1 << 16)
@@ -42,6 +44,10 @@
42#define OMAP3430_GRPSEL_GPIO3_MASK (1 << 14) 44#define OMAP3430_GRPSEL_GPIO3_MASK (1 << 14)
43#define OMAP3430_GRPSEL_GPIO2_MASK (1 << 13) 45#define OMAP3430_GRPSEL_GPIO2_MASK (1 << 13)
44#define OMAP3430_GRPSEL_UART3_MASK (1 << 11) 46#define OMAP3430_GRPSEL_UART3_MASK (1 << 11)
47#define OMAP3430_GRPSEL_GPT8_MASK (1 << 9)
48#define OMAP3430_GRPSEL_GPT7_MASK (1 << 8)
49#define OMAP3430_GRPSEL_GPT6_MASK (1 << 7)
50#define OMAP3430_GRPSEL_GPT5_MASK (1 << 6)
45#define OMAP3430_GRPSEL_MCBSP4_MASK (1 << 2) 51#define OMAP3430_GRPSEL_MCBSP4_MASK (1 << 2)
46#define OMAP3430_GRPSEL_MCBSP3_MASK (1 << 1) 52#define OMAP3430_GRPSEL_MCBSP3_MASK (1 << 1)
47#define OMAP3430_GRPSEL_MCBSP2_MASK (1 << 0) 53#define OMAP3430_GRPSEL_MCBSP2_MASK (1 << 0)
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index de2a34c423a7..01ca8086fb6c 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -462,6 +462,7 @@ IS_OMAP_TYPE(3430, 0x3430)
462#define DRA7XX_CLASS 0x07000000 462#define DRA7XX_CLASS 0x07000000
463#define DRA752_REV_ES1_0 (DRA7XX_CLASS | (0x52 << 16) | (0x10 << 8)) 463#define DRA752_REV_ES1_0 (DRA7XX_CLASS | (0x52 << 16) | (0x10 << 8))
464#define DRA752_REV_ES1_1 (DRA7XX_CLASS | (0x52 << 16) | (0x11 << 8)) 464#define DRA752_REV_ES1_1 (DRA7XX_CLASS | (0x52 << 16) | (0x11 << 8))
465#define DRA722_REV_ES1_0 (DRA7XX_CLASS | (0x22 << 16) | (0x10 << 8))
465 466
466void omap2xxx_check_revision(void); 467void omap2xxx_check_revision(void);
467void omap3xxx_check_revision(void); 468void omap3xxx_check_revision(void);
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 4d09469320c8..42d4753683ce 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -12,8 +12,81 @@
12 12
13#include <linux/clk-provider.h> 13#include <linux/clk-provider.h>
14#include <linux/clocksource.h> 14#include <linux/clocksource.h>
15#include <linux/delay.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/of_address.h>
19#include <linux/of_irq.h>
20#include <linux/of_platform.h>
21#include <linux/io.h>
22#include <linux/reboot.h>
15 23
16#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26#include <asm/system_misc.h>
27
28#define SUN4I_WATCHDOG_CTRL_REG 0x00
29#define SUN4I_WATCHDOG_CTRL_RESTART BIT(0)
30#define SUN4I_WATCHDOG_MODE_REG 0x04
31#define SUN4I_WATCHDOG_MODE_ENABLE BIT(0)
32#define SUN4I_WATCHDOG_MODE_RESET_ENABLE BIT(1)
33
34#define SUN6I_WATCHDOG1_IRQ_REG 0x00
35#define SUN6I_WATCHDOG1_CTRL_REG 0x10
36#define SUN6I_WATCHDOG1_CTRL_RESTART BIT(0)
37#define SUN6I_WATCHDOG1_CONFIG_REG 0x14
38#define SUN6I_WATCHDOG1_CONFIG_RESTART BIT(0)
39#define SUN6I_WATCHDOG1_CONFIG_IRQ BIT(1)
40#define SUN6I_WATCHDOG1_MODE_REG 0x18
41#define SUN6I_WATCHDOG1_MODE_ENABLE BIT(0)
42
43static void __iomem *wdt_base;
44
45static void sun4i_restart(enum reboot_mode mode, const char *cmd)
46{
47 if (!wdt_base)
48 return;
49
50 /* Enable timer and set reset bit in the watchdog */
51 writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
52 wdt_base + SUN4I_WATCHDOG_MODE_REG);
53
54 /*
55 * Restart the watchdog. The default (and lowest) interval
56 * value for the watchdog is 0.5s.
57 */
58 writel(SUN4I_WATCHDOG_CTRL_RESTART, wdt_base + SUN4I_WATCHDOG_CTRL_REG);
59
60 while (1) {
61 mdelay(5);
62 writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
63 wdt_base + SUN4I_WATCHDOG_MODE_REG);
64 }
65}
66
67static struct of_device_id sunxi_restart_ids[] = {
68 { .compatible = "allwinner,sun4i-a10-wdt" },
69 { /*sentinel*/ }
70};
71
72static void sunxi_setup_restart(void)
73{
74 struct device_node *np;
75
76 np = of_find_matching_node(NULL, sunxi_restart_ids);
77 if (WARN(!np, "unable to setup watchdog restart"))
78 return;
79
80 wdt_base = of_iomap(np, 0);
81 WARN(!wdt_base, "failed to map watchdog base address");
82}
83
84static void __init sunxi_dt_init(void)
85{
86 sunxi_setup_restart();
87
88 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
89}
17 90
18static const char * const sunxi_board_dt_compat[] = { 91static const char * const sunxi_board_dt_compat[] = {
19 "allwinner,sun4i-a10", 92 "allwinner,sun4i-a10",
@@ -23,7 +96,9 @@ static const char * const sunxi_board_dt_compat[] = {
23}; 96};
24 97
25DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)") 98DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
99 .init_machine = sunxi_dt_init,
26 .dt_compat = sunxi_board_dt_compat, 100 .dt_compat = sunxi_board_dt_compat,
101 .restart = sun4i_restart,
27MACHINE_END 102MACHINE_END
28 103
29static const char * const sun6i_board_dt_compat[] = { 104static const char * const sun6i_board_dt_compat[] = {
@@ -51,7 +126,9 @@ static const char * const sun7i_board_dt_compat[] = {
51}; 126};
52 127
53DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family") 128DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family")
129 .init_machine = sunxi_dt_init,
54 .dt_compat = sun7i_board_dt_compat, 130 .dt_compat = sun7i_board_dt_compat,
131 .restart = sun4i_restart,
55MACHINE_END 132MACHINE_END
56 133
57static const char * const sun8i_board_dt_compat[] = { 134static const char * const sun8i_board_dt_compat[] = {
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 076172b69422..7c3fb41a462e 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -664,7 +664,7 @@ static int l2c310_cpu_enable_flz(struct notifier_block *nb, unsigned long act, v
664 664
665static void __init l2c310_enable(void __iomem *base, u32 aux, unsigned num_lock) 665static void __init l2c310_enable(void __iomem *base, u32 aux, unsigned num_lock)
666{ 666{
667 unsigned rev = readl_relaxed(base + L2X0_CACHE_ID) & L2X0_CACHE_ID_PART_MASK; 667 unsigned rev = readl_relaxed(base + L2X0_CACHE_ID) & L2X0_CACHE_ID_RTL_MASK;
668 bool cortex_a9 = read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9; 668 bool cortex_a9 = read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9;
669 669
670 if (rev >= L310_CACHE_ID_RTL_R2P0) { 670 if (rev >= L310_CACHE_ID_RTL_R2P0) {
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 13:20:44 -0500