diff options
author | Mark Brown <broonie@sirena.org.uk> | 2008-03-04 05:14:23 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-04-19 06:29:03 -0400 |
commit | 60bfe7fa3dc13fe90d273371b65ae3ec89583c52 (patch) | |
tree | 8ba51a09944c0e7e3b0d7bef2c20a15df4c673c1 /arch/arm | |
parent | 27b98a671ff4cda89ba279452115000da59a9067 (diff) |
[ARM] 4832/2: Support AC97CLK on PXA3xx via the clock API
The AC97 clock rate on PXA3xx is generated with a configurable divider
from sys_pll.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-pxa/pxa3xx.c | 30 |
1 files changed, 28 insertions, 2 deletions
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index 54c9e8371a21..93f3236b4100 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c | |||
@@ -110,6 +110,25 @@ unsigned int pxa3xx_get_memclk_frequency_10khz(void) | |||
110 | } | 110 | } |
111 | 111 | ||
112 | /* | 112 | /* |
113 | * Return the current AC97 clock frequency. | ||
114 | */ | ||
115 | static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk) | ||
116 | { | ||
117 | unsigned long rate = 312000000; | ||
118 | unsigned long ac97_div; | ||
119 | |||
120 | ac97_div = AC97_DIV; | ||
121 | |||
122 | /* This may loose precision for some rates but won't for the | ||
123 | * standard 24.576MHz. | ||
124 | */ | ||
125 | rate /= (ac97_div >> 12) & 0x7fff; | ||
126 | rate *= (ac97_div & 0xfff); | ||
127 | |||
128 | return rate; | ||
129 | } | ||
130 | |||
131 | /* | ||
113 | * Return the current HSIO bus clock frequency | 132 | * Return the current HSIO bus clock frequency |
114 | */ | 133 | */ |
115 | static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) | 134 | static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) |
@@ -156,6 +175,12 @@ static const struct clkops clk_pxa3xx_hsio_ops = { | |||
156 | .getrate = clk_pxa3xx_hsio_getrate, | 175 | .getrate = clk_pxa3xx_hsio_getrate, |
157 | }; | 176 | }; |
158 | 177 | ||
178 | static const struct clkops clk_pxa3xx_ac97_ops = { | ||
179 | .enable = clk_pxa3xx_cken_enable, | ||
180 | .disable = clk_pxa3xx_cken_disable, | ||
181 | .getrate = clk_pxa3xx_ac97_getrate, | ||
182 | }; | ||
183 | |||
159 | static void clk_pout_enable(struct clk *clk) | 184 | static void clk_pout_enable(struct clk *clk) |
160 | { | 185 | { |
161 | OSCC |= OSCC_PEN; | 186 | OSCC |= OSCC_PEN; |
@@ -197,8 +222,9 @@ static struct clk pxa3xx_clks[] = { | |||
197 | .delay = 70, | 222 | .delay = 70, |
198 | }, | 223 | }, |
199 | 224 | ||
200 | PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev), | 225 | PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev), |
201 | PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL), | 226 | PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL), |
227 | PXA3xx_CK("AC97CLK", AC97, &clk_pxa3xx_ac97_ops, NULL), | ||
202 | 228 | ||
203 | PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), | 229 | PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), |
204 | PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), | 230 | PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), |