aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm
diff options
context:
space:
mode:
authorTomasz Figa <t.figa@samsung.com>2014-07-02 13:42:03 -0400
committerKukjin Kim <kgene.kim@samsung.com>2014-07-18 15:24:59 -0400
commit32726d2d5502302ba5753854f5f2f12ba22681c4 (patch)
treee432c5599c79ea3bdf7304477cdebb39e3a82c26 /arch/arm
parentf73d4cb681d2ede6d31974dde3ecce7a3ae8e8ff (diff)
ARM: SAMSUNG: Remove legacy clock code
Since S5PV210 now has a complete clock driver using Common Clock Framework, there is no reason to keep the old code. Remove it together with the whole legacy Samsung-specific clock framework which no longer has any users. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/mach-exynos/pm.c1
-rw-r--r--arch/arm/mach-s3c24xx/common.c2
-rw-r--r--arch/arm/mach-s3c24xx/iotiming-s3c2412.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-h1940.c5
-rw-r--r--arch/arm/mach-s3c24xx/mach-jive.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-smdk2413.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-smdk2416.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-smdk2443.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-vstms.c1
-rw-r--r--arch/arm/mach-s3c24xx/s3c2410.c6
-rw-r--r--arch/arm/mach-s3c24xx/s3c2412.c6
-rw-r--r--arch/arm/mach-s3c24xx/s3c2442.c1
-rw-r--r--arch/arm/mach-s3c24xx/s3c244x.c6
-rw-r--r--arch/arm/mach-s3c64xx/mach-anw6410.c1
-rw-r--r--arch/arm/mach-s3c64xx/mach-crag6410.c1
-rw-r--r--arch/arm/mach-s3c64xx/mach-hmt.c1
-rw-r--r--arch/arm/mach-s3c64xx/mach-ncp.c1
-rw-r--r--arch/arm/mach-s3c64xx/mach-smartq.c1
-rw-r--r--arch/arm/mach-s3c64xx/mach-smdk6400.c1
-rw-r--r--arch/arm/mach-s3c64xx/mach-smdk6410.c1
-rw-r--r--arch/arm/mach-s3c64xx/s3c6400.c1
-rw-r--r--arch/arm/mach-s3c64xx/s3c6410.c1
-rw-r--r--arch/arm/mach-s5pv210/Kconfig9
-rw-r--r--arch/arm/mach-s5pv210/Makefile1
-rw-r--r--arch/arm/mach-s5pv210/clock.c1365
-rw-r--r--arch/arm/mach-s5pv210/common.c16
-rw-r--r--arch/arm/mach-s5pv210/common.h6
-rw-r--r--arch/arm/mach-s5pv210/mach-goni.c1
-rw-r--r--arch/arm/mach-s5pv210/mach-smdkv210.c1
-rw-r--r--arch/arm/mach-s5pv210/pm.c48
-rw-r--r--arch/arm/plat-samsung/Kconfig18
-rw-r--r--arch/arm/plat-samsung/Makefile5
-rw-r--r--arch/arm/plat-samsung/clock-clksrc.c212
-rw-r--r--arch/arm/plat-samsung/clock.c539
-rw-r--r--arch/arm/plat-samsung/include/plat/clock-clksrc.h83
-rw-r--r--arch/arm/plat-samsung/include/plat/clock.h152
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu-freq-core.h3
-rw-r--r--arch/arm/plat-samsung/include/plat/pll.h323
-rw-r--r--arch/arm/plat-samsung/include/plat/s5p-clock.h65
-rw-r--r--arch/arm/plat-samsung/init.c1
-rw-r--r--arch/arm/plat-samsung/s5p-clock.c294
42 files changed, 6 insertions, 3179 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f4396fd8d6b9..c0c1c3f83679 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -765,6 +765,7 @@ config ARCH_S5PV210
765 select ATAGS 765 select ATAGS
766 select CLKDEV_LOOKUP 766 select CLKDEV_LOOKUP
767 select CLKSRC_SAMSUNG_PWM 767 select CLKSRC_SAMSUNG_PWM
768 select COMMON_CLK_SAMSUNG
768 select CPU_V7 769 select CPU_V7
769 select GENERIC_CLOCKEVENTS 770 select GENERIC_CLOCKEVENTS
770 select GPIO_SAMSUNG 771 select GPIO_SAMSUNG
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index f127c0cefbb8..a8b5af545d26 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -28,7 +28,6 @@
28#include <asm/suspend.h> 28#include <asm/suspend.h>
29 29
30#include <plat/pm-common.h> 30#include <plat/pm-common.h>
31#include <plat/pll.h>
32#include <plat/regs-srom.h> 31#include <plat/regs-srom.h>
33 32
34#include <mach/map.h> 33#include <mach/map.h>
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index c0763b837745..44fa95df9262 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -49,9 +49,7 @@
49 49
50#include <plat/cpu.h> 50#include <plat/cpu.h>
51#include <plat/devs.h> 51#include <plat/devs.h>
52#include <plat/clock.h>
53#include <plat/cpu-freq.h> 52#include <plat/cpu-freq.h>
54#include <plat/pll.h>
55#include <plat/pwm-core.h> 53#include <plat/pwm-core.h>
56#include <plat/watchdog-reset.h> 54#include <plat/watchdog-reset.h>
57 55
diff --git a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
index bd064c05c473..28b13951de87 100644
--- a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
@@ -29,7 +29,6 @@
29 29
30#include <plat/cpu.h> 30#include <plat/cpu.h>
31#include <plat/cpu-freq-core.h> 31#include <plat/cpu-freq-core.h>
32#include <plat/clock.h>
33 32
34#include <mach/s3c2412.h> 33#include <mach/s3c2412.h>
35 34
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index fbf5487ae5d1..c9a99bbad545 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -60,7 +60,6 @@
60#include <plat/cpu.h> 60#include <plat/cpu.h>
61#include <plat/devs.h> 61#include <plat/devs.h>
62#include <plat/gpio-cfg.h> 62#include <plat/gpio-cfg.h>
63#include <plat/pll.h>
64#include <plat/pm.h> 63#include <plat/pm.h>
65#include <plat/samsung-time.h> 64#include <plat/samsung-time.h>
66 65
@@ -73,6 +72,10 @@
73 72
74#define H1940_LATCH_BIT(x) (1 << ((x) + 16 - S3C_GPIO_END)) 73#define H1940_LATCH_BIT(x) (1 << ((x) + 16 - S3C_GPIO_END))
75 74
75#define S3C24XX_PLL_MDIV_SHIFT (12)
76#define S3C24XX_PLL_PDIV_SHIFT (4)
77#define S3C24XX_PLL_SDIV_SHIFT (0)
78
76static struct map_desc h1940_iodesc[] __initdata = { 79static struct map_desc h1940_iodesc[] __initdata = {
77 [0] = { 80 [0] = {
78 .virtual = (unsigned long)H1940_LATCH, 81 .virtual = (unsigned long)H1940_LATCH,
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index e81ea82c55f9..e647b47244a9 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -48,7 +48,6 @@
48#include <linux/mtd/partitions.h> 48#include <linux/mtd/partitions.h>
49 49
50#include <plat/gpio-cfg.h> 50#include <plat/gpio-cfg.h>
51#include <plat/clock.h>
52#include <plat/devs.h> 51#include <plat/devs.h>
53#include <plat/cpu.h> 52#include <plat/cpu.h>
54#include <plat/pm.h> 53#include <plat/pm.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c
index fb3b80e44595..10726bf84920 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2413.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c
@@ -43,7 +43,6 @@
43#include <mach/gpio-samsung.h> 43#include <mach/gpio-samsung.h>
44#include <mach/fb.h> 44#include <mach/fb.h>
45 45
46#include <plat/clock.h>
47#include <plat/devs.h> 46#include <plat/devs.h>
48#include <plat/cpu.h> 47#include <plat/cpu.h>
49#include <plat/samsung-time.h> 48#include <plat/samsung-time.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index fa6f30d23601..24189e8e8560 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -44,7 +44,6 @@
44#include <linux/platform_data/i2c-s3c2410.h> 44#include <linux/platform_data/i2c-s3c2410.h>
45 45
46#include <plat/gpio-cfg.h> 46#include <plat/gpio-cfg.h>
47#include <plat/clock.h>
48#include <plat/devs.h> 47#include <plat/devs.h>
49#include <plat/cpu.h> 48#include <plat/cpu.h>
50#include <linux/platform_data/mtd-nand-s3c2410.h> 49#include <linux/platform_data/mtd-nand-s3c2410.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c
index ef5d5ea33182..0ed77614dcfe 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2443.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c
@@ -38,7 +38,6 @@
38#include <mach/fb.h> 38#include <mach/fb.h>
39#include <linux/platform_data/i2c-s3c2410.h> 39#include <linux/platform_data/i2c-s3c2410.h>
40 40
41#include <plat/clock.h>
42#include <plat/devs.h> 41#include <plat/devs.h>
43#include <plat/cpu.h> 42#include <plat/cpu.h>
44#include <plat/samsung-time.h> 43#include <plat/samsung-time.h>
diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c
index 9104c2be36c9..9d4f64750698 100644
--- a/arch/arm/mach-s3c24xx/mach-vstms.c
+++ b/arch/arm/mach-s3c24xx/mach-vstms.c
@@ -42,7 +42,6 @@
42#include <linux/platform_data/i2c-s3c2410.h> 42#include <linux/platform_data/i2c-s3c2410.h>
43#include <linux/platform_data/mtd-nand-s3c2410.h> 43#include <linux/platform_data/mtd-nand-s3c2410.h>
44 44
45#include <plat/clock.h>
46#include <plat/devs.h> 45#include <plat/devs.h>
47#include <plat/cpu.h> 46#include <plat/cpu.h>
48#include <plat/samsung-time.h> 47#include <plat/samsung-time.h>
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index 7eab88829883..5ffe828cd659 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -41,8 +41,6 @@
41 41
42#include <plat/cpu.h> 42#include <plat/cpu.h>
43#include <plat/devs.h> 43#include <plat/devs.h>
44#include <plat/clock.h>
45#include <plat/pll.h>
46#include <plat/pm.h> 44#include <plat/pm.h>
47#include <plat/watchdog-reset.h> 45#include <plat/watchdog-reset.h>
48 46
@@ -83,10 +81,6 @@ void __init s3c2410_map_io(void)
83 iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc)); 81 iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
84} 82}
85 83
86void __init_or_cpufreq s3c2410_setup_clocks(void)
87{
88}
89
90struct bus_type s3c2410_subsys = { 84struct bus_type s3c2410_subsys = {
91 .name = "s3c2410-core", 85 .name = "s3c2410-core",
92 .dev_name = "s3c2410-core", 86 .dev_name = "s3c2410-core",
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index d49f52fbc842..569f3f5a6c71 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -37,12 +37,10 @@
37#include <mach/regs-clock.h> 37#include <mach/regs-clock.h>
38#include <mach/regs-gpio.h> 38#include <mach/regs-gpio.h>
39 39
40#include <plat/clock.h>
41#include <plat/cpu.h> 40#include <plat/cpu.h>
42#include <plat/cpu-freq.h> 41#include <plat/cpu-freq.h>
43#include <plat/devs.h> 42#include <plat/devs.h>
44#include <plat/nand-core.h> 43#include <plat/nand-core.h>
45#include <plat/pll.h>
46#include <plat/pm.h> 44#include <plat/pm.h>
47#include <plat/regs-spi.h> 45#include <plat/regs-spi.h>
48 46
@@ -171,10 +169,6 @@ void __init s3c2412_map_io(void)
171 iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc)); 169 iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
172} 170}
173 171
174void __init_or_cpufreq s3c2412_setup_clocks(void)
175{
176}
177
178/* need to register the subsystem before we actually register the device, and 172/* need to register the subsystem before we actually register the device, and
179 * we also need to ensure that it has been initialised before any of the 173 * we also need to ensure that it has been initialised before any of the
180 * drivers even try to use it (even if not on an s3c2412 based system) 174 * drivers even try to use it (even if not on an s3c2412 based system)
diff --git a/arch/arm/mach-s3c24xx/s3c2442.c b/arch/arm/mach-s3c24xx/s3c2442.c
index fb9da2b603a2..7b043349f1c8 100644
--- a/arch/arm/mach-s3c24xx/s3c2442.c
+++ b/arch/arm/mach-s3c24xx/s3c2442.c
@@ -43,7 +43,6 @@
43 43
44#include <mach/regs-clock.h> 44#include <mach/regs-clock.h>
45 45
46#include <plat/clock.h>
47#include <plat/cpu.h> 46#include <plat/cpu.h>
48#include <plat/pm.h> 47#include <plat/pm.h>
49 48
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index 4a64bcc9eb51..d1c3e65785a1 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -38,11 +38,9 @@
38#include <mach/regs-clock.h> 38#include <mach/regs-clock.h>
39#include <mach/regs-gpio.h> 39#include <mach/regs-gpio.h>
40 40
41#include <plat/clock.h>
42#include <plat/devs.h> 41#include <plat/devs.h>
43#include <plat/cpu.h> 42#include <plat/cpu.h>
44#include <plat/pm.h> 43#include <plat/pm.h>
45#include <plat/pll.h>
46#include <plat/nand-core.h> 44#include <plat/nand-core.h>
47#include <plat/watchdog-reset.h> 45#include <plat/watchdog-reset.h>
48 46
@@ -78,10 +76,6 @@ void __init s3c244x_map_io(void)
78 s3c2410_device_dclk.name = "s3c2440-dclk"; 76 s3c2410_device_dclk.name = "s3c2440-dclk";
79} 77}
80 78
81void __init_or_cpufreq s3c244x_setup_clocks(void)
82{
83}
84
85/* Since the S3C2442 and S3C2440 share items, put both subsystems here */ 79/* Since the S3C2442 and S3C2440 share items, put both subsystems here */
86 80
87struct bus_type s3c2440_subsys = { 81struct bus_type s3c2440_subsys = {
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index 55eb6a69655b..60576dfbea8d 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -45,7 +45,6 @@
45#include <linux/platform_data/i2c-s3c2410.h> 45#include <linux/platform_data/i2c-s3c2410.h>
46#include <plat/fb.h> 46#include <plat/fb.h>
47 47
48#include <plat/clock.h>
49#include <plat/devs.h> 48#include <plat/devs.h>
50#include <plat/cpu.h> 49#include <plat/cpu.h>
51#include <mach/regs-gpio.h> 50#include <mach/regs-gpio.h>
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 4b0199fff9f5..fe116334afda 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -58,7 +58,6 @@
58#include <linux/platform_data/spi-s3c64xx.h> 58#include <linux/platform_data/spi-s3c64xx.h>
59 59
60#include <plat/keypad.h> 60#include <plat/keypad.h>
61#include <plat/clock.h>
62#include <plat/devs.h> 61#include <plat/devs.h>
63#include <plat/cpu.h> 62#include <plat/cpu.h>
64#include <plat/adc.h> 63#include <plat/adc.h>
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index 72cee08c8bf5..19e8feb908fd 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -39,7 +39,6 @@
39#include <plat/fb.h> 39#include <plat/fb.h>
40#include <linux/platform_data/mtd-nand-s3c2410.h> 40#include <linux/platform_data/mtd-nand-s3c2410.h>
41 41
42#include <plat/clock.h>
43#include <plat/devs.h> 42#include <plat/devs.h>
44#include <plat/cpu.h> 43#include <plat/cpu.h>
45#include <plat/samsung-time.h> 44#include <plat/samsung-time.h>
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index 67f06a9ae656..4bae7dc49eea 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -40,7 +40,6 @@
40#include <linux/platform_data/i2c-s3c2410.h> 40#include <linux/platform_data/i2c-s3c2410.h>
41#include <plat/fb.h> 41#include <plat/fb.h>
42 42
43#include <plat/clock.h>
44#include <plat/devs.h> 43#include <plat/devs.h>
45#include <plat/cpu.h> 44#include <plat/cpu.h>
46#include <plat/samsung-time.h> 45#include <plat/samsung-time.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index 78dd6f73c072..b3d13537a7f0 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -28,7 +28,6 @@
28#include <mach/regs-gpio.h> 28#include <mach/regs-gpio.h>
29#include <mach/gpio-samsung.h> 29#include <mach/gpio-samsung.h>
30 30
31#include <plat/clock.h>
32#include <plat/cpu.h> 31#include <plat/cpu.h>
33#include <plat/devs.h> 32#include <plat/devs.h>
34#include <linux/platform_data/i2c-s3c2410.h> 33#include <linux/platform_data/i2c-s3c2410.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index c85d1cbe769f..910749768340 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -30,7 +30,6 @@
30#include <mach/hardware.h> 30#include <mach/hardware.h>
31#include <mach/map.h> 31#include <mach/map.h>
32 32
33#include <plat/clock.h>
34#include <plat/devs.h> 33#include <plat/devs.h>
35#include <plat/cpu.h> 34#include <plat/cpu.h>
36#include <linux/platform_data/i2c-s3c2410.h> 35#include <linux/platform_data/i2c-s3c2410.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index c6a8b2ab0240..1dc86d76b530 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -63,7 +63,6 @@
63#include <plat/fb.h> 63#include <plat/fb.h>
64#include <plat/gpio-cfg.h> 64#include <plat/gpio-cfg.h>
65 65
66#include <plat/clock.h>
67#include <plat/devs.h> 66#include <plat/devs.h>
68#include <plat/cpu.h> 67#include <plat/cpu.h>
69#include <plat/adc.h> 68#include <plat/adc.h>
diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c
index 8c42807bf579..1ce48c54cd9c 100644
--- a/arch/arm/mach-s3c64xx/s3c6400.c
+++ b/arch/arm/mach-s3c64xx/s3c6400.c
@@ -39,7 +39,6 @@
39 39
40#include <plat/cpu.h> 40#include <plat/cpu.h>
41#include <plat/devs.h> 41#include <plat/devs.h>
42#include <plat/clock.h>
43#include <plat/sdhci.h> 42#include <plat/sdhci.h>
44#include <plat/iic-core.h> 43#include <plat/iic-core.h>
45#include <plat/onenand-core.h> 44#include <plat/onenand-core.h>
diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c
index 5be3f09bac92..b2a7930548d9 100644
--- a/arch/arm/mach-s3c64xx/s3c6410.c
+++ b/arch/arm/mach-s3c64xx/s3c6410.c
@@ -40,7 +40,6 @@
40 40
41#include <plat/cpu.h> 41#include <plat/cpu.h>
42#include <plat/devs.h> 42#include <plat/devs.h>
43#include <plat/clock.h>
44#include <plat/sdhci.h> 43#include <plat/sdhci.h>
45#include <plat/ata-core.h> 44#include <plat/ata-core.h>
46#include <plat/adc-core.h> 45#include <plat/adc-core.h>
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 60785cea7c61..f60f2862856d 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -13,7 +13,6 @@ config CPU_S5PV210
13 bool 13 bool
14 select ARM_AMBA 14 select ARM_AMBA
15 select PL330_DMA if DMADEVICES 15 select PL330_DMA if DMADEVICES
16 select S5P_CLOCK if !COMMON_CLK
17 select S5P_EXT_INT 16 select S5P_EXT_INT
18 select S5P_PM if PM 17 select S5P_PM if PM
19 select S5P_SLEEP if PM 18 select S5P_SLEEP if PM
@@ -71,14 +70,6 @@ config S5PV210_SETUP_USB_PHY
71 help 70 help
72 Common setup code for USB PHY controller 71 Common setup code for USB PHY controller
73 72
74config COMMON_CLK_S5PV210
75 bool "Common Clock Framework support"
76 default y
77 select COMMON_CLK_SAMSUNG
78 help
79 Enable this option to use new clock driver
80 based on Common Clock Framework.
81
82menu "S5PC110 Machines" 73menu "S5PC110 Machines"
83 74
84config MACH_AQUILA 75config MACH_AQUILA
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index d1a493aea1cf..08358bbccb88 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -13,7 +13,6 @@ obj- :=
13# Core 13# Core
14 14
15obj-y += common.o 15obj-y += common.o
16obj-$(CONFIG_S5P_CLOCK) += clock.o
17obj-$(CONFIG_PM) += pm.o 16obj-$(CONFIG_PM) += pm.o
18 17
19obj-y += dma.o 18obj-y += dma.o
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
deleted file mode 100644
index ca463724a3df..000000000000
--- a/arch/arm/mach-s5pv210/clock.c
+++ /dev/null
@@ -1,1365 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/clock.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV210 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/clk.h>
20#include <linux/device.h>
21#include <linux/io.h>
22
23#include <mach/map.h>
24
25#include <plat/cpu-freq.h>
26#include <mach/regs-clock.h>
27#include <plat/clock.h>
28#include <plat/cpu.h>
29#include <plat/pll.h>
30#include <plat/s5p-clock.h>
31#include <plat/clock-clksrc.h>
32
33#include "common.h"
34
35static unsigned long xtal;
36
37static struct clksrc_clk clk_mout_apll = {
38 .clk = {
39 .name = "mout_apll",
40 },
41 .sources = &clk_src_apll,
42 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
43};
44
45static struct clksrc_clk clk_mout_epll = {
46 .clk = {
47 .name = "mout_epll",
48 },
49 .sources = &clk_src_epll,
50 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
51};
52
53static struct clksrc_clk clk_mout_mpll = {
54 .clk = {
55 .name = "mout_mpll",
56 },
57 .sources = &clk_src_mpll,
58 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
59};
60
61static struct clk *clkset_armclk_list[] = {
62 [0] = &clk_mout_apll.clk,
63 [1] = &clk_mout_mpll.clk,
64};
65
66static struct clksrc_sources clkset_armclk = {
67 .sources = clkset_armclk_list,
68 .nr_sources = ARRAY_SIZE(clkset_armclk_list),
69};
70
71static struct clksrc_clk clk_armclk = {
72 .clk = {
73 .name = "armclk",
74 },
75 .sources = &clkset_armclk,
76 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
77 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
78};
79
80static struct clksrc_clk clk_hclk_msys = {
81 .clk = {
82 .name = "hclk_msys",
83 .parent = &clk_armclk.clk,
84 },
85 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
86};
87
88static struct clksrc_clk clk_pclk_msys = {
89 .clk = {
90 .name = "pclk_msys",
91 .parent = &clk_hclk_msys.clk,
92 },
93 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
94};
95
96static struct clksrc_clk clk_sclk_a2m = {
97 .clk = {
98 .name = "sclk_a2m",
99 .parent = &clk_mout_apll.clk,
100 },
101 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
102};
103
104static struct clk *clkset_hclk_sys_list[] = {
105 [0] = &clk_mout_mpll.clk,
106 [1] = &clk_sclk_a2m.clk,
107};
108
109static struct clksrc_sources clkset_hclk_sys = {
110 .sources = clkset_hclk_sys_list,
111 .nr_sources = ARRAY_SIZE(clkset_hclk_sys_list),
112};
113
114static struct clksrc_clk clk_hclk_dsys = {
115 .clk = {
116 .name = "hclk_dsys",
117 },
118 .sources = &clkset_hclk_sys,
119 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
120 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
121};
122
123static struct clksrc_clk clk_pclk_dsys = {
124 .clk = {
125 .name = "pclk_dsys",
126 .parent = &clk_hclk_dsys.clk,
127 },
128 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
129};
130
131static struct clksrc_clk clk_hclk_psys = {
132 .clk = {
133 .name = "hclk_psys",
134 },
135 .sources = &clkset_hclk_sys,
136 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
137 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
138};
139
140static struct clksrc_clk clk_pclk_psys = {
141 .clk = {
142 .name = "pclk_psys",
143 .parent = &clk_hclk_psys.clk,
144 },
145 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
146};
147
148static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
149{
150 return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
151}
152
153static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
154{
155 return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
156}
157
158static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
159{
160 return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
161}
162
163static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
164{
165 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
166}
167
168static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
169{
170 return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
171}
172
173static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
174{
175 return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
176}
177
178static int s5pv210_clk_hdmiphy_ctrl(struct clk *clk, int enable)
179{
180 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
181}
182
183static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
184{
185 return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
186}
187
188static struct clk clk_sclk_hdmi27m = {
189 .name = "sclk_hdmi27m",
190 .rate = 27000000,
191};
192
193static struct clk clk_sclk_hdmiphy = {
194 .name = "sclk_hdmiphy",
195};
196
197static struct clk clk_sclk_usbphy0 = {
198 .name = "sclk_usbphy0",
199};
200
201static struct clk clk_sclk_usbphy1 = {
202 .name = "sclk_usbphy1",
203};
204
205static struct clk clk_pcmcdclk0 = {
206 .name = "pcmcdclk",
207};
208
209static struct clk clk_pcmcdclk1 = {
210 .name = "pcmcdclk",
211};
212
213static struct clk clk_pcmcdclk2 = {
214 .name = "pcmcdclk",
215};
216
217static struct clk *clkset_vpllsrc_list[] = {
218 [0] = &clk_fin_vpll,
219 [1] = &clk_sclk_hdmi27m,
220};
221
222static struct clksrc_sources clkset_vpllsrc = {
223 .sources = clkset_vpllsrc_list,
224 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
225};
226
227static struct clksrc_clk clk_vpllsrc = {
228 .clk = {
229 .name = "vpll_src",
230 .enable = s5pv210_clk_mask0_ctrl,
231 .ctrlbit = (1 << 7),
232 },
233 .sources = &clkset_vpllsrc,
234 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
235};
236
237static struct clk *clkset_sclk_vpll_list[] = {
238 [0] = &clk_vpllsrc.clk,
239 [1] = &clk_fout_vpll,
240};
241
242static struct clksrc_sources clkset_sclk_vpll = {
243 .sources = clkset_sclk_vpll_list,
244 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
245};
246
247static struct clksrc_clk clk_sclk_vpll = {
248 .clk = {
249 .name = "sclk_vpll",
250 },
251 .sources = &clkset_sclk_vpll,
252 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
253};
254
255static struct clk *clkset_moutdmc0src_list[] = {
256 [0] = &clk_sclk_a2m.clk,
257 [1] = &clk_mout_mpll.clk,
258 [2] = NULL,
259 [3] = NULL,
260};
261
262static struct clksrc_sources clkset_moutdmc0src = {
263 .sources = clkset_moutdmc0src_list,
264 .nr_sources = ARRAY_SIZE(clkset_moutdmc0src_list),
265};
266
267static struct clksrc_clk clk_mout_dmc0 = {
268 .clk = {
269 .name = "mout_dmc0",
270 },
271 .sources = &clkset_moutdmc0src,
272 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
273};
274
275static struct clksrc_clk clk_sclk_dmc0 = {
276 .clk = {
277 .name = "sclk_dmc0",
278 .parent = &clk_mout_dmc0.clk,
279 },
280 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
281};
282
283static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
284{
285 return clk_get_rate(clk->parent) / 2;
286}
287
288static struct clk_ops clk_hclk_imem_ops = {
289 .get_rate = s5pv210_clk_imem_get_rate,
290};
291
292static unsigned long s5pv210_clk_fout_apll_get_rate(struct clk *clk)
293{
294 return s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
295}
296
297static struct clk_ops clk_fout_apll_ops = {
298 .get_rate = s5pv210_clk_fout_apll_get_rate,
299};
300
301static struct clk init_clocks_off[] = {
302 {
303 .name = "rot",
304 .parent = &clk_hclk_dsys.clk,
305 .enable = s5pv210_clk_ip0_ctrl,
306 .ctrlbit = (1<<29),
307 }, {
308 .name = "fimc",
309 .devname = "s5pv210-fimc.0",
310 .parent = &clk_hclk_dsys.clk,
311 .enable = s5pv210_clk_ip0_ctrl,
312 .ctrlbit = (1 << 24),
313 }, {
314 .name = "fimc",
315 .devname = "s5pv210-fimc.1",
316 .parent = &clk_hclk_dsys.clk,
317 .enable = s5pv210_clk_ip0_ctrl,
318 .ctrlbit = (1 << 25),
319 }, {
320 .name = "fimc",
321 .devname = "s5pv210-fimc.2",
322 .parent = &clk_hclk_dsys.clk,
323 .enable = s5pv210_clk_ip0_ctrl,
324 .ctrlbit = (1 << 26),
325 }, {
326 .name = "jpeg",
327 .parent = &clk_hclk_dsys.clk,
328 .enable = s5pv210_clk_ip0_ctrl,
329 .ctrlbit = (1 << 28),
330 }, {
331 .name = "mfc",
332 .devname = "s5p-mfc",
333 .parent = &clk_pclk_psys.clk,
334 .enable = s5pv210_clk_ip0_ctrl,
335 .ctrlbit = (1 << 16),
336 }, {
337 .name = "dac",
338 .devname = "s5p-sdo",
339 .parent = &clk_hclk_dsys.clk,
340 .enable = s5pv210_clk_ip1_ctrl,
341 .ctrlbit = (1 << 10),
342 }, {
343 .name = "mixer",
344 .devname = "s5p-mixer",
345 .parent = &clk_hclk_dsys.clk,
346 .enable = s5pv210_clk_ip1_ctrl,
347 .ctrlbit = (1 << 9),
348 }, {
349 .name = "vp",
350 .devname = "s5p-mixer",
351 .parent = &clk_hclk_dsys.clk,
352 .enable = s5pv210_clk_ip1_ctrl,
353 .ctrlbit = (1 << 8),
354 }, {
355 .name = "hdmi",
356 .devname = "s5pv210-hdmi",
357 .parent = &clk_hclk_dsys.clk,
358 .enable = s5pv210_clk_ip1_ctrl,
359 .ctrlbit = (1 << 11),
360 }, {
361 .name = "hdmiphy",
362 .devname = "s5pv210-hdmi",
363 .enable = s5pv210_clk_hdmiphy_ctrl,
364 .ctrlbit = (1 << 0),
365 }, {
366 .name = "dacphy",
367 .devname = "s5p-sdo",
368 .enable = exynos4_clk_dac_ctrl,
369 .ctrlbit = (1 << 0),
370 }, {
371 .name = "otg",
372 .parent = &clk_hclk_psys.clk,
373 .enable = s5pv210_clk_ip1_ctrl,
374 .ctrlbit = (1<<16),
375 }, {
376 .name = "usb-host",
377 .parent = &clk_hclk_psys.clk,
378 .enable = s5pv210_clk_ip1_ctrl,
379 .ctrlbit = (1<<17),
380 }, {
381 .name = "lcd",
382 .parent = &clk_hclk_dsys.clk,
383 .enable = s5pv210_clk_ip1_ctrl,
384 .ctrlbit = (1<<0),
385 }, {
386 .name = "cfcon",
387 .parent = &clk_hclk_psys.clk,
388 .enable = s5pv210_clk_ip1_ctrl,
389 .ctrlbit = (1<<25),
390 }, {
391 .name = "systimer",
392 .parent = &clk_pclk_psys.clk,
393 .enable = s5pv210_clk_ip3_ctrl,
394 .ctrlbit = (1<<16),
395 }, {
396 .name = "watchdog",
397 .parent = &clk_pclk_psys.clk,
398 .enable = s5pv210_clk_ip3_ctrl,
399 .ctrlbit = (1<<22),
400 }, {
401 .name = "rtc",
402 .parent = &clk_pclk_psys.clk,
403 .enable = s5pv210_clk_ip3_ctrl,
404 .ctrlbit = (1<<15),
405 }, {
406 .name = "i2c",
407 .devname = "s3c2440-i2c.0",
408 .parent = &clk_pclk_psys.clk,
409 .enable = s5pv210_clk_ip3_ctrl,
410 .ctrlbit = (1<<7),
411 }, {
412 .name = "i2c",
413 .devname = "s3c2440-i2c.1",
414 .parent = &clk_pclk_psys.clk,
415 .enable = s5pv210_clk_ip3_ctrl,
416 .ctrlbit = (1 << 10),
417 }, {
418 .name = "i2c",
419 .devname = "s3c2440-i2c.2",
420 .parent = &clk_pclk_psys.clk,
421 .enable = s5pv210_clk_ip3_ctrl,
422 .ctrlbit = (1<<9),
423 }, {
424 .name = "i2c",
425 .devname = "s3c2440-hdmiphy-i2c",
426 .parent = &clk_pclk_psys.clk,
427 .enable = s5pv210_clk_ip3_ctrl,
428 .ctrlbit = (1 << 11),
429 }, {
430 .name = "spi",
431 .devname = "s5pv210-spi.0",
432 .parent = &clk_pclk_psys.clk,
433 .enable = s5pv210_clk_ip3_ctrl,
434 .ctrlbit = (1<<12),
435 }, {
436 .name = "spi",
437 .devname = "s5pv210-spi.1",
438 .parent = &clk_pclk_psys.clk,
439 .enable = s5pv210_clk_ip3_ctrl,
440 .ctrlbit = (1<<13),
441 }, {
442 .name = "spi",
443 .devname = "s5pv210-spi.2",
444 .parent = &clk_pclk_psys.clk,
445 .enable = s5pv210_clk_ip3_ctrl,
446 .ctrlbit = (1<<14),
447 }, {
448 .name = "timers",
449 .parent = &clk_pclk_psys.clk,
450 .enable = s5pv210_clk_ip3_ctrl,
451 .ctrlbit = (1<<23),
452 }, {
453 .name = "adc",
454 .parent = &clk_pclk_psys.clk,
455 .enable = s5pv210_clk_ip3_ctrl,
456 .ctrlbit = (1<<24),
457 }, {
458 .name = "keypad",
459 .parent = &clk_pclk_psys.clk,
460 .enable = s5pv210_clk_ip3_ctrl,
461 .ctrlbit = (1<<21),
462 }, {
463 .name = "iis",
464 .devname = "samsung-i2s.0",
465 .parent = &clk_p,
466 .enable = s5pv210_clk_ip3_ctrl,
467 .ctrlbit = (1<<4),
468 }, {
469 .name = "iis",
470 .devname = "samsung-i2s.1",
471 .parent = &clk_p,
472 .enable = s5pv210_clk_ip3_ctrl,
473 .ctrlbit = (1 << 5),
474 }, {
475 .name = "iis",
476 .devname = "samsung-i2s.2",
477 .parent = &clk_p,
478 .enable = s5pv210_clk_ip3_ctrl,
479 .ctrlbit = (1 << 6),
480 }, {
481 .name = "spdif",
482 .parent = &clk_p,
483 .enable = s5pv210_clk_ip3_ctrl,
484 .ctrlbit = (1 << 0),
485 },
486};
487
488static struct clk init_clocks[] = {
489 {
490 .name = "hclk_imem",
491 .parent = &clk_hclk_msys.clk,
492 .ctrlbit = (1 << 5),
493 .enable = s5pv210_clk_ip0_ctrl,
494 .ops = &clk_hclk_imem_ops,
495 }, {
496 .name = "uart",
497 .devname = "s5pv210-uart.0",
498 .parent = &clk_pclk_psys.clk,
499 .enable = s5pv210_clk_ip3_ctrl,
500 .ctrlbit = (1 << 17),
501 }, {
502 .name = "uart",
503 .devname = "s5pv210-uart.1",
504 .parent = &clk_pclk_psys.clk,
505 .enable = s5pv210_clk_ip3_ctrl,
506 .ctrlbit = (1 << 18),
507 }, {
508 .name = "uart",
509 .devname = "s5pv210-uart.2",
510 .parent = &clk_pclk_psys.clk,
511 .enable = s5pv210_clk_ip3_ctrl,
512 .ctrlbit = (1 << 19),
513 }, {
514 .name = "uart",
515 .devname = "s5pv210-uart.3",
516 .parent = &clk_pclk_psys.clk,
517 .enable = s5pv210_clk_ip3_ctrl,
518 .ctrlbit = (1 << 20),
519 }, {
520 .name = "sromc",
521 .parent = &clk_hclk_psys.clk,
522 .enable = s5pv210_clk_ip1_ctrl,
523 .ctrlbit = (1 << 26),
524 },
525};
526
527static struct clk clk_hsmmc0 = {
528 .name = "hsmmc",
529 .devname = "s3c-sdhci.0",
530 .parent = &clk_hclk_psys.clk,
531 .enable = s5pv210_clk_ip2_ctrl,
532 .ctrlbit = (1<<16),
533};
534
535static struct clk clk_hsmmc1 = {
536 .name = "hsmmc",
537 .devname = "s3c-sdhci.1",
538 .parent = &clk_hclk_psys.clk,
539 .enable = s5pv210_clk_ip2_ctrl,
540 .ctrlbit = (1<<17),
541};
542
543static struct clk clk_hsmmc2 = {
544 .name = "hsmmc",
545 .devname = "s3c-sdhci.2",
546 .parent = &clk_hclk_psys.clk,
547 .enable = s5pv210_clk_ip2_ctrl,
548 .ctrlbit = (1<<18),
549};
550
551static struct clk clk_hsmmc3 = {
552 .name = "hsmmc",
553 .devname = "s3c-sdhci.3",
554 .parent = &clk_hclk_psys.clk,
555 .enable = s5pv210_clk_ip2_ctrl,
556 .ctrlbit = (1<<19),
557};
558
559static struct clk clk_pdma0 = {
560 .name = "pdma0",
561 .parent = &clk_hclk_psys.clk,
562 .enable = s5pv210_clk_ip0_ctrl,
563 .ctrlbit = (1 << 3),
564};
565
566static struct clk clk_pdma1 = {
567 .name = "pdma1",
568 .parent = &clk_hclk_psys.clk,
569 .enable = s5pv210_clk_ip0_ctrl,
570 .ctrlbit = (1 << 4),
571};
572
573static struct clk *clkset_uart_list[] = {
574 [6] = &clk_mout_mpll.clk,
575 [7] = &clk_mout_epll.clk,
576};
577
578static struct clksrc_sources clkset_uart = {
579 .sources = clkset_uart_list,
580 .nr_sources = ARRAY_SIZE(clkset_uart_list),
581};
582
583static struct clk *clkset_group1_list[] = {
584 [0] = &clk_sclk_a2m.clk,
585 [1] = &clk_mout_mpll.clk,
586 [2] = &clk_mout_epll.clk,
587 [3] = &clk_sclk_vpll.clk,
588};
589
590static struct clksrc_sources clkset_group1 = {
591 .sources = clkset_group1_list,
592 .nr_sources = ARRAY_SIZE(clkset_group1_list),
593};
594
595static struct clk *clkset_sclk_onenand_list[] = {
596 [0] = &clk_hclk_psys.clk,
597 [1] = &clk_hclk_dsys.clk,
598};
599
600static struct clksrc_sources clkset_sclk_onenand = {
601 .sources = clkset_sclk_onenand_list,
602 .nr_sources = ARRAY_SIZE(clkset_sclk_onenand_list),
603};
604
605static struct clk *clkset_sclk_dac_list[] = {
606 [0] = &clk_sclk_vpll.clk,
607 [1] = &clk_sclk_hdmiphy,
608};
609
610static struct clksrc_sources clkset_sclk_dac = {
611 .sources = clkset_sclk_dac_list,
612 .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
613};
614
615static struct clksrc_clk clk_sclk_dac = {
616 .clk = {
617 .name = "sclk_dac",
618 .enable = s5pv210_clk_mask0_ctrl,
619 .ctrlbit = (1 << 2),
620 },
621 .sources = &clkset_sclk_dac,
622 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
623};
624
625static struct clksrc_clk clk_sclk_pixel = {
626 .clk = {
627 .name = "sclk_pixel",
628 .parent = &clk_sclk_vpll.clk,
629 },
630 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
631};
632
633static struct clk *clkset_sclk_hdmi_list[] = {
634 [0] = &clk_sclk_pixel.clk,
635 [1] = &clk_sclk_hdmiphy,
636};
637
638static struct clksrc_sources clkset_sclk_hdmi = {
639 .sources = clkset_sclk_hdmi_list,
640 .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
641};
642
643static struct clksrc_clk clk_sclk_hdmi = {
644 .clk = {
645 .name = "sclk_hdmi",
646 .enable = s5pv210_clk_mask0_ctrl,
647 .ctrlbit = (1 << 0),
648 },
649 .sources = &clkset_sclk_hdmi,
650 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
651};
652
653static struct clk *clkset_sclk_mixer_list[] = {
654 [0] = &clk_sclk_dac.clk,
655 [1] = &clk_sclk_hdmi.clk,
656};
657
658static struct clksrc_sources clkset_sclk_mixer = {
659 .sources = clkset_sclk_mixer_list,
660 .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
661};
662
663static struct clksrc_clk clk_sclk_mixer = {
664 .clk = {
665 .name = "sclk_mixer",
666 .enable = s5pv210_clk_mask0_ctrl,
667 .ctrlbit = (1 << 1),
668 },
669 .sources = &clkset_sclk_mixer,
670 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
671};
672
673static struct clksrc_clk *sclk_tv[] = {
674 &clk_sclk_dac,
675 &clk_sclk_pixel,
676 &clk_sclk_hdmi,
677 &clk_sclk_mixer,
678};
679
680static struct clk *clkset_sclk_audio0_list[] = {
681 [0] = &clk_ext_xtal_mux,
682 [1] = &clk_pcmcdclk0,
683 [2] = &clk_sclk_hdmi27m,
684 [3] = &clk_sclk_usbphy0,
685 [4] = &clk_sclk_usbphy1,
686 [5] = &clk_sclk_hdmiphy,
687 [6] = &clk_mout_mpll.clk,
688 [7] = &clk_mout_epll.clk,
689 [8] = &clk_sclk_vpll.clk,
690};
691
692static struct clksrc_sources clkset_sclk_audio0 = {
693 .sources = clkset_sclk_audio0_list,
694 .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
695};
696
697static struct clksrc_clk clk_sclk_audio0 = {
698 .clk = {
699 .name = "sclk_audio",
700 .devname = "soc-audio.0",
701 .enable = s5pv210_clk_mask0_ctrl,
702 .ctrlbit = (1 << 24),
703 },
704 .sources = &clkset_sclk_audio0,
705 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
706 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 },
707};
708
709static struct clk *clkset_sclk_audio1_list[] = {
710 [0] = &clk_ext_xtal_mux,
711 [1] = &clk_pcmcdclk1,
712 [2] = &clk_sclk_hdmi27m,
713 [3] = &clk_sclk_usbphy0,
714 [4] = &clk_sclk_usbphy1,
715 [5] = &clk_sclk_hdmiphy,
716 [6] = &clk_mout_mpll.clk,
717 [7] = &clk_mout_epll.clk,
718 [8] = &clk_sclk_vpll.clk,
719};
720
721static struct clksrc_sources clkset_sclk_audio1 = {
722 .sources = clkset_sclk_audio1_list,
723 .nr_sources = ARRAY_SIZE(clkset_sclk_audio1_list),
724};
725
726static struct clksrc_clk clk_sclk_audio1 = {
727 .clk = {
728 .name = "sclk_audio",
729 .devname = "soc-audio.1",
730 .enable = s5pv210_clk_mask0_ctrl,
731 .ctrlbit = (1 << 25),
732 },
733 .sources = &clkset_sclk_audio1,
734 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
735 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 },
736};
737
738static struct clk *clkset_sclk_audio2_list[] = {
739 [0] = &clk_ext_xtal_mux,
740 [1] = &clk_pcmcdclk0,
741 [2] = &clk_sclk_hdmi27m,
742 [3] = &clk_sclk_usbphy0,
743 [4] = &clk_sclk_usbphy1,
744 [5] = &clk_sclk_hdmiphy,
745 [6] = &clk_mout_mpll.clk,
746 [7] = &clk_mout_epll.clk,
747 [8] = &clk_sclk_vpll.clk,
748};
749
750static struct clksrc_sources clkset_sclk_audio2 = {
751 .sources = clkset_sclk_audio2_list,
752 .nr_sources = ARRAY_SIZE(clkset_sclk_audio2_list),
753};
754
755static struct clksrc_clk clk_sclk_audio2 = {
756 .clk = {
757 .name = "sclk_audio",
758 .devname = "soc-audio.2",
759 .enable = s5pv210_clk_mask0_ctrl,
760 .ctrlbit = (1 << 26),
761 },
762 .sources = &clkset_sclk_audio2,
763 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
764 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 },
765};
766
767static struct clk *clkset_sclk_spdif_list[] = {
768 [0] = &clk_sclk_audio0.clk,
769 [1] = &clk_sclk_audio1.clk,
770 [2] = &clk_sclk_audio2.clk,
771};
772
773static struct clksrc_sources clkset_sclk_spdif = {
774 .sources = clkset_sclk_spdif_list,
775 .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list),
776};
777
778static struct clksrc_clk clk_sclk_spdif = {
779 .clk = {
780 .name = "sclk_spdif",
781 .enable = s5pv210_clk_mask0_ctrl,
782 .ctrlbit = (1 << 27),
783 .ops = &s5p_sclk_spdif_ops,
784 },
785 .sources = &clkset_sclk_spdif,
786 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
787};
788
789static struct clk *clkset_group2_list[] = {
790 [0] = &clk_ext_xtal_mux,
791 [1] = &clk_xusbxti,
792 [2] = &clk_sclk_hdmi27m,
793 [3] = &clk_sclk_usbphy0,
794 [4] = &clk_sclk_usbphy1,
795 [5] = &clk_sclk_hdmiphy,
796 [6] = &clk_mout_mpll.clk,
797 [7] = &clk_mout_epll.clk,
798 [8] = &clk_sclk_vpll.clk,
799};
800
801static struct clksrc_sources clkset_group2 = {
802 .sources = clkset_group2_list,
803 .nr_sources = ARRAY_SIZE(clkset_group2_list),
804};
805
806static struct clksrc_clk clksrcs[] = {
807 {
808 .clk = {
809 .name = "sclk_dmc",
810 },
811 .sources = &clkset_group1,
812 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
813 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
814 }, {
815 .clk = {
816 .name = "sclk_onenand",
817 },
818 .sources = &clkset_sclk_onenand,
819 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
820 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
821 }, {
822 .clk = {
823 .name = "sclk_fimc",
824 .devname = "s5pv210-fimc.0",
825 .enable = s5pv210_clk_mask1_ctrl,
826 .ctrlbit = (1 << 2),
827 },
828 .sources = &clkset_group2,
829 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
830 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
831 }, {
832 .clk = {
833 .name = "sclk_fimc",
834 .devname = "s5pv210-fimc.1",
835 .enable = s5pv210_clk_mask1_ctrl,
836 .ctrlbit = (1 << 3),
837 },
838 .sources = &clkset_group2,
839 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
840 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
841 }, {
842 .clk = {
843 .name = "sclk_fimc",
844 .devname = "s5pv210-fimc.2",
845 .enable = s5pv210_clk_mask1_ctrl,
846 .ctrlbit = (1 << 4),
847 },
848 .sources = &clkset_group2,
849 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
850 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
851 }, {
852 .clk = {
853 .name = "sclk_cam0",
854 .enable = s5pv210_clk_mask0_ctrl,
855 .ctrlbit = (1 << 3),
856 },
857 .sources = &clkset_group2,
858 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
859 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
860 }, {
861 .clk = {
862 .name = "sclk_cam1",
863 .enable = s5pv210_clk_mask0_ctrl,
864 .ctrlbit = (1 << 4),
865 },
866 .sources = &clkset_group2,
867 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
868 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
869 }, {
870 .clk = {
871 .name = "sclk_fimd",
872 .enable = s5pv210_clk_mask0_ctrl,
873 .ctrlbit = (1 << 5),
874 },
875 .sources = &clkset_group2,
876 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
877 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
878 }, {
879 .clk = {
880 .name = "sclk_mfc",
881 .devname = "s5p-mfc",
882 .enable = s5pv210_clk_ip0_ctrl,
883 .ctrlbit = (1 << 16),
884 },
885 .sources = &clkset_group1,
886 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
887 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
888 }, {
889 .clk = {
890 .name = "sclk_g2d",
891 .enable = s5pv210_clk_ip0_ctrl,
892 .ctrlbit = (1 << 12),
893 },
894 .sources = &clkset_group1,
895 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
896 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
897 }, {
898 .clk = {
899 .name = "sclk_g3d",
900 .enable = s5pv210_clk_ip0_ctrl,
901 .ctrlbit = (1 << 8),
902 },
903 .sources = &clkset_group1,
904 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
905 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
906 }, {
907 .clk = {
908 .name = "sclk_csis",
909 .enable = s5pv210_clk_mask0_ctrl,
910 .ctrlbit = (1 << 6),
911 },
912 .sources = &clkset_group2,
913 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
914 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
915 }, {
916 .clk = {
917 .name = "sclk_pwi",
918 .enable = s5pv210_clk_mask0_ctrl,
919 .ctrlbit = (1 << 29),
920 },
921 .sources = &clkset_group2,
922 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
923 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 },
924 }, {
925 .clk = {
926 .name = "sclk_pwm",
927 .enable = s5pv210_clk_mask0_ctrl,
928 .ctrlbit = (1 << 19),
929 },
930 .sources = &clkset_group2,
931 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
932 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 },
933 },
934};
935
936static struct clksrc_clk clk_sclk_uart0 = {
937 .clk = {
938 .name = "uclk1",
939 .devname = "s5pv210-uart.0",
940 .enable = s5pv210_clk_mask0_ctrl,
941 .ctrlbit = (1 << 12),
942 },
943 .sources = &clkset_uart,
944 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
945 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
946};
947
948static struct clksrc_clk clk_sclk_uart1 = {
949 .clk = {
950 .name = "uclk1",
951 .devname = "s5pv210-uart.1",
952 .enable = s5pv210_clk_mask0_ctrl,
953 .ctrlbit = (1 << 13),
954 },
955 .sources = &clkset_uart,
956 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
957 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
958};
959
960static struct clksrc_clk clk_sclk_uart2 = {
961 .clk = {
962 .name = "uclk1",
963 .devname = "s5pv210-uart.2",
964 .enable = s5pv210_clk_mask0_ctrl,
965 .ctrlbit = (1 << 14),
966 },
967 .sources = &clkset_uart,
968 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
969 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
970};
971
972static struct clksrc_clk clk_sclk_uart3 = {
973 .clk = {
974 .name = "uclk1",
975 .devname = "s5pv210-uart.3",
976 .enable = s5pv210_clk_mask0_ctrl,
977 .ctrlbit = (1 << 15),
978 },
979 .sources = &clkset_uart,
980 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
981 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
982};
983
984static struct clksrc_clk clk_sclk_mmc0 = {
985 .clk = {
986 .name = "sclk_mmc",
987 .devname = "s3c-sdhci.0",
988 .enable = s5pv210_clk_mask0_ctrl,
989 .ctrlbit = (1 << 8),
990 },
991 .sources = &clkset_group2,
992 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
993 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
994};
995
996static struct clksrc_clk clk_sclk_mmc1 = {
997 .clk = {
998 .name = "sclk_mmc",
999 .devname = "s3c-sdhci.1",
1000 .enable = s5pv210_clk_mask0_ctrl,
1001 .ctrlbit = (1 << 9),
1002 },
1003 .sources = &clkset_group2,
1004 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
1005 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
1006};
1007
1008static struct clksrc_clk clk_sclk_mmc2 = {
1009 .clk = {
1010 .name = "sclk_mmc",
1011 .devname = "s3c-sdhci.2",
1012 .enable = s5pv210_clk_mask0_ctrl,
1013 .ctrlbit = (1 << 10),
1014 },
1015 .sources = &clkset_group2,
1016 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
1017 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
1018};
1019
1020static struct clksrc_clk clk_sclk_mmc3 = {
1021 .clk = {
1022 .name = "sclk_mmc",
1023 .devname = "s3c-sdhci.3",
1024 .enable = s5pv210_clk_mask0_ctrl,
1025 .ctrlbit = (1 << 11),
1026 },
1027 .sources = &clkset_group2,
1028 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
1029 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
1030};
1031
1032static struct clksrc_clk clk_sclk_spi0 = {
1033 .clk = {
1034 .name = "sclk_spi",
1035 .devname = "s5pv210-spi.0",
1036 .enable = s5pv210_clk_mask0_ctrl,
1037 .ctrlbit = (1 << 16),
1038 },
1039 .sources = &clkset_group2,
1040 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
1041 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
1042 };
1043
1044static struct clksrc_clk clk_sclk_spi1 = {
1045 .clk = {
1046 .name = "sclk_spi",
1047 .devname = "s5pv210-spi.1",
1048 .enable = s5pv210_clk_mask0_ctrl,
1049 .ctrlbit = (1 << 17),
1050 },
1051 .sources = &clkset_group2,
1052 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
1053 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
1054 };
1055
1056
1057static struct clksrc_clk *clksrc_cdev[] = {
1058 &clk_sclk_uart0,
1059 &clk_sclk_uart1,
1060 &clk_sclk_uart2,
1061 &clk_sclk_uart3,
1062 &clk_sclk_mmc0,
1063 &clk_sclk_mmc1,
1064 &clk_sclk_mmc2,
1065 &clk_sclk_mmc3,
1066 &clk_sclk_spi0,
1067 &clk_sclk_spi1,
1068};
1069
1070static struct clk *clk_cdev[] = {
1071 &clk_hsmmc0,
1072 &clk_hsmmc1,
1073 &clk_hsmmc2,
1074 &clk_hsmmc3,
1075 &clk_pdma0,
1076 &clk_pdma1,
1077};
1078
1079/* Clock initialisation code */
1080static struct clksrc_clk *sysclks[] = {
1081 &clk_mout_apll,
1082 &clk_mout_epll,
1083 &clk_mout_mpll,
1084 &clk_armclk,
1085 &clk_hclk_msys,
1086 &clk_sclk_a2m,
1087 &clk_hclk_dsys,
1088 &clk_hclk_psys,
1089 &clk_pclk_msys,
1090 &clk_pclk_dsys,
1091 &clk_pclk_psys,
1092 &clk_vpllsrc,
1093 &clk_sclk_vpll,
1094 &clk_mout_dmc0,
1095 &clk_sclk_dmc0,
1096 &clk_sclk_audio0,
1097 &clk_sclk_audio1,
1098 &clk_sclk_audio2,
1099 &clk_sclk_spdif,
1100};
1101
1102static u32 epll_div[][6] = {
1103 { 48000000, 0, 48, 3, 3, 0 },
1104 { 96000000, 0, 48, 3, 2, 0 },
1105 { 144000000, 1, 72, 3, 2, 0 },
1106 { 192000000, 0, 48, 3, 1, 0 },
1107 { 288000000, 1, 72, 3, 1, 0 },
1108 { 32750000, 1, 65, 3, 4, 35127 },
1109 { 32768000, 1, 65, 3, 4, 35127 },
1110 { 45158400, 0, 45, 3, 3, 10355 },
1111 { 45000000, 0, 45, 3, 3, 10355 },
1112 { 45158000, 0, 45, 3, 3, 10355 },
1113 { 49125000, 0, 49, 3, 3, 9961 },
1114 { 49152000, 0, 49, 3, 3, 9961 },
1115 { 67737600, 1, 67, 3, 3, 48366 },
1116 { 67738000, 1, 67, 3, 3, 48366 },
1117 { 73800000, 1, 73, 3, 3, 47710 },
1118 { 73728000, 1, 73, 3, 3, 47710 },
1119 { 36000000, 1, 32, 3, 4, 0 },
1120 { 60000000, 1, 60, 3, 3, 0 },
1121 { 72000000, 1, 72, 3, 3, 0 },
1122 { 80000000, 1, 80, 3, 3, 0 },
1123 { 84000000, 0, 42, 3, 2, 0 },
1124 { 50000000, 0, 50, 3, 3, 0 },
1125};
1126
1127static int s5pv210_epll_set_rate(struct clk *clk, unsigned long rate)
1128{
1129 unsigned int epll_con, epll_con_k;
1130 unsigned int i;
1131
1132 /* Return if nothing changed */
1133 if (clk->rate == rate)
1134 return 0;
1135
1136 epll_con = __raw_readl(S5P_EPLL_CON);
1137 epll_con_k = __raw_readl(S5P_EPLL_CON1);
1138
1139 epll_con_k &= ~PLL46XX_KDIV_MASK;
1140 epll_con &= ~(1 << 27 |
1141 PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |
1142 PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |
1143 PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1144
1145 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1146 if (epll_div[i][0] == rate) {
1147 epll_con_k |= epll_div[i][5] << 0;
1148 epll_con |= (epll_div[i][1] << 27 |
1149 epll_div[i][2] << PLL46XX_MDIV_SHIFT |
1150 epll_div[i][3] << PLL46XX_PDIV_SHIFT |
1151 epll_div[i][4] << PLL46XX_SDIV_SHIFT);
1152 break;
1153 }
1154 }
1155
1156 if (i == ARRAY_SIZE(epll_div)) {
1157 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1158 __func__);
1159 return -EINVAL;
1160 }
1161
1162 __raw_writel(epll_con, S5P_EPLL_CON);
1163 __raw_writel(epll_con_k, S5P_EPLL_CON1);
1164
1165 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
1166 clk->rate, rate);
1167
1168 clk->rate = rate;
1169
1170 return 0;
1171}
1172
1173static struct clk_ops s5pv210_epll_ops = {
1174 .set_rate = s5pv210_epll_set_rate,
1175 .get_rate = s5p_epll_get_rate,
1176};
1177
1178static u32 vpll_div[][5] = {
1179 { 54000000, 3, 53, 3, 0 },
1180 { 108000000, 3, 53, 2, 0 },
1181};
1182
1183static unsigned long s5pv210_vpll_get_rate(struct clk *clk)
1184{
1185 return clk->rate;
1186}
1187
1188static int s5pv210_vpll_set_rate(struct clk *clk, unsigned long rate)
1189{
1190 unsigned int vpll_con;
1191 unsigned int i;
1192
1193 /* Return if nothing changed */
1194 if (clk->rate == rate)
1195 return 0;
1196
1197 vpll_con = __raw_readl(S5P_VPLL_CON);
1198 vpll_con &= ~(0x1 << 27 | \
1199 PLL90XX_MDIV_MASK << PLL90XX_MDIV_SHIFT | \
1200 PLL90XX_PDIV_MASK << PLL90XX_PDIV_SHIFT | \
1201 PLL90XX_SDIV_MASK << PLL90XX_SDIV_SHIFT);
1202
1203 for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
1204 if (vpll_div[i][0] == rate) {
1205 vpll_con |= vpll_div[i][1] << PLL90XX_PDIV_SHIFT;
1206 vpll_con |= vpll_div[i][2] << PLL90XX_MDIV_SHIFT;
1207 vpll_con |= vpll_div[i][3] << PLL90XX_SDIV_SHIFT;
1208 vpll_con |= vpll_div[i][4] << 27;
1209 break;
1210 }
1211 }
1212
1213 if (i == ARRAY_SIZE(vpll_div)) {
1214 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1215 __func__);
1216 return -EINVAL;
1217 }
1218
1219 __raw_writel(vpll_con, S5P_VPLL_CON);
1220
1221 /* Wait for VPLL lock */
1222 while (!(__raw_readl(S5P_VPLL_CON) & (1 << PLL90XX_LOCKED_SHIFT)))
1223 continue;
1224
1225 clk->rate = rate;
1226 return 0;
1227}
1228static struct clk_ops s5pv210_vpll_ops = {
1229 .get_rate = s5pv210_vpll_get_rate,
1230 .set_rate = s5pv210_vpll_set_rate,
1231};
1232
1233void __init_or_cpufreq s5pv210_setup_clocks(void)
1234{
1235 struct clk *xtal_clk;
1236 unsigned long vpllsrc;
1237 unsigned long armclk;
1238 unsigned long hclk_msys;
1239 unsigned long hclk_dsys;
1240 unsigned long hclk_psys;
1241 unsigned long pclk_msys;
1242 unsigned long pclk_dsys;
1243 unsigned long pclk_psys;
1244 unsigned long apll;
1245 unsigned long mpll;
1246 unsigned long epll;
1247 unsigned long vpll;
1248 unsigned int ptr;
1249 u32 clkdiv0, clkdiv1;
1250
1251 /* Set functions for clk_fout_epll */
1252 clk_fout_epll.enable = s5p_epll_enable;
1253 clk_fout_epll.ops = &s5pv210_epll_ops;
1254
1255 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1256
1257 clkdiv0 = __raw_readl(S5P_CLK_DIV0);
1258 clkdiv1 = __raw_readl(S5P_CLK_DIV1);
1259
1260 printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
1261 __func__, clkdiv0, clkdiv1);
1262
1263 xtal_clk = clk_get(NULL, "xtal");
1264 BUG_ON(IS_ERR(xtal_clk));
1265
1266 xtal = clk_get_rate(xtal_clk);
1267 clk_put(xtal_clk);
1268
1269 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1270
1271 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
1272 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
1273 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON),
1274 __raw_readl(S5P_EPLL_CON1), pll_4600);
1275 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1276 vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
1277
1278 clk_fout_apll.ops = &clk_fout_apll_ops;
1279 clk_fout_mpll.rate = mpll;
1280 clk_fout_epll.rate = epll;
1281 clk_fout_vpll.ops = &s5pv210_vpll_ops;
1282 clk_fout_vpll.rate = vpll;
1283
1284 printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1285 apll, mpll, epll, vpll);
1286
1287 armclk = clk_get_rate(&clk_armclk.clk);
1288 hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
1289 hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
1290 hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
1291 pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
1292 pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
1293 pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
1294
1295 printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
1296 "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
1297 armclk, hclk_msys, hclk_dsys, hclk_psys,
1298 pclk_msys, pclk_dsys, pclk_psys);
1299
1300 clk_f.rate = armclk;
1301 clk_h.rate = hclk_psys;
1302 clk_p.rate = pclk_psys;
1303
1304 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1305 s3c_set_clksrc(&clksrcs[ptr], true);
1306}
1307
1308static struct clk *clks[] __initdata = {
1309 &clk_sclk_hdmi27m,
1310 &clk_sclk_hdmiphy,
1311 &clk_sclk_usbphy0,
1312 &clk_sclk_usbphy1,
1313 &clk_pcmcdclk0,
1314 &clk_pcmcdclk1,
1315 &clk_pcmcdclk2,
1316};
1317
1318static struct clk_lookup s5pv210_clk_lookup[] = {
1319 CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p),
1320 CLKDEV_INIT("s5pv210-uart.0", "clk_uart_baud1", &clk_sclk_uart0.clk),
1321 CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk),
1322 CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk),
1323 CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk),
1324 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
1325 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
1326 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
1327 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.0", &clk_hsmmc3),
1328 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1329 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1330 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1331 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
1332 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
1333 CLKDEV_INIT("s5pv210-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
1334 CLKDEV_INIT("s5pv210-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
1335 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
1336 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
1337};
1338
1339void __init s5pv210_register_clocks(void)
1340{
1341 int ptr;
1342
1343 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1344
1345 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1346 s3c_register_clksrc(sysclks[ptr], 1);
1347
1348 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
1349 s3c_register_clksrc(sclk_tv[ptr], 1);
1350
1351 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1352 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1353
1354 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1355 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1356
1357 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1358 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1359 clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup));
1360
1361 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1362 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1363 s3c_disable_clocks(clk_cdev[ptr], 1);
1364
1365}
diff --git a/arch/arm/mach-s5pv210/common.c b/arch/arm/mach-s5pv210/common.c
index 2e2202ac7173..30bd5421aa79 100644
--- a/arch/arm/mach-s5pv210/common.c
+++ b/arch/arm/mach-s5pv210/common.c
@@ -17,6 +17,7 @@
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/module.h> 18#include <linux/module.h>
19#include <linux/clk.h> 19#include <linux/clk.h>
20#include <linux/clk-provider.h>
20#include <linux/io.h> 21#include <linux/io.h>
21#include <linux/device.h> 22#include <linux/device.h>
22#include <clocksource/samsung_pwm.h> 23#include <clocksource/samsung_pwm.h>
@@ -37,12 +38,6 @@
37 38
38#include <plat/cpu.h> 39#include <plat/cpu.h>
39 40
40#ifdef CONFIG_S5P_CLOCK
41#include <plat/clock.h>
42#else
43#include <linux/clk-provider.h>
44#endif
45
46#include <plat/devs.h> 41#include <plat/devs.h>
47#include <plat/sdhci.h> 42#include <plat/sdhci.h>
48#include <plat/adc-core.h> 43#include <plat/adc-core.h>
@@ -239,16 +234,7 @@ void __init s5pv210_map_io(void)
239 234
240void __init s5pv210_init_clocks(int xtal) 235void __init s5pv210_init_clocks(int xtal)
241{ 236{
242#ifdef CONFIG_S5P_CLOCK
243 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
244
245 s3c24xx_register_baseclocks(xtal);
246 s5p_register_clocks(xtal);
247 s5pv210_register_clocks();
248 s5pv210_setup_clocks();
249#else
250 xusbxti_f = xtal; 237 xusbxti_f = xtal;
251#endif
252} 238}
253 239
254void __init s5pv210_init_irq(void) 240void __init s5pv210_init_irq(void)
diff --git a/arch/arm/mach-s5pv210/common.h b/arch/arm/mach-s5pv210/common.h
index a2e85cb9b471..083ffe7b5079 100644
--- a/arch/arm/mach-s5pv210/common.h
+++ b/arch/arm/mach-s5pv210/common.h
@@ -14,14 +14,8 @@
14 14
15#include <linux/reboot.h> 15#include <linux/reboot.h>
16 16
17#ifdef CONFIG_COMMON_CLK_S5PV210
18void s5pv210_clk_init(unsigned long xxti_f, unsigned long xusbxti_f, 17void s5pv210_clk_init(unsigned long xxti_f, unsigned long xusbxti_f,
19 void __iomem *reg_base); 18 void __iomem *reg_base);
20#else
21static inline void s5pv210_clk_init(unsigned long xxti_f,
22 unsigned long xusbxti_f,
23 void __iomem *reg_base) {}
24#endif
25 19
26void s5pv210_init_io(struct map_desc *mach_desc, int size); 20void s5pv210_init_io(struct map_desc *mach_desc, int size);
27void s5pv210_init_irq(void); 21void s5pv210_init_irq(void);
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 0fc71beab779..315926f0b5d3 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -46,7 +46,6 @@
46#include <linux/platform_data/i2c-s3c2410.h> 46#include <linux/platform_data/i2c-s3c2410.h>
47#include <plat/keypad.h> 47#include <plat/keypad.h>
48#include <plat/sdhci.h> 48#include <plat/sdhci.h>
49#include <plat/clock.h>
50#include <plat/samsung-time.h> 49#include <plat/samsung-time.h>
51#include <plat/mfc.h> 50#include <plat/mfc.h>
52 51
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 1bde3a37060b..6816ccdfd86c 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -47,7 +47,6 @@
47#include <plat/samsung-time.h> 47#include <plat/samsung-time.h>
48#include <plat/backlight.h> 48#include <plat/backlight.h>
49#include <plat/mfc.h> 49#include <plat/mfc.h>
50#include <plat/clock.h>
51 50
52#include "common.h" 51#include "common.h"
53 52
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
index 3cf3f9c8ddd1..dd5bfec16b4f 100644
--- a/arch/arm/mach-s5pv210/pm.c
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -26,55 +26,7 @@
26#include <mach/regs-clock.h> 26#include <mach/regs-clock.h>
27 27
28static struct sleep_save s5pv210_core_save[] = { 28static struct sleep_save s5pv210_core_save[] = {
29 /* Clock source */
30 SAVE_ITEM(S5P_CLK_SRC0),
31 SAVE_ITEM(S5P_CLK_SRC1),
32 SAVE_ITEM(S5P_CLK_SRC2),
33 SAVE_ITEM(S5P_CLK_SRC3),
34 SAVE_ITEM(S5P_CLK_SRC4),
35 SAVE_ITEM(S5P_CLK_SRC5),
36 SAVE_ITEM(S5P_CLK_SRC6),
37
38 /* Clock source Mask */
39 SAVE_ITEM(S5P_CLK_SRC_MASK0),
40 SAVE_ITEM(S5P_CLK_SRC_MASK1),
41
42 /* Clock Divider */
43 SAVE_ITEM(S5P_CLK_DIV0),
44 SAVE_ITEM(S5P_CLK_DIV1),
45 SAVE_ITEM(S5P_CLK_DIV2),
46 SAVE_ITEM(S5P_CLK_DIV3),
47 SAVE_ITEM(S5P_CLK_DIV4),
48 SAVE_ITEM(S5P_CLK_DIV5),
49 SAVE_ITEM(S5P_CLK_DIV6),
50 SAVE_ITEM(S5P_CLK_DIV7),
51
52 /* Clock Main Gate */
53 SAVE_ITEM(S5P_CLKGATE_MAIN0),
54 SAVE_ITEM(S5P_CLKGATE_MAIN1),
55 SAVE_ITEM(S5P_CLKGATE_MAIN2),
56
57 /* Clock source Peri Gate */
58 SAVE_ITEM(S5P_CLKGATE_PERI0),
59 SAVE_ITEM(S5P_CLKGATE_PERI1),
60
61 /* Clock source SCLK Gate */
62 SAVE_ITEM(S5P_CLKGATE_SCLK0),
63 SAVE_ITEM(S5P_CLKGATE_SCLK1),
64
65 /* Clock IP Clock gate */
66 SAVE_ITEM(S5P_CLKGATE_IP0),
67 SAVE_ITEM(S5P_CLKGATE_IP1),
68 SAVE_ITEM(S5P_CLKGATE_IP2),
69 SAVE_ITEM(S5P_CLKGATE_IP3),
70 SAVE_ITEM(S5P_CLKGATE_IP4),
71
72 /* Clock Blcok and Bus gate */
73 SAVE_ITEM(S5P_CLKGATE_BLOCK),
74 SAVE_ITEM(S5P_CLKGATE_BUS0),
75
76 /* Clock ETC */ 29 /* Clock ETC */
77 SAVE_ITEM(S5P_CLK_OUT),
78 SAVE_ITEM(S5P_MDNIE_SEL), 30 SAVE_ITEM(S5P_MDNIE_SEL),
79}; 31};
80 32
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 42f5d5bde627..f8185b542218 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -23,7 +23,6 @@ config PLAT_S5P
23 select PLAT_SAMSUNG 23 select PLAT_SAMSUNG
24 select S3C_GPIO_TRACK 24 select S3C_GPIO_TRACK
25 select S5P_GPIO_DRVSTR 25 select S5P_GPIO_DRVSTR
26 select SAMSUNG_CLKSRC if !COMMON_CLK
27 help 26 help
28 Base platform code for Samsung's S5P series SoC. 27 Base platform code for Samsung's S5P series SoC.
29 28
@@ -65,23 +64,6 @@ config SAMSUNG_ATAGS
65 64
66if SAMSUNG_ATAGS 65if SAMSUNG_ATAGS
67 66
68# clock options
69
70config SAMSUNG_CLOCK
71 bool
72 default y if !COMMON_CLK
73
74config SAMSUNG_CLKSRC
75 bool
76 help
77 Select the clock code for the clksrc implementation
78 used by newer systems such as the S3C64XX.
79
80config S5P_CLOCK
81 bool
82 help
83 Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs
84
85# options for IRQ support 67# options for IRQ support
86 68
87config S5P_IRQ 69config S5P_IRQ
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 5e5beaa9ae15..906f54b11225 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -16,11 +16,6 @@ obj- :=
16 16
17obj-y += init.o cpu.o 17obj-y += init.o cpu.o
18 18
19obj-$(CONFIG_SAMSUNG_CLOCK) += clock.o
20
21obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o
22obj-$(CONFIG_S5P_CLOCK) += s5p-clock.o
23
24obj-$(CONFIG_S5P_IRQ) += s5p-irq.o 19obj-$(CONFIG_S5P_IRQ) += s5p-irq.o
25obj-$(CONFIG_S5P_EXT_INT) += s5p-irq-eint.o 20obj-$(CONFIG_S5P_EXT_INT) += s5p-irq-eint.o
26obj-$(CONFIG_S5P_GPIO_INT) += s5p-irq-gpioint.o 21obj-$(CONFIG_S5P_GPIO_INT) += s5p-irq-gpioint.o
diff --git a/arch/arm/plat-samsung/clock-clksrc.c b/arch/arm/plat-samsung/clock-clksrc.c
deleted file mode 100644
index 786a4107a157..000000000000
--- a/arch/arm/plat-samsung/clock-clksrc.c
+++ /dev/null
@@ -1,212 +0,0 @@
1/* linux/arch/arm/plat-samsung/clock-clksrc.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/errno.h>
17#include <linux/err.h>
18#include <linux/clk.h>
19#include <linux/device.h>
20#include <linux/io.h>
21
22#include <plat/clock.h>
23#include <plat/clock-clksrc.h>
24#include <plat/cpu-freq.h>
25
26static inline struct clksrc_clk *to_clksrc(struct clk *clk)
27{
28 return container_of(clk, struct clksrc_clk, clk);
29}
30
31static inline u32 bit_mask(u32 shift, u32 nr_bits)
32{
33 u32 mask = 0xffffffff >> (32 - nr_bits);
34
35 return mask << shift;
36}
37
38static unsigned long s3c_getrate_clksrc(struct clk *clk)
39{
40 struct clksrc_clk *sclk = to_clksrc(clk);
41 unsigned long rate = clk_get_rate(clk->parent);
42 u32 clkdiv = __raw_readl(sclk->reg_div.reg);
43 u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size);
44
45 clkdiv &= mask;
46 clkdiv >>= sclk->reg_div.shift;
47 clkdiv++;
48
49 rate /= clkdiv;
50 return rate;
51}
52
53static int s3c_setrate_clksrc(struct clk *clk, unsigned long rate)
54{
55 struct clksrc_clk *sclk = to_clksrc(clk);
56 void __iomem *reg = sclk->reg_div.reg;
57 unsigned int div;
58 u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size);
59 u32 val;
60
61 rate = clk_round_rate(clk, rate);
62 div = clk_get_rate(clk->parent) / rate;
63 if (div > (1 << sclk->reg_div.size))
64 return -EINVAL;
65
66 val = __raw_readl(reg);
67 val &= ~mask;
68 val |= (div - 1) << sclk->reg_div.shift;
69 __raw_writel(val, reg);
70
71 return 0;
72}
73
74static int s3c_setparent_clksrc(struct clk *clk, struct clk *parent)
75{
76 struct clksrc_clk *sclk = to_clksrc(clk);
77 struct clksrc_sources *srcs = sclk->sources;
78 u32 clksrc = __raw_readl(sclk->reg_src.reg);
79 u32 mask = bit_mask(sclk->reg_src.shift, sclk->reg_src.size);
80 int src_nr = -1;
81 int ptr;
82
83 for (ptr = 0; ptr < srcs->nr_sources; ptr++)
84 if (srcs->sources[ptr] == parent) {
85 src_nr = ptr;
86 break;
87 }
88
89 if (src_nr >= 0) {
90 clk->parent = parent;
91
92 clksrc &= ~mask;
93 clksrc |= src_nr << sclk->reg_src.shift;
94
95 __raw_writel(clksrc, sclk->reg_src.reg);
96 return 0;
97 }
98
99 return -EINVAL;
100}
101
102static unsigned long s3c_roundrate_clksrc(struct clk *clk,
103 unsigned long rate)
104{
105 struct clksrc_clk *sclk = to_clksrc(clk);
106 unsigned long parent_rate = clk_get_rate(clk->parent);
107 int max_div = 1 << sclk->reg_div.size;
108 int div;
109
110 if (rate >= parent_rate)
111 rate = parent_rate;
112 else {
113 div = parent_rate / rate;
114 if (parent_rate % rate)
115 div++;
116
117 if (div == 0)
118 div = 1;
119 if (div > max_div)
120 div = max_div;
121
122 rate = parent_rate / div;
123 }
124
125 return rate;
126}
127
128/* Clock initialisation code */
129
130void __init_or_cpufreq s3c_set_clksrc(struct clksrc_clk *clk, bool announce)
131{
132 struct clksrc_sources *srcs = clk->sources;
133 u32 mask = bit_mask(clk->reg_src.shift, clk->reg_src.size);
134 u32 clksrc;
135
136 if (!clk->reg_src.reg) {
137 if (!clk->clk.parent)
138 printk(KERN_ERR "%s: no parent clock specified\n",
139 clk->clk.name);
140 return;
141 }
142
143 clksrc = __raw_readl(clk->reg_src.reg);
144 clksrc &= mask;
145 clksrc >>= clk->reg_src.shift;
146
147 if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
148 printk(KERN_ERR "%s: bad source %d\n",
149 clk->clk.name, clksrc);
150 return;
151 }
152
153 clk->clk.parent = srcs->sources[clksrc];
154
155 if (announce)
156 printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
157 clk->clk.name, clk->clk.parent->name, clksrc,
158 clk_get_rate(&clk->clk));
159}
160
161static struct clk_ops clksrc_ops = {
162 .set_parent = s3c_setparent_clksrc,
163 .get_rate = s3c_getrate_clksrc,
164 .set_rate = s3c_setrate_clksrc,
165 .round_rate = s3c_roundrate_clksrc,
166};
167
168static struct clk_ops clksrc_ops_nodiv = {
169 .set_parent = s3c_setparent_clksrc,
170};
171
172static struct clk_ops clksrc_ops_nosrc = {
173 .get_rate = s3c_getrate_clksrc,
174 .set_rate = s3c_setrate_clksrc,
175 .round_rate = s3c_roundrate_clksrc,
176};
177
178void __init s3c_register_clksrc(struct clksrc_clk *clksrc, int size)
179{
180 int ret;
181
182 for (; size > 0; size--, clksrc++) {
183 if (!clksrc->reg_div.reg && !clksrc->reg_src.reg)
184 printk(KERN_ERR "%s: clock %s has no registers set\n",
185 __func__, clksrc->clk.name);
186
187 /* fill in the default functions */
188
189 if (!clksrc->clk.ops) {
190 if (!clksrc->reg_div.reg)
191 clksrc->clk.ops = &clksrc_ops_nodiv;
192 else if (!clksrc->reg_src.reg)
193 clksrc->clk.ops = &clksrc_ops_nosrc;
194 else
195 clksrc->clk.ops = &clksrc_ops;
196 }
197
198 /* setup the clocksource, but do not announce it
199 * as it may be re-set by the setup routines
200 * called after the rest of the clocks have been
201 * registered
202 */
203 s3c_set_clksrc(clksrc, false);
204
205 ret = s3c24xx_register_clock(&clksrc->clk);
206
207 if (ret < 0) {
208 printk(KERN_ERR "%s: failed to register %s (%d)\n",
209 __func__, clksrc->clk.name, ret);
210 }
211 }
212}
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
deleted file mode 100644
index d103ac1a52af..000000000000
--- a/arch/arm/plat-samsung/clock.c
+++ /dev/null
@@ -1,539 +0,0 @@
1/* linux/arch/arm/plat-s3c24xx/clock.c
2 *
3 * Copyright 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C24XX Core clock control support
7 *
8 * Based on, and code from linux/arch/arm/mach-versatile/clock.c
9 **
10 ** Copyright (C) 2004 ARM Limited.
11 ** Written by Deep Blue Solutions Limited.
12 *
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27*/
28
29#include <linux/init.h>
30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/list.h>
33#include <linux/errno.h>
34#include <linux/err.h>
35#include <linux/platform_device.h>
36#include <linux/device.h>
37#include <linux/interrupt.h>
38#include <linux/ioport.h>
39#include <linux/clk.h>
40#include <linux/spinlock.h>
41#include <linux/io.h>
42#if defined(CONFIG_DEBUG_FS)
43#include <linux/debugfs.h>
44#endif
45
46#include <asm/irq.h>
47
48#include <plat/cpu-freq.h>
49
50#include <plat/clock.h>
51#include <plat/cpu.h>
52
53#include <linux/serial_core.h>
54#include <linux/serial_s3c.h> /* for s3c24xx_uart_devs */
55
56/* clock information */
57
58static LIST_HEAD(clocks);
59
60/* We originally used an mutex here, but some contexts (see resume)
61 * are calling functions such as clk_set_parent() with IRQs disabled
62 * causing an BUG to be triggered.
63 */
64DEFINE_SPINLOCK(clocks_lock);
65
66/* Global watchdog clock used by arch_wtd_reset() callback */
67struct clk *s3c2410_wdtclk;
68static int __init s3c_wdt_reset_init(void)
69{
70 s3c2410_wdtclk = clk_get(NULL, "watchdog");
71 if (IS_ERR(s3c2410_wdtclk))
72 printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
73 return 0;
74}
75arch_initcall(s3c_wdt_reset_init);
76
77/* enable and disable calls for use with the clk struct */
78
79static int clk_null_enable(struct clk *clk, int enable)
80{
81 return 0;
82}
83
84int clk_enable(struct clk *clk)
85{
86 unsigned long flags;
87
88 if (IS_ERR(clk) || clk == NULL)
89 return -EINVAL;
90
91 clk_enable(clk->parent);
92
93 spin_lock_irqsave(&clocks_lock, flags);
94
95 if ((clk->usage++) == 0)
96 (clk->enable)(clk, 1);
97
98 spin_unlock_irqrestore(&clocks_lock, flags);
99 return 0;
100}
101
102void clk_disable(struct clk *clk)
103{
104 unsigned long flags;
105
106 if (IS_ERR(clk) || clk == NULL)
107 return;
108
109 spin_lock_irqsave(&clocks_lock, flags);
110
111 if ((--clk->usage) == 0)
112 (clk->enable)(clk, 0);
113
114 spin_unlock_irqrestore(&clocks_lock, flags);
115 clk_disable(clk->parent);
116}
117
118
119unsigned long clk_get_rate(struct clk *clk)
120{
121 if (IS_ERR_OR_NULL(clk))
122 return 0;
123
124 if (clk->rate != 0)
125 return clk->rate;
126
127 if (clk->ops != NULL && clk->ops->get_rate != NULL)
128 return (clk->ops->get_rate)(clk);
129
130 if (clk->parent != NULL)
131 return clk_get_rate(clk->parent);
132
133 return clk->rate;
134}
135
136long clk_round_rate(struct clk *clk, unsigned long rate)
137{
138 if (!IS_ERR_OR_NULL(clk) && clk->ops && clk->ops->round_rate)
139 return (clk->ops->round_rate)(clk, rate);
140
141 return rate;
142}
143
144int clk_set_rate(struct clk *clk, unsigned long rate)
145{
146 unsigned long flags;
147 int ret;
148
149 if (IS_ERR_OR_NULL(clk))
150 return -EINVAL;
151
152 /* We do not default just do a clk->rate = rate as
153 * the clock may have been made this way by choice.
154 */
155
156 WARN_ON(clk->ops == NULL);
157 WARN_ON(clk->ops && clk->ops->set_rate == NULL);
158
159 if (clk->ops == NULL || clk->ops->set_rate == NULL)
160 return -EINVAL;
161
162 spin_lock_irqsave(&clocks_lock, flags);
163 ret = (clk->ops->set_rate)(clk, rate);
164 spin_unlock_irqrestore(&clocks_lock, flags);
165
166 return ret;
167}
168
169struct clk *clk_get_parent(struct clk *clk)
170{
171 return clk->parent;
172}
173
174int clk_set_parent(struct clk *clk, struct clk *parent)
175{
176 unsigned long flags;
177 int ret = 0;
178
179 if (IS_ERR_OR_NULL(clk) || IS_ERR_OR_NULL(parent))
180 return -EINVAL;
181
182 spin_lock_irqsave(&clocks_lock, flags);
183
184 if (clk->ops && clk->ops->set_parent)
185 ret = (clk->ops->set_parent)(clk, parent);
186
187 spin_unlock_irqrestore(&clocks_lock, flags);
188
189 return ret;
190}
191
192EXPORT_SYMBOL(clk_enable);
193EXPORT_SYMBOL(clk_disable);
194EXPORT_SYMBOL(clk_get_rate);
195EXPORT_SYMBOL(clk_round_rate);
196EXPORT_SYMBOL(clk_set_rate);
197EXPORT_SYMBOL(clk_get_parent);
198EXPORT_SYMBOL(clk_set_parent);
199
200/* base clocks */
201
202int clk_default_setrate(struct clk *clk, unsigned long rate)
203{
204 clk->rate = rate;
205 return 0;
206}
207
208struct clk_ops clk_ops_def_setrate = {
209 .set_rate = clk_default_setrate,
210};
211
212struct clk clk_xtal = {
213 .name = "xtal",
214 .rate = 0,
215 .parent = NULL,
216 .ctrlbit = 0,
217};
218
219struct clk clk_ext = {
220 .name = "ext",
221};
222
223struct clk clk_epll = {
224 .name = "epll",
225};
226
227struct clk clk_mpll = {
228 .name = "mpll",
229 .ops = &clk_ops_def_setrate,
230};
231
232struct clk clk_upll = {
233 .name = "upll",
234 .parent = NULL,
235 .ctrlbit = 0,
236};
237
238struct clk clk_f = {
239 .name = "fclk",
240 .rate = 0,
241 .parent = &clk_mpll,
242 .ctrlbit = 0,
243};
244
245struct clk clk_h = {
246 .name = "hclk",
247 .rate = 0,
248 .parent = NULL,
249 .ctrlbit = 0,
250 .ops = &clk_ops_def_setrate,
251};
252
253struct clk clk_p = {
254 .name = "pclk",
255 .rate = 0,
256 .parent = NULL,
257 .ctrlbit = 0,
258 .ops = &clk_ops_def_setrate,
259};
260
261struct clk clk_usb_bus = {
262 .name = "usb-bus",
263 .rate = 0,
264 .parent = &clk_upll,
265};
266
267
268struct clk s3c24xx_uclk = {
269 .name = "uclk",
270};
271
272/* initialise the clock system */
273
274/**
275 * s3c24xx_register_clock() - register a clock
276 * @clk: The clock to register
277 *
278 * Add the specified clock to the list of clocks known by the system.
279 */
280int s3c24xx_register_clock(struct clk *clk)
281{
282 if (clk->enable == NULL)
283 clk->enable = clk_null_enable;
284
285 /* fill up the clk_lookup structure and register it*/
286 clk->lookup.dev_id = clk->devname;
287 clk->lookup.con_id = clk->name;
288 clk->lookup.clk = clk;
289 clkdev_add(&clk->lookup);
290
291 return 0;
292}
293
294/**
295 * s3c24xx_register_clocks() - register an array of clock pointers
296 * @clks: Pointer to an array of struct clk pointers
297 * @nr_clks: The number of clocks in the @clks array.
298 *
299 * Call s3c24xx_register_clock() for all the clock pointers contained
300 * in the @clks list. Returns the number of failures.
301 */
302int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
303{
304 int fails = 0;
305
306 for (; nr_clks > 0; nr_clks--, clks++) {
307 if (s3c24xx_register_clock(*clks) < 0) {
308 struct clk *clk = *clks;
309 printk(KERN_ERR "%s: failed to register %p: %s\n",
310 __func__, clk, clk->name);
311 fails++;
312 }
313 }
314
315 return fails;
316}
317
318/**
319 * s3c_register_clocks() - register an array of clocks
320 * @clkp: Pointer to the first clock in the array.
321 * @nr_clks: Number of clocks to register.
322 *
323 * Call s3c24xx_register_clock() on the @clkp array given, printing an
324 * error if it fails to register the clock (unlikely).
325 */
326void __init s3c_register_clocks(struct clk *clkp, int nr_clks)
327{
328 int ret;
329
330 for (; nr_clks > 0; nr_clks--, clkp++) {
331 ret = s3c24xx_register_clock(clkp);
332
333 if (ret < 0) {
334 printk(KERN_ERR "Failed to register clock %s (%d)\n",
335 clkp->name, ret);
336 }
337 }
338}
339
340/**
341 * s3c_disable_clocks() - disable an array of clocks
342 * @clkp: Pointer to the first clock in the array.
343 * @nr_clks: Number of clocks to register.
344 *
345 * for internal use only at initialisation time. disable the clocks in the
346 * @clkp array.
347 */
348
349void __init s3c_disable_clocks(struct clk *clkp, int nr_clks)
350{
351 for (; nr_clks > 0; nr_clks--, clkp++)
352 (clkp->enable)(clkp, 0);
353}
354
355/* initialise all the clocks */
356
357int __init s3c24xx_register_baseclocks(unsigned long xtal)
358{
359 printk(KERN_INFO "S3C24XX Clocks, Copyright 2004 Simtec Electronics\n");
360
361 clk_xtal.rate = xtal;
362
363 /* register our clocks */
364
365 if (s3c24xx_register_clock(&clk_xtal) < 0)
366 printk(KERN_ERR "failed to register master xtal\n");
367
368 if (s3c24xx_register_clock(&clk_mpll) < 0)
369 printk(KERN_ERR "failed to register mpll clock\n");
370
371 if (s3c24xx_register_clock(&clk_upll) < 0)
372 printk(KERN_ERR "failed to register upll clock\n");
373
374 if (s3c24xx_register_clock(&clk_f) < 0)
375 printk(KERN_ERR "failed to register cpu fclk\n");
376
377 if (s3c24xx_register_clock(&clk_h) < 0)
378 printk(KERN_ERR "failed to register cpu hclk\n");
379
380 if (s3c24xx_register_clock(&clk_p) < 0)
381 printk(KERN_ERR "failed to register cpu pclk\n");
382
383 return 0;
384}
385
386#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
387/* debugfs support to trace clock tree hierarchy and attributes */
388
389static struct dentry *clk_debugfs_root;
390
391static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level)
392{
393 struct clk *child;
394 const char *state;
395 char buf[255] = { 0 };
396 int n = 0;
397
398 if (c->name)
399 n = snprintf(buf, sizeof(buf) - 1, "%s", c->name);
400
401 if (c->devname)
402 n += snprintf(buf + n, sizeof(buf) - 1 - n, ":%s", c->devname);
403
404 state = (c->usage > 0) ? "on" : "off";
405
406 seq_printf(s, "%*s%-*s %-6s %-3d %-10lu\n",
407 level * 3 + 1, "",
408 50 - level * 3, buf,
409 state, c->usage, clk_get_rate(c));
410
411 list_for_each_entry(child, &clocks, list) {
412 if (child->parent != c)
413 continue;
414
415 clock_tree_show_one(s, child, level + 1);
416 }
417}
418
419static int clock_tree_show(struct seq_file *s, void *data)
420{
421 struct clk *c;
422 unsigned long flags;
423
424 seq_printf(s, " clock state ref rate\n");
425 seq_printf(s, "----------------------------------------------------\n");
426
427 spin_lock_irqsave(&clocks_lock, flags);
428
429 list_for_each_entry(c, &clocks, list)
430 if (c->parent == NULL)
431 clock_tree_show_one(s, c, 0);
432
433 spin_unlock_irqrestore(&clocks_lock, flags);
434 return 0;
435}
436
437static int clock_tree_open(struct inode *inode, struct file *file)
438{
439 return single_open(file, clock_tree_show, inode->i_private);
440}
441
442static const struct file_operations clock_tree_fops = {
443 .open = clock_tree_open,
444 .read = seq_read,
445 .llseek = seq_lseek,
446 .release = single_release,
447};
448
449static int clock_rate_show(void *data, u64 *val)
450{
451 struct clk *c = data;
452 *val = clk_get_rate(c);
453 return 0;
454}
455DEFINE_SIMPLE_ATTRIBUTE(clock_rate_fops, clock_rate_show, NULL, "%llu\n");
456
457static int clk_debugfs_register_one(struct clk *c)
458{
459 int err;
460 struct dentry *d;
461 struct clk *pa = c->parent;
462 char s[255];
463 char *p = s;
464
465 p += sprintf(p, "%s", c->devname);
466
467 d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
468 if (!d)
469 return -ENOMEM;
470
471 c->dent = d;
472
473 d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usage);
474 if (!d) {
475 err = -ENOMEM;
476 goto err_out;
477 }
478
479 d = debugfs_create_file("rate", S_IRUGO, c->dent, c, &clock_rate_fops);
480 if (!d) {
481 err = -ENOMEM;
482 goto err_out;
483 }
484 return 0;
485
486err_out:
487 debugfs_remove_recursive(c->dent);
488 return err;
489}
490
491static int clk_debugfs_register(struct clk *c)
492{
493 int err;
494 struct clk *pa = c->parent;
495
496 if (pa && !pa->dent) {
497 err = clk_debugfs_register(pa);
498 if (err)
499 return err;
500 }
501
502 if (!c->dent) {
503 err = clk_debugfs_register_one(c);
504 if (err)
505 return err;
506 }
507 return 0;
508}
509
510static int __init clk_debugfs_init(void)
511{
512 struct clk *c;
513 struct dentry *d;
514 int err = -ENOMEM;
515
516 d = debugfs_create_dir("clock", NULL);
517 if (!d)
518 return -ENOMEM;
519 clk_debugfs_root = d;
520
521 d = debugfs_create_file("clock_tree", S_IRUGO, clk_debugfs_root, NULL,
522 &clock_tree_fops);
523 if (!d)
524 goto err_out;
525
526 list_for_each_entry(c, &clocks, list) {
527 err = clk_debugfs_register(c);
528 if (err)
529 goto err_out;
530 }
531 return 0;
532
533err_out:
534 debugfs_remove_recursive(clk_debugfs_root);
535 return err;
536}
537late_initcall(clk_debugfs_init);
538
539#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */
diff --git a/arch/arm/plat-samsung/include/plat/clock-clksrc.h b/arch/arm/plat-samsung/include/plat/clock-clksrc.h
deleted file mode 100644
index 50a8ca7c3760..000000000000
--- a/arch/arm/plat-samsung/include/plat/clock-clksrc.h
+++ /dev/null
@@ -1,83 +0,0 @@
1/* linux/arch/arm/plat-samsung/include/plat/clock-clksrc.h
2 *
3 * Parts taken from arch/arm/plat-s3c64xx/clock.c
4 * Copyright 2008 Openmoko, Inc.
5 * Copyright 2008 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * http://armlinux.simtec.co.uk/
8 *
9 * Copyright 2009 Ben Dooks <ben-linux@fluff.org>
10 * Copyright 2009 Harald Welte
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15*/
16
17/**
18 * struct clksrc_sources - list of sources for a given clock
19 * @sources: array of pointers to clocks
20 * @nr_sources: The size of @sources
21 */
22struct clksrc_sources {
23 unsigned int nr_sources;
24 struct clk **sources;
25};
26
27/**
28 * struct clksrc_reg - register definition for clock control bits
29 * @reg: pointer to the register in virtual memory.
30 * @shift: the shift in bits to where the bitfield is.
31 * @size: the size in bits of the bitfield.
32 *
33 * This specifies the size and position of the bits we are interested
34 * in within the register specified by @reg.
35 */
36struct clksrc_reg {
37 void __iomem *reg;
38 unsigned short shift;
39 unsigned short size;
40};
41
42/**
43 * struct clksrc_clk - class of clock for newer style samsung devices.
44 * @clk: the standard clock representation
45 * @sources: the sources for this clock
46 * @reg_src: the register definition for selecting the clock's source
47 * @reg_div: the register definition for the clock's output divisor
48 *
49 * This clock implements the features required by the newer SoCs where
50 * the standard clock block provides an input mux and a post-mux divisor
51 * to provide the periperhal's clock.
52 *
53 * The array of @sources provides the mapping of mux position to the
54 * clock, and @reg_src shows the code where to modify to change the mux
55 * position. The @reg_div defines how to change the divider settings on
56 * the output.
57 */
58struct clksrc_clk {
59 struct clk clk;
60 struct clksrc_sources *sources;
61
62 struct clksrc_reg reg_src;
63 struct clksrc_reg reg_div;
64};
65
66/**
67 * s3c_set_clksrc() - setup the clock from the register settings
68 * @clk: The clock to setup.
69 * @announce: true to announce the setting to printk().
70 *
71 * Setup the clock from the current register settings, for when the
72 * kernel boots or if it is resuming from a possibly unknown state.
73 */
74extern void s3c_set_clksrc(struct clksrc_clk *clk, bool announce);
75
76/**
77 * s3c_register_clksrc() register clocks from an array of clksrc clocks
78 * @srcs: The array of clocks to register
79 * @size: The size of the @srcs array.
80 *
81 * Initialise and register the array of clocks described by @srcs.
82 */
83extern void s3c_register_clksrc(struct clksrc_clk *srcs, int size);
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
deleted file mode 100644
index 63239f409807..000000000000
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ /dev/null
@@ -1,152 +0,0 @@
1/* linux/arch/arm/plat-s3c/include/plat/clock.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/SWLINUX/
5 * Written by Ben Dooks, <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef __ASM_PLAT_CLOCK_H
13#define __ASM_PLAT_CLOCK_H __FILE__
14
15#include <linux/spinlock.h>
16#include <linux/clkdev.h>
17
18struct clk;
19
20/**
21 * struct clk_ops - standard clock operations
22 * @set_rate: set the clock rate, see clk_set_rate().
23 * @get_rate: get the clock rate, see clk_get_rate().
24 * @round_rate: round a given clock rate, see clk_round_rate().
25 * @set_parent: set the clock's parent, see clk_set_parent().
26 *
27 * Group the common clock implementations together so that we
28 * don't have to keep setting the same fields again. We leave
29 * enable in struct clk.
30 *
31 * Adding an extra layer of indirection into the process should
32 * not be a problem as it is unlikely these operations are going
33 * to need to be called quickly.
34 */
35struct clk_ops {
36 int (*set_rate)(struct clk *c, unsigned long rate);
37 unsigned long (*get_rate)(struct clk *c);
38 unsigned long (*round_rate)(struct clk *c, unsigned long rate);
39 int (*set_parent)(struct clk *c, struct clk *parent);
40};
41
42struct clk {
43 struct list_head list;
44 struct module *owner;
45 struct clk *parent;
46 const char *name;
47 const char *devname;
48 int id;
49 int usage;
50 unsigned long rate;
51 unsigned long ctrlbit;
52
53 struct clk_ops *ops;
54 int (*enable)(struct clk *, int enable);
55 struct clk_lookup lookup;
56#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
57 struct dentry *dent; /* For visible tree hierarchy */
58#endif
59};
60
61/* other clocks which may be registered by board support */
62
63extern struct clk s3c24xx_dclk0;
64extern struct clk s3c24xx_dclk1;
65extern struct clk s3c24xx_clkout0;
66extern struct clk s3c24xx_clkout1;
67extern struct clk s3c24xx_uclk;
68
69extern struct clk clk_usb_bus;
70
71/* core clock support */
72
73extern struct clk clk_f;
74extern struct clk clk_h;
75extern struct clk clk_p;
76extern struct clk clk_mpll;
77extern struct clk clk_upll;
78extern struct clk clk_epll;
79extern struct clk clk_xtal;
80extern struct clk clk_ext;
81
82/* S3C2443/S3C2416 specific clocks */
83extern struct clksrc_clk clk_epllref;
84extern struct clksrc_clk clk_esysclk;
85
86/* S3C24XX UART clocks */
87extern struct clk s3c24xx_clk_uart0;
88extern struct clk s3c24xx_clk_uart1;
89extern struct clk s3c24xx_clk_uart2;
90
91/* S3C64XX specific clocks */
92extern struct clk clk_h2;
93extern struct clk clk_27m;
94extern struct clk clk_48m;
95extern struct clk clk_xusbxti;
96
97extern int clk_default_setrate(struct clk *clk, unsigned long rate);
98extern struct clk_ops clk_ops_def_setrate;
99
100/* exports for arch/arm/mach-s3c2410
101 *
102 * Please DO NOT use these outside of arch/arm/mach-s3c2410
103*/
104
105extern spinlock_t clocks_lock;
106
107extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
108
109extern int s3c24xx_register_clock(struct clk *clk);
110extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
111
112extern void s3c_register_clocks(struct clk *clk, int nr_clks);
113extern void s3c_disable_clocks(struct clk *clkp, int nr_clks);
114
115extern int s3c24xx_register_baseclocks(unsigned long xtal);
116
117extern void s5p_register_clocks(unsigned long xtal_freq);
118
119extern void s3c24xx_setup_clocks(unsigned long fclk,
120 unsigned long hclk,
121 unsigned long pclk);
122
123extern void s3c2410_setup_clocks(void);
124extern void s3c2412_setup_clocks(void);
125extern void s3c244x_setup_clocks(void);
126
127/* S3C2410 specific clock functions */
128
129extern int s3c2410_baseclk_add(void);
130
131/* S3C2443/S3C2416 specific clock functions */
132
133typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base);
134
135extern void s3c2443_common_setup_clocks(pll_fn get_mpll);
136extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
137 unsigned int *divs, int nr_divs,
138 int divmask);
139
140extern int s3c2443_clkcon_enable_h(struct clk *clk, int enable);
141extern int s3c2443_clkcon_enable_p(struct clk *clk, int enable);
142extern int s3c2443_clkcon_enable_s(struct clk *clk, int enable);
143
144/* S3C64XX specific functions and clocks */
145
146extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable);
147
148/* Global watchdog clock used by arch_wtd_reset() callback */
149
150extern struct clk *s3c2410_wdtclk;
151
152#endif /* __ASM_PLAT_CLOCK_H */
diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
index 72d4178ad23b..317c52303288 100644
--- a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
+++ b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
@@ -140,7 +140,6 @@ struct s3c_cpufreq_config {
140 * any frequency changes. This is really only need by devices like the 140 * any frequency changes. This is really only need by devices like the
141 * S3C2410 where there is no or limited divider between the PLL and the 141 * S3C2410 where there is no or limited divider between the PLL and the
142 * ARMCLK. 142 * ARMCLK.
143 * @resume_clocks: Update the clocks on resume.
144 * @get_iotiming: Get the current IO timing data, mainly for use at start. 143 * @get_iotiming: Get the current IO timing data, mainly for use at start.
145 * @set_iotiming: Update the IO timings from the cached copies calculated 144 * @set_iotiming: Update the IO timings from the cached copies calculated
146 * from the @calc_iotiming entry when changing the frequency. 145 * from the @calc_iotiming entry when changing the frequency.
@@ -169,8 +168,6 @@ struct s3c_cpufreq_info {
169 168
170 /* driver routines */ 169 /* driver routines */
171 170
172 void (*resume_clocks)(void);
173
174 int (*get_iotiming)(struct s3c_cpufreq_config *cfg, 171 int (*get_iotiming)(struct s3c_cpufreq_config *cfg,
175 struct s3c_iotimings *timings); 172 struct s3c_iotimings *timings);
176 173
diff --git a/arch/arm/plat-samsung/include/plat/pll.h b/arch/arm/plat-samsung/include/plat/pll.h
deleted file mode 100644
index 357af7c1c664..000000000000
--- a/arch/arm/plat-samsung/include/plat/pll.h
+++ /dev/null
@@ -1,323 +0,0 @@
1/* linux/arch/arm/plat-samsung/include/plat/pll.h
2 *
3 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * Samsung PLL codes
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16*/
17
18#include <asm/div64.h>
19
20#define S3C24XX_PLL_MDIV_MASK (0xFF)
21#define S3C24XX_PLL_PDIV_MASK (0x1F)
22#define S3C24XX_PLL_SDIV_MASK (0x3)
23#define S3C24XX_PLL_MDIV_SHIFT (12)
24#define S3C24XX_PLL_PDIV_SHIFT (4)
25#define S3C24XX_PLL_SDIV_SHIFT (0)
26
27static inline unsigned int s3c24xx_get_pll(unsigned int pllval,
28 unsigned int baseclk)
29{
30 unsigned int mdiv, pdiv, sdiv;
31 uint64_t fvco;
32
33 mdiv = (pllval >> S3C24XX_PLL_MDIV_SHIFT) & S3C24XX_PLL_MDIV_MASK;
34 pdiv = (pllval >> S3C24XX_PLL_PDIV_SHIFT) & S3C24XX_PLL_PDIV_MASK;
35 sdiv = (pllval >> S3C24XX_PLL_SDIV_SHIFT) & S3C24XX_PLL_SDIV_MASK;
36
37 fvco = (uint64_t)baseclk * (mdiv + 8);
38 do_div(fvco, (pdiv + 2) << sdiv);
39
40 return (unsigned int)fvco;
41}
42
43#define S3C2416_PLL_MDIV_MASK (0x3FF)
44#define S3C2416_PLL_PDIV_MASK (0x3F)
45#define S3C2416_PLL_SDIV_MASK (0x7)
46#define S3C2416_PLL_MDIV_SHIFT (14)
47#define S3C2416_PLL_PDIV_SHIFT (5)
48#define S3C2416_PLL_SDIV_SHIFT (0)
49
50static inline unsigned int s3c2416_get_pll(unsigned int pllval,
51 unsigned int baseclk)
52{
53 unsigned int mdiv, pdiv, sdiv;
54 uint64_t fvco;
55
56 mdiv = (pllval >> S3C2416_PLL_MDIV_SHIFT) & S3C2416_PLL_MDIV_MASK;
57 pdiv = (pllval >> S3C2416_PLL_PDIV_SHIFT) & S3C2416_PLL_PDIV_MASK;
58 sdiv = (pllval >> S3C2416_PLL_SDIV_SHIFT) & S3C2416_PLL_SDIV_MASK;
59
60 fvco = (uint64_t)baseclk * mdiv;
61 do_div(fvco, (pdiv << sdiv));
62
63 return (unsigned int)fvco;
64}
65
66#define S3C6400_PLL_MDIV_MASK (0x3FF)
67#define S3C6400_PLL_PDIV_MASK (0x3F)
68#define S3C6400_PLL_SDIV_MASK (0x7)
69#define S3C6400_PLL_MDIV_SHIFT (16)
70#define S3C6400_PLL_PDIV_SHIFT (8)
71#define S3C6400_PLL_SDIV_SHIFT (0)
72
73static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
74 u32 pllcon)
75{
76 u32 mdiv, pdiv, sdiv;
77 u64 fvco = baseclk;
78
79 mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK;
80 pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK;
81 sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK;
82
83 fvco *= mdiv;
84 do_div(fvco, (pdiv << sdiv));
85
86 return (unsigned long)fvco;
87}
88
89#define PLL6553X_MDIV_MASK (0x7F)
90#define PLL6553X_PDIV_MASK (0x1F)
91#define PLL6553X_SDIV_MASK (0x3)
92#define PLL6553X_KDIV_MASK (0xFFFF)
93#define PLL6553X_MDIV_SHIFT (16)
94#define PLL6553X_PDIV_SHIFT (8)
95#define PLL6553X_SDIV_SHIFT (0)
96
97static inline unsigned long s3c_get_pll6553x(unsigned long baseclk,
98 u32 pll_con0, u32 pll_con1)
99{
100 unsigned long result;
101 u32 mdiv, pdiv, sdiv, kdiv;
102 u64 tmp;
103
104 mdiv = (pll_con0 >> PLL6553X_MDIV_SHIFT) & PLL6553X_MDIV_MASK;
105 pdiv = (pll_con0 >> PLL6553X_PDIV_SHIFT) & PLL6553X_PDIV_MASK;
106 sdiv = (pll_con0 >> PLL6553X_SDIV_SHIFT) & PLL6553X_SDIV_MASK;
107 kdiv = pll_con1 & PLL6553X_KDIV_MASK;
108
109 /*
110 * We need to multiple baseclk by mdiv (the integer part) and kdiv
111 * which is in 2^16ths, so shift mdiv up (does not overflow) and
112 * add kdiv before multiplying. The use of tmp is to avoid any
113 * overflows before shifting bac down into result when multipling
114 * by the mdiv and kdiv pair.
115 */
116
117 tmp = baseclk;
118 tmp *= (mdiv << 16) + kdiv;
119 do_div(tmp, (pdiv << sdiv));
120 result = tmp >> 16;
121
122 return result;
123}
124
125#define PLL35XX_MDIV_MASK (0x3FF)
126#define PLL35XX_PDIV_MASK (0x3F)
127#define PLL35XX_SDIV_MASK (0x7)
128#define PLL35XX_MDIV_SHIFT (16)
129#define PLL35XX_PDIV_SHIFT (8)
130#define PLL35XX_SDIV_SHIFT (0)
131
132static inline unsigned long s5p_get_pll35xx(unsigned long baseclk, u32 pll_con)
133{
134 u32 mdiv, pdiv, sdiv;
135 u64 fvco = baseclk;
136
137 mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
138 pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
139 sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
140
141 fvco *= mdiv;
142 do_div(fvco, (pdiv << sdiv));
143
144 return (unsigned long)fvco;
145}
146
147#define PLL36XX_KDIV_MASK (0xFFFF)
148#define PLL36XX_MDIV_MASK (0x1FF)
149#define PLL36XX_PDIV_MASK (0x3F)
150#define PLL36XX_SDIV_MASK (0x7)
151#define PLL36XX_MDIV_SHIFT (16)
152#define PLL36XX_PDIV_SHIFT (8)
153#define PLL36XX_SDIV_SHIFT (0)
154
155static inline unsigned long s5p_get_pll36xx(unsigned long baseclk,
156 u32 pll_con0, u32 pll_con1)
157{
158 unsigned long result;
159 u32 mdiv, pdiv, sdiv, kdiv;
160 u64 tmp;
161
162 mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
163 pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
164 sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
165 kdiv = pll_con1 & PLL36XX_KDIV_MASK;
166
167 tmp = baseclk;
168
169 tmp *= (mdiv << 16) + kdiv;
170 do_div(tmp, (pdiv << sdiv));
171 result = tmp >> 16;
172
173 return result;
174}
175
176#define PLL45XX_MDIV_MASK (0x3FF)
177#define PLL45XX_PDIV_MASK (0x3F)
178#define PLL45XX_SDIV_MASK (0x7)
179#define PLL45XX_MDIV_SHIFT (16)
180#define PLL45XX_PDIV_SHIFT (8)
181#define PLL45XX_SDIV_SHIFT (0)
182
183enum pll45xx_type_t {
184 pll_4500,
185 pll_4502,
186 pll_4508
187};
188
189static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con,
190 enum pll45xx_type_t pll_type)
191{
192 u32 mdiv, pdiv, sdiv;
193 u64 fvco = baseclk;
194
195 mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
196 pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
197 sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
198
199 if (pll_type == pll_4508)
200 sdiv = sdiv - 1;
201
202 fvco *= mdiv;
203 do_div(fvco, (pdiv << sdiv));
204
205 return (unsigned long)fvco;
206}
207
208/* CON0 bit-fields */
209#define PLL46XX_MDIV_MASK (0x1FF)
210#define PLL46XX_PDIV_MASK (0x3F)
211#define PLL46XX_SDIV_MASK (0x7)
212#define PLL46XX_LOCKED_SHIFT (29)
213#define PLL46XX_MDIV_SHIFT (16)
214#define PLL46XX_PDIV_SHIFT (8)
215#define PLL46XX_SDIV_SHIFT (0)
216
217/* CON1 bit-fields */
218#define PLL46XX_MRR_MASK (0x1F)
219#define PLL46XX_MFR_MASK (0x3F)
220#define PLL46XX_KDIV_MASK (0xFFFF)
221#define PLL4650C_KDIV_MASK (0xFFF)
222#define PLL46XX_MRR_SHIFT (24)
223#define PLL46XX_MFR_SHIFT (16)
224#define PLL46XX_KDIV_SHIFT (0)
225
226enum pll46xx_type_t {
227 pll_4600,
228 pll_4650,
229 pll_4650c,
230};
231
232static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
233 u32 pll_con0, u32 pll_con1,
234 enum pll46xx_type_t pll_type)
235{
236 unsigned long result;
237 u32 mdiv, pdiv, sdiv, kdiv;
238 u64 tmp;
239
240 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
241 pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
242 sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
243 kdiv = pll_con1 & PLL46XX_KDIV_MASK;
244
245 if (pll_type == pll_4650c)
246 kdiv = pll_con1 & PLL4650C_KDIV_MASK;
247 else
248 kdiv = pll_con1 & PLL46XX_KDIV_MASK;
249
250 tmp = baseclk;
251
252 if (pll_type == pll_4600) {
253 tmp *= (mdiv << 16) + kdiv;
254 do_div(tmp, (pdiv << sdiv));
255 result = tmp >> 16;
256 } else {
257 tmp *= (mdiv << 10) + kdiv;
258 do_div(tmp, (pdiv << sdiv));
259 result = tmp >> 10;
260 }
261
262 return result;
263}
264
265#define PLL90XX_MDIV_MASK (0xFF)
266#define PLL90XX_PDIV_MASK (0x3F)
267#define PLL90XX_SDIV_MASK (0x7)
268#define PLL90XX_KDIV_MASK (0xffff)
269#define PLL90XX_LOCKED_SHIFT (29)
270#define PLL90XX_MDIV_SHIFT (16)
271#define PLL90XX_PDIV_SHIFT (8)
272#define PLL90XX_SDIV_SHIFT (0)
273#define PLL90XX_KDIV_SHIFT (0)
274
275static inline unsigned long s5p_get_pll90xx(unsigned long baseclk,
276 u32 pll_con, u32 pll_conk)
277{
278 unsigned long result;
279 u32 mdiv, pdiv, sdiv, kdiv;
280 u64 tmp;
281
282 mdiv = (pll_con >> PLL90XX_MDIV_SHIFT) & PLL90XX_MDIV_MASK;
283 pdiv = (pll_con >> PLL90XX_PDIV_SHIFT) & PLL90XX_PDIV_MASK;
284 sdiv = (pll_con >> PLL90XX_SDIV_SHIFT) & PLL90XX_SDIV_MASK;
285 kdiv = pll_conk & PLL90XX_KDIV_MASK;
286
287 /*
288 * We need to multiple baseclk by mdiv (the integer part) and kdiv
289 * which is in 2^16ths, so shift mdiv up (does not overflow) and
290 * add kdiv before multiplying. The use of tmp is to avoid any
291 * overflows before shifting bac down into result when multipling
292 * by the mdiv and kdiv pair.
293 */
294
295 tmp = baseclk;
296 tmp *= (mdiv << 16) + kdiv;
297 do_div(tmp, (pdiv << sdiv));
298 result = tmp >> 16;
299
300 return result;
301}
302
303#define PLL65XX_MDIV_MASK (0x3FF)
304#define PLL65XX_PDIV_MASK (0x3F)
305#define PLL65XX_SDIV_MASK (0x7)
306#define PLL65XX_MDIV_SHIFT (16)
307#define PLL65XX_PDIV_SHIFT (8)
308#define PLL65XX_SDIV_SHIFT (0)
309
310static inline unsigned long s5p_get_pll65xx(unsigned long baseclk, u32 pll_con)
311{
312 u32 mdiv, pdiv, sdiv;
313 u64 fvco = baseclk;
314
315 mdiv = (pll_con >> PLL65XX_MDIV_SHIFT) & PLL65XX_MDIV_MASK;
316 pdiv = (pll_con >> PLL65XX_PDIV_SHIFT) & PLL65XX_PDIV_MASK;
317 sdiv = (pll_con >> PLL65XX_SDIV_SHIFT) & PLL65XX_SDIV_MASK;
318
319 fvco *= mdiv;
320 do_div(fvco, (pdiv << sdiv));
321
322 return (unsigned long)fvco;
323}
diff --git a/arch/arm/plat-samsung/include/plat/s5p-clock.h b/arch/arm/plat-samsung/include/plat/s5p-clock.h
deleted file mode 100644
index acacc4b88a39..000000000000
--- a/arch/arm/plat-samsung/include/plat/s5p-clock.h
+++ /dev/null
@@ -1,65 +0,0 @@
1/* linux/arch/arm/plat-samsung/include/plat/s5p-clock.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Header file for s5p clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_PLAT_S5P_CLOCK_H
14#define __ASM_PLAT_S5P_CLOCK_H __FILE__
15
16#include <linux/clk.h>
17
18#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
19
20#define clk_fin_apll clk_ext_xtal_mux
21#define clk_fin_bpll clk_ext_xtal_mux
22#define clk_fin_cpll clk_ext_xtal_mux
23#define clk_fin_mpll clk_ext_xtal_mux
24#define clk_fin_epll clk_ext_xtal_mux
25#define clk_fin_dpll clk_ext_xtal_mux
26#define clk_fin_vpll clk_ext_xtal_mux
27#define clk_fin_hpll clk_ext_xtal_mux
28
29extern struct clk clk_ext_xtal_mux;
30extern struct clk clk_xusbxti;
31extern struct clk clk_48m;
32extern struct clk s5p_clk_27m;
33extern struct clk clk_fout_apll;
34extern struct clk clk_fout_bpll;
35extern struct clk clk_fout_bpll_div2;
36extern struct clk clk_fout_cpll;
37extern struct clk clk_fout_mpll;
38extern struct clk clk_fout_mpll_div2;
39extern struct clk clk_fout_epll;
40extern struct clk clk_fout_dpll;
41extern struct clk clk_fout_vpll;
42extern struct clk clk_arm;
43extern struct clk clk_vpll;
44
45extern struct clksrc_sources clk_src_apll;
46extern struct clksrc_sources clk_src_bpll;
47extern struct clksrc_sources clk_src_bpll_fout;
48extern struct clksrc_sources clk_src_cpll;
49extern struct clksrc_sources clk_src_mpll;
50extern struct clksrc_sources clk_src_mpll_fout;
51extern struct clksrc_sources clk_src_epll;
52extern struct clksrc_sources clk_src_dpll;
53
54extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable);
55
56/* Common EPLL operations for S5P platform */
57extern int s5p_epll_enable(struct clk *clk, int enable);
58extern unsigned long s5p_epll_get_rate(struct clk *clk);
59
60/* SPDIF clk operations common for S5PV210/C110 and Exynos4 */
61extern int s5p_spdif_set_rate(struct clk *clk, unsigned long rate);
62extern unsigned long s5p_spdif_get_rate(struct clk *clk);
63
64extern struct clk_ops s5p_sclk_spdif_ops;
65#endif /* __ASM_PLAT_S5P_CLOCK_H */
diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c
index a1f925f3121f..11fbbc26e49f 100644
--- a/arch/arm/plat-samsung/init.c
+++ b/arch/arm/plat-samsung/init.c
@@ -30,7 +30,6 @@
30 30
31#include <plat/cpu.h> 31#include <plat/cpu.h>
32#include <plat/devs.h> 32#include <plat/devs.h>
33#include <plat/clock.h>
34 33
35static struct cpu_table *cpu; 34static struct cpu_table *cpu;
36 35
diff --git a/arch/arm/plat-samsung/s5p-clock.c b/arch/arm/plat-samsung/s5p-clock.c
deleted file mode 100644
index 48a159911037..000000000000
--- a/arch/arm/plat-samsung/s5p-clock.c
+++ /dev/null
@@ -1,294 +0,0 @@
1/*
2 * Copyright 2009 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
4 *
5 * S5P - Common clock support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/errno.h>
17#include <linux/err.h>
18#include <linux/clk.h>
19#include <linux/device.h>
20#include <linux/io.h>
21#include <asm/div64.h>
22
23#include <mach/regs-clock.h>
24
25#include <plat/clock.h>
26#include <plat/clock-clksrc.h>
27#include <plat/s5p-clock.h>
28
29/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
30 * clk_ext_xtal_mux.
31*/
32struct clk clk_ext_xtal_mux = {
33 .name = "ext_xtal",
34 .id = -1,
35};
36
37struct clk clk_xusbxti = {
38 .name = "xusbxti",
39 .id = -1,
40 .rate = 24000000,
41};
42
43struct clk s5p_clk_27m = {
44 .name = "clk_27m",
45 .id = -1,
46 .rate = 27000000,
47};
48
49/* 48MHz USB Phy clock output */
50struct clk clk_48m = {
51 .name = "clk_48m",
52 .id = -1,
53 .rate = 48000000,
54};
55
56/* APLL clock output
57 * No need .ctrlbit, this is always on
58*/
59struct clk clk_fout_apll = {
60 .name = "fout_apll",
61 .id = -1,
62};
63
64/* BPLL clock output */
65
66struct clk clk_fout_bpll = {
67 .name = "fout_bpll",
68 .id = -1,
69};
70
71struct clk clk_fout_bpll_div2 = {
72 .name = "fout_bpll_div2",
73 .id = -1,
74};
75
76/* CPLL clock output */
77
78struct clk clk_fout_cpll = {
79 .name = "fout_cpll",
80 .id = -1,
81};
82
83/* MPLL clock output
84 * No need .ctrlbit, this is always on
85*/
86struct clk clk_fout_mpll = {
87 .name = "fout_mpll",
88 .id = -1,
89};
90
91struct clk clk_fout_mpll_div2 = {
92 .name = "fout_mpll_div2",
93 .id = -1,
94};
95
96/* EPLL clock output */
97struct clk clk_fout_epll = {
98 .name = "fout_epll",
99 .id = -1,
100 .ctrlbit = (1 << 31),
101};
102
103/* DPLL clock output */
104struct clk clk_fout_dpll = {
105 .name = "fout_dpll",
106 .id = -1,
107 .ctrlbit = (1 << 31),
108};
109
110/* VPLL clock output */
111struct clk clk_fout_vpll = {
112 .name = "fout_vpll",
113 .id = -1,
114 .ctrlbit = (1 << 31),
115};
116
117/* Possible clock sources for APLL Mux */
118static struct clk *clk_src_apll_list[] = {
119 [0] = &clk_fin_apll,
120 [1] = &clk_fout_apll,
121};
122
123struct clksrc_sources clk_src_apll = {
124 .sources = clk_src_apll_list,
125 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
126};
127
128/* Possible clock sources for BPLL Mux */
129static struct clk *clk_src_bpll_list[] = {
130 [0] = &clk_fin_bpll,
131 [1] = &clk_fout_bpll,
132};
133
134struct clksrc_sources clk_src_bpll = {
135 .sources = clk_src_bpll_list,
136 .nr_sources = ARRAY_SIZE(clk_src_bpll_list),
137};
138
139static struct clk *clk_src_bpll_fout_list[] = {
140 [0] = &clk_fout_bpll_div2,
141 [1] = &clk_fout_bpll,
142};
143
144struct clksrc_sources clk_src_bpll_fout = {
145 .sources = clk_src_bpll_fout_list,
146 .nr_sources = ARRAY_SIZE(clk_src_bpll_fout_list),
147};
148
149/* Possible clock sources for CPLL Mux */
150static struct clk *clk_src_cpll_list[] = {
151 [0] = &clk_fin_cpll,
152 [1] = &clk_fout_cpll,
153};
154
155struct clksrc_sources clk_src_cpll = {
156 .sources = clk_src_cpll_list,
157 .nr_sources = ARRAY_SIZE(clk_src_cpll_list),
158};
159
160/* Possible clock sources for MPLL Mux */
161static struct clk *clk_src_mpll_list[] = {
162 [0] = &clk_fin_mpll,
163 [1] = &clk_fout_mpll,
164};
165
166struct clksrc_sources clk_src_mpll = {
167 .sources = clk_src_mpll_list,
168 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
169};
170
171static struct clk *clk_src_mpll_fout_list[] = {
172 [0] = &clk_fout_mpll_div2,
173 [1] = &clk_fout_mpll,
174};
175
176struct clksrc_sources clk_src_mpll_fout = {
177 .sources = clk_src_mpll_fout_list,
178 .nr_sources = ARRAY_SIZE(clk_src_mpll_fout_list),
179};
180
181/* Possible clock sources for EPLL Mux */
182static struct clk *clk_src_epll_list[] = {
183 [0] = &clk_fin_epll,
184 [1] = &clk_fout_epll,
185};
186
187struct clksrc_sources clk_src_epll = {
188 .sources = clk_src_epll_list,
189 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
190};
191
192/* Possible clock sources for DPLL Mux */
193static struct clk *clk_src_dpll_list[] = {
194 [0] = &clk_fin_dpll,
195 [1] = &clk_fout_dpll,
196};
197
198struct clksrc_sources clk_src_dpll = {
199 .sources = clk_src_dpll_list,
200 .nr_sources = ARRAY_SIZE(clk_src_dpll_list),
201};
202
203struct clk clk_vpll = {
204 .name = "vpll",
205 .id = -1,
206};
207
208int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable)
209{
210 unsigned int ctrlbit = clk->ctrlbit;
211 u32 con;
212
213 con = __raw_readl(reg);
214 con = enable ? (con | ctrlbit) : (con & ~ctrlbit);
215 __raw_writel(con, reg);
216 return 0;
217}
218
219int s5p_epll_enable(struct clk *clk, int enable)
220{
221 unsigned int ctrlbit = clk->ctrlbit;
222 unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
223
224 if (enable)
225 __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
226 else
227 __raw_writel(epll_con, S5P_EPLL_CON);
228
229 return 0;
230}
231
232unsigned long s5p_epll_get_rate(struct clk *clk)
233{
234 return clk->rate;
235}
236
237int s5p_spdif_set_rate(struct clk *clk, unsigned long rate)
238{
239 struct clk *pclk;
240 int ret;
241
242 pclk = clk_get_parent(clk);
243 if (IS_ERR(pclk))
244 return -EINVAL;
245
246 ret = pclk->ops->set_rate(pclk, rate);
247 clk_put(pclk);
248
249 return ret;
250}
251
252unsigned long s5p_spdif_get_rate(struct clk *clk)
253{
254 struct clk *pclk;
255 int rate;
256
257 pclk = clk_get_parent(clk);
258 if (IS_ERR(pclk))
259 return -EINVAL;
260
261 rate = pclk->ops->get_rate(pclk);
262 clk_put(pclk);
263
264 return rate;
265}
266
267struct clk_ops s5p_sclk_spdif_ops = {
268 .set_rate = s5p_spdif_set_rate,
269 .get_rate = s5p_spdif_get_rate,
270};
271
272static struct clk *s5p_clks[] __initdata = {
273 &clk_ext_xtal_mux,
274 &clk_48m,
275 &s5p_clk_27m,
276 &clk_fout_apll,
277 &clk_fout_mpll,
278 &clk_fout_epll,
279 &clk_fout_dpll,
280 &clk_fout_vpll,
281 &clk_vpll,
282 &clk_xusbxti,
283};
284
285void __init s5p_register_clocks(unsigned long xtal_freq)
286{
287 int ret;
288
289 clk_ext_xtal_mux.rate = xtal_freq;
290
291 ret = s3c24xx_register_clocks(s5p_clks, ARRAY_SIZE(s5p_clks));
292 if (ret > 0)
293 printk(KERN_ERR "Failed to register s5p clocks\n");
294}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 05:10:16 -0500