Merge tag 'imx-soc-3.15' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc

i.MX SoC changes for 3.15 from Shawn Guo: - Support suspend from ocram (DDR IO floating) for imx6 platforms - Add cpuidle support for imx6sl - Sparse warning fixes for imx6sl and vf610 clock code - Remove PWM platform code - Support ptp and rmii clock from pad - Support WEIM CS GPR configuration - Random cleanups and defconfig updates * tag 'imx-soc-3.15' of git://git.linaro.org/people/shawnguo/linux-2.6: (373 commits) ARM: imx6: drop .text.head section annotation from headsmp.S ARM: imx6: build suspend-imx6.o with CONFIG_SOC_IMX6 ARM: imx6: rename pm-imx6q.c to pm-imx6.c ARM: imx6: introduce CONFIG_SOC_IMX6 for i.MX6 common stuff ARM: imx6: do not call imx6q_suspend_init() with !CONFIG_SUSPEND ARM: imx6: call suspend_set_ops() from suspend routine ARM: imx6: build headsmp.o only on CONFIG_SMP ARM: imx6: move v7_cpu_resume() into suspend-imx6.S ARM i.MX6q: Mark VPU and IPU AXI transfers as cacheable, increase IPU priority ARM: imx6q: Add GPR6 and GPR7 register definitions for iomuxc gpr bus: imx-weim: support CS GPR configuration ARM: mach-imx: Kconfig: Remove IMX_HAVE_PLATFORM_IMX2_WDT from SOC_IMX53 ARM: imx_v6_v7_defconfig: Select CONFIG_DEBUG_FS ARM: mach-imx: Select CONFIG_SRAM at ARCH_MXC level ARM: imx: add speed grading check for i.mx6 soc ARM: imx: avoid calling clk APIs in idle thread which may cause schedule ARM: imx6q: support ptp and rmii clock from pad ARM: imx6q: remove unneeded clk lookups ARM: imx_v6_v7_defconfig: Select CONFIG_MMC_UNSAFE_RESUME ARM: imx_v4_v5_defconfig: Select CONFIG_MMC_UNSAFE_RESUME ...
author: Olof Johansson <olof@lixom.net> 2014-03-09 15:03:18 -0400
committer: Olof Johansson <olof@lixom.net> 2014-03-09 15:03:18 -0400
commit: 1760e4f855a2ead08a40deac9abd4fb8cdf3af32 (patch)
tree: 8ee1c79f4c46fd225d90e832def3d7f7e3742086 /arch/arm
parent: 1e871089f66416ce540d8e362225a0878a5d2c06 (diff)
parent: c8ae7e9bfc8caf679e891c4f0a04f2435b45e2da (diff)
98 files changed, 1442 insertions, 882 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d57b4753585d..cbee1169b883 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -306,9 +306,11 @@ choice
 config ARCH_MULTIPLATFORM
        bool "Allow multiple platforms to be selected"
        depends on MMU
+        select ARCH_WANT_OPTIONAL_GPIOLIB
        select ARM_PATCH_PHYS_VIRT
        select AUTO_ZRELADDR
        select COMMON_CLK
+        select GENERIC_CLOCKEVENTS
        select MULTI_IRQ_HANDLER
        select SPARSE_IRQ
        select USE_OF
@@ -905,16 +907,18 @@ config ARCH_MULTI_V4_V5
 config ARCH_MULTI_V6
        bool "ARMv6 based platforms (ARM11)"
        select ARCH_MULTI_V6_V7
-        select CPU_V6
+        select CPU_V6K
 config ARCH_MULTI_V7
        bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
        default y
        select ARCH_MULTI_V6_V7
        select CPU_V7
+        select HAVE_SMP
 config ARCH_MULTI_V6_V7
        bool
+        select MIGHT_HAVE_CACHE_L2X0
 config ARCH_MULTI_CPU_AUTO
        def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
@@ -922,6 +926,13 @@ config ARCH_MULTI_CPU_AUTO
 endmenu
+config ARCH_VIRT
+        bool "Dummy Virtual Machine" if ARCH_MULTI_V7
+        select ARM_AMBA
+        select ARM_GIC
+        select ARM_PSCI
+        select HAVE_ARM_ARCH_TIMER
 #
 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 # Kconfigs may be included either alphabetically (according to the
@@ -1047,8 +1058,6 @@ source "arch/arm/mach-versatile/Kconfig"
 source "arch/arm/mach-vexpress/Kconfig"
 source "arch/arm/plat-versatile/Kconfig"
-source "arch/arm/mach-virt/Kconfig"
 source "arch/arm/mach-vt8500/Kconfig"
 source "arch/arm/mach-w90x900/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 51e5bede657f..dd1bd7ed77be 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -200,7 +200,6 @@ machine-$(CONFIG_ARCH_U300)		+= u300
 machine-$(CONFIG_ARCH_U8500)            += ux500
 machine-$(CONFIG_ARCH_VERSATILE)        += versatile
 machine-$(CONFIG_ARCH_VEXPRESS)         += vexpress
-machine-$(CONFIG_ARCH_VIRT)             += virt
 machine-$(CONFIG_ARCH_VT8500)           += vt8500
 machine-$(CONFIG_ARCH_W90X900)          += w90x900
 machine-$(CONFIG_ARCH_ZYNQ)             += zynq
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 3269029a1ce6..4a89023f55ab 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -206,7 +206,8 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
        omap3-n900.dtb \
        omap3-n9.dtb \
        omap3-n950.dtb \
-        omap3-tobi.dtb \
+        omap3-overo-tobi.dtb \
+        omap3-overo-storm-tobi.dtb \
        omap3-gta04.dtb \
        omap3-igep0020.dtb \
        omap3-igep0030.dtb \
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index 4718ec4a4dbf..486880b74831 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -121,7 +121,7 @@
                ti,model = "AM335x-EVMSK";
                ti,audio-codec = <&tlv320aic3106>;
                ti,mcasp-controller = <&mcasp1>;
-                ti,codec-clock-rate = <24576000>;
+                ti,codec-clock-rate = <24000000>;
                ti,audio-routing =
                        "Headphone Jack",       "HPLOUT",
                        "Headphone Jack",       "HPROUT";
@@ -256,6 +256,12 @@
                >;
        };
+        mmc1_pins: pinmux_mmc1_pins {
+                pinctrl-single,pins = <
+                        0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+                >;
+        };
        mcasp1_pins: mcasp1_pins {
                pinctrl-single,pins = <
                        0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
@@ -456,6 +462,9 @@
        status = "okay";
        vmmc-supply = <&vmmc_reg>;
        bus-width = <4>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins>;
+        cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
 };
 &sham {
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 66609684d41b..9480cf891f8c 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -23,6 +23,7 @@
                gpio0 = &gpio0;
                gpio1 = &gpio1;
                gpio2 = &gpio2;
+                eth3 = &eth3;
        };
        cpus {
@@ -291,7 +292,7 @@
                                interrupts = <91>;
                        };
-                        ethernet@34000 {
+                        eth3: ethernet@34000 {
                                compatible = "marvell,armada-370-neta";
                                reg = <0x34000 0x4000>;
                                interrupts = <14>;
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 2b76524f4aa7..187fd46b7b5e 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -379,15 +379,6 @@
                                #clock-cells = <1>;
                        };
-                        pmu_intc: pmu-interrupt-ctrl@d0050 {
-                                compatible = "marvell,dove-pmu-intc";
-                                interrupt-controller;
-                                #interrupt-cells = <1>;
-                                reg = <0xd0050 0x8>;
-                                interrupts = <33>;
-                                marvell,#interrupts = <7>;
-                        };
                        pinctrl: pin-ctrl@d0200 {
                                compatible = "marvell,dove-pinctrl";
                                reg = <0xd0200 0x10>;
@@ -610,8 +601,6 @@
                        rtc: real-time-clock@d8500 {
                                compatible = "marvell,orion-rtc";
                                reg = <0xd8500 0x20>;
-                                interrupt-parent = <&pmu_intc>;
-                                interrupts = <5>;
                        };
                        gpio2: gpio-ctrl@e8400 {
diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts
index fd8fc7cd53f3..5bfae54fb780 100644
--- a/arch/arm/boot/dts/imx6dl-hummingboard.dts
+++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts
@@ -52,12 +52,6 @@
                };
        };
-        codec: spdif-transmitter {
-                compatible = "linux,spdif-dit";
-                pinctrl-names = "default";
-                pinctrl-0 = <&pinctrl_hummingboard_spdif>;
-        };
        sound-spdif {
                compatible = "fsl,imx-audio-spdif";
                model = "imx-spdif";
@@ -111,7 +105,7 @@
                };
                pinctrl_hummingboard_spdif: hummingboard-spdif {
-                        fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0>;
+                        fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
                };
                pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus {
@@ -142,6 +136,8 @@
 };
 &spdif {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hummingboard_spdif>;
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
index 64daa3b311f6..c2a24888a276 100644
--- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
@@ -46,12 +46,6 @@
                };
        };
-        codec: spdif-transmitter {
-                compatible = "linux,spdif-dit";
-                pinctrl-names = "default";
-                pinctrl-0 = <&pinctrl_cubox_i_spdif>;
-        };
        sound-spdif {
                compatible = "fsl,imx-audio-spdif";
                model = "imx-spdif";
@@ -89,7 +83,7 @@
                };
                pinctrl_cubox_i_spdif: cubox-i-spdif {
-                        fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0>;
+                        fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
                };
                pinctrl_cubox_i_usbh1_vbus: cubox-i-usbh1-vbus {
@@ -121,6 +115,8 @@
 };
 &spdif {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_cubox_i_spdif>;
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/omap3-gta04.dts b/arch/arm/boot/dts/omap3-gta04.dts
index b9b55c95a566..c551e4af4d83 100644
--- a/arch/arm/boot/dts/omap3-gta04.dts
+++ b/arch/arm/boot/dts/omap3-gta04.dts
@@ -32,7 +32,7 @@
                aux-button {
                        label = "aux";
                        linux,code = <169>;
-                        gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
+                        gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
                        gpio-key,wakeup;
                };
        };
@@ -92,6 +92,8 @@
        bmp085@77 {
                compatible = "bosch,bmp085";
                reg = <0x77>;
+                interrupt-parent = <&gpio4>;
+                interrupts = <17 IRQ_TYPE_EDGE_RISING>;
        };
        /* leds */
@@ -141,8 +143,8 @@
        pinctrl-names = "default";
        pinctrl-0 = <&mmc1_pins>;
        vmmc-supply = <&vmmc1>;
-        vmmc_aux-supply = <&vsim>;
        bus-width = <4>;
+        ti,non-removable;
 };
 &mmc2 {
diff --git a/arch/arm/boot/dts/omap3-n9.dts b/arch/arm/boot/dts/omap3-n9.dts
index 39828ce464ee..9938b5dc1909 100644
--- a/arch/arm/boot/dts/omap3-n9.dts
+++ b/arch/arm/boot/dts/omap3-n9.dts
@@ -14,5 +14,5 @@
 / {
        model = "Nokia N9";
-        compatible = "nokia,omap3-n9", "ti,omap3";
+        compatible = "nokia,omap3-n9", "ti,omap36xx", "ti,omap3";
 };
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 6fc85f963530..0bf40c90faba 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -1,6 +1,6 @@
 /*
 * Copyright (C) 2013 Pavel Machek <pavel@ucw.cz>
- * Copyright 2013 Aaro Koskinen <aaro.koskinen@iki.fi>
+ * Copyright (C) 2013-2014 Aaro Koskinen <aaro.koskinen@iki.fi>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 (or later) as
@@ -13,7 +13,7 @@
 / {
        model = "Nokia N900";
-        compatible = "nokia,omap3-n900", "ti,omap3";
+        compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3";
        cpus {
                cpu@0 {
diff --git a/arch/arm/boot/dts/omap3-n950.dts b/arch/arm/boot/dts/omap3-n950.dts
index b076a526b999..261c5589bfa3 100644
--- a/arch/arm/boot/dts/omap3-n950.dts
+++ b/arch/arm/boot/dts/omap3-n950.dts
@@ -14,5 +14,5 @@
 / {
        model = "Nokia N950";
-        compatible = "nokia,omap3-n950", "ti,omap3";
+        compatible = "nokia,omap3-n950", "ti,omap36xx", "ti,omap3";
 };
diff --git a/arch/arm/boot/dts/omap3-overo-storm-tobi.dts b/arch/arm/boot/dts/omap3-overo-storm-tobi.dts
new file mode 100644
index 000000000000..966b5c9cd96a
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-storm-tobi.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * Tobi expansion board is manufactured by Gumstix Inc.
+ */
+/dts-v1/;
+#include "omap36xx.dtsi"
+#include "omap3-overo-tobi-common.dtsi"
+/ {
+        model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Tobi";
+        compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+};
diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi
index 7e4ad2aec37a..4edc013a91c1 100644
--- a/arch/arm/boot/dts/omap3-tobi.dts
+++ b/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi
@@ -13,9 +13,6 @@
 #include "omap3-overo.dtsi"
 / {
-        model = "TI OMAP3 Gumstix Overo on Tobi";
-        compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3";
        leds {
                compatible = "gpio-leds";
                heartbeat {
diff --git a/arch/arm/boot/dts/omap3-overo-tobi.dts b/arch/arm/boot/dts/omap3-overo-tobi.dts
new file mode 100644
index 000000000000..de5653e1b5ca
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-tobi.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * Tobi expansion board is manufactured by Gumstix Inc.
+ */
+/dts-v1/;
+#include "omap34xx.dtsi"
+#include "omap3-overo-tobi-common.dtsi"
+/ {
+        model = "OMAP35xx Gumstix Overo on Tobi";
+        compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3";
+};
diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi
index a461d2fd1fb0..597099907f8e 100644
--- a/arch/arm/boot/dts/omap3-overo.dtsi
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -9,9 +9,6 @@
 /*
 * The Gumstix Overo must be combined with an expansion board.
 */
-/dts-v1/;
-#include "omap34xx.dtsi"
 / {
        pwmleds {
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 389e987ec281..44ec401ec366 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -57,6 +57,8 @@
                        resets = <&tegra_car 27>;
                        reset-names = "dc";
+                        nvidia,head = <0>;
                        rgb {
                                status = "disabled";
                        };
@@ -72,6 +74,8 @@
                        resets = <&tegra_car 26>;
                        reset-names = "dc";
+                        nvidia,head = <1>;
                        rgb {
                                status = "disabled";
                        };
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 480ecda3416b..48d2a7f4d0c0 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -94,6 +94,8 @@
                        resets = <&tegra_car 27>;
                        reset-names = "dc";
+                        nvidia,head = <0>;
                        rgb {
                                status = "disabled";
                        };
@@ -109,6 +111,8 @@
                        resets = <&tegra_car 26>;
                        reset-names = "dc";
+                        nvidia,head = <1>;
                        rgb {
                                status = "disabled";
                        };
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 9104224124ee..1e156d9d0506 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -28,7 +28,7 @@
        compatible = "nvidia,cardhu", "nvidia,tegra30";
        aliases {
-                rtc0 = "/i2c@7000d000/tps6586x@34";
+                rtc0 = "/i2c@7000d000/tps65911@2d";
                rtc1 = "/rtc@7000e000";
        };
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index ed8e7700b46d..19a84e933f4e 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -170,6 +170,8 @@
                        resets = <&tegra_car 27>;
                        reset-names = "dc";
+                        nvidia,head = <0>;
                        rgb {
                                status = "disabled";
                        };
@@ -185,6 +187,8 @@
                        resets = <&tegra_car 26>;
                        reset-names = "dc";
+                        nvidia,head = <1>;
                        rgb {
                                status = "disabled";
                        };
diff --git a/arch/arm/boot/dts/testcases/tests-interrupts.dtsi b/arch/arm/boot/dts/testcases/tests-interrupts.dtsi
deleted file mode 100644
index c843720bd3e5..000000000000
--- a/arch/arm/boot/dts/testcases/tests-interrupts.dtsi
+++ /dev/null
@@ -1,58 +0,0 @@
-/ {
-        testcase-data {
-                interrupts {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        test_intc0: intc0 {
-                                interrupt-controller;
-                                #interrupt-cells = <1>;
-                        };
-                        test_intc1: intc1 {
-                                interrupt-controller;
-                                #interrupt-cells = <3>;
-                        };
-                        test_intc2: intc2 {
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                        };
-                        test_intmap0: intmap0 {
-                                #interrupt-cells = <1>;
-                                #address-cells = <0>;
-                                interrupt-map = <1 &test_intc0 9>,
-                                                <2 &test_intc1 10 11 12>,
-                                                <3 &test_intc2 13 14>,
-                                                <4 &test_intc2 15 16>;
-                        };
-                        test_intmap1: intmap1 {
-                                #interrupt-cells = <2>;
-                                interrupt-map = <0x5000 1 2 &test_intc0 15>;
-                        };
-                        interrupts0 {
-                                interrupt-parent = <&test_intc0>;
-                                interrupts = <1>, <2>, <3>, <4>;
-                        };
-                        interrupts1 {
-                                interrupt-parent = <&test_intmap0>;
-                                interrupts = <1>, <2>, <3>, <4>;
-                        };
-                        interrupts-extended0 {
-                                reg = <0x5000 0x100>;
-                                interrupts-extended = <&test_intc0 1>,
-                                                      <&test_intc1 2 3 4>,
-                                                      <&test_intc2 5 6>,
-                                                      <&test_intmap0 1>,
-                                                      <&test_intmap0 2>,
-                                                      <&test_intmap0 3>,
-                                                      <&test_intmap1 1 2>;
-                        };
-                };
-        };
-};
diff --git a/arch/arm/boot/dts/testcases/tests-phandle.dtsi b/arch/arm/boot/dts/testcases/tests-phandle.dtsi
deleted file mode 100644
index 0007d3cd7dc2..000000000000
--- a/arch/arm/boot/dts/testcases/tests-phandle.dtsi
+++ /dev/null
@@ -1,39 +0,0 @@
-/ {
-        testcase-data {
-                phandle-tests {
-                        provider0: provider0 {
-                                #phandle-cells = <0>;
-                        };
-                        provider1: provider1 {
-                                #phandle-cells = <1>;
-                        };
-                        provider2: provider2 {
-                                #phandle-cells = <2>;
-                        };
-                        provider3: provider3 {
-                                #phandle-cells = <3>;
-                        };
-                        consumer-a {
-                                phandle-list =  <&provider1 1>,
-                                                <&provider2 2 0>,
-                                                <0>,
-                                                <&provider3 4 4 3>,
-                                                <&provider2 5 100>,
-                                                <&provider0>,
-                                                <&provider1 7>;
-                                phandle-list-names = "first", "second", "third";
-                                phandle-list-bad-phandle = <12345678 0 0>;
-                                phandle-list-bad-args = <&provider2 1 0>,
-                                                        <&provider3 0>;
-                                empty-property;
-                                unterminated-string = [40 41 42 43];
-                        };
-                };
-        };
-};
diff --git a/arch/arm/boot/dts/testcases/tests.dtsi b/arch/arm/boot/dts/testcases/tests.dtsi
deleted file mode 100644
index 3f123ecc9dd7..000000000000
--- a/arch/arm/boot/dts/testcases/tests.dtsi
+++ /dev/null
@@ -1,2 +0,0 @@
-/include/ "tests-phandle.dtsi"
-/include/ "tests-interrupts.dtsi"
diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts
index f43907c40c93..65f657711323 100644
--- a/arch/arm/boot/dts/versatile-pb.dts
+++ b/arch/arm/boot/dts/versatile-pb.dts
@@ -1,4 +1,4 @@
-/include/ "versatile-ab.dts"
+#include <versatile-ab.dts>
 / {
        model = "ARM Versatile PB";
@@ -47,4 +47,4 @@
        };
 };
-/include/ "testcases/tests.dtsi"
+#include <testcases.dtsi>
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index 6309ee52ccfc..f1aeb7d72712 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -154,6 +154,7 @@ CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_MXC=y
 CONFIG_MMC=y
+CONFIG_MMC_UNSAFE_RESUME=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_ESDHC_IMX=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 53e82c2523eb..09e974392fa1 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -39,6 +39,8 @@ CONFIG_SOC_IMX53=y
 CONFIG_SOC_IMX6Q=y
 CONFIG_SOC_IMX6SL=y
 CONFIG_SOC_VF610=y
+CONFIG_PCI=y
+CONFIG_PCI_IMX6=y
 CONFIG_SMP=y
 CONFIG_VMSPLIT_2G=y
 CONFIG_PREEMPT_VOLUNTARY=y
@@ -165,6 +167,7 @@ CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_ANATOP=y
 CONFIG_REGULATOR_DA9052=y
+CONFIG_REGULATOR_GPIO=y
 CONFIG_REGULATOR_MC13783=y
 CONFIG_REGULATOR_MC13892=y
 CONFIG_REGULATOR_PFUZE100=y
@@ -186,6 +189,7 @@ CONFIG_LCD_L4F00242T03=y
 CONFIG_LCD_PLATFORM=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_PWM=y
+CONFIG_BACKLIGHT_GPIO=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_LOGO=y
 CONFIG_SOUND=y
@@ -211,6 +215,7 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_ETH=m
 CONFIG_USB_MASS_STORAGE=m
 CONFIG_MMC=y
+CONFIG_MMC_UNSAFE_RESUME=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_ESDHC_IMX=y
@@ -225,6 +230,7 @@ CONFIG_LEDS_TRIGGER_BACKLIGHT=y
 CONFIG_LEDS_TRIGGER_GPIO=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_DRV_PCF8563=y
 CONFIG_RTC_DRV_MC13XXX=y
 CONFIG_RTC_DRV_MXC=y
 CONFIG_RTC_DRV_SNVS=y
@@ -277,6 +283,7 @@ CONFIG_NLS_ASCII=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_UTF8=y
+CONFIG_DEBUG_FS=y
 CONFIG_MAGIC_SYSRQ=y
 # CONFIG_SCHED_DEBUG is not set
 CONFIG_PROVE_LOCKING=y
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index e9a49fe0284e..8b8b61685a34 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -212,6 +212,7 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *,
 static inline void __flush_icache_all(void)
 {
        __flush_icache_preferred();
+        dsb();
 }
 /*
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
index 03243f7eeddf..85c60adc8b60 100644
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -120,13 +120,16 @@
 /*
 * 2nd stage PTE definitions for LPAE.
 */
-#define L_PTE_S2_MT_UNCACHED     (_AT(pteval_t, 0x5) << 2) /* MemAttr[3:0] */
+#define L_PTE_S2_MT_UNCACHED            (_AT(pteval_t, 0x0) << 2) /* strongly ordered */
-#define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* MemAttr[3:0] */
+#define L_PTE_S2_MT_WRITETHROUGH        (_AT(pteval_t, 0xa) << 2) /* normal inner write-through */
-#define L_PTE_S2_MT_WRITEBACK    (_AT(pteval_t, 0xf) << 2) /* MemAttr[3:0] */
+#define L_PTE_S2_MT_WRITEBACK           (_AT(pteval_t, 0xf) << 2) /* normal inner write-back */
-#define L_PTE_S2_RDONLY          (_AT(pteval_t, 1) << 6)   /* HAP[1]   */
+#define L_PTE_S2_MT_DEV_SHARED          (_AT(pteval_t, 0x1) << 2) /* device */
-#define L_PTE_S2_RDWR            (_AT(pteval_t, 3) << 6)   /* HAP[2:1] */
+#define L_PTE_S2_MT_MASK                (_AT(pteval_t, 0xf) << 2)
-#define L_PMD_S2_RDWR            (_AT(pmdval_t, 3) << 6)   /* HAP[2:1] */
+#define L_PTE_S2_RDONLY                 (_AT(pteval_t, 1) << 6)   /* HAP[1]   */
+#define L_PTE_S2_RDWR                   (_AT(pteval_t, 3) << 6)   /* HAP[2:1] */
+#define L_PMD_S2_RDWR                   (_AT(pmdval_t, 3) << 6)   /* HAP[2:1] */
 /*
 * Hyp-mode PL2 PTE definitions for LPAE.
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h
index ef3c6072aa45..ac4bfae26702 100644
--- a/arch/arm/include/asm/spinlock.h
+++ b/arch/arm/include/asm/spinlock.h
@@ -37,18 +37,9 @@
 static inline void dsb_sev(void)
 {
-#if __LINUX_ARM_ARCH__ >= 7
-        __asm__ __volatile__ (
+        dsb(ishst);
-                "dsb ishst\n"
+        __asm__(SEV);
-                SEV
-        );
-#else
-        __asm__ __volatile__ (
-                "mcr p15, 0, %0, c7, c10, 4\n"
-                SEV
-                : : "r" (0)
-        );
-#endif
 }
 /*
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index b0df9761de6d..1e8b030dbefd 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -731,7 +731,7 @@ static void __init request_standard_resources(const struct machine_desc *mdesc)
        kernel_data.end     = virt_to_phys(_end - 1);
        for_each_memblock(memory, region) {
-                res = memblock_virt_alloc_low(sizeof(*res), 0);
+                res = memblock_virt_alloc(sizeof(*res), 0);
                res->name  = "System RAM";
                res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
                res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index b1aa6a9b3bd1..af4f2dfda40c 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -16,12 +16,7 @@ config ARCH_BCM_MOBILE
        select ARM_ERRATA_754322
        select ARM_ERRATA_764369 if SMP
        select ARM_GIC
-        select CPU_V7
-        select CLKSRC_OF
-        select GENERIC_CLOCKEVENTS
-        select GENERIC_TIME
        select GPIO_BCM_KONA
-        select SPARSE_IRQ
        select TICK_ONESHOT
        select CACHE_L2X0
        select HAVE_ARM_ARCH_TIMER
diff --git a/arch/arm/mach-bcm2835/Kconfig b/arch/arm/mach-bcm2835/Kconfig
index d1f9612f8c15..3a369350a26f 100644
--- a/arch/arm/mach-bcm2835/Kconfig
+++ b/arch/arm/mach-bcm2835/Kconfig
@@ -4,10 +4,6 @@ config ARCH_BCM2835
        select ARM_AMBA
        select ARM_ERRATA_411920
        select ARM_TIMER_SP804
-        select CLKDEV_LOOKUP
-        select CLKSRC_OF
-        select CPU_V6
-        select GENERIC_CLOCKEVENTS
        select PINCTRL
        select PINCTRL_BCM2835
        help
diff --git a/arch/arm/mach-berlin/Kconfig b/arch/arm/mach-berlin/Kconfig
index 7a02d222c378..b0cb0722acd2 100644
--- a/arch/arm/mach-berlin/Kconfig
+++ b/arch/arm/mach-berlin/Kconfig
@@ -1,9 +1,7 @@
 config ARCH_BERLIN
        bool "Marvell Berlin SoCs" if ARCH_MULTI_V7
        select ARM_GIC
-        select GENERIC_CLOCKEVENTS
        select GENERIC_IRQ_CHIP
-        select COMMON_CLK
        select DW_APB_ICTL
        select DW_APB_TIMER_OF
@@ -16,12 +14,10 @@ config MACH_BERLIN_BG2
        select CACHE_L2X0
        select CPU_PJ4B
        select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
 config MACH_BERLIN_BG2CD
        bool "Marvell Armada 1500-mini (BG2CD)"
        select CACHE_L2X0
-        select CPU_V7
        select HAVE_ARM_TWD if SMP
 endmenu
diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig
index dbf0df8bb0ac..dce8decd5d46 100644
--- a/arch/arm/mach-cns3xxx/Kconfig
+++ b/arch/arm/mach-cns3xxx/Kconfig
@@ -1,9 +1,6 @@
 config ARCH_CNS3XXX
        bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6
        select ARM_GIC
-        select CPU_V6K
-        select GENERIC_CLOCKEVENTS
-        select MIGHT_HAVE_CACHE_L2X0
        select MIGHT_HAVE_PCI
        select PCI_DOMAINS if PCI
        help
diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
index 0aded64a9ebc..830b76e70250 100644
--- a/arch/arm/mach-highbank/Kconfig
+++ b/arch/arm/mach-highbank/Kconfig
@@ -5,7 +5,6 @@ config ARCH_HIGHBANK
        select ARCH_HAS_HOLES_MEMORYMODEL
        select ARCH_HAS_OPP
        select ARCH_SUPPORTS_BIG_ENDIAN
-        select ARCH_WANT_OPTIONAL_GPIOLIB
        select ARM_AMBA
        select ARM_ERRATA_764369 if SMP
        select ARM_ERRATA_775420
@@ -14,14 +13,8 @@ config ARCH_HIGHBANK
        select ARM_PSCI
        select ARM_TIMER_SP804
        select CACHE_L2X0
-        select COMMON_CLK
-        select CPU_V7
-        select GENERIC_CLOCKEVENTS
        select HAVE_ARM_SCU
        select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
        select MAILBOX
        select PL320_MBOX
-        select SPARSE_IRQ
-        select USE_OF
        select ZONE_DMA if ARM_LPAE
diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig
index 1abae5f6a418..9d0a87b025e3 100644
--- a/arch/arm/mach-hisi/Kconfig
+++ b/arch/arm/mach-hisi/Kconfig
@@ -3,13 +3,9 @@ config ARCH_HI3xxx
        select ARM_AMBA
        select ARM_GIC
        select ARM_TIMER_SP804
-        select ARCH_WANT_OPTIONAL_GPIOLIB
        select CACHE_L2X0
-        select CLKSRC_OF
-        select GENERIC_CLOCKEVENTS
        select HAVE_ARM_SCU
        select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
        select PINCTRL
        select PINCTRL_SINGLE
        help
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 33567aa5880f..5740296dc429 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,19 +1,15 @@
 config ARCH_MXC
        bool "Freescale i.MX family" if ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7
+        select ARCH_HAS_CPUFREQ
+        select ARCH_HAS_OPP
        select ARCH_REQUIRE_GPIOLIB
        select ARM_CPU_SUSPEND if PM
-        select ARM_PATCH_PHYS_VIRT
        select CLKSRC_MMIO
-        select COMMON_CLK
-        select GENERIC_ALLOCATOR
-        select GENERIC_CLOCKEVENTS
        select GENERIC_IRQ_CHIP
-        select MIGHT_HAVE_CACHE_L2X0 if ARCH_MULTI_V6_V7
-        select MULTI_IRQ_HANDLER
        select PINCTRL
+        select PM_OPP if PM
        select SOC_BUS
-        select SPARSE_IRQ
+        select SRAM
-        select USE_OF
        help
          Support for Freescale MXC/iMX-based family of processors
@@ -121,18 +117,16 @@ config SOC_IMX31
 config SOC_IMX35
        bool
        select ARCH_MXC_IOMUX_V3
-        select CPU_V6K
        select HAVE_EPIT
        select MXC_AVIC
+        select PINCTRL_IMX35
        select SMP_ON_UP if SMP
-        select PINCTRL
 config SOC_IMX5
        bool
        select ARCH_HAS_CPUFREQ
        select ARCH_HAS_OPP
        select ARCH_MXC_IOMUX_V3
-        select CPU_V7
        select MXC_TZIC
 config  SOC_IMX51
@@ -777,65 +771,50 @@ config	SOC_IMX50
 config  SOC_IMX53
        bool "i.MX53 support"
        select HAVE_IMX_SRC
-        select IMX_HAVE_PLATFORM_IMX2_WDT
        select PINCTRL_IMX53
        select SOC_IMX5
        help
          This enables support for Freescale i.MX53 processor.
-config SOC_IMX6Q
+config SOC_IMX6
-        bool "i.MX6 Quad/DualLite support"
+        bool
-        select ARCH_HAS_CPUFREQ
-        select ARCH_HAS_OPP
        select ARM_ERRATA_754322
-        select ARM_ERRATA_764369 if SMP
        select ARM_ERRATA_775420
        select ARM_GIC
-        select CPU_V7
-        select HAVE_ARM_SCU if SMP
-        select HAVE_ARM_TWD if SMP
        select HAVE_IMX_ANATOP
        select HAVE_IMX_GPC
        select HAVE_IMX_MMDC
        select HAVE_IMX_SRC
-        select HAVE_SMP
        select MFD_SYSCON
-        select MIGHT_HAVE_PCI
-        select PCI_DOMAINS if PCI
-        select PINCTRL_IMX6Q
        select PL310_ERRATA_588369 if CACHE_PL310
        select PL310_ERRATA_727915 if CACHE_PL310
        select PL310_ERRATA_769419 if CACHE_PL310
-        select PM_OPP if PM
+config SOC_IMX6Q
+        bool "i.MX6 Quad/DualLite support"
+        select ARM_ERRATA_764369 if SMP
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if SMP
+        select MIGHT_HAVE_PCI
+        select PCI_DOMAINS if PCI
+        select PINCTRL_IMX6Q
+        select SOC_IMX6
        help
          This enables support for Freescale i.MX6 Quad processor.
 config SOC_IMX6SL
        bool "i.MX6 SoloLite support"
-        select ARM_ERRATA_754322
-        select ARM_ERRATA_775420
-        select ARM_GIC
-        select CPU_V7
-        select HAVE_IMX_ANATOP
-        select HAVE_IMX_GPC
-        select HAVE_IMX_MMDC
-        select HAVE_IMX_SRC
-        select MFD_SYSCON
        select PINCTRL_IMX6SL
-        select PL310_ERRATA_588369 if CACHE_PL310
+        select SOC_IMX6
-        select PL310_ERRATA_727915 if CACHE_PL310
-        select PL310_ERRATA_769419 if CACHE_PL310
        help
          This enables support for Freescale i.MX6 SoloLite processor.
 config SOC_VF610
        bool "Vybrid Family VF610 support"
-        select CPU_V7
        select ARM_GIC
-        select CLKSRC_OF
        select PINCTRL_VF610
        select VF_PIT_TIMER
        select PL310_ERRATA_588369 if CACHE_PL310
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index befcaf5d0574..f4ed83032dd0 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o
 obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o
+obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o
 endif
 ifdef CONFIG_SND_IMX_SOC
@@ -101,11 +102,11 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
 obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
 obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
-ifeq ($(CONFIG_PM),y)
+ifeq ($(CONFIG_SUSPEND),y)
-obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
+AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
-# i.MX6SL reuses i.MX6Q code
+obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o
-obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o headsmp.o
 endif
+obj-$(CONFIG_SOC_IMX6) += pm-imx6.o
 # i.MX5 based machines
 obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
index d7ed66091a2a..bdc2e4630a08 100644
--- a/arch/arm/mach-imx/clk-imx21.c
+++ b/arch/arm/mach-imx/clk-imx21.c
@@ -149,7 +149,6 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
        clk_register_clkdev(clk[per1], "per", "imx-gpt.1");
        clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2");
        clk_register_clkdev(clk[per1], "per", "imx-gpt.2");
-        clk_register_clkdev(clk[pwm_ipg_gate], "pwm", "mxc_pwm.0");
        clk_register_clkdev(clk[per2], "per", "imx21-cspi.0");
        clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx21-cspi.0");
        clk_register_clkdev(clk[per2], "per", "imx21-cspi.1");
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index 69858c78f40d..dc36e6c2f1da 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -265,14 +265,6 @@ int __init mx25_clocks_init(void)
        clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0");
        clk_register_clkdev(clk[cspi2_ipg], NULL, "imx35-cspi.1");
        clk_register_clkdev(clk[cspi3_ipg], NULL, "imx35-cspi.2");
-        clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.0");
-        clk_register_clkdev(clk[per10], "per", "mxc_pwm.0");
-        clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.1");
-        clk_register_clkdev(clk[per10], "per", "mxc_pwm.1");
-        clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.2");
-        clk_register_clkdev(clk[per10], "per", "mxc_pwm.2");
-        clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.3");
-        clk_register_clkdev(clk[per10], "per", "mxc_pwm.3");
        clk_register_clkdev(clk[kpp_ipg], NULL, "imx-keypad");
        clk_register_clkdev(clk[tsc_ipg], NULL, "mx25-adc");
        clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.0");
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index c6b40f386786..d2da8908b268 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -231,7 +231,6 @@ int __init mx27_clocks_init(unsigned long fref)
        clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.4");
        clk_register_clkdev(clk[gpt6_ipg_gate], "ipg", "imx-gpt.5");
        clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.5");
-        clk_register_clkdev(clk[pwm_ipg_gate], NULL, "mxc_pwm.0");
        clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.0");
        clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "imx21-mmc.0");
        clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.1");
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 19fca1fdc6fe..568ef0a4de84 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -266,8 +266,6 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
        clk_register_clkdev(clk[IMX5_CLK_ECSPI2_PER_GATE], "per", "imx51-ecspi.1");
        clk_register_clkdev(clk[IMX5_CLK_ECSPI2_IPG_GATE], "ipg", "imx51-ecspi.1");
        clk_register_clkdev(clk[IMX5_CLK_CSPI_IPG_GATE], NULL, "imx35-cspi.2");
-        clk_register_clkdev(clk[IMX5_CLK_PWM1_IPG_GATE], "pwm", "mxc_pwm.0");
-        clk_register_clkdev(clk[IMX5_CLK_PWM2_IPG_GATE], "pwm", "mxc_pwm.1");
        clk_register_clkdev(clk[IMX5_CLK_I2C1_GATE], NULL, "imx21-i2c.0");
        clk_register_clkdev(clk[IMX5_CLK_I2C2_GATE], NULL, "imx21-i2c.1");
        clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.0");
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 4d677f442539..b0e7f9d2c245 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -437,12 +437,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
        clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
-        clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
+        clk_register_clkdev(clk[enet_ref], "enet_ref", NULL);
-        clk_register_clkdev(clk[ahb], "ahb", NULL);
-        clk_register_clkdev(clk[cko1], "cko1", NULL);
-        clk_register_clkdev(clk[arm], NULL, "cpu0");
-        clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL);
-        clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL);
        if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
            cpu_is_imx6dl()) {
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index 4c86f3035205..f7073c0782fb 100644
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
@@ -18,27 +18,43 @@
 #include "clk.h"
 #include "common.h"
-static const char const *step_sels[]            = { "osc", "pll2_pfd2", };
+#define CCSR                    0xc
-static const char const *pll1_sw_sels[]         = { "pll1_sys", "step", };
+#define BM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
-static const char const *ocram_alt_sels[]       = { "pll2_pfd2", "pll3_pfd1", };
+#define CACRR                   0x10
-static const char const *ocram_sels[]           = { "periph", "ocram_alt_sels", };
+#define CDHIPR                  0x48
-static const char const *pre_periph_sels[]      = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", };
+#define BM_CDHIPR_ARM_PODF_BUSY (1 << 16)
-static const char const *periph_clk2_sels[]     = { "pll3_usb_otg", "osc", "osc", "dummy", };
+#define ARM_WAIT_DIV_396M       2
-static const char const *periph2_clk2_sels[]    = { "pll3_usb_otg", "pll2_bus", };
+#define ARM_WAIT_DIV_792M       4
-static const char const *periph_sels[]          = { "pre_periph_sel", "periph_clk2_podf", };
+#define ARM_WAIT_DIV_996M       6
-static const char const *periph2_sels[]         = { "pre_periph2_sel", "periph2_clk2_podf", };
-static const char const *csi_lcdif_sels[]       = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
+#define PLL_ARM                 0x0
-static const char const *usdhc_sels[]           = { "pll2_pfd2", "pll2_pfd0", };
+#define BM_PLL_ARM_DIV_SELECT   (0x7f << 0)
-static const char const *ssi_sels[]             = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", };
+#define BM_PLL_ARM_POWERDOWN    (1 << 12)
-static const char const *perclk_sels[]          = { "ipg", "osc", };
+#define BM_PLL_ARM_ENABLE       (1 << 13)
-static const char const *epdc_pxp_sels[]        = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", };
+#define BM_PLL_ARM_LOCK         (1 << 31)
-static const char const *gpu2d_ovg_sels[]       = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
+#define PLL_ARM_DIV_792M        66
-static const char const *gpu2d_sels[]           = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
-static const char const *lcdif_pix_sels[]       = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
+static const char *step_sels[]          = { "osc", "pll2_pfd2", };
-static const char const *epdc_pix_sels[]        = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", };
+static const char *pll1_sw_sels[]       = { "pll1_sys", "step", };
-static const char const *audio_sels[]           = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
+static const char *ocram_alt_sels[]     = { "pll2_pfd2", "pll3_pfd1", };
-static const char const *ecspi_sels[]           = { "pll3_60m", "osc", };
+static const char *ocram_sels[]         = { "periph", "ocram_alt_sels", };
-static const char const *uart_sels[]            = { "pll3_80m", "osc", };
+static const char *pre_periph_sels[]    = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", };
+static const char *periph_clk2_sels[]   = { "pll3_usb_otg", "osc", "osc", "dummy", };
+static const char *periph2_clk2_sels[]  = { "pll3_usb_otg", "pll2_bus", };
+static const char *periph_sels[]        = { "pre_periph_sel", "periph_clk2_podf", };
+static const char *periph2_sels[]       = { "pre_periph2_sel", "periph2_clk2_podf", };
+static const char *csi_lcdif_sels[]     = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
+static const char *usdhc_sels[]         = { "pll2_pfd2", "pll2_pfd0", };
+static const char *ssi_sels[]           = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", };
+static const char *perclk_sels[]        = { "ipg", "osc", };
+static const char *epdc_pxp_sels[]      = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", };
+static const char *gpu2d_ovg_sels[]     = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
+static const char *gpu2d_sels[]         = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
+static const char *lcdif_pix_sels[]     = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
+static const char *epdc_pix_sels[]      = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", };
+static const char *audio_sels[]         = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
+static const char *ecspi_sels[]         = { "pll3_60m", "osc", };
+static const char *uart_sels[]          = { "pll3_80m", "osc", };
 static struct clk_div_table clk_enet_ref_table[] = {
        { .val = 0, .div = 20, },
@@ -65,6 +81,89 @@ static struct clk_div_table video_div_table[] = {
 static struct clk *clks[IMX6SL_CLK_END];
 static struct clk_onecell_data clk_data;
+static void __iomem *ccm_base;
+static void __iomem *anatop_base;
+static const u32 clks_init_on[] __initconst = {
+        IMX6SL_CLK_IPG, IMX6SL_CLK_ARM, IMX6SL_CLK_MMDC_ROOT,
+};
+/*
+ * ERR005311 CCM: After exit from WAIT mode, unwanted interrupt(s) taken
+ *           during WAIT mode entry process could cause cache memory
+ *           corruption.
+ *
+ * Software workaround:
+ *     To prevent this issue from occurring, software should ensure that the
+ * ARM to IPG clock ratio is less than 12:5 (that is < 2.4x), before
+ * entering WAIT mode.
+ *
+ * This function will set the ARM clk to max value within the 12:5 limit.
+ * As IPG clock is fixed at 66MHz(so ARM freq must not exceed 158.4MHz),
+ * ARM freq are one of below setpoints: 396MHz, 792MHz and 996MHz, since
+ * the clk APIs can NOT be called in idle thread(may cause kernel schedule
+ * as there is sleep function in PLL wait function), so here we just slow
+ * down ARM to below freq according to previous freq:
+ *
+ * run mode      wait mode
+ * 396MHz   ->   132MHz;
+ * 792MHz   ->   158.4MHz;
+ * 996MHz   ->   142.3MHz;
+ */
+static int imx6sl_get_arm_divider_for_wait(void)
+{
+        if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) {
+                return ARM_WAIT_DIV_396M;
+        } else {
+                if ((readl_relaxed(anatop_base + PLL_ARM) &
+                        BM_PLL_ARM_DIV_SELECT) == PLL_ARM_DIV_792M)
+                        return ARM_WAIT_DIV_792M;
+                else
+                        return ARM_WAIT_DIV_996M;
+        }
+}
+static void imx6sl_enable_pll_arm(bool enable)
+{
+        static u32 saved_pll_arm;
+        u32 val;
+        if (enable) {
+                saved_pll_arm = val = readl_relaxed(anatop_base + PLL_ARM);
+                val |= BM_PLL_ARM_ENABLE;
+                val &= ~BM_PLL_ARM_POWERDOWN;
+                writel_relaxed(val, anatop_base + PLL_ARM);
+                while (!(__raw_readl(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK))
+                        ;
+        } else {
+                 writel_relaxed(saved_pll_arm, anatop_base + PLL_ARM);
+        }
+}
+void imx6sl_set_wait_clk(bool enter)
+{
+        static unsigned long saved_arm_div;
+        int arm_div_for_wait = imx6sl_get_arm_divider_for_wait();
+        /*
+         * According to hardware design, arm podf change need
+         * PLL1 clock enabled.
+         */
+        if (arm_div_for_wait == ARM_WAIT_DIV_396M)
+                imx6sl_enable_pll_arm(true);
+        if (enter) {
+                saved_arm_div = readl_relaxed(ccm_base + CACRR);
+                writel_relaxed(arm_div_for_wait, ccm_base + CACRR);
+        } else {
+                writel_relaxed(saved_arm_div, ccm_base + CACRR);
+        }
+        while (__raw_readl(ccm_base + CDHIPR) & BM_CDHIPR_ARM_PODF_BUSY)
+                ;
+        if (arm_div_for_wait == ARM_WAIT_DIV_396M)
+                imx6sl_enable_pll_arm(false);
+}
 static void __init imx6sl_clocks_init(struct device_node *ccm_node)
 {
@@ -72,6 +171,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
        void __iomem *base;
        int irq;
        int i;
+        int ret;
        clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
        clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
@@ -80,6 +180,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
        np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");
        base = of_iomap(np, 0);
        WARN_ON(!base);
+        anatop_base = base;
        /*                                             type               name            parent  base         div_mask */
        clks[IMX6SL_CLK_PLL1_SYS]      = imx_clk_pllv3(IMX_PLLV3_SYS,     "pll1_sys",      "osc", base,        0x7f);
@@ -127,6 +228,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
        np = ccm_node;
        base = of_iomap(np, 0);
        WARN_ON(!base);
+        ccm_base = base;
        /* Reuse imx6q pm code */
        imx6q_pm_set_ccm_base(base);
@@ -258,6 +360,19 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
        clk_register_clkdev(clks[IMX6SL_CLK_GPT], "ipg", "imx-gpt.0");
        clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0");
+        /* Ensure the AHB clk is at 132MHz. */
+        ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000);
+        if (ret)
+                pr_warn("%s: failed to set AHB clock rate %d!\n",
+                        __func__, ret);
+        /*
+         * Make sure those always on clocks are enabled to maintain the correct
+         * usecount and enabling/disabling of parent PLLs.
+         */
+        for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
+                clk_prepare_enable(clks[clks_init_on[i]]);
        if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
                clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]);
                clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c
index ecd66d8e20b6..22dc3ee21fd4 100644
--- a/arch/arm/mach-imx/clk-vf610.c
+++ b/arch/arm/mach-imx/clk-vf610.c
@@ -63,25 +63,25 @@ static void __iomem *anatop_base;
 static void __iomem *ccm_base;
 /* sources for multiplexer clocks, this is used multiple times */
-static const char const *fast_sels[]    = { "firc", "fxosc", };
+static const char *fast_sels[]  = { "firc", "fxosc", };
-static const char const *slow_sels[]    = { "sirc_32k", "sxosc", };
+static const char *slow_sels[]  = { "sirc_32k", "sxosc", };
-static const char const *pll1_sels[]    = { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", };
+static const char *pll1_sels[]  = { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", };
-static const char const *pll2_sels[]    = { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", };
+static const char *pll2_sels[]  = { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", };
-static const char const *sys_sels[]     = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", };
+static const char *sys_sels[]   = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", };
-static const char const *ddr_sels[]     = { "pll2_pfd2", "sys_sel", };
+static const char *ddr_sels[]   = { "pll2_pfd2", "sys_sel", };
-static const char const *rmii_sels[]    = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", };
+static const char *rmii_sels[]  = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", };
-static const char const *enet_ts_sels[] = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", };
+static const char *enet_ts_sels[]       = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", };
-static const char const *esai_sels[]    = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
+static const char *esai_sels[]  = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
-static const char const *sai_sels[]     = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
+static const char *sai_sels[]   = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
-static const char const *nfc_sels[]     = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", };
+static const char *nfc_sels[]   = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", };
-static const char const *qspi_sels[]    = { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", };
+static const char *qspi_sels[]  = { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", };
-static const char const *esdhc_sels[]   = { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", };
+static const char *esdhc_sels[] = { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", };
-static const char const *dcu_sels[]     = { "pll1_pfd2", "pll3_main", };
+static const char *dcu_sels[]   = { "pll1_pfd2", "pll3_main", };
-static const char const *gpu_sels[]     = { "pll2_pfd2", "pll3_pfd2", };
+static const char *gpu_sels[]   = { "pll2_pfd2", "pll3_pfd2", };
-static const char const *vadc_sels[]    = { "pll6_main_div", "pll3_main_div", "pll3_main", };
+static const char *vadc_sels[]  = { "pll6_main_div", "pll3_main_div", "pll3_main", };
 /* FTM counter clock source, not module clock */
-static const char const *ftm_ext_sels[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", };
+static const char *ftm_ext_sels[]       = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", };
-static const char const *ftm_fix_sels[] = { "sxosc", "ipg_bus", };
+static const char *ftm_fix_sels[]       = { "sxosc", "ipg_bus", };
 static struct clk_div_table pll4_main_div_table[] = {
        { .val = 0, .div = 1 },
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 59c3b9b26bb4..b5241ea76706 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
 */
 /*
@@ -116,7 +116,6 @@ void imx_enable_cpu(int cpu, bool enable);
 void imx_set_cpu_jump(int cpu, void *jump_addr);
 u32 imx_get_cpu_arg(int cpu);
 void imx_set_cpu_arg(int cpu, u32 arg);
-void v7_cpu_resume(void);
 #ifdef CONFIG_SMP
 void v7_secondary_startup(void);
 void imx_scu_map_io(void);
@@ -139,18 +138,28 @@ void imx_anatop_init(void);
 void imx_anatop_pre_suspend(void);
 void imx_anatop_post_resume(void);
 int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
-void imx6q_set_chicken_bit(void);
+void imx6q_set_int_mem_clk_lpm(void);
+void imx6sl_set_wait_clk(bool enter);
 void imx_cpu_die(unsigned int cpu);
 int imx_cpu_kill(unsigned int cpu);
-#ifdef CONFIG_PM
+#ifdef CONFIG_SUSPEND
+void v7_cpu_resume(void);
+void imx6_suspend(void __iomem *ocram_vbase);
+#else
+static inline void v7_cpu_resume(void) {}
+static inline void imx6_suspend(void __iomem *ocram_vbase) {}
+#endif
 void imx6q_pm_init(void);
+void imx6dl_pm_init(void);
+void imx6sl_pm_init(void);
 void imx6q_pm_set_ccm_base(void __iomem *base);
+#ifdef CONFIG_PM
 void imx5_pm_init(void);
 #else
-static inline void imx6q_pm_init(void) {}
-static inline void imx6q_pm_set_ccm_base(void __iomem *base) {}
 static inline void imx5_pm_init(void) {}
 #endif
diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c
index 23ddfb693b2d..6bcae0479049 100644
--- a/arch/arm/mach-imx/cpuidle-imx6q.c
+++ b/arch/arm/mach-imx/cpuidle-imx6q.c
@@ -68,8 +68,8 @@ int __init imx6q_cpuidle_init(void)
        /* Need to enable SCU standby for entering WAIT modes */
        imx_scu_standby_enable();
-        /* Set chicken bit to get a reliable WAIT mode support */
+        /* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */
-        imx6q_set_chicken_bit();
+        imx6q_set_int_mem_clk_lpm();
        return cpuidle_register(&imx6q_cpuidle_driver, NULL);
 }
diff --git a/arch/arm/mach-imx/cpuidle-imx6sl.c b/arch/arm/mach-imx/cpuidle-imx6sl.c
new file mode 100644
index 000000000000..d4b6b8171fa9
--- /dev/null
+++ b/arch/arm/mach-imx/cpuidle-imx6sl.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/cpuidle.h>
+#include <linux/module.h>
+#include <asm/cpuidle.h>
+#include <asm/proc-fns.h>
+#include "common.h"
+#include "cpuidle.h"
+static int imx6sl_enter_wait(struct cpuidle_device *dev,
+                            struct cpuidle_driver *drv, int index)
+{
+        imx6q_set_lpm(WAIT_UNCLOCKED);
+        /*
+         * Software workaround for ERR005311, see function
+         * description for details.
+         */
+        imx6sl_set_wait_clk(true);
+        cpu_do_idle();
+        imx6sl_set_wait_clk(false);
+        imx6q_set_lpm(WAIT_CLOCKED);
+        return index;
+}
+static struct cpuidle_driver imx6sl_cpuidle_driver = {
+        .name = "imx6sl_cpuidle",
+        .owner = THIS_MODULE,
+        .states = {
+                /* WFI */
+                ARM_CPUIDLE_WFI_STATE,
+                /* WAIT */
+                {
+                        .exit_latency = 50,
+                        .target_residency = 75,
+                        .flags = CPUIDLE_FLAG_TIME_VALID |
+                                CPUIDLE_FLAG_TIMER_STOP,
+                        .enter = imx6sl_enter_wait,
+                        .name = "WAIT",
+                        .desc = "Clock off",
+                },
+        },
+        .state_count = 2,
+        .safe_state_index = 0,
+};
+int __init imx6sl_cpuidle_init(void)
+{
+        return cpuidle_register(&imx6sl_cpuidle_driver, NULL);
+}
diff --git a/arch/arm/mach-imx/cpuidle.h b/arch/arm/mach-imx/cpuidle.h
index 786f98ecc145..24e33670417c 100644
--- a/arch/arm/mach-imx/cpuidle.h
+++ b/arch/arm/mach-imx/cpuidle.h
@@ -13,6 +13,7 @@
 #ifdef CONFIG_CPU_IDLE
 extern int imx5_cpuidle_init(void);
 extern int imx6q_cpuidle_init(void);
+extern int imx6sl_cpuidle_init(void);
 #else
 static inline int imx5_cpuidle_init(void)
 {
@@ -22,4 +23,8 @@ static inline int imx6q_cpuidle_init(void)
 {
        return 0;
 }
+static inline int imx6sl_cpuidle_init(void)
+{
+        return 0;
+}
 #endif
diff --git a/arch/arm/mach-imx/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h
index 769563fdeaa0..61a114cddc39 100644
--- a/arch/arm/mach-imx/devices-imx25.h
+++ b/arch/arm/mach-imx/devices-imx25.h
@@ -83,7 +83,3 @@ extern const struct imx_spi_imx_data imx25_cspi_data[];
 #define imx25_add_spi_imx0(pdata)       imx25_add_spi_imx(0, pdata)
 #define imx25_add_spi_imx1(pdata)       imx25_add_spi_imx(1, pdata)
 #define imx25_add_spi_imx2(pdata)       imx25_add_spi_imx(2, pdata)
-extern struct imx_mxc_pwm_data imx25_mxc_pwm_data[];
-#define imx25_add_mxc_pwm(id)   \
-        imx_add_mxc_pwm(&imx25_mxc_pwm_data[id])
diff --git a/arch/arm/mach-imx/devices-imx51.h b/arch/arm/mach-imx/devices-imx51.h
index deee5baee88c..26389f35a2b2 100644
--- a/arch/arm/mach-imx/devices-imx51.h
+++ b/arch/arm/mach-imx/devices-imx51.h
@@ -57,10 +57,6 @@ extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[];
 #define imx51_add_imx2_wdt(id)  \
        imx_add_imx2_wdt(&imx51_imx2_wdt_data[id])
-extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[];
-#define imx51_add_mxc_pwm(id)   \
-        imx_add_mxc_pwm(&imx51_mxc_pwm_data[id])
 extern const struct imx_imx_keypad_data imx51_imx_keypad_data;
 #define imx51_add_imx_keypad(pdata)     \
        imx_add_imx_keypad(&imx51_imx_keypad_data, pdata)
diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig
index 68c74fb0373c..2d260a5a307c 100644
--- a/arch/arm/mach-imx/devices/Kconfig
+++ b/arch/arm/mach-imx/devices/Kconfig
@@ -67,9 +67,6 @@ config IMX_HAVE_PLATFORM_MXC_MMC
 config IMX_HAVE_PLATFORM_MXC_NAND
        bool
-config IMX_HAVE_PLATFORM_MXC_PWM
-        bool
 config IMX_HAVE_PLATFORM_MXC_RNGA
        bool
        select ARCH_HAS_RNGA
diff --git a/arch/arm/mach-imx/devices/Makefile b/arch/arm/mach-imx/devices/Makefile
index 67416fb1dc69..1cbc14cd80d1 100644
--- a/arch/arm/mach-imx/devices/Makefile
+++ b/arch/arm/mach-imx/devices/Makefile
@@ -23,7 +23,6 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
diff --git a/arch/arm/mach-imx/devices/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h
index c13b76b9f6b3..61352a80bb59 100644
--- a/arch/arm/mach-imx/devices/devices-common.h
+++ b/arch/arm/mach-imx/devices/devices-common.h
@@ -290,15 +290,6 @@ struct imx_pata_imx_data {
 struct platform_device *__init imx_add_pata_imx(
                const struct imx_pata_imx_data *data);
-struct imx_mxc_pwm_data {
-        int id;
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq;
-};
-struct platform_device *__init imx_add_mxc_pwm(
-                const struct imx_mxc_pwm_data *data);
 /* mxc_rtc */
 struct imx_mxc_rtc_data {
        const char *devid;
diff --git a/arch/arm/mach-imx/devices/platform-mxc_pwm.c b/arch/arm/mach-imx/devices/platform-mxc_pwm.c
deleted file mode 100644
index dcd289777687..000000000000
--- a/arch/arm/mach-imx/devices/platform-mxc_pwm.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "../hardware.h"
-#include "devices-common.h"
-#define imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size)           \
-        {                                                               \
-                .id = _id,                                              \
-                .iobase = soc ## _PWM ## _hwid ## _BASE_ADDR,           \
-                .iosize = _size,                                        \
-                .irq = soc ## _INT_PWM ## _hwid,                        \
-        }
-#define imx_mxc_pwm_data_entry(soc, _id, _hwid, _size)                  \
-        [_id] = imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size)
-#ifdef CONFIG_SOC_IMX21
-const struct imx_mxc_pwm_data imx21_mxc_pwm_data __initconst =
-        imx_mxc_pwm_data_entry_single(MX21, 0, , SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX21 */
-#ifdef CONFIG_SOC_IMX25
-const struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst = {
-#define imx25_mxc_pwm_data_entry(_id, _hwid)                            \
-        imx_mxc_pwm_data_entry(MX25, _id, _hwid, SZ_16K)
-        imx25_mxc_pwm_data_entry(0, 1),
-        imx25_mxc_pwm_data_entry(1, 2),
-        imx25_mxc_pwm_data_entry(2, 3),
-        imx25_mxc_pwm_data_entry(3, 4),
-};
-#endif /* ifdef CONFIG_SOC_IMX25 */
-#ifdef CONFIG_SOC_IMX27
-const struct imx_mxc_pwm_data imx27_mxc_pwm_data __initconst =
-        imx_mxc_pwm_data_entry_single(MX27, 0, , SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX27 */
-#ifdef CONFIG_SOC_IMX51
-const struct imx_mxc_pwm_data imx51_mxc_pwm_data[] __initconst = {
-#define imx51_mxc_pwm_data_entry(_id, _hwid)                            \
-        imx_mxc_pwm_data_entry(MX51, _id, _hwid, SZ_16K)
-        imx51_mxc_pwm_data_entry(0, 1),
-        imx51_mxc_pwm_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
-struct platform_device *__init imx_add_mxc_pwm(
-                const struct imx_mxc_pwm_data *data)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + data->iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-        return imx_add_platform_device("mxc_pwm", data->id,
-                        res, ARRAY_SIZE(res), NULL, 0);
-}
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
index a3b0b04b45c9..abf43bb47eca 100644
--- a/arch/arm/mach-imx/hardware.h
+++ b/arch/arm/mach-imx/hardware.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2007, 2014 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 *
 * This program is free software; you can redistribute it and/or
@@ -20,7 +20,9 @@
 #ifndef __ASM_ARCH_MXC_HARDWARE_H__
 #define __ASM_ARCH_MXC_HARDWARE_H__
+#ifndef __ASSEMBLY__
 #include <asm/io.h>
+#endif
 #include <asm/sizes.h>
 #define addr_in_module(addr, mod) \
diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
index 627f16f0e9d1..de5047c8a6c8 100644
--- a/arch/arm/mach-imx/headsmp.S
+++ b/arch/arm/mach-imx/headsmp.S
@@ -12,12 +12,7 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
-#include <asm/asm-offsets.h>
-#include <asm/hardware/cache-l2x0.h>
-        .section ".text.head", "ax"
-#ifdef CONFIG_SMP
 diag_reg_offset:
        .word   g_diag_reg - .
@@ -34,38 +29,3 @@ ENTRY(v7_secondary_startup)
        set_diag_reg
        b       secondary_startup
 ENDPROC(v7_secondary_startup)
-#endif
-#ifdef CONFIG_ARM_CPU_SUSPEND
-/*
- * The following code must assume it is running from physical address
- * where absolute virtual addresses to the data section have to be
- * turned into relative ones.
- */
-#ifdef CONFIG_CACHE_L2X0
-        .macro  pl310_resume
-        adr     r0, l2x0_saved_regs_offset
-        ldr     r2, [r0]
-        add     r2, r2, r0
-        ldr     r0, [r2, #L2X0_R_PHY_BASE]      @ get physical base of l2x0
-        ldr     r1, [r2, #L2X0_R_AUX_CTRL]      @ get aux_ctrl value
-        str     r1, [r0, #L2X0_AUX_CTRL]        @ restore aux_ctrl
-        mov     r1, #0x1
-        str     r1, [r0, #L2X0_CTRL]            @ re-enable L2
-        .endm
-l2x0_saved_regs_offset:
-        .word   l2x0_saved_regs - .
-#else
-        .macro  pl310_resume
-        .endm
-#endif
-ENTRY(v7_cpu_resume)
-        bl      v7_invalidate_l1
-        pl310_resume
-        b       cpu_resume
-ENDPROC(v7_cpu_resume)
-#endif
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 76e5db4fce35..e60456d85c9d 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -182,16 +182,83 @@ static void __init imx6q_enet_phy_init(void)
 static void __init imx6q_1588_init(void)
 {
+        struct device_node *np;
+        struct clk *ptp_clk;
+        struct clk *enet_ref;
        struct regmap *gpr;
+        u32 clksel;
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec");
+        if (!np) {
+                pr_warn("%s: failed to find fec node\n", __func__);
+                return;
+        }
+        ptp_clk = of_clk_get(np, 2);
+        if (IS_ERR(ptp_clk)) {
+                pr_warn("%s: failed to get ptp clock\n", __func__);
+                goto put_node;
+        }
+        enet_ref = clk_get_sys(NULL, "enet_ref");
+        if (IS_ERR(enet_ref)) {
+                pr_warn("%s: failed to get enet clock\n", __func__);
+                goto put_ptp_clk;
+        }
+        /*
+         * If enet_ref from ANATOP/CCM is the PTP clock source, we need to
+         * set bit IOMUXC_GPR1[21].  Or the PTP clock must be from pad
+         * (external OSC), and we need to clear the bit.
+         */
+        clksel = ptp_clk == enet_ref ? IMX6Q_GPR1_ENET_CLK_SEL_ANATOP :
+                                       IMX6Q_GPR1_ENET_CLK_SEL_PAD;
        gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
        if (!IS_ERR(gpr))
                regmap_update_bits(gpr, IOMUXC_GPR1,
                                IMX6Q_GPR1_ENET_CLK_SEL_MASK,
-                                IMX6Q_GPR1_ENET_CLK_SEL_ANATOP);
+                                clksel);
        else
                pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
+        clk_put(enet_ref);
+put_ptp_clk:
+        clk_put(ptp_clk);
+put_node:
+        of_node_put(np);
+}
+static void __init imx6q_axi_init(void)
+{
+        struct regmap *gpr;
+        unsigned int mask;
+        gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+        if (!IS_ERR(gpr)) {
+                /*
+                 * Enable the cacheable attribute of VPU and IPU
+                 * AXI transactions.
+                 */
+                mask = IMX6Q_GPR4_VPU_WR_CACHE_SEL |
+                        IMX6Q_GPR4_VPU_RD_CACHE_SEL |
+                        IMX6Q_GPR4_VPU_P_WR_CACHE_VAL |
+                        IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK |
+                        IMX6Q_GPR4_IPU_WR_CACHE_CTL |
+                        IMX6Q_GPR4_IPU_RD_CACHE_CTL;
+                regmap_update_bits(gpr, IOMUXC_GPR4, mask, mask);
+                /* Increase IPU read QoS priority */
+                regmap_update_bits(gpr, IOMUXC_GPR6,
+                                IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK |
+                                IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK,
+                                (0xf << 16) | (0x7 << 20));
+                regmap_update_bits(gpr, IOMUXC_GPR7,
+                                IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK |
+                                IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK,
+                                (0xf << 16) | (0x7 << 20));
+        } else {
+                pr_warn("failed to find fsl,imx6q-iomuxc-gpr regmap\n");
+        }
 }
 static void __init imx6q_init_machine(void)
@@ -212,15 +279,18 @@ static void __init imx6q_init_machine(void)
        of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
        imx_anatop_init();
-        imx6q_pm_init();
+        cpu_is_imx6q() ?  imx6q_pm_init() : imx6dl_pm_init();
        imx6q_1588_init();
+        imx6q_axi_init();
 }
 #define OCOTP_CFG3                      0x440
 #define OCOTP_CFG3_SPEED_SHIFT          16
 #define OCOTP_CFG3_SPEED_1P2GHZ         0x3
+#define OCOTP_CFG3_SPEED_996MHZ         0x2
+#define OCOTP_CFG3_SPEED_852MHZ         0x1
-static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
+static void __init imx6q_opp_check_speed_grading(struct device *cpu_dev)
 {
        struct device_node *np;
        void __iomem *base;
@@ -238,11 +308,29 @@ static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
                goto put_node;
        }
+        /*
+         * SPEED_GRADING[1:0] defines the max speed of ARM:
+         * 2b'11: 1200000000Hz;
+         * 2b'10: 996000000Hz;
+         * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
+         * 2b'00: 792000000Hz;
+         * We need to set the max speed of ARM according to fuse map.
+         */
        val = readl_relaxed(base + OCOTP_CFG3);
        val >>= OCOTP_CFG3_SPEED_SHIFT;
-        if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
+        val &= 0x3;
+        if (val != OCOTP_CFG3_SPEED_1P2GHZ)
                if (dev_pm_opp_disable(cpu_dev, 1200000000))
                        pr_warn("failed to disable 1.2 GHz OPP\n");
+        if (val < OCOTP_CFG3_SPEED_996MHZ)
+                if (dev_pm_opp_disable(cpu_dev, 996000000))
+                        pr_warn("failed to disable 996 MHz OPP\n");
+        if (cpu_is_imx6q()) {
+                if (val != OCOTP_CFG3_SPEED_852MHZ)
+                        if (dev_pm_opp_disable(cpu_dev, 852000000))
+                                pr_warn("failed to disable 852 MHz OPP\n");
+        }
 put_node:
        of_node_put(np);
@@ -268,7 +356,7 @@ static void __init imx6q_opp_init(void)
                goto put_node;
        }
-        imx6q_opp_check_1p2ghz(cpu_dev);
+        imx6q_opp_check_speed_grading(cpu_dev);
 put_node:
        of_node_put(np);
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
index 0f4fd4c0ab8e..ad323385115c 100644
--- a/arch/arm/mach-imx/mach-imx6sl.c
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -17,6 +17,7 @@
 #include <asm/mach/map.h>
 #include "common.h"
+#include "cpuidle.h"
 static void __init imx6sl_fec_init(void)
 {
@@ -39,6 +40,8 @@ static void __init imx6sl_init_late(void)
        /* imx6sl reuses imx6q cpufreq driver */
        if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
                platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
+        imx6sl_cpuidle_init();
 }
 static void __init imx6sl_init_machine(void)
@@ -55,8 +58,7 @@ static void __init imx6sl_init_machine(void)
        imx6sl_fec_init();
        imx_anatop_init();
-        /* Reuse imx6q pm code */
+        imx6sl_pm_init();
-        imx6q_pm_init();
 }
 static void __init imx6sl_init_irq(void)
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
new file mode 100644
index 000000000000..16f0d249f6a7
--- /dev/null
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -0,0 +1,552 @@
+/*
+ * Copyright 2011-2014 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/genalloc.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/regmap.h>
+#include <linux/suspend.h>
+#include <asm/cacheflush.h>
+#include <asm/fncpy.h>
+#include <asm/proc-fns.h>
+#include <asm/suspend.h>
+#include <asm/tlb.h>
+#include "common.h"
+#include "hardware.h"
+#define CCR                             0x0
+#define BM_CCR_WB_COUNT                 (0x7 << 16)
+#define BM_CCR_RBC_BYPASS_COUNT         (0x3f << 21)
+#define BM_CCR_RBC_EN                   (0x1 << 27)
+#define CLPCR                           0x54
+#define BP_CLPCR_LPM                    0
+#define BM_CLPCR_LPM                    (0x3 << 0)
+#define BM_CLPCR_BYPASS_PMIC_READY      (0x1 << 2)
+#define BM_CLPCR_ARM_CLK_DIS_ON_LPM     (0x1 << 5)
+#define BM_CLPCR_SBYOS                  (0x1 << 6)
+#define BM_CLPCR_DIS_REF_OSC            (0x1 << 7)
+#define BM_CLPCR_VSTBY                  (0x1 << 8)
+#define BP_CLPCR_STBY_COUNT             9
+#define BM_CLPCR_STBY_COUNT             (0x3 << 9)
+#define BM_CLPCR_COSC_PWRDOWN           (0x1 << 11)
+#define BM_CLPCR_WB_PER_AT_LPM          (0x1 << 16)
+#define BM_CLPCR_WB_CORE_AT_LPM         (0x1 << 17)
+#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS    (0x1 << 19)
+#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS    (0x1 << 21)
+#define BM_CLPCR_MASK_CORE0_WFI         (0x1 << 22)
+#define BM_CLPCR_MASK_CORE1_WFI         (0x1 << 23)
+#define BM_CLPCR_MASK_CORE2_WFI         (0x1 << 24)
+#define BM_CLPCR_MASK_CORE3_WFI         (0x1 << 25)
+#define BM_CLPCR_MASK_SCU_IDLE          (0x1 << 26)
+#define BM_CLPCR_MASK_L2CC_IDLE         (0x1 << 27)
+#define CGPR                            0x64
+#define BM_CGPR_INT_MEM_CLK_LPM         (0x1 << 17)
+#define MX6Q_SUSPEND_OCRAM_SIZE         0x1000
+#define MX6_MAX_MMDC_IO_NUM             33
+static void __iomem *ccm_base;
+static void __iomem *suspend_ocram_base;
+static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase);
+/*
+ * suspend ocram space layout:
+ * ======================== high address ======================
+ *                              .
+ *                              .
+ *                              .
+ *                              ^
+ *                              ^
+ *                              ^
+ *                      imx6_suspend code
+ *              PM_INFO structure(imx6_cpu_pm_info)
+ * ======================== low address =======================
+ */
+struct imx6_pm_base {
+        phys_addr_t pbase;
+        void __iomem *vbase;
+};
+struct imx6_pm_socdata {
+        u32 cpu_type;
+        const char *mmdc_compat;
+        const char *src_compat;
+        const char *iomuxc_compat;
+        const char *gpc_compat;
+        const u32 mmdc_io_num;
+        const u32 *mmdc_io_offset;
+};
+static const u32 imx6q_mmdc_io_offset[] __initconst = {
+        0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */
+        0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */
+        0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */
+        0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */
+        0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */
+        0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */
+        0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */
+        0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */
+        0x74c,                      /* GPR_ADDS */
+};
+static const u32 imx6dl_mmdc_io_offset[] __initconst = {
+        0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */
+        0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */
+        0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */
+        0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */
+        0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */
+        0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */
+        0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */
+        0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */
+        0x74c,                      /* GPR_ADDS */
+};
+static const u32 imx6sl_mmdc_io_offset[] __initconst = {
+        0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */
+        0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */
+        0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */
+        0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */
+        0x330, 0x334, 0x320,        /* SDCKE0, SDCKE1, RESET */
+};
+static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
+        .cpu_type = MXC_CPU_IMX6Q,
+        .mmdc_compat = "fsl,imx6q-mmdc",
+        .src_compat = "fsl,imx6q-src",
+        .iomuxc_compat = "fsl,imx6q-iomuxc",
+        .gpc_compat = "fsl,imx6q-gpc",
+        .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset),
+        .mmdc_io_offset = imx6q_mmdc_io_offset,
+};
+static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
+        .cpu_type = MXC_CPU_IMX6DL,
+        .mmdc_compat = "fsl,imx6q-mmdc",
+        .src_compat = "fsl,imx6q-src",
+        .iomuxc_compat = "fsl,imx6dl-iomuxc",
+        .gpc_compat = "fsl,imx6q-gpc",
+        .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset),
+        .mmdc_io_offset = imx6dl_mmdc_io_offset,
+};
+static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
+        .cpu_type = MXC_CPU_IMX6SL,
+        .mmdc_compat = "fsl,imx6sl-mmdc",
+        .src_compat = "fsl,imx6sl-src",
+        .iomuxc_compat = "fsl,imx6sl-iomuxc",
+        .gpc_compat = "fsl,imx6sl-gpc",
+        .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset),
+        .mmdc_io_offset = imx6sl_mmdc_io_offset,
+};
+/*
+ * This structure is for passing necessary data for low level ocram
+ * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
+ * definition is changed, the offset definition in
+ * arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly,
+ * otherwise, the suspend to ocram function will be broken!
+ */
+struct imx6_cpu_pm_info {
+        phys_addr_t pbase; /* The physical address of pm_info. */
+        phys_addr_t resume_addr; /* The physical resume address for asm code */
+        u32 cpu_type;
+        u32 pm_info_size; /* Size of pm_info. */
+        struct imx6_pm_base mmdc_base;
+        struct imx6_pm_base src_base;
+        struct imx6_pm_base iomuxc_base;
+        struct imx6_pm_base ccm_base;
+        struct imx6_pm_base gpc_base;
+        struct imx6_pm_base l2_base;
+        u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */
+        u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
+} __aligned(8);
+void imx6q_set_int_mem_clk_lpm(void)
+{
+        u32 val = readl_relaxed(ccm_base + CGPR);
+        val |= BM_CGPR_INT_MEM_CLK_LPM;
+        writel_relaxed(val, ccm_base + CGPR);
+}
+static void imx6q_enable_rbc(bool enable)
+{
+        u32 val;
+        /*
+         * need to mask all interrupts in GPC before
+         * operating RBC configurations
+         */
+        imx_gpc_mask_all();
+        /* configure RBC enable bit */
+        val = readl_relaxed(ccm_base + CCR);
+        val &= ~BM_CCR_RBC_EN;
+        val |= enable ? BM_CCR_RBC_EN : 0;
+        writel_relaxed(val, ccm_base + CCR);
+        /* configure RBC count */
+        val = readl_relaxed(ccm_base + CCR);
+        val &= ~BM_CCR_RBC_BYPASS_COUNT;
+        val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
+        writel(val, ccm_base + CCR);
+        /*
+         * need to delay at least 2 cycles of CKIL(32K)
+         * due to hardware design requirement, which is
+         * ~61us, here we use 65us for safe
+         */
+        udelay(65);
+        /* restore GPC interrupt mask settings */
+        imx_gpc_restore_all();
+}
+static void imx6q_enable_wb(bool enable)
+{
+        u32 val;
+        /* configure well bias enable bit */
+        val = readl_relaxed(ccm_base + CLPCR);
+        val &= ~BM_CLPCR_WB_PER_AT_LPM;
+        val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
+        writel_relaxed(val, ccm_base + CLPCR);
+        /* configure well bias count */
+        val = readl_relaxed(ccm_base + CCR);
+        val &= ~BM_CCR_WB_COUNT;
+        val |= enable ? BM_CCR_WB_COUNT : 0;
+        writel_relaxed(val, ccm_base + CCR);
+}
+int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
+{
+        struct irq_desc *iomuxc_irq_desc;
+        u32 val = readl_relaxed(ccm_base + CLPCR);
+        val &= ~BM_CLPCR_LPM;
+        switch (mode) {
+        case WAIT_CLOCKED:
+                break;
+        case WAIT_UNCLOCKED:
+                val |= 0x1 << BP_CLPCR_LPM;
+                val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
+                break;
+        case STOP_POWER_ON:
+                val |= 0x2 << BP_CLPCR_LPM;
+                break;
+        case WAIT_UNCLOCKED_POWER_OFF:
+                val |= 0x1 << BP_CLPCR_LPM;
+                val &= ~BM_CLPCR_VSTBY;
+                val &= ~BM_CLPCR_SBYOS;
+                break;
+        case STOP_POWER_OFF:
+                val |= 0x2 << BP_CLPCR_LPM;
+                val |= 0x3 << BP_CLPCR_STBY_COUNT;
+                val |= BM_CLPCR_VSTBY;
+                val |= BM_CLPCR_SBYOS;
+                if (cpu_is_imx6sl()) {
+                        val |= BM_CLPCR_BYPASS_PMIC_READY;
+                        val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
+                } else {
+                        val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
+                }
+                break;
+        default:
+                return -EINVAL;
+        }
+        /*
+         * ERR007265: CCM: When improper low-power sequence is used,
+         * the SoC enters low power mode before the ARM core executes WFI.
+         *
+         * Software workaround:
+         * 1) Software should trigger IRQ #32 (IOMUX) to be always pending
+         *    by setting IOMUX_GPR1_GINT.
+         * 2) Software should then unmask IRQ #32 in GPC before setting CCM
+         *    Low-Power mode.
+         * 3) Software should mask IRQ #32 right after CCM Low-Power mode
+         *    is set (set bits 0-1 of CCM_CLPCR).
+         */
+        iomuxc_irq_desc = irq_to_desc(32);
+        imx_gpc_irq_unmask(&iomuxc_irq_desc->irq_data);
+        writel_relaxed(val, ccm_base + CLPCR);
+        imx_gpc_irq_mask(&iomuxc_irq_desc->irq_data);
+        return 0;
+}
+static int imx6q_suspend_finish(unsigned long val)
+{
+        if (!imx6_suspend_in_ocram_fn) {
+                cpu_do_idle();
+        } else {
+                /*
+                 * call low level suspend function in ocram,
+                 * as we need to float DDR IO.
+                 */
+                local_flush_tlb_all();
+                imx6_suspend_in_ocram_fn(suspend_ocram_base);
+        }
+        return 0;
+}
+static int imx6q_pm_enter(suspend_state_t state)
+{
+        switch (state) {
+        case PM_SUSPEND_MEM:
+                imx6q_set_lpm(STOP_POWER_OFF);
+                imx6q_enable_wb(true);
+                /*
+                 * For suspend into ocram, asm code already take care of
+                 * RBC setting, so we do NOT need to do that here.
+                 */
+                if (!imx6_suspend_in_ocram_fn)
+                        imx6q_enable_rbc(true);
+                imx_gpc_pre_suspend();
+                imx_anatop_pre_suspend();
+                imx_set_cpu_jump(0, v7_cpu_resume);
+                /* Zzz ... */
+                cpu_suspend(0, imx6q_suspend_finish);
+                if (cpu_is_imx6q() || cpu_is_imx6dl())
+                        imx_smp_prepare();
+                imx_anatop_post_resume();
+                imx_gpc_post_resume();
+                imx6q_enable_rbc(false);
+                imx6q_enable_wb(false);
+                imx6q_set_lpm(WAIT_CLOCKED);
+                break;
+        default:
+                return -EINVAL;
+        }
+        return 0;
+}
+static const struct platform_suspend_ops imx6q_pm_ops = {
+        .enter = imx6q_pm_enter,
+        .valid = suspend_valid_only_mem,
+};
+void __init imx6q_pm_set_ccm_base(void __iomem *base)
+{
+        ccm_base = base;
+}
+static int __init imx6_pm_get_base(struct imx6_pm_base *base,
+                                const char *compat)
+{
+        struct device_node *node;
+        struct resource res;
+        int ret = 0;
+        node = of_find_compatible_node(NULL, NULL, compat);
+        if (!node) {
+                ret = -ENODEV;
+                goto out;
+        }
+        ret = of_address_to_resource(node, 0, &res);
+        if (ret)
+                goto put_node;
+        base->pbase = res.start;
+        base->vbase = ioremap(res.start, resource_size(&res));
+        if (!base->vbase)
+                ret = -ENOMEM;
+put_node:
+        of_node_put(node);
+out:
+        return ret;
+}
+static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
+{
+        phys_addr_t ocram_pbase;
+        struct device_node *node;
+        struct platform_device *pdev;
+        struct imx6_cpu_pm_info *pm_info;
+        struct gen_pool *ocram_pool;
+        unsigned long ocram_base;
+        int i, ret = 0;
+        const u32 *mmdc_offset_array;
+        suspend_set_ops(&imx6q_pm_ops);
+        if (!socdata) {
+                pr_warn("%s: invalid argument!\n", __func__);
+                return -EINVAL;
+        }
+        node = of_find_compatible_node(NULL, NULL, "mmio-sram");
+        if (!node) {
+                pr_warn("%s: failed to find ocram node!\n", __func__);
+                return -ENODEV;
+        }
+        pdev = of_find_device_by_node(node);
+        if (!pdev) {
+                pr_warn("%s: failed to find ocram device!\n", __func__);
+                ret = -ENODEV;
+                goto put_node;
+        }
+        ocram_pool = dev_get_gen_pool(&pdev->dev);
+        if (!ocram_pool) {
+                pr_warn("%s: ocram pool unavailable!\n", __func__);
+                ret = -ENODEV;
+                goto put_node;
+        }
+        ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE);
+        if (!ocram_base) {
+                pr_warn("%s: unable to alloc ocram!\n", __func__);
+                ret = -ENOMEM;
+                goto put_node;
+        }
+        ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base);
+        suspend_ocram_base = __arm_ioremap_exec(ocram_pbase,
+                MX6Q_SUSPEND_OCRAM_SIZE, false);
+        pm_info = suspend_ocram_base;
+        pm_info->pbase = ocram_pbase;
+        pm_info->resume_addr = virt_to_phys(v7_cpu_resume);
+        pm_info->pm_info_size = sizeof(*pm_info);
+        /*
+         * ccm physical address is not used by asm code currently,
+         * so get ccm virtual address directly, as we already have
+         * it from ccm driver.
+         */
+        pm_info->ccm_base.vbase = ccm_base;
+        ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat);
+        if (ret) {
+                pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret);
+                goto put_node;
+        }
+        ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat);
+        if (ret) {
+                pr_warn("%s: failed to get src base %d!\n", __func__, ret);
+                goto src_map_failed;
+        }
+        ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat);
+        if (ret) {
+                pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret);
+                goto iomuxc_map_failed;
+        }
+        ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat);
+        if (ret) {
+                pr_warn("%s: failed to get gpc base %d!\n", __func__, ret);
+                goto gpc_map_failed;
+        }
+        ret = imx6_pm_get_base(&pm_info->l2_base, "arm,pl310-cache");
+        if (ret) {
+                pr_warn("%s: failed to get pl310-cache base %d!\n",
+                        __func__, ret);
+                goto pl310_cache_map_failed;
+        }
+        pm_info->cpu_type = socdata->cpu_type;
+        pm_info->mmdc_io_num = socdata->mmdc_io_num;
+        mmdc_offset_array = socdata->mmdc_io_offset;
+        for (i = 0; i < pm_info->mmdc_io_num; i++) {
+                pm_info->mmdc_io_val[i][0] =
+                        mmdc_offset_array[i];
+                pm_info->mmdc_io_val[i][1] =
+                        readl_relaxed(pm_info->iomuxc_base.vbase +
+                        mmdc_offset_array[i]);
+        }
+        imx6_suspend_in_ocram_fn = fncpy(
+                suspend_ocram_base + sizeof(*pm_info),
+                &imx6_suspend,
+                MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info));
+        goto put_node;
+pl310_cache_map_failed:
+        iounmap(&pm_info->gpc_base.vbase);
+gpc_map_failed:
+        iounmap(&pm_info->iomuxc_base.vbase);
+iomuxc_map_failed:
+        iounmap(&pm_info->src_base.vbase);
+src_map_failed:
+        iounmap(&pm_info->mmdc_base.vbase);
+put_node:
+        of_node_put(node);
+        return ret;
+}
+static void __init imx6_pm_common_init(const struct imx6_pm_socdata
+                                        *socdata)
+{
+        struct regmap *gpr;
+        int ret;
+        WARN_ON(!ccm_base);
+        if (IS_ENABLED(CONFIG_SUSPEND)) {
+                ret = imx6q_suspend_init(socdata);
+                if (ret)
+                        pr_warn("%s: No DDR LPM support with suspend %d!\n",
+                                __func__, ret);
+        }
+        /*
+         * This is for SW workaround step #1 of ERR007265, see comments
+         * in imx6q_set_lpm for details of this errata.
+         * Force IOMUXC irq pending, so that the interrupt to GPC can be
+         * used to deassert dsm_request signal when the signal gets
+         * asserted unexpectedly.
+         */
+        gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+        if (!IS_ERR(gpr))
+                regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
+                                   IMX6Q_GPR1_GINT);
+}
+void __init imx6q_pm_init(void)
+{
+        imx6_pm_common_init(&imx6q_pm_data);
+}
+void __init imx6dl_pm_init(void)
+{
+        imx6_pm_common_init(&imx6dl_pm_data);
+}
+void __init imx6sl_pm_init(void)
+{
+        imx6_pm_common_init(&imx6sl_pm_data);
+}
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
deleted file mode 100644
index 7a9b98589db7..000000000000
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * Copyright 2011-2013 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/mfd/syscon.h>
-#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/regmap.h>
-#include <linux/suspend.h>
-#include <asm/cacheflush.h>
-#include <asm/proc-fns.h>
-#include <asm/suspend.h>
-#include <asm/hardware/cache-l2x0.h>
-#include "common.h"
-#include "hardware.h"
-#define CCR                             0x0
-#define BM_CCR_WB_COUNT                 (0x7 << 16)
-#define BM_CCR_RBC_BYPASS_COUNT         (0x3f << 21)
-#define BM_CCR_RBC_EN                   (0x1 << 27)
-#define CLPCR                           0x54
-#define BP_CLPCR_LPM                    0
-#define BM_CLPCR_LPM                    (0x3 << 0)
-#define BM_CLPCR_BYPASS_PMIC_READY      (0x1 << 2)
-#define BM_CLPCR_ARM_CLK_DIS_ON_LPM     (0x1 << 5)
-#define BM_CLPCR_SBYOS                  (0x1 << 6)
-#define BM_CLPCR_DIS_REF_OSC            (0x1 << 7)
-#define BM_CLPCR_VSTBY                  (0x1 << 8)
-#define BP_CLPCR_STBY_COUNT             9
-#define BM_CLPCR_STBY_COUNT             (0x3 << 9)
-#define BM_CLPCR_COSC_PWRDOWN           (0x1 << 11)
-#define BM_CLPCR_WB_PER_AT_LPM          (0x1 << 16)
-#define BM_CLPCR_WB_CORE_AT_LPM         (0x1 << 17)
-#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS    (0x1 << 19)
-#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS    (0x1 << 21)
-#define BM_CLPCR_MASK_CORE0_WFI         (0x1 << 22)
-#define BM_CLPCR_MASK_CORE1_WFI         (0x1 << 23)
-#define BM_CLPCR_MASK_CORE2_WFI         (0x1 << 24)
-#define BM_CLPCR_MASK_CORE3_WFI         (0x1 << 25)
-#define BM_CLPCR_MASK_SCU_IDLE          (0x1 << 26)
-#define BM_CLPCR_MASK_L2CC_IDLE         (0x1 << 27)
-#define CGPR                            0x64
-#define BM_CGPR_CHICKEN_BIT             (0x1 << 17)
-static void __iomem *ccm_base;
-void imx6q_set_chicken_bit(void)
-{
-        u32 val = readl_relaxed(ccm_base + CGPR);
-        val |= BM_CGPR_CHICKEN_BIT;
-        writel_relaxed(val, ccm_base + CGPR);
-}
-static void imx6q_enable_rbc(bool enable)
-{
-        u32 val;
-        /*
-         * need to mask all interrupts in GPC before
-         * operating RBC configurations
-         */
-        imx_gpc_mask_all();
-        /* configure RBC enable bit */
-        val = readl_relaxed(ccm_base + CCR);
-        val &= ~BM_CCR_RBC_EN;
-        val |= enable ? BM_CCR_RBC_EN : 0;
-        writel_relaxed(val, ccm_base + CCR);
-        /* configure RBC count */
-        val = readl_relaxed(ccm_base + CCR);
-        val &= ~BM_CCR_RBC_BYPASS_COUNT;
-        val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
-        writel(val, ccm_base + CCR);
-        /*
-         * need to delay at least 2 cycles of CKIL(32K)
-         * due to hardware design requirement, which is
-         * ~61us, here we use 65us for safe
-         */
-        udelay(65);
-        /* restore GPC interrupt mask settings */
-        imx_gpc_restore_all();
-}
-static void imx6q_enable_wb(bool enable)
-{
-        u32 val;
-        /* configure well bias enable bit */
-        val = readl_relaxed(ccm_base + CLPCR);
-        val &= ~BM_CLPCR_WB_PER_AT_LPM;
-        val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
-        writel_relaxed(val, ccm_base + CLPCR);
-        /* configure well bias count */
-        val = readl_relaxed(ccm_base + CCR);
-        val &= ~BM_CCR_WB_COUNT;
-        val |= enable ? BM_CCR_WB_COUNT : 0;
-        writel_relaxed(val, ccm_base + CCR);
-}
-int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
-{
-        struct irq_desc *iomuxc_irq_desc;
-        u32 val = readl_relaxed(ccm_base + CLPCR);
-        val &= ~BM_CLPCR_LPM;
-        switch (mode) {
-        case WAIT_CLOCKED:
-                break;
-        case WAIT_UNCLOCKED:
-                val |= 0x1 << BP_CLPCR_LPM;
-                val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
-                break;
-        case STOP_POWER_ON:
-                val |= 0x2 << BP_CLPCR_LPM;
-                break;
-        case WAIT_UNCLOCKED_POWER_OFF:
-                val |= 0x1 << BP_CLPCR_LPM;
-                val &= ~BM_CLPCR_VSTBY;
-                val &= ~BM_CLPCR_SBYOS;
-                break;
-        case STOP_POWER_OFF:
-                val |= 0x2 << BP_CLPCR_LPM;
-                val |= 0x3 << BP_CLPCR_STBY_COUNT;
-                val |= BM_CLPCR_VSTBY;
-                val |= BM_CLPCR_SBYOS;
-                if (cpu_is_imx6sl()) {
-                        val |= BM_CLPCR_BYPASS_PMIC_READY;
-                        val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
-                } else {
-                        val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
-                }
-                break;
-        default:
-                return -EINVAL;
-        }
-        /*
-         * ERR007265: CCM: When improper low-power sequence is used,
-         * the SoC enters low power mode before the ARM core executes WFI.
-         *
-         * Software workaround:
-         * 1) Software should trigger IRQ #32 (IOMUX) to be always pending
-         *    by setting IOMUX_GPR1_GINT.
-         * 2) Software should then unmask IRQ #32 in GPC before setting CCM
-         *    Low-Power mode.
-         * 3) Software should mask IRQ #32 right after CCM Low-Power mode
-         *    is set (set bits 0-1 of CCM_CLPCR).
-         */
-        iomuxc_irq_desc = irq_to_desc(32);
-        imx_gpc_irq_unmask(&iomuxc_irq_desc->irq_data);
-        writel_relaxed(val, ccm_base + CLPCR);
-        imx_gpc_irq_mask(&iomuxc_irq_desc->irq_data);
-        return 0;
-}
-static int imx6q_suspend_finish(unsigned long val)
-{
-        cpu_do_idle();
-        return 0;
-}
-static int imx6q_pm_enter(suspend_state_t state)
-{
-        switch (state) {
-        case PM_SUSPEND_MEM:
-                imx6q_set_lpm(STOP_POWER_OFF);
-                imx6q_enable_wb(true);
-                imx6q_enable_rbc(true);
-                imx_gpc_pre_suspend();
-                imx_anatop_pre_suspend();
-                imx_set_cpu_jump(0, v7_cpu_resume);
-                /* Zzz ... */
-                cpu_suspend(0, imx6q_suspend_finish);
-                if (cpu_is_imx6q() || cpu_is_imx6dl())
-                        imx_smp_prepare();
-                imx_anatop_post_resume();
-                imx_gpc_post_resume();
-                imx6q_enable_rbc(false);
-                imx6q_enable_wb(false);
-                imx6q_set_lpm(WAIT_CLOCKED);
-                break;
-        default:
-                return -EINVAL;
-        }
-        return 0;
-}
-static const struct platform_suspend_ops imx6q_pm_ops = {
-        .enter = imx6q_pm_enter,
-        .valid = suspend_valid_only_mem,
-};
-void __init imx6q_pm_set_ccm_base(void __iomem *base)
-{
-        ccm_base = base;
-}
-void __init imx6q_pm_init(void)
-{
-        struct regmap *gpr;
-        WARN_ON(!ccm_base);
-        /*
-         * This is for SW workaround step #1 of ERR007265, see comments
-         * in imx6q_set_lpm for details of this errata.
-         * Force IOMUXC irq pending, so that the interrupt to GPC can be
-         * used to deassert dsm_request signal when the signal gets
-         * asserted unexpectedly.
-         */
-        gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
-        if (!IS_ERR(gpr))
-                regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
-                                   IMX6Q_GPR1_GINT);
-        suspend_set_ops(&imx6q_pm_ops);
-}
diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S
new file mode 100644
index 000000000000..20048ff05739
--- /dev/null
+++ b/arch/arm/mach-imx/suspend-imx6.S
@@ -0,0 +1,361 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/linkage.h>
+#include <asm/asm-offsets.h>
+#include <asm/hardware/cache-l2x0.h>
+#include "hardware.h"
+/*
+ * ==================== low level suspend ====================
+ *
+ * Better to follow below rules to use ARM registers:
+ * r0: pm_info structure address;
+ * r1 ~ r4: for saving pm_info members;
+ * r5 ~ r10: free registers;
+ * r11: io base address.
+ *
+ * suspend ocram space layout:
+ * ======================== high address ======================
+ *                              .
+ *                              .
+ *                              .
+ *                              ^
+ *                              ^
+ *                              ^
+ *                      imx6_suspend code
+ *              PM_INFO structure(imx6_cpu_pm_info)
+ * ======================== low address =======================
+ */
+/*
+ * Below offsets are based on struct imx6_cpu_pm_info
+ * which defined in arch/arm/mach-imx/pm-imx6q.c, this
+ * structure contains necessary pm info for low level
+ * suspend related code.
+ */
+#define PM_INFO_PBASE_OFFSET                    0x0
+#define PM_INFO_RESUME_ADDR_OFFSET              0x4
+#define PM_INFO_CPU_TYPE_OFFSET                 0x8
+#define PM_INFO_PM_INFO_SIZE_OFFSET             0xC
+#define PM_INFO_MX6Q_MMDC_P_OFFSET              0x10
+#define PM_INFO_MX6Q_MMDC_V_OFFSET              0x14
+#define PM_INFO_MX6Q_SRC_P_OFFSET               0x18
+#define PM_INFO_MX6Q_SRC_V_OFFSET               0x1C
+#define PM_INFO_MX6Q_IOMUXC_P_OFFSET            0x20
+#define PM_INFO_MX6Q_IOMUXC_V_OFFSET            0x24
+#define PM_INFO_MX6Q_CCM_P_OFFSET               0x28
+#define PM_INFO_MX6Q_CCM_V_OFFSET               0x2C
+#define PM_INFO_MX6Q_GPC_P_OFFSET               0x30
+#define PM_INFO_MX6Q_GPC_V_OFFSET               0x34
+#define PM_INFO_MX6Q_L2_P_OFFSET                0x38
+#define PM_INFO_MX6Q_L2_V_OFFSET                0x3C
+#define PM_INFO_MMDC_IO_NUM_OFFSET              0x40
+#define PM_INFO_MMDC_IO_VAL_OFFSET              0x44
+#define MX6Q_SRC_GPR1   0x20
+#define MX6Q_SRC_GPR2   0x24
+#define MX6Q_MMDC_MAPSR 0x404
+#define MX6Q_MMDC_MPDGCTRL0     0x83c
+#define MX6Q_GPC_IMR1   0x08
+#define MX6Q_GPC_IMR2   0x0c
+#define MX6Q_GPC_IMR3   0x10
+#define MX6Q_GPC_IMR4   0x14
+#define MX6Q_CCM_CCR    0x0
+        .align 3
+        .macro  sync_l2_cache
+        /* sync L2 cache to drain L2's buffers to DRAM. */
+#ifdef CONFIG_CACHE_L2X0
+        ldr     r11, [r0, #PM_INFO_MX6Q_L2_V_OFFSET]
+        mov     r6, #0x0
+        str     r6, [r11, #L2X0_CACHE_SYNC]
+1:
+        ldr     r6, [r11, #L2X0_CACHE_SYNC]
+        ands    r6, r6, #0x1
+        bne     1b
+#endif
+        .endm
+        .macro  resume_mmdc
+        /* restore MMDC IO */
+        cmp     r5, #0x0
+        ldreq   r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
+        ldrne   r11, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET]
+        ldr     r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
+        ldr     r7, =PM_INFO_MMDC_IO_VAL_OFFSET
+        add     r7, r7, r0
+1:
+        ldr     r8, [r7], #0x4
+        ldr     r9, [r7], #0x4
+        str     r9, [r11, r8]
+        subs    r6, r6, #0x1
+        bne     1b
+        cmp     r5, #0x0
+        ldreq   r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
+        ldrne   r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
+        cmp     r3, #MXC_CPU_IMX6SL
+        bne     4f
+        /* reset read FIFO, RST_RD_FIFO */
+        ldr     r7, =MX6Q_MMDC_MPDGCTRL0
+        ldr     r6, [r11, r7]
+        orr     r6, r6, #(1 << 31)
+        str     r6, [r11, r7]
+2:
+        ldr     r6, [r11, r7]
+        ands    r6, r6, #(1 << 31)
+        bne     2b
+        /* reset FIFO a second time */
+        ldr     r6, [r11, r7]
+        orr     r6, r6, #(1 << 31)
+        str     r6, [r11, r7]
+3:
+        ldr     r6, [r11, r7]
+        ands    r6, r6, #(1 << 31)
+        bne     3b
+4:
+        /* let DDR out of self-refresh */
+        ldr     r7, [r11, #MX6Q_MMDC_MAPSR]
+        bic     r7, r7, #(1 << 21)
+        str     r7, [r11, #MX6Q_MMDC_MAPSR]
+5:
+        ldr     r7, [r11, #MX6Q_MMDC_MAPSR]
+        ands    r7, r7, #(1 << 25)
+        bne     5b
+        /* enable DDR auto power saving */
+        ldr     r7, [r11, #MX6Q_MMDC_MAPSR]
+        bic     r7, r7, #0x1
+        str     r7, [r11, #MX6Q_MMDC_MAPSR]
+        .endm
+ENTRY(imx6_suspend)
+        ldr     r1, [r0, #PM_INFO_PBASE_OFFSET]
+        ldr     r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
+        ldr     r3, [r0, #PM_INFO_CPU_TYPE_OFFSET]
+        ldr     r4, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET]
+        /*
+         * counting the resume address in iram
+         * to set it in SRC register.
+         */
+        ldr     r6, =imx6_suspend
+        ldr     r7, =resume
+        sub     r7, r7, r6
+        add     r8, r1, r4
+        add     r9, r8, r7
+        /*
+         * make sure TLB contain the addr we want,
+         * as we will access them after MMDC IO floated.
+         */
+        ldr     r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
+        ldr     r6, [r11, #0x0]
+        ldr     r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
+        ldr     r6, [r11, #0x0]
+        /* use r11 to store the IO address */
+        ldr     r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET]
+        /* store physical resume addr and pm_info address. */
+        str     r9, [r11, #MX6Q_SRC_GPR1]
+        str     r1, [r11, #MX6Q_SRC_GPR2]
+        /* need to sync L2 cache before DSM. */
+        sync_l2_cache
+        ldr     r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
+        /*
+         * put DDR explicitly into self-refresh and
+         * disable automatic power savings.
+         */
+        ldr     r7, [r11, #MX6Q_MMDC_MAPSR]
+        orr     r7, r7, #0x1
+        str     r7, [r11, #MX6Q_MMDC_MAPSR]
+        /* make the DDR explicitly enter self-refresh. */
+        ldr     r7, [r11, #MX6Q_MMDC_MAPSR]
+        orr     r7, r7, #(1 << 21)
+        str     r7, [r11, #MX6Q_MMDC_MAPSR]
+poll_dvfs_set:
+        ldr     r7, [r11, #MX6Q_MMDC_MAPSR]
+        ands    r7, r7, #(1 << 25)
+        beq     poll_dvfs_set
+        ldr     r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
+        ldr     r6, =0x0
+        ldr     r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
+        ldr     r8, =PM_INFO_MMDC_IO_VAL_OFFSET
+        add     r8, r8, r0
+        /* i.MX6SL's last 3 IOs need special setting */
+        cmp     r3, #MXC_CPU_IMX6SL
+        subeq   r7, r7, #0x3
+set_mmdc_io_lpm:
+        ldr     r9, [r8], #0x8
+        str     r6, [r11, r9]
+        subs    r7, r7, #0x1
+        bne     set_mmdc_io_lpm
+        cmp     r3, #MXC_CPU_IMX6SL
+        bne     set_mmdc_io_lpm_done
+        ldr     r6, =0x1000
+        ldr     r9, [r8], #0x8
+        str     r6, [r11, r9]
+        ldr     r9, [r8], #0x8
+        str     r6, [r11, r9]
+        ldr     r6, =0x80000
+        ldr     r9, [r8]
+        str     r6, [r11, r9]
+set_mmdc_io_lpm_done:
+        /*
+         * mask all GPC interrupts before
+         * enabling the RBC counters to
+         * avoid the counter starting too
+         * early if an interupt is already
+         * pending.
+         */
+        ldr     r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
+        ldr     r6, [r11, #MX6Q_GPC_IMR1]
+        ldr     r7, [r11, #MX6Q_GPC_IMR2]
+        ldr     r8, [r11, #MX6Q_GPC_IMR3]
+        ldr     r9, [r11, #MX6Q_GPC_IMR4]
+        ldr     r10, =0xffffffff
+        str     r10, [r11, #MX6Q_GPC_IMR1]
+        str     r10, [r11, #MX6Q_GPC_IMR2]
+        str     r10, [r11, #MX6Q_GPC_IMR3]
+        str     r10, [r11, #MX6Q_GPC_IMR4]
+        /*
+         * enable the RBC bypass counter here
+         * to hold off the interrupts. RBC counter
+         * = 32 (1ms), Minimum RBC delay should be
+         * 400us for the analog LDOs to power down.
+         */
+        ldr     r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
+        ldr     r10, [r11, #MX6Q_CCM_CCR]
+        bic     r10, r10, #(0x3f << 21)
+        orr     r10, r10, #(0x20 << 21)
+        str     r10, [r11, #MX6Q_CCM_CCR]
+        /* enable the counter. */
+        ldr     r10, [r11, #MX6Q_CCM_CCR]
+        orr     r10, r10, #(0x1 << 27)
+        str     r10, [r11, #MX6Q_CCM_CCR]
+        /* unmask all the GPC interrupts. */
+        ldr     r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
+        str     r6, [r11, #MX6Q_GPC_IMR1]
+        str     r7, [r11, #MX6Q_GPC_IMR2]
+        str     r8, [r11, #MX6Q_GPC_IMR3]
+        str     r9, [r11, #MX6Q_GPC_IMR4]
+        /*
+         * now delay for a short while (3usec)
+         * ARM is at 1GHz at this point
+         * so a short loop should be enough.
+         * this delay is required to ensure that
+         * the RBC counter can start counting in
+         * case an interrupt is already pending
+         * or in case an interrupt arrives just
+         * as ARM is about to assert DSM_request.
+         */
+        ldr     r6, =2000
+rbc_loop:
+        subs    r6, r6, #0x1
+        bne     rbc_loop
+        /* Zzz, enter stop mode */
+        wfi
+        nop
+        nop
+        nop
+        nop
+        /*
+         * run to here means there is pending
+         * wakeup source, system should auto
+         * resume, we need to restore MMDC IO first
+         */
+        mov     r5, #0x0
+        resume_mmdc
+        /* return to suspend finish */
+        mov     pc, lr
+resume:
+        /* invalidate L1 I-cache first */
+        mov     r6, #0x0
+        mcr     p15, 0, r6, c7, c5, 0
+        mcr     p15, 0, r6, c7, c5, 6
+        /* enable the Icache and branch prediction */
+        mov     r6, #0x1800
+        mcr     p15, 0, r6, c1, c0, 0
+        isb
+        /* get physical resume address from pm_info. */
+        ldr     lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
+        /* clear core0's entry and parameter */
+        ldr     r11, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET]
+        mov     r7, #0x0
+        str     r7, [r11, #MX6Q_SRC_GPR1]
+        str     r7, [r11, #MX6Q_SRC_GPR2]
+        ldr     r3, [r0, #PM_INFO_CPU_TYPE_OFFSET]
+        mov     r5, #0x1
+        resume_mmdc
+        mov     pc, lr
+ENDPROC(imx6_suspend)
+/*
+ * The following code must assume it is running from physical address
+ * where absolute virtual addresses to the data section have to be
+ * turned into relative ones.
+ */
+#ifdef CONFIG_CACHE_L2X0
+        .macro  pl310_resume
+        adr     r0, l2x0_saved_regs_offset
+        ldr     r2, [r0]
+        add     r2, r2, r0
+        ldr     r0, [r2, #L2X0_R_PHY_BASE]      @ get physical base of l2x0
+        ldr     r1, [r2, #L2X0_R_AUX_CTRL]      @ get aux_ctrl value
+        str     r1, [r0, #L2X0_AUX_CTRL]        @ restore aux_ctrl
+        mov     r1, #0x1
+        str     r1, [r0, #L2X0_CTRL]            @ re-enable L2
+        .endm
+l2x0_saved_regs_offset:
+        .word   l2x0_saved_regs - .
+#else
+        .macro  pl310_resume
+        .endm
+#endif
+ENTRY(v7_cpu_resume)
+        bl      v7_invalidate_l1
+        pl310_resume
+        b       cpu_resume
+ENDPROC(v7_cpu_resume)
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index 1a3a5f615770..65222ea0df6d 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -25,6 +25,7 @@
 #include <linux/irq.h>
 #include <linux/clockchips.h>
 #include <linux/clk.h>
+#include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/sched_clock.h>
@@ -116,11 +117,22 @@ static u64 notrace mxc_read_sched_clock(void)
        return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
 }
+static struct delay_timer imx_delay_timer;
+static unsigned long imx_read_current_timer(void)
+{
+        return __raw_readl(sched_clock_reg);
+}
 static int __init mxc_clocksource_init(struct clk *timer_clk)
 {
        unsigned int c = clk_get_rate(timer_clk);
        void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN);
+        imx_delay_timer.read_current_timer = &imx_read_current_timer;
+        imx_delay_timer.freq = c;
+        register_current_timer_delay(&imx_delay_timer);
        sched_clock_reg = reg;
        sched_clock_register(mxc_read_sched_clock, 32, c);
diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig
index 90a708fef541..f50bc936cb84 100644
--- a/arch/arm/mach-keystone/Kconfig
+++ b/arch/arm/mach-keystone/Kconfig
@@ -1,13 +1,9 @@
 config ARCH_KEYSTONE
        bool "Texas Instruments Keystone Devices"
        depends on ARCH_MULTI_V7
-        select CPU_V7
        select ARM_GIC
        select HAVE_ARM_ARCH_TIMER
-        select HAVE_SMP
        select CLKSRC_MMIO
-        select GENERIC_CLOCKEVENTS
-        select ARCH_WANT_OPTIONAL_GPIOLIB
        select ARM_ERRATA_798181 if SMP
        select COMMON_CLK_KEYSTONE
        select ARCH_SUPPORTS_BIG_ENDIAN
diff --git a/arch/arm/mach-moxart/Kconfig b/arch/arm/mach-moxart/Kconfig
index 3795ae28a613..95a6a4b43c37 100644
--- a/arch/arm/mach-moxart/Kconfig
+++ b/arch/arm/mach-moxart/Kconfig
@@ -2,14 +2,9 @@ config ARCH_MOXART
        bool "MOXA ART SoC" if ARCH_MULTI_V4T
        select CPU_FA526
        select ARM_DMA_MEM_BUFFERABLE
-        select USE_OF
-        select CLKSRC_OF
        select CLKSRC_MMIO
-        select HAVE_CLK
-        select COMMON_CLK
        select GENERIC_IRQ_CHIP
        select ARCH_REQUIRE_GPIOLIB
-        select GENERIC_CLOCKEVENTS
        select PHYLIB if NETDEVICES
        help
          Say Y here if you want to run your kernel on hardware with a
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 884b275ab056..f961ae4ec4ee 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -2,15 +2,10 @@ config ARCH_MVEBU
        bool "Marvell SOCs with Device Tree support" if ARCH_MULTI_V7
        select ARCH_SUPPORTS_BIG_ENDIAN
        select CLKSRC_MMIO
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
        select GENERIC_IRQ_CHIP
        select IRQ_DOMAIN
-        select MULTI_IRQ_HANDLER
        select PINCTRL
        select PLAT_ORION
-        select SPARSE_IRQ
-        select CLKDEV_LOOKUP
        select MVEBU_MBUS
        select ZONE_DMA if ARM_LPAE
        select ARCH_REQUIRE_GPIOLIB
@@ -24,7 +19,6 @@ menu "Marvell SOC with device tree"
 config MACH_MVEBU_V7
        bool
        select ARMADA_370_XP_TIMER
-        select HAVE_SMP
        select CACHE_L2X0
 config MACH_ARMADA_370
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 8cde9e05b5d6..84794137b175 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -16,11 +16,7 @@ config ARCH_MXS
        bool "Freescale MXS (i.MX23, i.MX28) support"
        depends on ARCH_MULTI_V5
        select ARCH_REQUIRE_GPIOLIB
-        select CLKDEV_LOOKUP
        select CLKSRC_MMIO
-        select CLKSRC_OF
-        select GENERIC_CLOCKEVENTS
-        select HAVE_CLK_PREPARE
        select PINCTRL
        select SOC_BUS
        select SOC_IMX23
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
index 4d42da49753c..486d301f43fd 100644
--- a/arch/arm/mach-nomadik/Kconfig
+++ b/arch/arm/mach-nomadik/Kconfig
@@ -6,16 +6,11 @@ config ARCH_NOMADIK
        select ARM_VIC
        select CLKSRC_NOMADIK_MTU
        select CLKSRC_NOMADIK_MTU_SCHED_CLOCK
-        select CLKSRC_OF
-        select COMMON_CLK
        select CPU_ARM926T
-        select GENERIC_CLOCKEVENTS
        select MIGHT_HAVE_CACHE_L2X0
        select PINCTRL
        select PINCTRL_NOMADIK
        select PINCTRL_STN8815
-        select SPARSE_IRQ
-        select USE_OF
        help
          Support for the Nomadik platform by ST-Ericsson
diff --git a/arch/arm/mach-nspire/Kconfig b/arch/arm/mach-nspire/Kconfig
index 59d8f0a70919..bc41f26c1a12 100644
--- a/arch/arm/mach-nspire/Kconfig
+++ b/arch/arm/mach-nspire/Kconfig
@@ -3,14 +3,9 @@ config ARCH_NSPIRE
        depends on ARCH_MULTI_V4_V5
        depends on MMU
        select CPU_ARM926T
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
        select GENERIC_IRQ_CHIP
-        select SPARSE_IRQ
        select ARM_AMBA
        select ARM_VIC
        select ARM_TIMER_SP804
-        select USE_OF
-        select CLKSRC_OF
        help
          This enables support for systems using the TI-NSPIRE CPU
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 91449c5cb70f..85089d821982 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -156,6 +156,7 @@ static struct omap_usb_config nokia770_usb_config __initdata = {
        .register_dev   = 1,
        .hmc_mode       = 16,
        .pins[0]        = 6,
+        .extcon         = "tahvo-usb",
 };
 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 40fd5c31b594..e55ae63bb030 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -6,7 +6,6 @@ config ARCH_OMAP2
        depends on ARCH_MULTI_V6
        select ARCH_OMAP2PLUS
        select CPU_V6
-        select MULTI_IRQ_HANDLER
        select SOC_HAS_OMAP2_SDRC
 config ARCH_OMAP3
@@ -15,8 +14,6 @@ config ARCH_OMAP3
        select ARCH_OMAP2PLUS
        select ARCH_HAS_OPP
        select ARM_CPU_SUSPEND if PM
-        select CPU_V7
-        select MULTI_IRQ_HANDLER
        select OMAP_INTERCONNECT
        select PM_OPP if PM
        select PM_RUNTIME if CPU_IDLE
@@ -33,10 +30,8 @@ config ARCH_OMAP4
        select ARM_ERRATA_720789
        select ARM_GIC
        select CACHE_L2X0
-        select CPU_V7
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
        select OMAP_INTERCONNECT
        select PL310_ERRATA_588369
        select PL310_ERRATA_727915
@@ -50,12 +45,11 @@ config SOC_OMAP5
        bool "TI OMAP5"
        depends on ARCH_MULTI_V7
        select ARCH_OMAP2PLUS
+        select ARCH_HAS_OPP
        select ARM_CPU_SUSPEND if PM
        select ARM_GIC
-        select CPU_V7
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
        select HAVE_ARM_ARCH_TIMER
        select ARM_ERRATA_798181 if SMP
@@ -63,16 +57,14 @@ config SOC_AM33XX
        bool "TI AM33XX"
        depends on ARCH_MULTI_V7
        select ARCH_OMAP2PLUS
+        select ARCH_HAS_OPP
        select ARM_CPU_SUSPEND if PM
-        select CPU_V7
-        select MULTI_IRQ_HANDLER
 config SOC_AM43XX
        bool "TI AM43x"
        depends on ARCH_MULTI_V7
-        select CPU_V7
        select ARCH_OMAP2PLUS
-        select MULTI_IRQ_HANDLER
+        select ARCH_HAS_OPP
        select ARM_GIC
        select MACH_OMAP_GENERIC
@@ -80,10 +72,9 @@ config SOC_DRA7XX
        bool "TI DRA7XX"
        depends on ARCH_MULTI_V7
        select ARCH_OMAP2PLUS
+        select ARCH_HAS_OPP
        select ARM_CPU_SUSPEND if PM
        select ARM_GIC
-        select CPU_V7
-        select HAVE_SMP
        select HAVE_ARM_ARCH_TIMER
 config ARCH_OMAP2PLUS
@@ -94,17 +85,13 @@ config ARCH_OMAP2PLUS
        select ARCH_OMAP
        select ARCH_REQUIRE_GPIOLIB
        select CLKSRC_MMIO
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
        select GENERIC_IRQ_CHIP
        select MACH_OMAP_GENERIC
        select OMAP_DM_TIMER
        select PINCTRL
        select PROC_DEVICETREE if PROC_FS
        select SOC_BUS
-        select SPARSE_IRQ
        select TI_PRIV_EDMA
-        select USE_OF
        help
          Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
@@ -262,9 +249,6 @@ config MACH_OMAP_3430SDP
        default y
        select OMAP_PACKAGE_CBB
-config MACH_NOKIA_N800
-       bool
 config MACH_NOKIA_N810
       bool
@@ -275,7 +259,6 @@ config MACH_NOKIA_N8X0
        bool "Nokia N800/N810"
        depends on SOC_OMAP2420
        default y
-        select MACH_NOKIA_N800
        select MACH_NOKIA_N810
        select MACH_NOKIA_N810_WIMAX
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index d24926e6340f..ab43755364f5 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -1339,7 +1339,7 @@ static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
                of_property_read_bool(np, "gpmc,time-para-granularity");
 }
-#ifdef CONFIG_MTD_NAND
+#if IS_ENABLED(CONFIG_MTD_NAND)
 static const char * const nand_xfer_types[] = {
        [NAND_OMAP_PREFETCH_POLLED]             = "prefetch-polled",
@@ -1429,7 +1429,7 @@ static int gpmc_probe_nand_child(struct platform_device *pdev,
 }
 #endif
-#ifdef CONFIG_MTD_ONENAND
+#if IS_ENABLED(CONFIG_MTD_ONENAND)
 static int gpmc_probe_onenand_child(struct platform_device *pdev,
                                 struct device_node *child)
 {
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index d9714113a01a..f14f9ac2dca1 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -179,15 +179,6 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
                .length         = L4_EMU_34XX_SIZE,
                .type           = MT_DEVICE
        },
-#if defined(CONFIG_DEBUG_LL) &&                                                 \
-        (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
-        {
-                .virtual        = ZOOM_UART_VIRT,
-                .pfn            = __phys_to_pfn(ZOOM_UART_BASE),
-                .length         = SZ_1M,
-                .type           = MT_DEVICE
-        },
-#endif
 };
 #endif
diff --git a/arch/arm/mach-picoxcell/Kconfig b/arch/arm/mach-picoxcell/Kconfig
index b1022f4315f7..eca9eb1c5931 100644
--- a/arch/arm/mach-picoxcell/Kconfig
+++ b/arch/arm/mach-picoxcell/Kconfig
@@ -1,12 +1,7 @@
 config ARCH_PICOXCELL
        bool "Picochip PicoXcell" if ARCH_MULTI_V6
        select ARCH_REQUIRE_GPIOLIB
-        select ARM_PATCH_PHYS_VIRT
        select ARM_VIC
-        select CPU_V6K
        select DW_APB_TIMER_OF
-        select GENERIC_CLOCKEVENTS
        select HAVE_TCM
        select NO_IOPORT
-        select SPARSE_IRQ
-        select USE_OF
diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig
index 6988b117fc17..2c726b4f9356 100644
--- a/arch/arm/mach-prima2/Kconfig
+++ b/arch/arm/mach-prima2/Kconfig
@@ -1,9 +1,7 @@
 config ARCH_SIRF
        bool "CSR SiRF" if ARCH_MULTI_V7
        select ARCH_REQUIRE_GPIOLIB
-        select GENERIC_CLOCKEVENTS
        select GENERIC_IRQ_CHIP
-        select MIGHT_HAVE_CACHE_L2X0
        select NO_IOPORT
        select PINCTRL
        select PINCTRL_SIRF
@@ -17,7 +15,6 @@ menu "CSR SiRF atlas6/primaII/Marco/Polo Specific Features"
 config ARCH_ATLAS6
        bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform"
        default y
-        select CPU_V7
        select SIRF_IRQ
        help
          Support for CSR SiRFSoC ARM Cortex A9 Platform
@@ -25,7 +22,6 @@ config ARCH_ATLAS6
 config ARCH_PRIMA2
        bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
        default y
-        select CPU_V7
        select SIRF_IRQ
        select ZONE_DMA
        help
@@ -35,9 +31,7 @@ config ARCH_MARCO
        bool "CSR SiRFSoC MARCO ARM Cortex A9 Platform"
        default y
        select ARM_GIC
-        select CPU_V7
        select HAVE_ARM_SCU if SMP
-        select HAVE_SMP
        select SMP_ON_UP if SMP
        help
          Support for CSR SiRFSoC ARM Cortex A9 Platform
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index f70583fee59f..29997bde277d 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -38,6 +38,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/usb/gpio_vbus.h>
 #include <linux/reboot.h>
+#include <linux/regulator/fixed.h>
 #include <linux/regulator/max1586.h>
 #include <linux/slab.h>
 #include <linux/i2c/pxa-i2c.h>
@@ -714,6 +715,10 @@ static struct gpio global_gpios[] = {
        { GPIO56_MT9M111_nOE, GPIOF_OUT_INIT_LOW, "Camera nOE" },
 };
+static struct regulator_consumer_supply fixed_5v0_consumers[] = {
+        REGULATOR_SUPPLY("power", "pwm-backlight"),
+};
 static void __init mioa701_machine_init(void)
 {
        int rc;
@@ -753,6 +758,10 @@ static void __init mioa701_machine_init(void)
        pxa_set_i2c_info(&i2c_pdata);
        pxa27x_set_i2c_power_info(NULL);
        pxa_set_camera_info(&mioa701_pxacamera_platform_data);
+        regulator_register_always_on(0, "fixed-5.0V", fixed_5v0_consumers,
+                                     ARRAY_SIZE(fixed_5v0_consumers),
+                                     5000000);
 }
 static void mioa701_machine_exit(void)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 133410e178a7..1caee6d548b8 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -7,9 +7,6 @@ config ARCH_ROCKCHIP
        select CACHE_L2X0
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
        select DW_APB_TIMER_OF
        select ARM_GLOBAL_TIMER
        select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 05fa505df585..8a685edf3bbc 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -5,18 +5,13 @@ config ARCH_SHMOBILE_MULTI
        bool "Renesas ARM SoCs" if ARCH_MULTI_V7
        depends on MMU
        select ARCH_SHMOBILE
-        select CPU_V7
-        select GENERIC_CLOCKEVENTS
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
        select ARM_GIC
-        select MIGHT_HAVE_CACHE_L2X0
        select MIGHT_HAVE_PCI
        select NO_IOPORT
        select PINCTRL
        select ARCH_REQUIRE_GPIOLIB
-        select CLKDEV_LOOKUP
 if ARCH_SHMOBILE_MULTI
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index aee77f06f887..b5f8d75d51a0 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -1,17 +1,10 @@
 config ARCH_SOCFPGA
        bool "Altera SOCFPGA family" if ARCH_MULTI_V7
-        select ARCH_WANT_OPTIONAL_GPIOLIB
        select ARM_AMBA
        select ARM_GIC
        select CACHE_L2X0
-        select COMMON_CLK
-        select CPU_V7
        select DW_APB_TIMER_OF
-        select GENERIC_CLOCKEVENTS
        select GPIO_PL061 if GPIOLIB
        select HAVE_ARM_SCU
        select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
        select MFD_SYSCON
-        select SPARSE_IRQ
-        select USE_OF
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index ac1710e64d9a..5c57262b97e9 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -8,8 +8,6 @@ menuconfig PLAT_SPEAR
        select ARCH_REQUIRE_GPIOLIB
        select ARM_AMBA
        select CLKSRC_MMIO
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
 if PLAT_SPEAR
@@ -18,14 +16,10 @@ config ARCH_SPEAR13XX
        depends on ARCH_MULTI_V7 || PLAT_SPEAR_SINGLE
        select ARCH_HAS_CPUFREQ
        select ARM_GIC
-        select CPU_V7
        select GPIO_SPEAR_SPICS
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
-        select MIGHT_HAVE_CACHE_L2X0
        select PINCTRL
-        select USE_OF
        help
          Supports for ARM's SPEAR13XX family
@@ -50,9 +44,7 @@ config ARCH_SPEAR3XX
        depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE
        depends on !ARCH_SPEAR13XX
        select ARM_VIC
-        select CPU_ARM926T
        select PINCTRL
-        select USE_OF
        help
          Supports for ARM's SPEAR3XX family
@@ -83,14 +75,12 @@ config ARCH_SPEAR6XX
        depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE
        depends on !ARCH_SPEAR13XX
        select ARM_VIC
-        select CPU_ARM926T
        help
          Supports for ARM's SPEAR6XX family
 config MACH_SPEAR600
        def_bool y
        depends on ARCH_SPEAR6XX
-        select USE_OF
        help
          Supports ST SPEAr600 boards configured via the device-treesource "arch/arm/mach-spear6xx/Kconfig"
diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig
index d71654bc8d54..d2c13ba1190b 100644
--- a/arch/arm/mach-sti/Kconfig
+++ b/arch/arm/mach-sti/Kconfig
@@ -1,14 +1,10 @@
 menuconfig ARCH_STI
        bool "STMicroelectronics Consumer Electronics SOCs with Device Trees" if ARCH_MULTI_V7
-        select GENERIC_CLOCKEVENTS
-        select CLKDEV_LOOKUP
        select ARM_GIC
        select ARM_GLOBAL_TIMER
        select PINCTRL
        select PINCTRL_ST
        select MFD_SYSCON
-        select MIGHT_HAVE_CACHE_L2X0
-        select HAVE_SMP
        select HAVE_ARM_SCU if SMP
        select ARCH_REQUIRE_GPIOLIB
        select ARM_ERRATA_754322
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index b9d6cad8669b..9de27cfa688f 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -5,14 +5,9 @@ config ARCH_SUNXI
        select ARM_GIC
        select ARM_PSCI
        select CLKSRC_MMIO
-        select CLKSRC_OF
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
        select GENERIC_IRQ_CHIP
-        select HAVE_SMP
        select PINCTRL
        select PINCTRL_SUNXI
        select RESET_CONTROLLER
-        select SPARSE_IRQ
        select SUN4I_TIMER
        select SUN5I_HSTIMER
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index b1232d8be6f5..f61cd5b9f103 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -5,24 +5,16 @@ config ARCH_TEGRA
        select ARCH_SUPPORTS_TRUSTED_FOUNDATIONS
        select ARM_GIC
        select CLKSRC_MMIO
-        select CLKSRC_OF
-        select COMMON_CLK
-        select CPU_V7
-        select GENERIC_CLOCKEVENTS
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
-        select MIGHT_HAVE_CACHE_L2X0
        select MIGHT_HAVE_PCI
        select PINCTRL
        select ARCH_HAS_RESET_CONTROLLER
        select RESET_CONTROLLER
        select SOC_BUS
-        select SPARSE_IRQ
        select USB_ARCH_HAS_EHCI if USB_SUPPORT
        select USB_ULPI if USB_PHY
        select USB_ULPI_VIEWPORT if USB_PHY
-        select USE_OF
        help
          This enables support for NVIDIA Tegra based systems.
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 4ae0286b468d..f55b05a29b55 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -24,6 +24,7 @@
 #include <linux/cpu_pm.h>
 #include <linux/suspend.h>
 #include <linux/err.h>
+#include <linux/slab.h>
 #include <linux/clk/tegra.h>
 #include <asm/smp_plat.h>
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index 303a285d80fd..6191603379e1 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -73,10 +73,20 @@ u32 tegra_uart_config[3] = {
 static void __init tegra_init_cache(void)
 {
 #ifdef CONFIG_CACHE_L2X0
+        static const struct of_device_id pl310_ids[] __initconst = {
+                { .compatible = "arm,pl310-cache",  },
+                {}
+        };
+        struct device_node *np;
        int ret;
        void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
        u32 aux_ctrl, cache_type;
+        np = of_find_matching_node(NULL, pl310_ids);
+        if (!np)
+                return;
        cache_type = readl(p + L2X0_CACHE_TYPE);
        aux_ctrl = (cache_type & 0x700) << (17-8);
        aux_ctrl |= 0x7C400001;
diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig
index 8e23071bd1b3..e3a96d7302e9 100644
--- a/arch/arm/mach-u300/Kconfig
+++ b/arch/arm/mach-u300/Kconfig
@@ -3,20 +3,14 @@ config ARCH_U300
        depends on MMU
        select ARCH_REQUIRE_GPIOLIB
        select ARM_AMBA
-        select ARM_PATCH_PHYS_VIRT
        select ARM_VIC
        select CLKSRC_MMIO
-        select CLKSRC_OF
-        select COMMON_CLK
        select CPU_ARM926T
-        select GENERIC_CLOCKEVENTS
        select HAVE_TCM
        select PINCTRL
        select PINCTRL_COH901
        select PINCTRL_U300
-        select SPARSE_IRQ
        select MFD_SYSCON
-        select USE_OF
        help
          Support for ST-Ericsson U300 series mobile platforms.
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 0034d2cd6973..8052bd52450d 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -11,13 +11,8 @@ config ARCH_U8500
        select ARM_GIC
        select CACHE_L2X0
        select CLKSRC_NOMADIK_MTU
-        select COMMON_CLK
-        select CPU_V7
-        select GENERIC_CLOCKEVENTS
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
-        select MIGHT_HAVE_CACHE_L2X0
        select PINCTRL
        select PINCTRL_ABX500
        select PINCTRL_NOMADIK
@@ -76,7 +71,6 @@ config UX500_AUTO_PLATFORM
 config MACH_UX500_DT
        bool "Generic U8500 support using device tree"
        depends on MACH_MOP500
-        select USE_OF
 endmenu
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 4a70be485ff8..80b4be36f10a 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -5,16 +5,11 @@ config ARCH_VEXPRESS
        select ARM_AMBA
        select ARM_GIC
        select ARM_TIMER_SP804
-        select COMMON_CLK
        select COMMON_CLK_VERSATILE
-        select CPU_V7
-        select GENERIC_CLOCKEVENTS
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP
        select HAVE_PATA_PLATFORM
-        select HAVE_SMP
        select ICST
-        select MIGHT_HAVE_CACHE_L2X0
        select NO_IOPORT
        select PLAT_VERSATILE
        select PLAT_VERSATILE_CLCD
diff --git a/arch/arm/mach-virt/Kconfig b/arch/arm/mach-virt/Kconfig
deleted file mode 100644
index 081d46929436..000000000000
--- a/arch/arm/mach-virt/Kconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-config ARCH_VIRT
-        bool "Dummy Virtual Machine" if ARCH_MULTI_V7
-        select ARCH_WANT_OPTIONAL_GPIOLIB
-        select ARM_GIC
-        select HAVE_ARM_ARCH_TIMER
-        select ARM_PSCI
-        select HAVE_SMP
-        select CPU_V7
-        select SPARSE_IRQ
-        select USE_OF
diff --git a/arch/arm/mach-virt/Makefile b/arch/arm/mach-virt/Makefile
deleted file mode 100644
index 7ddbfa60227f..000000000000
--- a/arch/arm/mach-virt/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-obj-y                                   := virt.o
diff --git a/arch/arm/mach-virt/virt.c b/arch/arm/mach-virt/virt.c
deleted file mode 100644
index b184e57d1854..000000000000
--- a/arch/arm/mach-virt/virt.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Dummy Virtual Machine - does what it says on the tin.
- *
- * Copyright (C) 2012 ARM Ltd
- * Authors: Will Deacon <will.deacon@arm.com>,
- *          Marc Zyngier <marc.zyngier@arm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-#include <linux/smp.h>
-#include <asm/mach/arch.h>
-static void __init virt_init(void)
-{
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-static const char *virt_dt_match[] = {
-        "linux,dummy-virt",
-        "xen,xenvm",
-        NULL
-};
-DT_MACHINE_START(VIRT, "Dummy Virtual Machine")
-        .init_machine   = virt_init,
-        .dt_compat      = virt_dt_match,
-MACHINE_END
diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig
index 927be93b692e..08f56a41cb55 100644
--- a/arch/arm/mach-vt8500/Kconfig
+++ b/arch/arm/mach-vt8500/Kconfig
@@ -3,8 +3,6 @@ config ARCH_VT8500
        select ARCH_HAS_CPUFREQ
        select ARCH_REQUIRE_GPIOLIB
        select CLKDEV_LOOKUP
-        select CLKSRC_OF
-        select GENERIC_CLOCKEVENTS
        select VT8500_TIMER
        select PINCTRL
        help
@@ -21,7 +19,6 @@ config ARCH_WM8750
        bool "WonderMedia WM8750"
        depends on ARCH_MULTI_V6
        select ARCH_VT8500
-        select CPU_V6
        help
          Support for WonderMedia WM8750 System-on-Chip.
@@ -29,6 +26,5 @@ config ARCH_WM8850
        bool "WonderMedia WM8850"
        depends on ARCH_MULTI_V7
        select ARCH_VT8500
-        select CPU_V7
        help
          Support for WonderMedia WM8850 System-on-Chip.
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index 6b04260aa142..105d39b72a25 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -2,16 +2,9 @@ config ARCH_ZYNQ
        bool "Xilinx Zynq ARM Cortex A9 Platform" if ARCH_MULTI_V7
        select ARM_AMBA
        select ARM_GIC
-        select COMMON_CLK
-        select CPU_V7
-        select GENERIC_CLOCKEVENTS
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP
        select ICST
-        select MIGHT_HAVE_CACHE_L2X0
-        select USE_OF
-        select HAVE_SMP
-        select SPARSE_IRQ
        select CADENCE_TTC_TIMER
        select ARM_GLOBAL_TIMER
        help
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 1a77450e728a..11b3914660d2 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1358,7 +1358,7 @@ static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
        *handle = DMA_ERROR_CODE;
        size = PAGE_ALIGN(size);
-        if (gfp & GFP_ATOMIC)
+        if (!(gfp & __GFP_WAIT))
                return __iommu_alloc_atomic(dev, size, handle);
        /*
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index d5a982d15a88..7ea641b7aa7d 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -38,6 +38,7 @@ static inline pmd_t *pmd_off_k(unsigned long virt)
 struct mem_type {
        pteval_t prot_pte;
+        pteval_t prot_pte_s2;
        pmdval_t prot_l1;
        pmdval_t prot_sect;
        unsigned int domain;
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 4f08c133cc25..a623cb3ad012 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -232,12 +232,16 @@ __setup("noalign", noalign_setup);
 #endif /* ifdef CONFIG_CPU_CP15 / else */
 #define PROT_PTE_DEVICE         L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
+#define PROT_PTE_S2_DEVICE      PROT_PTE_DEVICE
 #define PROT_SECT_DEVICE        PMD_TYPE_SECT|PMD_SECT_AP_WRITE
 static struct mem_type mem_types[] = {
        [MT_DEVICE] = {           /* Strongly ordered / ARMv6 shared device */
                .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
                                  L_PTE_SHARED,
+                .prot_pte_s2    = s2_policy(PROT_PTE_S2_DEVICE) |
+                                  s2_policy(L_PTE_S2_MT_DEV_SHARED) |
+                                  L_PTE_SHARED,
                .prot_l1        = PMD_TYPE_TABLE,
                .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_S,
                .domain         = DOMAIN_IO,
@@ -508,7 +512,8 @@ static void __init build_mem_type_table(void)
        cp = &cache_policies[cachepolicy];
        vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
        s2_pgprot = cp->pte_s2;
-        hyp_device_pgprot = s2_device_pgprot = mem_types[MT_DEVICE].prot_pte;
+        hyp_device_pgprot = mem_types[MT_DEVICE].prot_pte;
+        s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2;
        /*
         * ARMv6 and above have extended page tables.
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 45dc29f85d56..32b3558321c4 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -208,7 +208,6 @@ __v6_setup:
        mcr     p15, 0, r0, c7, c14, 0          @ clean+invalidate D cache
        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
        mcr     p15, 0, r0, c7, c15, 0          @ clean+invalidate cache
-        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
 #ifdef CONFIG_MMU
        mcr     p15, 0, r0, c8, c7, 0           @ invalidate I + D TLBs
        mcr     p15, 0, r0, c2, c0, 2           @ TTB control register
@@ -218,6 +217,8 @@ __v6_setup:
        ALT_UP(orr      r8, r8, #TTB_FLAGS_UP)
        mcr     p15, 0, r8, c2, c0, 1           @ load TTB1
 #endif /* CONFIG_MMU */
+        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer and
+                                                @ complete invalidations
        adr     r5, v6_crval
        ldmia   r5, {r5, r6}
 ARM_BE8(orr    r6, r6, #1 << 25)               @ big-endian page tables
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index bd1781979a39..74f6033e76dd 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -351,7 +351,6 @@ __v7_setup:
 4:      mov     r10, #0
        mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate
-        dsb
 #ifdef CONFIG_MMU
        mcr     p15, 0, r10, c8, c7, 0          @ invalidate I + D TLBs
        v7_ttb_setup r10, r4, r8, r5            @ TTBCR, TTBRx setup
@@ -360,6 +359,7 @@ __v7_setup:
        mcr     p15, 0, r5, c10, c2, 0          @ write PRRR
        mcr     p15, 0, r6, c10, c2, 1          @ write NMRR
 #endif
+        dsb                                     @ Complete invalidations
 #ifndef CONFIG_ARM_THUMBEE
        mrc     p15, 0, r0, c0, c1, 0           @ read ID_PFR0 for ThumbEE
        and     r0, r0, #(0xf << 12)            @ ThumbEE enabled field
author	Olof Johansson <olof@lixom.net>	2014-03-09 15:03:18 -0400
committer	Olof Johansson <olof@lixom.net>	2014-03-09 15:03:18 -0400
commit	1760e4f855a2ead08a40deac9abd4fb8cdf3af32 (patch)
tree	8ee1c79f4c46fd225d90e832def3d7f7e3742086 /arch/arm
parent	1e871089f66416ce540d8e362225a0878a5d2c06 (diff)
parent	c8ae7e9bfc8caf679e891c4f0a04f2435b45e2da (diff)