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authorPaul Walmsley <paul@pwsan.com>2010-05-18 20:40:24 -0400
committerPaul Walmsley <paul@pwsan.com>2010-05-20 14:31:06 -0400
commitd74b4949714741f4c58cd1801a6a92737b89a61c (patch)
treea0e838fff3cab45bfba0c319fcdf7f1ea594686f /arch/arm
parent275f675c24a16ea45cc78bc03ff73fd06be8bffb (diff)
OMAP2+ clock: remove DEFAULT_RATE clksel_rate flag
The DEFAULT_RATE clksel_rate flag is essentially useless. It was set on some of the lowest divisors, which, when switching to a much higher-rate parent, could have potentially resulted in rates that exceeded the hardware specifications for downstream clocks in the window between the clk_set_parent(), and a subsequent clk_set_rate(). It seems much safer to just remove the flag and always use the highest available divisor (resulting in the lowest possible rate) after the switch, and this patch does so. Ideally, it would be best to first attempt to switch to a divisor that matches the clock's rate with the previous parent, if at all possible. But that is a project for some other day or some other person. The parent changing code is rarely used. Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-omap2/clkt_clksel.c57
-rw-r--r--arch/arm/mach-omap2/clock2420_data.c46
-rw-r--r--arch/arm/mach-omap2/clock2430_data.c48
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c80
-rw-r--r--arch/arm/mach-omap2/clock_common_data.c6
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h13
6 files changed, 135 insertions, 115 deletions
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index e50812dd03fd..9a23aebeea7e 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -67,38 +67,61 @@ static const struct clksel *_omap2_get_clksel_by_parent(struct clk *clk,
67 return clks; 67 return clks;
68} 68}
69 69
70/* 70/**
71 * Converts encoded control register address into a full address 71 * _omap2_clksel_get_src_field - find the new clksel divisor to use
72 * On error, the return value (parent_div) will be 0. 72 * @src_clk: planned new parent struct clk *
73 * @clk: struct clk * that is being reparented
74 * @field_val: pointer to a u32 to contain the register data for the divisor
75 *
76 * Given an intended new parent struct clk * @src_clk, and the struct
77 * clk * @clk to the clock that is being reparented, find the
78 * appropriate rate divisor for the new clock (returned as the return
79 * value), and the corresponding register bitfield data to program to
80 * reach that divisor (returned in the u32 pointed to by @field_val).
81 * Returns 0 on error, or returns the newly-selected divisor upon
82 * success (in this latter case, the corresponding register bitfield
83 * value is passed back in the variable pointed to by @field_val)
73 */ 84 */
74static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk, 85static u8 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk,
75 u32 *field_val) 86 u32 *field_val)
76{ 87{
77 const struct clksel *clks; 88 const struct clksel *clks;
78 const struct clksel_rate *clkr; 89 const struct clksel_rate *clkr, *max_clkr;
90 u8 max_div = 0;
79 91
80 clks = _omap2_get_clksel_by_parent(clk, src_clk); 92 clks = _omap2_get_clksel_by_parent(clk, src_clk);
81 if (!clks) 93 if (!clks)
82 return 0; 94 return 0;
83 95
96 /*
97 * Find the highest divisor (e.g., the one resulting in the
98 * lowest rate) to use as the default. This should avoid
99 * clock rates that are too high for the device. XXX A better
100 * solution here would be to try to determine if there is a
101 * divisor matching the original clock rate before the parent
102 * switch, and if it cannot be found, to fall back to the
103 * highest divisor.
104 */
84 for (clkr = clks->rates; clkr->div; clkr++) { 105 for (clkr = clks->rates; clkr->div; clkr++) {
85 if (clkr->flags & cpu_mask && clkr->flags & DEFAULT_RATE) 106 if (!(clkr->flags & cpu_mask))
86 break; /* Found the default rate for this platform */ 107 continue;
108
109 if (clkr->div > max_div) {
110 max_div = clkr->div;
111 max_clkr = clkr;
112 }
87 } 113 }
88 114
89 if (!clkr->div) { 115 if (max_div == 0) {
90 printk(KERN_ERR "clock: Could not find default rate for " 116 WARN(1, "clock: Could not find divisor for "
91 "clock %s parent %s\n", clk->name, 117 "clock %s parent %s\n", clk->name,
92 src_clk->parent->name); 118 src_clk->parent->name);
93 return 0; 119 return 0;
94 } 120 }
95 121
96 /* Should never happen. Add a clksel mask to the struct clk. */ 122 *field_val = max_clkr->val;
97 WARN_ON(clk->clksel_mask == 0);
98 123
99 *field_val = clkr->val; 124 return max_div;
100
101 return clkr->div;
102} 125}
103 126
104 127
@@ -177,8 +200,6 @@ unsigned long omap2_clksel_recalc(struct clk *clk)
177 * 200 *
178 * Finds 'best' divider value in an array based on the source and target 201 * Finds 'best' divider value in an array based on the source and target
179 * rates. The divider array must be sorted with smallest divider first. 202 * rates. The divider array must be sorted with smallest divider first.
180 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
181 * they are only settable as part of virtual_prcm set.
182 * 203 *
183 * Returns the rounded clock rate or returns 0xffffffff on error. 204 * Returns the rounded clock rate or returns 0xffffffff on error.
184 */ 205 */
@@ -380,7 +401,7 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
380{ 401{
381 u32 field_val, v, parent_div; 402 u32 field_val, v, parent_div;
382 403
383 if (!clk->clksel) 404 if (!clk->clksel || !clk->clksel_mask)
384 return -EINVAL; 405 return -EINVAL;
385 406
386 parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val); 407 parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val);
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 1381e767ce31..23bc981574f6 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -155,12 +155,12 @@ static struct clk apll54_ck = {
155/* func_54m_ck */ 155/* func_54m_ck */
156 156
157static const struct clksel_rate func_54m_apll54_rates[] = { 157static const struct clksel_rate func_54m_apll54_rates[] = {
158 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 158 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
159 { .div = 0 }, 159 { .div = 0 },
160}; 160};
161 161
162static const struct clksel_rate func_54m_alt_rates[] = { 162static const struct clksel_rate func_54m_alt_rates[] = {
163 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 163 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
164 { .div = 0 }, 164 { .div = 0 },
165}; 165};
166 166
@@ -201,12 +201,12 @@ static struct clk func_96m_ck = {
201/* func_48m_ck */ 201/* func_48m_ck */
202 202
203static const struct clksel_rate func_48m_apll96_rates[] = { 203static const struct clksel_rate func_48m_apll96_rates[] = {
204 { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 204 { .div = 2, .val = 0, .flags = RATE_IN_24XX },
205 { .div = 0 }, 205 { .div = 0 },
206}; 206};
207 207
208static const struct clksel_rate func_48m_alt_rates[] = { 208static const struct clksel_rate func_48m_alt_rates[] = {
209 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 209 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
210 { .div = 0 }, 210 { .div = 0 },
211}; 211};
212 212
@@ -256,22 +256,22 @@ static struct clk wdt1_osc_ck = {
256 * flags fields, which mark them as 2420-only. 256 * flags fields, which mark them as 2420-only.
257 */ 257 */
258static const struct clksel_rate common_clkout_src_core_rates[] = { 258static const struct clksel_rate common_clkout_src_core_rates[] = {
259 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 259 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
260 { .div = 0 } 260 { .div = 0 }
261}; 261};
262 262
263static const struct clksel_rate common_clkout_src_sys_rates[] = { 263static const struct clksel_rate common_clkout_src_sys_rates[] = {
264 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 264 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
265 { .div = 0 } 265 { .div = 0 }
266}; 266};
267 267
268static const struct clksel_rate common_clkout_src_96m_rates[] = { 268static const struct clksel_rate common_clkout_src_96m_rates[] = {
269 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, 269 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
270 { .div = 0 } 270 { .div = 0 }
271}; 271};
272 272
273static const struct clksel_rate common_clkout_src_54m_rates[] = { 273static const struct clksel_rate common_clkout_src_54m_rates[] = {
274 { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE }, 274 { .div = 1, .val = 3, .flags = RATE_IN_24XX },
275 { .div = 0 } 275 { .div = 0 }
276}; 276};
277 277
@@ -300,7 +300,7 @@ static struct clk sys_clkout_src = {
300}; 300};
301 301
302static const struct clksel_rate common_clkout_rates[] = { 302static const struct clksel_rate common_clkout_rates[] = {
303 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 303 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
304 { .div = 2, .val = 1, .flags = RATE_IN_24XX }, 304 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
305 { .div = 4, .val = 2, .flags = RATE_IN_24XX }, 305 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
306 { .div = 8, .val = 3, .flags = RATE_IN_24XX }, 306 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
@@ -384,7 +384,7 @@ static struct clk emul_ck = {
384 * 384 *
385 */ 385 */
386static const struct clksel_rate mpu_core_rates[] = { 386static const struct clksel_rate mpu_core_rates[] = {
387 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 387 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
388 { .div = 2, .val = 2, .flags = RATE_IN_24XX }, 388 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
389 { .div = 4, .val = 4, .flags = RATE_IN_242X }, 389 { .div = 4, .val = 4, .flags = RATE_IN_242X },
390 { .div = 6, .val = 6, .flags = RATE_IN_242X }, 390 { .div = 6, .val = 6, .flags = RATE_IN_242X },
@@ -420,7 +420,7 @@ static struct clk mpu_ck = { /* Control cpu */
420 * routed into a synchronizer and out of clocks abc. 420 * routed into a synchronizer and out of clocks abc.
421 */ 421 */
422static const struct clksel_rate dsp_fck_core_rates[] = { 422static const struct clksel_rate dsp_fck_core_rates[] = {
423 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 423 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
424 { .div = 2, .val = 2, .flags = RATE_IN_24XX }, 424 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
425 { .div = 3, .val = 3, .flags = RATE_IN_24XX }, 425 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
426 { .div = 4, .val = 4, .flags = RATE_IN_24XX }, 426 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
@@ -450,7 +450,7 @@ static struct clk dsp_fck = {
450 450
451/* DSP interface clock */ 451/* DSP interface clock */
452static const struct clksel_rate dsp_irate_ick_rates[] = { 452static const struct clksel_rate dsp_irate_ick_rates[] = {
453 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 453 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
454 { .div = 2, .val = 2, .flags = RATE_IN_24XX }, 454 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
455 { .div = 0 }, 455 { .div = 0 },
456}; 456};
@@ -532,7 +532,7 @@ static struct clk iva1_mpu_int_ifck = {
532static const struct clksel_rate core_l3_core_rates[] = { 532static const struct clksel_rate core_l3_core_rates[] = {
533 { .div = 1, .val = 1, .flags = RATE_IN_24XX }, 533 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
534 { .div = 2, .val = 2, .flags = RATE_IN_242X }, 534 { .div = 2, .val = 2, .flags = RATE_IN_242X },
535 { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE }, 535 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
536 { .div = 6, .val = 6, .flags = RATE_IN_24XX }, 536 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
537 { .div = 8, .val = 8, .flags = RATE_IN_242X }, 537 { .div = 8, .val = 8, .flags = RATE_IN_242X },
538 { .div = 12, .val = 12, .flags = RATE_IN_242X }, 538 { .div = 12, .val = 12, .flags = RATE_IN_242X },
@@ -559,7 +559,7 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
559/* usb_l4_ick */ 559/* usb_l4_ick */
560static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { 560static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
561 { .div = 1, .val = 1, .flags = RATE_IN_24XX }, 561 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
562 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, 562 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
563 { .div = 4, .val = 4, .flags = RATE_IN_24XX }, 563 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
564 { .div = 0 } 564 { .div = 0 }
565}; 565};
@@ -591,7 +591,7 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */
591 * this domain. 591 * this domain.
592 */ 592 */
593static const struct clksel_rate l4_core_l3_rates[] = { 593static const struct clksel_rate l4_core_l3_rates[] = {
594 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 594 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
595 { .div = 2, .val = 2, .flags = RATE_IN_24XX }, 595 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
596 { .div = 0 } 596 { .div = 0 }
597}; 597};
@@ -622,7 +622,7 @@ static struct clk l4_ck = { /* used both as an ick and fck */
622 */ 622 */
623static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { 623static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
624 { .div = 1, .val = 1, .flags = RATE_IN_24XX }, 624 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
625 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, 625 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
626 { .div = 3, .val = 3, .flags = RATE_IN_24XX }, 626 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
627 { .div = 4, .val = 4, .flags = RATE_IN_24XX }, 627 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
628 { .div = 6, .val = 6, .flags = RATE_IN_242X }, 628 { .div = 6, .val = 6, .flags = RATE_IN_242X },
@@ -730,7 +730,7 @@ static struct clk gfx_ick = {
730/* XXX Add RATE_NOT_VALIDATED */ 730/* XXX Add RATE_NOT_VALIDATED */
731 731
732static const struct clksel_rate dss1_fck_sys_rates[] = { 732static const struct clksel_rate dss1_fck_sys_rates[] = {
733 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 733 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
734 { .div = 0 } 734 { .div = 0 }
735}; 735};
736 736
@@ -744,7 +744,7 @@ static const struct clksel_rate dss1_fck_core_rates[] = {
744 { .div = 8, .val = 8, .flags = RATE_IN_24XX }, 744 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
745 { .div = 9, .val = 9, .flags = RATE_IN_24XX }, 745 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
746 { .div = 12, .val = 12, .flags = RATE_IN_24XX }, 746 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
747 { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE }, 747 { .div = 16, .val = 16, .flags = RATE_IN_24XX },
748 { .div = 0 } 748 { .div = 0 }
749}; 749};
750 750
@@ -779,12 +779,12 @@ static struct clk dss1_fck = {
779}; 779};
780 780
781static const struct clksel_rate dss2_fck_sys_rates[] = { 781static const struct clksel_rate dss2_fck_sys_rates[] = {
782 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 782 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
783 { .div = 0 } 783 { .div = 0 }
784}; 784};
785 785
786static const struct clksel_rate dss2_fck_48m_rates[] = { 786static const struct clksel_rate dss2_fck_48m_rates[] = {
787 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 787 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
788 { .div = 0 } 788 { .div = 0 }
789}; 789};
790 790
@@ -825,7 +825,7 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */
825 * functional clock parents. 825 * functional clock parents.
826 */ 826 */
827static const struct clksel_rate gpt_alt_rates[] = { 827static const struct clksel_rate gpt_alt_rates[] = {
828 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, 828 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
829 { .div = 0 } 829 { .div = 0 }
830}; 830};
831 831
@@ -1588,7 +1588,7 @@ static struct clk vlynq_ick = {
1588}; 1588};
1589 1589
1590static const struct clksel_rate vlynq_fck_96m_rates[] = { 1590static const struct clksel_rate vlynq_fck_96m_rates[] = {
1591 { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE }, 1591 { .div = 1, .val = 0, .flags = RATE_IN_242X },
1592 { .div = 0 } 1592 { .div = 0 }
1593}; 1593};
1594 1594
@@ -1601,7 +1601,7 @@ static const struct clksel_rate vlynq_fck_core_rates[] = {
1601 { .div = 8, .val = 8, .flags = RATE_IN_242X }, 1601 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1602 { .div = 9, .val = 9, .flags = RATE_IN_242X }, 1602 { .div = 9, .val = 9, .flags = RATE_IN_242X },
1603 { .div = 12, .val = 12, .flags = RATE_IN_242X }, 1603 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1604 { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE }, 1604 { .div = 16, .val = 16, .flags = RATE_IN_242X },
1605 { .div = 18, .val = 18, .flags = RATE_IN_242X }, 1605 { .div = 18, .val = 18, .flags = RATE_IN_242X },
1606 { .div = 0 } 1606 { .div = 0 }
1607}; 1607};
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 1aac22709dfe..2df50d97deb2 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -155,12 +155,12 @@ static struct clk apll54_ck = {
155/* func_54m_ck */ 155/* func_54m_ck */
156 156
157static const struct clksel_rate func_54m_apll54_rates[] = { 157static const struct clksel_rate func_54m_apll54_rates[] = {
158 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 158 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
159 { .div = 0 }, 159 { .div = 0 },
160}; 160};
161 161
162static const struct clksel_rate func_54m_alt_rates[] = { 162static const struct clksel_rate func_54m_alt_rates[] = {
163 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 163 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
164 { .div = 0 }, 164 { .div = 0 },
165}; 165};
166 166
@@ -192,12 +192,12 @@ static struct clk core_ck = {
192 192
193/* func_96m_ck */ 193/* func_96m_ck */
194static const struct clksel_rate func_96m_apll96_rates[] = { 194static const struct clksel_rate func_96m_apll96_rates[] = {
195 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 195 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
196 { .div = 0 }, 196 { .div = 0 },
197}; 197};
198 198
199static const struct clksel_rate func_96m_alt_rates[] = { 199static const struct clksel_rate func_96m_alt_rates[] = {
200 { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE }, 200 { .div = 1, .val = 1, .flags = RATE_IN_243X },
201 { .div = 0 }, 201 { .div = 0 },
202}; 202};
203 203
@@ -222,12 +222,12 @@ static struct clk func_96m_ck = {
222/* func_48m_ck */ 222/* func_48m_ck */
223 223
224static const struct clksel_rate func_48m_apll96_rates[] = { 224static const struct clksel_rate func_48m_apll96_rates[] = {
225 { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 225 { .div = 2, .val = 0, .flags = RATE_IN_24XX },
226 { .div = 0 }, 226 { .div = 0 },
227}; 227};
228 228
229static const struct clksel_rate func_48m_alt_rates[] = { 229static const struct clksel_rate func_48m_alt_rates[] = {
230 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 230 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
231 { .div = 0 }, 231 { .div = 0 },
232}; 232};
233 233
@@ -277,22 +277,22 @@ static struct clk wdt1_osc_ck = {
277 * flags fields, which mark them as 2420-only. 277 * flags fields, which mark them as 2420-only.
278 */ 278 */
279static const struct clksel_rate common_clkout_src_core_rates[] = { 279static const struct clksel_rate common_clkout_src_core_rates[] = {
280 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 280 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
281 { .div = 0 } 281 { .div = 0 }
282}; 282};
283 283
284static const struct clksel_rate common_clkout_src_sys_rates[] = { 284static const struct clksel_rate common_clkout_src_sys_rates[] = {
285 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 285 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
286 { .div = 0 } 286 { .div = 0 }
287}; 287};
288 288
289static const struct clksel_rate common_clkout_src_96m_rates[] = { 289static const struct clksel_rate common_clkout_src_96m_rates[] = {
290 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, 290 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
291 { .div = 0 } 291 { .div = 0 }
292}; 292};
293 293
294static const struct clksel_rate common_clkout_src_54m_rates[] = { 294static const struct clksel_rate common_clkout_src_54m_rates[] = {
295 { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE }, 295 { .div = 1, .val = 3, .flags = RATE_IN_24XX },
296 { .div = 0 } 296 { .div = 0 }
297}; 297};
298 298
@@ -321,7 +321,7 @@ static struct clk sys_clkout_src = {
321}; 321};
322 322
323static const struct clksel_rate common_clkout_rates[] = { 323static const struct clksel_rate common_clkout_rates[] = {
324 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 324 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
325 { .div = 2, .val = 1, .flags = RATE_IN_24XX }, 325 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
326 { .div = 4, .val = 2, .flags = RATE_IN_24XX }, 326 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
327 { .div = 8, .val = 3, .flags = RATE_IN_24XX }, 327 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
@@ -369,7 +369,7 @@ static struct clk emul_ck = {
369 * 369 *
370 */ 370 */
371static const struct clksel_rate mpu_core_rates[] = { 371static const struct clksel_rate mpu_core_rates[] = {
372 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 372 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
373 { .div = 2, .val = 2, .flags = RATE_IN_24XX }, 373 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
374 { .div = 0 }, 374 { .div = 0 },
375}; 375};
@@ -402,7 +402,7 @@ static struct clk mpu_ck = { /* Control cpu */
402 * routed into a synchronizer and out of clocks abc. 402 * routed into a synchronizer and out of clocks abc.
403 */ 403 */
404static const struct clksel_rate dsp_fck_core_rates[] = { 404static const struct clksel_rate dsp_fck_core_rates[] = {
405 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 405 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
406 { .div = 2, .val = 2, .flags = RATE_IN_24XX }, 406 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
407 { .div = 3, .val = 3, .flags = RATE_IN_24XX }, 407 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
408 { .div = 4, .val = 4, .flags = RATE_IN_24XX }, 408 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
@@ -429,7 +429,7 @@ static struct clk dsp_fck = {
429 429
430/* DSP interface clock */ 430/* DSP interface clock */
431static const struct clksel_rate dsp_irate_ick_rates[] = { 431static const struct clksel_rate dsp_irate_ick_rates[] = {
432 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 432 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
433 { .div = 2, .val = 2, .flags = RATE_IN_24XX }, 433 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
434 { .div = 3, .val = 3, .flags = RATE_IN_243X }, 434 { .div = 3, .val = 3, .flags = RATE_IN_243X },
435 { .div = 0 }, 435 { .div = 0 },
@@ -481,7 +481,7 @@ static struct clk iva2_1_ick = {
481 */ 481 */
482static const struct clksel_rate core_l3_core_rates[] = { 482static const struct clksel_rate core_l3_core_rates[] = {
483 { .div = 1, .val = 1, .flags = RATE_IN_24XX }, 483 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
484 { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE }, 484 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
485 { .div = 6, .val = 6, .flags = RATE_IN_24XX }, 485 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
486 { .div = 0 } 486 { .div = 0 }
487}; 487};
@@ -505,7 +505,7 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
505/* usb_l4_ick */ 505/* usb_l4_ick */
506static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { 506static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
507 { .div = 1, .val = 1, .flags = RATE_IN_24XX }, 507 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
508 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, 508 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
509 { .div = 4, .val = 4, .flags = RATE_IN_24XX }, 509 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
510 { .div = 0 } 510 { .div = 0 }
511}; 511};
@@ -537,7 +537,7 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */
537 * this domain. 537 * this domain.
538 */ 538 */
539static const struct clksel_rate l4_core_l3_rates[] = { 539static const struct clksel_rate l4_core_l3_rates[] = {
540 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 540 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
541 { .div = 2, .val = 2, .flags = RATE_IN_24XX }, 541 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
542 { .div = 0 } 542 { .div = 0 }
543}; 543};
@@ -568,7 +568,7 @@ static struct clk l4_ck = { /* used both as an ick and fck */
568 */ 568 */
569static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { 569static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
570 { .div = 1, .val = 1, .flags = RATE_IN_24XX }, 570 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
571 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, 571 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
572 { .div = 3, .val = 3, .flags = RATE_IN_24XX }, 572 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
573 { .div = 4, .val = 4, .flags = RATE_IN_24XX }, 573 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
574 { .div = 5, .val = 5, .flags = RATE_IN_243X }, 574 { .div = 5, .val = 5, .flags = RATE_IN_243X },
@@ -673,7 +673,7 @@ static struct clk gfx_ick = {
673 */ 673 */
674static const struct clksel_rate mdm_ick_core_rates[] = { 674static const struct clksel_rate mdm_ick_core_rates[] = {
675 { .div = 1, .val = 1, .flags = RATE_IN_243X }, 675 { .div = 1, .val = 1, .flags = RATE_IN_243X },
676 { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE }, 676 { .div = 4, .val = 4, .flags = RATE_IN_243X },
677 { .div = 6, .val = 6, .flags = RATE_IN_243X }, 677 { .div = 6, .val = 6, .flags = RATE_IN_243X },
678 { .div = 9, .val = 9, .flags = RATE_IN_243X }, 678 { .div = 9, .val = 9, .flags = RATE_IN_243X },
679 { .div = 0 } 679 { .div = 0 }
@@ -718,7 +718,7 @@ static struct clk mdm_osc_ck = {
718/* XXX Add RATE_NOT_VALIDATED */ 718/* XXX Add RATE_NOT_VALIDATED */
719 719
720static const struct clksel_rate dss1_fck_sys_rates[] = { 720static const struct clksel_rate dss1_fck_sys_rates[] = {
721 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 721 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
722 { .div = 0 } 722 { .div = 0 }
723}; 723};
724 724
@@ -732,7 +732,7 @@ static const struct clksel_rate dss1_fck_core_rates[] = {
732 { .div = 8, .val = 8, .flags = RATE_IN_24XX }, 732 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
733 { .div = 9, .val = 9, .flags = RATE_IN_24XX }, 733 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
734 { .div = 12, .val = 12, .flags = RATE_IN_24XX }, 734 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
735 { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE }, 735 { .div = 16, .val = 16, .flags = RATE_IN_24XX },
736 { .div = 0 } 736 { .div = 0 }
737}; 737};
738 738
@@ -767,12 +767,12 @@ static struct clk dss1_fck = {
767}; 767};
768 768
769static const struct clksel_rate dss2_fck_sys_rates[] = { 769static const struct clksel_rate dss2_fck_sys_rates[] = {
770 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 770 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
771 { .div = 0 } 771 { .div = 0 }
772}; 772};
773 773
774static const struct clksel_rate dss2_fck_48m_rates[] = { 774static const struct clksel_rate dss2_fck_48m_rates[] = {
775 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 775 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
776 { .div = 0 } 776 { .div = 0 }
777}; 777};
778 778
@@ -813,7 +813,7 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */
813 * functional clock parents. 813 * functional clock parents.
814 */ 814 */
815static const struct clksel_rate gpt_alt_rates[] = { 815static const struct clksel_rate gpt_alt_rates[] = {
816 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, 816 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
817 { .div = 0 } 817 { .div = 0 }
818}; 818};
819 819
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 6905eb7aa67c..80a12acdf9f8 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -110,32 +110,32 @@ static struct clk virt_38_4m_ck = {
110}; 110};
111 111
112static const struct clksel_rate osc_sys_12m_rates[] = { 112static const struct clksel_rate osc_sys_12m_rates[] = {
113 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 113 { .div = 1, .val = 0, .flags = RATE_IN_343X },
114 { .div = 0 } 114 { .div = 0 }
115}; 115};
116 116
117static const struct clksel_rate osc_sys_13m_rates[] = { 117static const struct clksel_rate osc_sys_13m_rates[] = {
118 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 118 { .div = 1, .val = 1, .flags = RATE_IN_343X },
119 { .div = 0 } 119 { .div = 0 }
120}; 120};
121 121
122static const struct clksel_rate osc_sys_16_8m_rates[] = { 122static const struct clksel_rate osc_sys_16_8m_rates[] = {
123 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE }, 123 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 },
124 { .div = 0 } 124 { .div = 0 }
125}; 125};
126 126
127static const struct clksel_rate osc_sys_19_2m_rates[] = { 127static const struct clksel_rate osc_sys_19_2m_rates[] = {
128 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, 128 { .div = 1, .val = 2, .flags = RATE_IN_343X },
129 { .div = 0 } 129 { .div = 0 }
130}; 130};
131 131
132static const struct clksel_rate osc_sys_26m_rates[] = { 132static const struct clksel_rate osc_sys_26m_rates[] = {
133 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, 133 { .div = 1, .val = 3, .flags = RATE_IN_343X },
134 { .div = 0 } 134 { .div = 0 }
135}; 135};
136 136
137static const struct clksel_rate osc_sys_38_4m_rates[] = { 137static const struct clksel_rate osc_sys_38_4m_rates[] = {
138 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE }, 138 { .div = 1, .val = 4, .flags = RATE_IN_343X },
139 { .div = 0 } 139 { .div = 0 }
140}; 140};
141 141
@@ -163,7 +163,7 @@ static struct clk osc_sys_ck = {
163}; 163};
164 164
165static const struct clksel_rate div2_rates[] = { 165static const struct clksel_rate div2_rates[] = {
166 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 166 { .div = 1, .val = 1, .flags = RATE_IN_343X },
167 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 167 { .div = 2, .val = 2, .flags = RATE_IN_343X },
168 { .div = 0 } 168 { .div = 0 }
169}; 169};
@@ -213,7 +213,7 @@ static struct clk sys_clkout1 = {
213/* CM CLOCKS */ 213/* CM CLOCKS */
214 214
215static const struct clksel_rate div16_dpll_rates[] = { 215static const struct clksel_rate div16_dpll_rates[] = {
216 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 216 { .div = 1, .val = 1, .flags = RATE_IN_343X },
217 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 217 { .div = 2, .val = 2, .flags = RATE_IN_343X },
218 { .div = 3, .val = 3, .flags = RATE_IN_343X }, 218 { .div = 3, .val = 3, .flags = RATE_IN_343X },
219 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 219 { .div = 4, .val = 4, .flags = RATE_IN_343X },
@@ -233,7 +233,7 @@ static const struct clksel_rate div16_dpll_rates[] = {
233}; 233};
234 234
235static const struct clksel_rate div32_dpll4_rates_3630[] = { 235static const struct clksel_rate div32_dpll4_rates_3630[] = {
236 { .div = 1, .val = 1, .flags = RATE_IN_36XX | DEFAULT_RATE }, 236 { .div = 1, .val = 1, .flags = RATE_IN_36XX },
237 { .div = 2, .val = 2, .flags = RATE_IN_36XX }, 237 { .div = 2, .val = 2, .flags = RATE_IN_36XX },
238 { .div = 3, .val = 3, .flags = RATE_IN_36XX }, 238 { .div = 3, .val = 3, .flags = RATE_IN_36XX },
239 { .div = 4, .val = 4, .flags = RATE_IN_36XX }, 239 { .div = 4, .val = 4, .flags = RATE_IN_36XX },
@@ -450,7 +450,7 @@ static struct clk dpll3_x2_ck = {
450}; 450};
451 451
452static const struct clksel_rate div31_dpll3_rates[] = { 452static const struct clksel_rate div31_dpll3_rates[] = {
453 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 453 { .div = 1, .val = 1, .flags = RATE_IN_343X },
454 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 454 { .div = 2, .val = 2, .flags = RATE_IN_343X },
455 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 }, 455 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
456 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 }, 456 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
@@ -698,7 +698,7 @@ static struct clk omap_192m_alwon_fck = {
698 698
699static const struct clksel_rate omap_96m_alwon_fck_rates[] = { 699static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
700 { .div = 1, .val = 1, .flags = RATE_IN_36XX }, 700 { .div = 1, .val = 1, .flags = RATE_IN_36XX },
701 { .div = 2, .val = 2, .flags = RATE_IN_36XX | DEFAULT_RATE }, 701 { .div = 2, .val = 2, .flags = RATE_IN_36XX },
702 { .div = 0 } 702 { .div = 0 }
703}; 703};
704 704
@@ -708,12 +708,12 @@ static const struct clksel omap_96m_alwon_fck_clksel[] = {
708}; 708};
709 709
710static const struct clksel_rate omap_96m_dpll_rates[] = { 710static const struct clksel_rate omap_96m_dpll_rates[] = {
711 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 711 { .div = 1, .val = 0, .flags = RATE_IN_343X },
712 { .div = 0 } 712 { .div = 0 }
713}; 713};
714 714
715static const struct clksel_rate omap_96m_sys_rates[] = { 715static const struct clksel_rate omap_96m_sys_rates[] = {
716 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 716 { .div = 1, .val = 1, .flags = RATE_IN_343X },
717 { .div = 0 } 717 { .div = 0 }
718}; 718};
719 719
@@ -799,12 +799,12 @@ static struct clk dpll4_m3x2_ck = {
799}; 799};
800 800
801static const struct clksel_rate omap_54m_d4m3x2_rates[] = { 801static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
802 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 802 { .div = 1, .val = 0, .flags = RATE_IN_343X },
803 { .div = 0 } 803 { .div = 0 }
804}; 804};
805 805
806static const struct clksel_rate omap_54m_alt_rates[] = { 806static const struct clksel_rate omap_54m_alt_rates[] = {
807 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 807 { .div = 1, .val = 1, .flags = RATE_IN_343X },
808 { .div = 0 } 808 { .div = 0 }
809}; 809};
810 810
@@ -825,12 +825,12 @@ static struct clk omap_54m_fck = {
825}; 825};
826 826
827static const struct clksel_rate omap_48m_cm96m_rates[] = { 827static const struct clksel_rate omap_48m_cm96m_rates[] = {
828 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 828 { .div = 2, .val = 0, .flags = RATE_IN_343X },
829 { .div = 0 } 829 { .div = 0 }
830}; 830};
831 831
832static const struct clksel_rate omap_48m_alt_rates[] = { 832static const struct clksel_rate omap_48m_alt_rates[] = {
833 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 833 { .div = 1, .val = 1, .flags = RATE_IN_343X },
834 { .div = 0 } 834 { .div = 0 }
835}; 835};
836 836
@@ -1049,22 +1049,22 @@ static struct clk dpll5_m2_ck = {
1049/* CM EXTERNAL CLOCK OUTPUTS */ 1049/* CM EXTERNAL CLOCK OUTPUTS */
1050 1050
1051static const struct clksel_rate clkout2_src_core_rates[] = { 1051static const struct clksel_rate clkout2_src_core_rates[] = {
1052 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 1052 { .div = 1, .val = 0, .flags = RATE_IN_343X },
1053 { .div = 0 } 1053 { .div = 0 }
1054}; 1054};
1055 1055
1056static const struct clksel_rate clkout2_src_sys_rates[] = { 1056static const struct clksel_rate clkout2_src_sys_rates[] = {
1057 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 1057 { .div = 1, .val = 1, .flags = RATE_IN_343X },
1058 { .div = 0 } 1058 { .div = 0 }
1059}; 1059};
1060 1060
1061static const struct clksel_rate clkout2_src_96m_rates[] = { 1061static const struct clksel_rate clkout2_src_96m_rates[] = {
1062 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, 1062 { .div = 1, .val = 2, .flags = RATE_IN_343X },
1063 { .div = 0 } 1063 { .div = 0 }
1064}; 1064};
1065 1065
1066static const struct clksel_rate clkout2_src_54m_rates[] = { 1066static const struct clksel_rate clkout2_src_54m_rates[] = {
1067 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, 1067 { .div = 1, .val = 3, .flags = RATE_IN_343X },
1068 { .div = 0 } 1068 { .div = 0 }
1069}; 1069};
1070 1070
@@ -1090,7 +1090,7 @@ static struct clk clkout2_src_ck = {
1090}; 1090};
1091 1091
1092static const struct clksel_rate sys_clkout2_rates[] = { 1092static const struct clksel_rate sys_clkout2_rates[] = {
1093 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 1093 { .div = 1, .val = 0, .flags = RATE_IN_343X },
1094 { .div = 2, .val = 1, .flags = RATE_IN_343X }, 1094 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1095 { .div = 4, .val = 2, .flags = RATE_IN_343X }, 1095 { .div = 4, .val = 2, .flags = RATE_IN_343X },
1096 { .div = 8, .val = 3, .flags = RATE_IN_343X }, 1096 { .div = 8, .val = 3, .flags = RATE_IN_343X },
@@ -1125,7 +1125,7 @@ static struct clk corex2_fck = {
1125/* DPLL power domain clock controls */ 1125/* DPLL power domain clock controls */
1126 1126
1127static const struct clksel_rate div4_rates[] = { 1127static const struct clksel_rate div4_rates[] = {
1128 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 1128 { .div = 1, .val = 1, .flags = RATE_IN_343X },
1129 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 1129 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1130 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 1130 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1131 { .div = 0 } 1131 { .div = 0 }
@@ -1161,7 +1161,7 @@ static struct clk mpu_ck = {
1161 1161
1162/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ 1162/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1163static const struct clksel_rate arm_fck_rates[] = { 1163static const struct clksel_rate arm_fck_rates[] = {
1164 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 1164 { .div = 1, .val = 0, .flags = RATE_IN_343X },
1165 { .div = 2, .val = 1, .flags = RATE_IN_343X }, 1165 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1166 { .div = 0 }, 1166 { .div = 0 },
1167}; 1167};
@@ -1333,25 +1333,25 @@ static struct clk gfx_cg2_ck = {
1333 1333
1334static const struct clksel_rate sgx_core_rates[] = { 1334static const struct clksel_rate sgx_core_rates[] = {
1335 { .div = 2, .val = 5, .flags = RATE_IN_36XX }, 1335 { .div = 2, .val = 5, .flags = RATE_IN_36XX },
1336 { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 1336 { .div = 3, .val = 0, .flags = RATE_IN_343X },
1337 { .div = 4, .val = 1, .flags = RATE_IN_343X }, 1337 { .div = 4, .val = 1, .flags = RATE_IN_343X },
1338 { .div = 6, .val = 2, .flags = RATE_IN_343X }, 1338 { .div = 6, .val = 2, .flags = RATE_IN_343X },
1339 { .div = 0 }, 1339 { .div = 0 },
1340}; 1340};
1341 1341
1342static const struct clksel_rate sgx_192m_rates[] = { 1342static const struct clksel_rate sgx_192m_rates[] = {
1343 { .div = 1, .val = 4, .flags = RATE_IN_36XX | DEFAULT_RATE }, 1343 { .div = 1, .val = 4, .flags = RATE_IN_36XX },
1344 { .div = 0 }, 1344 { .div = 0 },
1345}; 1345};
1346 1346
1347static const struct clksel_rate sgx_corex2_rates[] = { 1347static const struct clksel_rate sgx_corex2_rates[] = {
1348 { .div = 3, .val = 6, .flags = RATE_IN_36XX | DEFAULT_RATE }, 1348 { .div = 3, .val = 6, .flags = RATE_IN_36XX },
1349 { .div = 5, .val = 7, .flags = RATE_IN_36XX }, 1349 { .div = 5, .val = 7, .flags = RATE_IN_36XX },
1350 { .div = 0 }, 1350 { .div = 0 },
1351}; 1351};
1352 1352
1353static const struct clksel_rate sgx_96m_rates[] = { 1353static const struct clksel_rate sgx_96m_rates[] = {
1354 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, 1354 { .div = 1, .val = 3, .flags = RATE_IN_343X },
1355 { .div = 0 }, 1355 { .div = 0 },
1356}; 1356};
1357 1357
@@ -1576,12 +1576,12 @@ static struct clk i2c1_fck = {
1576 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck. 1576 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1577 */ 1577 */
1578static const struct clksel_rate common_mcbsp_96m_rates[] = { 1578static const struct clksel_rate common_mcbsp_96m_rates[] = {
1579 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 1579 { .div = 1, .val = 0, .flags = RATE_IN_343X },
1580 { .div = 0 } 1580 { .div = 0 }
1581}; 1581};
1582 1582
1583static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { 1583static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1584 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 1584 { .div = 1, .val = 1, .flags = RATE_IN_343X },
1585 { .div = 0 } 1585 { .div = 0 }
1586}; 1586};
1587 1587
@@ -1714,7 +1714,7 @@ static struct clk hdq_fck = {
1714/* DPLL3-derived clock */ 1714/* DPLL3-derived clock */
1715 1715
1716static const struct clksel_rate ssi_ssr_corex2_rates[] = { 1716static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1717 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 1717 { .div = 1, .val = 1, .flags = RATE_IN_343X },
1718 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 1718 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1719 { .div = 3, .val = 3, .flags = RATE_IN_343X }, 1719 { .div = 3, .val = 3, .flags = RATE_IN_343X },
1720 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 1720 { .div = 4, .val = 4, .flags = RATE_IN_343X },
@@ -2353,7 +2353,7 @@ static struct clk usbhost_ick = {
2353/* WKUP */ 2353/* WKUP */
2354 2354
2355static const struct clksel_rate usim_96m_rates[] = { 2355static const struct clksel_rate usim_96m_rates[] = {
2356 { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, 2356 { .div = 2, .val = 3, .flags = RATE_IN_343X },
2357 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 2357 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2358 { .div = 8, .val = 5, .flags = RATE_IN_343X }, 2358 { .div = 8, .val = 5, .flags = RATE_IN_343X },
2359 { .div = 10, .val = 6, .flags = RATE_IN_343X }, 2359 { .div = 10, .val = 6, .flags = RATE_IN_343X },
@@ -2361,7 +2361,7 @@ static const struct clksel_rate usim_96m_rates[] = {
2361}; 2361};
2362 2362
2363static const struct clksel_rate usim_120m_rates[] = { 2363static const struct clksel_rate usim_120m_rates[] = {
2364 { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE }, 2364 { .div = 4, .val = 7, .flags = RATE_IN_343X },
2365 { .div = 8, .val = 8, .flags = RATE_IN_343X }, 2365 { .div = 8, .val = 8, .flags = RATE_IN_343X },
2366 { .div = 16, .val = 9, .flags = RATE_IN_343X }, 2366 { .div = 16, .val = 9, .flags = RATE_IN_343X },
2367 { .div = 20, .val = 10, .flags = RATE_IN_343X }, 2367 { .div = 20, .val = 10, .flags = RATE_IN_343X },
@@ -2951,22 +2951,22 @@ static struct clk mcbsp4_fck = {
2951/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */ 2951/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2952 2952
2953static const struct clksel_rate emu_src_sys_rates[] = { 2953static const struct clksel_rate emu_src_sys_rates[] = {
2954 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 2954 { .div = 1, .val = 0, .flags = RATE_IN_343X },
2955 { .div = 0 }, 2955 { .div = 0 },
2956}; 2956};
2957 2957
2958static const struct clksel_rate emu_src_core_rates[] = { 2958static const struct clksel_rate emu_src_core_rates[] = {
2959 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 2959 { .div = 1, .val = 1, .flags = RATE_IN_343X },
2960 { .div = 0 }, 2960 { .div = 0 },
2961}; 2961};
2962 2962
2963static const struct clksel_rate emu_src_per_rates[] = { 2963static const struct clksel_rate emu_src_per_rates[] = {
2964 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, 2964 { .div = 1, .val = 2, .flags = RATE_IN_343X },
2965 { .div = 0 }, 2965 { .div = 0 },
2966}; 2966};
2967 2967
2968static const struct clksel_rate emu_src_mpu_rates[] = { 2968static const struct clksel_rate emu_src_mpu_rates[] = {
2969 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, 2969 { .div = 1, .val = 3, .flags = RATE_IN_343X },
2970 { .div = 0 }, 2970 { .div = 0 },
2971}; 2971};
2972 2972
@@ -2995,7 +2995,7 @@ static struct clk emu_src_ck = {
2995}; 2995};
2996 2996
2997static const struct clksel_rate pclk_emu_rates[] = { 2997static const struct clksel_rate pclk_emu_rates[] = {
2998 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, 2998 { .div = 2, .val = 2, .flags = RATE_IN_343X },
2999 { .div = 3, .val = 3, .flags = RATE_IN_343X }, 2999 { .div = 3, .val = 3, .flags = RATE_IN_343X },
3000 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 3000 { .div = 4, .val = 4, .flags = RATE_IN_343X },
3001 { .div = 6, .val = 6, .flags = RATE_IN_343X }, 3001 { .div = 6, .val = 6, .flags = RATE_IN_343X },
@@ -3019,7 +3019,7 @@ static struct clk pclk_fck = {
3019}; 3019};
3020 3020
3021static const struct clksel_rate pclkx2_emu_rates[] = { 3021static const struct clksel_rate pclkx2_emu_rates[] = {
3022 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 3022 { .div = 1, .val = 1, .flags = RATE_IN_343X },
3023 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 3023 { .div = 2, .val = 2, .flags = RATE_IN_343X },
3024 { .div = 3, .val = 3, .flags = RATE_IN_343X }, 3024 { .div = 3, .val = 3, .flags = RATE_IN_343X },
3025 { .div = 0 }, 3025 { .div = 0 },
@@ -3069,7 +3069,7 @@ static struct clk traceclk_src_fck = {
3069}; 3069};
3070 3070
3071static const struct clksel_rate traceclk_rates[] = { 3071static const struct clksel_rate traceclk_rates[] = {
3072 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 3072 { .div = 1, .val = 1, .flags = RATE_IN_343X },
3073 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 3073 { .div = 2, .val = 2, .flags = RATE_IN_343X },
3074 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 3074 { .div = 4, .val = 4, .flags = RATE_IN_343X },
3075 { .div = 0 }, 3075 { .div = 0 },
diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c
index f69096b88cdb..6f96dc4ef254 100644
--- a/arch/arm/mach-omap2/clock_common_data.c
+++ b/arch/arm/mach-omap2/clock_common_data.c
@@ -20,18 +20,18 @@
20 20
21/* clksel_rate data common to 24xx/343x */ 21/* clksel_rate data common to 24xx/343x */
22const struct clksel_rate gpt_32k_rates[] = { 22const struct clksel_rate gpt_32k_rates[] = {
23 { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, 23 { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X },
24 { .div = 0 } 24 { .div = 0 }
25}; 25};
26 26
27const struct clksel_rate gpt_sys_rates[] = { 27const struct clksel_rate gpt_sys_rates[] = {
28 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, 28 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X },
29 { .div = 0 } 29 { .div = 0 }
30}; 30};
31 31
32const struct clksel_rate gfx_l3_rates[] = { 32const struct clksel_rate gfx_l3_rates[] = {
33 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X }, 33 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X },
34 { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, 34 { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X },
35 { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X }, 35 { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X },
36 { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X }, 36 { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X },
37 { .div = 0 } 37 { .div = 0 }
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 34f7fa9ad4c0..9c551d676c63 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -196,13 +196,12 @@ extern struct clk dummy_ck;
196#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ 196#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
197 197
198/* Clksel_rate flags */ 198/* Clksel_rate flags */
199#define DEFAULT_RATE (1 << 0) 199#define RATE_IN_242X (1 << 0)
200#define RATE_IN_242X (1 << 1) 200#define RATE_IN_243X (1 << 1)
201#define RATE_IN_243X (1 << 2) 201#define RATE_IN_343X (1 << 2) /* rates common to all 343X */
202#define RATE_IN_343X (1 << 3) /* rates common to all 343X */ 202#define RATE_IN_3430ES2 (1 << 3) /* 3430ES2 rates only */
203#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */ 203#define RATE_IN_36XX (1 << 4)
204#define RATE_IN_36XX (1 << 5) 204#define RATE_IN_4430 (1 << 5)
205#define RATE_IN_4430 (1 << 6)
206 205
207#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) 206#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
208 207