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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2007-12-14 08:30:14 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-01-26 10:07:52 -0500
commit9e2697ff371b4380dca108a66860868c19d8c4b6 (patch)
treebf0d821b2a841a2246c5427ec670a81abc1eb35c /arch/arm
parentcae0554126e0545f8fc37282db7a906df1ec5c3c (diff)
[ARM] pxa: add cpufreq support
There have been patches hanging around for ages to add support for cpufreq to PXA255 processors. It's about time we applied one. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig8
-rw-r--r--arch/arm/mach-pxa/Makefile1
-rw-r--r--arch/arm/mach-pxa/cpu-pxa.c293
3 files changed, 301 insertions, 1 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1be718208704..4ea3d9e97f7f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -868,7 +868,7 @@ config KEXEC
868 868
869endmenu 869endmenu
870 870
871if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX ) 871if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA)
872 872
873menu "CPU Frequency scaling" 873menu "CPU Frequency scaling"
874 874
@@ -904,6 +904,12 @@ config CPU_FREQ_IMX
904 904
905 If in doubt, say N. 905 If in doubt, say N.
906 906
907config CPU_FREQ_PXA
908 bool
909 depends on CPU_FREQ && ARCH_PXA && PXA25x
910 default y
911 select CPU_FREQ_DEFAULT_GOV_USERSPACE
912
907endmenu 913endmenu
908 914
909endif 915endif
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 4263527e5123..3133dc4eaa7e 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_LEDS) += $(led-y)
42 42
43# Misc features 43# Misc features
44obj-$(CONFIG_PM) += pm.o sleep.o 44obj-$(CONFIG_PM) += pm.o sleep.o
45obj-$(CONFIG_CPU_FREQ) += cpu-pxa.o
45obj-$(CONFIG_PXA_SSP) += ssp.o 46obj-$(CONFIG_PXA_SSP) += ssp.o
46 47
47ifeq ($(CONFIG_PXA27x),y) 48ifeq ($(CONFIG_PXA27x),y)
diff --git a/arch/arm/mach-pxa/cpu-pxa.c b/arch/arm/mach-pxa/cpu-pxa.c
new file mode 100644
index 000000000000..18d042bdf243
--- /dev/null
+++ b/arch/arm/mach-pxa/cpu-pxa.c
@@ -0,0 +1,293 @@
1/*
2 * linux/arch/arm/mach-pxa/cpu-pxa.c
3 *
4 * Copyright (C) 2002,2003 Intrinsyc Software
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 * History:
21 * 31-Jul-2002 : Initial version [FB]
22 * 29-Jan-2003 : added PXA255 support [FB]
23 * 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
24 *
25 * Note:
26 * This driver may change the memory bus clock rate, but will not do any
27 * platform specific access timing changes... for example if you have flash
28 * memory connected to CS0, you will need to register a platform specific
29 * notifier which will adjust the memory access strobes to maintain a
30 * minimum strobe width.
31 *
32 */
33
34#include <linux/kernel.h>
35#include <linux/module.h>
36#include <linux/sched.h>
37#include <linux/init.h>
38#include <linux/cpufreq.h>
39
40#include <asm/hardware.h>
41#include <asm/arch/pxa-regs.h>
42
43#ifdef DEBUG
44static unsigned int freq_debug;
45MODULE_PARM(freq_debug, "i");
46MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
47#else
48#define freq_debug 0
49#endif
50
51typedef struct {
52 unsigned int khz;
53 unsigned int membus;
54 unsigned int cccr;
55 unsigned int div2;
56} pxa_freqs_t;
57
58/* Define the refresh period in mSec for the SDRAM and the number of rows */
59#define SDRAM_TREF 64 /* standard 64ms SDRAM */
60#define SDRAM_ROWS 4096 /* 64MB=8192 32MB=4096 */
61#define MDREFR_DRI(x) (((x) * SDRAM_TREF) / (SDRAM_ROWS * 32))
62
63#define CCLKCFG_TURBO 0x1
64#define CCLKCFG_FCS 0x2
65#define PXA25x_MIN_FREQ 99500
66#define PXA25x_MAX_FREQ 398100
67#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
68#define MDREFR_DRI_MASK 0xFFF
69
70
71/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */
72static pxa_freqs_t pxa255_run_freqs[] =
73{
74 /* CPU MEMBUS CCCR DIV2*/
75 { 99500, 99500, 0x121, 1}, /* run= 99, turbo= 99, PXbus=50, SDRAM=50 */
76 {132700, 132700, 0x123, 1}, /* run=133, turbo=133, PXbus=66, SDRAM=66 */
77 {199100, 99500, 0x141, 0}, /* run=199, turbo=199, PXbus=99, SDRAM=99 */
78 {265400, 132700, 0x143, 1}, /* run=265, turbo=265, PXbus=133, SDRAM=66 */
79 {331800, 165900, 0x145, 1}, /* run=331, turbo=331, PXbus=166, SDRAM=83 */
80 {398100, 99500, 0x161, 0}, /* run=398, turbo=398, PXbus=196, SDRAM=99 */
81 {0,}
82};
83#define NUM_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
84
85static struct cpufreq_frequency_table pxa255_run_freq_table[NUM_RUN_FREQS+1];
86
87/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
88static pxa_freqs_t pxa255_turbo_freqs[] =
89{
90 /* CPU MEMBUS CCCR DIV2*/
91 { 99500, 99500, 0x121, 1}, /* run=99, turbo= 99, PXbus=50, SDRAM=50 */
92 {199100, 99500, 0x221, 0}, /* run=99, turbo=199, PXbus=50, SDRAM=99 */
93 {298500, 99500, 0x321, 0}, /* run=99, turbo=287, PXbus=50, SDRAM=99 */
94 {298600, 99500, 0x1c1, 0}, /* run=199, turbo=287, PXbus=99, SDRAM=99 */
95 {398100, 99500, 0x241, 0}, /* run=199, turbo=398, PXbus=99, SDRAM=99 */
96 {0,}
97};
98#define NUM_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
99
100static struct cpufreq_frequency_table pxa255_turbo_freq_table[NUM_TURBO_FREQS+1];
101
102extern unsigned get_clk_frequency_khz(int info);
103
104/* find a valid frequency point */
105static int pxa_verify_policy(struct cpufreq_policy *policy)
106{
107 struct cpufreq_frequency_table *pxa_freqs_table;
108 int ret;
109
110 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
111 pxa_freqs_table = pxa255_run_freq_table;
112 } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
113 pxa_freqs_table = pxa255_turbo_freq_table;
114 } else {
115 printk("CPU PXA: Unknown policy found. "
116 "Using CPUFREQ_POLICY_PERFORMANCE\n");
117 pxa_freqs_table = pxa255_run_freq_table;
118 }
119
120 ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table);
121
122 if (freq_debug)
123 pr_debug("Verified CPU policy: %dKhz min to %dKhz max\n",
124 policy->min, policy->max);
125
126 return ret;
127}
128
129static int pxa_set_target(struct cpufreq_policy *policy,
130 unsigned int target_freq,
131 unsigned int relation)
132{
133 struct cpufreq_frequency_table *pxa_freqs_table;
134 pxa_freqs_t *pxa_freq_settings;
135 struct cpufreq_freqs freqs;
136 int idx;
137 unsigned long flags;
138 unsigned int unused, preset_mdrefr, postset_mdrefr;
139 void *ramstart = phys_to_virt(0xa0000000);
140
141 /* Get the current policy */
142 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
143 pxa_freq_settings = pxa255_run_freqs;
144 pxa_freqs_table = pxa255_run_freq_table;
145 } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
146 pxa_freq_settings = pxa255_turbo_freqs;
147 pxa_freqs_table = pxa255_turbo_freq_table;
148 } else {
149 printk("CPU PXA: Unknown policy found. "
150 "Using CPUFREQ_POLICY_PERFORMANCE\n");
151 pxa_freq_settings = pxa255_run_freqs;
152 pxa_freqs_table = pxa255_run_freq_table;
153 }
154
155 /* Lookup the next frequency */
156 if (cpufreq_frequency_table_target(policy, pxa_freqs_table,
157 target_freq, relation, &idx)) {
158 return -EINVAL;
159 }
160
161 freqs.old = policy->cur;
162 freqs.new = pxa_freq_settings[idx].khz;
163 freqs.cpu = policy->cpu;
164
165 if (freq_debug)
166 pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n",
167 freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
168 (pxa_freq_settings[idx].membus / 2000) :
169 (pxa_freq_settings[idx].membus / 1000));
170
171 /*
172 * Tell everyone what we're about to do...
173 * you should add a notify client with any platform specific
174 * Vcc changing capability
175 */
176 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
177
178 /* Calculate the next MDREFR. If we're slowing down the SDRAM clock
179 * we need to preset the smaller DRI before the change. If we're speeding
180 * up we need to set the larger DRI value after the change.
181 */
182 preset_mdrefr = postset_mdrefr = MDREFR;
183 if ((MDREFR & MDREFR_DRI_MASK) > MDREFR_DRI(pxa_freq_settings[idx].membus)) {
184 preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK) |
185 MDREFR_DRI(pxa_freq_settings[idx].membus);
186 }
187 postset_mdrefr = (postset_mdrefr & ~MDREFR_DRI_MASK) |
188 MDREFR_DRI(pxa_freq_settings[idx].membus);
189
190 /* If we're dividing the memory clock by two for the SDRAM clock, this
191 * must be set prior to the change. Clearing the divide must be done
192 * after the change.
193 */
194 if (pxa_freq_settings[idx].div2) {
195 preset_mdrefr |= MDREFR_DB2_MASK;
196 postset_mdrefr |= MDREFR_DB2_MASK;
197 } else {
198 postset_mdrefr &= ~MDREFR_DB2_MASK;
199 }
200
201 local_irq_save(flags);
202
203 /* Set new the CCCR */
204 CCCR = pxa_freq_settings[idx].cccr;
205
206 asm volatile(" \n\
207 ldr r4, [%1] /* load MDREFR */ \n\
208 b 2f \n\
209 .align 5 \n\
2101: \n\
211 str %4, [%1] /* preset the MDREFR */ \n\
212 mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\
213 str %5, [%1] /* postset the MDREFR */ \n\
214 \n\
215 b 3f \n\
2162: b 1b \n\
2173: nop \n\
218 "
219 : "=&r" (unused)
220 : "r" (&MDREFR), "r" (CCLKCFG_TURBO|CCLKCFG_FCS), "r" (ramstart),
221 "r" (preset_mdrefr), "r" (postset_mdrefr)
222 : "r4", "r5");
223 local_irq_restore(flags);
224
225 /*
226 * Tell everyone what we've just done...
227 * you should add a notify client with any platform specific
228 * SDRAM refresh timer adjustments
229 */
230 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
231
232 return 0;
233}
234
235static int pxa_cpufreq_init(struct cpufreq_policy *policy)
236{
237 int i;
238
239 /* set default policy and cpuinfo */
240 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
241 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
242 policy->cpuinfo.max_freq = PXA25x_MAX_FREQ;
243 policy->cpuinfo.min_freq = PXA25x_MIN_FREQ;
244 policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
245 policy->cur = get_clk_frequency_khz(0); /* current freq */
246 policy->min = policy->max = policy->cur;
247
248 /* Generate the run cpufreq_frequency_table struct */
249 for (i = 0; i < NUM_RUN_FREQS; i++) {
250 pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
251 pxa255_run_freq_table[i].index = i;
252 }
253
254 pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
255 /* Generate the turbo cpufreq_frequency_table struct */
256 for (i = 0; i < NUM_TURBO_FREQS; i++) {
257 pxa255_turbo_freq_table[i].frequency = pxa255_turbo_freqs[i].khz;
258 pxa255_turbo_freq_table[i].index = i;
259 }
260 pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
261
262 printk(KERN_INFO "PXA CPU frequency change support initialized\n");
263
264 return 0;
265}
266
267static struct cpufreq_driver pxa_cpufreq_driver = {
268 .verify = pxa_verify_policy,
269 .target = pxa_set_target,
270 .init = pxa_cpufreq_init,
271 .name = "PXA25x",
272};
273
274static int __init pxa_cpu_init(void)
275{
276 int ret = -ENODEV;
277 if (cpu_is_pxa25x())
278 ret = cpufreq_register_driver(&pxa_cpufreq_driver);
279 return ret;
280}
281
282static void __exit pxa_cpu_exit(void)
283{
284 if (cpu_is_pxa25x())
285 cpufreq_unregister_driver(&pxa_cpufreq_driver);
286}
287
288
289MODULE_AUTHOR ("Intrinsyc Software Inc.");
290MODULE_DESCRIPTION ("CPU frequency changing driver for the PXA architecture");
291MODULE_LICENSE("GPL");
292module_init(pxa_cpu_init);
293module_exit(pxa_cpu_exit);