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authorMarc Zyngier <marc.zyngier@arm.com>2013-02-11 14:03:52 -0500
committerMarc Zyngier <marc.zyngier@arm.com>2013-02-11 14:03:52 -0500
commit9ae9e2535d7dd1c21d6a7db1a7f2fc507a5e4080 (patch)
treef059571830a159f05b8cdf4ec354b01ca7d6bc45 /arch/arm
parent75431f9d7335daf7fb9e72b3a1539ce610142618 (diff)
parent9e02e394c7d7fdc2570a73fb7fc6da3c79f6db2a (diff)
Merge branch 'for-arm-soc/arch-timers' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into kvm-arm/timer
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig4
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/armada-370-db.dts2
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78230.dtsi14
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78260.dtsi21
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78460.dtsi21
-rw-r--r--arch/arm/boot/dts/at91rm9200.dtsi4
-rw-r--r--arch/arm/boot/dts/at91sam9260.dtsi18
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi36
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi36
-rw-r--r--arch/arm/boot/dts/at91sam9n12.dtsi26
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi92
-rw-r--r--arch/arm/boot/dts/cros5250-common.dtsi12
-rw-r--r--arch/arm/boot/dts/dove-cubox.dts14
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts8
-rw-r--r--arch/arm/boot/dts/kirkwood-ns2-common.dtsi16
-rw-r--r--arch/arm/boot/dts/kirkwood.dtsi2
-rw-r--r--arch/arm/boot/dts/kizbox.dts2
-rw-r--r--arch/arm/boot/dts/sunxi.dtsi6
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts2
-rw-r--r--arch/arm/configs/at91_dt_defconfig3
-rw-r--r--arch/arm/include/asm/arch_timer.h109
-rw-r--r--arch/arm/kernel/arch_timer.c504
-rw-r--r--arch/arm/kernel/debug.S2
-rw-r--r--arch/arm/kernel/head.S5
-rw-r--r--arch/arm/kernel/hyp-stub.S18
-rw-r--r--arch/arm/kernel/smp.c13
-rw-r--r--arch/arm/mach-at91/setup.c2
-rw-r--r--arch/arm/mach-imx/Kconfig1
-rw-r--r--arch/arm/mach-imx/clk-imx25.c6
-rw-r--r--arch/arm/mach-imx/clk-imx27.c6
-rw-r--r--arch/arm/mach-imx/clk-imx31.c6
-rw-r--r--arch/arm/mach-imx/clk-imx35.c6
-rw-r--r--arch/arm/mach-imx/clk-imx51-imx53.c6
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c3
-rw-r--r--arch/arm/mach-imx/common.h1
-rw-r--r--arch/arm/mach-imx/devices/devices-common.h1
-rw-r--r--arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c15
-rw-r--r--arch/arm/mach-imx/devices/platform-imx-fb.c2
-rw-r--r--arch/arm/mach-imx/hotplug.c10
-rw-r--r--arch/arm/mach-imx/iram.h41
-rw-r--r--arch/arm/mach-imx/iram_alloc.c3
-rw-r--r--arch/arm/mach-imx/platsmp.c1
-rw-r--r--arch/arm/mach-imx/pm-imx6q.c1
-rw-r--r--arch/arm/mach-integrator/pci_v3.c14
-rw-r--r--arch/arm/mach-kirkwood/board-ns2.c38
-rw-r--r--arch/arm/mach-mvebu/Makefile2
-rw-r--r--arch/arm/mach-omap2/Kconfig2
-rw-r--r--arch/arm/mach-omap2/board-omap4panda.c6
-rw-r--r--arch/arm/mach-omap2/cclock2420_data.c2
-rw-r--r--arch/arm/mach-omap2/cclock2430_data.c2
-rw-r--r--arch/arm/mach-omap2/cclock44xx_data.c13
-rw-r--r--arch/arm/mach-omap2/devices.c2
-rw-r--r--arch/arm/mach-omap2/drm.c3
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c6
-rw-r--r--arch/arm/mach-omap2/timer.c8
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa27x.h3
-rw-r--r--arch/arm/mach-pxa/pxa27x.c4
-rw-r--r--arch/arm/mach-s3c64xx/mach-crag6410-module.c2
-rw-r--r--arch/arm/mach-s3c64xx/pm.c2
-rw-r--r--arch/arm/mm/dma-mapping.c18
-rw-r--r--arch/arm/mm/mmu.c2
-rw-r--r--arch/arm/plat-versatile/headsmp.S2
-rw-r--r--arch/arm/vfp/entry.S6
-rw-r--r--arch/arm/vfp/vfphw.S4
65 files changed, 504 insertions, 739 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e0627cdbcda5..0ad2823bf8c2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -4,6 +4,7 @@ config ARM
4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE 4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE 5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H 6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_WANT_IPC_PARSE_VERSION 8 select ARCH_WANT_IPC_PARSE_VERSION
8 select BUILDTIME_EXTABLE_SORT if MMU 9 select BUILDTIME_EXTABLE_SORT if MMU
9 select CPU_PM if (SUSPEND || CPU_IDLE) 10 select CPU_PM if (SUSPEND || CPU_IDLE)
@@ -1572,9 +1573,10 @@ config HAVE_ARM_SCU
1572 help 1573 help
1573 This option enables support for the ARM system coherency unit 1574 This option enables support for the ARM system coherency unit
1574 1575
1575config ARM_ARCH_TIMER 1576config HAVE_ARM_ARCH_TIMER
1576 bool "Architected timer support" 1577 bool "Architected timer support"
1577 depends on CPU_V7 1578 depends on CPU_V7
1579 select ARM_ARCH_TIMER
1578 help 1580 help
1579 This option enables support for the ARM architected timer 1581 This option enables support for the ARM architected timer
1580 1582
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index e44da40d984f..5ebb44fe826a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -155,6 +155,7 @@ dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
155dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb 155dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb
156 156
157targets += dtbs 157targets += dtbs
158targets += $(dtb-y)
158endif 159endif
159 160
160# *.dtb used to be generated in the directory above. Clean out the 161# *.dtb used to be generated in the directory above. Clean out the
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index 00044026ef1f..9b82facb2561 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -26,7 +26,7 @@
26 26
27 memory { 27 memory {
28 device_type = "memory"; 28 device_type = "memory";
29 reg = <0x00000000 0x20000000>; /* 512 MB */ 29 reg = <0x00000000 0x40000000>; /* 1 GB */
30 }; 30 };
31 31
32 soc { 32 soc {
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index 271855a6e224..e041f42ed711 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -50,27 +50,25 @@
50 }; 50 };
51 51
52 gpio0: gpio@d0018100 { 52 gpio0: gpio@d0018100 {
53 compatible = "marvell,armadaxp-gpio"; 53 compatible = "marvell,orion-gpio";
54 reg = <0xd0018100 0x40>, 54 reg = <0xd0018100 0x40>;
55 <0xd0018800 0x30>;
56 ngpios = <32>; 55 ngpios = <32>;
57 gpio-controller; 56 gpio-controller;
58 #gpio-cells = <2>; 57 #gpio-cells = <2>;
59 interrupt-controller; 58 interrupt-controller;
60 #interrupts-cells = <2>; 59 #interrupts-cells = <2>;
61 interrupts = <16>, <17>, <18>, <19>; 60 interrupts = <82>, <83>, <84>, <85>;
62 }; 61 };
63 62
64 gpio1: gpio@d0018140 { 63 gpio1: gpio@d0018140 {
65 compatible = "marvell,armadaxp-gpio"; 64 compatible = "marvell,orion-gpio";
66 reg = <0xd0018140 0x40>, 65 reg = <0xd0018140 0x40>;
67 <0xd0018840 0x30>;
68 ngpios = <17>; 66 ngpios = <17>;
69 gpio-controller; 67 gpio-controller;
70 #gpio-cells = <2>; 68 #gpio-cells = <2>;
71 interrupt-controller; 69 interrupt-controller;
72 #interrupts-cells = <2>; 70 #interrupts-cells = <2>;
73 interrupts = <20>, <21>, <22>; 71 interrupts = <87>, <88>, <89>;
74 }; 72 };
75 }; 73 };
76}; 74};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 1c1937dbce73..9e23bd8c9536 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -51,39 +51,36 @@
51 }; 51 };
52 52
53 gpio0: gpio@d0018100 { 53 gpio0: gpio@d0018100 {
54 compatible = "marvell,armadaxp-gpio"; 54 compatible = "marvell,orion-gpio";
55 reg = <0xd0018100 0x40>, 55 reg = <0xd0018100 0x40>;
56 <0xd0018800 0x30>;
57 ngpios = <32>; 56 ngpios = <32>;
58 gpio-controller; 57 gpio-controller;
59 #gpio-cells = <2>; 58 #gpio-cells = <2>;
60 interrupt-controller; 59 interrupt-controller;
61 #interrupts-cells = <2>; 60 #interrupts-cells = <2>;
62 interrupts = <16>, <17>, <18>, <19>; 61 interrupts = <82>, <83>, <84>, <85>;
63 }; 62 };
64 63
65 gpio1: gpio@d0018140 { 64 gpio1: gpio@d0018140 {
66 compatible = "marvell,armadaxp-gpio"; 65 compatible = "marvell,orion-gpio";
67 reg = <0xd0018140 0x40>, 66 reg = <0xd0018140 0x40>;
68 <0xd0018840 0x30>;
69 ngpios = <32>; 67 ngpios = <32>;
70 gpio-controller; 68 gpio-controller;
71 #gpio-cells = <2>; 69 #gpio-cells = <2>;
72 interrupt-controller; 70 interrupt-controller;
73 #interrupts-cells = <2>; 71 #interrupts-cells = <2>;
74 interrupts = <20>, <21>, <22>, <23>; 72 interrupts = <87>, <88>, <89>, <90>;
75 }; 73 };
76 74
77 gpio2: gpio@d0018180 { 75 gpio2: gpio@d0018180 {
78 compatible = "marvell,armadaxp-gpio"; 76 compatible = "marvell,orion-gpio";
79 reg = <0xd0018180 0x40>, 77 reg = <0xd0018180 0x40>;
80 <0xd0018870 0x30>;
81 ngpios = <3>; 78 ngpios = <3>;
82 gpio-controller; 79 gpio-controller;
83 #gpio-cells = <2>; 80 #gpio-cells = <2>;
84 interrupt-controller; 81 interrupt-controller;
85 #interrupts-cells = <2>; 82 #interrupts-cells = <2>;
86 interrupts = <24>; 83 interrupts = <91>;
87 }; 84 };
88 85
89 ethernet@d0034000 { 86 ethernet@d0034000 {
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 4905cf3a5ef8..965966110e38 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -66,39 +66,36 @@
66 }; 66 };
67 67
68 gpio0: gpio@d0018100 { 68 gpio0: gpio@d0018100 {
69 compatible = "marvell,armadaxp-gpio"; 69 compatible = "marvell,orion-gpio";
70 reg = <0xd0018100 0x40>, 70 reg = <0xd0018100 0x40>;
71 <0xd0018800 0x30>;
72 ngpios = <32>; 71 ngpios = <32>;
73 gpio-controller; 72 gpio-controller;
74 #gpio-cells = <2>; 73 #gpio-cells = <2>;
75 interrupt-controller; 74 interrupt-controller;
76 #interrupts-cells = <2>; 75 #interrupts-cells = <2>;
77 interrupts = <16>, <17>, <18>, <19>; 76 interrupts = <82>, <83>, <84>, <85>;
78 }; 77 };
79 78
80 gpio1: gpio@d0018140 { 79 gpio1: gpio@d0018140 {
81 compatible = "marvell,armadaxp-gpio"; 80 compatible = "marvell,orion-gpio";
82 reg = <0xd0018140 0x40>, 81 reg = <0xd0018140 0x40>;
83 <0xd0018840 0x30>;
84 ngpios = <32>; 82 ngpios = <32>;
85 gpio-controller; 83 gpio-controller;
86 #gpio-cells = <2>; 84 #gpio-cells = <2>;
87 interrupt-controller; 85 interrupt-controller;
88 #interrupts-cells = <2>; 86 #interrupts-cells = <2>;
89 interrupts = <20>, <21>, <22>, <23>; 87 interrupts = <87>, <88>, <89>, <90>;
90 }; 88 };
91 89
92 gpio2: gpio@d0018180 { 90 gpio2: gpio@d0018180 {
93 compatible = "marvell,armadaxp-gpio"; 91 compatible = "marvell,orion-gpio";
94 reg = <0xd0018180 0x40>, 92 reg = <0xd0018180 0x40>;
95 <0xd0018870 0x30>;
96 ngpios = <3>; 93 ngpios = <3>;
97 gpio-controller; 94 gpio-controller;
98 #gpio-cells = <2>; 95 #gpio-cells = <2>;
99 interrupt-controller; 96 interrupt-controller;
100 #interrupts-cells = <2>; 97 #interrupts-cells = <2>;
101 interrupts = <24>; 98 interrupts = <91>;
102 }; 99 };
103 100
104 ethernet@d0034000 { 101 ethernet@d0034000 {
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index e154f242c680..222047f1ece9 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -336,8 +336,8 @@
336 336
337 i2c@0 { 337 i2c@0 {
338 compatible = "i2c-gpio"; 338 compatible = "i2c-gpio";
339 gpios = <&pioA 23 0 /* sda */ 339 gpios = <&pioA 25 0 /* sda */
340 &pioA 24 0 /* scl */ 340 &pioA 26 0 /* scl */
341 >; 341 >;
342 i2c-gpio,sda-open-drain; 342 i2c-gpio,sda-open-drain;
343 i2c-gpio,scl-open-drain; 343 i2c-gpio,scl-open-drain;
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 68bccf41a2c6..cb7bcc51608d 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -306,6 +306,22 @@
306 }; 306 };
307 }; 307 };
308 308
309 ssc0 {
310 pinctrl_ssc0_tx: ssc0_tx-0 {
311 atmel,pins =
312 <1 16 0x1 0x0 /* PB16 periph A */
313 1 17 0x1 0x0 /* PB17 periph A */
314 1 18 0x1 0x0>; /* PB18 periph A */
315 };
316
317 pinctrl_ssc0_rx: ssc0_rx-0 {
318 atmel,pins =
319 <1 19 0x1 0x0 /* PB19 periph A */
320 1 20 0x1 0x0 /* PB20 periph A */
321 1 21 0x1 0x0>; /* PB21 periph A */
322 };
323 };
324
309 pioA: gpio@fffff400 { 325 pioA: gpio@fffff400 {
310 compatible = "atmel,at91rm9200-gpio"; 326 compatible = "atmel,at91rm9200-gpio";
311 reg = <0xfffff400 0x200>; 327 reg = <0xfffff400 0x200>;
@@ -450,6 +466,8 @@
450 compatible = "atmel,at91rm9200-ssc"; 466 compatible = "atmel,at91rm9200-ssc";
451 reg = <0xfffbc000 0x4000>; 467 reg = <0xfffbc000 0x4000>;
452 interrupts = <14 4 5>; 468 interrupts = <14 4 5>;
469 pinctrl-names = "default";
470 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
453 status = "disabled"; 471 status = "disabled";
454 }; 472 };
455 473
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 32ec62cf5385..271d4de026e9 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -271,6 +271,38 @@
271 }; 271 };
272 }; 272 };
273 273
274 ssc0 {
275 pinctrl_ssc0_tx: ssc0_tx-0 {
276 atmel,pins =
277 <1 0 0x2 0x0 /* PB0 periph B */
278 1 1 0x2 0x0 /* PB1 periph B */
279 1 2 0x2 0x0>; /* PB2 periph B */
280 };
281
282 pinctrl_ssc0_rx: ssc0_rx-0 {
283 atmel,pins =
284 <1 3 0x2 0x0 /* PB3 periph B */
285 1 4 0x2 0x0 /* PB4 periph B */
286 1 5 0x2 0x0>; /* PB5 periph B */
287 };
288 };
289
290 ssc1 {
291 pinctrl_ssc1_tx: ssc1_tx-0 {
292 atmel,pins =
293 <1 6 0x1 0x0 /* PB6 periph A */
294 1 7 0x1 0x0 /* PB7 periph A */
295 1 8 0x1 0x0>; /* PB8 periph A */
296 };
297
298 pinctrl_ssc1_rx: ssc1_rx-0 {
299 atmel,pins =
300 <1 9 0x1 0x0 /* PB9 periph A */
301 1 10 0x1 0x0 /* PB10 periph A */
302 1 11 0x1 0x0>; /* PB11 periph A */
303 };
304 };
305
274 pioA: gpio@fffff200 { 306 pioA: gpio@fffff200 {
275 compatible = "atmel,at91rm9200-gpio"; 307 compatible = "atmel,at91rm9200-gpio";
276 reg = <0xfffff200 0x200>; 308 reg = <0xfffff200 0x200>;
@@ -368,6 +400,8 @@
368 compatible = "atmel,at91rm9200-ssc"; 400 compatible = "atmel,at91rm9200-ssc";
369 reg = <0xfff98000 0x4000>; 401 reg = <0xfff98000 0x4000>;
370 interrupts = <16 4 5>; 402 interrupts = <16 4 5>;
403 pinctrl-names = "default";
404 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
371 status = "disabled"; 405 status = "disabled";
372 }; 406 };
373 407
@@ -375,6 +409,8 @@
375 compatible = "atmel,at91rm9200-ssc"; 409 compatible = "atmel,at91rm9200-ssc";
376 reg = <0xfff9c000 0x4000>; 410 reg = <0xfff9c000 0x4000>;
377 interrupts = <17 4 5>; 411 interrupts = <17 4 5>;
412 pinctrl-names = "default";
413 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
378 status = "disabled"; 414 status = "disabled";
379 }; 415 };
380 416
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 231858ffd850..6b1d4cab24c2 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -290,6 +290,38 @@
290 }; 290 };
291 }; 291 };
292 292
293 ssc0 {
294 pinctrl_ssc0_tx: ssc0_tx-0 {
295 atmel,pins =
296 <3 0 0x1 0x0 /* PD0 periph A */
297 3 1 0x1 0x0 /* PD1 periph A */
298 3 2 0x1 0x0>; /* PD2 periph A */
299 };
300
301 pinctrl_ssc0_rx: ssc0_rx-0 {
302 atmel,pins =
303 <3 3 0x1 0x0 /* PD3 periph A */
304 3 4 0x1 0x0 /* PD4 periph A */
305 3 5 0x1 0x0>; /* PD5 periph A */
306 };
307 };
308
309 ssc1 {
310 pinctrl_ssc1_tx: ssc1_tx-0 {
311 atmel,pins =
312 <3 10 0x1 0x0 /* PD10 periph A */
313 3 11 0x1 0x0 /* PD11 periph A */
314 3 12 0x1 0x0>; /* PD12 periph A */
315 };
316
317 pinctrl_ssc1_rx: ssc1_rx-0 {
318 atmel,pins =
319 <3 13 0x1 0x0 /* PD13 periph A */
320 3 14 0x1 0x0 /* PD14 periph A */
321 3 15 0x1 0x0>; /* PD15 periph A */
322 };
323 };
324
293 pioA: gpio@fffff200 { 325 pioA: gpio@fffff200 {
294 compatible = "atmel,at91rm9200-gpio"; 326 compatible = "atmel,at91rm9200-gpio";
295 reg = <0xfffff200 0x200>; 327 reg = <0xfffff200 0x200>;
@@ -425,6 +457,8 @@
425 compatible = "atmel,at91sam9g45-ssc"; 457 compatible = "atmel,at91sam9g45-ssc";
426 reg = <0xfff9c000 0x4000>; 458 reg = <0xfff9c000 0x4000>;
427 interrupts = <16 4 5>; 459 interrupts = <16 4 5>;
460 pinctrl-names = "default";
461 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
428 status = "disabled"; 462 status = "disabled";
429 }; 463 };
430 464
@@ -432,6 +466,8 @@
432 compatible = "atmel,at91sam9g45-ssc"; 466 compatible = "atmel,at91sam9g45-ssc";
433 reg = <0xfffa0000 0x4000>; 467 reg = <0xfffa0000 0x4000>;
434 interrupts = <17 4 5>; 468 interrupts = <17 4 5>;
469 pinctrl-names = "default";
470 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
435 status = "disabled"; 471 status = "disabled";
436 }; 472 };
437 473
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index e9efb34f4379..80e29c605d4e 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -28,6 +28,7 @@
28 tcb1 = &tcb1; 28 tcb1 = &tcb1;
29 i2c0 = &i2c0; 29 i2c0 = &i2c0;
30 i2c1 = &i2c1; 30 i2c1 = &i2c1;
31 ssc0 = &ssc0;
31 }; 32 };
32 cpus { 33 cpus {
33 cpu@0 { 34 cpu@0 {
@@ -244,6 +245,22 @@
244 }; 245 };
245 }; 246 };
246 247
248 ssc0 {
249 pinctrl_ssc0_tx: ssc0_tx-0 {
250 atmel,pins =
251 <0 24 0x2 0x0 /* PA24 periph B */
252 0 25 0x2 0x0 /* PA25 periph B */
253 0 26 0x2 0x0>; /* PA26 periph B */
254 };
255
256 pinctrl_ssc0_rx: ssc0_rx-0 {
257 atmel,pins =
258 <0 27 0x2 0x0 /* PA27 periph B */
259 0 28 0x2 0x0 /* PA28 periph B */
260 0 29 0x2 0x0>; /* PA29 periph B */
261 };
262 };
263
247 pioA: gpio@fffff400 { 264 pioA: gpio@fffff400 {
248 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 265 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
249 reg = <0xfffff400 0x200>; 266 reg = <0xfffff400 0x200>;
@@ -294,6 +311,15 @@
294 status = "disabled"; 311 status = "disabled";
295 }; 312 };
296 313
314 ssc0: ssc@f0010000 {
315 compatible = "atmel,at91sam9g45-ssc";
316 reg = <0xf0010000 0x4000>;
317 interrupts = <28 4 5>;
318 pinctrl-names = "default";
319 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
320 status = "disabled";
321 };
322
297 usart0: serial@f801c000 { 323 usart0: serial@f801c000 {
298 compatible = "atmel,at91sam9260-usart"; 324 compatible = "atmel,at91sam9260-usart";
299 reg = <0xf801c000 0x4000>; 325 reg = <0xf801c000 0x4000>;
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 40ac3a4eb1ab..8ecca6948d81 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -88,13 +88,6 @@
88 interrupts = <1 4 7>; 88 interrupts = <1 4 7>;
89 }; 89 };
90 90
91 ssc0: ssc@f0010000 {
92 compatible = "atmel,at91sam9g45-ssc";
93 reg = <0xf0010000 0x4000>;
94 interrupts = <28 4 5>;
95 status = "disabled";
96 };
97
98 tcb0: timer@f8008000 { 91 tcb0: timer@f8008000 {
99 compatible = "atmel,at91sam9x5-tcb"; 92 compatible = "atmel,at91sam9x5-tcb";
100 reg = <0xf8008000 0x100>; 93 reg = <0xf8008000 0x100>;
@@ -150,6 +143,11 @@
150 atmel,pins = 143 atmel,pins =
151 <0 3 0x1 0x0>; /* PA3 periph A */ 144 <0 3 0x1 0x0>; /* PA3 periph A */
152 }; 145 };
146
147 pinctrl_usart0_sck: usart0_sck-0 {
148 atmel,pins =
149 <0 4 0x1 0x0>; /* PA4 periph A */
150 };
153 }; 151 };
154 152
155 usart1 { 153 usart1 {
@@ -161,12 +159,17 @@
161 159
162 pinctrl_usart1_rts: usart1_rts-0 { 160 pinctrl_usart1_rts: usart1_rts-0 {
163 atmel,pins = 161 atmel,pins =
164 <3 27 0x3 0x0>; /* PC27 periph C */ 162 <2 27 0x3 0x0>; /* PC27 periph C */
165 }; 163 };
166 164
167 pinctrl_usart1_cts: usart1_cts-0 { 165 pinctrl_usart1_cts: usart1_cts-0 {
168 atmel,pins = 166 atmel,pins =
169 <3 28 0x3 0x0>; /* PC28 periph C */ 167 <2 28 0x3 0x0>; /* PC28 periph C */
168 };
169
170 pinctrl_usart1_sck: usart1_sck-0 {
171 atmel,pins =
172 <2 28 0x3 0x0>; /* PC29 periph C */
170 }; 173 };
171 }; 174 };
172 175
@@ -179,46 +182,56 @@
179 182
180 pinctrl_uart2_rts: uart2_rts-0 { 183 pinctrl_uart2_rts: uart2_rts-0 {
181 atmel,pins = 184 atmel,pins =
182 <0 0 0x2 0x0>; /* PB0 periph B */ 185 <1 0 0x2 0x0>; /* PB0 periph B */
183 }; 186 };
184 187
185 pinctrl_uart2_cts: uart2_cts-0 { 188 pinctrl_uart2_cts: uart2_cts-0 {
186 atmel,pins = 189 atmel,pins =
187 <0 1 0x2 0x0>; /* PB1 periph B */ 190 <1 1 0x2 0x0>; /* PB1 periph B */
191 };
192
193 pinctrl_usart2_sck: usart2_sck-0 {
194 atmel,pins =
195 <1 2 0x2 0x0>; /* PB2 periph B */
188 }; 196 };
189 }; 197 };
190 198
191 usart3 { 199 usart3 {
192 pinctrl_uart3: usart3-0 { 200 pinctrl_uart3: usart3-0 {
193 atmel,pins = 201 atmel,pins =
194 <3 23 0x2 0x1 /* PC22 periph B with pullup */ 202 <2 23 0x2 0x1 /* PC22 periph B with pullup */
195 3 23 0x2 0x0>; /* PC23 periph B */ 203 2 23 0x2 0x0>; /* PC23 periph B */
196 }; 204 };
197 205
198 pinctrl_usart3_rts: usart3_rts-0 { 206 pinctrl_usart3_rts: usart3_rts-0 {
199 atmel,pins = 207 atmel,pins =
200 <3 24 0x2 0x0>; /* PC24 periph B */ 208 <2 24 0x2 0x0>; /* PC24 periph B */
201 }; 209 };
202 210
203 pinctrl_usart3_cts: usart3_cts-0 { 211 pinctrl_usart3_cts: usart3_cts-0 {
204 atmel,pins = 212 atmel,pins =
205 <3 25 0x2 0x0>; /* PC25 periph B */ 213 <2 25 0x2 0x0>; /* PC25 periph B */
214 };
215
216 pinctrl_usart3_sck: usart3_sck-0 {
217 atmel,pins =
218 <2 26 0x2 0x0>; /* PC26 periph B */
206 }; 219 };
207 }; 220 };
208 221
209 uart0 { 222 uart0 {
210 pinctrl_uart0: uart0-0 { 223 pinctrl_uart0: uart0-0 {
211 atmel,pins = 224 atmel,pins =
212 <3 8 0x3 0x0 /* PC8 periph C */ 225 <2 8 0x3 0x0 /* PC8 periph C */
213 3 9 0x3 0x1>; /* PC9 periph C with pullup */ 226 2 9 0x3 0x1>; /* PC9 periph C with pullup */
214 }; 227 };
215 }; 228 };
216 229
217 uart1 { 230 uart1 {
218 pinctrl_uart1: uart1-0 { 231 pinctrl_uart1: uart1-0 {
219 atmel,pins = 232 atmel,pins =
220 <3 16 0x3 0x0 /* PC16 periph C */ 233 <2 16 0x3 0x0 /* PC16 periph C */
221 3 17 0x3 0x1>; /* PC17 periph C with pullup */ 234 2 17 0x3 0x1>; /* PC17 periph C with pullup */
222 }; 235 };
223 }; 236 };
224 237
@@ -247,14 +260,14 @@
247 260
248 pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 { 261 pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
249 atmel,pins = 262 atmel,pins =
250 <1 8 0x1 0x0 /* PA8 periph A */ 263 <1 8 0x1 0x0 /* PB8 periph A */
251 1 11 0x1 0x0 /* PA11 periph A */ 264 1 11 0x1 0x0 /* PB11 periph A */
252 1 12 0x1 0x0 /* PA12 periph A */ 265 1 12 0x1 0x0 /* PB12 periph A */
253 1 13 0x1 0x0 /* PA13 periph A */ 266 1 13 0x1 0x0 /* PB13 periph A */
254 1 14 0x1 0x0 /* PA14 periph A */ 267 1 14 0x1 0x0 /* PB14 periph A */
255 1 15 0x1 0x0 /* PA15 periph A */ 268 1 15 0x1 0x0 /* PB15 periph A */
256 1 16 0x1 0x0 /* PA16 periph A */ 269 1 16 0x1 0x0 /* PB16 periph A */
257 1 17 0x1 0x0>; /* PA17 periph A */ 270 1 17 0x1 0x0>; /* PB17 periph A */
258 }; 271 };
259 }; 272 };
260 273
@@ -290,6 +303,22 @@
290 }; 303 };
291 }; 304 };
292 305
306 ssc0 {
307 pinctrl_ssc0_tx: ssc0_tx-0 {
308 atmel,pins =
309 <0 24 0x2 0x0 /* PA24 periph B */
310 0 25 0x2 0x0 /* PA25 periph B */
311 0 26 0x2 0x0>; /* PA26 periph B */
312 };
313
314 pinctrl_ssc0_rx: ssc0_rx-0 {
315 atmel,pins =
316 <0 27 0x2 0x0 /* PA27 periph B */
317 0 28 0x2 0x0 /* PA28 periph B */
318 0 29 0x2 0x0>; /* PA29 periph B */
319 };
320 };
321
293 pioA: gpio@fffff400 { 322 pioA: gpio@fffff400 {
294 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 323 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
295 reg = <0xfffff400 0x200>; 324 reg = <0xfffff400 0x200>;
@@ -333,6 +362,15 @@
333 }; 362 };
334 }; 363 };
335 364
365 ssc0: ssc@f0010000 {
366 compatible = "atmel,at91sam9g45-ssc";
367 reg = <0xf0010000 0x4000>;
368 interrupts = <28 4 5>;
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
371 status = "disabled";
372 };
373
336 mmc0: mmc@f0008000 { 374 mmc0: mmc@f0008000 {
337 compatible = "atmel,hsmci"; 375 compatible = "atmel,hsmci";
338 reg = <0xf0008000 0x600>; 376 reg = <0xf0008000 0x600>;
diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi
index fddd17417433..46c098017036 100644
--- a/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/arch/arm/boot/dts/cros5250-common.dtsi
@@ -96,8 +96,8 @@
96 fifo-depth = <0x80>; 96 fifo-depth = <0x80>;
97 card-detect-delay = <200>; 97 card-detect-delay = <200>;
98 samsung,dw-mshc-ciu-div = <3>; 98 samsung,dw-mshc-ciu-div = <3>;
99 samsung,dw-mshc-sdr-timing = <2 3 3>; 99 samsung,dw-mshc-sdr-timing = <2 3>;
100 samsung,dw-mshc-ddr-timing = <1 2 3>; 100 samsung,dw-mshc-ddr-timing = <1 2>;
101 101
102 slot@0 { 102 slot@0 {
103 reg = <0>; 103 reg = <0>;
@@ -120,8 +120,8 @@
120 fifo-depth = <0x80>; 120 fifo-depth = <0x80>;
121 card-detect-delay = <200>; 121 card-detect-delay = <200>;
122 samsung,dw-mshc-ciu-div = <3>; 122 samsung,dw-mshc-ciu-div = <3>;
123 samsung,dw-mshc-sdr-timing = <2 3 3>; 123 samsung,dw-mshc-sdr-timing = <2 3>;
124 samsung,dw-mshc-ddr-timing = <1 2 3>; 124 samsung,dw-mshc-ddr-timing = <1 2>;
125 125
126 slot@0 { 126 slot@0 {
127 reg = <0>; 127 reg = <0>;
@@ -141,8 +141,8 @@
141 fifo-depth = <0x80>; 141 fifo-depth = <0x80>;
142 card-detect-delay = <200>; 142 card-detect-delay = <200>;
143 samsung,dw-mshc-ciu-div = <3>; 143 samsung,dw-mshc-ciu-div = <3>;
144 samsung,dw-mshc-sdr-timing = <2 3 3>; 144 samsung,dw-mshc-sdr-timing = <2 3>;
145 samsung,dw-mshc-ddr-timing = <1 2 3>; 145 samsung,dw-mshc-ddr-timing = <1 2>;
146 146
147 slot@0 { 147 slot@0 {
148 reg = <0>; 148 reg = <0>;
diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
index fed7d3f9f431..cdee96fca6e2 100644
--- a/arch/arm/boot/dts/dove-cubox.dts
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -26,10 +26,15 @@
26}; 26};
27 27
28&uart0 { status = "okay"; }; 28&uart0 { status = "okay"; };
29&sdio0 { status = "okay"; };
30&sata0 { status = "okay"; }; 29&sata0 { status = "okay"; };
31&i2c0 { status = "okay"; }; 30&i2c0 { status = "okay"; };
32 31
32&sdio0 {
33 status = "okay";
34 /* sdio0 card detect is connected to wrong pin on CuBox */
35 cd-gpios = <&gpio0 12 1>;
36};
37
33&spi0 { 38&spi0 {
34 status = "okay"; 39 status = "okay";
35 40
@@ -42,9 +47,14 @@
42}; 47};
43 48
44&pinctrl { 49&pinctrl {
45 pinctrl-0 = <&pmx_gpio_18>; 50 pinctrl-0 = <&pmx_gpio_12 &pmx_gpio_18>;
46 pinctrl-names = "default"; 51 pinctrl-names = "default";
47 52
53 pmx_gpio_12: pmx-gpio-12 {
54 marvell,pins = "mpp12";
55 marvell,function = "gpio";
56 };
57
48 pmx_gpio_18: pmx-gpio-18 { 58 pmx_gpio_18: pmx-gpio-18 {
49 marvell,pins = "mpp18"; 59 marvell,pins = "mpp18";
50 marvell,function = "gpio"; 60 marvell,function = "gpio";
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 942d5761ca97..e05b18f3c33d 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -115,8 +115,8 @@
115 fifo-depth = <0x80>; 115 fifo-depth = <0x80>;
116 card-detect-delay = <200>; 116 card-detect-delay = <200>;
117 samsung,dw-mshc-ciu-div = <3>; 117 samsung,dw-mshc-ciu-div = <3>;
118 samsung,dw-mshc-sdr-timing = <2 3 3>; 118 samsung,dw-mshc-sdr-timing = <2 3>;
119 samsung,dw-mshc-ddr-timing = <1 2 3>; 119 samsung,dw-mshc-ddr-timing = <1 2>;
120 120
121 slot@0 { 121 slot@0 {
122 reg = <0>; 122 reg = <0>;
@@ -139,8 +139,8 @@
139 fifo-depth = <0x80>; 139 fifo-depth = <0x80>;
140 card-detect-delay = <200>; 140 card-detect-delay = <200>;
141 samsung,dw-mshc-ciu-div = <3>; 141 samsung,dw-mshc-ciu-div = <3>;
142 samsung,dw-mshc-sdr-timing = <2 3 3>; 142 samsung,dw-mshc-sdr-timing = <2 3>;
143 samsung,dw-mshc-ddr-timing = <1 2 3>; 143 samsung,dw-mshc-ddr-timing = <1 2>;
144 144
145 slot@0 { 145 slot@0 {
146 reg = <0>; 146 reg = <0>;
diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
index 9bc6785ad228..77d21abfcdf7 100644
--- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
@@ -1,4 +1,5 @@
1/include/ "kirkwood.dtsi" 1/include/ "kirkwood.dtsi"
2/include/ "kirkwood-6281.dtsi"
2 3
3/ { 4/ {
4 chosen { 5 chosen {
@@ -6,6 +7,21 @@
6 }; 7 };
7 8
8 ocp@f1000000 { 9 ocp@f1000000 {
10 pinctrl: pinctrl@10000 {
11 pinctrl-0 = < &pmx_spi &pmx_twsi0 &pmx_uart0
12 &pmx_ns2_sata0 &pmx_ns2_sata1>;
13 pinctrl-names = "default";
14
15 pmx_ns2_sata0: pmx-ns2-sata0 {
16 marvell,pins = "mpp21";
17 marvell,function = "sata0";
18 };
19 pmx_ns2_sata1: pmx-ns2-sata1 {
20 marvell,pins = "mpp20";
21 marvell,function = "sata1";
22 };
23 };
24
9 serial@12000 { 25 serial@12000 {
10 clock-frequency = <166666667>; 26 clock-frequency = <166666667>;
11 status = "okay"; 27 status = "okay";
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 110d6cbb795b..d6ab442b7011 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -36,6 +36,7 @@
36 reg = <0x10100 0x40>; 36 reg = <0x10100 0x40>;
37 ngpios = <32>; 37 ngpios = <32>;
38 interrupt-controller; 38 interrupt-controller;
39 #interrupt-cells = <2>;
39 interrupts = <35>, <36>, <37>, <38>; 40 interrupts = <35>, <36>, <37>, <38>;
40 }; 41 };
41 42
@@ -46,6 +47,7 @@
46 reg = <0x10140 0x40>; 47 reg = <0x10140 0x40>;
47 ngpios = <18>; 48 ngpios = <18>;
48 interrupt-controller; 49 interrupt-controller;
50 #interrupt-cells = <2>;
49 interrupts = <39>, <40>, <41>; 51 interrupts = <39>, <40>, <41>;
50 }; 52 };
51 53
diff --git a/arch/arm/boot/dts/kizbox.dts b/arch/arm/boot/dts/kizbox.dts
index e8814fe0e277..b4dc3ed9a3ec 100644
--- a/arch/arm/boot/dts/kizbox.dts
+++ b/arch/arm/boot/dts/kizbox.dts
@@ -48,6 +48,8 @@
48 48
49 macb0: ethernet@fffc4000 { 49 macb0: ethernet@fffc4000 {
50 phy-mode = "mii"; 50 phy-mode = "mii";
51 pinctrl-0 = <&pinctrl_macb_rmii
52 &pinctrl_macb_rmii_mii_alt>;
51 status = "okay"; 53 status = "okay";
52 }; 54 };
53 55
diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi
index 8bbc2bfef221..8b36abea9f2e 100644
--- a/arch/arm/boot/dts/sunxi.dtsi
+++ b/arch/arm/boot/dts/sunxi.dtsi
@@ -60,19 +60,21 @@
60 }; 60 };
61 61
62 uart0: uart@01c28000 { 62 uart0: uart@01c28000 {
63 compatible = "ns8250"; 63 compatible = "snps,dw-apb-uart";
64 reg = <0x01c28000 0x400>; 64 reg = <0x01c28000 0x400>;
65 interrupts = <1>; 65 interrupts = <1>;
66 reg-shift = <2>; 66 reg-shift = <2>;
67 reg-io-width = <4>;
67 clock-frequency = <24000000>; 68 clock-frequency = <24000000>;
68 status = "disabled"; 69 status = "disabled";
69 }; 70 };
70 71
71 uart1: uart@01c28400 { 72 uart1: uart@01c28400 {
72 compatible = "ns8250"; 73 compatible = "snps,dw-apb-uart";
73 reg = <0x01c28400 0x400>; 74 reg = <0x01c28400 0x400>;
74 interrupts = <2>; 75 interrupts = <2>;
75 reg-shift = <2>; 76 reg-shift = <2>;
77 reg-io-width = <4>;
76 clock-frequency = <24000000>; 78 clock-frequency = <24000000>;
77 status = "disabled"; 79 status = "disabled";
78 }; 80 };
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index 1fc405a9ecfb..cf8071ad22d5 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -45,7 +45,6 @@
45 reg = <1>; 45 reg = <1>;
46 }; 46 };
47 47
48/* A7s disabled till big.LITTLE patches are available...
49 cpu2: cpu@2 { 48 cpu2: cpu@2 {
50 device_type = "cpu"; 49 device_type = "cpu";
51 compatible = "arm,cortex-a7"; 50 compatible = "arm,cortex-a7";
@@ -63,7 +62,6 @@
63 compatible = "arm,cortex-a7"; 62 compatible = "arm,cortex-a7";
64 reg = <0x102>; 63 reg = <0x102>;
65 }; 64 };
66*/
67 }; 65 };
68 66
69 memory@80000000 { 67 memory@80000000 {
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index b175577d7abb..1ea959019fcd 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -19,6 +19,7 @@ CONFIG_SOC_AT91SAM9260=y
19CONFIG_SOC_AT91SAM9263=y 19CONFIG_SOC_AT91SAM9263=y
20CONFIG_SOC_AT91SAM9G45=y 20CONFIG_SOC_AT91SAM9G45=y
21CONFIG_SOC_AT91SAM9X5=y 21CONFIG_SOC_AT91SAM9X5=y
22CONFIG_SOC_AT91SAM9N12=y
22CONFIG_MACH_AT91SAM_DT=y 23CONFIG_MACH_AT91SAM_DT=y
23CONFIG_AT91_PROGRAMMABLE_CLOCKS=y 24CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
24CONFIG_AT91_TIMER_HZ=128 25CONFIG_AT91_TIMER_HZ=128
@@ -31,7 +32,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
31CONFIG_ZBOOT_ROM_BSS=0x0 32CONFIG_ZBOOT_ROM_BSS=0x0
32CONFIG_ARM_APPENDED_DTB=y 33CONFIG_ARM_APPENDED_DTB=y
33CONFIG_ARM_ATAG_DTB_COMPAT=y 34CONFIG_ARM_ATAG_DTB_COMPAT=y
34CONFIG_CMDLINE="mem=128M console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw" 35CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
35CONFIG_KEXEC=y 36CONFIG_KEXEC=y
36CONFIG_AUTO_ZRELADDR=y 37CONFIG_AUTO_ZRELADDR=y
37# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set 38# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index d40229d9a1c9..7ade91d8cc6f 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -1,13 +1,115 @@
1#ifndef __ASMARM_ARCH_TIMER_H 1#ifndef __ASMARM_ARCH_TIMER_H
2#define __ASMARM_ARCH_TIMER_H 2#define __ASMARM_ARCH_TIMER_H
3 3
4#include <asm/barrier.h>
4#include <asm/errno.h> 5#include <asm/errno.h>
5#include <linux/clocksource.h> 6#include <linux/clocksource.h>
7#include <linux/init.h>
8#include <linux/types.h>
9
10#include <clocksource/arm_arch_timer.h>
6 11
7#ifdef CONFIG_ARM_ARCH_TIMER 12#ifdef CONFIG_ARM_ARCH_TIMER
8int arch_timer_of_register(void); 13int arch_timer_of_register(void);
9int arch_timer_sched_clock_init(void); 14int arch_timer_sched_clock_init(void);
10struct timecounter *arch_timer_get_timecounter(void); 15
16/*
17 * These register accessors are marked inline so the compiler can
18 * nicely work out which register we want, and chuck away the rest of
19 * the code. At least it does so with a recent GCC (4.6.3).
20 */
21static inline void arch_timer_reg_write(const int access, const int reg, u32 val)
22{
23 if (access == ARCH_TIMER_PHYS_ACCESS) {
24 switch (reg) {
25 case ARCH_TIMER_REG_CTRL:
26 asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
27 break;
28 case ARCH_TIMER_REG_TVAL:
29 asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
30 break;
31 }
32 }
33
34 if (access == ARCH_TIMER_VIRT_ACCESS) {
35 switch (reg) {
36 case ARCH_TIMER_REG_CTRL:
37 asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val));
38 break;
39 case ARCH_TIMER_REG_TVAL:
40 asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val));
41 break;
42 }
43 }
44
45 isb();
46}
47
48static inline u32 arch_timer_reg_read(const int access, const int reg)
49{
50 u32 val = 0;
51
52 if (access == ARCH_TIMER_PHYS_ACCESS) {
53 switch (reg) {
54 case ARCH_TIMER_REG_CTRL:
55 asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
56 break;
57 case ARCH_TIMER_REG_TVAL:
58 asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
59 break;
60 }
61 }
62
63 if (access == ARCH_TIMER_VIRT_ACCESS) {
64 switch (reg) {
65 case ARCH_TIMER_REG_CTRL:
66 asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
67 break;
68 case ARCH_TIMER_REG_TVAL:
69 asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val));
70 break;
71 }
72 }
73
74 return val;
75}
76
77static inline u32 arch_timer_get_cntfrq(void)
78{
79 u32 val;
80 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
81 return val;
82}
83
84static inline u64 arch_counter_get_cntpct(void)
85{
86 u64 cval;
87
88 isb();
89 asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
90 return cval;
91}
92
93static inline u64 arch_counter_get_cntvct(void)
94{
95 u64 cval;
96
97 isb();
98 asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval));
99 return cval;
100}
101
102static inline void __cpuinit arch_counter_set_user_access(void)
103{
104 u32 cntkctl;
105
106 asm volatile("mrc p15, 0, %0, c14, c1, 0" : "=r" (cntkctl));
107
108 /* disable user access to everything */
109 cntkctl &= ~((3 << 8) | (7 << 0));
110
111 asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
112}
11#else 113#else
12static inline int arch_timer_of_register(void) 114static inline int arch_timer_of_register(void)
13{ 115{
@@ -18,11 +120,6 @@ static inline int arch_timer_sched_clock_init(void)
18{ 120{
19 return -ENXIO; 121 return -ENXIO;
20} 122}
21
22static inline struct timecounter *arch_timer_get_timecounter(void)
23{
24 return NULL;
25}
26#endif 123#endif
27 124
28#endif 125#endif
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index c8ef20747ee7..36ebcf4b516f 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -9,516 +9,52 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/kernel.h> 12#include <linux/types.h>
13#include <linux/delay.h>
14#include <linux/device.h>
15#include <linux/smp.h>
16#include <linux/cpu.h>
17#include <linux/jiffies.h>
18#include <linux/clockchips.h>
19#include <linux/interrupt.h>
20#include <linux/of_irq.h>
21#include <linux/io.h>
22 13
23#include <asm/cputype.h>
24#include <asm/delay.h> 14#include <asm/delay.h>
25#include <asm/localtimer.h>
26#include <asm/arch_timer.h>
27#include <asm/system_info.h>
28#include <asm/sched_clock.h> 15#include <asm/sched_clock.h>
29 16
30static unsigned long arch_timer_rate; 17#include <clocksource/arm_arch_timer.h>
31 18
32enum ppi_nr { 19static unsigned long arch_timer_read_counter_long(void)
33 PHYS_SECURE_PPI,
34 PHYS_NONSECURE_PPI,
35 VIRT_PPI,
36 HYP_PPI,
37 MAX_TIMER_PPI
38};
39
40static int arch_timer_ppi[MAX_TIMER_PPI];
41
42static struct clock_event_device __percpu **arch_timer_evt;
43static struct delay_timer arch_delay_timer;
44
45static bool arch_timer_use_virtual = true;
46
47/*
48 * Architected system timer support.
49 */
50
51#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
52#define ARCH_TIMER_CTRL_IT_MASK (1 << 1)
53#define ARCH_TIMER_CTRL_IT_STAT (1 << 2)
54
55#define ARCH_TIMER_REG_CTRL 0
56#define ARCH_TIMER_REG_FREQ 1
57#define ARCH_TIMER_REG_TVAL 2
58
59#define ARCH_TIMER_PHYS_ACCESS 0
60#define ARCH_TIMER_VIRT_ACCESS 1
61
62/*
63 * These register accessors are marked inline so the compiler can
64 * nicely work out which register we want, and chuck away the rest of
65 * the code. At least it does so with a recent GCC (4.6.3).
66 */
67static inline void arch_timer_reg_write(const int access, const int reg, u32 val)
68{
69 if (access == ARCH_TIMER_PHYS_ACCESS) {
70 switch (reg) {
71 case ARCH_TIMER_REG_CTRL:
72 asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
73 break;
74 case ARCH_TIMER_REG_TVAL:
75 asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
76 break;
77 }
78 }
79
80 if (access == ARCH_TIMER_VIRT_ACCESS) {
81 switch (reg) {
82 case ARCH_TIMER_REG_CTRL:
83 asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val));
84 break;
85 case ARCH_TIMER_REG_TVAL:
86 asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val));
87 break;
88 }
89 }
90
91 isb();
92}
93
94static inline u32 arch_timer_reg_read(const int access, const int reg)
95{
96 u32 val = 0;
97
98 if (access == ARCH_TIMER_PHYS_ACCESS) {
99 switch (reg) {
100 case ARCH_TIMER_REG_CTRL:
101 asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
102 break;
103 case ARCH_TIMER_REG_TVAL:
104 asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
105 break;
106 case ARCH_TIMER_REG_FREQ:
107 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
108 break;
109 }
110 }
111
112 if (access == ARCH_TIMER_VIRT_ACCESS) {
113 switch (reg) {
114 case ARCH_TIMER_REG_CTRL:
115 asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
116 break;
117 case ARCH_TIMER_REG_TVAL:
118 asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val));
119 break;
120 }
121 }
122
123 return val;
124}
125
126static inline cycle_t arch_timer_counter_read(const int access)
127{
128 cycle_t cval = 0;
129
130 if (access == ARCH_TIMER_PHYS_ACCESS)
131 asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
132
133 if (access == ARCH_TIMER_VIRT_ACCESS)
134 asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval));
135
136 return cval;
137}
138
139static inline cycle_t arch_counter_get_cntpct(void)
140{
141 return arch_timer_counter_read(ARCH_TIMER_PHYS_ACCESS);
142}
143
144static inline cycle_t arch_counter_get_cntvct(void)
145{
146 return arch_timer_counter_read(ARCH_TIMER_VIRT_ACCESS);
147}
148
149static irqreturn_t inline timer_handler(const int access,
150 struct clock_event_device *evt)
151{
152 unsigned long ctrl;
153 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
154 if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
155 ctrl |= ARCH_TIMER_CTRL_IT_MASK;
156 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
157 evt->event_handler(evt);
158 return IRQ_HANDLED;
159 }
160
161 return IRQ_NONE;
162}
163
164static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
165{
166 struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
167
168 return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
169}
170
171static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
172{
173 struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
174
175 return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
176}
177
178static inline void timer_set_mode(const int access, int mode)
179{
180 unsigned long ctrl;
181 switch (mode) {
182 case CLOCK_EVT_MODE_UNUSED:
183 case CLOCK_EVT_MODE_SHUTDOWN:
184 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
185 ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
186 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
187 break;
188 default:
189 break;
190 }
191}
192
193static void arch_timer_set_mode_virt(enum clock_event_mode mode,
194 struct clock_event_device *clk)
195{
196 timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode);
197}
198
199static void arch_timer_set_mode_phys(enum clock_event_mode mode,
200 struct clock_event_device *clk)
201{
202 timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode);
203}
204
205static inline void set_next_event(const int access, unsigned long evt)
206{
207 unsigned long ctrl;
208 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
209 ctrl |= ARCH_TIMER_CTRL_ENABLE;
210 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
211 arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt);
212 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
213}
214
215static int arch_timer_set_next_event_virt(unsigned long evt,
216 struct clock_event_device *unused)
217{
218 set_next_event(ARCH_TIMER_VIRT_ACCESS, evt);
219 return 0;
220}
221
222static int arch_timer_set_next_event_phys(unsigned long evt,
223 struct clock_event_device *unused)
224{
225 set_next_event(ARCH_TIMER_PHYS_ACCESS, evt);
226 return 0;
227}
228
229static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
230{
231 clk->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP;
232 clk->name = "arch_sys_timer";
233 clk->rating = 450;
234 if (arch_timer_use_virtual) {
235 clk->irq = arch_timer_ppi[VIRT_PPI];
236 clk->set_mode = arch_timer_set_mode_virt;
237 clk->set_next_event = arch_timer_set_next_event_virt;
238 } else {
239 clk->irq = arch_timer_ppi[PHYS_SECURE_PPI];
240 clk->set_mode = arch_timer_set_mode_phys;
241 clk->set_next_event = arch_timer_set_next_event_phys;
242 }
243
244 clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, NULL);
245
246 clockevents_config_and_register(clk, arch_timer_rate,
247 0xf, 0x7fffffff);
248
249 *__this_cpu_ptr(arch_timer_evt) = clk;
250
251 if (arch_timer_use_virtual)
252 enable_percpu_irq(arch_timer_ppi[VIRT_PPI], 0);
253 else {
254 enable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], 0);
255 if (arch_timer_ppi[PHYS_NONSECURE_PPI])
256 enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
257 }
258
259 return 0;
260}
261
262/* Is the optional system timer available? */
263static int local_timer_is_architected(void)
264{
265 return (cpu_architecture() >= CPU_ARCH_ARMv7) &&
266 ((read_cpuid_ext(CPUID_EXT_PFR1) >> 16) & 0xf) == 1;
267}
268
269static int arch_timer_available(void)
270{
271 unsigned long freq;
272
273 if (!local_timer_is_architected())
274 return -ENXIO;
275
276 if (arch_timer_rate == 0) {
277 freq = arch_timer_reg_read(ARCH_TIMER_PHYS_ACCESS,
278 ARCH_TIMER_REG_FREQ);
279
280 /* Check the timer frequency. */
281 if (freq == 0) {
282 pr_warn("Architected timer frequency not available\n");
283 return -EINVAL;
284 }
285
286 arch_timer_rate = freq;
287 }
288
289 pr_info_once("Architected local timer running at %lu.%02luMHz (%s).\n",
290 arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100,
291 arch_timer_use_virtual ? "virt" : "phys");
292 return 0;
293}
294
295static u32 notrace arch_counter_get_cntpct32(void)
296{
297 cycle_t cnt = arch_counter_get_cntpct();
298
299 /*
300 * The sched_clock infrastructure only knows about counters
301 * with at most 32bits. Forget about the upper 24 bits for the
302 * time being...
303 */
304 return (u32)cnt;
305}
306
307static u32 notrace arch_counter_get_cntvct32(void)
308{
309 cycle_t cnt = arch_counter_get_cntvct();
310
311 /*
312 * The sched_clock infrastructure only knows about counters
313 * with at most 32bits. Forget about the upper 24 bits for the
314 * time being...
315 */
316 return (u32)cnt;
317}
318
319static cycle_t arch_counter_read(struct clocksource *cs)
320{
321 /*
322 * Always use the physical counter for the clocksource.
323 * CNTHCTL.PL1PCTEN must be set to 1.
324 */
325 return arch_counter_get_cntpct();
326}
327
328static unsigned long arch_timer_read_current_timer(void)
329{ 20{
330 return arch_counter_get_cntpct(); 21 return arch_timer_read_counter();
331} 22}
332 23
333static cycle_t arch_counter_read_cc(const struct cyclecounter *cc) 24static u32 arch_timer_read_counter_u32(void)
334{ 25{
335 /* 26 return arch_timer_read_counter();
336 * Always use the physical counter for the clocksource.
337 * CNTHCTL.PL1PCTEN must be set to 1.
338 */
339 return arch_counter_get_cntpct();
340} 27}
341 28
342static struct clocksource clocksource_counter = { 29static struct delay_timer arch_delay_timer;
343 .name = "arch_sys_counter",
344 .rating = 400,
345 .read = arch_counter_read,
346 .mask = CLOCKSOURCE_MASK(56),
347 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
348};
349
350static struct cyclecounter cyclecounter = {
351 .read = arch_counter_read_cc,
352 .mask = CLOCKSOURCE_MASK(56),
353};
354
355static struct timecounter timecounter;
356
357struct timecounter *arch_timer_get_timecounter(void)
358{
359 return &timecounter;
360}
361
362static void __cpuinit arch_timer_stop(struct clock_event_device *clk)
363{
364 pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
365 clk->irq, smp_processor_id());
366
367 if (arch_timer_use_virtual)
368 disable_percpu_irq(arch_timer_ppi[VIRT_PPI]);
369 else {
370 disable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI]);
371 if (arch_timer_ppi[PHYS_NONSECURE_PPI])
372 disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]);
373 }
374
375 clk->set_mode(CLOCK_EVT_MODE_UNUSED, clk);
376}
377
378static struct local_timer_ops arch_timer_ops __cpuinitdata = {
379 .setup = arch_timer_setup,
380 .stop = arch_timer_stop,
381};
382
383static struct clock_event_device arch_timer_global_evt;
384 30
385static int __init arch_timer_register(void) 31static void __init arch_timer_delay_timer_register(void)
386{ 32{
387 int err;
388 int ppi;
389
390 err = arch_timer_available();
391 if (err)
392 goto out;
393
394 arch_timer_evt = alloc_percpu(struct clock_event_device *);
395 if (!arch_timer_evt) {
396 err = -ENOMEM;
397 goto out;
398 }
399
400 clocksource_register_hz(&clocksource_counter, arch_timer_rate);
401 cyclecounter.mult = clocksource_counter.mult;
402 cyclecounter.shift = clocksource_counter.shift;
403 timecounter_init(&timecounter, &cyclecounter,
404 arch_counter_get_cntpct());
405
406 if (arch_timer_use_virtual) {
407 ppi = arch_timer_ppi[VIRT_PPI];
408 err = request_percpu_irq(ppi, arch_timer_handler_virt,
409 "arch_timer", arch_timer_evt);
410 } else {
411 ppi = arch_timer_ppi[PHYS_SECURE_PPI];
412 err = request_percpu_irq(ppi, arch_timer_handler_phys,
413 "arch_timer", arch_timer_evt);
414 if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) {
415 ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
416 err = request_percpu_irq(ppi, arch_timer_handler_phys,
417 "arch_timer", arch_timer_evt);
418 if (err)
419 free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
420 arch_timer_evt);
421 }
422 }
423
424 if (err) {
425 pr_err("arch_timer: can't register interrupt %d (%d)\n",
426 ppi, err);
427 goto out_free;
428 }
429
430 err = local_timer_register(&arch_timer_ops);
431 if (err) {
432 /*
433 * We couldn't register as a local timer (could be
434 * because we're on a UP platform, or because some
435 * other local timer is already present...). Try as a
436 * global timer instead.
437 */
438 arch_timer_global_evt.cpumask = cpumask_of(0);
439 err = arch_timer_setup(&arch_timer_global_evt);
440 }
441 if (err)
442 goto out_free_irq;
443
444 /* Use the architected timer for the delay loop. */ 33 /* Use the architected timer for the delay loop. */
445 arch_delay_timer.read_current_timer = &arch_timer_read_current_timer; 34 arch_delay_timer.read_current_timer = arch_timer_read_counter_long;
446 arch_delay_timer.freq = arch_timer_rate; 35 arch_delay_timer.freq = arch_timer_get_rate();
447 register_current_timer_delay(&arch_delay_timer); 36 register_current_timer_delay(&arch_delay_timer);
448 return 0;
449
450out_free_irq:
451 if (arch_timer_use_virtual)
452 free_percpu_irq(arch_timer_ppi[VIRT_PPI], arch_timer_evt);
453 else {
454 free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
455 arch_timer_evt);
456 if (arch_timer_ppi[PHYS_NONSECURE_PPI])
457 free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI],
458 arch_timer_evt);
459 }
460
461out_free:
462 free_percpu(arch_timer_evt);
463out:
464 return err;
465} 37}
466 38
467static const struct of_device_id arch_timer_of_match[] __initconst = {
468 { .compatible = "arm,armv7-timer", },
469 {},
470};
471
472int __init arch_timer_of_register(void) 39int __init arch_timer_of_register(void)
473{ 40{
474 struct device_node *np; 41 int ret;
475 u32 freq;
476 int i;
477
478 np = of_find_matching_node(NULL, arch_timer_of_match);
479 if (!np) {
480 pr_err("arch_timer: can't find DT node\n");
481 return -ENODEV;
482 }
483
484 /* Try to determine the frequency from the device tree or CNTFRQ */
485 if (!of_property_read_u32(np, "clock-frequency", &freq))
486 arch_timer_rate = freq;
487
488 for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
489 arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
490 42
491 /* 43 ret = arch_timer_init();
492 * If no interrupt provided for virtual timer, we'll have to 44 if (ret)
493 * stick to the physical timer. It'd better be accessible... 45 return ret;
494 */
495 if (!arch_timer_ppi[VIRT_PPI]) {
496 arch_timer_use_virtual = false;
497 46
498 if (!arch_timer_ppi[PHYS_SECURE_PPI] || 47 arch_timer_delay_timer_register();
499 !arch_timer_ppi[PHYS_NONSECURE_PPI]) {
500 pr_warn("arch_timer: No interrupt available, giving up\n");
501 return -EINVAL;
502 }
503 }
504 48
505 return arch_timer_register(); 49 return 0;
506} 50}
507 51
508int __init arch_timer_sched_clock_init(void) 52int __init arch_timer_sched_clock_init(void)
509{ 53{
510 u32 (*cnt32)(void); 54 if (arch_timer_get_rate() == 0)
511 int err; 55 return -ENXIO;
512
513 err = arch_timer_available();
514 if (err)
515 return err;
516
517 if (arch_timer_use_virtual)
518 cnt32 = arch_counter_get_cntvct32;
519 else
520 cnt32 = arch_counter_get_cntpct32;
521 56
522 setup_sched_clock(cnt32, 32, arch_timer_rate); 57 setup_sched_clock(arch_timer_read_counter_u32,
58 32, arch_timer_get_rate());
523 return 0; 59 return 0;
524} 60}
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
index 6809200c31fb..14f7c3b14632 100644
--- a/arch/arm/kernel/debug.S
+++ b/arch/arm/kernel/debug.S
@@ -100,12 +100,14 @@ ENTRY(printch)
100 b 1b 100 b 1b
101ENDPROC(printch) 101ENDPROC(printch)
102 102
103#ifdef CONFIG_MMU
103ENTRY(debug_ll_addr) 104ENTRY(debug_ll_addr)
104 addruart r2, r3, ip 105 addruart r2, r3, ip
105 str r2, [r0] 106 str r2, [r0]
106 str r3, [r1] 107 str r3, [r1]
107 mov pc, lr 108 mov pc, lr
108ENDPROC(debug_ll_addr) 109ENDPROC(debug_ll_addr)
110#endif
109 111
110#else 112#else
111 113
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 4eee351f4668..486a15ae9011 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -246,6 +246,7 @@ __create_page_tables:
246 246
247 /* 247 /*
248 * Then map boot params address in r2 if specified. 248 * Then map boot params address in r2 if specified.
249 * We map 2 sections in case the ATAGs/DTB crosses a section boundary.
249 */ 250 */
250 mov r0, r2, lsr #SECTION_SHIFT 251 mov r0, r2, lsr #SECTION_SHIFT
251 movs r0, r0, lsl #SECTION_SHIFT 252 movs r0, r0, lsl #SECTION_SHIFT
@@ -253,6 +254,8 @@ __create_page_tables:
253 addne r3, r3, #PAGE_OFFSET 254 addne r3, r3, #PAGE_OFFSET
254 addne r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER) 255 addne r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER)
255 orrne r6, r7, r0 256 orrne r6, r7, r0
257 strne r6, [r3], #1 << PMD_ORDER
258 addne r6, r6, #1 << SECTION_SHIFT
256 strne r6, [r3] 259 strne r6, [r3]
257 260
258#ifdef CONFIG_DEBUG_LL 261#ifdef CONFIG_DEBUG_LL
@@ -331,7 +334,7 @@ ENTRY(secondary_startup)
331 * as it has already been validated by the primary processor. 334 * as it has already been validated by the primary processor.
332 */ 335 */
333#ifdef CONFIG_ARM_VIRT_EXT 336#ifdef CONFIG_ARM_VIRT_EXT
334 bl __hyp_stub_install 337 bl __hyp_stub_install_secondary
335#endif 338#endif
336 safe_svcmode_maskall r9 339 safe_svcmode_maskall r9
337 340
diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S
index 65b2417aebce..1315c4ccfa56 100644
--- a/arch/arm/kernel/hyp-stub.S
+++ b/arch/arm/kernel/hyp-stub.S
@@ -99,7 +99,7 @@ ENTRY(__hyp_stub_install_secondary)
99 * immediately. 99 * immediately.
100 */ 100 */
101 compare_cpu_mode_with_primary r4, r5, r6, r7 101 compare_cpu_mode_with_primary r4, r5, r6, r7
102 bxne lr 102 movne pc, lr
103 103
104 /* 104 /*
105 * Once we have given up on one CPU, we do not try to install the 105 * Once we have given up on one CPU, we do not try to install the
@@ -111,7 +111,7 @@ ENTRY(__hyp_stub_install_secondary)
111 */ 111 */
112 112
113 cmp r4, #HYP_MODE 113 cmp r4, #HYP_MODE
114 bxne lr @ give up if the CPU is not in HYP mode 114 movne pc, lr @ give up if the CPU is not in HYP mode
115 115
116/* 116/*
117 * Configure HSCTLR to set correct exception endianness/instruction set 117 * Configure HSCTLR to set correct exception endianness/instruction set
@@ -120,7 +120,8 @@ ENTRY(__hyp_stub_install_secondary)
120 * Eventually, CPU-specific code might be needed -- assume not for now 120 * Eventually, CPU-specific code might be needed -- assume not for now
121 * 121 *
122 * This code relies on the "eret" instruction to synchronize the 122 * This code relies on the "eret" instruction to synchronize the
123 * various coprocessor accesses. 123 * various coprocessor accesses. This is done when we switch to SVC
124 * (see safe_svcmode_maskall).
124 */ 125 */
125 @ Now install the hypervisor stub: 126 @ Now install the hypervisor stub:
126 adr r7, __hyp_stub_vectors 127 adr r7, __hyp_stub_vectors
@@ -155,14 +156,7 @@ THUMB( orr r7, #(1 << 30) ) @ HSCTLR.TE
1551: 1561:
156#endif 157#endif
157 158
158 bic r7, r4, #MODE_MASK 159 bx lr @ The boot CPU mode is left in r4.
159 orr r7, r7, #SVC_MODE
160THUMB( orr r7, r7, #PSR_T_BIT )
161 msr spsr_cxsf, r7 @ This is SPSR_hyp.
162
163 __MSR_ELR_HYP(14) @ msr elr_hyp, lr
164 __ERET @ return, switching to SVC mode
165 @ The boot CPU mode is left in r4.
166ENDPROC(__hyp_stub_install_secondary) 160ENDPROC(__hyp_stub_install_secondary)
167 161
168__hyp_stub_do_trap: 162__hyp_stub_do_trap:
@@ -200,7 +194,7 @@ ENDPROC(__hyp_get_vectors)
200 @ fall through 194 @ fall through
201ENTRY(__hyp_set_vectors) 195ENTRY(__hyp_set_vectors)
202 __HVC(0) 196 __HVC(0)
203 bx lr 197 mov pc, lr
204ENDPROC(__hyp_set_vectors) 198ENDPROC(__hyp_set_vectors)
205 199
206#ifndef ZIMAGE 200#ifndef ZIMAGE
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 3fc96db2a4b6..a77b0532f97e 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -476,14 +476,8 @@ u64 smp_irq_stat_cpu(unsigned int cpu)
476 */ 476 */
477static DEFINE_PER_CPU(struct clock_event_device, percpu_clockevent); 477static DEFINE_PER_CPU(struct clock_event_device, percpu_clockevent);
478 478
479static void ipi_timer(void)
480{
481 struct clock_event_device *evt = &__get_cpu_var(percpu_clockevent);
482 evt->event_handler(evt);
483}
484
485#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST 479#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
486static void smp_timer_broadcast(const struct cpumask *mask) 480void tick_broadcast(const struct cpumask *mask)
487{ 481{
488 smp_cross_call(mask, IPI_TIMER); 482 smp_cross_call(mask, IPI_TIMER);
489} 483}
@@ -531,7 +525,6 @@ static void __cpuinit percpu_timer_setup(void)
531 struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu); 525 struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
532 526
533 evt->cpumask = cpumask_of(cpu); 527 evt->cpumask = cpumask_of(cpu);
534 evt->broadcast = smp_timer_broadcast;
535 528
536 if (!lt_ops || lt_ops->setup(evt)) 529 if (!lt_ops || lt_ops->setup(evt))
537 broadcast_timer_setup(evt); 530 broadcast_timer_setup(evt);
@@ -597,11 +590,13 @@ void handle_IPI(int ipinr, struct pt_regs *regs)
597 case IPI_WAKEUP: 590 case IPI_WAKEUP:
598 break; 591 break;
599 592
593#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
600 case IPI_TIMER: 594 case IPI_TIMER:
601 irq_enter(); 595 irq_enter();
602 ipi_timer(); 596 tick_receive_broadcast();
603 irq_exit(); 597 irq_exit();
604 break; 598 break;
599#endif
605 600
606 case IPI_RESCHEDULE: 601 case IPI_RESCHEDULE:
607 scheduler_ipi(); 602 scheduler_ipi();
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 9ee866ce0478..4b678478cf95 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -105,6 +105,8 @@ static void __init soc_detect(u32 dbgu_base)
105 switch (socid) { 105 switch (socid) {
106 case ARCH_ID_AT91RM9200: 106 case ARCH_ID_AT91RM9200:
107 at91_soc_initdata.type = AT91_SOC_RM9200; 107 at91_soc_initdata.type = AT91_SOC_RM9200;
108 if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_NONE)
109 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
108 at91_boot_soc = at91rm9200_soc; 110 at91_boot_soc = at91rm9200_soc;
109 break; 111 break;
110 112
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 3e628fd7a674..0a2349dc7018 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -851,6 +851,7 @@ config SOC_IMX6Q
851 select HAVE_CAN_FLEXCAN if CAN 851 select HAVE_CAN_FLEXCAN if CAN
852 select HAVE_IMX_GPC 852 select HAVE_IMX_GPC
853 select HAVE_IMX_MMDC 853 select HAVE_IMX_MMDC
854 select HAVE_IMX_SRC
854 select HAVE_SMP 855 select HAVE_SMP
855 select MFD_SYSCON 856 select MFD_SYSCON
856 select PINCTRL 857 select PINCTRL
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index b197aa73dc4b..2c570cdaae7b 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -254,9 +254,9 @@ int __init mx25_clocks_init(void)
254 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2"); 254 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
255 clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.2"); 255 clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.2");
256 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2"); 256 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
257 clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc"); 257 clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27");
258 clk_register_clkdev(clk[usbotg_ahb], "ahb", "fsl-usb2-udc"); 258 clk_register_clkdev(clk[usbotg_ahb], "ahb", "imx-udc-mx27");
259 clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc"); 259 clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27");
260 clk_register_clkdev(clk[nfc_ipg_per], NULL, "imx25-nand.0"); 260 clk_register_clkdev(clk[nfc_ipg_per], NULL, "imx25-nand.0");
261 /* i.mx25 has the i.mx35 type cspi */ 261 /* i.mx25 has the i.mx35 type cspi */
262 clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0"); 262 clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0");
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index 4c1d1e4efc74..1ffe3b534e51 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -236,9 +236,9 @@ int __init mx27_clocks_init(unsigned long fref)
236 clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx21-fb.0"); 236 clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx21-fb.0");
237 clk_register_clkdev(clk[csi_ahb_gate], "ahb", "imx27-camera.0"); 237 clk_register_clkdev(clk[csi_ahb_gate], "ahb", "imx27-camera.0");
238 clk_register_clkdev(clk[per4_gate], "per", "imx27-camera.0"); 238 clk_register_clkdev(clk[per4_gate], "per", "imx27-camera.0");
239 clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc"); 239 clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27");
240 clk_register_clkdev(clk[usb_ipg_gate], "ipg", "fsl-usb2-udc"); 240 clk_register_clkdev(clk[usb_ipg_gate], "ipg", "imx-udc-mx27");
241 clk_register_clkdev(clk[usb_ahb_gate], "ahb", "fsl-usb2-udc"); 241 clk_register_clkdev(clk[usb_ahb_gate], "ahb", "imx-udc-mx27");
242 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0"); 242 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
243 clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.0"); 243 clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.0");
244 clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.0"); 244 clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.0");
diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c
index 8be64e0a4ace..16ccbd41dea9 100644
--- a/arch/arm/mach-imx/clk-imx31.c
+++ b/arch/arm/mach-imx/clk-imx31.c
@@ -139,9 +139,9 @@ int __init mx31_clocks_init(unsigned long fref)
139 clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.2"); 139 clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.2");
140 clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.2"); 140 clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.2");
141 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2"); 141 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
142 clk_register_clkdev(clk[usb_div_post], "per", "fsl-usb2-udc"); 142 clk_register_clkdev(clk[usb_div_post], "per", "imx-udc-mx27");
143 clk_register_clkdev(clk[usb_gate], "ahb", "fsl-usb2-udc"); 143 clk_register_clkdev(clk[usb_gate], "ahb", "imx-udc-mx27");
144 clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc"); 144 clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27");
145 clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0"); 145 clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
146 /* i.mx31 has the i.mx21 type uart */ 146 /* i.mx31 has the i.mx21 type uart */
147 clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0"); 147 clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index 66f3d65ea275..f0727e80815d 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -251,9 +251,9 @@ int __init mx35_clocks_init()
251 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2"); 251 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
252 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2"); 252 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
253 clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.2"); 253 clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.2");
254 clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc"); 254 clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27");
255 clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc"); 255 clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27");
256 clk_register_clkdev(clk[usbotg_gate], "ahb", "fsl-usb2-udc"); 256 clk_register_clkdev(clk[usbotg_gate], "ahb", "imx-udc-mx27");
257 clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0"); 257 clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
258 clk_register_clkdev(clk[nfc_div], NULL, "imx25-nand.0"); 258 clk_register_clkdev(clk[nfc_div], NULL, "imx25-nand.0");
259 clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0"); 259 clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 579023f59dc1..fb7cb841b64c 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -269,9 +269,9 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
269 clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.2"); 269 clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.2");
270 clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.2"); 270 clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.2");
271 clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.2"); 271 clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.2");
272 clk_register_clkdev(clk[usboh3_per_gate], "per", "fsl-usb2-udc"); 272 clk_register_clkdev(clk[usboh3_per_gate], "per", "imx-udc-mx51");
273 clk_register_clkdev(clk[usboh3_gate], "ipg", "fsl-usb2-udc"); 273 clk_register_clkdev(clk[usboh3_gate], "ipg", "imx-udc-mx51");
274 clk_register_clkdev(clk[usboh3_gate], "ahb", "fsl-usb2-udc"); 274 clk_register_clkdev(clk[usboh3_gate], "ahb", "imx-udc-mx51");
275 clk_register_clkdev(clk[nfc_gate], NULL, "imx51-nand"); 275 clk_register_clkdev(clk[nfc_gate], NULL, "imx51-nand");
276 clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0"); 276 clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
277 clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1"); 277 clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 7f2c10c7413a..c0c4e723b7f5 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -436,6 +436,9 @@ int __init mx6q_clocks_init(void)
436 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) 436 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
437 clk_prepare_enable(clk[clks_init_on[i]]); 437 clk_prepare_enable(clk[clks_init_on[i]]);
438 438
439 /* Set initial power mode */
440 imx6q_set_lpm(WAIT_CLOCKED);
441
439 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"); 442 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
440 base = of_iomap(np, 0); 443 base = of_iomap(np, 0);
441 WARN_ON(!base); 444 WARN_ON(!base);
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index b0164da63b0c..e17dbc50c85f 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -141,6 +141,7 @@ extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
141extern void imx6q_clock_map_io(void); 141extern void imx6q_clock_map_io(void);
142 142
143extern void imx_cpu_die(unsigned int cpu); 143extern void imx_cpu_die(unsigned int cpu);
144extern int imx_cpu_kill(unsigned int cpu);
144 145
145#ifdef CONFIG_PM 146#ifdef CONFIG_PM
146extern void imx6q_pm_init(void); 147extern void imx6q_pm_init(void);
diff --git a/arch/arm/mach-imx/devices/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h
index 6277baf1b7be..9bd5777ff0e7 100644
--- a/arch/arm/mach-imx/devices/devices-common.h
+++ b/arch/arm/mach-imx/devices/devices-common.h
@@ -63,6 +63,7 @@ struct platform_device *__init imx_add_flexcan(
63 63
64#include <linux/fsl_devices.h> 64#include <linux/fsl_devices.h>
65struct imx_fsl_usb2_udc_data { 65struct imx_fsl_usb2_udc_data {
66 const char *devid;
66 resource_size_t iobase; 67 resource_size_t iobase;
67 resource_size_t irq; 68 resource_size_t irq;
68}; 69};
diff --git a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c b/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
index 37e44398197b..3c06bd96e9cc 100644
--- a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
+++ b/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
@@ -11,35 +11,36 @@
11#include "../hardware.h" 11#include "../hardware.h"
12#include "devices-common.h" 12#include "devices-common.h"
13 13
14#define imx_fsl_usb2_udc_data_entry_single(soc) \ 14#define imx_fsl_usb2_udc_data_entry_single(soc, _devid) \
15 { \ 15 { \
16 .devid = _devid, \
16 .iobase = soc ## _USB_OTG_BASE_ADDR, \ 17 .iobase = soc ## _USB_OTG_BASE_ADDR, \
17 .irq = soc ## _INT_USB_OTG, \ 18 .irq = soc ## _INT_USB_OTG, \
18 } 19 }
19 20
20#ifdef CONFIG_SOC_IMX25 21#ifdef CONFIG_SOC_IMX25
21const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst = 22const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst =
22 imx_fsl_usb2_udc_data_entry_single(MX25); 23 imx_fsl_usb2_udc_data_entry_single(MX25, "imx-udc-mx27");
23#endif /* ifdef CONFIG_SOC_IMX25 */ 24#endif /* ifdef CONFIG_SOC_IMX25 */
24 25
25#ifdef CONFIG_SOC_IMX27 26#ifdef CONFIG_SOC_IMX27
26const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst = 27const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst =
27 imx_fsl_usb2_udc_data_entry_single(MX27); 28 imx_fsl_usb2_udc_data_entry_single(MX27, "imx-udc-mx27");
28#endif /* ifdef CONFIG_SOC_IMX27 */ 29#endif /* ifdef CONFIG_SOC_IMX27 */
29 30
30#ifdef CONFIG_SOC_IMX31 31#ifdef CONFIG_SOC_IMX31
31const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst = 32const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst =
32 imx_fsl_usb2_udc_data_entry_single(MX31); 33 imx_fsl_usb2_udc_data_entry_single(MX31, "imx-udc-mx27");
33#endif /* ifdef CONFIG_SOC_IMX31 */ 34#endif /* ifdef CONFIG_SOC_IMX31 */
34 35
35#ifdef CONFIG_SOC_IMX35 36#ifdef CONFIG_SOC_IMX35
36const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst = 37const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst =
37 imx_fsl_usb2_udc_data_entry_single(MX35); 38 imx_fsl_usb2_udc_data_entry_single(MX35, "imx-udc-mx27");
38#endif /* ifdef CONFIG_SOC_IMX35 */ 39#endif /* ifdef CONFIG_SOC_IMX35 */
39 40
40#ifdef CONFIG_SOC_IMX51 41#ifdef CONFIG_SOC_IMX51
41const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data __initconst = 42const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data __initconst =
42 imx_fsl_usb2_udc_data_entry_single(MX51); 43 imx_fsl_usb2_udc_data_entry_single(MX51, "imx-udc-mx51");
43#endif 44#endif
44 45
45struct platform_device *__init imx_add_fsl_usb2_udc( 46struct platform_device *__init imx_add_fsl_usb2_udc(
@@ -57,7 +58,7 @@ struct platform_device *__init imx_add_fsl_usb2_udc(
57 .flags = IORESOURCE_IRQ, 58 .flags = IORESOURCE_IRQ,
58 }, 59 },
59 }; 60 };
60 return imx_add_platform_device_dmamask("fsl-usb2-udc", -1, 61 return imx_add_platform_device_dmamask(data->devid, -1,
61 res, ARRAY_SIZE(res), 62 res, ARRAY_SIZE(res),
62 pdata, sizeof(*pdata), DMA_BIT_MASK(32)); 63 pdata, sizeof(*pdata), DMA_BIT_MASK(32));
63} 64}
diff --git a/arch/arm/mach-imx/devices/platform-imx-fb.c b/arch/arm/mach-imx/devices/platform-imx-fb.c
index 10b0ed39f07f..25a47c616b2d 100644
--- a/arch/arm/mach-imx/devices/platform-imx-fb.c
+++ b/arch/arm/mach-imx/devices/platform-imx-fb.c
@@ -54,7 +54,7 @@ struct platform_device *__init imx_add_imx_fb(
54 .flags = IORESOURCE_IRQ, 54 .flags = IORESOURCE_IRQ,
55 }, 55 },
56 }; 56 };
57 return imx_add_platform_device_dmamask("imx-fb", 0, 57 return imx_add_platform_device_dmamask(data->devid, 0,
58 res, ARRAY_SIZE(res), 58 res, ARRAY_SIZE(res),
59 pdata, sizeof(*pdata), DMA_BIT_MASK(32)); 59 pdata, sizeof(*pdata), DMA_BIT_MASK(32));
60} 60}
diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
index 3dec962b0770..7bc5fe15dda2 100644
--- a/arch/arm/mach-imx/hotplug.c
+++ b/arch/arm/mach-imx/hotplug.c
@@ -46,9 +46,11 @@ static inline void cpu_enter_lowpower(void)
46void imx_cpu_die(unsigned int cpu) 46void imx_cpu_die(unsigned int cpu)
47{ 47{
48 cpu_enter_lowpower(); 48 cpu_enter_lowpower();
49 imx_enable_cpu(cpu, false); 49 cpu_do_idle();
50}
50 51
51 /* spin here until hardware takes it down */ 52int imx_cpu_kill(unsigned int cpu)
52 while (1) 53{
53 ; 54 imx_enable_cpu(cpu, false);
55 return 1;
54} 56}
diff --git a/arch/arm/mach-imx/iram.h b/arch/arm/mach-imx/iram.h
deleted file mode 100644
index 022690c33702..000000000000
--- a/arch/arm/mach-imx/iram.h
+++ /dev/null
@@ -1,41 +0,0 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19#include <linux/errno.h>
20
21#ifdef CONFIG_IRAM_ALLOC
22
23int __init iram_init(unsigned long base, unsigned long size);
24void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr);
25void iram_free(unsigned long dma_addr, unsigned int size);
26
27#else
28
29static inline int __init iram_init(unsigned long base, unsigned long size)
30{
31 return -ENOMEM;
32}
33
34static inline void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr)
35{
36 return NULL;
37}
38
39static inline void iram_free(unsigned long base, unsigned long size) {}
40
41#endif
diff --git a/arch/arm/mach-imx/iram_alloc.c b/arch/arm/mach-imx/iram_alloc.c
index 6c80424f678e..e05cf407db65 100644
--- a/arch/arm/mach-imx/iram_alloc.c
+++ b/arch/arm/mach-imx/iram_alloc.c
@@ -22,8 +22,7 @@
22#include <linux/module.h> 22#include <linux/module.h>
23#include <linux/spinlock.h> 23#include <linux/spinlock.h>
24#include <linux/genalloc.h> 24#include <linux/genalloc.h>
25 25#include "linux/platform_data/imx-iram.h"
26#include "iram.h"
27 26
28static unsigned long iram_phys_base; 27static unsigned long iram_phys_base;
29static void __iomem *iram_virt_base; 28static void __iomem *iram_virt_base;
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index d35693117991..b2872ec614a4 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -90,5 +90,6 @@ struct smp_operations imx_smp_ops __initdata = {
90 .smp_boot_secondary = imx_boot_secondary, 90 .smp_boot_secondary = imx_boot_secondary,
91#ifdef CONFIG_HOTPLUG_CPU 91#ifdef CONFIG_HOTPLUG_CPU
92 .cpu_die = imx_cpu_die, 92 .cpu_die = imx_cpu_die,
93 .cpu_kill = imx_cpu_kill,
93#endif 94#endif
94}; 95};
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
index a17543da602d..ee42d20cba19 100644
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ b/arch/arm/mach-imx/pm-imx6q.c
@@ -41,6 +41,7 @@ static int imx6q_pm_enter(suspend_state_t state)
41 cpu_suspend(0, imx6q_suspend_finish); 41 cpu_suspend(0, imx6q_suspend_finish);
42 imx_smp_prepare(); 42 imx_smp_prepare();
43 imx_gpc_post_resume(); 43 imx_gpc_post_resume();
44 imx6q_set_lpm(WAIT_CLOCKED);
44 break; 45 break;
45 default: 46 default:
46 return -EINVAL; 47 return -EINVAL;
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index be50e795536d..e7fcea7f3300 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -475,13 +475,12 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
475{ 475{
476 int ret = 0; 476 int ret = 0;
477 477
478 if (!ap_syscon_base)
479 return -EINVAL;
480
478 if (nr == 0) { 481 if (nr == 0) {
479 sys->mem_offset = PHYS_PCI_MEM_BASE; 482 sys->mem_offset = PHYS_PCI_MEM_BASE;
480 ret = pci_v3_setup_resources(sys); 483 ret = pci_v3_setup_resources(sys);
481 /* Remap the Integrator system controller */
482 ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100);
483 if (!ap_syscon_base)
484 return -EINVAL;
485 } 484 }
486 485
487 return ret; 486 return ret;
@@ -497,6 +496,13 @@ void __init pci_v3_preinit(void)
497 unsigned int temp; 496 unsigned int temp;
498 int ret; 497 int ret;
499 498
499 /* Remap the Integrator system controller */
500 ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100);
501 if (!ap_syscon_base) {
502 pr_err("unable to remap the AP syscon for PCIv3\n");
503 return;
504 }
505
500 pcibios_min_mem = 0x00100000; 506 pcibios_min_mem = 0x00100000;
501 507
502 /* 508 /*
diff --git a/arch/arm/mach-kirkwood/board-ns2.c b/arch/arm/mach-kirkwood/board-ns2.c
index 8821720ab5a4..f4632a809f68 100644
--- a/arch/arm/mach-kirkwood/board-ns2.c
+++ b/arch/arm/mach-kirkwood/board-ns2.c
@@ -18,47 +18,11 @@
18#include <linux/gpio.h> 18#include <linux/gpio.h>
19#include <linux/of.h> 19#include <linux/of.h>
20#include "common.h" 20#include "common.h"
21#include "mpp.h"
22 21
23static struct mv643xx_eth_platform_data ns2_ge00_data = { 22static struct mv643xx_eth_platform_data ns2_ge00_data = {
24 .phy_addr = MV643XX_ETH_PHY_ADDR(8), 23 .phy_addr = MV643XX_ETH_PHY_ADDR(8),
25}; 24};
26 25
27static unsigned int ns2_mpp_config[] __initdata = {
28 MPP0_SPI_SCn,
29 MPP1_SPI_MOSI,
30 MPP2_SPI_SCK,
31 MPP3_SPI_MISO,
32 MPP4_NF_IO6,
33 MPP5_NF_IO7,
34 MPP6_SYSRST_OUTn,
35 MPP7_GPO, /* Fan speed (bit 1) */
36 MPP8_TW0_SDA,
37 MPP9_TW0_SCK,
38 MPP10_UART0_TXD,
39 MPP11_UART0_RXD,
40 MPP12_GPO, /* Red led */
41 MPP14_GPIO, /* USB fuse */
42 MPP16_GPIO, /* SATA 0 power */
43 MPP17_GPIO, /* SATA 1 power */
44 MPP18_NF_IO0,
45 MPP19_NF_IO1,
46 MPP20_SATA1_ACTn,
47 MPP21_SATA0_ACTn,
48 MPP22_GPIO, /* Fan speed (bit 0) */
49 MPP23_GPIO, /* Fan power */
50 MPP24_GPIO, /* USB mode select */
51 MPP25_GPIO, /* Fan rotation fail */
52 MPP26_GPIO, /* USB device vbus */
53 MPP28_GPIO, /* USB enable host vbus */
54 MPP29_GPIO, /* Blue led (slow register) */
55 MPP30_GPIO, /* Blue led (command register) */
56 MPP31_GPIO, /* Board power off */
57 MPP32_GPIO, /* Power button (0 = Released, 1 = Pushed) */
58 MPP33_GPO, /* Fan speed (bit 2) */
59 0
60};
61
62#define NS2_GPIO_POWER_OFF 31 26#define NS2_GPIO_POWER_OFF 31
63 27
64static void ns2_power_off(void) 28static void ns2_power_off(void)
@@ -71,8 +35,6 @@ void __init ns2_init(void)
71 /* 35 /*
72 * Basic setup. Needs to be called early. 36 * Basic setup. Needs to be called early.
73 */ 37 */
74 kirkwood_mpp_conf(ns2_mpp_config);
75
76 if (of_machine_is_compatible("lacie,netspace_lite_v2") || 38 if (of_machine_is_compatible("lacie,netspace_lite_v2") ||
77 of_machine_is_compatible("lacie,netspace_mini_v2")) 39 of_machine_is_compatible("lacie,netspace_mini_v2"))
78 ns2_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0); 40 ns2_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 5dcb369b58aa..99df4df680fd 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -1,6 +1,8 @@
1ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \ 1ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
2 -I$(srctree)/arch/arm/plat-orion/include 2 -I$(srctree)/arch/arm/plat-orion/include
3 3
4AFLAGS_coherency_ll.o := -Wa,-march=armv7-a
5
4obj-y += system-controller.o 6obj-y += system-controller.o
5obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o coherency_ll.o pmsu.o 7obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o coherency_ll.o pmsu.o
6obj-$(CONFIG_SMP) += platsmp.o headsmp.o 8obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 41b581fd0213..9d7909e58980 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -76,12 +76,12 @@ config ARCH_OMAP4
76 76
77config SOC_OMAP5 77config SOC_OMAP5
78 bool "TI OMAP5" 78 bool "TI OMAP5"
79 select ARM_ARCH_TIMER
80 select ARM_CPU_SUSPEND if PM 79 select ARM_CPU_SUSPEND if PM
81 select ARM_GIC 80 select ARM_GIC
82 select CPU_V7 81 select CPU_V7
83 select HAVE_SMP 82 select HAVE_SMP
84 select COMMON_CLK 83 select COMMON_CLK
84 select HAVE_ARM_ARCH_TIMER
85 85
86comment "OMAP Core Type" 86comment "OMAP Core Type"
87 depends on ARCH_OMAP2 87 depends on ARCH_OMAP2
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 37495bc9a59c..e9270b3e44c7 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -397,6 +397,12 @@ static struct omap_board_mux board_mux[] __initdata = {
397 OMAP_PULL_ENA), 397 OMAP_PULL_ENA),
398 OMAP4_MUX(ABE_MCBSP1_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), 398 OMAP4_MUX(ABE_MCBSP1_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
399 399
400 /* UART2 - BT/FM/GPS shared transport */
401 OMAP4_MUX(UART2_CTS, OMAP_PIN_INPUT | OMAP_MUX_MODE0),
402 OMAP4_MUX(UART2_RTS, OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
403 OMAP4_MUX(UART2_RX, OMAP_PIN_INPUT | OMAP_MUX_MODE0),
404 OMAP4_MUX(UART2_TX, OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
405
400 { .reg_offset = OMAP_MUX_TERMINATOR }, 406 { .reg_offset = OMAP_MUX_TERMINATOR },
401}; 407};
402 408
diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c
index 7e5febe456d9..ab7e952d2070 100644
--- a/arch/arm/mach-omap2/cclock2420_data.c
+++ b/arch/arm/mach-omap2/cclock2420_data.c
@@ -1935,6 +1935,8 @@ int __init omap2420_clk_init(void)
1935 omap2_init_clk_hw_omap_clocks(c->lk.clk); 1935 omap2_init_clk_hw_omap_clocks(c->lk.clk);
1936 } 1936 }
1937 1937
1938 omap2xxx_clkt_vps_late_init();
1939
1938 omap2_clk_disable_autoidle_all(); 1940 omap2_clk_disable_autoidle_all();
1939 1941
1940 omap2_clk_enable_init_clocks(enable_init_clks, 1942 omap2_clk_enable_init_clocks(enable_init_clks,
diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c
index eda079b96c6a..eb3dab68d536 100644
--- a/arch/arm/mach-omap2/cclock2430_data.c
+++ b/arch/arm/mach-omap2/cclock2430_data.c
@@ -2050,6 +2050,8 @@ int __init omap2430_clk_init(void)
2050 omap2_init_clk_hw_omap_clocks(c->lk.clk); 2050 omap2_init_clk_hw_omap_clocks(c->lk.clk);
2051 } 2051 }
2052 2052
2053 omap2xxx_clkt_vps_late_init();
2054
2053 omap2_clk_disable_autoidle_all(); 2055 omap2_clk_disable_autoidle_all();
2054 2056
2055 omap2_clk_enable_init_clocks(enable_init_clks, 2057 omap2_clk_enable_init_clocks(enable_init_clks,
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index 5789a5e25563..a2cc046b47f4 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -2026,14 +2026,13 @@ int __init omap4xxx_clk_init(void)
2026 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power 2026 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
2027 * state when turning the ABE clock domain. Workaround this by 2027 * state when turning the ABE clock domain. Workaround this by
2028 * locking the ABE DPLL on boot. 2028 * locking the ABE DPLL on boot.
2029 * Lock the ABE DPLL in any case to avoid issues with audio.
2029 */ 2030 */
2030 if (cpu_is_omap446x()) { 2031 rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck);
2031 rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck); 2032 if (!rc)
2032 if (!rc) 2033 rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ);
2033 rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ); 2034 if (rc)
2034 if (rc) 2035 pr_err("%s: failed to configure ABE DPLL!\n", __func__);
2035 pr_err("%s: failed to configure ABE DPLL!\n", __func__);
2036 }
2037 2036
2038 return 0; 2037 return 0;
2039} 2038}
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 5e304d0719a2..626f3ea3142f 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -639,7 +639,7 @@ static int count_ocp2scp_devices(struct omap_ocp2scp_dev *ocp2scp_dev)
639 return cnt; 639 return cnt;
640} 640}
641 641
642static void omap_init_ocp2scp(void) 642static void __init omap_init_ocp2scp(void)
643{ 643{
644 struct omap_hwmod *oh; 644 struct omap_hwmod *oh;
645 struct platform_device *pdev; 645 struct platform_device *pdev;
diff --git a/arch/arm/mach-omap2/drm.c b/arch/arm/mach-omap2/drm.c
index 4c7566c7e24a..2a2cfa88ddbf 100644
--- a/arch/arm/mach-omap2/drm.c
+++ b/arch/arm/mach-omap2/drm.c
@@ -25,6 +25,7 @@
25#include <linux/dma-mapping.h> 25#include <linux/dma-mapping.h>
26#include <linux/platform_data/omap_drm.h> 26#include <linux/platform_data/omap_drm.h>
27 27
28#include "soc.h"
28#include "omap_device.h" 29#include "omap_device.h"
29#include "omap_hwmod.h" 30#include "omap_hwmod.h"
30 31
@@ -56,7 +57,7 @@ static int __init omap_init_drm(void)
56 oh->name); 57 oh->name);
57 } 58 }
58 59
59 platform_data.omaprev = GET_OMAP_REVISION(); 60 platform_data.omaprev = GET_OMAP_TYPE;
60 61
61 return platform_device_register(&omap_drm_device); 62 return platform_device_register(&omap_drm_device);
62 63
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 129d5081ed15..793f54ac7d14 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -2132,8 +2132,12 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2132 * currently reset very early during boot, before I2C is 2132 * currently reset very early during boot, before I2C is
2133 * available, so it doesn't seem that we have any choice in 2133 * available, so it doesn't seem that we have any choice in
2134 * the kernel other than to avoid resetting it. 2134 * the kernel other than to avoid resetting it.
2135 *
2136 * Also, McPDM needs to be configured to NO_IDLE mode when it
2137 * is in used otherwise vital clocks will be gated which
2138 * results 'slow motion' audio playback.
2135 */ 2139 */
2136 .flags = HWMOD_EXT_OPT_MAIN_CLK, 2140 .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
2137 .mpu_irqs = omap44xx_mcpdm_irqs, 2141 .mpu_irqs = omap44xx_mcpdm_irqs,
2138 .sdma_reqs = omap44xx_mcpdm_sdma_reqs, 2142 .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
2139 .main_clk = "mcpdm_fck", 2143 .main_clk = "mcpdm_fck",
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 691aa674665a..b8ad6e632bb8 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -165,15 +165,11 @@ static struct device_node * __init omap_get_timer_dt(struct of_device_id *match,
165 struct device_node *np; 165 struct device_node *np;
166 166
167 for_each_matching_node(np, match) { 167 for_each_matching_node(np, match) {
168 if (!of_device_is_available(np)) { 168 if (!of_device_is_available(np))
169 of_node_put(np);
170 continue; 169 continue;
171 }
172 170
173 if (property && !of_get_property(np, property, NULL)) { 171 if (property && !of_get_property(np, property, NULL))
174 of_node_put(np);
175 continue; 172 continue;
176 }
177 173
178 of_add_property(np, &device_disabled); 174 of_add_property(np, &device_disabled);
179 return np; 175 return np;
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
index a611ad3153c7..b6132aa95dc0 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
@@ -463,6 +463,9 @@
463 GPIO76_LCD_PCLK, \ 463 GPIO76_LCD_PCLK, \
464 GPIO77_LCD_BIAS 464 GPIO77_LCD_BIAS
465 465
466/* these enable a work-around for a hw bug in pxa27x during ac97 warm reset */
467#define GPIO113_AC97_nRESET_GPIO_HIGH MFP_CFG_OUT(GPIO113, AF0, DEFAULT)
468#define GPIO95_AC97_nRESET_GPIO_HIGH MFP_CFG_OUT(GPIO95, AF0, DEFAULT)
466 469
467extern int keypad_set_wake(unsigned int on); 470extern int keypad_set_wake(unsigned int on);
468#endif /* __ASM_ARCH_MFP_PXA27X_H */ 471#endif /* __ASM_ARCH_MFP_PXA27X_H */
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 8047ee0effc5..616cb87b6179 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -47,9 +47,9 @@ void pxa27x_clear_otgph(void)
47EXPORT_SYMBOL(pxa27x_clear_otgph); 47EXPORT_SYMBOL(pxa27x_clear_otgph);
48 48
49static unsigned long ac97_reset_config[] = { 49static unsigned long ac97_reset_config[] = {
50 GPIO113_GPIO, 50 GPIO113_AC97_nRESET_GPIO_HIGH,
51 GPIO113_AC97_nRESET, 51 GPIO113_AC97_nRESET,
52 GPIO95_GPIO, 52 GPIO95_AC97_nRESET_GPIO_HIGH,
53 GPIO95_AC97_nRESET, 53 GPIO95_AC97_nRESET,
54}; 54};
55 55
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
index 553059f51841..755c0bb119f4 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -47,7 +47,7 @@ static struct spi_board_info wm1253_devs[] = {
47 .bus_num = 0, 47 .bus_num = 0,
48 .chip_select = 0, 48 .chip_select = 0,
49 .mode = SPI_MODE_0, 49 .mode = SPI_MODE_0,
50 .irq = S3C_EINT(5), 50 .irq = S3C_EINT(4),
51 .controller_data = &wm0010_spi_csinfo, 51 .controller_data = &wm0010_spi_csinfo,
52 .platform_data = &wm0010_pdata, 52 .platform_data = &wm0010_pdata,
53 }, 53 },
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index 7feb426fc202..d2e1a16690bd 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -338,8 +338,10 @@ int __init s3c64xx_pm_init(void)
338 for (i = 0; i < ARRAY_SIZE(s3c64xx_pm_domains); i++) 338 for (i = 0; i < ARRAY_SIZE(s3c64xx_pm_domains); i++)
339 pm_genpd_init(&s3c64xx_pm_domains[i]->pd, NULL, false); 339 pm_genpd_init(&s3c64xx_pm_domains[i]->pd, NULL, false);
340 340
341#ifdef CONFIG_S3C_DEV_FB
341 if (dev_get_platdata(&s3c_device_fb.dev)) 342 if (dev_get_platdata(&s3c_device_fb.dev))
342 pm_genpd_add_device(&s3c64xx_pm_f.pd, &s3c_device_fb.dev); 343 pm_genpd_add_device(&s3c64xx_pm_f.pd, &s3c_device_fb.dev);
344#endif
343 345
344 return 0; 346 return 0;
345} 347}
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 6b2fb87c8698..076c26d43864 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -774,25 +774,27 @@ static void dma_cache_maint_page(struct page *page, unsigned long offset,
774 size_t size, enum dma_data_direction dir, 774 size_t size, enum dma_data_direction dir,
775 void (*op)(const void *, size_t, int)) 775 void (*op)(const void *, size_t, int))
776{ 776{
777 unsigned long pfn;
778 size_t left = size;
779
780 pfn = page_to_pfn(page) + offset / PAGE_SIZE;
781 offset %= PAGE_SIZE;
782
777 /* 783 /*
778 * A single sg entry may refer to multiple physically contiguous 784 * A single sg entry may refer to multiple physically contiguous
779 * pages. But we still need to process highmem pages individually. 785 * pages. But we still need to process highmem pages individually.
780 * If highmem is not configured then the bulk of this loop gets 786 * If highmem is not configured then the bulk of this loop gets
781 * optimized out. 787 * optimized out.
782 */ 788 */
783 size_t left = size;
784 do { 789 do {
785 size_t len = left; 790 size_t len = left;
786 void *vaddr; 791 void *vaddr;
787 792
793 page = pfn_to_page(pfn);
794
788 if (PageHighMem(page)) { 795 if (PageHighMem(page)) {
789 if (len + offset > PAGE_SIZE) { 796 if (len + offset > PAGE_SIZE)
790 if (offset >= PAGE_SIZE) {
791 page += offset / PAGE_SIZE;
792 offset %= PAGE_SIZE;
793 }
794 len = PAGE_SIZE - offset; 797 len = PAGE_SIZE - offset;
795 }
796 vaddr = kmap_high_get(page); 798 vaddr = kmap_high_get(page);
797 if (vaddr) { 799 if (vaddr) {
798 vaddr += offset; 800 vaddr += offset;
@@ -809,7 +811,7 @@ static void dma_cache_maint_page(struct page *page, unsigned long offset,
809 op(vaddr, len, dir); 811 op(vaddr, len, dir);
810 } 812 }
811 offset = 0; 813 offset = 0;
812 page++; 814 pfn++;
813 left -= len; 815 left -= len;
814 } while (left); 816 } while (left);
815} 817}
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 1f51d712b55a..8fcf8bd3ee49 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -298,7 +298,7 @@ static struct mem_type mem_types[] = {
298 }, 298 },
299 [MT_MEMORY_SO] = { 299 [MT_MEMORY_SO] = {
300 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 300 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
301 L_PTE_MT_UNCACHED, 301 L_PTE_MT_UNCACHED | L_PTE_XN,
302 .prot_l1 = PMD_TYPE_TABLE, 302 .prot_l1 = PMD_TYPE_TABLE,
303 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S | 303 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
304 PMD_SECT_UNCACHED | PMD_SECT_XN, 304 PMD_SECT_UNCACHED | PMD_SECT_XN,
diff --git a/arch/arm/plat-versatile/headsmp.S b/arch/arm/plat-versatile/headsmp.S
index dd703ef09b8d..b178d44e9eaa 100644
--- a/arch/arm/plat-versatile/headsmp.S
+++ b/arch/arm/plat-versatile/headsmp.S
@@ -20,7 +20,7 @@
20 */ 20 */
21ENTRY(versatile_secondary_startup) 21ENTRY(versatile_secondary_startup)
22 mrc p15, 0, r0, c0, c0, 5 22 mrc p15, 0, r0, c0, c0, 5
23 and r0, r0, #15 23 bic r0, #0xff000000
24 adr r4, 1f 24 adr r4, 1f
25 ldmia r4, {r5, r6} 25 ldmia r4, {r5, r6}
26 sub r4, r4, r5 26 sub r4, r4, r5
diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S
index cc926c985981..323ce1a62bbf 100644
--- a/arch/arm/vfp/entry.S
+++ b/arch/arm/vfp/entry.S
@@ -22,7 +22,7 @@
22@ IRQs disabled. 22@ IRQs disabled.
23@ 23@
24ENTRY(do_vfp) 24ENTRY(do_vfp)
25#ifdef CONFIG_PREEMPT 25#ifdef CONFIG_PREEMPT_COUNT
26 ldr r4, [r10, #TI_PREEMPT] @ get preempt count 26 ldr r4, [r10, #TI_PREEMPT] @ get preempt count
27 add r11, r4, #1 @ increment it 27 add r11, r4, #1 @ increment it
28 str r11, [r10, #TI_PREEMPT] 28 str r11, [r10, #TI_PREEMPT]
@@ -35,7 +35,7 @@ ENTRY(do_vfp)
35ENDPROC(do_vfp) 35ENDPROC(do_vfp)
36 36
37ENTRY(vfp_null_entry) 37ENTRY(vfp_null_entry)
38#ifdef CONFIG_PREEMPT 38#ifdef CONFIG_PREEMPT_COUNT
39 get_thread_info r10 39 get_thread_info r10
40 ldr r4, [r10, #TI_PREEMPT] @ get preempt count 40 ldr r4, [r10, #TI_PREEMPT] @ get preempt count
41 sub r11, r4, #1 @ decrement it 41 sub r11, r4, #1 @ decrement it
@@ -53,7 +53,7 @@ ENDPROC(vfp_null_entry)
53 53
54 __INIT 54 __INIT
55ENTRY(vfp_testing_entry) 55ENTRY(vfp_testing_entry)
56#ifdef CONFIG_PREEMPT 56#ifdef CONFIG_PREEMPT_COUNT
57 get_thread_info r10 57 get_thread_info r10
58 ldr r4, [r10, #TI_PREEMPT] @ get preempt count 58 ldr r4, [r10, #TI_PREEMPT] @ get preempt count
59 sub r11, r4, #1 @ decrement it 59 sub r11, r4, #1 @ decrement it
diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
index ea0349f63586..dd5e56f95f3f 100644
--- a/arch/arm/vfp/vfphw.S
+++ b/arch/arm/vfp/vfphw.S
@@ -168,7 +168,7 @@ vfp_hw_state_valid:
168 @ else it's one 32-bit instruction, so 168 @ else it's one 32-bit instruction, so
169 @ always subtract 4 from the following 169 @ always subtract 4 from the following
170 @ instruction address. 170 @ instruction address.
171#ifdef CONFIG_PREEMPT 171#ifdef CONFIG_PREEMPT_COUNT
172 get_thread_info r10 172 get_thread_info r10
173 ldr r4, [r10, #TI_PREEMPT] @ get preempt count 173 ldr r4, [r10, #TI_PREEMPT] @ get preempt count
174 sub r11, r4, #1 @ decrement it 174 sub r11, r4, #1 @ decrement it
@@ -192,7 +192,7 @@ look_for_VFP_exceptions:
192 @ not recognised by VFP 192 @ not recognised by VFP
193 193
194 DBGSTR "not VFP" 194 DBGSTR "not VFP"
195#ifdef CONFIG_PREEMPT 195#ifdef CONFIG_PREEMPT_COUNT
196 get_thread_info r10 196 get_thread_info r10
197 ldr r4, [r10, #TI_PREEMPT] @ get preempt count 197 ldr r4, [r10, #TI_PREEMPT] @ get preempt count
198 sub r11, r4, #1 @ decrement it 198 sub r11, r4, #1 @ decrement it
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-16 01:37:25 -0500