aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2011-07-24 23:56:18 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-07-24 23:56:18 -0400
commit8405b044e5238afebd7248d927c1d261d2239767 (patch)
tree56c6a3c1a4542ead63b4abdd9fe6629d849402d5 /arch/arm
parentee05eff6f79c25617e5b7d7677b8f79d26abbe37 (diff)
parent133de1211982bd2ba9ab401f7a73d25d052ccd61 (diff)
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/davej/cpufreq
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/davej/cpufreq: [CPUFREQ] s5pv210: make needlessly global symbols static [CPUFREQ] exynos4210: make needlessly global symbols static [CPUFREQ] S3C6410: Add some lower frequencies for 800MHz base clock operation [CPUFREQ] S5PV210: Add reboot notifier to prevent system hang [CPUFREQ] S5PV210: Adjust udelay prior to voltage scaling down [CPUFREQ] S5PV210: Lock a mutex while changing the cpu frequency [CPUFREQ] S5PV210: Add pm_notifier to prevent system unstable [CPUFREQ] S5PV210: Add arm/int voltage control support [CPUFREQ] S5PV210: Add additional symantics for "relation" in cpufreq with pm [CPUFREQ] S3C64xx: Notify transition complete as soon as frequency changed [CPUFREQ] S3C6410: Support 800MHz operation in cpufreq [CPUFREQ] s5pv210-cpufreq.c: Add missing clk_put [CPUFREQ] Move compile for S3C64XX cpufreq to /drivers/cpufreq [CPUFREQ] Remove some vi noise that escaped into the Makefile. [CPUFREQ] Move ARM Samsung cpufreq drivers to drivers/cpufreq/ [CPUFREQ/S3C64xx] Move S3C64xx CPUfreq driver into drivers/cpufreq [CPUFREQ] Handle CPUs with different capabilities in acpi-cpufreq
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig4
-rw-r--r--arch/arm/mach-exynos4/Makefile1
-rw-r--r--arch/arm/mach-exynos4/cpufreq.c569
-rw-r--r--arch/arm/mach-s3c64xx/Makefile4
-rw-r--r--arch/arm/mach-s3c64xx/cpufreq.c270
-rw-r--r--arch/arm/mach-s5pv210/Makefile1
-rw-r--r--arch/arm/mach-s5pv210/cpufreq.c485
7 files changed, 0 insertions, 1334 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1478c6171b00..83a7aa2ca57a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1895,10 +1895,6 @@ config CPU_FREQ_PXA
1895 default y 1895 default y
1896 select CPU_FREQ_DEFAULT_GOV_USERSPACE 1896 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1897 1897
1898config CPU_FREQ_S3C64XX
1899 bool "CPUfreq support for Samsung S3C64XX CPUs"
1900 depends on CPU_FREQ && CPU_S3C6410
1901
1902config CPU_FREQ_S3C 1898config CPU_FREQ_S3C
1903 bool 1899 bool
1904 help 1900 help
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index 60fe5ecf3599..1366995d8c2c 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -15,7 +15,6 @@ obj- :=
15obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o 15obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o
16obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o 16obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o
17obj-$(CONFIG_PM) += pm.o sleep.o 17obj-$(CONFIG_PM) += pm.o sleep.o
18obj-$(CONFIG_CPU_FREQ) += cpufreq.o
19obj-$(CONFIG_CPU_IDLE) += cpuidle.o 18obj-$(CONFIG_CPU_IDLE) += cpuidle.o
20 19
21obj-$(CONFIG_SMP) += platsmp.o headsmp.o 20obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/arch/arm/mach-exynos4/cpufreq.c b/arch/arm/mach-exynos4/cpufreq.c
deleted file mode 100644
index a1bd258f0c4d..000000000000
--- a/arch/arm/mach-exynos4/cpufreq.c
+++ /dev/null
@@ -1,569 +0,0 @@
1/* linux/arch/arm/mach-exynos4/cpufreq.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - CPU frequency scaling support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/types.h>
14#include <linux/kernel.h>
15#include <linux/err.h>
16#include <linux/clk.h>
17#include <linux/io.h>
18#include <linux/slab.h>
19#include <linux/regulator/consumer.h>
20#include <linux/cpufreq.h>
21
22#include <mach/map.h>
23#include <mach/regs-clock.h>
24#include <mach/regs-mem.h>
25
26#include <plat/clock.h>
27#include <plat/pm.h>
28
29static struct clk *cpu_clk;
30static struct clk *moutcore;
31static struct clk *mout_mpll;
32static struct clk *mout_apll;
33
34static struct regulator *arm_regulator;
35static struct regulator *int_regulator;
36
37static struct cpufreq_freqs freqs;
38static unsigned int memtype;
39
40enum exynos4_memory_type {
41 DDR2 = 4,
42 LPDDR2,
43 DDR3,
44};
45
46enum cpufreq_level_index {
47 L0, L1, L2, L3, CPUFREQ_LEVEL_END,
48};
49
50static struct cpufreq_frequency_table exynos4_freq_table[] = {
51 {L0, 1000*1000},
52 {L1, 800*1000},
53 {L2, 400*1000},
54 {L3, 100*1000},
55 {0, CPUFREQ_TABLE_END},
56};
57
58static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
59 /*
60 * Clock divider value for following
61 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
62 * DIVATB, DIVPCLK_DBG, DIVAPLL }
63 */
64
65 /* ARM L0: 1000MHz */
66 { 0, 3, 7, 3, 3, 0, 1 },
67
68 /* ARM L1: 800MHz */
69 { 0, 3, 7, 3, 3, 0, 1 },
70
71 /* ARM L2: 400MHz */
72 { 0, 1, 3, 1, 3, 0, 1 },
73
74 /* ARM L3: 100MHz */
75 { 0, 0, 1, 0, 3, 1, 1 },
76};
77
78static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
79 /*
80 * Clock divider value for following
81 * { DIVCOPY, DIVHPM }
82 */
83
84 /* ARM L0: 1000MHz */
85 { 3, 0 },
86
87 /* ARM L1: 800MHz */
88 { 3, 0 },
89
90 /* ARM L2: 400MHz */
91 { 3, 0 },
92
93 /* ARM L3: 100MHz */
94 { 3, 0 },
95};
96
97static unsigned int clkdiv_dmc0[CPUFREQ_LEVEL_END][8] = {
98 /*
99 * Clock divider value for following
100 * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
101 * DIVDMCP, DIVCOPY2, DIVCORE_TIMERS }
102 */
103
104 /* DMC L0: 400MHz */
105 { 3, 1, 1, 1, 1, 1, 3, 1 },
106
107 /* DMC L1: 400MHz */
108 { 3, 1, 1, 1, 1, 1, 3, 1 },
109
110 /* DMC L2: 266.7MHz */
111 { 7, 1, 1, 2, 1, 1, 3, 1 },
112
113 /* DMC L3: 200MHz */
114 { 7, 1, 1, 3, 1, 1, 3, 1 },
115};
116
117static unsigned int clkdiv_top[CPUFREQ_LEVEL_END][5] = {
118 /*
119 * Clock divider value for following
120 * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
121 */
122
123 /* ACLK200 L0: 200MHz */
124 { 3, 7, 4, 5, 1 },
125
126 /* ACLK200 L1: 200MHz */
127 { 3, 7, 4, 5, 1 },
128
129 /* ACLK200 L2: 160MHz */
130 { 4, 7, 5, 7, 1 },
131
132 /* ACLK200 L3: 133.3MHz */
133 { 5, 7, 7, 7, 1 },
134};
135
136static unsigned int clkdiv_lr_bus[CPUFREQ_LEVEL_END][2] = {
137 /*
138 * Clock divider value for following
139 * { DIVGDL/R, DIVGPL/R }
140 */
141
142 /* ACLK_GDL/R L0: 200MHz */
143 { 3, 1 },
144
145 /* ACLK_GDL/R L1: 200MHz */
146 { 3, 1 },
147
148 /* ACLK_GDL/R L2: 160MHz */
149 { 4, 1 },
150
151 /* ACLK_GDL/R L3: 133.3MHz */
152 { 5, 1 },
153};
154
155struct cpufreq_voltage_table {
156 unsigned int index; /* any */
157 unsigned int arm_volt; /* uV */
158 unsigned int int_volt;
159};
160
161static struct cpufreq_voltage_table exynos4_volt_table[CPUFREQ_LEVEL_END] = {
162 {
163 .index = L0,
164 .arm_volt = 1200000,
165 .int_volt = 1100000,
166 }, {
167 .index = L1,
168 .arm_volt = 1100000,
169 .int_volt = 1100000,
170 }, {
171 .index = L2,
172 .arm_volt = 1000000,
173 .int_volt = 1000000,
174 }, {
175 .index = L3,
176 .arm_volt = 900000,
177 .int_volt = 1000000,
178 },
179};
180
181static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {
182 /* APLL FOUT L0: 1000MHz */
183 ((250 << 16) | (6 << 8) | 1),
184
185 /* APLL FOUT L1: 800MHz */
186 ((200 << 16) | (6 << 8) | 1),
187
188 /* APLL FOUT L2 : 400MHz */
189 ((200 << 16) | (6 << 8) | 2),
190
191 /* APLL FOUT L3: 100MHz */
192 ((200 << 16) | (6 << 8) | 4),
193};
194
195int exynos4_verify_speed(struct cpufreq_policy *policy)
196{
197 return cpufreq_frequency_table_verify(policy, exynos4_freq_table);
198}
199
200unsigned int exynos4_getspeed(unsigned int cpu)
201{
202 return clk_get_rate(cpu_clk) / 1000;
203}
204
205void exynos4_set_clkdiv(unsigned int div_index)
206{
207 unsigned int tmp;
208
209 /* Change Divider - CPU0 */
210
211 tmp = __raw_readl(S5P_CLKDIV_CPU);
212
213 tmp &= ~(S5P_CLKDIV_CPU0_CORE_MASK | S5P_CLKDIV_CPU0_COREM0_MASK |
214 S5P_CLKDIV_CPU0_COREM1_MASK | S5P_CLKDIV_CPU0_PERIPH_MASK |
215 S5P_CLKDIV_CPU0_ATB_MASK | S5P_CLKDIV_CPU0_PCLKDBG_MASK |
216 S5P_CLKDIV_CPU0_APLL_MASK);
217
218 tmp |= ((clkdiv_cpu0[div_index][0] << S5P_CLKDIV_CPU0_CORE_SHIFT) |
219 (clkdiv_cpu0[div_index][1] << S5P_CLKDIV_CPU0_COREM0_SHIFT) |
220 (clkdiv_cpu0[div_index][2] << S5P_CLKDIV_CPU0_COREM1_SHIFT) |
221 (clkdiv_cpu0[div_index][3] << S5P_CLKDIV_CPU0_PERIPH_SHIFT) |
222 (clkdiv_cpu0[div_index][4] << S5P_CLKDIV_CPU0_ATB_SHIFT) |
223 (clkdiv_cpu0[div_index][5] << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) |
224 (clkdiv_cpu0[div_index][6] << S5P_CLKDIV_CPU0_APLL_SHIFT));
225
226 __raw_writel(tmp, S5P_CLKDIV_CPU);
227
228 do {
229 tmp = __raw_readl(S5P_CLKDIV_STATCPU);
230 } while (tmp & 0x1111111);
231
232 /* Change Divider - CPU1 */
233
234 tmp = __raw_readl(S5P_CLKDIV_CPU1);
235
236 tmp &= ~((0x7 << 4) | 0x7);
237
238 tmp |= ((clkdiv_cpu1[div_index][0] << 4) |
239 (clkdiv_cpu1[div_index][1] << 0));
240
241 __raw_writel(tmp, S5P_CLKDIV_CPU1);
242
243 do {
244 tmp = __raw_readl(S5P_CLKDIV_STATCPU1);
245 } while (tmp & 0x11);
246
247 /* Change Divider - DMC0 */
248
249 tmp = __raw_readl(S5P_CLKDIV_DMC0);
250
251 tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK | S5P_CLKDIV_DMC0_ACPPCLK_MASK |
252 S5P_CLKDIV_DMC0_DPHY_MASK | S5P_CLKDIV_DMC0_DMC_MASK |
253 S5P_CLKDIV_DMC0_DMCD_MASK | S5P_CLKDIV_DMC0_DMCP_MASK |
254 S5P_CLKDIV_DMC0_COPY2_MASK | S5P_CLKDIV_DMC0_CORETI_MASK);
255
256 tmp |= ((clkdiv_dmc0[div_index][0] << S5P_CLKDIV_DMC0_ACP_SHIFT) |
257 (clkdiv_dmc0[div_index][1] << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) |
258 (clkdiv_dmc0[div_index][2] << S5P_CLKDIV_DMC0_DPHY_SHIFT) |
259 (clkdiv_dmc0[div_index][3] << S5P_CLKDIV_DMC0_DMC_SHIFT) |
260 (clkdiv_dmc0[div_index][4] << S5P_CLKDIV_DMC0_DMCD_SHIFT) |
261 (clkdiv_dmc0[div_index][5] << S5P_CLKDIV_DMC0_DMCP_SHIFT) |
262 (clkdiv_dmc0[div_index][6] << S5P_CLKDIV_DMC0_COPY2_SHIFT) |
263 (clkdiv_dmc0[div_index][7] << S5P_CLKDIV_DMC0_CORETI_SHIFT));
264
265 __raw_writel(tmp, S5P_CLKDIV_DMC0);
266
267 do {
268 tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0);
269 } while (tmp & 0x11111111);
270
271 /* Change Divider - TOP */
272
273 tmp = __raw_readl(S5P_CLKDIV_TOP);
274
275 tmp &= ~(S5P_CLKDIV_TOP_ACLK200_MASK | S5P_CLKDIV_TOP_ACLK100_MASK |
276 S5P_CLKDIV_TOP_ACLK160_MASK | S5P_CLKDIV_TOP_ACLK133_MASK |
277 S5P_CLKDIV_TOP_ONENAND_MASK);
278
279 tmp |= ((clkdiv_top[div_index][0] << S5P_CLKDIV_TOP_ACLK200_SHIFT) |
280 (clkdiv_top[div_index][1] << S5P_CLKDIV_TOP_ACLK100_SHIFT) |
281 (clkdiv_top[div_index][2] << S5P_CLKDIV_TOP_ACLK160_SHIFT) |
282 (clkdiv_top[div_index][3] << S5P_CLKDIV_TOP_ACLK133_SHIFT) |
283 (clkdiv_top[div_index][4] << S5P_CLKDIV_TOP_ONENAND_SHIFT));
284
285 __raw_writel(tmp, S5P_CLKDIV_TOP);
286
287 do {
288 tmp = __raw_readl(S5P_CLKDIV_STAT_TOP);
289 } while (tmp & 0x11111);
290
291 /* Change Divider - LEFTBUS */
292
293 tmp = __raw_readl(S5P_CLKDIV_LEFTBUS);
294
295 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
296
297 tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
298 (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
299
300 __raw_writel(tmp, S5P_CLKDIV_LEFTBUS);
301
302 do {
303 tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS);
304 } while (tmp & 0x11);
305
306 /* Change Divider - RIGHTBUS */
307
308 tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS);
309
310 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
311
312 tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
313 (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
314
315 __raw_writel(tmp, S5P_CLKDIV_RIGHTBUS);
316
317 do {
318 tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS);
319 } while (tmp & 0x11);
320}
321
322static void exynos4_set_apll(unsigned int index)
323{
324 unsigned int tmp;
325
326 /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
327 clk_set_parent(moutcore, mout_mpll);
328
329 do {
330 tmp = (__raw_readl(S5P_CLKMUX_STATCPU)
331 >> S5P_CLKSRC_CPU_MUXCORE_SHIFT);
332 tmp &= 0x7;
333 } while (tmp != 0x2);
334
335 /* 2. Set APLL Lock time */
336 __raw_writel(S5P_APLL_LOCKTIME, S5P_APLL_LOCK);
337
338 /* 3. Change PLL PMS values */
339 tmp = __raw_readl(S5P_APLL_CON0);
340 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
341 tmp |= exynos4_apll_pms_table[index];
342 __raw_writel(tmp, S5P_APLL_CON0);
343
344 /* 4. wait_lock_time */
345 do {
346 tmp = __raw_readl(S5P_APLL_CON0);
347 } while (!(tmp & (0x1 << S5P_APLLCON0_LOCKED_SHIFT)));
348
349 /* 5. MUX_CORE_SEL = APLL */
350 clk_set_parent(moutcore, mout_apll);
351
352 do {
353 tmp = __raw_readl(S5P_CLKMUX_STATCPU);
354 tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK;
355 } while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
356}
357
358static void exynos4_set_frequency(unsigned int old_index, unsigned int new_index)
359{
360 unsigned int tmp;
361
362 if (old_index > new_index) {
363 /* The frequency changing to L0 needs to change apll */
364 if (freqs.new == exynos4_freq_table[L0].frequency) {
365 /* 1. Change the system clock divider values */
366 exynos4_set_clkdiv(new_index);
367
368 /* 2. Change the apll m,p,s value */
369 exynos4_set_apll(new_index);
370 } else {
371 /* 1. Change the system clock divider values */
372 exynos4_set_clkdiv(new_index);
373
374 /* 2. Change just s value in apll m,p,s value */
375 tmp = __raw_readl(S5P_APLL_CON0);
376 tmp &= ~(0x7 << 0);
377 tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
378 __raw_writel(tmp, S5P_APLL_CON0);
379 }
380 }
381
382 else if (old_index < new_index) {
383 /* The frequency changing from L0 needs to change apll */
384 if (freqs.old == exynos4_freq_table[L0].frequency) {
385 /* 1. Change the apll m,p,s value */
386 exynos4_set_apll(new_index);
387
388 /* 2. Change the system clock divider values */
389 exynos4_set_clkdiv(new_index);
390 } else {
391 /* 1. Change just s value in apll m,p,s value */
392 tmp = __raw_readl(S5P_APLL_CON0);
393 tmp &= ~(0x7 << 0);
394 tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
395 __raw_writel(tmp, S5P_APLL_CON0);
396
397 /* 2. Change the system clock divider values */
398 exynos4_set_clkdiv(new_index);
399 }
400 }
401}
402
403static int exynos4_target(struct cpufreq_policy *policy,
404 unsigned int target_freq,
405 unsigned int relation)
406{
407 unsigned int index, old_index;
408 unsigned int arm_volt, int_volt;
409
410 freqs.old = exynos4_getspeed(policy->cpu);
411
412 if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
413 freqs.old, relation, &old_index))
414 return -EINVAL;
415
416 if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
417 target_freq, relation, &index))
418 return -EINVAL;
419
420 freqs.new = exynos4_freq_table[index].frequency;
421 freqs.cpu = policy->cpu;
422
423 if (freqs.new == freqs.old)
424 return 0;
425
426 /* get the voltage value */
427 arm_volt = exynos4_volt_table[index].arm_volt;
428 int_volt = exynos4_volt_table[index].int_volt;
429
430 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
431
432 /* control regulator */
433 if (freqs.new > freqs.old) {
434 /* Voltage up */
435 regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
436 regulator_set_voltage(int_regulator, int_volt, int_volt);
437 }
438
439 /* Clock Configuration Procedure */
440 exynos4_set_frequency(old_index, index);
441
442 /* control regulator */
443 if (freqs.new < freqs.old) {
444 /* Voltage down */
445 regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
446 regulator_set_voltage(int_regulator, int_volt, int_volt);
447 }
448
449 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
450
451 return 0;
452}
453
454#ifdef CONFIG_PM
455static int exynos4_cpufreq_suspend(struct cpufreq_policy *policy)
456{
457 return 0;
458}
459
460static int exynos4_cpufreq_resume(struct cpufreq_policy *policy)
461{
462 return 0;
463}
464#endif
465
466static int exynos4_cpufreq_cpu_init(struct cpufreq_policy *policy)
467{
468 policy->cur = policy->min = policy->max = exynos4_getspeed(policy->cpu);
469
470 cpufreq_frequency_table_get_attr(exynos4_freq_table, policy->cpu);
471
472 /* set the transition latency value */
473 policy->cpuinfo.transition_latency = 100000;
474
475 /*
476 * EXYNOS4 multi-core processors has 2 cores
477 * that the frequency cannot be set independently.
478 * Each cpu is bound to the same speed.
479 * So the affected cpu is all of the cpus.
480 */
481 cpumask_setall(policy->cpus);
482
483 return cpufreq_frequency_table_cpuinfo(policy, exynos4_freq_table);
484}
485
486static struct cpufreq_driver exynos4_driver = {
487 .flags = CPUFREQ_STICKY,
488 .verify = exynos4_verify_speed,
489 .target = exynos4_target,
490 .get = exynos4_getspeed,
491 .init = exynos4_cpufreq_cpu_init,
492 .name = "exynos4_cpufreq",
493#ifdef CONFIG_PM
494 .suspend = exynos4_cpufreq_suspend,
495 .resume = exynos4_cpufreq_resume,
496#endif
497};
498
499static int __init exynos4_cpufreq_init(void)
500{
501 cpu_clk = clk_get(NULL, "armclk");
502 if (IS_ERR(cpu_clk))
503 return PTR_ERR(cpu_clk);
504
505 moutcore = clk_get(NULL, "moutcore");
506 if (IS_ERR(moutcore))
507 goto out;
508
509 mout_mpll = clk_get(NULL, "mout_mpll");
510 if (IS_ERR(mout_mpll))
511 goto out;
512
513 mout_apll = clk_get(NULL, "mout_apll");
514 if (IS_ERR(mout_apll))
515 goto out;
516
517 arm_regulator = regulator_get(NULL, "vdd_arm");
518 if (IS_ERR(arm_regulator)) {
519 printk(KERN_ERR "failed to get resource %s\n", "vdd_arm");
520 goto out;
521 }
522
523 int_regulator = regulator_get(NULL, "vdd_int");
524 if (IS_ERR(int_regulator)) {
525 printk(KERN_ERR "failed to get resource %s\n", "vdd_int");
526 goto out;
527 }
528
529 /*
530 * Check DRAM type.
531 * Because DVFS level is different according to DRAM type.
532 */
533 memtype = __raw_readl(S5P_VA_DMC0 + S5P_DMC0_MEMCON_OFFSET);
534 memtype = (memtype >> S5P_DMC0_MEMTYPE_SHIFT);
535 memtype &= S5P_DMC0_MEMTYPE_MASK;
536
537 if ((memtype < DDR2) && (memtype > DDR3)) {
538 printk(KERN_ERR "%s: wrong memtype= 0x%x\n", __func__, memtype);
539 goto out;
540 } else {
541 printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype);
542 }
543
544 return cpufreq_register_driver(&exynos4_driver);
545
546out:
547 if (!IS_ERR(cpu_clk))
548 clk_put(cpu_clk);
549
550 if (!IS_ERR(moutcore))
551 clk_put(moutcore);
552
553 if (!IS_ERR(mout_mpll))
554 clk_put(mout_mpll);
555
556 if (!IS_ERR(mout_apll))
557 clk_put(mout_apll);
558
559 if (!IS_ERR(arm_regulator))
560 regulator_put(arm_regulator);
561
562 if (!IS_ERR(int_regulator))
563 regulator_put(int_regulator);
564
565 printk(KERN_ERR "%s: failed initialization\n", __func__);
566
567 return -EINVAL;
568}
569late_initcall(exynos4_cpufreq_init);
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 4657363f0674..f5a7144a052f 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -23,10 +23,6 @@ obj-$(CONFIG_CPU_S3C6410) += s3c6410.o
23obj-y += irq.o 23obj-y += irq.o
24obj-y += irq-eint.o 24obj-y += irq-eint.o
25 25
26# CPU frequency scaling
27
28obj-$(CONFIG_CPU_FREQ_S3C64XX) += cpufreq.o
29
30# DMA support 26# DMA support
31 27
32obj-$(CONFIG_S3C64XX_DMA) += dma.o 28obj-$(CONFIG_S3C64XX_DMA) += dma.o
diff --git a/arch/arm/mach-s3c64xx/cpufreq.c b/arch/arm/mach-s3c64xx/cpufreq.c
deleted file mode 100644
index 4375b97588b8..000000000000
--- a/arch/arm/mach-s3c64xx/cpufreq.c
+++ /dev/null
@@ -1,270 +0,0 @@
1/* linux/arch/arm/plat-s3c64xx/cpufreq.c
2 *
3 * Copyright 2009 Wolfson Microelectronics plc
4 *
5 * S3C64xx CPUfreq Support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/init.h>
15#include <linux/cpufreq.h>
16#include <linux/clk.h>
17#include <linux/err.h>
18#include <linux/regulator/consumer.h>
19
20static struct clk *armclk;
21static struct regulator *vddarm;
22static unsigned long regulator_latency;
23
24#ifdef CONFIG_CPU_S3C6410
25struct s3c64xx_dvfs {
26 unsigned int vddarm_min;
27 unsigned int vddarm_max;
28};
29
30static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = {
31 [0] = { 1000000, 1150000 },
32 [1] = { 1050000, 1150000 },
33 [2] = { 1100000, 1150000 },
34 [3] = { 1200000, 1350000 },
35};
36
37static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
38 { 0, 66000 },
39 { 0, 133000 },
40 { 1, 222000 },
41 { 1, 266000 },
42 { 2, 333000 },
43 { 2, 400000 },
44 { 2, 532000 },
45 { 2, 533000 },
46 { 3, 667000 },
47 { 0, CPUFREQ_TABLE_END },
48};
49#endif
50
51static int s3c64xx_cpufreq_verify_speed(struct cpufreq_policy *policy)
52{
53 if (policy->cpu != 0)
54 return -EINVAL;
55
56 return cpufreq_frequency_table_verify(policy, s3c64xx_freq_table);
57}
58
59static unsigned int s3c64xx_cpufreq_get_speed(unsigned int cpu)
60{
61 if (cpu != 0)
62 return 0;
63
64 return clk_get_rate(armclk) / 1000;
65}
66
67static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy,
68 unsigned int target_freq,
69 unsigned int relation)
70{
71 int ret;
72 unsigned int i;
73 struct cpufreq_freqs freqs;
74 struct s3c64xx_dvfs *dvfs;
75
76 ret = cpufreq_frequency_table_target(policy, s3c64xx_freq_table,
77 target_freq, relation, &i);
78 if (ret != 0)
79 return ret;
80
81 freqs.cpu = 0;
82 freqs.old = clk_get_rate(armclk) / 1000;
83 freqs.new = s3c64xx_freq_table[i].frequency;
84 freqs.flags = 0;
85 dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[i].index];
86
87 if (freqs.old == freqs.new)
88 return 0;
89
90 pr_debug("cpufreq: Transition %d-%dkHz\n", freqs.old, freqs.new);
91
92 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
93
94#ifdef CONFIG_REGULATOR
95 if (vddarm && freqs.new > freqs.old) {
96 ret = regulator_set_voltage(vddarm,
97 dvfs->vddarm_min,
98 dvfs->vddarm_max);
99 if (ret != 0) {
100 pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
101 freqs.new, ret);
102 goto err;
103 }
104 }
105#endif
106
107 ret = clk_set_rate(armclk, freqs.new * 1000);
108 if (ret < 0) {
109 pr_err("cpufreq: Failed to set rate %dkHz: %d\n",
110 freqs.new, ret);
111 goto err;
112 }
113
114#ifdef CONFIG_REGULATOR
115 if (vddarm && freqs.new < freqs.old) {
116 ret = regulator_set_voltage(vddarm,
117 dvfs->vddarm_min,
118 dvfs->vddarm_max);
119 if (ret != 0) {
120 pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
121 freqs.new, ret);
122 goto err_clk;
123 }
124 }
125#endif
126
127 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
128
129 pr_debug("cpufreq: Set actual frequency %lukHz\n",
130 clk_get_rate(armclk) / 1000);
131
132 return 0;
133
134err_clk:
135 if (clk_set_rate(armclk, freqs.old * 1000) < 0)
136 pr_err("Failed to restore original clock rate\n");
137err:
138 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
139
140 return ret;
141}
142
143#ifdef CONFIG_REGULATOR
144static void __init s3c64xx_cpufreq_config_regulator(void)
145{
146 int count, v, i, found;
147 struct cpufreq_frequency_table *freq;
148 struct s3c64xx_dvfs *dvfs;
149
150 count = regulator_count_voltages(vddarm);
151 if (count < 0) {
152 pr_err("cpufreq: Unable to check supported voltages\n");
153 }
154
155 freq = s3c64xx_freq_table;
156 while (count > 0 && freq->frequency != CPUFREQ_TABLE_END) {
157 if (freq->frequency == CPUFREQ_ENTRY_INVALID)
158 continue;
159
160 dvfs = &s3c64xx_dvfs_table[freq->index];
161 found = 0;
162
163 for (i = 0; i < count; i++) {
164 v = regulator_list_voltage(vddarm, i);
165 if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max)
166 found = 1;
167 }
168
169 if (!found) {
170 pr_debug("cpufreq: %dkHz unsupported by regulator\n",
171 freq->frequency);
172 freq->frequency = CPUFREQ_ENTRY_INVALID;
173 }
174
175 freq++;
176 }
177
178 /* Guess based on having to do an I2C/SPI write; in future we
179 * will be able to query the regulator performance here. */
180 regulator_latency = 1 * 1000 * 1000;
181}
182#endif
183
184static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
185{
186 int ret;
187 struct cpufreq_frequency_table *freq;
188
189 if (policy->cpu != 0)
190 return -EINVAL;
191
192 if (s3c64xx_freq_table == NULL) {
193 pr_err("cpufreq: No frequency information for this CPU\n");
194 return -ENODEV;
195 }
196
197 armclk = clk_get(NULL, "armclk");
198 if (IS_ERR(armclk)) {
199 pr_err("cpufreq: Unable to obtain ARMCLK: %ld\n",
200 PTR_ERR(armclk));
201 return PTR_ERR(armclk);
202 }
203
204#ifdef CONFIG_REGULATOR
205 vddarm = regulator_get(NULL, "vddarm");
206 if (IS_ERR(vddarm)) {
207 ret = PTR_ERR(vddarm);
208 pr_err("cpufreq: Failed to obtain VDDARM: %d\n", ret);
209 pr_err("cpufreq: Only frequency scaling available\n");
210 vddarm = NULL;
211 } else {
212 s3c64xx_cpufreq_config_regulator();
213 }
214#endif
215
216 freq = s3c64xx_freq_table;
217 while (freq->frequency != CPUFREQ_TABLE_END) {
218 unsigned long r;
219
220 /* Check for frequencies we can generate */
221 r = clk_round_rate(armclk, freq->frequency * 1000);
222 r /= 1000;
223 if (r != freq->frequency) {
224 pr_debug("cpufreq: %dkHz unsupported by clock\n",
225 freq->frequency);
226 freq->frequency = CPUFREQ_ENTRY_INVALID;
227 }
228
229 /* If we have no regulator then assume startup
230 * frequency is the maximum we can support. */
231 if (!vddarm && freq->frequency > s3c64xx_cpufreq_get_speed(0))
232 freq->frequency = CPUFREQ_ENTRY_INVALID;
233
234 freq++;
235 }
236
237 policy->cur = clk_get_rate(armclk) / 1000;
238
239 /* Datasheet says PLL stabalisation time (if we were to use
240 * the PLLs, which we don't currently) is ~300us worst case,
241 * but add some fudge.
242 */
243 policy->cpuinfo.transition_latency = (500 * 1000) + regulator_latency;
244
245 ret = cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table);
246 if (ret != 0) {
247 pr_err("cpufreq: Failed to configure frequency table: %d\n",
248 ret);
249 regulator_put(vddarm);
250 clk_put(armclk);
251 }
252
253 return ret;
254}
255
256static struct cpufreq_driver s3c64xx_cpufreq_driver = {
257 .owner = THIS_MODULE,
258 .flags = 0,
259 .verify = s3c64xx_cpufreq_verify_speed,
260 .target = s3c64xx_cpufreq_set_target,
261 .get = s3c64xx_cpufreq_get_speed,
262 .init = s3c64xx_cpufreq_driver_init,
263 .name = "s3c",
264};
265
266static int __init s3c64xx_cpufreq_init(void)
267{
268 return cpufreq_register_driver(&s3c64xx_cpufreq_driver);
269}
270module_init(s3c64xx_cpufreq_init);
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 50907aca006c..599a3c0e8f6c 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -15,7 +15,6 @@ obj- :=
15obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o 15obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o
16obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o 16obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o
17obj-$(CONFIG_S5PV210_PM) += pm.o sleep.o 17obj-$(CONFIG_S5PV210_PM) += pm.o sleep.o
18obj-$(CONFIG_CPU_FREQ) += cpufreq.o
19 18
20# machine support 19# machine support
21 20
diff --git a/arch/arm/mach-s5pv210/cpufreq.c b/arch/arm/mach-s5pv210/cpufreq.c
deleted file mode 100644
index 153af8b359ec..000000000000
--- a/arch/arm/mach-s5pv210/cpufreq.c
+++ /dev/null
@@ -1,485 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/cpufreq.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * CPU frequency scaling for S5PC110/S5PV210
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/types.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/err.h>
17#include <linux/clk.h>
18#include <linux/io.h>
19#include <linux/cpufreq.h>
20
21#include <mach/map.h>
22#include <mach/regs-clock.h>
23
24static struct clk *cpu_clk;
25static struct clk *dmc0_clk;
26static struct clk *dmc1_clk;
27static struct cpufreq_freqs freqs;
28
29/* APLL M,P,S values for 1G/800Mhz */
30#define APLL_VAL_1000 ((1 << 31) | (125 << 16) | (3 << 8) | 1)
31#define APLL_VAL_800 ((1 << 31) | (100 << 16) | (3 << 8) | 1)
32
33/*
34 * DRAM configurations to calculate refresh counter for changing
35 * frequency of memory.
36 */
37struct dram_conf {
38 unsigned long freq; /* HZ */
39 unsigned long refresh; /* DRAM refresh counter * 1000 */
40};
41
42/* DRAM configuration (DMC0 and DMC1) */
43static struct dram_conf s5pv210_dram_conf[2];
44
45enum perf_level {
46 L0, L1, L2, L3, L4,
47};
48
49enum s5pv210_mem_type {
50 LPDDR = 0x1,
51 LPDDR2 = 0x2,
52 DDR2 = 0x4,
53};
54
55enum s5pv210_dmc_port {
56 DMC0 = 0,
57 DMC1,
58};
59
60static struct cpufreq_frequency_table s5pv210_freq_table[] = {
61 {L0, 1000*1000},
62 {L1, 800*1000},
63 {L2, 400*1000},
64 {L3, 200*1000},
65 {L4, 100*1000},
66 {0, CPUFREQ_TABLE_END},
67};
68
69static u32 clkdiv_val[5][11] = {
70 /*
71 * Clock divider value for following
72 * { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
73 * HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS,
74 * ONEDRAM, MFC, G3D }
75 */
76
77 /* L0 : [1000/200/100][166/83][133/66][200/200] */
78 {0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
79
80 /* L1 : [800/200/100][166/83][133/66][200/200] */
81 {0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},
82
83 /* L2 : [400/200/100][166/83][133/66][200/200] */
84 {1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
85
86 /* L3 : [200/200/100][166/83][133/66][200/200] */
87 {3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
88
89 /* L4 : [100/100/100][83/83][66/66][100/100] */
90 {7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
91};
92
93/*
94 * This function set DRAM refresh counter
95 * accoriding to operating frequency of DRAM
96 * ch: DMC port number 0 or 1
97 * freq: Operating frequency of DRAM(KHz)
98 */
99static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq)
100{
101 unsigned long tmp, tmp1;
102 void __iomem *reg = NULL;
103
104 if (ch == DMC0) {
105 reg = (S5P_VA_DMC0 + 0x30);
106 } else if (ch == DMC1) {
107 reg = (S5P_VA_DMC1 + 0x30);
108 } else {
109 printk(KERN_ERR "Cannot find DMC port\n");
110 return;
111 }
112
113 /* Find current DRAM frequency */
114 tmp = s5pv210_dram_conf[ch].freq;
115
116 do_div(tmp, freq);
117
118 tmp1 = s5pv210_dram_conf[ch].refresh;
119
120 do_div(tmp1, tmp);
121
122 __raw_writel(tmp1, reg);
123}
124
125int s5pv210_verify_speed(struct cpufreq_policy *policy)
126{
127 if (policy->cpu)
128 return -EINVAL;
129
130 return cpufreq_frequency_table_verify(policy, s5pv210_freq_table);
131}
132
133unsigned int s5pv210_getspeed(unsigned int cpu)
134{
135 if (cpu)
136 return 0;
137
138 return clk_get_rate(cpu_clk) / 1000;
139}
140
141static int s5pv210_target(struct cpufreq_policy *policy,
142 unsigned int target_freq,
143 unsigned int relation)
144{
145 unsigned long reg;
146 unsigned int index, priv_index;
147 unsigned int pll_changing = 0;
148 unsigned int bus_speed_changing = 0;
149
150 freqs.old = s5pv210_getspeed(0);
151
152 if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
153 target_freq, relation, &index))
154 return -EINVAL;
155
156 freqs.new = s5pv210_freq_table[index].frequency;
157 freqs.cpu = 0;
158
159 if (freqs.new == freqs.old)
160 return 0;
161
162 /* Finding current running level index */
163 if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
164 freqs.old, relation, &priv_index))
165 return -EINVAL;
166
167 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
168
169 if (freqs.new > freqs.old) {
170 /* Voltage up: will be implemented */
171 }
172
173 /* Check if there need to change PLL */
174 if ((index == L0) || (priv_index == L0))
175 pll_changing = 1;
176
177 /* Check if there need to change System bus clock */
178 if ((index == L4) || (priv_index == L4))
179 bus_speed_changing = 1;
180
181 if (bus_speed_changing) {
182 /*
183 * Reconfigure DRAM refresh counter value for minimum
184 * temporary clock while changing divider.
185 * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287
186 */
187 if (pll_changing)
188 s5pv210_set_refresh(DMC1, 83000);
189 else
190 s5pv210_set_refresh(DMC1, 100000);
191
192 s5pv210_set_refresh(DMC0, 83000);
193 }
194
195 /*
196 * APLL should be changed in this level
197 * APLL -> MPLL(for stable transition) -> APLL
198 * Some clock source's clock API are not prepared.
199 * Do not use clock API in below code.
200 */
201 if (pll_changing) {
202 /*
203 * 1. Temporary Change divider for MFC and G3D
204 * SCLKA2M(200/1=200)->(200/4=50)Mhz
205 */
206 reg = __raw_readl(S5P_CLK_DIV2);
207 reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
208 reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) |
209 (3 << S5P_CLKDIV2_MFC_SHIFT);
210 __raw_writel(reg, S5P_CLK_DIV2);
211
212 /* For MFC, G3D dividing */
213 do {
214 reg = __raw_readl(S5P_CLKDIV_STAT0);
215 } while (reg & ((1 << 16) | (1 << 17)));
216
217 /*
218 * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX
219 * (200/4=50)->(667/4=166)Mhz
220 */
221 reg = __raw_readl(S5P_CLK_SRC2);
222 reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
223 reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) |
224 (1 << S5P_CLKSRC2_MFC_SHIFT);
225 __raw_writel(reg, S5P_CLK_SRC2);
226
227 do {
228 reg = __raw_readl(S5P_CLKMUX_STAT1);
229 } while (reg & ((1 << 7) | (1 << 3)));
230
231 /*
232 * 3. DMC1 refresh count for 133Mhz if (index == L4) is
233 * true refresh counter is already programed in upper
234 * code. 0x287@83Mhz
235 */
236 if (!bus_speed_changing)
237 s5pv210_set_refresh(DMC1, 133000);
238
239 /* 4. SCLKAPLL -> SCLKMPLL */
240 reg = __raw_readl(S5P_CLK_SRC0);
241 reg &= ~(S5P_CLKSRC0_MUX200_MASK);
242 reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT);
243 __raw_writel(reg, S5P_CLK_SRC0);
244
245 do {
246 reg = __raw_readl(S5P_CLKMUX_STAT0);
247 } while (reg & (0x1 << 18));
248
249 }
250
251 /* Change divider */
252 reg = __raw_readl(S5P_CLK_DIV0);
253
254 reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK |
255 S5P_CLKDIV0_HCLK200_MASK | S5P_CLKDIV0_PCLK100_MASK |
256 S5P_CLKDIV0_HCLK166_MASK | S5P_CLKDIV0_PCLK83_MASK |
257 S5P_CLKDIV0_HCLK133_MASK | S5P_CLKDIV0_PCLK66_MASK);
258
259 reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) |
260 (clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT) |
261 (clkdiv_val[index][2] << S5P_CLKDIV0_HCLK200_SHIFT) |
262 (clkdiv_val[index][3] << S5P_CLKDIV0_PCLK100_SHIFT) |
263 (clkdiv_val[index][4] << S5P_CLKDIV0_HCLK166_SHIFT) |
264 (clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT) |
265 (clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) |
266 (clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT));
267
268 __raw_writel(reg, S5P_CLK_DIV0);
269
270 do {
271 reg = __raw_readl(S5P_CLKDIV_STAT0);
272 } while (reg & 0xff);
273
274 /* ARM MCS value changed */
275 reg = __raw_readl(S5P_ARM_MCS_CON);
276 reg &= ~0x3;
277 if (index >= L3)
278 reg |= 0x3;
279 else
280 reg |= 0x1;
281
282 __raw_writel(reg, S5P_ARM_MCS_CON);
283
284 if (pll_changing) {
285 /* 5. Set Lock time = 30us*24Mhz = 0x2cf */
286 __raw_writel(0x2cf, S5P_APLL_LOCK);
287
288 /*
289 * 6. Turn on APLL
290 * 6-1. Set PMS values
291 * 6-2. Wait untile the PLL is locked
292 */
293 if (index == L0)
294 __raw_writel(APLL_VAL_1000, S5P_APLL_CON);
295 else
296 __raw_writel(APLL_VAL_800, S5P_APLL_CON);
297
298 do {
299 reg = __raw_readl(S5P_APLL_CON);
300 } while (!(reg & (0x1 << 29)));
301
302 /*
303 * 7. Change souce clock from SCLKMPLL(667Mhz)
304 * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
305 * (667/4=166)->(200/4=50)Mhz
306 */
307 reg = __raw_readl(S5P_CLK_SRC2);
308 reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
309 reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) |
310 (0 << S5P_CLKSRC2_MFC_SHIFT);
311 __raw_writel(reg, S5P_CLK_SRC2);
312
313 do {
314 reg = __raw_readl(S5P_CLKMUX_STAT1);
315 } while (reg & ((1 << 7) | (1 << 3)));
316
317 /*
318 * 8. Change divider for MFC and G3D
319 * (200/4=50)->(200/1=200)Mhz
320 */
321 reg = __raw_readl(S5P_CLK_DIV2);
322 reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
323 reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) |
324 (clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT);
325 __raw_writel(reg, S5P_CLK_DIV2);
326
327 /* For MFC, G3D dividing */
328 do {
329 reg = __raw_readl(S5P_CLKDIV_STAT0);
330 } while (reg & ((1 << 16) | (1 << 17)));
331
332 /* 9. Change MPLL to APLL in MSYS_MUX */
333 reg = __raw_readl(S5P_CLK_SRC0);
334 reg &= ~(S5P_CLKSRC0_MUX200_MASK);
335 reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT);
336 __raw_writel(reg, S5P_CLK_SRC0);
337
338 do {
339 reg = __raw_readl(S5P_CLKMUX_STAT0);
340 } while (reg & (0x1 << 18));
341
342 /*
343 * 10. DMC1 refresh counter
344 * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c
345 * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618
346 */
347 if (!bus_speed_changing)
348 s5pv210_set_refresh(DMC1, 200000);
349 }
350
351 /*
352 * L4 level need to change memory bus speed, hence onedram clock divier
353 * and memory refresh parameter should be changed
354 */
355 if (bus_speed_changing) {
356 reg = __raw_readl(S5P_CLK_DIV6);
357 reg &= ~S5P_CLKDIV6_ONEDRAM_MASK;
358 reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT);
359 __raw_writel(reg, S5P_CLK_DIV6);
360
361 do {
362 reg = __raw_readl(S5P_CLKDIV_STAT1);
363 } while (reg & (1 << 15));
364
365 /* Reconfigure DRAM refresh counter value */
366 if (index != L4) {
367 /*
368 * DMC0 : 166Mhz
369 * DMC1 : 200Mhz
370 */
371 s5pv210_set_refresh(DMC0, 166000);
372 s5pv210_set_refresh(DMC1, 200000);
373 } else {
374 /*
375 * DMC0 : 83Mhz
376 * DMC1 : 100Mhz
377 */
378 s5pv210_set_refresh(DMC0, 83000);
379 s5pv210_set_refresh(DMC1, 100000);
380 }
381 }
382
383 if (freqs.new < freqs.old) {
384 /* Voltage down: will be implemented */
385 }
386
387 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
388
389 printk(KERN_DEBUG "Perf changed[L%d]\n", index);
390
391 return 0;
392}
393
394#ifdef CONFIG_PM
395static int s5pv210_cpufreq_suspend(struct cpufreq_policy *policy)
396{
397 return 0;
398}
399
400static int s5pv210_cpufreq_resume(struct cpufreq_policy *policy)
401{
402 return 0;
403}
404#endif
405
406static int check_mem_type(void __iomem *dmc_reg)
407{
408 unsigned long val;
409
410 val = __raw_readl(dmc_reg + 0x4);
411 val = (val & (0xf << 8));
412
413 return val >> 8;
414}
415
416static int __init s5pv210_cpu_init(struct cpufreq_policy *policy)
417{
418 unsigned long mem_type;
419
420 cpu_clk = clk_get(NULL, "armclk");
421 if (IS_ERR(cpu_clk))
422 return PTR_ERR(cpu_clk);
423
424 dmc0_clk = clk_get(NULL, "sclk_dmc0");
425 if (IS_ERR(dmc0_clk)) {
426 clk_put(cpu_clk);
427 return PTR_ERR(dmc0_clk);
428 }
429
430 dmc1_clk = clk_get(NULL, "hclk_msys");
431 if (IS_ERR(dmc1_clk)) {
432 clk_put(dmc0_clk);
433 clk_put(cpu_clk);
434 return PTR_ERR(dmc1_clk);
435 }
436
437 if (policy->cpu != 0)
438 return -EINVAL;
439
440 /*
441 * check_mem_type : This driver only support LPDDR & LPDDR2.
442 * other memory type is not supported.
443 */
444 mem_type = check_mem_type(S5P_VA_DMC0);
445
446 if ((mem_type != LPDDR) && (mem_type != LPDDR2)) {
447 printk(KERN_ERR "CPUFreq doesn't support this memory type\n");
448 return -EINVAL;
449 }
450
451 /* Find current refresh counter and frequency each DMC */
452 s5pv210_dram_conf[0].refresh = (__raw_readl(S5P_VA_DMC0 + 0x30) * 1000);
453 s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk);
454
455 s5pv210_dram_conf[1].refresh = (__raw_readl(S5P_VA_DMC1 + 0x30) * 1000);
456 s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk);
457
458 policy->cur = policy->min = policy->max = s5pv210_getspeed(0);
459
460 cpufreq_frequency_table_get_attr(s5pv210_freq_table, policy->cpu);
461
462 policy->cpuinfo.transition_latency = 40000;
463
464 return cpufreq_frequency_table_cpuinfo(policy, s5pv210_freq_table);
465}
466
467static struct cpufreq_driver s5pv210_driver = {
468 .flags = CPUFREQ_STICKY,
469 .verify = s5pv210_verify_speed,
470 .target = s5pv210_target,
471 .get = s5pv210_getspeed,
472 .init = s5pv210_cpu_init,
473 .name = "s5pv210",
474#ifdef CONFIG_PM
475 .suspend = s5pv210_cpufreq_suspend,
476 .resume = s5pv210_cpufreq_resume,
477#endif
478};
479
480static int __init s5pv210_cpufreq_init(void)
481{
482 return cpufreq_register_driver(&s5pv210_driver);
483}
484
485late_initcall(s5pv210_cpufreq_init);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-08 10:54:43 -0500