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authorTakashi Iwai <tiwai@suse.de>2010-09-03 16:38:52 -0400
committerTakashi Iwai <tiwai@suse.de>2010-09-03 16:38:52 -0400
commit68885a3ff38ed51fa02f241feb405c9922a90ee0 (patch)
tree2fc626df39d5e0e1f6b065238141f7d49187c737 /arch/arm
parent7b28079b3284ccb15ad4f003fb7073890600d0c1 (diff)
parenta2acad8298a42b7be684a32fafaf83332bba9c2b (diff)
Merge branch 'fix/misc' into topic/misc
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig3
-rw-r--r--arch/arm/Makefile3
-rw-r--r--arch/arm/configs/omap_4430sdp_defconfig3
-rw-r--r--arch/arm/include/asm/ptrace.h17
-rw-r--r--arch/arm/include/asm/unistd.h1
-rw-r--r--arch/arm/kernel/calls.S1
-rw-r--r--arch/arm/kernel/etm.c2
-rw-r--r--arch/arm/kernel/kgdb.c2
-rw-r--r--arch/arm/kernel/sys_arm.c14
-rw-r--r--arch/arm/mach-imx/mach-cpuimx27.c4
-rw-r--r--arch/arm/mach-imx/mach-pca100.c4
-rw-r--r--arch/arm/mach-mx25/mach-cpuimx25.c2
-rw-r--r--arch/arm/mach-mx3/mach-cpuimx35.c2
-rw-r--r--arch/arm/mach-omap2/Makefile1
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c14
-rw-r--r--arch/arm/mach-omap2/id.c2
-rw-r--r--arch/arm/mach-omap2/include/mach/entry-macro.S6
-rw-r--r--arch/arm/mach-omap2/omap-smp.c3
-rw-r--r--arch/arm/mach-omap2/pm34xx.c4
-rw-r--r--arch/arm/mach-s3c2410/include/mach/vmalloc.h2
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/vmalloc.h2
-rw-r--r--arch/arm/mach-s5p6440/include/mach/vmalloc.h2
-rw-r--r--arch/arm/mach-s5p6442/include/mach/vmalloc.h2
-rw-r--r--arch/arm/mach-s5pv210/include/mach/vmalloc.h2
-rw-r--r--arch/arm/mach-s5pv310/clock.c82
-rw-r--r--arch/arm/mach-s5pv310/cpu.c10
-rw-r--r--arch/arm/mach-s5pv310/include/mach/irqs.h11
-rw-r--r--arch/arm/mach-s5pv310/include/mach/map.h16
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-clock.h59
-rw-r--r--arch/arm/mach-s5pv310/include/mach/vmalloc.h2
-rw-r--r--arch/arm/mach-s5pv310/platsmp.c2
-rw-r--r--arch/arm/mach-tegra/board-harmony.c2
-rw-r--r--arch/arm/mach-tegra/include/mach/vmalloc.h2
-rw-r--r--arch/arm/plat-omap/include/plat/smp.h7
-rw-r--r--arch/arm/plat-s5p/include/plat/map-s5p.h2
-rw-r--r--arch/arm/plat-samsung/dev-hsmmc.c2
-rw-r--r--arch/arm/plat-samsung/dev-hsmmc1.c2
-rw-r--r--arch/arm/plat-samsung/dev-hsmmc2.c2
38 files changed, 197 insertions, 102 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 92951103255a..a7ed21f0136a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1622,7 +1622,8 @@ config ZRELADDR
1622 default 0x40008000 if ARCH_STMP378X ||\ 1622 default 0x40008000 if ARCH_STMP378X ||\
1623 ARCH_STMP37XX ||\ 1623 ARCH_STMP37XX ||\
1624 ARCH_SH7372 ||\ 1624 ARCH_SH7372 ||\
1625 ARCH_SH7377 1625 ARCH_SH7377 ||\
1626 ARCH_S5PV310
1626 default 0x50008000 if ARCH_S3C64XX ||\ 1627 default 0x50008000 if ARCH_S3C64XX ||\
1627 ARCH_SH7367 1628 ARCH_SH7367
1628 default 0x60008000 if ARCH_VEXPRESS 1629 default 0x60008000 if ARCH_VEXPRESS
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 99b8200138d2..59c1ce858fc8 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -21,6 +21,9 @@ GZFLAGS :=-9
21# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb: 21# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
22KBUILD_CFLAGS +=$(call cc-option,-marm,) 22KBUILD_CFLAGS +=$(call cc-option,-marm,)
23 23
24# Never generate .eh_frame
25KBUILD_CFLAGS += $(call cc-option,-fno-dwarf2-cfi-asm)
26
24# Do not use arch/arm/defconfig - it's always outdated. 27# Do not use arch/arm/defconfig - it's always outdated.
25# Select a platform tht is kept up-to-date 28# Select a platform tht is kept up-to-date
26KBUILD_DEFCONFIG := versatile_defconfig 29KBUILD_DEFCONFIG := versatile_defconfig
diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig
index 63e0c2d50f32..14c1e18c648f 100644
--- a/arch/arm/configs/omap_4430sdp_defconfig
+++ b/arch/arm/configs/omap_4430sdp_defconfig
@@ -13,6 +13,9 @@ CONFIG_MODULE_SRCVERSION_ALL=y
13# CONFIG_BLK_DEV_BSG is not set 13# CONFIG_BLK_DEV_BSG is not set
14CONFIG_ARCH_OMAP=y 14CONFIG_ARCH_OMAP=y
15CONFIG_ARCH_OMAP4=y 15CONFIG_ARCH_OMAP4=y
16# CONFIG_ARCH_OMAP2PLUS_TYPICAL is not set
17# CONFIG_ARCH_OMAP2 is not set
18# CONFIG_ARCH_OMAP3 is not set
16# CONFIG_OMAP_MUX is not set 19# CONFIG_OMAP_MUX is not set
17CONFIG_OMAP_32K_TIMER=y 20CONFIG_OMAP_32K_TIMER=y
18CONFIG_OMAP_DM_TIMER=y 21CONFIG_OMAP_DM_TIMER=y
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index c974be8913a7..7ce15eb15f72 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -158,15 +158,24 @@ struct pt_regs {
158 */ 158 */
159static inline int valid_user_regs(struct pt_regs *regs) 159static inline int valid_user_regs(struct pt_regs *regs)
160{ 160{
161 if (user_mode(regs) && (regs->ARM_cpsr & PSR_I_BIT) == 0) { 161 unsigned long mode = regs->ARM_cpsr & MODE_MASK;
162 regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT); 162
163 return 1; 163 /*
164 * Always clear the F (FIQ) and A (delayed abort) bits
165 */
166 regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT);
167
168 if ((regs->ARM_cpsr & PSR_I_BIT) == 0) {
169 if (mode == USR_MODE)
170 return 1;
171 if (elf_hwcap & HWCAP_26BIT && mode == USR26_MODE)
172 return 1;
164 } 173 }
165 174
166 /* 175 /*
167 * Force CPSR to something logical... 176 * Force CPSR to something logical...
168 */ 177 */
169 regs->ARM_cpsr &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | PSR_T_BIT | MODE32_BIT; 178 regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT;
170 if (!(elf_hwcap & HWCAP_26BIT)) 179 if (!(elf_hwcap & HWCAP_26BIT))
171 regs->ARM_cpsr |= USR_MODE; 180 regs->ARM_cpsr |= USR_MODE;
172 181
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index dd2bf53000fe..d02cfb683487 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -392,6 +392,7 @@
392#define __NR_rt_tgsigqueueinfo (__NR_SYSCALL_BASE+363) 392#define __NR_rt_tgsigqueueinfo (__NR_SYSCALL_BASE+363)
393#define __NR_perf_event_open (__NR_SYSCALL_BASE+364) 393#define __NR_perf_event_open (__NR_SYSCALL_BASE+364)
394#define __NR_recvmmsg (__NR_SYSCALL_BASE+365) 394#define __NR_recvmmsg (__NR_SYSCALL_BASE+365)
395#define __NR_accept4 (__NR_SYSCALL_BASE+366)
395 396
396/* 397/*
397 * The following SWIs are ARM private. 398 * The following SWIs are ARM private.
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
index 37ae301cc47c..afeb71fa72cb 100644
--- a/arch/arm/kernel/calls.S
+++ b/arch/arm/kernel/calls.S
@@ -375,6 +375,7 @@
375 CALL(sys_rt_tgsigqueueinfo) 375 CALL(sys_rt_tgsigqueueinfo)
376 CALL(sys_perf_event_open) 376 CALL(sys_perf_event_open)
377/* 365 */ CALL(sys_recvmmsg) 377/* 365 */ CALL(sys_recvmmsg)
378 CALL(sys_accept4)
378#ifndef syscalls_counted 379#ifndef syscalls_counted
379.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls 380.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
380#define syscalls_counted 381#define syscalls_counted
diff --git a/arch/arm/kernel/etm.c b/arch/arm/kernel/etm.c
index 56418f98cd01..33c7077174db 100644
--- a/arch/arm/kernel/etm.c
+++ b/arch/arm/kernel/etm.c
@@ -230,7 +230,7 @@ static void etm_dump(void)
230 etb_lock(t); 230 etb_lock(t);
231} 231}
232 232
233static void sysrq_etm_dump(int key, struct tty_struct *tty) 233static void sysrq_etm_dump(int key)
234{ 234{
235 dev_dbg(tracer.dev, "Dumping ETB buffer\n"); 235 dev_dbg(tracer.dev, "Dumping ETB buffer\n");
236 etm_dump(); 236 etm_dump();
diff --git a/arch/arm/kernel/kgdb.c b/arch/arm/kernel/kgdb.c
index 778c2f7024ff..d6e8b4d2e60d 100644
--- a/arch/arm/kernel/kgdb.c
+++ b/arch/arm/kernel/kgdb.c
@@ -79,7 +79,7 @@ sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *task)
79 return; 79 return;
80 80
81 /* Initialize to zero */ 81 /* Initialize to zero */
82 for (regno = 0; regno < GDB_MAX_REGS; regno++) 82 for (regno = 0; regno < DBG_MAX_REG_NUM; regno++)
83 gdb_regs[regno] = 0; 83 gdb_regs[regno] = 0;
84 84
85 /* Otherwise, we have only some registers from switch_to() */ 85 /* Otherwise, we have only some registers from switch_to() */
diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c
index 5b7c541a4c63..62e7c61d0342 100644
--- a/arch/arm/kernel/sys_arm.c
+++ b/arch/arm/kernel/sys_arm.c
@@ -62,8 +62,9 @@ asmlinkage int sys_vfork(struct pt_regs *regs)
62/* sys_execve() executes a new program. 62/* sys_execve() executes a new program.
63 * This is called indirectly via a small wrapper 63 * This is called indirectly via a small wrapper
64 */ 64 */
65asmlinkage int sys_execve(const char __user *filenamei, char __user * __user *argv, 65asmlinkage int sys_execve(const char __user *filenamei,
66 char __user * __user *envp, struct pt_regs *regs) 66 const char __user *const __user *argv,
67 const char __user *const __user *envp, struct pt_regs *regs)
67{ 68{
68 int error; 69 int error;
69 char * filename; 70 char * filename;
@@ -78,14 +79,17 @@ out:
78 return error; 79 return error;
79} 80}
80 81
81int kernel_execve(const char *filename, char *const argv[], char *const envp[]) 82int kernel_execve(const char *filename,
83 const char *const argv[],
84 const char *const envp[])
82{ 85{
83 struct pt_regs regs; 86 struct pt_regs regs;
84 int ret; 87 int ret;
85 88
86 memset(&regs, 0, sizeof(struct pt_regs)); 89 memset(&regs, 0, sizeof(struct pt_regs));
87 ret = do_execve(filename, (char __user * __user *)argv, 90 ret = do_execve(filename,
88 (char __user * __user *)envp, &regs); 91 (const char __user *const __user *)argv,
92 (const char __user *const __user *)envp, &regs);
89 if (ret < 0) 93 if (ret < 0)
90 goto out; 94 goto out;
91 95
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 575ff1ae85a7..339150ab0ea5 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -279,13 +279,13 @@ static void __init eukrea_cpuimx27_init(void)
279#if defined(CONFIG_USB_ULPI) 279#if defined(CONFIG_USB_ULPI)
280 if (otg_mode_host) { 280 if (otg_mode_host) {
281 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 281 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
282 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); 282 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
283 283
284 mxc_register_device(&mxc_otg_host, &otg_pdata); 284 mxc_register_device(&mxc_otg_host, &otg_pdata);
285 } 285 }
286 286
287 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 287 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
288 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); 288 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
289 289
290 mxc_register_device(&mxc_usbh2, &usbh2_pdata); 290 mxc_register_device(&mxc_usbh2, &usbh2_pdata);
291#endif 291#endif
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index a389d1148f18..23c9e1f37b9c 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -419,13 +419,13 @@ static void __init pca100_init(void)
419#if defined(CONFIG_USB_ULPI) 419#if defined(CONFIG_USB_ULPI)
420 if (otg_mode_host) { 420 if (otg_mode_host) {
421 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 421 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
422 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); 422 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
423 423
424 mxc_register_device(&mxc_otg_host, &otg_pdata); 424 mxc_register_device(&mxc_otg_host, &otg_pdata);
425 } 425 }
426 426
427 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 427 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
428 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); 428 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
429 429
430 mxc_register_device(&mxc_usbh2, &usbh2_pdata); 430 mxc_register_device(&mxc_usbh2, &usbh2_pdata);
431#endif 431#endif
diff --git a/arch/arm/mach-mx25/mach-cpuimx25.c b/arch/arm/mach-mx25/mach-cpuimx25.c
index 56b2e26d23b4..a5f0174290b4 100644
--- a/arch/arm/mach-mx25/mach-cpuimx25.c
+++ b/arch/arm/mach-mx25/mach-cpuimx25.c
@@ -138,7 +138,7 @@ static void __init eukrea_cpuimx25_init(void)
138#if defined(CONFIG_USB_ULPI) 138#if defined(CONFIG_USB_ULPI)
139 if (otg_mode_host) { 139 if (otg_mode_host) {
140 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 140 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
141 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); 141 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
142 142
143 mxc_register_device(&mxc_otg, &otg_pdata); 143 mxc_register_device(&mxc_otg, &otg_pdata);
144 } 144 }
diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c
index 63f970f340a2..9770a6a973be 100644
--- a/arch/arm/mach-mx3/mach-cpuimx35.c
+++ b/arch/arm/mach-mx3/mach-cpuimx35.c
@@ -192,7 +192,7 @@ static void __init mxc_board_init(void)
192#if defined(CONFIG_USB_ULPI) 192#if defined(CONFIG_USB_ULPI)
193 if (otg_mode_host) { 193 if (otg_mode_host) {
194 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 194 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
195 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); 195 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
196 196
197 mxc_register_device(&mxc_otg_host, &otg_pdata); 197 mxc_register_device(&mxc_otg_host, &otg_pdata);
198 } 198 }
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 63b2d8859c3c..88d3a1e920f5 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_LOCAL_TIMERS) += timer-mpu.o
25obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o 25obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o
26obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o omap4-common.o 26obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o omap4-common.o
27 27
28AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a
28AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a 29AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a
29 30
30# Functions loaded to SRAM 31# Functions loaded to SRAM
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 138646deac89..dfdce2d82779 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3417,7 +3417,13 @@ int __init omap3xxx_clk_init(void)
3417 struct omap_clk *c; 3417 struct omap_clk *c;
3418 u32 cpu_clkflg = CK_3XXX; 3418 u32 cpu_clkflg = CK_3XXX;
3419 3419
3420 if (cpu_is_omap34xx()) { 3420 if (cpu_is_omap3517()) {
3421 cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
3422 cpu_clkflg |= CK_3517;
3423 } else if (cpu_is_omap3505()) {
3424 cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
3425 cpu_clkflg |= CK_3505;
3426 } else if (cpu_is_omap34xx()) {
3421 cpu_mask = RATE_IN_3XXX; 3427 cpu_mask = RATE_IN_3XXX;
3422 cpu_clkflg |= CK_343X; 3428 cpu_clkflg |= CK_343X;
3423 3429
@@ -3432,12 +3438,6 @@ int __init omap3xxx_clk_init(void)
3432 cpu_mask |= RATE_IN_3430ES2PLUS; 3438 cpu_mask |= RATE_IN_3430ES2PLUS;
3433 cpu_clkflg |= CK_3430ES2; 3439 cpu_clkflg |= CK_3430ES2;
3434 } 3440 }
3435 } else if (cpu_is_omap3517()) {
3436 cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
3437 cpu_clkflg |= CK_3517;
3438 } else if (cpu_is_omap3505()) {
3439 cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
3440 cpu_clkflg |= CK_3505;
3441 } 3441 }
3442 3442
3443 if (omap3_has_192mhz_clk()) 3443 if (omap3_has_192mhz_clk())
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index e8256a2ed8e7..9a879f959509 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -284,8 +284,8 @@ static void __init omap3_check_revision(void)
284 default: 284 default:
285 omap_revision = OMAP3630_REV_ES1_2; 285 omap_revision = OMAP3630_REV_ES1_2;
286 omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; 286 omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
287 break;
288 } 287 }
288 break;
289 default: 289 default:
290 /* Unknown default to latest silicon rev as default*/ 290 /* Unknown default to latest silicon rev as default*/
291 omap_revision = OMAP3630_REV_ES1_2; 291 omap_revision = OMAP3630_REV_ES1_2;
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
index 50fd74916643..06e64e1fc28a 100644
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -177,7 +177,10 @@ omap_irq_base: .word 0
177 cmpne \irqnr, \tmp 177 cmpne \irqnr, \tmp
178 cmpcs \irqnr, \irqnr 178 cmpcs \irqnr, \irqnr
179 .endm 179 .endm
180#endif
181#endif /* MULTI_OMAP2 */
180 182
183#ifdef CONFIG_SMP
181 /* We assume that irqstat (the raw value of the IRQ acknowledge 184 /* We assume that irqstat (the raw value of the IRQ acknowledge
182 * register) is preserved from the macro above. 185 * register) is preserved from the macro above.
183 * If there is an IPI, we immediately signal end of interrupt 186 * If there is an IPI, we immediately signal end of interrupt
@@ -205,8 +208,7 @@ omap_irq_base: .word 0
205 streq \irqstat, [\base, #GIC_CPU_EOI] 208 streq \irqstat, [\base, #GIC_CPU_EOI]
206 cmp \tmp, #0 209 cmp \tmp, #0
207 .endm 210 .endm
208#endif 211#endif /* CONFIG_SMP */
209#endif /* MULTI_OMAP2 */
210 212
211 .macro irq_prio_table 213 .macro irq_prio_table
212 .endm 214 .endm
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index af3c20c8d3f9..9e9f70e18e3c 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -102,8 +102,7 @@ static void __init wakeup_secondary(void)
102 * Send a 'sev' to wake the secondary core from WFE. 102 * Send a 'sev' to wake the secondary core from WFE.
103 * Drain the outstanding writes to memory 103 * Drain the outstanding writes to memory
104 */ 104 */
105 dsb(); 105 dsb_sev();
106 set_event();
107 mb(); 106 mb();
108} 107}
109 108
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index fb4994ad622e..7b03426c72a3 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -480,7 +480,9 @@ void omap_sram_idle(void)
480 } 480 }
481 481
482 /* Disable IO-PAD and IO-CHAIN wakeup */ 482 /* Disable IO-PAD and IO-CHAIN wakeup */
483 if (omap3_has_io_wakeup() && core_next_state < PWRDM_POWER_ON) { 483 if (omap3_has_io_wakeup() &&
484 (per_next_state < PWRDM_POWER_ON ||
485 core_next_state < PWRDM_POWER_ON)) {
484 prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); 486 prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
485 omap3_disable_io_chain(); 487 omap3_disable_io_chain();
486 } 488 }
diff --git a/arch/arm/mach-s3c2410/include/mach/vmalloc.h b/arch/arm/mach-s3c2410/include/mach/vmalloc.h
index 315b0078a34d..54297eb0bf5e 100644
--- a/arch/arm/mach-s3c2410/include/mach/vmalloc.h
+++ b/arch/arm/mach-s3c2410/include/mach/vmalloc.h
@@ -15,6 +15,6 @@
15#ifndef __ASM_ARCH_VMALLOC_H 15#ifndef __ASM_ARCH_VMALLOC_H
16#define __ASM_ARCH_VMALLOC_H 16#define __ASM_ARCH_VMALLOC_H
17 17
18#define VMALLOC_END (0xE0000000) 18#define VMALLOC_END 0xE0000000UL
19 19
20#endif /* __ASM_ARCH_VMALLOC_H */ 20#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/vmalloc.h b/arch/arm/mach-s3c64xx/include/mach/vmalloc.h
index 7411ef3711a6..bc0e91389864 100644
--- a/arch/arm/mach-s3c64xx/include/mach/vmalloc.h
+++ b/arch/arm/mach-s3c64xx/include/mach/vmalloc.h
@@ -15,6 +15,6 @@
15#ifndef __ASM_ARCH_VMALLOC_H 15#ifndef __ASM_ARCH_VMALLOC_H
16#define __ASM_ARCH_VMALLOC_H 16#define __ASM_ARCH_VMALLOC_H
17 17
18#define VMALLOC_END (0xE0000000) 18#define VMALLOC_END 0xE0000000UL
19 19
20#endif /* __ASM_ARCH_VMALLOC_H */ 20#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/vmalloc.h b/arch/arm/mach-s5p6440/include/mach/vmalloc.h
index 16df257b1dce..e3f0eebf5205 100644
--- a/arch/arm/mach-s5p6440/include/mach/vmalloc.h
+++ b/arch/arm/mach-s5p6440/include/mach/vmalloc.h
@@ -12,6 +12,6 @@
12#ifndef __ASM_ARCH_VMALLOC_H 12#ifndef __ASM_ARCH_VMALLOC_H
13#define __ASM_ARCH_VMALLOC_H 13#define __ASM_ARCH_VMALLOC_H
14 14
15#define VMALLOC_END (0xE0000000) 15#define VMALLOC_END 0xE0000000UL
16 16
17#endif /* __ASM_ARCH_VMALLOC_H */ 17#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/vmalloc.h b/arch/arm/mach-s5p6442/include/mach/vmalloc.h
index be3333688c20..f5c83f02c18e 100644
--- a/arch/arm/mach-s5p6442/include/mach/vmalloc.h
+++ b/arch/arm/mach-s5p6442/include/mach/vmalloc.h
@@ -12,6 +12,6 @@
12#ifndef __ASM_ARCH_VMALLOC_H 12#ifndef __ASM_ARCH_VMALLOC_H
13#define __ASM_ARCH_VMALLOC_H 13#define __ASM_ARCH_VMALLOC_H
14 14
15#define VMALLOC_END (0xE0000000) 15#define VMALLOC_END 0xE0000000UL
16 16
17#endif /* __ASM_ARCH_VMALLOC_H */ 17#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/vmalloc.h b/arch/arm/mach-s5pv210/include/mach/vmalloc.h
index 58f515e0747e..df9a28808323 100644
--- a/arch/arm/mach-s5pv210/include/mach/vmalloc.h
+++ b/arch/arm/mach-s5pv210/include/mach/vmalloc.h
@@ -17,6 +17,6 @@
17#ifndef __ASM_ARCH_VMALLOC_H 17#ifndef __ASM_ARCH_VMALLOC_H
18#define __ASM_ARCH_VMALLOC_H __FILE__ 18#define __ASM_ARCH_VMALLOC_H __FILE__
19 19
20#define VMALLOC_END (0xE0000000) 20#define VMALLOC_END (0xE0000000UL)
21 21
22#endif /* __ASM_ARCH_VMALLOC_H */ 22#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index 77f2b4d85e6b..26a0f03df8ea 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -30,6 +30,16 @@ static struct clk clk_sclk_hdmi27m = {
30 .rate = 27000000, 30 .rate = 27000000,
31}; 31};
32 32
33static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
34{
35 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
36}
37
38static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
39{
40 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
41}
42
33/* Core list of CMU_CPU side */ 43/* Core list of CMU_CPU side */
34 44
35static struct clksrc_clk clk_mout_apll = { 45static struct clksrc_clk clk_mout_apll = {
@@ -39,6 +49,14 @@ static struct clksrc_clk clk_mout_apll = {
39 }, 49 },
40 .sources = &clk_src_apll, 50 .sources = &clk_src_apll,
41 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 }, 51 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
52};
53
54static struct clksrc_clk clk_sclk_apll = {
55 .clk = {
56 .name = "sclk_apll",
57 .id = -1,
58 .parent = &clk_mout_apll.clk,
59 },
42 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 }, 60 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
43}; 61};
44 62
@@ -61,7 +79,7 @@ static struct clksrc_clk clk_mout_mpll = {
61}; 79};
62 80
63static struct clk *clkset_moutcore_list[] = { 81static struct clk *clkset_moutcore_list[] = {
64 [0] = &clk_mout_apll.clk, 82 [0] = &clk_sclk_apll.clk,
65 [1] = &clk_mout_mpll.clk, 83 [1] = &clk_mout_mpll.clk,
66}; 84};
67 85
@@ -154,7 +172,7 @@ static struct clksrc_clk clk_pclk_dbg = {
154 172
155static struct clk *clkset_corebus_list[] = { 173static struct clk *clkset_corebus_list[] = {
156 [0] = &clk_mout_mpll.clk, 174 [0] = &clk_mout_mpll.clk,
157 [1] = &clk_mout_apll.clk, 175 [1] = &clk_sclk_apll.clk,
158}; 176};
159 177
160static struct clksrc_sources clkset_mout_corebus = { 178static struct clksrc_sources clkset_mout_corebus = {
@@ -220,7 +238,7 @@ static struct clksrc_clk clk_pclk_acp = {
220 238
221static struct clk *clkset_aclk_top_list[] = { 239static struct clk *clkset_aclk_top_list[] = {
222 [0] = &clk_mout_mpll.clk, 240 [0] = &clk_mout_mpll.clk,
223 [1] = &clk_mout_apll.clk, 241 [1] = &clk_sclk_apll.clk,
224}; 242};
225 243
226static struct clksrc_sources clkset_aclk_200 = { 244static struct clksrc_sources clkset_aclk_200 = {
@@ -321,11 +339,6 @@ static struct clksrc_clk clk_sclk_vpll = {
321 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 }, 339 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
322}; 340};
323 341
324static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
325{
326 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
327}
328
329static struct clk init_clocks_disable[] = { 342static struct clk init_clocks_disable[] = {
330 { 343 {
331 .name = "timers", 344 .name = "timers",
@@ -337,7 +350,37 @@ static struct clk init_clocks_disable[] = {
337}; 350};
338 351
339static struct clk init_clocks[] = { 352static struct clk init_clocks[] = {
340 /* Nothing here yet */ 353 {
354 .name = "uart",
355 .id = 0,
356 .enable = s5pv310_clk_ip_peril_ctrl,
357 .ctrlbit = (1 << 0),
358 }, {
359 .name = "uart",
360 .id = 1,
361 .enable = s5pv310_clk_ip_peril_ctrl,
362 .ctrlbit = (1 << 1),
363 }, {
364 .name = "uart",
365 .id = 2,
366 .enable = s5pv310_clk_ip_peril_ctrl,
367 .ctrlbit = (1 << 2),
368 }, {
369 .name = "uart",
370 .id = 3,
371 .enable = s5pv310_clk_ip_peril_ctrl,
372 .ctrlbit = (1 << 3),
373 }, {
374 .name = "uart",
375 .id = 4,
376 .enable = s5pv310_clk_ip_peril_ctrl,
377 .ctrlbit = (1 << 4),
378 }, {
379 .name = "uart",
380 .id = 5,
381 .enable = s5pv310_clk_ip_peril_ctrl,
382 .ctrlbit = (1 << 5),
383 }
341}; 384};
342 385
343static struct clk *clkset_group_list[] = { 386static struct clk *clkset_group_list[] = {
@@ -359,8 +402,8 @@ static struct clksrc_clk clksrcs[] = {
359 .clk = { 402 .clk = {
360 .name = "uclk1", 403 .name = "uclk1",
361 .id = 0, 404 .id = 0,
405 .enable = s5pv310_clksrc_mask_peril0_ctrl,
362 .ctrlbit = (1 << 0), 406 .ctrlbit = (1 << 0),
363 .enable = s5pv310_clk_ip_peril_ctrl,
364 }, 407 },
365 .sources = &clkset_group, 408 .sources = &clkset_group,
366 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 }, 409 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
@@ -369,8 +412,8 @@ static struct clksrc_clk clksrcs[] = {
369 .clk = { 412 .clk = {
370 .name = "uclk1", 413 .name = "uclk1",
371 .id = 1, 414 .id = 1,
372 .enable = s5pv310_clk_ip_peril_ctrl, 415 .enable = s5pv310_clksrc_mask_peril0_ctrl,
373 .ctrlbit = (1 << 1), 416 .ctrlbit = (1 << 4),
374 }, 417 },
375 .sources = &clkset_group, 418 .sources = &clkset_group,
376 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 }, 419 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
@@ -379,8 +422,8 @@ static struct clksrc_clk clksrcs[] = {
379 .clk = { 422 .clk = {
380 .name = "uclk1", 423 .name = "uclk1",
381 .id = 2, 424 .id = 2,
382 .enable = s5pv310_clk_ip_peril_ctrl, 425 .enable = s5pv310_clksrc_mask_peril0_ctrl,
383 .ctrlbit = (1 << 2), 426 .ctrlbit = (1 << 8),
384 }, 427 },
385 .sources = &clkset_group, 428 .sources = &clkset_group,
386 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 }, 429 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
@@ -389,8 +432,8 @@ static struct clksrc_clk clksrcs[] = {
389 .clk = { 432 .clk = {
390 .name = "uclk1", 433 .name = "uclk1",
391 .id = 3, 434 .id = 3,
392 .enable = s5pv310_clk_ip_peril_ctrl, 435 .enable = s5pv310_clksrc_mask_peril0_ctrl,
393 .ctrlbit = (1 << 3), 436 .ctrlbit = (1 << 12),
394 }, 437 },
395 .sources = &clkset_group, 438 .sources = &clkset_group,
396 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 }, 439 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
@@ -399,7 +442,7 @@ static struct clksrc_clk clksrcs[] = {
399 .clk = { 442 .clk = {
400 .name = "sclk_pwm", 443 .name = "sclk_pwm",
401 .id = -1, 444 .id = -1,
402 .enable = s5pv310_clk_ip_peril_ctrl, 445 .enable = s5pv310_clksrc_mask_peril0_ctrl,
403 .ctrlbit = (1 << 24), 446 .ctrlbit = (1 << 24),
404 }, 447 },
405 .sources = &clkset_group, 448 .sources = &clkset_group,
@@ -411,6 +454,7 @@ static struct clksrc_clk clksrcs[] = {
411/* Clock initialization code */ 454/* Clock initialization code */
412static struct clksrc_clk *sysclks[] = { 455static struct clksrc_clk *sysclks[] = {
413 &clk_mout_apll, 456 &clk_mout_apll,
457 &clk_sclk_apll,
414 &clk_mout_epll, 458 &clk_mout_epll,
415 &clk_mout_mpll, 459 &clk_mout_mpll,
416 &clk_moutcore, 460 &clk_moutcore,
@@ -470,11 +514,11 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
470 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508); 514 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
471 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508); 515 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
472 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0), 516 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
473 __raw_readl(S5P_EPLL_CON1), pll_4500); 517 __raw_readl(S5P_EPLL_CON1), pll_4600);
474 518
475 vpllsrc = clk_get_rate(&clk_vpllsrc.clk); 519 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
476 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), 520 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
477 __raw_readl(S5P_VPLL_CON1), pll_4502); 521 __raw_readl(S5P_VPLL_CON1), pll_4650);
478 522
479 clk_fout_apll.rate = apll; 523 clk_fout_apll.rate = apll;
480 clk_fout_mpll.rate = mpll; 524 clk_fout_mpll.rate = mpll;
diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c
index 196c9f12ed85..e5b261a99ab2 100644
--- a/arch/arm/mach-s5pv310/cpu.c
+++ b/arch/arm/mach-s5pv310/cpu.c
@@ -45,6 +45,16 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
45 .pfn = __phys_to_pfn(S5PV310_PA_L2CC), 45 .pfn = __phys_to_pfn(S5PV310_PA_L2CC),
46 .length = SZ_4K, 46 .length = SZ_4K,
47 .type = MT_DEVICE, 47 .type = MT_DEVICE,
48 }, {
49 .virtual = (unsigned long)S5P_VA_SYSRAM,
50 .pfn = __phys_to_pfn(S5PV310_PA_SYSRAM),
51 .length = SZ_4K,
52 .type = MT_DEVICE,
53 }, {
54 .virtual = (unsigned long)S5P_VA_CMU,
55 .pfn = __phys_to_pfn(S5PV310_PA_CMU),
56 .length = SZ_128K,
57 .type = MT_DEVICE,
48 }, 58 },
49}; 59};
50 60
diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-s5pv310/include/mach/irqs.h
index 56885ca3773c..4cdedda6e652 100644
--- a/arch/arm/mach-s5pv310/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv310/include/mach/irqs.h
@@ -15,12 +15,14 @@
15 15
16#include <plat/irqs.h> 16#include <plat/irqs.h>
17 17
18/* Private Peripheral Interrupt */ 18/* PPI: Private Peripheral Interrupt */
19
19#define IRQ_PPI(x) S5P_IRQ(x+16) 20#define IRQ_PPI(x) S5P_IRQ(x+16)
20 21
21#define IRQ_LOCALTIMER IRQ_PPI(13) 22#define IRQ_LOCALTIMER IRQ_PPI(13)
22 23
23/* Shared Peripheral Interrupt */ 24/* SPI: Shared Peripheral Interrupt */
25
24#define IRQ_SPI(x) S5P_IRQ(x+32) 26#define IRQ_SPI(x) S5P_IRQ(x+32)
25 27
26#define IRQ_EINT0 IRQ_SPI(40) 28#define IRQ_EINT0 IRQ_SPI(40)
@@ -36,7 +38,7 @@
36#define IRQ_PCIE IRQ_SPI(50) 38#define IRQ_PCIE IRQ_SPI(50)
37#define IRQ_SYSTEM_TIMER IRQ_SPI(51) 39#define IRQ_SYSTEM_TIMER IRQ_SPI(51)
38#define IRQ_MFC IRQ_SPI(52) 40#define IRQ_MFC IRQ_SPI(52)
39#define IRQ_WTD IRQ_SPI(53) 41#define IRQ_WDT IRQ_SPI(53)
40#define IRQ_AUDIO_SS IRQ_SPI(54) 42#define IRQ_AUDIO_SS IRQ_SPI(54)
41#define IRQ_AC97 IRQ_SPI(55) 43#define IRQ_AC97 IRQ_SPI(55)
42#define IRQ_SPDIF IRQ_SPI(56) 44#define IRQ_SPDIF IRQ_SPI(56)
@@ -67,8 +69,9 @@
67#define IRQ_IIC COMBINER_IRQ(27, 0) 69#define IRQ_IIC COMBINER_IRQ(27, 0)
68 70
69/* Set the default NR_IRQS */ 71/* Set the default NR_IRQS */
72
70#define NR_IRQS COMBINER_IRQ(MAX_COMBINER_NR, 0) 73#define NR_IRQS COMBINER_IRQ(MAX_COMBINER_NR, 0)
71 74
72#define MAX_COMBINER_NR 39 75#define MAX_COMBINER_NR 39
73 76
74#endif /* ASM_ARCH_IRQS_H */ 77#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h
index 87697c9fca5b..213e1101a3b3 100644
--- a/arch/arm/mach-s5pv310/include/mach/map.h
+++ b/arch/arm/mach-s5pv310/include/mach/map.h
@@ -23,12 +23,16 @@
23 23
24#include <plat/map-s5p.h> 24#include <plat/map-s5p.h>
25 25
26#define S5PV310_PA_SYSRAM (0x02025000)
27
26#define S5PV310_PA_CHIPID (0x10000000) 28#define S5PV310_PA_CHIPID (0x10000000)
27#define S5P_PA_CHIPID S5PV310_PA_CHIPID 29#define S5P_PA_CHIPID S5PV310_PA_CHIPID
28 30
29#define S5PV310_PA_SYSCON (0x10020000) 31#define S5PV310_PA_SYSCON (0x10020000)
30#define S5P_PA_SYSCON S5PV310_PA_SYSCON 32#define S5P_PA_SYSCON S5PV310_PA_SYSCON
31 33
34#define S5PV310_PA_CMU (0x10030000)
35
32#define S5PV310_PA_WATCHDOG (0x10060000) 36#define S5PV310_PA_WATCHDOG (0x10060000)
33 37
34#define S5PV310_PA_COMBINER (0x10448000) 38#define S5PV310_PA_COMBINER (0x10448000)
@@ -39,8 +43,12 @@
39#define S5PV310_PA_GIC_DIST (0x10501000) 43#define S5PV310_PA_GIC_DIST (0x10501000)
40#define S5PV310_PA_L2CC (0x10502000) 44#define S5PV310_PA_L2CC (0x10502000)
41 45
42#define S5PV310_PA_GPIO (0x11000000) 46#define S5PV310_PA_GPIO1 (0x11400000)
43#define S5P_PA_GPIO S5PV310_PA_GPIO 47#define S5PV310_PA_GPIO2 (0x11000000)
48#define S5PV310_PA_GPIO3 (0x03860000)
49#define S5P_PA_GPIO S5PV310_PA_GPIO1
50
51#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
44 52
45#define S5PV310_PA_UART (0x13800000) 53#define S5PV310_PA_UART (0x13800000)
46 54
@@ -63,6 +71,10 @@
63 71
64/* compatibiltiy defines. */ 72/* compatibiltiy defines. */
65#define S3C_PA_UART S5PV310_PA_UART 73#define S3C_PA_UART S5PV310_PA_UART
74#define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0)
75#define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1)
76#define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2)
77#define S3C_PA_HSMMC3 S5PV310_PA_HSMMC(3)
66#define S3C_PA_IIC S5PV310_PA_IIC0 78#define S3C_PA_IIC S5PV310_PA_IIC0
67#define S3C_PA_WDT S5PV310_PA_WATCHDOG 79#define S3C_PA_WDT S5PV310_PA_WATCHDOG
68 80
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-clock.h b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
index 59e3a7e94d80..4013553cd9be 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
@@ -15,48 +15,49 @@
15 15
16#include <mach/map.h> 16#include <mach/map.h>
17 17
18#define S5P_CLKREG(x) (S3C_VA_SYS + (x)) 18#define S5P_CLKREG(x) (S5P_VA_CMU + (x))
19 19
20#define S5P_INFORM0 S5P_CLKREG(0x800) 20#define S5P_INFORM0 S5P_CLKREG(0x800)
21 21
22#define S5P_EPLL_CON0 S5P_CLKREG(0x1C110) 22#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
23#define S5P_EPLL_CON1 S5P_CLKREG(0x1C114) 23#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
24#define S5P_VPLL_CON0 S5P_CLKREG(0x1C120) 24#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
25#define S5P_VPLL_CON1 S5P_CLKREG(0x1C124) 25#define S5P_VPLL_CON1 S5P_CLKREG(0x0C124)
26 26
27#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x1C210) 27#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
28#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x1C214) 28#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
29 29
30#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x1C250) 30#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250)
31 31
32#define S5P_CLKDIV_TOP S5P_CLKREG(0x1C510) 32#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510)
33 33
34#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x1C550) 34#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550)
35#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x1C554) 35#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x0C554)
36#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x1C558) 36#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x0C558)
37#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x1C55C) 37#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C)
38#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x1C560) 38#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560)
39#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x1C564) 39#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
40 40
41#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x1C950) 41#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
42 42
43#define S5P_CLKSRC_CORE S5P_CLKREG(0x20200) 43#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
44 44
45#define S5P_CLKDIV_CORE0 S5P_CLKREG(0x20500) 45#define S5P_CLKSRC_CORE S5P_CLKREG(0x10200)
46#define S5P_CLKDIV_CORE0 S5P_CLKREG(0x10500)
46 47
47#define S5P_APLL_LOCK S5P_CLKREG(0x24000) 48#define S5P_APLL_LOCK S5P_CLKREG(0x14000)
48#define S5P_MPLL_LOCK S5P_CLKREG(0x24004) 49#define S5P_MPLL_LOCK S5P_CLKREG(0x14004)
49#define S5P_APLL_CON0 S5P_CLKREG(0x24100) 50#define S5P_APLL_CON0 S5P_CLKREG(0x14100)
50#define S5P_APLL_CON1 S5P_CLKREG(0x24104) 51#define S5P_APLL_CON1 S5P_CLKREG(0x14104)
51#define S5P_MPLL_CON0 S5P_CLKREG(0x24108) 52#define S5P_MPLL_CON0 S5P_CLKREG(0x14108)
52#define S5P_MPLL_CON1 S5P_CLKREG(0x2410C) 53#define S5P_MPLL_CON1 S5P_CLKREG(0x1410C)
53 54
54#define S5P_CLKSRC_CPU S5P_CLKREG(0x24200) 55#define S5P_CLKSRC_CPU S5P_CLKREG(0x14200)
55#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x24400) 56#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400)
56 57
57#define S5P_CLKDIV_CPU S5P_CLKREG(0x24500) 58#define S5P_CLKDIV_CPU S5P_CLKREG(0x14500)
58#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x24600) 59#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600)
59 60
60#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x24800) 61#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800)
61 62
62#endif /* __ASM_ARCH_REGS_CLOCK_H */ 63#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/vmalloc.h b/arch/arm/mach-s5pv310/include/mach/vmalloc.h
index 3f565ebb7daa..256f221edf3a 100644
--- a/arch/arm/mach-s5pv310/include/mach/vmalloc.h
+++ b/arch/arm/mach-s5pv310/include/mach/vmalloc.h
@@ -17,6 +17,6 @@
17#ifndef __ASM_ARCH_VMALLOC_H 17#ifndef __ASM_ARCH_VMALLOC_H
18#define __ASM_ARCH_VMALLOC_H __FILE__ 18#define __ASM_ARCH_VMALLOC_H __FILE__
19 19
20#define VMALLOC_END (0xF0000000) 20#define VMALLOC_END (0xF0000000UL)
21 21
22#endif /* __ASM_ARCH_VMALLOC_H */ 22#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5pv310/platsmp.c b/arch/arm/mach-s5pv310/platsmp.c
index fe9469abd006..d357c198edee 100644
--- a/arch/arm/mach-s5pv310/platsmp.c
+++ b/arch/arm/mach-s5pv310/platsmp.c
@@ -187,6 +187,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
187 * until it receives a soft interrupt, and then the 187 * until it receives a soft interrupt, and then the
188 * secondary CPU branches to this address. 188 * secondary CPU branches to this address.
189 */ 189 */
190 __raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_INFORM0); 190 __raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_VA_SYSRAM);
191 } 191 }
192} 192}
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
index 05e78dd9b50c..9e305de56be9 100644
--- a/arch/arm/mach-tegra/board-harmony.c
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -91,10 +91,8 @@ static void __init tegra_harmony_fixup(struct machine_desc *desc,
91{ 91{
92 mi->nr_banks = 2; 92 mi->nr_banks = 2;
93 mi->bank[0].start = PHYS_OFFSET; 93 mi->bank[0].start = PHYS_OFFSET;
94 mi->bank[0].node = PHYS_TO_NID(PHYS_OFFSET);
95 mi->bank[0].size = 448 * SZ_1M; 94 mi->bank[0].size = 448 * SZ_1M;
96 mi->bank[1].start = SZ_512M; 95 mi->bank[1].start = SZ_512M;
97 mi->bank[1].node = PHYS_TO_NID(SZ_512M);
98 mi->bank[1].size = SZ_512M; 96 mi->bank[1].size = SZ_512M;
99} 97}
100 98
diff --git a/arch/arm/mach-tegra/include/mach/vmalloc.h b/arch/arm/mach-tegra/include/mach/vmalloc.h
index 267a141730d9..fd6aa65b2dc6 100644
--- a/arch/arm/mach-tegra/include/mach/vmalloc.h
+++ b/arch/arm/mach-tegra/include/mach/vmalloc.h
@@ -23,6 +23,6 @@
23 23
24#include <asm/sizes.h> 24#include <asm/sizes.h>
25 25
26#define VMALLOC_END 0xFE000000 26#define VMALLOC_END 0xFE000000UL
27 27
28#endif 28#endif
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
index 6a3ff65c0303..5177a9c5a25a 100644
--- a/arch/arm/plat-omap/include/plat/smp.h
+++ b/arch/arm/plat-omap/include/plat/smp.h
@@ -19,13 +19,6 @@
19 19
20#include <asm/hardware/gic.h> 20#include <asm/hardware/gic.h>
21 21
22/*
23 * set_event() is used to wake up secondary core from wfe using sev. ROM
24 * code puts the second core into wfe(standby).
25 *
26 */
27#define set_event() __asm__ __volatile__ ("sev" : : : "memory")
28
29/* Needed for secondary core boot */ 22/* Needed for secondary core boot */
30extern void omap_secondary_startup(void); 23extern void omap_secondary_startup(void);
31extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); 24extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h
index 54e9fb9d315e..c4ff88bf6477 100644
--- a/arch/arm/plat-s5p/include/plat/map-s5p.h
+++ b/arch/arm/plat-s5p/include/plat/map-s5p.h
@@ -17,6 +17,7 @@
17#define S5P_VA_GPIO S3C_ADDR(0x00500000) 17#define S5P_VA_GPIO S3C_ADDR(0x00500000)
18#define S5P_VA_SYSTIMER S3C_ADDR(0x01200000) 18#define S5P_VA_SYSTIMER S3C_ADDR(0x01200000)
19#define S5P_VA_SROMC S3C_ADDR(0x01100000) 19#define S5P_VA_SROMC S3C_ADDR(0x01100000)
20#define S5P_VA_SYSRAM S3C_ADDR(0x01180000)
20 21
21#define S5P_VA_COMBINER_BASE S3C_ADDR(0x00600000) 22#define S5P_VA_COMBINER_BASE S3C_ADDR(0x00600000)
22#define S5P_VA_COMBINER(x) (S5P_VA_COMBINER_BASE + ((x) >> 2) * 0x10) 23#define S5P_VA_COMBINER(x) (S5P_VA_COMBINER_BASE + ((x) >> 2) * 0x10)
@@ -29,6 +30,7 @@
29#define S5P_VA_GIC_DIST S5P_VA_COREPERI(0x1000) 30#define S5P_VA_GIC_DIST S5P_VA_COREPERI(0x1000)
30 31
31#define S5P_VA_L2CC S3C_ADDR(0x00900000) 32#define S5P_VA_L2CC S3C_ADDR(0x00900000)
33#define S5P_VA_CMU S3C_ADDR(0x00920000)
32 34
33#define S5P_VA_UART(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) 35#define S5P_VA_UART(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
34#define S5P_VA_UART0 S5P_VA_UART(0) 36#define S5P_VA_UART0 S5P_VA_UART(0)
diff --git a/arch/arm/plat-samsung/dev-hsmmc.c b/arch/arm/plat-samsung/dev-hsmmc.c
index b0f93f11e281..9d2be0941410 100644
--- a/arch/arm/plat-samsung/dev-hsmmc.c
+++ b/arch/arm/plat-samsung/dev-hsmmc.c
@@ -70,4 +70,6 @@ void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
70 set->cfg_gpio = pd->cfg_gpio; 70 set->cfg_gpio = pd->cfg_gpio;
71 if (pd->cfg_card) 71 if (pd->cfg_card)
72 set->cfg_card = pd->cfg_card; 72 set->cfg_card = pd->cfg_card;
73 if (pd->host_caps)
74 set->host_caps = pd->host_caps;
73} 75}
diff --git a/arch/arm/plat-samsung/dev-hsmmc1.c b/arch/arm/plat-samsung/dev-hsmmc1.c
index 1504fd802865..a6c8295840af 100644
--- a/arch/arm/plat-samsung/dev-hsmmc1.c
+++ b/arch/arm/plat-samsung/dev-hsmmc1.c
@@ -70,4 +70,6 @@ void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
70 set->cfg_gpio = pd->cfg_gpio; 70 set->cfg_gpio = pd->cfg_gpio;
71 if (pd->cfg_card) 71 if (pd->cfg_card)
72 set->cfg_card = pd->cfg_card; 72 set->cfg_card = pd->cfg_card;
73 if (pd->host_caps)
74 set->host_caps = pd->host_caps;
73} 75}
diff --git a/arch/arm/plat-samsung/dev-hsmmc2.c b/arch/arm/plat-samsung/dev-hsmmc2.c
index b28ef173444d..cb0d7143381a 100644
--- a/arch/arm/plat-samsung/dev-hsmmc2.c
+++ b/arch/arm/plat-samsung/dev-hsmmc2.c
@@ -71,4 +71,6 @@ void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
71 set->cfg_gpio = pd->cfg_gpio; 71 set->cfg_gpio = pd->cfg_gpio;
72 if (pd->cfg_card) 72 if (pd->cfg_card)
73 set->cfg_card = pd->cfg_card; 73 set->cfg_card = pd->cfg_card;
74 if (pd->host_caps)
75 set->host_caps = pd->host_caps;
74} 76}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-02 20:08:58 -0500