Merge tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC cleanups from Olof Johansson:
 "This branch contains code cleanups, moves and removals for 3.12.

  There's a large number of various cleanups, and a nice net removal of
  13500 lines of code.

  Highlights worth mentioning are:

   - A series of patches from Stephen Boyd removing the ARM local timer
     API.
   - Move of Qualcomm MSM IOMMU code to drivers/iommu.
   - Samsung PWM driver cleanups from Tomasz Figa, removing legacy PWM
     driver and switching over to the drivers/pwm one.
   - Removal of some unusued auto-generated headers for OMAP2+ (PRM/CM).

  There's also a move of a header file out of include/linux/i2c/ to
  platform_data, where it really belongs.  It touches mostly ARM
  platform code for include changes so we took it through our tree"

* tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (83 commits)
  ARM: OMAP2+: Add back the define for AM33XX_RST_GLOBAL_WARM_SW_MASK
  gpio: (gpio-pca953x) move header to linux/platform_data/
  arm: zynq: hotplug: Remove unreachable code
  ARM: SAMSUNG: Remove unnecessary exynos4_default_sdhci*()
  tegra: simplify use of devm_ioremap_resource
  ARM: SAMSUNG: Remove plat/regs-timer.h header
  ARM: SAMSUNG: Remove remaining uses of plat/regs-timer.h header
  ARM: SAMSUNG: Remove pwm-clock infrastructure
  ARM: SAMSUNG: Remove old PWM timer platform devices
  pwm: Remove superseded pwm-samsung-legacy driver
  ARM: SAMSUNG: Modify board files to use new PWM platform device
  ARM: SAMSUNG: Rework private data handling in dev-backlight
  pwm: Add new pwm-samsung driver
  ARM: mach-mvebu: remove redundant DT parsing and validation
  ARM: msm: Only compile io.c on platforms that use it
  iommu/msm: Move mach includes to iommu directory
  ARM: msm: Remove devices-iommu.c
  ARM: msm: Move mach/board.h contents to common.h
  ARM: msm: Migrate msm_timer to CLOCKSOURCE_OF_DECLARE
  ARM: msm: Remove TMR and TMR0 static mappings
  ...

150 files changed, 613 insertions, 16350 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5d1f5704a284..bf7976439c39 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -631,6 +631,7 @@ config ARCH_MSM
         bool "Qualcomm MSM"
         select ARCH_REQUIRE_GPIOLIB
         select CLKDEV_LOOKUP
+        select CLKSRC_OF if OF
         select COMMON_CLK
         select GENERIC_CLOCKEVENTS
         help
@@ -646,7 +647,7 @@ config ARCH_SHMOBILE
         select CLKDEV_LOOKUP
         select GENERIC_CLOCKEVENTS
         select HAVE_ARM_SCU if SMP
-        select HAVE_ARM_TWD if LOCAL_TIMERS
+        select HAVE_ARM_TWD if SMP
         select HAVE_CLK
         select HAVE_MACH_CLKDEV
         select HAVE_SMP
@@ -701,7 +702,7 @@ config ARCH_S3C24XX
         select ARCH_HAS_CPUFREQ
         select ARCH_REQUIRE_GPIOLIB
         select CLKDEV_LOOKUP
-        select CLKSRC_MMIO
+        select CLKSRC_SAMSUNG_PWM
         select GENERIC_CLOCKEVENTS
         select GPIO_SAMSUNG
         select HAVE_CLK
@@ -724,7 +725,7 @@ config ARCH_S3C64XX
         select ARCH_REQUIRE_GPIOLIB
         select ARM_VIC
         select CLKDEV_LOOKUP
-        select CLKSRC_MMIO
+        select CLKSRC_SAMSUNG_PWM
         select CPU_V6
         select GENERIC_CLOCKEVENTS
         select GPIO_SAMSUNG
@@ -740,7 +741,6 @@ config ARCH_S3C64XX
         select SAMSUNG_ATAGS
         select SAMSUNG_CLKSRC
         select SAMSUNG_GPIOLIB_4BIT
-        select SAMSUNG_IRQ_VIC_TIMER
         select SAMSUNG_WDT_RESET
         select USB_ARCH_HAS_OHCI
         help
@@ -749,7 +749,7 @@ config ARCH_S3C64XX
 config ARCH_S5P64X0
         bool "Samsung S5P6440 S5P6450"
         select CLKDEV_LOOKUP
-        select CLKSRC_MMIO
+        select CLKSRC_SAMSUNG_PWM
         select CPU_V6
         select GENERIC_CLOCKEVENTS
         select GPIO_SAMSUNG
@@ -768,7 +768,7 @@ config ARCH_S5PC100
         bool "Samsung S5PC100"
         select ARCH_REQUIRE_GPIOLIB
         select CLKDEV_LOOKUP
-        select CLKSRC_MMIO
+        select CLKSRC_SAMSUNG_PWM
         select CPU_V7
         select GENERIC_CLOCKEVENTS
         select GPIO_SAMSUNG
@@ -788,7 +788,7 @@ config ARCH_S5PV210
         select ARCH_HAS_HOLES_MEMORYMODEL
         select ARCH_SPARSEMEM_ENABLE
         select CLKDEV_LOOKUP
-        select CLKSRC_MMIO
+        select CLKSRC_SAMSUNG_PWM
         select CPU_V7
         select GENERIC_CLOCKEVENTS
         select GPIO_SAMSUNG
@@ -1594,16 +1594,6 @@ config ARM_PSCI
           0022A ("Power State Coordination Interface System Software on
           ARM processors").
 
-config LOCAL_TIMERS
-        bool "Use local timer interrupts"
-        depends on SMP
-        default y
-        help
-          Enable support for local timers on SMP platforms, rather then the
-          legacy IPI broadcast method.  Local timers allows the system
-          accounting to be spread across the timer interval, preventing a
-          "thundering herd" at every timer tick.
-
 # The GPIO number here must be sorted by descending number. In case of
 # a multiplatform kernel, we just want the highest value required by the
 # selected platforms.
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 4137529850cb..9762c84b4198 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -895,6 +895,11 @@ config DEBUG_LL_INCLUDE
                                  DEBUG_IMX53_UART ||\
                                  DEBUG_IMX6Q_UART || \
                                  DEBUG_IMX6SL_UART
+        default "debug/msm.S" if DEBUG_MSM_UART1 || \
+                                 DEBUG_MSM_UART2 || \
+                                 DEBUG_MSM_UART3 || \
+                                 DEBUG_MSM8660_UART || \
+                                 DEBUG_MSM8960_UART
         default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
         default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
         default "debug/sti.S" if DEBUG_STI_UART
@@ -1056,7 +1061,7 @@ config DEBUG_UART_8250_FLOW_CONTROL
 
 config DEBUG_UNCOMPRESS
         bool
-        depends on ARCH_MULTIPLATFORM
+        depends on ARCH_MULTIPLATFORM || ARCH_MSM
         default y if DEBUG_LL && !DEBUG_OMAP2PLUS_UART && \
                      (!DEBUG_TEGRA_UART || !ZBOOT_ROM)
         help
@@ -1072,7 +1077,7 @@ config DEBUG_UNCOMPRESS
 
 config UNCOMPRESS_INCLUDE
         string
-        default "debug/uncompress.h" if ARCH_MULTIPLATFORM
+        default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM
         default "mach/uncompress.h"
 
 config EARLY_PRINTK
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index b7f358a93bcb..53e25273ca74 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -72,7 +72,7 @@
                 };
         };
 
-        clock: clock-controller@0x10030000 {
+        clock: clock-controller@10030000 {
                 compatible = "samsung,exynos4210-clock";
                 reg = <0x10030000 0x20000>;
                 #clock-cells = <1>;
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 01da194ba329..3aa2f060ba61 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -28,7 +28,7 @@
                 pinctrl3 = &pinctrl_3;
         };
 
-        clock: clock-controller@0x10030000 {
+        clock: clock-controller@10030000 {
                 compatible = "samsung,exynos4412-clock";
                 reg = <0x10030000 0x20000>;
                 #clock-cells = <1>;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 376090f07231..f2dfa6b1f1a1 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -68,17 +68,17 @@
                 };
         };
 
-        pd_gsc: gsc-power-domain@0x10044000 {
+        pd_gsc: gsc-power-domain@10044000 {
                 compatible = "samsung,exynos4210-pd";
                 reg = <0x10044000 0x20>;
         };
 
-        pd_mfc: mfc-power-domain@0x10044040 {
+        pd_mfc: mfc-power-domain@10044040 {
                 compatible = "samsung,exynos4210-pd";
                 reg = <0x10044040 0x20>;
         };
 
-        clock: clock-controller@0x10010000 {
+        clock: clock-controller@10010000 {
                 compatible = "samsung,exynos5250-clock";
                 reg = <0x10010000 0x30000>;
                 #clock-cells = <1>;
@@ -559,7 +559,7 @@
                 };
         };
 
-        gsc_0:  gsc@0x13e00000 {
+        gsc_0:  gsc@13e00000 {
                 compatible = "samsung,exynos5-gsc";
                 reg = <0x13e00000 0x1000>;
                 interrupts = <0 85 0>;
@@ -568,7 +568,7 @@
                 clock-names = "gscl";
         };
 
-        gsc_1:  gsc@0x13e10000 {
+        gsc_1:  gsc@13e10000 {
                 compatible = "samsung,exynos5-gsc";
                 reg = <0x13e10000 0x1000>;
                 interrupts = <0 86 0>;
@@ -577,7 +577,7 @@
                 clock-names = "gscl";
         };
 
-        gsc_2:  gsc@0x13e20000 {
+        gsc_2:  gsc@13e20000 {
                 compatible = "samsung,exynos5-gsc";
                 reg = <0x13e20000 0x1000>;
                 interrupts = <0 87 0>;
@@ -586,7 +586,7 @@
                 clock-names = "gscl";
         };
 
-        gsc_3:  gsc@0x13e30000 {
+        gsc_3:  gsc@13e30000 {
                 compatible = "samsung,exynos5-gsc";
                 reg = <0x13e30000 0x1000>;
                 interrupts = <0 88 0>;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 8c54c4b74f0e..9e90d1ec0c28 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -59,7 +59,7 @@
                 };
         };
 
-        clock: clock-controller@0x10010000 {
+        clock: clock-controller@10010000 {
                 compatible = "samsung,exynos5420-clock";
                 reg = <0x10010000 0x30000>;
                 #clock-cells = <1>;
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 586134e2a382..1b81f36896bc 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -20,7 +20,7 @@
                 spi0 = &spi_0;
         };
 
-        clock: clock-controller@0x160000 {
+        clock: clock-controller@160000 {
                 compatible = "samsung,exynos5440-clock";
                 reg = <0x160000 0x1000>;
                 #clock-cells = <1>;
diff --git a/arch/arm/configs/exynos4_defconfig b/arch/arm/configs/exynos4_defconfig
deleted file mode 100644
index bffe68e190a3..000000000000
--- a/arch/arm/configs/exynos4_defconfig
+++ /dev/null
@@ -1,68 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_EXYNOS=y
-CONFIG_S3C_LOWLEVEL_UART_PORT=1
-CONFIG_MACH_SMDKC210=y
-CONFIG_MACH_ARMLEX4210=y
-CONFIG_MACH_UNIVERSAL_C210=y
-CONFIG_MACH_NURI=y
-CONFIG_MACH_ORIGEN=y
-CONFIG_MACH_SMDK4412=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M"
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_SAMSUNG=y
-CONFIG_SERIAL_SAMSUNG_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-# CONFIG_HWMON is not set
-# CONFIG_MFD_SUPPORT is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_EXT2_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_CRAMFS=y
-CONFIG_ROMFS_FS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_RT_MUTEXES=y
-CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_MUTEXES=y
-CONFIG_DEBUG_INFO=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CRC_CCITT=y
diff --git a/arch/arm/include/asm/localtimer.h b/arch/arm/include/asm/localtimer.h
deleted file mode 100644
index f77ffc1eb0c2..000000000000
--- a/arch/arm/include/asm/localtimer.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- *  arch/arm/include/asm/localtimer.h
- *
- *  Copyright (C) 2004-2005 ARM Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARM_LOCALTIMER_H
-#define __ASM_ARM_LOCALTIMER_H
-
-#include <linux/errno.h>
-
-struct clock_event_device;
-
-struct local_timer_ops {
-        int  (*setup)(struct clock_event_device *);
-        void (*stop)(struct clock_event_device *);
-};
-
-#ifdef CONFIG_LOCAL_TIMERS
-/*
- * Register a local timer driver
- */
-int local_timer_register(struct local_timer_ops *);
-#else
-static inline int local_timer_register(struct local_timer_ops *ops)
-{
-        return -ENXIO;
-}
-#endif
-
-#endif
diff --git a/arch/arm/mach-msm/include/mach/debug-macro.S b/arch/arm/include/debug/msm.S
index 0e05f88abcd5..9166e1bc470e 100644
--- a/arch/arm/mach-msm/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/msm.S
@@ -15,8 +15,36 @@
  *
  */
 
-#include <mach/hardware.h>
-#include <mach/msm_iomap.h>
+#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_QSD8X50)
+#define MSM_UART1_PHYS        0xA9A00000
+#define MSM_UART2_PHYS        0xA9B00000
+#define MSM_UART3_PHYS        0xA9C00000
+#elif defined(CONFIG_ARCH_MSM7X30)
+#define MSM_UART1_PHYS        0xACA00000
+#define MSM_UART2_PHYS        0xACB00000
+#define MSM_UART3_PHYS        0xACC00000
+#endif
+
+#if defined(CONFIG_DEBUG_MSM_UART1)
+#define MSM_DEBUG_UART_BASE     0xE1000000
+#define MSM_DEBUG_UART_PHYS     MSM_UART1_PHYS
+#elif defined(CONFIG_DEBUG_MSM_UART2)
+#define MSM_DEBUG_UART_BASE     0xE1000000
+#define MSM_DEBUG_UART_PHYS     MSM_UART2_PHYS
+#elif defined(CONFIG_DEBUG_MSM_UART3)
+#define MSM_DEBUG_UART_BASE     0xE1000000
+#define MSM_DEBUG_UART_PHYS     MSM_UART3_PHYS
+#endif
+
+#ifdef CONFIG_DEBUG_MSM8660_UART
+#define MSM_DEBUG_UART_BASE     0xF0040000
+#define MSM_DEBUG_UART_PHYS     0x19C40000
+#endif
+
+#ifdef CONFIG_DEBUG_MSM8960_UART
+#define MSM_DEBUG_UART_BASE     0xF0040000
+#define MSM_DEBUG_UART_PHYS     0x16440000
+#endif
 
         .macro  addruart, rp, rv, tmp
 #ifdef MSM_DEBUG_UART_PHYS
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 92d10e503746..72024ea8a3a6 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -41,7 +41,6 @@
 #include <asm/sections.h>
 #include <asm/tlbflush.h>
 #include <asm/ptrace.h>
-#include <asm/localtimer.h>
 #include <asm/smp_plat.h>
 #include <asm/virt.h>
 #include <asm/mach/arch.h>
@@ -156,8 +155,6 @@ int platform_can_cpu_hotplug(void)
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
-static void percpu_timer_stop(void);
-
 static int platform_cpu_kill(unsigned int cpu)
 {
         if (smp_ops.cpu_kill)
@@ -201,11 +198,6 @@ int __cpu_disable(void)
         migrate_irqs();
 
         /*
-         * Stop the local timer for this CPU.
-         */
-        percpu_timer_stop();
-
-        /*
          * Flush user cache and TLB mappings, and then remove this CPU
          * from the vm mask set of all processes.
          *
@@ -326,8 +318,6 @@ static void smp_store_cpu_info(unsigned int cpuid)
         store_cpu_topology(cpuid);
 }
 
-static void percpu_timer_setup(void);
-
 /*
  * This is the secondary CPU boot entry.  We're using this CPUs
  * idle thread stack, but a set of temporary page tables.
@@ -382,11 +372,6 @@ asmlinkage void secondary_start_kernel(void)
         set_cpu_online(cpu, true);
         complete(&cpu_running);
 
-        /*
-         * Setup the percpu timer for this CPU.
-         */
-        percpu_timer_setup();
-
         local_irq_enable();
         local_fiq_enable();
 
@@ -424,12 +409,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
                 max_cpus = ncores;
         if (ncores > 1 && max_cpus) {
                 /*
-                 * Enable the local timer or broadcast device for the
-                 * boot CPU, but only if we have more than one CPU.
-                 */
-                percpu_timer_setup();
-
-                /*
                  * Initialise the present map, which describes the set of CPUs
                  * actually populated at the present time. A platform should
                  * re-initialize the map in the platforms smp_prepare_cpus()
@@ -505,11 +484,6 @@ u64 smp_irq_stat_cpu(unsigned int cpu)
         return sum;
 }
 
-/*
- * Timer (local or broadcast) support
- */
-static DEFINE_PER_CPU(struct clock_event_device, percpu_clockevent);
-
 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
 void tick_broadcast(const struct cpumask *mask)
 {
@@ -517,67 +491,6 @@ void tick_broadcast(const struct cpumask *mask)
 }
 #endif
 
-static void broadcast_timer_set_mode(enum clock_event_mode mode,
-        struct clock_event_device *evt)
-{
-}
-
-static void broadcast_timer_setup(struct clock_event_device *evt)
-{
-        evt->name       = "dummy_timer";
-        evt->features   = CLOCK_EVT_FEAT_ONESHOT |
-                          CLOCK_EVT_FEAT_PERIODIC |
-                          CLOCK_EVT_FEAT_DUMMY;
-        evt->rating     = 100;
-        evt->mult       = 1;
-        evt->set_mode   = broadcast_timer_set_mode;
-
-        clockevents_register_device(evt);
-}
-
-static struct local_timer_ops *lt_ops;
-
-#ifdef CONFIG_LOCAL_TIMERS
-int local_timer_register(struct local_timer_ops *ops)
-{
-        if (!is_smp() || !setup_max_cpus)
-                return -ENXIO;
-
-        if (lt_ops)
-                return -EBUSY;
-
-        lt_ops = ops;
-        return 0;
-}
-#endif
-
-static void percpu_timer_setup(void)
-{
-        unsigned int cpu = smp_processor_id();
-        struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
-
-        evt->cpumask = cpumask_of(cpu);
-
-        if (!lt_ops || lt_ops->setup(evt))
-                broadcast_timer_setup(evt);
-}
-
-#ifdef CONFIG_HOTPLUG_CPU
-/*
- * The generic clock events code purposely does not stop the local timer
- * on CPU_DEAD/CPU_DEAD_FROZEN hotplug events, so we have to do it
- * manually here.
- */
-static void percpu_timer_stop(void)
-{
-        unsigned int cpu = smp_processor_id();
-        struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
-
-        if (lt_ops)
-                lt_ops->stop(evt);
-}
-#endif
-
 static DEFINE_RAW_SPINLOCK(stop_lock);
 
 /*
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 25956204ef23..2985c9f0905d 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -11,6 +11,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/clk.h>
+#include <linux/cpu.h>
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/err.h>
@@ -24,7 +25,6 @@
 
 #include <asm/smp_plat.h>
 #include <asm/smp_twd.h>
-#include <asm/localtimer.h>
 
 /* set up by the platform code */
 static void __iomem *twd_base;
@@ -33,7 +33,7 @@ static struct clk *twd_clk;
 static unsigned long twd_timer_rate;
 static DEFINE_PER_CPU(bool, percpu_setup_called);
 
-static struct clock_event_device __percpu **twd_evt;
+static struct clock_event_device __percpu *twd_evt;
 static int twd_ppi;
 
 static void twd_set_mode(enum clock_event_mode mode,
@@ -90,8 +90,10 @@ static int twd_timer_ack(void)
         return 0;
 }
 
-static void twd_timer_stop(struct clock_event_device *clk)
+static void twd_timer_stop(void)
 {
+        struct clock_event_device *clk = __this_cpu_ptr(twd_evt);
+
         twd_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
         disable_percpu_irq(clk->irq);
 }
@@ -106,7 +108,7 @@ static void twd_update_frequency(void *new_rate)
 {
         twd_timer_rate = *((unsigned long *) new_rate);
 
-        clockevents_update_freq(*__this_cpu_ptr(twd_evt), twd_timer_rate);
+        clockevents_update_freq(__this_cpu_ptr(twd_evt), twd_timer_rate);
 }
 
 static int twd_rate_change(struct notifier_block *nb,
@@ -132,7 +134,7 @@ static struct notifier_block twd_clk_nb = {
 
 static int twd_clk_init(void)
 {
-        if (twd_evt && *__this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk))
+        if (twd_evt && __this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk))
                 return clk_notifier_register(twd_clk, &twd_clk_nb);
 
         return 0;
@@ -151,7 +153,7 @@ static void twd_update_frequency(void *data)
 {
         twd_timer_rate = clk_get_rate(twd_clk);
 
-        clockevents_update_freq(*__this_cpu_ptr(twd_evt), twd_timer_rate);
+        clockevents_update_freq(__this_cpu_ptr(twd_evt), twd_timer_rate);
 }
 
 static int twd_cpufreq_transition(struct notifier_block *nb,
@@ -177,7 +179,7 @@ static struct notifier_block twd_cpufreq_nb = {
 
 static int twd_cpufreq_init(void)
 {
-        if (twd_evt && *__this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk))
+        if (twd_evt && __this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk))
                 return cpufreq_register_notifier(&twd_cpufreq_nb,
                         CPUFREQ_TRANSITION_NOTIFIER);
 
@@ -228,7 +230,7 @@ static void twd_calibrate_rate(void)
 
 static irqreturn_t twd_handler(int irq, void *dev_id)
 {
-        struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
+        struct clock_event_device *evt = dev_id;
 
         if (twd_timer_ack()) {
                 evt->event_handler(evt);
@@ -265,9 +267,9 @@ static void twd_get_clock(struct device_node *np)
 /*
  * Setup the local clock events for a CPU.
  */
-static int twd_timer_setup(struct clock_event_device *clk)
+static void twd_timer_setup(void)
 {
-        struct clock_event_device **this_cpu_clk;
+        struct clock_event_device *clk = __this_cpu_ptr(twd_evt);
         int cpu = smp_processor_id();
 
         /*
@@ -276,9 +278,9 @@ static int twd_timer_setup(struct clock_event_device *clk)
          */
         if (per_cpu(percpu_setup_called, cpu)) {
                 __raw_writel(0, twd_base + TWD_TIMER_CONTROL);
-                clockevents_register_device(*__this_cpu_ptr(twd_evt));
+                clockevents_register_device(clk);
                 enable_percpu_irq(clk->irq, 0);
-                return 0;
+                return;
         }
         per_cpu(percpu_setup_called, cpu) = true;
 
@@ -297,27 +299,37 @@ static int twd_timer_setup(struct clock_event_device *clk)
         clk->set_mode = twd_set_mode;
         clk->set_next_event = twd_set_next_event;
         clk->irq = twd_ppi;
-
-        this_cpu_clk = __this_cpu_ptr(twd_evt);
-        *this_cpu_clk = clk;
+        clk->cpumask = cpumask_of(cpu);
 
         clockevents_config_and_register(clk, twd_timer_rate,
                                         0xf, 0xffffffff);
         enable_percpu_irq(clk->irq, 0);
+}
 
-        return 0;
+static int twd_timer_cpu_notify(struct notifier_block *self,
+                                unsigned long action, void *hcpu)
+{
+        switch (action & ~CPU_TASKS_FROZEN) {
+        case CPU_STARTING:
+                twd_timer_setup();
+                break;
+        case CPU_DYING:
+                twd_timer_stop();
+                break;
+        }
+
+        return NOTIFY_OK;
 }
 
-static struct local_timer_ops twd_lt_ops = {
-        .setup  = twd_timer_setup,
-        .stop   = twd_timer_stop,
+static struct notifier_block twd_timer_cpu_nb = {
+        .notifier_call = twd_timer_cpu_notify,
 };
 
 static int __init twd_local_timer_common_register(struct device_node *np)
 {
         int err;
 
-        twd_evt = alloc_percpu(struct clock_event_device *);
+        twd_evt = alloc_percpu(struct clock_event_device);
         if (!twd_evt) {
                 err = -ENOMEM;
                 goto out_free;
@@ -329,12 +341,22 @@ static int __init twd_local_timer_common_register(struct device_node *np)
                 goto out_free;
         }
 
-        err = local_timer_register(&twd_lt_ops);
+        err = register_cpu_notifier(&twd_timer_cpu_nb);
         if (err)
                 goto out_irq;
 
         twd_get_clock(np);
 
+        /*
+         * Immediately configure the timer on the boot CPU, unless we need
+         * jiffies to be incrementing to calibrate the rate in which case
+         * setup the timer in late_time_init.
+         */
+        if (twd_timer_rate)
+                twd_timer_setup();
+        else
+                late_time_init = twd_timer_setup;
+
         return 0;
 
 out_irq:
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index 3aaa9784cf0e..f1d49e929ccb 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -26,7 +26,7 @@
 #include <linux/gpio.h>
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
-#include <linux/i2c/pca953x.h>
+#include <linux/platform_data/pca953x.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 9f09f45835f8..f5c228190fdd 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -19,7 +19,7 @@
 #include <linux/kernel.h>
 #include <linux/i2c.h>
 #include <linux/i2c/at24.h>
-#include <linux/i2c/pca953x.h>
+#include <linux/platform_data/pca953x.h>
 #include <linux/input.h>
 #include <linux/input/tps6507x-ts.h>
 #include <linux/mfd/tps6507x.h>
diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c
index 605956fd07a2..64f2e50e19ca 100644
--- a/arch/arm/mach-ep93xx/vision_ep9307.c
+++ b/arch/arm/mach-ep93xx/vision_ep9307.c
@@ -23,7 +23,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
-#include <linux/i2c/pca953x.h>
+#include <linux/platform_data/pca953x.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #include <linux/spi/mmc_spi.h>
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 972490fc09d6..8646a141ae46 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -17,7 +17,6 @@
 
 void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
 void exynos_init_time(void);
-extern unsigned long xxti_f, xusbxti_f;
 
 struct map_desc;
 void exynos_init_io(void);
@@ -25,56 +24,14 @@ void exynos4_restart(enum reboot_mode mode, const char *cmd);
 void exynos5_restart(enum reboot_mode mode, const char *cmd);
 void exynos_init_late(void);
 
-/* ToDo: remove these after migrating legacy exynos4 platforms to dt */
-void exynos4_clk_init(struct device_node *np, int is_exynos4210, void __iomem *reg_base, unsigned long xom);
-void exynos4_clk_register_fixed_ext(unsigned long, unsigned long);
-
 void exynos_firmware_init(void);
 
-void exynos_set_timer_source(u8 channels);
-
 #ifdef CONFIG_PM_GENERIC_DOMAINS
 int exynos_pm_late_initcall(void);
 #else
 static inline int exynos_pm_late_initcall(void) { return 0; }
 #endif
 
-#ifdef CONFIG_ARCH_EXYNOS4
-void exynos4_register_clocks(void);
-void exynos4_setup_clocks(void);
-
-#else
-#define exynos4_register_clocks()
-#define exynos4_setup_clocks()
-#endif
-
-#ifdef CONFIG_ARCH_EXYNOS5
-void exynos5_register_clocks(void);
-void exynos5_setup_clocks(void);
-
-#else
-#define exynos5_register_clocks()
-#define exynos5_setup_clocks()
-#endif
-
-#ifdef CONFIG_CPU_EXYNOS4210
-void exynos4210_register_clocks(void);
-
-#else
-#define exynos4210_register_clocks()
-#endif
-
-#ifdef CONFIG_SOC_EXYNOS4212
-void exynos4212_register_clocks(void);
-
-#else
-#define exynos4212_register_clocks()
-#endif
-
-struct device_node;
-void combiner_init(void __iomem *combiner_base, struct device_node *np,
-                        unsigned int max_nr, int irq_base);
-
 extern struct smp_operations exynos_smp_ops;
 
 extern void exynos_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
index cd9fcb1cd7ab..6acbdabf6222 100644
--- a/arch/arm/mach-highbank/Kconfig
+++ b/arch/arm/mach-highbank/Kconfig
@@ -12,7 +12,7 @@ config ARCH_HIGHBANK
         select CPU_V7
         select GENERIC_CLOCKEVENTS
         select HAVE_ARM_SCU
-        select HAVE_ARM_TWD if LOCAL_TIMERS
+        select HAVE_ARM_TWD if SMP
         select HAVE_SMP
         select MAILBOX
         select PL320_MBOX
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index f54656091a9d..1303e334c343 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -793,7 +793,7 @@ config SOC_IMX6Q
         select COMMON_CLK
         select CPU_V7
         select HAVE_ARM_SCU if SMP
-        select HAVE_ARM_TWD if LOCAL_TIMERS
+        select HAVE_ARM_TWD if SMP
         select HAVE_IMX_ANATOP
         select HAVE_IMX_GPC
         select HAVE_IMX_MMDC
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 29ac8ee651d2..97f9c6297fcf 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -26,7 +26,7 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
 #include <linux/i2c.h>
-#include <linux/i2c/pca953x.h>
+#include <linux/platform_data/pca953x.h>
 #include <linux/input.h>
 #include <linux/gpio.h>
 #include <linux/delay.h>
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index a27faaba98ec..c91894003da9 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -26,7 +26,7 @@
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 #include <linux/gpio.h>
-#include <linux/i2c/pca953x.h>
+#include <linux/platform_data/pca953x.h>
 
 #include "common.h"
 #include "devices-imx27.h"
diff --git a/arch/arm/mach-ks8695/board-acs5k.c b/arch/arm/mach-ks8695/board-acs5k.c
index 456d6386edf8..9f9c0441a917 100644
--- a/arch/arm/mach-ks8695/board-acs5k.c
+++ b/arch/arm/mach-ks8695/board-acs5k.c
@@ -20,7 +20,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c-algo-bit.h>
 #include <linux/i2c-gpio.h>
-#include <linux/i2c/pca953x.h>
+#include <linux/platform_data/pca953x.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/map.h>
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index 8483906d4308..702232996c8c 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -15,7 +15,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/onenand.h>
 #include <linux/interrupt.h>
-#include <linux/i2c/pca953x.h>
+#include <linux/platform_data/pca953x.h>
 #include <linux/gpio.h>
 #include <linux/gpio-pxa.h>
 #include <linux/mfd/88pm860x.h>
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index d257ff40e16b..d872634c2f85 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,17 +1,16 @@
-obj-y += io.o timer.o
+obj-y += timer.o
 obj-y += clock.o
 
 obj-$(CONFIG_MSM_VIC) += irq-vic.o
-obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o
 
 obj-$(CONFIG_ARCH_MSM7X00A) += irq.o
 obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
 
 obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
 
-obj-$(CONFIG_ARCH_MSM7X00A) += dma.o
-obj-$(CONFIG_ARCH_MSM7X30) += dma.o
-obj-$(CONFIG_ARCH_QSD8X50) += dma.o
+obj-$(CONFIG_ARCH_MSM7X00A) += dma.o io.o
+obj-$(CONFIG_ARCH_MSM7X30) += dma.o io.o
+obj-$(CONFIG_ARCH_QSD8X50) += dma.o io.o
 
 obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
 obj-$(CONFIG_MSM_SMD) += last_radio_log.o
diff --git a/arch/arm/mach-msm/board-dt-8660.c b/arch/arm/mach-msm/board-dt-8660.c
index 492f5cd87b0a..c2946892f5e3 100644
--- a/arch/arm/mach-msm/board-dt-8660.c
+++ b/arch/arm/mach-msm/board-dt-8660.c
@@ -15,8 +15,8 @@
 #include <linux/of_platform.h>
 
 #include <asm/mach/arch.h>
+#include <asm/mach/map.h>
 
-#include <mach/board.h>
 #include "common.h"
 
 static void __init msm8x60_init_late(void)
@@ -42,9 +42,7 @@ static const char *msm8x60_fluid_match[] __initdata = {
 
 DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
         .smp = smp_ops(msm_smp_ops),
-        .map_io = msm_map_msm8x60_io,
         .init_machine = msm8x60_dt_init,
         .init_late = msm8x60_init_late,
-        .init_time      = msm_dt_timer_init,
         .dt_compat = msm8x60_fluid_match,
 MACHINE_END
diff --git a/arch/arm/mach-msm/board-dt-8960.c b/arch/arm/mach-msm/board-dt-8960.c
index bb5530957c4f..d4ca52c45111 100644
--- a/arch/arm/mach-msm/board-dt-8960.c
+++ b/arch/arm/mach-msm/board-dt-8960.c
@@ -14,6 +14,7 @@
 #include <linux/of_platform.h>
 
 #include <asm/mach/arch.h>
+#include <asm/mach/map.h>
 
 #include "common.h"
 
@@ -29,8 +30,6 @@ static const char * const msm8960_dt_match[] __initconst = {
 
 DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)")
         .smp = smp_ops(msm_smp_ops),
-        .map_io = msm_map_msm8960_io,
-        .init_time      = msm_dt_timer_init,
         .init_machine = msm_dt_init,
         .dt_compat = msm8960_dt_match,
 MACHINE_END
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index 803651ad4f62..a77529887cbc 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -29,7 +29,6 @@
 #include <asm/setup.h>
 
 #include <mach/irqs.h>
-#include <mach/board.h>
 #include <mach/msm_iomap.h>
 
 #include <linux/mtd/nand.h>
diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c
index 30c3496db593..7d9981cb400e 100644
--- a/arch/arm/mach-msm/board-mahimahi.c
+++ b/arch/arm/mach-msm/board-mahimahi.c
@@ -28,12 +28,12 @@
 #include <asm/mach/map.h>
 #include <asm/setup.h>
 
-#include <mach/board.h>
 #include <mach/hardware.h>
 
 #include "board-mahimahi.h"
 #include "devices.h"
 #include "proc_comm.h"
+#include "common.h"
 
 static uint debug_uart;
 
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index db3d8c0bc8a4..f9af5a46e8b6 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -30,7 +30,6 @@
 #include <asm/memory.h>
 #include <asm/setup.h>
 
-#include <mach/board.h>
 #include <mach/msm_iomap.h>
 #include <mach/dma.h>
 
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index f14a73d86bc0..5f933bc50783 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -28,7 +28,6 @@
 #include <asm/io.h>
 #include <asm/setup.h>
 
-#include <mach/board.h>
 #include <mach/irqs.h>
 #include <mach/sirc.h>
 #include <mach/vreg.h>
diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c
index 70730111b37c..327605174d63 100644
--- a/arch/arm/mach-msm/board-sapphire.c
+++ b/arch/arm/mach-msm/board-sapphire.c
@@ -28,7 +28,6 @@
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 #include <mach/vreg.h>
-#include <mach/board.h>
 
 #include <asm/io.h>
 #include <asm/delay.h>
@@ -41,6 +40,7 @@
 #include "board-sapphire.h"
 #include "proc_comm.h"
 #include "devices.h"
+#include "common.h"
 
 void msm_init_irq(void);
 void msm_init_gpio(void);
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index 64a46eb4fc49..ccf6621bc664 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -25,7 +25,6 @@
 #include <asm/mach/map.h>
 #include <asm/setup.h>
 
-#include <mach/board.h>
 #include <mach/hardware.h>
 #include <mach/msm_iomap.h>
 
diff --git a/arch/arm/mach-msm/board-trout.h b/arch/arm/mach-msm/board-trout.h
index 651851c3e1dd..b2379ede43bc 100644
--- a/arch/arm/mach-msm/board-trout.h
+++ b/arch/arm/mach-msm/board-trout.h
@@ -4,7 +4,7 @@
 #ifndef __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
 #define __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
 
-#include <mach/board.h>
+#include "common.h"
 
 #define MSM_SMI_BASE            0x00000000
 #define MSM_SMI_SIZE            0x00800000
diff --git a/arch/arm/mach-msm/common.h b/arch/arm/mach-msm/common.h
index 421cf7751a80..33c7725adae2 100644
--- a/arch/arm/mach-msm/common.h
+++ b/arch/arm/mach-msm/common.h
@@ -14,13 +14,10 @@
 
 extern void msm7x01_timer_init(void);
 extern void msm7x30_timer_init(void);
-extern void msm_dt_timer_init(void);
 extern void qsd8x50_timer_init(void);
 
 extern void msm_map_common_io(void);
 extern void msm_map_msm7x30_io(void);
-extern void msm_map_msm8x60_io(void);
-extern void msm_map_msm8960_io(void);
 extern void msm_map_qsd8x50_io(void);
 
 extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
@@ -29,4 +26,19 @@ extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
 extern struct smp_operations msm_smp_ops;
 extern void msm_cpu_die(unsigned int cpu);
 
+struct msm_mmc_platform_data;
+
+extern void msm_add_devices(void);
+extern void msm_init_irq(void);
+extern void msm_init_gpio(void);
+extern int msm_add_sdcc(unsigned int controller,
+                        struct msm_mmc_platform_data *plat,
+                        unsigned int stat_irq, unsigned long stat_irq_flags);
+
+#if defined(CONFIG_MSM_SMD) && defined(CONFIG_DEBUG_FS)
+extern int smd_debugfs_init(void);
+#else
+static inline int smd_debugfs_init(void) { return 0; }
+#endif
+
 #endif
diff --git a/arch/arm/mach-msm/devices-iommu.c b/arch/arm/mach-msm/devices-iommu.c
deleted file mode 100644
index 0fb7a17df398..000000000000
--- a/arch/arm/mach-msm/devices-iommu.c
+++ /dev/null
@@ -1,912 +0,0 @@
-/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/bootmem.h>
-#include <linux/module.h>
-#include <mach/irqs.h>
-#include <mach/iommu.h>
-
-static struct resource msm_iommu_jpegd_resources[] = {
-        {
-                .start = 0x07300000,
-                .end   = 0x07300000 + SZ_1M - 1,
-                .name  = "physbase",
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name = "nonsecure_irq",
-                .start = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
-                .end   = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name = "secure_irq",
-                .start = SMMU_JPEGD_CB_SC_SECURE_IRQ,
-                .end   = SMMU_JPEGD_CB_SC_SECURE_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource msm_iommu_vpe_resources[] = {
-        {
-                .start = 0x07400000,
-                .end   = 0x07400000 + SZ_1M - 1,
-                .name  = "physbase",
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name = "nonsecure_irq",
-                .start = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
-                .end   = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name = "secure_irq",
-                .start = SMMU_VPE_CB_SC_SECURE_IRQ,
-                .end   = SMMU_VPE_CB_SC_SECURE_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource msm_iommu_mdp0_resources[] = {
-        {
-                .start = 0x07500000,
-                .end   = 0x07500000 + SZ_1M - 1,
-                .name  = "physbase",
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name = "nonsecure_irq",
-                .start = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
-                .end   = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name = "secure_irq",
-                .start = SMMU_MDP0_CB_SC_SECURE_IRQ,
-                .end   = SMMU_MDP0_CB_SC_SECURE_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource msm_iommu_mdp1_resources[] = {
-        {
-                .start = 0x07600000,
-                .end   = 0x07600000 + SZ_1M - 1,
-                .name  = "physbase",
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name = "nonsecure_irq",
-                .start = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
-                .end   = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name = "secure_irq",
-                .start = SMMU_MDP1_CB_SC_SECURE_IRQ,
-                .end   = SMMU_MDP1_CB_SC_SECURE_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource msm_iommu_rot_resources[] = {
-        {
-                .start = 0x07700000,
-                .end   = 0x07700000 + SZ_1M - 1,
-                .name  = "physbase",
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name = "nonsecure_irq",
-                .start = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
-                .end   = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name = "secure_irq",
-                .start = SMMU_ROT_CB_SC_SECURE_IRQ,
-                .end   = SMMU_ROT_CB_SC_SECURE_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource msm_iommu_ijpeg_resources[] = {
-        {
-                .start = 0x07800000,
-                .end   = 0x07800000 + SZ_1M - 1,
-                .name  = "physbase",
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name = "nonsecure_irq",
-                .start = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
-                .end   = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name = "secure_irq",
-                .start = SMMU_IJPEG_CB_SC_SECURE_IRQ,
-                .end   = SMMU_IJPEG_CB_SC_SECURE_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource msm_iommu_vfe_resources[] = {
-        {
-                .start = 0x07900000,
-                .end   = 0x07900000 + SZ_1M - 1,
-                .name  = "physbase",
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name = "nonsecure_irq",
-                .start = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
-                .end   = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name = "secure_irq",
-                .start = SMMU_VFE_CB_SC_SECURE_IRQ,
-                .end   = SMMU_VFE_CB_SC_SECURE_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource msm_iommu_vcodec_a_resources[] = {
-        {
-                .start = 0x07A00000,
-                .end   = 0x07A00000 + SZ_1M - 1,
-                .name  = "physbase",
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name = "nonsecure_irq",
-                .start = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
-                .end   = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name = "secure_irq",
-                .start = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
-                .end   = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource msm_iommu_vcodec_b_resources[] = {
-        {
-                .start = 0x07B00000,
-                .end   = 0x07B00000 + SZ_1M - 1,
-                .name  = "physbase",
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name = "nonsecure_irq",
-                .start = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
-                .end   = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name = "secure_irq",
-                .start = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
-                .end   = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource msm_iommu_gfx3d_resources[] = {
-        {
-                .start = 0x07C00000,
-                .end   = 0x07C00000 + SZ_1M - 1,
-                .name  = "physbase",
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name = "nonsecure_irq",
-                .start = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
-                .end   = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name = "secure_irq",
-                .start = SMMU_GFX3D_CB_SC_SECURE_IRQ,
-                .end   = SMMU_GFX3D_CB_SC_SECURE_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource msm_iommu_gfx2d0_resources[] = {
-        {
-                .start = 0x07D00000,
-                .end   = 0x07D00000 + SZ_1M - 1,
-                .name  = "physbase",
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name = "nonsecure_irq",
-                .start = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
-                .end   = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name = "secure_irq",
-                .start = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
-                .end   = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource msm_iommu_gfx2d1_resources[] = {
-        {
-                .start = 0x07E00000,
-                .end   = 0x07E00000 + SZ_1M - 1,
-                .name  = "physbase",
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name = "nonsecure_irq",
-                .start = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ,
-                .end   = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name = "secure_irq",
-                .start = SMMU_GFX2D1_CB_SC_SECURE_IRQ,
-                .end   = SMMU_GFX2D1_CB_SC_SECURE_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device msm_root_iommu_dev = {
-        .name = "msm_iommu",
-        .id = -1,
-};
-
-static struct msm_iommu_dev jpegd_iommu = {
-        .name = "jpegd",
-        .ncb = 2,
-};
-
-static struct msm_iommu_dev vpe_iommu = {
-        .name = "vpe",
-        .ncb = 2,
-};
-
-static struct msm_iommu_dev mdp0_iommu = {
-        .name = "mdp0",
-        .ncb = 2,
-};
-
-static struct msm_iommu_dev mdp1_iommu = {
-        .name = "mdp1",
-        .ncb = 2,
-};
-
-static struct msm_iommu_dev rot_iommu = {
-        .name = "rot",
-        .ncb = 2,
-};
-
-static struct msm_iommu_dev ijpeg_iommu = {
-        .name = "ijpeg",
-        .ncb = 2,
-};
-
-static struct msm_iommu_dev vfe_iommu = {
-        .name = "vfe",
-        .ncb = 2,
-};
-
-static struct msm_iommu_dev vcodec_a_iommu = {
-        .name = "vcodec_a",
-        .ncb = 2,
-};
-
-static struct msm_iommu_dev vcodec_b_iommu = {
-        .name = "vcodec_b",
-        .ncb = 2,
-};
-
-static struct msm_iommu_dev gfx3d_iommu = {
-        .name = "gfx3d",
-        .ncb = 3,
-};
-
-static struct msm_iommu_dev gfx2d0_iommu = {
-        .name = "gfx2d0",
-        .ncb = 2,
-};
-
-static struct msm_iommu_dev gfx2d1_iommu = {
-        .name = "gfx2d1",
-        .ncb = 2,
-};
-
-static struct platform_device msm_device_iommu_jpegd = {
-        .name = "msm_iommu",
-        .id = 0,
-        .dev = {
-                .parent = &msm_root_iommu_dev.dev,
-        },
-        .num_resources = ARRAY_SIZE(msm_iommu_jpegd_resources),
-        .resource = msm_iommu_jpegd_resources,
-};
-
-static struct platform_device msm_device_iommu_vpe = {
-        .name = "msm_iommu",
-        .id = 1,
-        .dev = {
-                .parent = &msm_root_iommu_dev.dev,
-        },
-        .num_resources = ARRAY_SIZE(msm_iommu_vpe_resources),
-        .resource = msm_iommu_vpe_resources,
-};
-
-static struct platform_device msm_device_iommu_mdp0 = {
-        .name = "msm_iommu",
-        .id = 2,
-        .dev = {
-                .parent = &msm_root_iommu_dev.dev,
-        },
-        .num_resources = ARRAY_SIZE(msm_iommu_mdp0_resources),
-        .resource = msm_iommu_mdp0_resources,
-};
-
-static struct platform_device msm_device_iommu_mdp1 = {
-        .name = "msm_iommu",
-        .id = 3,
-        .dev = {
-                .parent = &msm_root_iommu_dev.dev,
-        },
-        .num_resources = ARRAY_SIZE(msm_iommu_mdp1_resources),
-        .resource = msm_iommu_mdp1_resources,
-};
-
-static struct platform_device msm_device_iommu_rot = {
-        .name = "msm_iommu",
-        .id = 4,
-        .dev = {
-                .parent = &msm_root_iommu_dev.dev,
-        },
-        .num_resources = ARRAY_SIZE(msm_iommu_rot_resources),
-        .resource = msm_iommu_rot_resources,
-};
-
-static struct platform_device msm_device_iommu_ijpeg = {
-        .name = "msm_iommu",
-        .id = 5,
-        .dev = {
-                .parent = &msm_root_iommu_dev.dev,
-        },
-        .num_resources = ARRAY_SIZE(msm_iommu_ijpeg_resources),
-        .resource = msm_iommu_ijpeg_resources,
-};
-
-static struct platform_device msm_device_iommu_vfe = {
-        .name = "msm_iommu",
-        .id = 6,
-        .dev = {
-                .parent = &msm_root_iommu_dev.dev,
-        },
-        .num_resources = ARRAY_SIZE(msm_iommu_vfe_resources),
-        .resource = msm_iommu_vfe_resources,
-};
-
-static struct platform_device msm_device_iommu_vcodec_a = {
-        .name = "msm_iommu",
-        .id = 7,
-        .dev = {
-                .parent = &msm_root_iommu_dev.dev,
-        },
-        .num_resources = ARRAY_SIZE(msm_iommu_vcodec_a_resources),
-        .resource = msm_iommu_vcodec_a_resources,
-};
-
-static struct platform_device msm_device_iommu_vcodec_b = {
-        .name = "msm_iommu",
-        .id = 8,
-        .dev = {
-                .parent = &msm_root_iommu_dev.dev,
-        },
-        .num_resources = ARRAY_SIZE(msm_iommu_vcodec_b_resources),
-        .resource = msm_iommu_vcodec_b_resources,
-};
-
-static struct platform_device msm_device_iommu_gfx3d = {
-        .name = "msm_iommu",
-        .id = 9,
-        .dev = {
-                .parent = &msm_root_iommu_dev.dev,
-        },
-        .num_resources = ARRAY_SIZE(msm_iommu_gfx3d_resources),
-        .resource = msm_iommu_gfx3d_resources,
-};
-
-static struct platform_device msm_device_iommu_gfx2d0 = {
-        .name = "msm_iommu",
-        .id = 10,
-        .dev = {
-                .parent = &msm_root_iommu_dev.dev,
-        },
-        .num_resources = ARRAY_SIZE(msm_iommu_gfx2d0_resources),
-        .resource = msm_iommu_gfx2d0_resources,
-};
-
-struct platform_device msm_device_iommu_gfx2d1 = {
-        .name = "msm_iommu",
-        .id = 11,
-        .dev = {
-                .parent = &msm_root_iommu_dev.dev,
-        },
-        .num_resources = ARRAY_SIZE(msm_iommu_gfx2d1_resources),
-        .resource = msm_iommu_gfx2d1_resources,
-};
-
-static struct msm_iommu_ctx_dev jpegd_src_ctx = {
-        .name = "jpegd_src",
-        .num = 0,
-        .mids = {0, -1}
-};
-
-static struct msm_iommu_ctx_dev jpegd_dst_ctx = {
-        .name = "jpegd_dst",
-        .num = 1,
-        .mids = {1, -1}
-};
-
-static struct msm_iommu_ctx_dev vpe_src_ctx = {
-        .name = "vpe_src",
-        .num = 0,
-        .mids = {0, -1}
-};
-
-static struct msm_iommu_ctx_dev vpe_dst_ctx = {
-        .name = "vpe_dst",
-        .num = 1,
-        .mids = {1, -1}
-};
-
-static struct msm_iommu_ctx_dev mdp_vg1_ctx = {
-        .name = "mdp_vg1",
-        .num = 0,
-        .mids = {0, 2, -1}
-};
-
-static struct msm_iommu_ctx_dev mdp_rgb1_ctx = {
-        .name = "mdp_rgb1",
-        .num = 1,
-        .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1}
-};
-
-static struct msm_iommu_ctx_dev mdp_vg2_ctx = {
-        .name = "mdp_vg2",
-        .num = 0,
-        .mids = {0, 2, -1}
-};
-
-static struct msm_iommu_ctx_dev mdp_rgb2_ctx = {
-        .name = "mdp_rgb2",
-        .num = 1,
-        .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1}
-};
-
-static struct msm_iommu_ctx_dev rot_src_ctx = {
-        .name = "rot_src",
-        .num = 0,
-        .mids = {0, -1}
-};
-
-static struct msm_iommu_ctx_dev rot_dst_ctx = {
-        .name = "rot_dst",
-        .num = 1,
-        .mids = {1, -1}
-};
-
-static struct msm_iommu_ctx_dev ijpeg_src_ctx = {
-        .name = "ijpeg_src",
-        .num = 0,
-        .mids = {0, -1}
-};
-
-static struct msm_iommu_ctx_dev ijpeg_dst_ctx = {
-        .name = "ijpeg_dst",
-        .num = 1,
-        .mids = {1, -1}
-};
-
-static struct msm_iommu_ctx_dev vfe_imgwr_ctx = {
-        .name = "vfe_imgwr",
-        .num = 0,
-        .mids = {2, 3, 4, 5, 6, 7, 8, -1}
-};
-
-static struct msm_iommu_ctx_dev vfe_misc_ctx = {
-        .name = "vfe_misc",
-        .num = 1,
-        .mids = {0, 1, 9, -1}
-};
-
-static struct msm_iommu_ctx_dev vcodec_a_stream_ctx = {
-        .name = "vcodec_a_stream",
-        .num = 0,
-        .mids = {2, 5, -1}
-};
-
-static struct msm_iommu_ctx_dev vcodec_a_mm1_ctx = {
-        .name = "vcodec_a_mm1",
-        .num = 1,
-        .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
-};
-
-static struct msm_iommu_ctx_dev vcodec_b_mm2_ctx = {
-        .name = "vcodec_b_mm2",
-        .num = 0,
-        .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
-};
-
-static struct msm_iommu_ctx_dev gfx3d_user_ctx = {
-        .name = "gfx3d_user",
-        .num = 0,
-        .mids = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
-};
-
-static struct msm_iommu_ctx_dev gfx3d_priv_ctx = {
-        .name = "gfx3d_priv",
-        .num = 1,
-        .mids = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
-                 31, -1}
-};
-
-static struct msm_iommu_ctx_dev gfx2d0_2d0_ctx = {
-        .name = "gfx2d0_2d0",
-        .num = 0,
-        .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
-};
-
-static struct msm_iommu_ctx_dev gfx2d1_2d1_ctx = {
-        .name = "gfx2d1_2d1",
-        .num = 0,
-        .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
-};
-
-static struct platform_device msm_device_jpegd_src_ctx = {
-        .name = "msm_iommu_ctx",
-        .id = 0,
-        .dev = {
-                .parent = &msm_device_iommu_jpegd.dev,
-        },
-};
-
-static struct platform_device msm_device_jpegd_dst_ctx = {
-        .name = "msm_iommu_ctx",
-        .id = 1,
-        .dev = {
-                .parent = &msm_device_iommu_jpegd.dev,
-        },
-};
-
-static struct platform_device msm_device_vpe_src_ctx = {
-        .name = "msm_iommu_ctx",
-        .id = 2,
-        .dev = {
-                .parent = &msm_device_iommu_vpe.dev,
-        },
-};
-
-static struct platform_device msm_device_vpe_dst_ctx = {
-        .name = "msm_iommu_ctx",
-        .id = 3,
-        .dev = {
-                .parent = &msm_device_iommu_vpe.dev,
-        },
-};
-
-static struct platform_device msm_device_mdp_vg1_ctx = {
-        .name = "msm_iommu_ctx",
-        .id = 4,
-        .dev = {
-                .parent = &msm_device_iommu_mdp0.dev,
-        },
-};
-
-static struct platform_device msm_device_mdp_rgb1_ctx = {
-        .name = "msm_iommu_ctx",
-        .id = 5,
-        .dev = {
-                .parent = &msm_device_iommu_mdp0.dev,
-        },
-};
-
-static struct platform_device msm_device_mdp_vg2_ctx = {
-        .name = "msm_iommu_ctx",
-        .id = 6,
-        .dev = {
-                .parent = &msm_device_iommu_mdp1.dev,
-        },
-};
-
-static struct platform_device msm_device_mdp_rgb2_ctx = {
-        .name = "msm_iommu_ctx",
-        .id = 7,
-        .dev = {
-                .parent = &msm_device_iommu_mdp1.dev,
-        },
-};
-
-static struct platform_device msm_device_rot_src_ctx = {
-        .name = "msm_iommu_ctx",
-        .id = 8,
-        .dev = {
-                .parent = &msm_device_iommu_rot.dev,
-        },
-};
-
-static struct platform_device msm_device_rot_dst_ctx = {
-        .name = "msm_iommu_ctx",
-        .id = 9,
-        .dev = {
-                .parent = &msm_device_iommu_rot.dev,
-        },
-};
-
-static struct platform_device msm_device_ijpeg_src_ctx = {
-        .name = "msm_iommu_ctx",
-        .id = 10,
-        .dev = {
-                .parent = &msm_device_iommu_ijpeg.dev,
-        },
-};
-
-static struct platform_device msm_device_ijpeg_dst_ctx = {
-        .name = "msm_iommu_ctx",
-        .id = 11,
-        .dev = {
-                .parent = &msm_device_iommu_ijpeg.dev,
-        },
-};
-
-static struct platform_device msm_device_vfe_imgwr_ctx = {
-        .name = "msm_iommu_ctx",
-        .id = 12,
-        .dev = {
-                .parent = &msm_device_iommu_vfe.dev,
-        },
-};
-
-static struct platform_device msm_device_vfe_misc_ctx = {
-        .name = "msm_iommu_ctx",
-        .id = 13,
-        .dev = {
-                .parent = &msm_device_iommu_vfe.dev,
-        },
-};
-
-static struct platform_device msm_device_vcodec_a_stream_ctx = {
-        .name = "msm_iommu_ctx",
-        .id = 14,
-        .dev = {
-                .parent = &msm_device_iommu_vcodec_a.dev,
-        },
-};
-
-static struct platform_device msm_device_vcodec_a_mm1_ctx = {
-        .name = "msm_iommu_ctx",
-        .id = 15,
-        .dev = {
-                .parent = &msm_device_iommu_vcodec_a.dev,
-        },
-};
-
-static struct platform_device msm_device_vcodec_b_mm2_ctx = {
-        .name = "msm_iommu_ctx",
-        .id = 16,
-        .dev = {
-                .parent = &msm_device_iommu_vcodec_b.dev,
-        },
-};
-
-static struct platform_device msm_device_gfx3d_user_ctx = {
-        .name = "msm_iommu_ctx",
-        .id = 17,
-        .dev = {
-                .parent = &msm_device_iommu_gfx3d.dev,
-        },
-};
-
-static struct platform_device msm_device_gfx3d_priv_ctx = {
-        .name = "msm_iommu_ctx",
-        .id = 18,
-        .dev = {
-                .parent = &msm_device_iommu_gfx3d.dev,
-        },
-};
-
-static struct platform_device msm_device_gfx2d0_2d0_ctx = {
-        .name = "msm_iommu_ctx",
-        .id = 19,
-        .dev = {
-                .parent = &msm_device_iommu_gfx2d0.dev,
-        },
-};
-
-static struct platform_device msm_device_gfx2d1_2d1_ctx = {
-        .name = "msm_iommu_ctx",
-        .id = 20,
-        .dev = {
-                .parent = &msm_device_iommu_gfx2d1.dev,
-        },
-};
-
-static struct platform_device *msm_iommu_devs[] = {
-        &msm_device_iommu_jpegd,
-        &msm_device_iommu_vpe,
-        &msm_device_iommu_mdp0,
-        &msm_device_iommu_mdp1,
-        &msm_device_iommu_rot,
-        &msm_device_iommu_ijpeg,
-        &msm_device_iommu_vfe,
-        &msm_device_iommu_vcodec_a,
-        &msm_device_iommu_vcodec_b,
-        &msm_device_iommu_gfx3d,
-        &msm_device_iommu_gfx2d0,
-        &msm_device_iommu_gfx2d1,
-};
-
-static struct msm_iommu_dev *msm_iommu_data[] = {
-        &jpegd_iommu,
-        &vpe_iommu,
-        &mdp0_iommu,
-        &mdp1_iommu,
-        &rot_iommu,
-        &ijpeg_iommu,
-        &vfe_iommu,
-        &vcodec_a_iommu,
-        &vcodec_b_iommu,
-        &gfx3d_iommu,
-        &gfx2d0_iommu,
-        &gfx2d1_iommu,
-};
-
-static struct platform_device *msm_iommu_ctx_devs[] = {
-        &msm_device_jpegd_src_ctx,
-        &msm_device_jpegd_dst_ctx,
-        &msm_device_vpe_src_ctx,
-        &msm_device_vpe_dst_ctx,
-        &msm_device_mdp_vg1_ctx,
-        &msm_device_mdp_rgb1_ctx,
-        &msm_device_mdp_vg2_ctx,
-        &msm_device_mdp_rgb2_ctx,
-        &msm_device_rot_src_ctx,
-        &msm_device_rot_dst_ctx,
-        &msm_device_ijpeg_src_ctx,
-        &msm_device_ijpeg_dst_ctx,
-        &msm_device_vfe_imgwr_ctx,
-        &msm_device_vfe_misc_ctx,
-        &msm_device_vcodec_a_stream_ctx,
-        &msm_device_vcodec_a_mm1_ctx,
-        &msm_device_vcodec_b_mm2_ctx,
-        &msm_device_gfx3d_user_ctx,
-        &msm_device_gfx3d_priv_ctx,
-        &msm_device_gfx2d0_2d0_ctx,
-        &msm_device_gfx2d1_2d1_ctx,
-};
-
-static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = {
-        &jpegd_src_ctx,
-        &jpegd_dst_ctx,
-        &vpe_src_ctx,
-        &vpe_dst_ctx,
-        &mdp_vg1_ctx,
-        &mdp_rgb1_ctx,
-        &mdp_vg2_ctx,
-        &mdp_rgb2_ctx,
-        &rot_src_ctx,
-        &rot_dst_ctx,
-        &ijpeg_src_ctx,
-        &ijpeg_dst_ctx,
-        &vfe_imgwr_ctx,
-        &vfe_misc_ctx,
-        &vcodec_a_stream_ctx,
-        &vcodec_a_mm1_ctx,
-        &vcodec_b_mm2_ctx,
-        &gfx3d_user_ctx,
-        &gfx3d_priv_ctx,
-        &gfx2d0_2d0_ctx,
-        &gfx2d1_2d1_ctx,
-};
-
-static int __init msm8x60_iommu_init(void)
-{
-        int ret, i;
-
-        ret = platform_device_register(&msm_root_iommu_dev);
-        if (ret != 0) {
-                pr_err("Failed to register root IOMMU device!\n");
-                goto failure;
-        }
-
-        for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); i++) {
-                ret = platform_device_add_data(msm_iommu_devs[i],
-                                               msm_iommu_data[i],
-                                               sizeof(struct msm_iommu_dev));
-                if (ret != 0) {
-                        pr_err("platform_device_add_data failed, "
-                               "i = %d\n", i);
-                        goto failure_unwind;
-                }
-
-                ret = platform_device_register(msm_iommu_devs[i]);
-
-                if (ret != 0) {
-                        pr_err("platform_device_register iommu failed, "
-                               "i = %d\n", i);
-                        goto failure_unwind;
-                }
-        }
-
-        for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++) {
-                ret = platform_device_add_data(msm_iommu_ctx_devs[i],
-                                               msm_iommu_ctx_data[i],
-                                               sizeof(*msm_iommu_ctx_devs[i]));
-                if (ret != 0) {
-                        pr_err("platform_device_add_data iommu failed, "
-                               "i = %d\n", i);
-                        goto failure_unwind2;
-                }
-
-                ret = platform_device_register(msm_iommu_ctx_devs[i]);
-                if (ret != 0) {
-                        pr_err("platform_device_register ctx failed, "
-                               "i = %d\n", i);
-                        goto failure_unwind2;
-                }
-        }
-        return 0;
-
-failure_unwind2:
-        while (--i >= 0)
-                platform_device_unregister(msm_iommu_ctx_devs[i]);
-failure_unwind:
-        while (--i >= 0)
-                platform_device_unregister(msm_iommu_devs[i]);
-
-        platform_device_unregister(&msm_root_iommu_dev);
-failure:
-        return ret;
-}
-
-static void __exit msm8x60_iommu_exit(void)
-{
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++)
-                platform_device_unregister(msm_iommu_ctx_devs[i]);
-
-        for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); ++i)
-                platform_device_unregister(msm_iommu_devs[i]);
-
-        platform_device_unregister(&msm_root_iommu_dev);
-}
-
-subsys_initcall(msm8x60_iommu_init);
-module_exit(msm8x60_iommu_exit);
-
-MODULE_LICENSE("GPL v2");
-MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index 14e286948f69..c15ea8ab20a7 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -21,10 +21,10 @@
 #include <mach/irqs.h>
 #include <mach/msm_iomap.h>
 #include <mach/dma.h>
-#include <mach/board.h>
 
 #include "devices.h"
 #include "smd_private.h"
+#include "common.h"
 
 #include <asm/mach/flash.h>
 
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index 2ed89b25d304..9e1e9ce07b1a 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -21,9 +21,9 @@
 #include <mach/irqs.h>
 #include <mach/msm_iomap.h>
 #include <mach/dma.h>
-#include <mach/board.h>
 
 #include "devices.h"
+#include "common.h"
 
 #include <asm/mach/flash.h>
 
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
deleted file mode 100644
index c34e246a3e07..000000000000
--- a/arch/arm/mach-msm/include/mach/board.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* arch/arm/mach-msm/include/mach/board.h
- *
- * Copyright (C) 2007 Google, Inc.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARCH_MSM_BOARD_H
-#define __ASM_ARCH_MSM_BOARD_H
-
-#include <linux/types.h>
-#include <linux/platform_data/mmc-msm_sdcc.h>
-
-/* common init routines for use by arch/arm/mach-msm/board-*.c */
-
-void __init msm_add_devices(void);
-void __init msm_init_irq(void);
-void __init msm_init_gpio(void);
-int __init msm_add_sdcc(unsigned int controller,
-                        struct msm_mmc_platform_data *plat,
-                        unsigned int stat_irq, unsigned long stat_irq_flags);
-
-#if defined(CONFIG_MSM_SMD) && defined(CONFIG_DEBUG_FS)
-int smd_debugfs_init(void);
-#else
-static inline int smd_debugfs_init(void) { return 0; }
-#endif
-
-#endif
diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h
deleted file mode 100644
index 5c7c955e6d25..000000000000
--- a/arch/arm/mach-msm/include/mach/iommu.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-
-#ifndef MSM_IOMMU_H
-#define MSM_IOMMU_H
-
-#include <linux/interrupt.h>
-#include <linux/clk.h>
-
-/* Sharability attributes of MSM IOMMU mappings */
-#define MSM_IOMMU_ATTR_NON_SH           0x0
-#define MSM_IOMMU_ATTR_SH               0x4
-
-/* Cacheability attributes of MSM IOMMU mappings */
-#define MSM_IOMMU_ATTR_NONCACHED        0x0
-#define MSM_IOMMU_ATTR_CACHED_WB_WA     0x1
-#define MSM_IOMMU_ATTR_CACHED_WB_NWA    0x2
-#define MSM_IOMMU_ATTR_CACHED_WT        0x3
-
-/* Mask for the cache policy attribute */
-#define MSM_IOMMU_CP_MASK               0x03
-
-/* Maximum number of Machine IDs that we are allowing to be mapped to the same
- * context bank. The number of MIDs mapped to the same CB does not affect
- * performance, but there is a practical limit on how many distinct MIDs may
- * be present. These mappings are typically determined at design time and are
- * not expected to change at run time.
- */
-#define MAX_NUM_MIDS    32
-
-/**
- * struct msm_iommu_dev - a single IOMMU hardware instance
- * name         Human-readable name given to this IOMMU HW instance
- * ncb          Number of context banks present on this IOMMU HW instance
- */
-struct msm_iommu_dev {
-        const char *name;
-        int ncb;
-};
-
-/**
- * struct msm_iommu_ctx_dev - an IOMMU context bank instance
- * name         Human-readable name given to this context bank
- * num          Index of this context bank within the hardware
- * mids         List of Machine IDs that are to be mapped into this context
- *              bank, terminated by -1. The MID is a set of signals on the
- *              AXI bus that identifies the function associated with a specific
- *              memory request. (See ARM spec).
- */
-struct msm_iommu_ctx_dev {
-        const char *name;
-        int num;
-        int mids[MAX_NUM_MIDS];
-};
-
-
-/**
- * struct msm_iommu_drvdata - A single IOMMU hardware instance
- * @base:       IOMMU config port base address (VA)
- * @ncb         The number of contexts on this IOMMU
- * @irq:        Interrupt number
- * @clk:        The bus clock for this IOMMU hardware instance
- * @pclk:       The clock for the IOMMU bus interconnect
- *
- * A msm_iommu_drvdata holds the global driver data about a single piece
- * of an IOMMU hardware instance.
- */
-struct msm_iommu_drvdata {
-        void __iomem *base;
-        int irq;
-        int ncb;
-        struct clk *clk;
-        struct clk *pclk;
-};
-
-/**
- * struct msm_iommu_ctx_drvdata - an IOMMU context bank instance
- * @num:                Hardware context number of this context
- * @pdev:               Platform device associated wit this HW instance
- * @attached_elm:       List element for domains to track which devices are
- *                      attached to them
- *
- * A msm_iommu_ctx_drvdata holds the driver data for a single context bank
- * within each IOMMU hardware instance
- */
-struct msm_iommu_ctx_drvdata {
-        int num;
-        struct platform_device *pdev;
-        struct list_head attached_elm;
-};
-
-/*
- * Look up an IOMMU context device by its context name. NULL if none found.
- * Useful for testing and drivers that do not yet fully have IOMMU stuff in
- * their platform devices.
- */
-struct device *msm_iommu_get_ctx(const char *ctx_name);
-
-/*
- * Interrupt handler for the IOMMU context fault interrupt. Hooking the
- * interrupt is not supported in the API yet, but this will print an error
- * message and dump useful IOMMU registers.
- */
-irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id);
-
-#endif
diff --git a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
deleted file mode 100644
index fc160101dead..000000000000
--- a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
+++ /dev/null
@@ -1,1865 +0,0 @@
-/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-
-#ifndef __ARCH_ARM_MACH_MSM_IOMMU_HW_8XXX_H
-#define __ARCH_ARM_MACH_MSM_IOMMU_HW_8XXX_H
-
-#define CTX_SHIFT 12
-
-#define GET_GLOBAL_REG(reg, base) (readl((base) + (reg)))
-#define GET_CTX_REG(reg, base, ctx) \
-                                (readl((base) + (reg) + ((ctx) << CTX_SHIFT)))
-
-#define SET_GLOBAL_REG(reg, base, val)  writel((val), ((base) + (reg)))
-
-#define SET_CTX_REG(reg, base, ctx, val) \
-                        writel((val), ((base) + (reg) + ((ctx) << CTX_SHIFT)))
-
-/* Wrappers for numbered registers */
-#define SET_GLOBAL_REG_N(b, n, r, v) SET_GLOBAL_REG(b, ((r) + (n << 2)), (v))
-#define GET_GLOBAL_REG_N(b, n, r)    GET_GLOBAL_REG(b, ((r) + (n << 2)))
-
-/* Field wrappers */
-#define GET_GLOBAL_FIELD(b, r, F)    GET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT)
-#define GET_CONTEXT_FIELD(b, c, r, F)   \
-        GET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT)
-
-#define SET_GLOBAL_FIELD(b, r, F, v) \
-        SET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT, (v))
-#define SET_CONTEXT_FIELD(b, c, r, F, v)        \
-        SET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT, (v))
-
-#define GET_FIELD(addr, mask, shift)  ((readl(addr) >> (shift)) & (mask))
-
-#define SET_FIELD(addr, mask, shift, v) \
-do { \
-        int t = readl(addr); \
-        writel((t & ~((mask) << (shift))) + (((v) & (mask)) << (shift)), addr);\
-} while (0)
-
-
-#define NUM_FL_PTE      4096
-#define NUM_SL_PTE      256
-#define NUM_TEX_CLASS   8
-
-/* First-level page table bits */
-#define FL_BASE_MASK            0xFFFFFC00
-#define FL_TYPE_TABLE           (1 << 0)
-#define FL_TYPE_SECT            (2 << 0)
-#define FL_SUPERSECTION         (1 << 18)
-#define FL_AP_WRITE             (1 << 10)
-#define FL_AP_READ              (1 << 11)
-#define FL_SHARED               (1 << 16)
-#define FL_BUFFERABLE           (1 << 2)
-#define FL_CACHEABLE            (1 << 3)
-#define FL_TEX0                 (1 << 12)
-#define FL_OFFSET(va)           (((va) & 0xFFF00000) >> 20)
-#define FL_NG                   (1 << 17)
-
-/* Second-level page table bits */
-#define SL_BASE_MASK_LARGE      0xFFFF0000
-#define SL_BASE_MASK_SMALL      0xFFFFF000
-#define SL_TYPE_LARGE           (1 << 0)
-#define SL_TYPE_SMALL           (2 << 0)
-#define SL_AP0                  (1 << 4)
-#define SL_AP1                  (2 << 4)
-#define SL_SHARED               (1 << 10)
-#define SL_BUFFERABLE           (1 << 2)
-#define SL_CACHEABLE            (1 << 3)
-#define SL_TEX0                 (1 << 6)
-#define SL_OFFSET(va)           (((va) & 0xFF000) >> 12)
-#define SL_NG                   (1 << 11)
-
-/* Memory type and cache policy attributes */
-#define MT_SO                   0
-#define MT_DEV                  1
-#define MT_NORMAL               2
-#define CP_NONCACHED            0
-#define CP_WB_WA                1
-#define CP_WT                   2
-#define CP_WB_NWA               3
-
-/* Global register setters / getters */
-#define SET_M2VCBR_N(b, N, v)    SET_GLOBAL_REG_N(M2VCBR_N, N, (b), (v))
-#define SET_CBACR_N(b, N, v)     SET_GLOBAL_REG_N(CBACR_N, N, (b), (v))
-#define SET_TLBRSW(b, v)         SET_GLOBAL_REG(TLBRSW, (b), (v))
-#define SET_TLBTR0(b, v)         SET_GLOBAL_REG(TLBTR0, (b), (v))
-#define SET_TLBTR1(b, v)         SET_GLOBAL_REG(TLBTR1, (b), (v))
-#define SET_TLBTR2(b, v)         SET_GLOBAL_REG(TLBTR2, (b), (v))
-#define SET_TESTBUSCR(b, v)      SET_GLOBAL_REG(TESTBUSCR, (b), (v))
-#define SET_GLOBAL_TLBIALL(b, v) SET_GLOBAL_REG(GLOBAL_TLBIALL, (b), (v))
-#define SET_TLBIVMID(b, v)       SET_GLOBAL_REG(TLBIVMID, (b), (v))
-#define SET_CR(b, v)             SET_GLOBAL_REG(CR, (b), (v))
-#define SET_EAR(b, v)            SET_GLOBAL_REG(EAR, (b), (v))
-#define SET_ESR(b, v)            SET_GLOBAL_REG(ESR, (b), (v))
-#define SET_ESRRESTORE(b, v)     SET_GLOBAL_REG(ESRRESTORE, (b), (v))
-#define SET_ESYNR0(b, v)         SET_GLOBAL_REG(ESYNR0, (b), (v))
-#define SET_ESYNR1(b, v)         SET_GLOBAL_REG(ESYNR1, (b), (v))
-#define SET_RPU_ACR(b, v)        SET_GLOBAL_REG(RPU_ACR, (b), (v))
-
-#define GET_M2VCBR_N(b, N)       GET_GLOBAL_REG_N(M2VCBR_N, N, (b))
-#define GET_CBACR_N(b, N)        GET_GLOBAL_REG_N(CBACR_N, N, (b))
-#define GET_TLBTR0(b)            GET_GLOBAL_REG(TLBTR0, (b))
-#define GET_TLBTR1(b)            GET_GLOBAL_REG(TLBTR1, (b))
-#define GET_TLBTR2(b)            GET_GLOBAL_REG(TLBTR2, (b))
-#define GET_TESTBUSCR(b)         GET_GLOBAL_REG(TESTBUSCR, (b))
-#define GET_GLOBAL_TLBIALL(b)    GET_GLOBAL_REG(GLOBAL_TLBIALL, (b))
-#define GET_TLBIVMID(b)          GET_GLOBAL_REG(TLBIVMID, (b))
-#define GET_CR(b)                GET_GLOBAL_REG(CR, (b))
-#define GET_EAR(b)               GET_GLOBAL_REG(EAR, (b))
-#define GET_ESR(b)               GET_GLOBAL_REG(ESR, (b))
-#define GET_ESRRESTORE(b)        GET_GLOBAL_REG(ESRRESTORE, (b))
-#define GET_ESYNR0(b)            GET_GLOBAL_REG(ESYNR0, (b))
-#define GET_ESYNR1(b)            GET_GLOBAL_REG(ESYNR1, (b))
-#define GET_REV(b)               GET_GLOBAL_REG(REV, (b))
-#define GET_IDR(b)               GET_GLOBAL_REG(IDR, (b))
-#define GET_RPU_ACR(b)           GET_GLOBAL_REG(RPU_ACR, (b))
-
-
-/* Context register setters/getters */
-#define SET_SCTLR(b, c, v)       SET_CTX_REG(SCTLR, (b), (c), (v))
-#define SET_ACTLR(b, c, v)       SET_CTX_REG(ACTLR, (b), (c), (v))
-#define SET_CONTEXTIDR(b, c, v)  SET_CTX_REG(CONTEXTIDR, (b), (c), (v))
-#define SET_TTBR0(b, c, v)       SET_CTX_REG(TTBR0, (b), (c), (v))
-#define SET_TTBR1(b, c, v)       SET_CTX_REG(TTBR1, (b), (c), (v))
-#define SET_TTBCR(b, c, v)       SET_CTX_REG(TTBCR, (b), (c), (v))
-#define SET_PAR(b, c, v)         SET_CTX_REG(PAR, (b), (c), (v))
-#define SET_FSR(b, c, v)         SET_CTX_REG(FSR, (b), (c), (v))
-#define SET_FSRRESTORE(b, c, v)  SET_CTX_REG(FSRRESTORE, (b), (c), (v))
-#define SET_FAR(b, c, v)         SET_CTX_REG(FAR, (b), (c), (v))
-#define SET_FSYNR0(b, c, v)      SET_CTX_REG(FSYNR0, (b), (c), (v))
-#define SET_FSYNR1(b, c, v)      SET_CTX_REG(FSYNR1, (b), (c), (v))
-#define SET_PRRR(b, c, v)        SET_CTX_REG(PRRR, (b), (c), (v))
-#define SET_NMRR(b, c, v)        SET_CTX_REG(NMRR, (b), (c), (v))
-#define SET_TLBLKCR(b, c, v)     SET_CTX_REG(TLBLCKR, (b), (c), (v))
-#define SET_V2PSR(b, c, v)       SET_CTX_REG(V2PSR, (b), (c), (v))
-#define SET_TLBFLPTER(b, c, v)   SET_CTX_REG(TLBFLPTER, (b), (c), (v))
-#define SET_TLBSLPTER(b, c, v)   SET_CTX_REG(TLBSLPTER, (b), (c), (v))
-#define SET_BFBCR(b, c, v)       SET_CTX_REG(BFBCR, (b), (c), (v))
-#define SET_CTX_TLBIALL(b, c, v) SET_CTX_REG(CTX_TLBIALL, (b), (c), (v))
-#define SET_TLBIASID(b, c, v)    SET_CTX_REG(TLBIASID, (b), (c), (v))
-#define SET_TLBIVA(b, c, v)      SET_CTX_REG(TLBIVA, (b), (c), (v))
-#define SET_TLBIVAA(b, c, v)     SET_CTX_REG(TLBIVAA, (b), (c), (v))
-#define SET_V2PPR(b, c, v)       SET_CTX_REG(V2PPR, (b), (c), (v))
-#define SET_V2PPW(b, c, v)       SET_CTX_REG(V2PPW, (b), (c), (v))
-#define SET_V2PUR(b, c, v)       SET_CTX_REG(V2PUR, (b), (c), (v))
-#define SET_V2PUW(b, c, v)       SET_CTX_REG(V2PUW, (b), (c), (v))
-#define SET_RESUME(b, c, v)      SET_CTX_REG(RESUME, (b), (c), (v))
-
-#define GET_SCTLR(b, c)          GET_CTX_REG(SCTLR, (b), (c))
-#define GET_ACTLR(b, c)          GET_CTX_REG(ACTLR, (b), (c))
-#define GET_CONTEXTIDR(b, c)     GET_CTX_REG(CONTEXTIDR, (b), (c))
-#define GET_TTBR0(b, c)          GET_CTX_REG(TTBR0, (b), (c))
-#define GET_TTBR1(b, c)          GET_CTX_REG(TTBR1, (b), (c))
-#define GET_TTBCR(b, c)          GET_CTX_REG(TTBCR, (b), (c))
-#define GET_PAR(b, c)            GET_CTX_REG(PAR, (b), (c))
-#define GET_FSR(b, c)            GET_CTX_REG(FSR, (b), (c))
-#define GET_FSRRESTORE(b, c)     GET_CTX_REG(FSRRESTORE, (b), (c))
-#define GET_FAR(b, c)            GET_CTX_REG(FAR, (b), (c))
-#define GET_FSYNR0(b, c)         GET_CTX_REG(FSYNR0, (b), (c))
-#define GET_FSYNR1(b, c)         GET_CTX_REG(FSYNR1, (b), (c))
-#define GET_PRRR(b, c)           GET_CTX_REG(PRRR, (b), (c))
-#define GET_NMRR(b, c)           GET_CTX_REG(NMRR, (b), (c))
-#define GET_TLBLCKR(b, c)        GET_CTX_REG(TLBLCKR, (b), (c))
-#define GET_V2PSR(b, c)          GET_CTX_REG(V2PSR, (b), (c))
-#define GET_TLBFLPTER(b, c)      GET_CTX_REG(TLBFLPTER, (b), (c))
-#define GET_TLBSLPTER(b, c)      GET_CTX_REG(TLBSLPTER, (b), (c))
-#define GET_BFBCR(b, c)          GET_CTX_REG(BFBCR, (b), (c))
-#define GET_CTX_TLBIALL(b, c)    GET_CTX_REG(CTX_TLBIALL, (b), (c))
-#define GET_TLBIASID(b, c)       GET_CTX_REG(TLBIASID, (b), (c))
-#define GET_TLBIVA(b, c)         GET_CTX_REG(TLBIVA, (b), (c))
-#define GET_TLBIVAA(b, c)        GET_CTX_REG(TLBIVAA, (b), (c))
-#define GET_V2PPR(b, c)          GET_CTX_REG(V2PPR, (b), (c))
-#define GET_V2PPW(b, c)          GET_CTX_REG(V2PPW, (b), (c))
-#define GET_V2PUR(b, c)          GET_CTX_REG(V2PUR, (b), (c))
-#define GET_V2PUW(b, c)          GET_CTX_REG(V2PUW, (b), (c))
-#define GET_RESUME(b, c)         GET_CTX_REG(RESUME, (b), (c))
-
-
-/* Global field setters / getters */
-/* Global Field Setters: */
-/* CBACR_N */
-#define SET_RWVMID(b, n, v)   SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWVMID, v)
-#define SET_RWE(b, n, v)      SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWE, v)
-#define SET_RWGE(b, n, v)     SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWGE, v)
-#define SET_CBVMID(b, n, v)   SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), CBVMID, v)
-#define SET_IRPTNDX(b, n, v)  SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), IRPTNDX, v)
-
-
-/* M2VCBR_N */
-#define SET_VMID(b, n, v)     SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), VMID, v)
-#define SET_CBNDX(b, n, v)    SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), CBNDX, v)
-#define SET_BYPASSD(b, n, v)  SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BYPASSD, v)
-#define SET_BPRCOSH(b, n, v)  SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCOSH, v)
-#define SET_BPRCISH(b, n, v)  SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCISH, v)
-#define SET_BPRCNSH(b, n, v)  SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCNSH, v)
-#define SET_BPSHCFG(b, n, v)  SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPSHCFG, v)
-#define SET_NSCFG(b, n, v)    SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), NSCFG, v)
-#define SET_BPMTCFG(b, n, v)  SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMTCFG, v)
-#define SET_BPMEMTYPE(b, n, v) \
-        SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMEMTYPE, v)
-
-
-/* CR */
-#define SET_RPUE(b, v)           SET_GLOBAL_FIELD(b, CR, RPUE, v)
-#define SET_RPUERE(b, v)         SET_GLOBAL_FIELD(b, CR, RPUERE, v)
-#define SET_RPUEIE(b, v)         SET_GLOBAL_FIELD(b, CR, RPUEIE, v)
-#define SET_DCDEE(b, v)          SET_GLOBAL_FIELD(b, CR, DCDEE, v)
-#define SET_CLIENTPD(b, v)       SET_GLOBAL_FIELD(b, CR, CLIENTPD, v)
-#define SET_STALLD(b, v)         SET_GLOBAL_FIELD(b, CR, STALLD, v)
-#define SET_TLBLKCRWE(b, v)      SET_GLOBAL_FIELD(b, CR, TLBLKCRWE, v)
-#define SET_CR_TLBIALLCFG(b, v)  SET_GLOBAL_FIELD(b, CR, CR_TLBIALLCFG, v)
-#define SET_TLBIVMIDCFG(b, v)    SET_GLOBAL_FIELD(b, CR, TLBIVMIDCFG, v)
-#define SET_CR_HUME(b, v)        SET_GLOBAL_FIELD(b, CR, CR_HUME, v)
-
-
-/* ESR */
-#define SET_CFG(b, v)            SET_GLOBAL_FIELD(b, ESR, CFG, v)
-#define SET_BYPASS(b, v)         SET_GLOBAL_FIELD(b, ESR, BYPASS, v)
-#define SET_ESR_MULTI(b, v)      SET_GLOBAL_FIELD(b, ESR, ESR_MULTI, v)
-
-
-/* ESYNR0 */
-#define SET_ESYNR0_AMID(b, v)    SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AMID, v)
-#define SET_ESYNR0_APID(b, v)    SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_APID, v)
-#define SET_ESYNR0_ABID(b, v)    SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ABID, v)
-#define SET_ESYNR0_AVMID(b, v)   SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AVMID, v)
-#define SET_ESYNR0_ATID(b, v)    SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ATID, v)
-
-
-/* ESYNR1 */
-#define SET_ESYNR1_AMEMTYPE(b, v) \
-                        SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AMEMTYPE, v)
-#define SET_ESYNR1_ASHARED(b, v)  SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASHARED, v)
-#define SET_ESYNR1_AINNERSHARED(b, v) \
-                        SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINNERSHARED, v)
-#define SET_ESYNR1_APRIV(b, v)   SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APRIV, v)
-#define SET_ESYNR1_APROTNS(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APROTNS, v)
-#define SET_ESYNR1_AINST(b, v)   SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINST, v)
-#define SET_ESYNR1_AWRITE(b, v)  SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AWRITE, v)
-#define SET_ESYNR1_ABURST(b, v)  SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ABURST, v)
-#define SET_ESYNR1_ALEN(b, v)    SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALEN, v)
-#define SET_ESYNR1_ASIZE(b, v)   SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASIZE, v)
-#define SET_ESYNR1_ALOCK(b, v)   SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALOCK, v)
-#define SET_ESYNR1_AOOO(b, v)    SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AOOO, v)
-#define SET_ESYNR1_AFULL(b, v)   SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AFULL, v)
-#define SET_ESYNR1_AC(b, v)      SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AC, v)
-#define SET_ESYNR1_DCD(b, v)     SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_DCD, v)
-
-
-/* TESTBUSCR */
-#define SET_TBE(b, v)            SET_GLOBAL_FIELD(b, TESTBUSCR, TBE, v)
-#define SET_SPDMBE(b, v)         SET_GLOBAL_FIELD(b, TESTBUSCR, SPDMBE, v)
-#define SET_WGSEL(b, v)          SET_GLOBAL_FIELD(b, TESTBUSCR, WGSEL, v)
-#define SET_TBLSEL(b, v)         SET_GLOBAL_FIELD(b, TESTBUSCR, TBLSEL, v)
-#define SET_TBHSEL(b, v)         SET_GLOBAL_FIELD(b, TESTBUSCR, TBHSEL, v)
-#define SET_SPDM0SEL(b, v)       SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM0SEL, v)
-#define SET_SPDM1SEL(b, v)       SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM1SEL, v)
-#define SET_SPDM2SEL(b, v)       SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM2SEL, v)
-#define SET_SPDM3SEL(b, v)       SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM3SEL, v)
-
-
-/* TLBIVMID */
-#define SET_TLBIVMID_VMID(b, v)  SET_GLOBAL_FIELD(b, TLBIVMID, TLBIVMID_VMID, v)
-
-
-/* TLBRSW */
-#define SET_TLBRSW_INDEX(b, v)   SET_GLOBAL_FIELD(b, TLBRSW, TLBRSW_INDEX, v)
-#define SET_TLBBFBS(b, v)        SET_GLOBAL_FIELD(b, TLBRSW, TLBBFBS, v)
-
-
-/* TLBTR0 */
-#define SET_PR(b, v)             SET_GLOBAL_FIELD(b, TLBTR0, PR, v)
-#define SET_PW(b, v)             SET_GLOBAL_FIELD(b, TLBTR0, PW, v)
-#define SET_UR(b, v)             SET_GLOBAL_FIELD(b, TLBTR0, UR, v)
-#define SET_UW(b, v)             SET_GLOBAL_FIELD(b, TLBTR0, UW, v)
-#define SET_XN(b, v)             SET_GLOBAL_FIELD(b, TLBTR0, XN, v)
-#define SET_NSDESC(b, v)         SET_GLOBAL_FIELD(b, TLBTR0, NSDESC, v)
-#define SET_ISH(b, v)            SET_GLOBAL_FIELD(b, TLBTR0, ISH, v)
-#define SET_SH(b, v)             SET_GLOBAL_FIELD(b, TLBTR0, SH, v)
-#define SET_MT(b, v)             SET_GLOBAL_FIELD(b, TLBTR0, MT, v)
-#define SET_DPSIZR(b, v)         SET_GLOBAL_FIELD(b, TLBTR0, DPSIZR, v)
-#define SET_DPSIZC(b, v)         SET_GLOBAL_FIELD(b, TLBTR0, DPSIZC, v)
-
-
-/* TLBTR1 */
-#define SET_TLBTR1_VMID(b, v)    SET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_VMID, v)
-#define SET_TLBTR1_PA(b, v)      SET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_PA, v)
-
-
-/* TLBTR2 */
-#define SET_TLBTR2_ASID(b, v)    SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_ASID, v)
-#define SET_TLBTR2_V(b, v)       SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_V, v)
-#define SET_TLBTR2_NSTID(b, v)   SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NSTID, v)
-#define SET_TLBTR2_NV(b, v)      SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NV, v)
-#define SET_TLBTR2_VA(b, v)      SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_VA, v)
-
-
-/* Global Field Getters */
-/* CBACR_N */
-#define GET_RWVMID(b, n)         GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWVMID)
-#define GET_RWE(b, n)            GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWE)
-#define GET_RWGE(b, n)           GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWGE)
-#define GET_CBVMID(b, n)         GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), CBVMID)
-#define GET_IRPTNDX(b, n)        GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), IRPTNDX)
-
-
-/* M2VCBR_N */
-#define GET_VMID(b, n)       GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), VMID)
-#define GET_CBNDX(b, n)      GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), CBNDX)
-#define GET_BYPASSD(b, n)    GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BYPASSD)
-#define GET_BPRCOSH(b, n)    GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCOSH)
-#define GET_BPRCISH(b, n)    GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCISH)
-#define GET_BPRCNSH(b, n)    GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCNSH)
-#define GET_BPSHCFG(b, n)    GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPSHCFG)
-#define GET_NSCFG(b, n)      GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), NSCFG)
-#define GET_BPMTCFG(b, n)    GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMTCFG)
-#define GET_BPMEMTYPE(b, n)  GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMEMTYPE)
-
-
-/* CR */
-#define GET_RPUE(b)              GET_GLOBAL_FIELD(b, CR, RPUE)
-#define GET_RPUERE(b)            GET_GLOBAL_FIELD(b, CR, RPUERE)
-#define GET_RPUEIE(b)            GET_GLOBAL_FIELD(b, CR, RPUEIE)
-#define GET_DCDEE(b)             GET_GLOBAL_FIELD(b, CR, DCDEE)
-#define GET_CLIENTPD(b)          GET_GLOBAL_FIELD(b, CR, CLIENTPD)
-#define GET_STALLD(b)            GET_GLOBAL_FIELD(b, CR, STALLD)
-#define GET_TLBLKCRWE(b)         GET_GLOBAL_FIELD(b, CR, TLBLKCRWE)
-#define GET_CR_TLBIALLCFG(b)     GET_GLOBAL_FIELD(b, CR, CR_TLBIALLCFG)
-#define GET_TLBIVMIDCFG(b)       GET_GLOBAL_FIELD(b, CR, TLBIVMIDCFG)
-#define GET_CR_HUME(b)           GET_GLOBAL_FIELD(b, CR, CR_HUME)
-
-
-/* ESR */
-#define GET_CFG(b)               GET_GLOBAL_FIELD(b, ESR, CFG)
-#define GET_BYPASS(b)            GET_GLOBAL_FIELD(b, ESR, BYPASS)
-#define GET_ESR_MULTI(b)         GET_GLOBAL_FIELD(b, ESR, ESR_MULTI)
-
-
-/* ESYNR0 */
-#define GET_ESYNR0_AMID(b)       GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AMID)
-#define GET_ESYNR0_APID(b)       GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_APID)
-#define GET_ESYNR0_ABID(b)       GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ABID)
-#define GET_ESYNR0_AVMID(b)      GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AVMID)
-#define GET_ESYNR0_ATID(b)       GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ATID)
-
-
-/* ESYNR1 */
-#define GET_ESYNR1_AMEMTYPE(b)   GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AMEMTYPE)
-#define GET_ESYNR1_ASHARED(b)    GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASHARED)
-#define GET_ESYNR1_AINNERSHARED(b) \
-                        GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINNERSHARED)
-#define GET_ESYNR1_APRIV(b)      GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APRIV)
-#define GET_ESYNR1_APROTNS(b)    GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APROTNS)
-#define GET_ESYNR1_AINST(b)      GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINST)
-#define GET_ESYNR1_AWRITE(b)     GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AWRITE)
-#define GET_ESYNR1_ABURST(b)     GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ABURST)
-#define GET_ESYNR1_ALEN(b)       GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALEN)
-#define GET_ESYNR1_ASIZE(b)      GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASIZE)
-#define GET_ESYNR1_ALOCK(b)      GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALOCK)
-#define GET_ESYNR1_AOOO(b)       GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AOOO)
-#define GET_ESYNR1_AFULL(b)      GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AFULL)
-#define GET_ESYNR1_AC(b)         GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AC)
-#define GET_ESYNR1_DCD(b)        GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_DCD)
-
-
-/* IDR */
-#define GET_NM2VCBMT(b)          GET_GLOBAL_FIELD(b, IDR, NM2VCBMT)
-#define GET_HTW(b)               GET_GLOBAL_FIELD(b, IDR, HTW)
-#define GET_HUM(b)               GET_GLOBAL_FIELD(b, IDR, HUM)
-#define GET_TLBSIZE(b)           GET_GLOBAL_FIELD(b, IDR, TLBSIZE)
-#define GET_NCB(b)               GET_GLOBAL_FIELD(b, IDR, NCB)
-#define GET_NIRPT(b)             GET_GLOBAL_FIELD(b, IDR, NIRPT)
-
-
-/* REV */
-#define GET_MAJOR(b)             GET_GLOBAL_FIELD(b, REV, MAJOR)
-#define GET_MINOR(b)             GET_GLOBAL_FIELD(b, REV, MINOR)
-
-
-/* TESTBUSCR */
-#define GET_TBE(b)               GET_GLOBAL_FIELD(b, TESTBUSCR, TBE)
-#define GET_SPDMBE(b)            GET_GLOBAL_FIELD(b, TESTBUSCR, SPDMBE)
-#define GET_WGSEL(b)             GET_GLOBAL_FIELD(b, TESTBUSCR, WGSEL)
-#define GET_TBLSEL(b)            GET_GLOBAL_FIELD(b, TESTBUSCR, TBLSEL)
-#define GET_TBHSEL(b)            GET_GLOBAL_FIELD(b, TESTBUSCR, TBHSEL)
-#define GET_SPDM0SEL(b)          GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM0SEL)
-#define GET_SPDM1SEL(b)          GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM1SEL)
-#define GET_SPDM2SEL(b)          GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM2SEL)
-#define GET_SPDM3SEL(b)          GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM3SEL)
-
-
-/* TLBIVMID */
-#define GET_TLBIVMID_VMID(b)     GET_GLOBAL_FIELD(b, TLBIVMID, TLBIVMID_VMID)
-
-
-/* TLBTR0 */
-#define GET_PR(b)                GET_GLOBAL_FIELD(b, TLBTR0, PR)
-#define GET_PW(b)                GET_GLOBAL_FIELD(b, TLBTR0, PW)
-#define GET_UR(b)                GET_GLOBAL_FIELD(b, TLBTR0, UR)
-#define GET_UW(b)                GET_GLOBAL_FIELD(b, TLBTR0, UW)
-#define GET_XN(b)                GET_GLOBAL_FIELD(b, TLBTR0, XN)
-#define GET_NSDESC(b)            GET_GLOBAL_FIELD(b, TLBTR0, NSDESC)
-#define GET_ISH(b)               GET_GLOBAL_FIELD(b, TLBTR0, ISH)
-#define GET_SH(b)                GET_GLOBAL_FIELD(b, TLBTR0, SH)
-#define GET_MT(b)                GET_GLOBAL_FIELD(b, TLBTR0, MT)
-#define GET_DPSIZR(b)            GET_GLOBAL_FIELD(b, TLBTR0, DPSIZR)
-#define GET_DPSIZC(b)            GET_GLOBAL_FIELD(b, TLBTR0, DPSIZC)
-
-
-/* TLBTR1 */
-#define GET_TLBTR1_VMID(b)       GET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_VMID)
-#define GET_TLBTR1_PA(b)         GET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_PA)
-
-
-/* TLBTR2 */
-#define GET_TLBTR2_ASID(b)       GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_ASID)
-#define GET_TLBTR2_V(b)          GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_V)
-#define GET_TLBTR2_NSTID(b)      GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NSTID)
-#define GET_TLBTR2_NV(b)         GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NV)
-#define GET_TLBTR2_VA(b)         GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_VA)
-
-
-/* Context Register setters / getters */
-/* Context Register setters */
-/* ACTLR */
-#define SET_CFERE(b, c, v)       SET_CONTEXT_FIELD(b, c, ACTLR, CFERE, v)
-#define SET_CFEIE(b, c, v)       SET_CONTEXT_FIELD(b, c, ACTLR, CFEIE, v)
-#define SET_PTSHCFG(b, c, v)     SET_CONTEXT_FIELD(b, c, ACTLR, PTSHCFG, v)
-#define SET_RCOSH(b, c, v)       SET_CONTEXT_FIELD(b, c, ACTLR, RCOSH, v)
-#define SET_RCISH(b, c, v)       SET_CONTEXT_FIELD(b, c, ACTLR, RCISH, v)
-#define SET_RCNSH(b, c, v)       SET_CONTEXT_FIELD(b, c, ACTLR, RCNSH, v)
-#define SET_PRIVCFG(b, c, v)     SET_CONTEXT_FIELD(b, c, ACTLR, PRIVCFG, v)
-#define SET_DNA(b, c, v)         SET_CONTEXT_FIELD(b, c, ACTLR, DNA, v)
-#define SET_DNLV2PA(b, c, v)     SET_CONTEXT_FIELD(b, c, ACTLR, DNLV2PA, v)
-#define SET_TLBMCFG(b, c, v)     SET_CONTEXT_FIELD(b, c, ACTLR, TLBMCFG, v)
-#define SET_CFCFG(b, c, v)       SET_CONTEXT_FIELD(b, c, ACTLR, CFCFG, v)
-#define SET_TIPCF(b, c, v)       SET_CONTEXT_FIELD(b, c, ACTLR, TIPCF, v)
-#define SET_V2PCFG(b, c, v)      SET_CONTEXT_FIELD(b, c, ACTLR, V2PCFG, v)
-#define SET_HUME(b, c, v)        SET_CONTEXT_FIELD(b, c, ACTLR, HUME, v)
-#define SET_PTMTCFG(b, c, v)     SET_CONTEXT_FIELD(b, c, ACTLR, PTMTCFG, v)
-#define SET_PTMEMTYPE(b, c, v)   SET_CONTEXT_FIELD(b, c, ACTLR, PTMEMTYPE, v)
-
-
-/* BFBCR */
-#define SET_BFBDFE(b, c, v)      SET_CONTEXT_FIELD(b, c, BFBCR, BFBDFE, v)
-#define SET_BFBSFE(b, c, v)      SET_CONTEXT_FIELD(b, c, BFBCR, BFBSFE, v)
-#define SET_SFVS(b, c, v)        SET_CONTEXT_FIELD(b, c, BFBCR, SFVS, v)
-#define SET_FLVIC(b, c, v)       SET_CONTEXT_FIELD(b, c, BFBCR, FLVIC, v)
-#define SET_SLVIC(b, c, v)       SET_CONTEXT_FIELD(b, c, BFBCR, SLVIC, v)
-
-
-/* CONTEXTIDR */
-#define SET_CONTEXTIDR_ASID(b, c, v)   \
-                SET_CONTEXT_FIELD(b, c, CONTEXTIDR, CONTEXTIDR_ASID, v)
-#define SET_CONTEXTIDR_PROCID(b, c, v) \
-                SET_CONTEXT_FIELD(b, c, CONTEXTIDR, PROCID, v)
-
-
-/* FSR */
-#define SET_TF(b, c, v)          SET_CONTEXT_FIELD(b, c, FSR, TF, v)
-#define SET_AFF(b, c, v)         SET_CONTEXT_FIELD(b, c, FSR, AFF, v)
-#define SET_APF(b, c, v)         SET_CONTEXT_FIELD(b, c, FSR, APF, v)
-#define SET_TLBMF(b, c, v)       SET_CONTEXT_FIELD(b, c, FSR, TLBMF, v)
-#define SET_HTWDEEF(b, c, v)     SET_CONTEXT_FIELD(b, c, FSR, HTWDEEF, v)
-#define SET_HTWSEEF(b, c, v)     SET_CONTEXT_FIELD(b, c, FSR, HTWSEEF, v)
-#define SET_MHF(b, c, v)         SET_CONTEXT_FIELD(b, c, FSR, MHF, v)
-#define SET_SL(b, c, v)          SET_CONTEXT_FIELD(b, c, FSR, SL, v)
-#define SET_SS(b, c, v)          SET_CONTEXT_FIELD(b, c, FSR, SS, v)
-#define SET_MULTI(b, c, v)       SET_CONTEXT_FIELD(b, c, FSR, MULTI, v)
-
-
-/* FSYNR0 */
-#define SET_AMID(b, c, v)        SET_CONTEXT_FIELD(b, c, FSYNR0, AMID, v)
-#define SET_APID(b, c, v)        SET_CONTEXT_FIELD(b, c, FSYNR0, APID, v)
-#define SET_ABID(b, c, v)        SET_CONTEXT_FIELD(b, c, FSYNR0, ABID, v)
-#define SET_ATID(b, c, v)        SET_CONTEXT_FIELD(b, c, FSYNR0, ATID, v)
-
-
-/* FSYNR1 */
-#define SET_AMEMTYPE(b, c, v)    SET_CONTEXT_FIELD(b, c, FSYNR1, AMEMTYPE, v)
-#define SET_ASHARED(b, c, v)     SET_CONTEXT_FIELD(b, c, FSYNR1, ASHARED, v)
-#define SET_AINNERSHARED(b, c, v)  \
-                                SET_CONTEXT_FIELD(b, c, FSYNR1, AINNERSHARED, v)
-#define SET_APRIV(b, c, v)       SET_CONTEXT_FIELD(b, c, FSYNR1, APRIV, v)
-#define SET_APROTNS(b, c, v)     SET_CONTEXT_FIELD(b, c, FSYNR1, APROTNS, v)
-#define SET_AINST(b, c, v)       SET_CONTEXT_FIELD(b, c, FSYNR1, AINST, v)
-#define SET_AWRITE(b, c, v)      SET_CONTEXT_FIELD(b, c, FSYNR1, AWRITE, v)
-#define SET_ABURST(b, c, v)      SET_CONTEXT_FIELD(b, c, FSYNR1, ABURST, v)
-#define SET_ALEN(b, c, v)        SET_CONTEXT_FIELD(b, c, FSYNR1, ALEN, v)
-#define SET_FSYNR1_ASIZE(b, c, v) \
-                                SET_CONTEXT_FIELD(b, c, FSYNR1, FSYNR1_ASIZE, v)
-#define SET_ALOCK(b, c, v)       SET_CONTEXT_FIELD(b, c, FSYNR1, ALOCK, v)
-#define SET_AFULL(b, c, v)       SET_CONTEXT_FIELD(b, c, FSYNR1, AFULL, v)
-
-
-/* NMRR */
-#define SET_ICPC0(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, ICPC0, v)
-#define SET_ICPC1(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, ICPC1, v)
-#define SET_ICPC2(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, ICPC2, v)
-#define SET_ICPC3(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, ICPC3, v)
-#define SET_ICPC4(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, ICPC4, v)
-#define SET_ICPC5(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, ICPC5, v)
-#define SET_ICPC6(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, ICPC6, v)
-#define SET_ICPC7(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, ICPC7, v)
-#define SET_OCPC0(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, OCPC0, v)
-#define SET_OCPC1(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, OCPC1, v)
-#define SET_OCPC2(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, OCPC2, v)
-#define SET_OCPC3(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, OCPC3, v)
-#define SET_OCPC4(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, OCPC4, v)
-#define SET_OCPC5(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, OCPC5, v)
-#define SET_OCPC6(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, OCPC6, v)
-#define SET_OCPC7(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, OCPC7, v)
-
-
-/* PAR */
-#define SET_FAULT(b, c, v)       SET_CONTEXT_FIELD(b, c, PAR, FAULT, v)
-
-#define SET_FAULT_TF(b, c, v)    SET_CONTEXT_FIELD(b, c, PAR, FAULT_TF, v)
-#define SET_FAULT_AFF(b, c, v)   SET_CONTEXT_FIELD(b, c, PAR, FAULT_AFF, v)
-#define SET_FAULT_APF(b, c, v)   SET_CONTEXT_FIELD(b, c, PAR, FAULT_APF, v)
-#define SET_FAULT_TLBMF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_TLBMF, v)
-#define SET_FAULT_HTWDEEF(b, c, v) \
-                                SET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWDEEF, v)
-#define SET_FAULT_HTWSEEF(b, c, v) \
-                                SET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWSEEF, v)
-#define SET_FAULT_MHF(b, c, v)   SET_CONTEXT_FIELD(b, c, PAR, FAULT_MHF, v)
-#define SET_FAULT_SL(b, c, v)    SET_CONTEXT_FIELD(b, c, PAR, FAULT_SL, v)
-#define SET_FAULT_SS(b, c, v)    SET_CONTEXT_FIELD(b, c, PAR, FAULT_SS, v)
-
-#define SET_NOFAULT_SS(b, c, v)  SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_SS, v)
-#define SET_NOFAULT_MT(b, c, v)  SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_MT, v)
-#define SET_NOFAULT_SH(b, c, v)  SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_SH, v)
-#define SET_NOFAULT_NS(b, c, v)  SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_NS, v)
-#define SET_NOFAULT_NOS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_NOS, v)
-#define SET_NPFAULT_PA(b, c, v)  SET_CONTEXT_FIELD(b, c, PAR, NPFAULT_PA, v)
-
-
-/* PRRR */
-#define SET_MTC0(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, MTC0, v)
-#define SET_MTC1(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, MTC1, v)
-#define SET_MTC2(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, MTC2, v)
-#define SET_MTC3(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, MTC3, v)
-#define SET_MTC4(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, MTC4, v)
-#define SET_MTC5(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, MTC5, v)
-#define SET_MTC6(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, MTC6, v)
-#define SET_MTC7(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, MTC7, v)
-#define SET_SHDSH0(b, c, v)      SET_CONTEXT_FIELD(b, c, PRRR, SHDSH0, v)
-#define SET_SHDSH1(b, c, v)      SET_CONTEXT_FIELD(b, c, PRRR, SHDSH1, v)
-#define SET_SHNMSH0(b, c, v)     SET_CONTEXT_FIELD(b, c, PRRR, SHNMSH0, v)
-#define SET_SHNMSH1(b, c, v)     SET_CONTEXT_FIELD(b, c, PRRR, SHNMSH1, v)
-#define SET_NOS0(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, NOS0, v)
-#define SET_NOS1(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, NOS1, v)
-#define SET_NOS2(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, NOS2, v)
-#define SET_NOS3(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, NOS3, v)
-#define SET_NOS4(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, NOS4, v)
-#define SET_NOS5(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, NOS5, v)
-#define SET_NOS6(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, NOS6, v)
-#define SET_NOS7(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, NOS7, v)
-
-
-/* RESUME */
-#define SET_TNR(b, c, v)         SET_CONTEXT_FIELD(b, c, RESUME, TNR, v)
-
-
-/* SCTLR */
-#define SET_M(b, c, v)           SET_CONTEXT_FIELD(b, c, SCTLR, M, v)
-#define SET_TRE(b, c, v)         SET_CONTEXT_FIELD(b, c, SCTLR, TRE, v)
-#define SET_AFE(b, c, v)         SET_CONTEXT_FIELD(b, c, SCTLR, AFE, v)
-#define SET_HAF(b, c, v)         SET_CONTEXT_FIELD(b, c, SCTLR, HAF, v)
-#define SET_BE(b, c, v)          SET_CONTEXT_FIELD(b, c, SCTLR, BE, v)
-#define SET_AFFD(b, c, v)        SET_CONTEXT_FIELD(b, c, SCTLR, AFFD, v)
-
-
-/* TLBLKCR */
-#define SET_LKE(b, c, v)           SET_CONTEXT_FIELD(b, c, TLBLKCR, LKE, v)
-#define SET_TLBLKCR_TLBIALLCFG(b, c, v) \
-                        SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBLCKR_TLBIALLCFG, v)
-#define SET_TLBIASIDCFG(b, c, v) \
-                        SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIASIDCFG, v)
-#define SET_TLBIVAACFG(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIVAACFG, v)
-#define SET_FLOOR(b, c, v)      SET_CONTEXT_FIELD(b, c, TLBLKCR, FLOOR, v)
-#define SET_VICTIM(b, c, v)     SET_CONTEXT_FIELD(b, c, TLBLKCR, VICTIM, v)
-
-
-/* TTBCR */
-#define SET_N(b, c, v)           SET_CONTEXT_FIELD(b, c, TTBCR, N, v)
-#define SET_PD0(b, c, v)         SET_CONTEXT_FIELD(b, c, TTBCR, PD0, v)
-#define SET_PD1(b, c, v)         SET_CONTEXT_FIELD(b, c, TTBCR, PD1, v)
-
-
-/* TTBR0 */
-#define SET_TTBR0_IRGNH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNH, v)
-#define SET_TTBR0_SH(b, c, v)    SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_SH, v)
-#define SET_TTBR0_ORGN(b, c, v)  SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_ORGN, v)
-#define SET_TTBR0_NOS(b, c, v)   SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_NOS, v)
-#define SET_TTBR0_IRGNL(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNL, v)
-#define SET_TTBR0_PA(b, c, v)    SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_PA, v)
-
-
-/* TTBR1 */
-#define SET_TTBR1_IRGNH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNH, v)
-#define SET_TTBR1_SH(b, c, v)    SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_SH, v)
-#define SET_TTBR1_ORGN(b, c, v)  SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_ORGN, v)
-#define SET_TTBR1_NOS(b, c, v)   SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_NOS, v)
-#define SET_TTBR1_IRGNL(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNL, v)
-#define SET_TTBR1_PA(b, c, v)    SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_PA, v)
-
-
-/* V2PSR */
-#define SET_HIT(b, c, v)         SET_CONTEXT_FIELD(b, c, V2PSR, HIT, v)
-#define SET_INDEX(b, c, v)       SET_CONTEXT_FIELD(b, c, V2PSR, INDEX, v)
-
-
-/* Context Register getters */
-/* ACTLR */
-#define GET_CFERE(b, c)         GET_CONTEXT_FIELD(b, c, ACTLR, CFERE)
-#define GET_CFEIE(b, c)         GET_CONTEXT_FIELD(b, c, ACTLR, CFEIE)
-#define GET_PTSHCFG(b, c)       GET_CONTEXT_FIELD(b, c, ACTLR, PTSHCFG)
-#define GET_RCOSH(b, c)         GET_CONTEXT_FIELD(b, c, ACTLR, RCOSH)
-#define GET_RCISH(b, c)         GET_CONTEXT_FIELD(b, c, ACTLR, RCISH)
-#define GET_RCNSH(b, c)         GET_CONTEXT_FIELD(b, c, ACTLR, RCNSH)
-#define GET_PRIVCFG(b, c)       GET_CONTEXT_FIELD(b, c, ACTLR, PRIVCFG)
-#define GET_DNA(b, c)           GET_CONTEXT_FIELD(b, c, ACTLR, DNA)
-#define GET_DNLV2PA(b, c)       GET_CONTEXT_FIELD(b, c, ACTLR, DNLV2PA)
-#define GET_TLBMCFG(b, c)       GET_CONTEXT_FIELD(b, c, ACTLR, TLBMCFG)
-#define GET_CFCFG(b, c)         GET_CONTEXT_FIELD(b, c, ACTLR, CFCFG)
-#define GET_TIPCF(b, c)         GET_CONTEXT_FIELD(b, c, ACTLR, TIPCF)
-#define GET_V2PCFG(b, c)        GET_CONTEXT_FIELD(b, c, ACTLR, V2PCFG)
-#define GET_HUME(b, c)          GET_CONTEXT_FIELD(b, c, ACTLR, HUME)
-#define GET_PTMTCFG(b, c)       GET_CONTEXT_FIELD(b, c, ACTLR, PTMTCFG)
-#define GET_PTMEMTYPE(b, c)     GET_CONTEXT_FIELD(b, c, ACTLR, PTMEMTYPE)
-
-/* BFBCR */
-#define GET_BFBDFE(b, c)        GET_CONTEXT_FIELD(b, c, BFBCR, BFBDFE)
-#define GET_BFBSFE(b, c)        GET_CONTEXT_FIELD(b, c, BFBCR, BFBSFE)
-#define GET_SFVS(b, c)          GET_CONTEXT_FIELD(b, c, BFBCR, SFVS)
-#define GET_FLVIC(b, c)         GET_CONTEXT_FIELD(b, c, BFBCR, FLVIC)
-#define GET_SLVIC(b, c)         GET_CONTEXT_FIELD(b, c, BFBCR, SLVIC)
-
-
-/* CONTEXTIDR */
-#define GET_CONTEXTIDR_ASID(b, c) \
-                        GET_CONTEXT_FIELD(b, c, CONTEXTIDR, CONTEXTIDR_ASID)
-#define GET_CONTEXTIDR_PROCID(b, c) GET_CONTEXT_FIELD(b, c, CONTEXTIDR, PROCID)
-
-
-/* FSR */
-#define GET_TF(b, c)            GET_CONTEXT_FIELD(b, c, FSR, TF)
-#define GET_AFF(b, c)           GET_CONTEXT_FIELD(b, c, FSR, AFF)
-#define GET_APF(b, c)           GET_CONTEXT_FIELD(b, c, FSR, APF)
-#define GET_TLBMF(b, c)         GET_CONTEXT_FIELD(b, c, FSR, TLBMF)
-#define GET_HTWDEEF(b, c)       GET_CONTEXT_FIELD(b, c, FSR, HTWDEEF)
-#define GET_HTWSEEF(b, c)       GET_CONTEXT_FIELD(b, c, FSR, HTWSEEF)
-#define GET_MHF(b, c)           GET_CONTEXT_FIELD(b, c, FSR, MHF)
-#define GET_SL(b, c)            GET_CONTEXT_FIELD(b, c, FSR, SL)
-#define GET_SS(b, c)            GET_CONTEXT_FIELD(b, c, FSR, SS)
-#define GET_MULTI(b, c)         GET_CONTEXT_FIELD(b, c, FSR, MULTI)
-
-
-/* FSYNR0 */
-#define GET_AMID(b, c)          GET_CONTEXT_FIELD(b, c, FSYNR0, AMID)
-#define GET_APID(b, c)          GET_CONTEXT_FIELD(b, c, FSYNR0, APID)
-#define GET_ABID(b, c)          GET_CONTEXT_FIELD(b, c, FSYNR0, ABID)
-#define GET_ATID(b, c)          GET_CONTEXT_FIELD(b, c, FSYNR0, ATID)
-
-
-/* FSYNR1 */
-#define GET_AMEMTYPE(b, c)      GET_CONTEXT_FIELD(b, c, FSYNR1, AMEMTYPE)
-#define GET_ASHARED(b, c)       GET_CONTEXT_FIELD(b, c, FSYNR1, ASHARED)
-#define GET_AINNERSHARED(b, c)  GET_CONTEXT_FIELD(b, c, FSYNR1, AINNERSHARED)
-#define GET_APRIV(b, c)         GET_CONTEXT_FIELD(b, c, FSYNR1, APRIV)
-#define GET_APROTNS(b, c)       GET_CONTEXT_FIELD(b, c, FSYNR1, APROTNS)
-#define GET_AINST(b, c)         GET_CONTEXT_FIELD(b, c, FSYNR1, AINST)
-#define GET_AWRITE(b, c)        GET_CONTEXT_FIELD(b, c, FSYNR1, AWRITE)
-#define GET_ABURST(b, c)        GET_CONTEXT_FIELD(b, c, FSYNR1, ABURST)
-#define GET_ALEN(b, c)          GET_CONTEXT_FIELD(b, c, FSYNR1, ALEN)
-#define GET_FSYNR1_ASIZE(b, c)  GET_CONTEXT_FIELD(b, c, FSYNR1, FSYNR1_ASIZE)
-#define GET_ALOCK(b, c)         GET_CONTEXT_FIELD(b, c, FSYNR1, ALOCK)
-#define GET_AFULL(b, c)         GET_CONTEXT_FIELD(b, c, FSYNR1, AFULL)
-
-
-/* NMRR */
-#define GET_ICPC0(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, ICPC0)
-#define GET_ICPC1(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, ICPC1)
-#define GET_ICPC2(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, ICPC2)
-#define GET_ICPC3(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, ICPC3)
-#define GET_ICPC4(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, ICPC4)
-#define GET_ICPC5(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, ICPC5)
-#define GET_ICPC6(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, ICPC6)
-#define GET_ICPC7(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, ICPC7)
-#define GET_OCPC0(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC0)
-#define GET_OCPC1(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC1)
-#define GET_OCPC2(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC2)
-#define GET_OCPC3(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC3)
-#define GET_OCPC4(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC4)
-#define GET_OCPC5(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC5)
-#define GET_OCPC6(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC6)
-#define GET_OCPC7(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC7)
-#define NMRR_ICP(nmrr, n)       (((nmrr) & (3 << ((n) * 2))) >> ((n) * 2))
-#define NMRR_OCP(nmrr, n)       (((nmrr) & (3 << ((n) * 2 + 16))) >> \
-                                                                ((n) * 2 + 16))
-
-/* PAR */
-#define GET_FAULT(b, c)         GET_CONTEXT_FIELD(b, c, PAR, FAULT)
-
-#define GET_FAULT_TF(b, c)      GET_CONTEXT_FIELD(b, c, PAR, FAULT_TF)
-#define GET_FAULT_AFF(b, c)     GET_CONTEXT_FIELD(b, c, PAR, FAULT_AFF)
-#define GET_FAULT_APF(b, c)     GET_CONTEXT_FIELD(b, c, PAR, FAULT_APF)
-#define GET_FAULT_TLBMF(b, c)   GET_CONTEXT_FIELD(b, c, PAR, FAULT_TLBMF)
-#define GET_FAULT_HTWDEEF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWDEEF)
-#define GET_FAULT_HTWSEEF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWSEEF)
-#define GET_FAULT_MHF(b, c)     GET_CONTEXT_FIELD(b, c, PAR, FAULT_MHF)
-#define GET_FAULT_SL(b, c)      GET_CONTEXT_FIELD(b, c, PAR, FAULT_SL)
-#define GET_FAULT_SS(b, c)      GET_CONTEXT_FIELD(b, c, PAR, FAULT_SS)
-
-#define GET_NOFAULT_SS(b, c)    GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_SS)
-#define GET_NOFAULT_MT(b, c)    GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_MT)
-#define GET_NOFAULT_SH(b, c)    GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_SH)
-#define GET_NOFAULT_NS(b, c)    GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_NS)
-#define GET_NOFAULT_NOS(b, c)   GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_NOS)
-#define GET_NPFAULT_PA(b, c)    GET_CONTEXT_FIELD(b, c, PAR, PAR_NPFAULT_PA)
-
-
-/* PRRR */
-#define GET_MTC0(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, MTC0)
-#define GET_MTC1(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, MTC1)
-#define GET_MTC2(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, MTC2)
-#define GET_MTC3(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, MTC3)
-#define GET_MTC4(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, MTC4)
-#define GET_MTC5(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, MTC5)
-#define GET_MTC6(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, MTC6)
-#define GET_MTC7(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, MTC7)
-#define GET_SHDSH0(b, c)        GET_CONTEXT_FIELD(b, c, PRRR, SHDSH0)
-#define GET_SHDSH1(b, c)        GET_CONTEXT_FIELD(b, c, PRRR, SHDSH1)
-#define GET_SHNMSH0(b, c)       GET_CONTEXT_FIELD(b, c, PRRR, SHNMSH0)
-#define GET_SHNMSH1(b, c)       GET_CONTEXT_FIELD(b, c, PRRR, SHNMSH1)
-#define GET_NOS0(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS0)
-#define GET_NOS1(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS1)
-#define GET_NOS2(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS2)
-#define GET_NOS3(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS3)
-#define GET_NOS4(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS4)
-#define GET_NOS5(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS5)
-#define GET_NOS6(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS6)
-#define GET_NOS7(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS7)
-#define PRRR_NOS(prrr, n)        ((prrr) & (1 << ((n) + 24)) ? 1 : 0)
-#define PRRR_MT(prrr, n)         ((((prrr) & (3 << ((n) * 2))) >> ((n) * 2)))
-
-
-/* RESUME */
-#define GET_TNR(b, c)           GET_CONTEXT_FIELD(b, c, RESUME, TNR)
-
-
-/* SCTLR */
-#define GET_M(b, c)             GET_CONTEXT_FIELD(b, c, SCTLR, M)
-#define GET_TRE(b, c)           GET_CONTEXT_FIELD(b, c, SCTLR, TRE)
-#define GET_AFE(b, c)           GET_CONTEXT_FIELD(b, c, SCTLR, AFE)
-#define GET_HAF(b, c)           GET_CONTEXT_FIELD(b, c, SCTLR, HAF)
-#define GET_BE(b, c)            GET_CONTEXT_FIELD(b, c, SCTLR, BE)
-#define GET_AFFD(b, c)          GET_CONTEXT_FIELD(b, c, SCTLR, AFFD)
-
-
-/* TLBLKCR */
-#define GET_LKE(b, c)           GET_CONTEXT_FIELD(b, c, TLBLKCR, LKE)
-#define GET_TLBLCKR_TLBIALLCFG(b, c) \
-                        GET_CONTEXT_FIELD(b, c, TLBLKCR, TLBLCKR_TLBIALLCFG)
-#define GET_TLBIASIDCFG(b, c)   GET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIASIDCFG)
-#define GET_TLBIVAACFG(b, c)    GET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIVAACFG)
-#define GET_FLOOR(b, c)         GET_CONTEXT_FIELD(b, c, TLBLKCR, FLOOR)
-#define GET_VICTIM(b, c)        GET_CONTEXT_FIELD(b, c, TLBLKCR, VICTIM)
-
-
-/* TTBCR */
-#define GET_N(b, c)             GET_CONTEXT_FIELD(b, c, TTBCR, N)
-#define GET_PD0(b, c)           GET_CONTEXT_FIELD(b, c, TTBCR, PD0)
-#define GET_PD1(b, c)           GET_CONTEXT_FIELD(b, c, TTBCR, PD1)
-
-
-/* TTBR0 */
-#define GET_TTBR0_IRGNH(b, c)   GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNH)
-#define GET_TTBR0_SH(b, c)      GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_SH)
-#define GET_TTBR0_ORGN(b, c)    GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_ORGN)
-#define GET_TTBR0_NOS(b, c)     GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_NOS)
-#define GET_TTBR0_IRGNL(b, c)   GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNL)
-#define GET_TTBR0_PA(b, c)      GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_PA)
-
-
-/* TTBR1 */
-#define GET_TTBR1_IRGNH(b, c)   GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNH)
-#define GET_TTBR1_SH(b, c)      GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_SH)
-#define GET_TTBR1_ORGN(b, c)    GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_ORGN)
-#define GET_TTBR1_NOS(b, c)     GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_NOS)
-#define GET_TTBR1_IRGNL(b, c)   GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNL)
-#define GET_TTBR1_PA(b, c)      GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_PA)
-
-
-/* V2PSR */
-#define GET_HIT(b, c)           GET_CONTEXT_FIELD(b, c, V2PSR, HIT)
-#define GET_INDEX(b, c)         GET_CONTEXT_FIELD(b, c, V2PSR, INDEX)
-
-
-/* Global Registers */
-#define M2VCBR_N        (0xFF000)
-#define CBACR_N         (0xFF800)
-#define TLBRSW          (0xFFE00)
-#define TLBTR0          (0xFFE80)
-#define TLBTR1          (0xFFE84)
-#define TLBTR2          (0xFFE88)
-#define TESTBUSCR       (0xFFE8C)
-#define GLOBAL_TLBIALL  (0xFFF00)
-#define TLBIVMID        (0xFFF04)
-#define CR              (0xFFF80)
-#define EAR             (0xFFF84)
-#define ESR             (0xFFF88)
-#define ESRRESTORE      (0xFFF8C)
-#define ESYNR0          (0xFFF90)
-#define ESYNR1          (0xFFF94)
-#define REV             (0xFFFF4)
-#define IDR             (0xFFFF8)
-#define RPU_ACR         (0xFFFFC)
-
-
-/* Context Bank Registers */
-#define SCTLR           (0x000)
-#define ACTLR           (0x004)
-#define CONTEXTIDR      (0x008)
-#define TTBR0           (0x010)
-#define TTBR1           (0x014)
-#define TTBCR           (0x018)
-#define PAR             (0x01C)
-#define FSR             (0x020)
-#define FSRRESTORE      (0x024)
-#define FAR             (0x028)
-#define FSYNR0          (0x02C)
-#define FSYNR1          (0x030)
-#define PRRR            (0x034)
-#define NMRR            (0x038)
-#define TLBLCKR         (0x03C)
-#define V2PSR           (0x040)
-#define TLBFLPTER       (0x044)
-#define TLBSLPTER       (0x048)
-#define BFBCR           (0x04C)
-#define CTX_TLBIALL     (0x800)
-#define TLBIASID        (0x804)
-#define TLBIVA          (0x808)
-#define TLBIVAA         (0x80C)
-#define V2PPR           (0x810)
-#define V2PPW           (0x814)
-#define V2PUR           (0x818)
-#define V2PUW           (0x81C)
-#define RESUME          (0x820)
-
-
-/* Global Register Fields */
-/* CBACRn */
-#define RWVMID        (RWVMID_MASK       << RWVMID_SHIFT)
-#define RWE           (RWE_MASK          << RWE_SHIFT)
-#define RWGE          (RWGE_MASK         << RWGE_SHIFT)
-#define CBVMID        (CBVMID_MASK       << CBVMID_SHIFT)
-#define IRPTNDX       (IRPTNDX_MASK      << IRPTNDX_SHIFT)
-
-
-/* CR */
-#define RPUE          (RPUE_MASK          << RPUE_SHIFT)
-#define RPUERE        (RPUERE_MASK        << RPUERE_SHIFT)
-#define RPUEIE        (RPUEIE_MASK        << RPUEIE_SHIFT)
-#define DCDEE         (DCDEE_MASK         << DCDEE_SHIFT)
-#define CLIENTPD      (CLIENTPD_MASK      << CLIENTPD_SHIFT)
-#define STALLD        (STALLD_MASK        << STALLD_SHIFT)
-#define TLBLKCRWE     (TLBLKCRWE_MASK     << TLBLKCRWE_SHIFT)
-#define CR_TLBIALLCFG (CR_TLBIALLCFG_MASK << CR_TLBIALLCFG_SHIFT)
-#define TLBIVMIDCFG   (TLBIVMIDCFG_MASK   << TLBIVMIDCFG_SHIFT)
-#define CR_HUME       (CR_HUME_MASK       << CR_HUME_SHIFT)
-
-
-/* ESR */
-#define CFG           (CFG_MASK          << CFG_SHIFT)
-#define BYPASS        (BYPASS_MASK       << BYPASS_SHIFT)
-#define ESR_MULTI     (ESR_MULTI_MASK    << ESR_MULTI_SHIFT)
-
-
-/* ESYNR0 */
-#define ESYNR0_AMID   (ESYNR0_AMID_MASK  << ESYNR0_AMID_SHIFT)
-#define ESYNR0_APID   (ESYNR0_APID_MASK  << ESYNR0_APID_SHIFT)
-#define ESYNR0_ABID   (ESYNR0_ABID_MASK  << ESYNR0_ABID_SHIFT)
-#define ESYNR0_AVMID  (ESYNR0_AVMID_MASK << ESYNR0_AVMID_SHIFT)
-#define ESYNR0_ATID   (ESYNR0_ATID_MASK  << ESYNR0_ATID_SHIFT)
-
-
-/* ESYNR1 */
-#define ESYNR1_AMEMTYPE      (ESYNR1_AMEMTYPE_MASK    << ESYNR1_AMEMTYPE_SHIFT)
-#define ESYNR1_ASHARED       (ESYNR1_ASHARED_MASK     << ESYNR1_ASHARED_SHIFT)
-#define ESYNR1_AINNERSHARED  (ESYNR1_AINNERSHARED_MASK<< \
-                                                ESYNR1_AINNERSHARED_SHIFT)
-#define ESYNR1_APRIV         (ESYNR1_APRIV_MASK       << ESYNR1_APRIV_SHIFT)
-#define ESYNR1_APROTNS       (ESYNR1_APROTNS_MASK     << ESYNR1_APROTNS_SHIFT)
-#define ESYNR1_AINST         (ESYNR1_AINST_MASK       << ESYNR1_AINST_SHIFT)
-#define ESYNR1_AWRITE        (ESYNR1_AWRITE_MASK      << ESYNR1_AWRITE_SHIFT)
-#define ESYNR1_ABURST        (ESYNR1_ABURST_MASK      << ESYNR1_ABURST_SHIFT)
-#define ESYNR1_ALEN          (ESYNR1_ALEN_MASK        << ESYNR1_ALEN_SHIFT)
-#define ESYNR1_ASIZE         (ESYNR1_ASIZE_MASK       << ESYNR1_ASIZE_SHIFT)
-#define ESYNR1_ALOCK         (ESYNR1_ALOCK_MASK       << ESYNR1_ALOCK_SHIFT)
-#define ESYNR1_AOOO          (ESYNR1_AOOO_MASK        << ESYNR1_AOOO_SHIFT)
-#define ESYNR1_AFULL         (ESYNR1_AFULL_MASK       << ESYNR1_AFULL_SHIFT)
-#define ESYNR1_AC            (ESYNR1_AC_MASK          << ESYNR1_AC_SHIFT)
-#define ESYNR1_DCD           (ESYNR1_DCD_MASK         << ESYNR1_DCD_SHIFT)
-
-
-/* IDR */
-#define NM2VCBMT      (NM2VCBMT_MASK     << NM2VCBMT_SHIFT)
-#define HTW           (HTW_MASK          << HTW_SHIFT)
-#define HUM           (HUM_MASK          << HUM_SHIFT)
-#define TLBSIZE       (TLBSIZE_MASK      << TLBSIZE_SHIFT)
-#define NCB           (NCB_MASK          << NCB_SHIFT)
-#define NIRPT         (NIRPT_MASK        << NIRPT_SHIFT)
-
-
-/* M2VCBRn */
-#define VMID          (VMID_MASK         << VMID_SHIFT)
-#define CBNDX         (CBNDX_MASK        << CBNDX_SHIFT)
-#define BYPASSD       (BYPASSD_MASK      << BYPASSD_SHIFT)
-#define BPRCOSH       (BPRCOSH_MASK      << BPRCOSH_SHIFT)
-#define BPRCISH       (BPRCISH_MASK      << BPRCISH_SHIFT)
-#define BPRCNSH       (BPRCNSH_MASK      << BPRCNSH_SHIFT)
-#define BPSHCFG       (BPSHCFG_MASK      << BPSHCFG_SHIFT)
-#define NSCFG         (NSCFG_MASK        << NSCFG_SHIFT)
-#define BPMTCFG       (BPMTCFG_MASK      << BPMTCFG_SHIFT)
-#define BPMEMTYPE     (BPMEMTYPE_MASK    << BPMEMTYPE_SHIFT)
-
-
-/* REV */
-#define IDR_MINOR     (MINOR_MASK        << MINOR_SHIFT)
-#define IDR_MAJOR     (MAJOR_MASK        << MAJOR_SHIFT)
-
-
-/* TESTBUSCR */
-#define TBE           (TBE_MASK          << TBE_SHIFT)
-#define SPDMBE        (SPDMBE_MASK       << SPDMBE_SHIFT)
-#define WGSEL         (WGSEL_MASK        << WGSEL_SHIFT)
-#define TBLSEL        (TBLSEL_MASK       << TBLSEL_SHIFT)
-#define TBHSEL        (TBHSEL_MASK       << TBHSEL_SHIFT)
-#define SPDM0SEL      (SPDM0SEL_MASK     << SPDM0SEL_SHIFT)
-#define SPDM1SEL      (SPDM1SEL_MASK     << SPDM1SEL_SHIFT)
-#define SPDM2SEL      (SPDM2SEL_MASK     << SPDM2SEL_SHIFT)
-#define SPDM3SEL      (SPDM3SEL_MASK     << SPDM3SEL_SHIFT)
-
-
-/* TLBIVMID */
-#define TLBIVMID_VMID (TLBIVMID_VMID_MASK << TLBIVMID_VMID_SHIFT)
-
-
-/* TLBRSW */
-#define TLBRSW_INDEX  (TLBRSW_INDEX_MASK << TLBRSW_INDEX_SHIFT)
-#define TLBBFBS       (TLBBFBS_MASK      << TLBBFBS_SHIFT)
-
-
-/* TLBTR0 */
-#define PR            (PR_MASK           << PR_SHIFT)
-#define PW            (PW_MASK           << PW_SHIFT)
-#define UR            (UR_MASK           << UR_SHIFT)
-#define UW            (UW_MASK           << UW_SHIFT)
-#define XN            (XN_MASK           << XN_SHIFT)
-#define NSDESC        (NSDESC_MASK       << NSDESC_SHIFT)
-#define ISH           (ISH_MASK          << ISH_SHIFT)
-#define SH            (SH_MASK           << SH_SHIFT)
-#define MT            (MT_MASK           << MT_SHIFT)
-#define DPSIZR        (DPSIZR_MASK       << DPSIZR_SHIFT)
-#define DPSIZC        (DPSIZC_MASK       << DPSIZC_SHIFT)
-
-
-/* TLBTR1 */
-#define TLBTR1_VMID   (TLBTR1_VMID_MASK  << TLBTR1_VMID_SHIFT)
-#define TLBTR1_PA     (TLBTR1_PA_MASK    << TLBTR1_PA_SHIFT)
-
-
-/* TLBTR2 */
-#define TLBTR2_ASID   (TLBTR2_ASID_MASK  << TLBTR2_ASID_SHIFT)
-#define TLBTR2_V      (TLBTR2_V_MASK     << TLBTR2_V_SHIFT)
-#define TLBTR2_NSTID  (TLBTR2_NSTID_MASK << TLBTR2_NSTID_SHIFT)
-#define TLBTR2_NV     (TLBTR2_NV_MASK    << TLBTR2_NV_SHIFT)
-#define TLBTR2_VA     (TLBTR2_VA_MASK    << TLBTR2_VA_SHIFT)
-
-
-/* Context Register Fields */
-/* ACTLR */
-#define CFERE              (CFERE_MASK              << CFERE_SHIFT)
-#define CFEIE              (CFEIE_MASK              << CFEIE_SHIFT)
-#define PTSHCFG            (PTSHCFG_MASK            << PTSHCFG_SHIFT)
-#define RCOSH              (RCOSH_MASK              << RCOSH_SHIFT)
-#define RCISH              (RCISH_MASK              << RCISH_SHIFT)
-#define RCNSH              (RCNSH_MASK              << RCNSH_SHIFT)
-#define PRIVCFG            (PRIVCFG_MASK            << PRIVCFG_SHIFT)
-#define DNA                (DNA_MASK                << DNA_SHIFT)
-#define DNLV2PA            (DNLV2PA_MASK            << DNLV2PA_SHIFT)
-#define TLBMCFG            (TLBMCFG_MASK            << TLBMCFG_SHIFT)
-#define CFCFG              (CFCFG_MASK              << CFCFG_SHIFT)
-#define TIPCF              (TIPCF_MASK              << TIPCF_SHIFT)
-#define V2PCFG             (V2PCFG_MASK             << V2PCFG_SHIFT)
-#define HUME               (HUME_MASK               << HUME_SHIFT)
-#define PTMTCFG            (PTMTCFG_MASK            << PTMTCFG_SHIFT)
-#define PTMEMTYPE          (PTMEMTYPE_MASK          << PTMEMTYPE_SHIFT)
-
-
-/* BFBCR */
-#define BFBDFE             (BFBDFE_MASK             << BFBDFE_SHIFT)
-#define BFBSFE             (BFBSFE_MASK             << BFBSFE_SHIFT)
-#define SFVS               (SFVS_MASK               << SFVS_SHIFT)
-#define FLVIC              (FLVIC_MASK              << FLVIC_SHIFT)
-#define SLVIC              (SLVIC_MASK              << SLVIC_SHIFT)
-
-
-/* CONTEXTIDR */
-#define CONTEXTIDR_ASID    (CONTEXTIDR_ASID_MASK    << CONTEXTIDR_ASID_SHIFT)
-#define PROCID             (PROCID_MASK             << PROCID_SHIFT)
-
-
-/* FSR */
-#define TF                 (TF_MASK                 << TF_SHIFT)
-#define AFF                (AFF_MASK                << AFF_SHIFT)
-#define APF                (APF_MASK                << APF_SHIFT)
-#define TLBMF              (TLBMF_MASK              << TLBMF_SHIFT)
-#define HTWDEEF            (HTWDEEF_MASK            << HTWDEEF_SHIFT)
-#define HTWSEEF            (HTWSEEF_MASK            << HTWSEEF_SHIFT)
-#define MHF                (MHF_MASK                << MHF_SHIFT)
-#define SL                 (SL_MASK                 << SL_SHIFT)
-#define SS                 (SS_MASK                 << SS_SHIFT)
-#define MULTI              (MULTI_MASK              << MULTI_SHIFT)
-
-
-/* FSYNR0 */
-#define AMID               (AMID_MASK               << AMID_SHIFT)
-#define APID               (APID_MASK               << APID_SHIFT)
-#define ABID               (ABID_MASK               << ABID_SHIFT)
-#define ATID               (ATID_MASK               << ATID_SHIFT)
-
-
-/* FSYNR1 */
-#define AMEMTYPE           (AMEMTYPE_MASK           << AMEMTYPE_SHIFT)
-#define ASHARED            (ASHARED_MASK            << ASHARED_SHIFT)
-#define AINNERSHARED       (AINNERSHARED_MASK       << AINNERSHARED_SHIFT)
-#define APRIV              (APRIV_MASK              << APRIV_SHIFT)
-#define APROTNS            (APROTNS_MASK            << APROTNS_SHIFT)
-#define AINST              (AINST_MASK              << AINST_SHIFT)
-#define AWRITE             (AWRITE_MASK             << AWRITE_SHIFT)
-#define ABURST             (ABURST_MASK             << ABURST_SHIFT)
-#define ALEN               (ALEN_MASK               << ALEN_SHIFT)
-#define FSYNR1_ASIZE       (FSYNR1_ASIZE_MASK       << FSYNR1_ASIZE_SHIFT)
-#define ALOCK              (ALOCK_MASK              << ALOCK_SHIFT)
-#define AFULL              (AFULL_MASK              << AFULL_SHIFT)
-
-
-/* NMRR */
-#define ICPC0              (ICPC0_MASK              << ICPC0_SHIFT)
-#define ICPC1              (ICPC1_MASK              << ICPC1_SHIFT)
-#define ICPC2              (ICPC2_MASK              << ICPC2_SHIFT)
-#define ICPC3              (ICPC3_MASK              << ICPC3_SHIFT)
-#define ICPC4              (ICPC4_MASK              << ICPC4_SHIFT)
-#define ICPC5              (ICPC5_MASK              << ICPC5_SHIFT)
-#define ICPC6              (ICPC6_MASK              << ICPC6_SHIFT)
-#define ICPC7              (ICPC7_MASK              << ICPC7_SHIFT)
-#define OCPC0              (OCPC0_MASK              << OCPC0_SHIFT)
-#define OCPC1              (OCPC1_MASK              << OCPC1_SHIFT)
-#define OCPC2              (OCPC2_MASK              << OCPC2_SHIFT)
-#define OCPC3              (OCPC3_MASK              << OCPC3_SHIFT)
-#define OCPC4              (OCPC4_MASK              << OCPC4_SHIFT)
-#define OCPC5              (OCPC5_MASK              << OCPC5_SHIFT)
-#define OCPC6              (OCPC6_MASK              << OCPC6_SHIFT)
-#define OCPC7              (OCPC7_MASK              << OCPC7_SHIFT)
-
-
-/* PAR */
-#define FAULT              (FAULT_MASK              << FAULT_SHIFT)
-/* If a fault is present, these are the
-same as the fault fields in the FAR */
-#define FAULT_TF           (FAULT_TF_MASK           << FAULT_TF_SHIFT)
-#define FAULT_AFF          (FAULT_AFF_MASK          << FAULT_AFF_SHIFT)
-#define FAULT_APF          (FAULT_APF_MASK          << FAULT_APF_SHIFT)
-#define FAULT_TLBMF        (FAULT_TLBMF_MASK        << FAULT_TLBMF_SHIFT)
-#define FAULT_HTWDEEF      (FAULT_HTWDEEF_MASK      << FAULT_HTWDEEF_SHIFT)
-#define FAULT_HTWSEEF      (FAULT_HTWSEEF_MASK      << FAULT_HTWSEEF_SHIFT)
-#define FAULT_MHF          (FAULT_MHF_MASK          << FAULT_MHF_SHIFT)
-#define FAULT_SL           (FAULT_SL_MASK           << FAULT_SL_SHIFT)
-#define FAULT_SS           (FAULT_SS_MASK           << FAULT_SS_SHIFT)
-
-/* If NO fault is present, the following fields are in effect */
-/* (FAULT remains as before) */
-#define PAR_NOFAULT_SS     (PAR_NOFAULT_SS_MASK     << PAR_NOFAULT_SS_SHIFT)
-#define PAR_NOFAULT_MT     (PAR_NOFAULT_MT_MASK     << PAR_NOFAULT_MT_SHIFT)
-#define PAR_NOFAULT_SH     (PAR_NOFAULT_SH_MASK     << PAR_NOFAULT_SH_SHIFT)
-#define PAR_NOFAULT_NS     (PAR_NOFAULT_NS_MASK     << PAR_NOFAULT_NS_SHIFT)
-#define PAR_NOFAULT_NOS    (PAR_NOFAULT_NOS_MASK    << PAR_NOFAULT_NOS_SHIFT)
-#define PAR_NPFAULT_PA     (PAR_NPFAULT_PA_MASK     << PAR_NPFAULT_PA_SHIFT)
-
-
-/* PRRR */
-#define MTC0               (MTC0_MASK               << MTC0_SHIFT)
-#define MTC1               (MTC1_MASK               << MTC1_SHIFT)
-#define MTC2               (MTC2_MASK               << MTC2_SHIFT)
-#define MTC3               (MTC3_MASK               << MTC3_SHIFT)
-#define MTC4               (MTC4_MASK               << MTC4_SHIFT)
-#define MTC5               (MTC5_MASK               << MTC5_SHIFT)
-#define MTC6               (MTC6_MASK               << MTC6_SHIFT)
-#define MTC7               (MTC7_MASK               << MTC7_SHIFT)
-#define SHDSH0             (SHDSH0_MASK             << SHDSH0_SHIFT)
-#define SHDSH1             (SHDSH1_MASK             << SHDSH1_SHIFT)
-#define SHNMSH0            (SHNMSH0_MASK            << SHNMSH0_SHIFT)
-#define SHNMSH1            (SHNMSH1_MASK            << SHNMSH1_SHIFT)
-#define NOS0               (NOS0_MASK               << NOS0_SHIFT)
-#define NOS1               (NOS1_MASK               << NOS1_SHIFT)
-#define NOS2               (NOS2_MASK               << NOS2_SHIFT)
-#define NOS3               (NOS3_MASK               << NOS3_SHIFT)
-#define NOS4               (NOS4_MASK               << NOS4_SHIFT)
-#define NOS5               (NOS5_MASK               << NOS5_SHIFT)
-#define NOS6               (NOS6_MASK               << NOS6_SHIFT)
-#define NOS7               (NOS7_MASK               << NOS7_SHIFT)
-
-
-/* RESUME */
-#define TNR                (TNR_MASK                << TNR_SHIFT)
-
-
-/* SCTLR */
-#define M                  (M_MASK                  << M_SHIFT)
-#define TRE                (TRE_MASK                << TRE_SHIFT)
-#define AFE                (AFE_MASK                << AFE_SHIFT)
-#define HAF                (HAF_MASK                << HAF_SHIFT)
-#define BE                 (BE_MASK                 << BE_SHIFT)
-#define AFFD               (AFFD_MASK               << AFFD_SHIFT)
-
-
-/* TLBIASID */
-#define TLBIASID_ASID      (TLBIASID_ASID_MASK      << TLBIASID_ASID_SHIFT)
-
-
-/* TLBIVA */
-#define TLBIVA_ASID        (TLBIVA_ASID_MASK        << TLBIVA_ASID_SHIFT)
-#define TLBIVA_VA          (TLBIVA_VA_MASK          << TLBIVA_VA_SHIFT)
-
-
-/* TLBIVAA */
-#define TLBIVAA_VA         (TLBIVAA_VA_MASK         << TLBIVAA_VA_SHIFT)
-
-
-/* TLBLCKR */
-#define LKE                (LKE_MASK                << LKE_SHIFT)
-#define TLBLCKR_TLBIALLCFG (TLBLCKR_TLBIALLCFG_MASK<<TLBLCKR_TLBIALLCFG_SHIFT)
-#define TLBIASIDCFG        (TLBIASIDCFG_MASK        << TLBIASIDCFG_SHIFT)
-#define TLBIVAACFG         (TLBIVAACFG_MASK         << TLBIVAACFG_SHIFT)
-#define FLOOR              (FLOOR_MASK              << FLOOR_SHIFT)
-#define VICTIM             (VICTIM_MASK             << VICTIM_SHIFT)
-
-
-/* TTBCR */
-#define N                  (N_MASK                  << N_SHIFT)
-#define PD0                (PD0_MASK                << PD0_SHIFT)
-#define PD1                (PD1_MASK                << PD1_SHIFT)
-
-
-/* TTBR0 */
-#define TTBR0_IRGNH        (TTBR0_IRGNH_MASK        << TTBR0_IRGNH_SHIFT)
-#define TTBR0_SH           (TTBR0_SH_MASK           << TTBR0_SH_SHIFT)
-#define TTBR0_ORGN         (TTBR0_ORGN_MASK         << TTBR0_ORGN_SHIFT)
-#define TTBR0_NOS          (TTBR0_NOS_MASK          << TTBR0_NOS_SHIFT)
-#define TTBR0_IRGNL        (TTBR0_IRGNL_MASK        << TTBR0_IRGNL_SHIFT)
-#define TTBR0_PA           (TTBR0_PA_MASK           << TTBR0_PA_SHIFT)
-
-
-/* TTBR1 */
-#define TTBR1_IRGNH        (TTBR1_IRGNH_MASK        << TTBR1_IRGNH_SHIFT)
-#define TTBR1_SH           (TTBR1_SH_MASK           << TTBR1_SH_SHIFT)
-#define TTBR1_ORGN         (TTBR1_ORGN_MASK         << TTBR1_ORGN_SHIFT)
-#define TTBR1_NOS          (TTBR1_NOS_MASK          << TTBR1_NOS_SHIFT)
-#define TTBR1_IRGNL        (TTBR1_IRGNL_MASK        << TTBR1_IRGNL_SHIFT)
-#define TTBR1_PA           (TTBR1_PA_MASK           << TTBR1_PA_SHIFT)
-
-
-/* V2PSR */
-#define HIT                (HIT_MASK                << HIT_SHIFT)
-#define INDEX              (INDEX_MASK              << INDEX_SHIFT)
-
-
-/* V2Pxx */
-#define V2Pxx_INDEX        (V2Pxx_INDEX_MASK        << V2Pxx_INDEX_SHIFT)
-#define V2Pxx_VA           (V2Pxx_VA_MASK           << V2Pxx_VA_SHIFT)
-
-
-/* Global Register Masks */
-/* CBACRn */
-#define RWVMID_MASK               0x1F
-#define RWE_MASK                  0x01
-#define RWGE_MASK                 0x01
-#define CBVMID_MASK               0x1F
-#define IRPTNDX_MASK              0xFF
-
-
-/* CR */
-#define RPUE_MASK                 0x01
-#define RPUERE_MASK               0x01
-#define RPUEIE_MASK               0x01
-#define DCDEE_MASK                0x01
-#define CLIENTPD_MASK             0x01
-#define STALLD_MASK               0x01
-#define TLBLKCRWE_MASK            0x01
-#define CR_TLBIALLCFG_MASK        0x01
-#define TLBIVMIDCFG_MASK          0x01
-#define CR_HUME_MASK              0x01
-
-
-/* ESR */
-#define CFG_MASK                  0x01
-#define BYPASS_MASK               0x01
-#define ESR_MULTI_MASK            0x01
-
-
-/* ESYNR0 */
-#define ESYNR0_AMID_MASK          0xFF
-#define ESYNR0_APID_MASK          0x1F
-#define ESYNR0_ABID_MASK          0x07
-#define ESYNR0_AVMID_MASK         0x1F
-#define ESYNR0_ATID_MASK          0xFF
-
-
-/* ESYNR1 */
-#define ESYNR1_AMEMTYPE_MASK             0x07
-#define ESYNR1_ASHARED_MASK              0x01
-#define ESYNR1_AINNERSHARED_MASK         0x01
-#define ESYNR1_APRIV_MASK                0x01
-#define ESYNR1_APROTNS_MASK              0x01
-#define ESYNR1_AINST_MASK                0x01
-#define ESYNR1_AWRITE_MASK               0x01
-#define ESYNR1_ABURST_MASK               0x01
-#define ESYNR1_ALEN_MASK                 0x0F
-#define ESYNR1_ASIZE_MASK                0x01
-#define ESYNR1_ALOCK_MASK                0x03
-#define ESYNR1_AOOO_MASK                 0x01
-#define ESYNR1_AFULL_MASK                0x01
-#define ESYNR1_AC_MASK                   0x01
-#define ESYNR1_DCD_MASK                  0x01
-
-
-/* IDR */
-#define NM2VCBMT_MASK             0x1FF
-#define HTW_MASK                  0x01
-#define HUM_MASK                  0x01
-#define TLBSIZE_MASK              0x0F
-#define NCB_MASK                  0xFF
-#define NIRPT_MASK                0xFF
-
-
-/* M2VCBRn */
-#define VMID_MASK                 0x1F
-#define CBNDX_MASK                0xFF
-#define BYPASSD_MASK              0x01
-#define BPRCOSH_MASK              0x01
-#define BPRCISH_MASK              0x01
-#define BPRCNSH_MASK              0x01
-#define BPSHCFG_MASK              0x03
-#define NSCFG_MASK                0x03
-#define BPMTCFG_MASK              0x01
-#define BPMEMTYPE_MASK            0x07
-
-
-/* REV */
-#define MINOR_MASK                0x0F
-#define MAJOR_MASK                0x0F
-
-
-/* TESTBUSCR */
-#define TBE_MASK                  0x01
-#define SPDMBE_MASK               0x01
-#define WGSEL_MASK                0x03
-#define TBLSEL_MASK               0x03
-#define TBHSEL_MASK               0x03
-#define SPDM0SEL_MASK             0x0F
-#define SPDM1SEL_MASK             0x0F
-#define SPDM2SEL_MASK             0x0F
-#define SPDM3SEL_MASK             0x0F
-
-
-/* TLBIMID */
-#define TLBIVMID_VMID_MASK        0x1F
-
-
-/* TLBRSW */
-#define TLBRSW_INDEX_MASK         0xFF
-#define TLBBFBS_MASK              0x03
-
-
-/* TLBTR0 */
-#define PR_MASK                   0x01
-#define PW_MASK                   0x01
-#define UR_MASK                   0x01
-#define UW_MASK                   0x01
-#define XN_MASK                   0x01
-#define NSDESC_MASK               0x01
-#define ISH_MASK                  0x01
-#define SH_MASK                   0x01
-#define MT_MASK                   0x07
-#define DPSIZR_MASK               0x07
-#define DPSIZC_MASK               0x07
-
-
-/* TLBTR1 */
-#define TLBTR1_VMID_MASK          0x1F
-#define TLBTR1_PA_MASK            0x000FFFFF
-
-
-/* TLBTR2 */
-#define TLBTR2_ASID_MASK          0xFF
-#define TLBTR2_V_MASK             0x01
-#define TLBTR2_NSTID_MASK         0x01
-#define TLBTR2_NV_MASK            0x01
-#define TLBTR2_VA_MASK            0x000FFFFF
-
-
-/* Global Register Shifts */
-/* CBACRn */
-#define RWVMID_SHIFT             0
-#define RWE_SHIFT                8
-#define RWGE_SHIFT               9
-#define CBVMID_SHIFT             16
-#define IRPTNDX_SHIFT            24
-
-
-/* CR */
-#define RPUE_SHIFT               0
-#define RPUERE_SHIFT             1
-#define RPUEIE_SHIFT             2
-#define DCDEE_SHIFT              3
-#define CLIENTPD_SHIFT           4
-#define STALLD_SHIFT             5
-#define TLBLKCRWE_SHIFT          6
-#define CR_TLBIALLCFG_SHIFT      7
-#define TLBIVMIDCFG_SHIFT        8
-#define CR_HUME_SHIFT            9
-
-
-/* ESR */
-#define CFG_SHIFT                0
-#define BYPASS_SHIFT             1
-#define ESR_MULTI_SHIFT          31
-
-
-/* ESYNR0 */
-#define ESYNR0_AMID_SHIFT        0
-#define ESYNR0_APID_SHIFT        8
-#define ESYNR0_ABID_SHIFT        13
-#define ESYNR0_AVMID_SHIFT       16
-#define ESYNR0_ATID_SHIFT        24
-
-
-/* ESYNR1 */
-#define ESYNR1_AMEMTYPE_SHIFT           0
-#define ESYNR1_ASHARED_SHIFT            3
-#define ESYNR1_AINNERSHARED_SHIFT       4
-#define ESYNR1_APRIV_SHIFT              5
-#define ESYNR1_APROTNS_SHIFT            6
-#define ESYNR1_AINST_SHIFT              7
-#define ESYNR1_AWRITE_SHIFT             8
-#define ESYNR1_ABURST_SHIFT             10
-#define ESYNR1_ALEN_SHIFT               12
-#define ESYNR1_ASIZE_SHIFT              16
-#define ESYNR1_ALOCK_SHIFT              20
-#define ESYNR1_AOOO_SHIFT               22
-#define ESYNR1_AFULL_SHIFT              24
-#define ESYNR1_AC_SHIFT                 30
-#define ESYNR1_DCD_SHIFT                31
-
-
-/* IDR */
-#define NM2VCBMT_SHIFT           0
-#define HTW_SHIFT                9
-#define HUM_SHIFT                10
-#define TLBSIZE_SHIFT            12
-#define NCB_SHIFT                16
-#define NIRPT_SHIFT              24
-
-
-/* M2VCBRn */
-#define VMID_SHIFT               0
-#define CBNDX_SHIFT              8
-#define BYPASSD_SHIFT            16
-#define BPRCOSH_SHIFT            17
-#define BPRCISH_SHIFT            18
-#define BPRCNSH_SHIFT            19
-#define BPSHCFG_SHIFT            20
-#define NSCFG_SHIFT              22
-#define BPMTCFG_SHIFT            24
-#define BPMEMTYPE_SHIFT          25
-
-
-/* REV */
-#define MINOR_SHIFT              0
-#define MAJOR_SHIFT              4
-
-
-/* TESTBUSCR */
-#define TBE_SHIFT                0
-#define SPDMBE_SHIFT             1
-#define WGSEL_SHIFT              8
-#define TBLSEL_SHIFT             12
-#define TBHSEL_SHIFT             14
-#define SPDM0SEL_SHIFT           16
-#define SPDM1SEL_SHIFT           20
-#define SPDM2SEL_SHIFT           24
-#define SPDM3SEL_SHIFT           28
-
-
-/* TLBIMID */
-#define TLBIVMID_VMID_SHIFT      0
-
-
-/* TLBRSW */
-#define TLBRSW_INDEX_SHIFT       0
-#define TLBBFBS_SHIFT            8
-
-
-/* TLBTR0 */
-#define PR_SHIFT                 0
-#define PW_SHIFT                 1
-#define UR_SHIFT                 2
-#define UW_SHIFT                 3
-#define XN_SHIFT                 4
-#define NSDESC_SHIFT             6
-#define ISH_SHIFT                7
-#define SH_SHIFT                 8
-#define MT_SHIFT                 9
-#define DPSIZR_SHIFT             16
-#define DPSIZC_SHIFT             20
-
-
-/* TLBTR1 */
-#define TLBTR1_VMID_SHIFT        0
-#define TLBTR1_PA_SHIFT          12
-
-
-/* TLBTR2 */
-#define TLBTR2_ASID_SHIFT        0
-#define TLBTR2_V_SHIFT           8
-#define TLBTR2_NSTID_SHIFT       9
-#define TLBTR2_NV_SHIFT          10
-#define TLBTR2_VA_SHIFT          12
-
-
-/* Context Register Masks */
-/* ACTLR */
-#define CFERE_MASK                       0x01
-#define CFEIE_MASK                       0x01
-#define PTSHCFG_MASK                     0x03
-#define RCOSH_MASK                       0x01
-#define RCISH_MASK                       0x01
-#define RCNSH_MASK                       0x01
-#define PRIVCFG_MASK                     0x03
-#define DNA_MASK                         0x01
-#define DNLV2PA_MASK                     0x01
-#define TLBMCFG_MASK                     0x03
-#define CFCFG_MASK                       0x01
-#define TIPCF_MASK                       0x01
-#define V2PCFG_MASK                      0x03
-#define HUME_MASK                        0x01
-#define PTMTCFG_MASK                     0x01
-#define PTMEMTYPE_MASK                   0x07
-
-
-/* BFBCR */
-#define BFBDFE_MASK                      0x01
-#define BFBSFE_MASK                      0x01
-#define SFVS_MASK                        0x01
-#define FLVIC_MASK                       0x0F
-#define SLVIC_MASK                       0x0F
-
-
-/* CONTEXTIDR */
-#define CONTEXTIDR_ASID_MASK             0xFF
-#define PROCID_MASK                      0x00FFFFFF
-
-
-/* FSR */
-#define TF_MASK                          0x01
-#define AFF_MASK                         0x01
-#define APF_MASK                         0x01
-#define TLBMF_MASK                       0x01
-#define HTWDEEF_MASK                     0x01
-#define HTWSEEF_MASK                     0x01
-#define MHF_MASK                         0x01
-#define SL_MASK                          0x01
-#define SS_MASK                          0x01
-#define MULTI_MASK                       0x01
-
-
-/* FSYNR0 */
-#define AMID_MASK                        0xFF
-#define APID_MASK                        0x1F
-#define ABID_MASK                        0x07
-#define ATID_MASK                        0xFF
-
-
-/* FSYNR1 */
-#define AMEMTYPE_MASK                    0x07
-#define ASHARED_MASK                     0x01
-#define AINNERSHARED_MASK                0x01
-#define APRIV_MASK                       0x01
-#define APROTNS_MASK                     0x01
-#define AINST_MASK                       0x01
-#define AWRITE_MASK                      0x01
-#define ABURST_MASK                      0x01
-#define ALEN_MASK                        0x0F
-#define FSYNR1_ASIZE_MASK                0x07
-#define ALOCK_MASK                       0x03
-#define AFULL_MASK                       0x01
-
-
-/* NMRR */
-#define ICPC0_MASK                       0x03
-#define ICPC1_MASK                       0x03
-#define ICPC2_MASK                       0x03
-#define ICPC3_MASK                       0x03
-#define ICPC4_MASK                       0x03
-#define ICPC5_MASK                       0x03
-#define ICPC6_MASK                       0x03
-#define ICPC7_MASK                       0x03
-#define OCPC0_MASK                       0x03
-#define OCPC1_MASK                       0x03
-#define OCPC2_MASK                       0x03
-#define OCPC3_MASK                       0x03
-#define OCPC4_MASK                       0x03
-#define OCPC5_MASK                       0x03
-#define OCPC6_MASK                       0x03
-#define OCPC7_MASK                       0x03
-
-
-/* PAR */
-#define FAULT_MASK                       0x01
-/* If a fault is present, these are the
-same as the fault fields in the FAR */
-#define FAULT_TF_MASK                    0x01
-#define FAULT_AFF_MASK                   0x01
-#define FAULT_APF_MASK                   0x01
-#define FAULT_TLBMF_MASK                 0x01
-#define FAULT_HTWDEEF_MASK               0x01
-#define FAULT_HTWSEEF_MASK               0x01
-#define FAULT_MHF_MASK                   0x01
-#define FAULT_SL_MASK                    0x01
-#define FAULT_SS_MASK                    0x01
-
-/* If NO fault is present, the following
- * fields are in effect
- * (FAULT remains as before) */
-#define PAR_NOFAULT_SS_MASK              0x01
-#define PAR_NOFAULT_MT_MASK              0x07
-#define PAR_NOFAULT_SH_MASK              0x01
-#define PAR_NOFAULT_NS_MASK              0x01
-#define PAR_NOFAULT_NOS_MASK             0x01
-#define PAR_NPFAULT_PA_MASK              0x000FFFFF
-
-
-/* PRRR */
-#define MTC0_MASK                        0x03
-#define MTC1_MASK                        0x03
-#define MTC2_MASK                        0x03
-#define MTC3_MASK                        0x03
-#define MTC4_MASK                        0x03
-#define MTC5_MASK                        0x03
-#define MTC6_MASK                        0x03
-#define MTC7_MASK                        0x03
-#define SHDSH0_MASK                      0x01
-#define SHDSH1_MASK                      0x01
-#define SHNMSH0_MASK                     0x01
-#define SHNMSH1_MASK                     0x01
-#define NOS0_MASK                        0x01
-#define NOS1_MASK                        0x01
-#define NOS2_MASK                        0x01
-#define NOS3_MASK                        0x01
-#define NOS4_MASK                        0x01
-#define NOS5_MASK                        0x01
-#define NOS6_MASK                        0x01
-#define NOS7_MASK                        0x01
-
-
-/* RESUME */
-#define TNR_MASK                         0x01
-
-
-/* SCTLR */
-#define M_MASK                           0x01
-#define TRE_MASK                         0x01
-#define AFE_MASK                         0x01
-#define HAF_MASK                         0x01
-#define BE_MASK                          0x01
-#define AFFD_MASK                        0x01
-
-
-/* TLBIASID */
-#define TLBIASID_ASID_MASK               0xFF
-
-
-/* TLBIVA */
-#define TLBIVA_ASID_MASK                 0xFF
-#define TLBIVA_VA_MASK                   0x000FFFFF
-
-
-/* TLBIVAA */
-#define TLBIVAA_VA_MASK                  0x000FFFFF
-
-
-/* TLBLCKR */
-#define LKE_MASK                         0x01
-#define TLBLCKR_TLBIALLCFG_MASK          0x01
-#define TLBIASIDCFG_MASK                 0x01
-#define TLBIVAACFG_MASK                  0x01
-#define FLOOR_MASK                       0xFF
-#define VICTIM_MASK                      0xFF
-
-
-/* TTBCR */
-#define N_MASK                           0x07
-#define PD0_MASK                         0x01
-#define PD1_MASK                         0x01
-
-
-/* TTBR0 */
-#define TTBR0_IRGNH_MASK                 0x01
-#define TTBR0_SH_MASK                    0x01
-#define TTBR0_ORGN_MASK                  0x03
-#define TTBR0_NOS_MASK                   0x01
-#define TTBR0_IRGNL_MASK                 0x01
-#define TTBR0_PA_MASK                    0x0003FFFF
-
-
-/* TTBR1 */
-#define TTBR1_IRGNH_MASK                 0x01
-#define TTBR1_SH_MASK                    0x01
-#define TTBR1_ORGN_MASK                  0x03
-#define TTBR1_NOS_MASK                   0x01
-#define TTBR1_IRGNL_MASK                 0x01
-#define TTBR1_PA_MASK                    0x0003FFFF
-
-
-/* V2PSR */
-#define HIT_MASK                         0x01
-#define INDEX_MASK                       0xFF
-
-
-/* V2Pxx */
-#define V2Pxx_INDEX_MASK                 0xFF
-#define V2Pxx_VA_MASK                    0x000FFFFF
-
-
-/* Context Register Shifts */
-/* ACTLR */
-#define CFERE_SHIFT                    0
-#define CFEIE_SHIFT                    1
-#define PTSHCFG_SHIFT                  2
-#define RCOSH_SHIFT                    4
-#define RCISH_SHIFT                    5
-#define RCNSH_SHIFT                    6
-#define PRIVCFG_SHIFT                  8
-#define DNA_SHIFT                      10
-#define DNLV2PA_SHIFT                  11
-#define TLBMCFG_SHIFT                  12
-#define CFCFG_SHIFT                    14
-#define TIPCF_SHIFT                    15
-#define V2PCFG_SHIFT                   16
-#define HUME_SHIFT                     18
-#define PTMTCFG_SHIFT                  20
-#define PTMEMTYPE_SHIFT                21
-
-
-/* BFBCR */
-#define BFBDFE_SHIFT                   0
-#define BFBSFE_SHIFT                   1
-#define SFVS_SHIFT                     2
-#define FLVIC_SHIFT                    4
-#define SLVIC_SHIFT                    8
-
-
-/* CONTEXTIDR */
-#define CONTEXTIDR_ASID_SHIFT          0
-#define PROCID_SHIFT                   8
-
-
-/* FSR */
-#define TF_SHIFT                       1
-#define AFF_SHIFT                      2
-#define APF_SHIFT                      3
-#define TLBMF_SHIFT                    4
-#define HTWDEEF_SHIFT                  5
-#define HTWSEEF_SHIFT                  6
-#define MHF_SHIFT                      7
-#define SL_SHIFT                       16
-#define SS_SHIFT                       30
-#define MULTI_SHIFT                    31
-
-
-/* FSYNR0 */
-#define AMID_SHIFT                     0
-#define APID_SHIFT                     8
-#define ABID_SHIFT                     13
-#define ATID_SHIFT                     24
-
-
-/* FSYNR1 */
-#define AMEMTYPE_SHIFT                 0
-#define ASHARED_SHIFT                  3
-#define AINNERSHARED_SHIFT             4
-#define APRIV_SHIFT                    5
-#define APROTNS_SHIFT                  6
-#define AINST_SHIFT                    7
-#define AWRITE_SHIFT                   8
-#define ABURST_SHIFT                   10
-#define ALEN_SHIFT                     12
-#define FSYNR1_ASIZE_SHIFT             16
-#define ALOCK_SHIFT                    20
-#define AFULL_SHIFT                    24
-
-
-/* NMRR */
-#define ICPC0_SHIFT                    0
-#define ICPC1_SHIFT                    2
-#define ICPC2_SHIFT                    4
-#define ICPC3_SHIFT                    6
-#define ICPC4_SHIFT                    8
-#define ICPC5_SHIFT                    10
-#define ICPC6_SHIFT                    12
-#define ICPC7_SHIFT                    14
-#define OCPC0_SHIFT                    16
-#define OCPC1_SHIFT                    18
-#define OCPC2_SHIFT                    20
-#define OCPC3_SHIFT                    22
-#define OCPC4_SHIFT                    24
-#define OCPC5_SHIFT                    26
-#define OCPC6_SHIFT                    28
-#define OCPC7_SHIFT                    30
-
-
-/* PAR */
-#define FAULT_SHIFT                    0
-/* If a fault is present, these are the
-same as the fault fields in the FAR */
-#define FAULT_TF_SHIFT                 1
-#define FAULT_AFF_SHIFT                2
-#define FAULT_APF_SHIFT                3
-#define FAULT_TLBMF_SHIFT              4
-#define FAULT_HTWDEEF_SHIFT            5
-#define FAULT_HTWSEEF_SHIFT            6
-#define FAULT_MHF_SHIFT                7
-#define FAULT_SL_SHIFT                 16
-#define FAULT_SS_SHIFT                 30
-
-/* If NO fault is present, the following
- * fields are in effect
- * (FAULT remains as before) */
-#define PAR_NOFAULT_SS_SHIFT           1
-#define PAR_NOFAULT_MT_SHIFT           4
-#define PAR_NOFAULT_SH_SHIFT           7
-#define PAR_NOFAULT_NS_SHIFT           9
-#define PAR_NOFAULT_NOS_SHIFT          10
-#define PAR_NPFAULT_PA_SHIFT           12
-
-
-/* PRRR */
-#define MTC0_SHIFT                     0
-#define MTC1_SHIFT                     2
-#define MTC2_SHIFT                     4
-#define MTC3_SHIFT                     6
-#define MTC4_SHIFT                     8
-#define MTC5_SHIFT                     10
-#define MTC6_SHIFT                     12
-#define MTC7_SHIFT                     14
-#define SHDSH0_SHIFT                   16
-#define SHDSH1_SHIFT                   17
-#define SHNMSH0_SHIFT                  18
-#define SHNMSH1_SHIFT                  19
-#define NOS0_SHIFT                     24
-#define NOS1_SHIFT                     25
-#define NOS2_SHIFT                     26
-#define NOS3_SHIFT                     27
-#define NOS4_SHIFT                     28
-#define NOS5_SHIFT                     29
-#define NOS6_SHIFT                     30
-#define NOS7_SHIFT                     31
-
-
-/* RESUME */
-#define TNR_SHIFT                      0
-
-
-/* SCTLR */
-#define M_SHIFT                        0
-#define TRE_SHIFT                      1
-#define AFE_SHIFT                      2
-#define HAF_SHIFT                      3
-#define BE_SHIFT                       4
-#define AFFD_SHIFT                     5
-
-
-/* TLBIASID */
-#define TLBIASID_ASID_SHIFT            0
-
-
-/* TLBIVA */
-#define TLBIVA_ASID_SHIFT              0
-#define TLBIVA_VA_SHIFT                12
-
-
-/* TLBIVAA */
-#define TLBIVAA_VA_SHIFT               12
-
-
-/* TLBLCKR */
-#define LKE_SHIFT                      0
-#define TLBLCKR_TLBIALLCFG_SHIFT       1
-#define TLBIASIDCFG_SHIFT              2
-#define TLBIVAACFG_SHIFT               3
-#define FLOOR_SHIFT                    8
-#define VICTIM_SHIFT                   8
-
-
-/* TTBCR */
-#define N_SHIFT                        3
-#define PD0_SHIFT                      4
-#define PD1_SHIFT                      5
-
-
-/* TTBR0 */
-#define TTBR0_IRGNH_SHIFT              0
-#define TTBR0_SH_SHIFT                 1
-#define TTBR0_ORGN_SHIFT               3
-#define TTBR0_NOS_SHIFT                5
-#define TTBR0_IRGNL_SHIFT              6
-#define TTBR0_PA_SHIFT                 14
-
-
-/* TTBR1 */
-#define TTBR1_IRGNH_SHIFT              0
-#define TTBR1_SH_SHIFT                 1
-#define TTBR1_ORGN_SHIFT               3
-#define TTBR1_NOS_SHIFT                5
-#define TTBR1_IRGNL_SHIFT              6
-#define TTBR1_PA_SHIFT                 14
-
-
-/* V2PSR */
-#define HIT_SHIFT                      0
-#define INDEX_SHIFT                    8
-
-
-/* V2Pxx */
-#define V2Pxx_INDEX_SHIFT              0
-#define V2Pxx_VA_SHIFT                 12
-
-#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
deleted file mode 100644
index 7bca8d7108d6..000000000000
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *
- * The MSM peripherals are spread all over across 768MB of physical
- * space, which makes just having a simple IO_ADDRESS macro to slide
- * them into the right virtual location rough.  Instead, we will
- * provide a master phys->virt mapping for peripherals here.
- *
- */
-
-#ifndef __ASM_ARCH_MSM_IOMAP_8960_H
-#define __ASM_ARCH_MSM_IOMAP_8960_H
-
-/* Physical base address and size of peripherals.
- * Ordered by the virtual base addresses they will be mapped at.
- *
- * If you add or remove entries here, you'll want to edit the
- * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
- * changes.
- *
- */
-
-#define MSM8960_TMR_PHYS        0x0200A000
-#define MSM8960_TMR_SIZE        SZ_4K
-
-#define MSM8960_TMR0_PHYS       0x0208A000
-#define MSM8960_TMR0_SIZE       SZ_4K
-
-#ifdef CONFIG_DEBUG_MSM8960_UART
-#define MSM_DEBUG_UART_BASE     0xF0040000
-#define MSM_DEBUG_UART_PHYS     0x16440000
-#endif
-
-#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
deleted file mode 100644
index 75a7b62c1c74..000000000000
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *
- * The MSM peripherals are spread all over across 768MB of physical
- * space, which makes just having a simple IO_ADDRESS macro to slide
- * them into the right virtual location rough.  Instead, we will
- * provide a master phys->virt mapping for peripherals here.
- *
- */
-
-#ifndef __ASM_ARCH_MSM_IOMAP_8X60_H
-#define __ASM_ARCH_MSM_IOMAP_8X60_H
-
-/* Physical base address and size of peripherals.
- * Ordered by the virtual base addresses they will be mapped at.
- *
- * MSM_VIC_BASE must be an value that can be loaded via a "mov"
- * instruction, otherwise entry-macro.S will not compile.
- *
- * If you add or remove entries here, you'll want to edit the
- * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
- * changes.
- *
- */
-
-#define MSM_TLMM_BASE           IOMEM(0xF0004000)
-#define MSM_TLMM_PHYS           0x00800000
-#define MSM_TLMM_SIZE           SZ_16K
-
-#define MSM8X60_TMR_PHYS        0x02000000
-#define MSM8X60_TMR_SIZE        SZ_4K
-
-#define MSM8X60_TMR0_PHYS       0x02040000
-#define MSM8X60_TMR0_SIZE       SZ_4K
-
-#ifdef CONFIG_DEBUG_MSM8660_UART
-#define MSM_DEBUG_UART_BASE     0xF0040000
-#define MSM_DEBUG_UART_PHYS     0x19C40000
-#endif
-
-#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index c56e81ffdcde..0e4f49157684 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -45,25 +45,8 @@
 #include "msm_iomap-7x00.h"
 #endif
 
-#include "msm_iomap-8x60.h"
-#include "msm_iomap-8960.h"
-
-#define MSM_DEBUG_UART_SIZE     SZ_4K
-#if defined(CONFIG_DEBUG_MSM_UART1)
-#define MSM_DEBUG_UART_BASE     0xE1000000
-#define MSM_DEBUG_UART_PHYS     MSM_UART1_PHYS
-#elif defined(CONFIG_DEBUG_MSM_UART2)
-#define MSM_DEBUG_UART_BASE     0xE1000000
-#define MSM_DEBUG_UART_PHYS     MSM_UART2_PHYS
-#elif defined(CONFIG_DEBUG_MSM_UART3)
-#define MSM_DEBUG_UART_BASE     0xE1000000
-#define MSM_DEBUG_UART_PHYS     MSM_UART3_PHYS
-#endif
-
 /* Virtual addresses shared across all MSM targets. */
 #define MSM_CSR_BASE            IOMEM(0xE0001000)
-#define MSM_TMR_BASE            IOMEM(0xF0200000)
-#define MSM_TMR0_BASE           IOMEM(0xF0201000)
 #define MSM_GPIO1_BASE          IOMEM(0xE0003000)
 #define MSM_GPIO2_BASE          IOMEM(0xE0004000)
 
diff --git a/arch/arm/mach-msm/include/mach/uncompress.h b/arch/arm/mach-msm/include/mach/uncompress.h
deleted file mode 100644
index 94324870fb04..000000000000
--- a/arch/arm/mach-msm/include/mach/uncompress.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARCH_MSM_UNCOMPRESS_H
-#define __ASM_ARCH_MSM_UNCOMPRESS_H
-
-#include <asm/barrier.h>
-#include <asm/processor.h>
-#include <mach/msm_iomap.h>
-
-#define UART_CSR      (*(volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x08))
-#define UART_TF       (*(volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x0c))
-
-#define UART_DM_SR    (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x08)))
-#define UART_DM_CR    (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x10)))
-#define UART_DM_ISR   (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x14)))
-#define UART_DM_NCHAR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x40)))
-#define UART_DM_TF    (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x70)))
-
-static void putc(int c)
-{
-#if defined(MSM_DEBUG_UART_PHYS)
-#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
-        /*
-         * Wait for TX_READY to be set; but skip it if we have a
-         * TX underrun.
-         */
-        if (!(UART_DM_SR & 0x08))
-                while (!(UART_DM_ISR & 0x80))
-                        cpu_relax();
-
-        UART_DM_CR = 0x300;
-        UART_DM_NCHAR = 0x1;
-        UART_DM_TF = c;
-#else
-        while (!(UART_CSR & 0x04))
-                cpu_relax();
-        UART_TF = c;
-#endif
-#endif
-}
-
-static inline void flush(void)
-{
-}
-
-static inline void arch_decomp_setup(void)
-{
-}
-
-#endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 3dc04ccaf59f..adc8971c7266 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -18,6 +18,7 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/bug.h>
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/export.h>
@@ -27,8 +28,6 @@
 #include <mach/msm_iomap.h>
 #include <asm/mach/map.h>
 
-#include <mach/board.h>
-
 #include "common.h"
 
 #define MSM_CHIP_DEVICE_TYPE(name, chip, mem_type) {                          \
@@ -52,26 +51,38 @@ static struct map_desc msm_io_desc[] __initdata = {
         MSM_CHIP_DEVICE_TYPE(GPIO1, MSM7X00, MT_DEVICE_NONSHARED),
         MSM_CHIP_DEVICE_TYPE(GPIO2, MSM7X00, MT_DEVICE_NONSHARED),
         MSM_DEVICE_TYPE(CLK_CTL, MT_DEVICE_NONSHARED),
-#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
-        defined(CONFIG_DEBUG_MSM_UART3)
-        MSM_DEVICE_TYPE(DEBUG_UART, MT_DEVICE_NONSHARED),
-#endif
         {
                 .virtual =  (unsigned long) MSM_SHARED_RAM_BASE,
                 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
                 .length =   MSM_SHARED_RAM_SIZE,
                 .type =     MT_DEVICE,
         },
+#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
+                defined(CONFIG_DEBUG_MSM_UART3)
+        {
+                /* Must be last: virtual and pfn filled in by debug_ll_addr() */
+                .length = SZ_4K,
+                .type = MT_DEVICE_NONSHARED,
+        }
+#endif
 };
 
 void __init msm_map_common_io(void)
 {
+        size_t size = ARRAY_SIZE(msm_io_desc);
+
         /* Make sure the peripheral register window is closed, since
          * we will use PTE flags (TEX[1]=1,B=0,C=1) to determine which
          * pages are peripheral interface or not.
          */
         asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0));
-        iotable_init(msm_io_desc, ARRAY_SIZE(msm_io_desc));
+#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
+                defined(CONFIG_DEBUG_MSM_UART3)
+        debug_ll_addr(&msm_io_desc[size - 1].pfn,
+                      &msm_io_desc[size - 1].virtual);
+        msm_io_desc[size - 1].pfn = __phys_to_pfn(msm_io_desc[size - 1].pfn);
+#endif
+        iotable_init(msm_io_desc, size);
 }
 #endif
 
@@ -87,10 +98,6 @@ static struct map_desc qsd8x50_io_desc[] __initdata = {
         MSM_DEVICE(SCPLL),
         MSM_DEVICE(AD5),
         MSM_DEVICE(MDC),
-#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
-        defined(CONFIG_DEBUG_MSM_UART3)
-        MSM_DEVICE(DEBUG_UART),
-#endif
         {
                 .virtual =  (unsigned long) MSM_SHARED_RAM_BASE,
                 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
@@ -101,40 +108,11 @@ static struct map_desc qsd8x50_io_desc[] __initdata = {
 
 void __init msm_map_qsd8x50_io(void)
 {
+        debug_ll_io_init();
         iotable_init(qsd8x50_io_desc, ARRAY_SIZE(qsd8x50_io_desc));
 }
 #endif /* CONFIG_ARCH_QSD8X50 */
 
-#ifdef CONFIG_ARCH_MSM8X60
-static struct map_desc msm8x60_io_desc[] __initdata = {
-        MSM_CHIP_DEVICE(TMR, MSM8X60),
-        MSM_CHIP_DEVICE(TMR0, MSM8X60),
-#ifdef CONFIG_DEBUG_MSM8660_UART
-        MSM_DEVICE(DEBUG_UART),
-#endif
-};
-
-void __init msm_map_msm8x60_io(void)
-{
-        iotable_init(msm8x60_io_desc, ARRAY_SIZE(msm8x60_io_desc));
-}
-#endif /* CONFIG_ARCH_MSM8X60 */
-
-#ifdef CONFIG_ARCH_MSM8960
-static struct map_desc msm8960_io_desc[] __initdata = {
-        MSM_CHIP_DEVICE(TMR, MSM8960),
-        MSM_CHIP_DEVICE(TMR0, MSM8960),
-#ifdef CONFIG_DEBUG_MSM8960_UART
-        MSM_DEVICE(DEBUG_UART),
-#endif
-};
-
-void __init msm_map_msm8960_io(void)
-{
-        iotable_init(msm8960_io_desc, ARRAY_SIZE(msm8960_io_desc));
-}
-#endif /* CONFIG_ARCH_MSM8960 */
-
 #ifdef CONFIG_ARCH_MSM7X30
 static struct map_desc msm7x30_io_desc[] __initdata = {
         MSM_DEVICE(VIC),
@@ -150,10 +128,6 @@ static struct map_desc msm7x30_io_desc[] __initdata = {
         MSM_DEVICE(SAW),
         MSM_DEVICE(GCC),
         MSM_DEVICE(TCSR),
-#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
-        defined(CONFIG_DEBUG_MSM_UART3)
-        MSM_DEVICE(DEBUG_UART),
-#endif
         {
                 .virtual =  (unsigned long) MSM_SHARED_RAM_BASE,
                 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
@@ -164,10 +138,12 @@ static struct map_desc msm7x30_io_desc[] __initdata = {
 
 void __init msm_map_msm7x30_io(void)
 {
+        debug_ll_io_init();
         iotable_init(msm7x30_io_desc, ARRAY_SIZE(msm7x30_io_desc));
 }
 #endif /* CONFIG_ARCH_MSM7X30 */
 
+#ifdef CONFIG_ARCH_MSM7X00A
 void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
                                    unsigned int mtype, void *caller)
 {
@@ -182,3 +158,4 @@ void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
 
         return __arm_ioremap_caller(phys_addr, size, mtype, caller);
 }
+#endif
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 8697cfc0d0b6..696fb73296d0 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -16,6 +16,7 @@
 
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
+#include <linux/cpu.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
@@ -26,7 +27,6 @@
 #include <linux/sched_clock.h>
 
 #include <asm/mach/time.h>
-#include <asm/localtimer.h>
 
 #include "common.h"
 
@@ -49,7 +49,7 @@ static void __iomem *sts_base;
 
 static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
 {
-        struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
+        struct clock_event_device *evt = dev_id;
         /* Stop the timer tick */
         if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
                 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
@@ -101,18 +101,7 @@ static void msm_timer_set_mode(enum clock_event_mode mode,
         writel_relaxed(ctrl, event_base + TIMER_ENABLE);
 }
 
-static struct clock_event_device msm_clockevent = {
-        .name           = "gp_timer",
-        .features       = CLOCK_EVT_FEAT_ONESHOT,
-        .rating         = 200,
-        .set_next_event = msm_timer_set_next_event,
-        .set_mode       = msm_timer_set_mode,
-};
-
-static union {
-        struct clock_event_device *evt;
-        struct clock_event_device * __percpu *percpu_evt;
-} msm_evt;
+static struct clock_event_device __percpu *msm_evt;
 
 static void __iomem *source_base;
 
@@ -138,23 +127,34 @@ static struct clocksource msm_clocksource = {
         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
-#ifdef CONFIG_LOCAL_TIMERS
+static int msm_timer_irq;
+static int msm_timer_has_ppi;
+
 static int msm_local_timer_setup(struct clock_event_device *evt)
 {
-        /* Use existing clock_event for cpu 0 */
-        if (!smp_processor_id())
-                return 0;
-
-        evt->irq = msm_clockevent.irq;
-        evt->name = "local_timer";
-        evt->features = msm_clockevent.features;
-        evt->rating = msm_clockevent.rating;
+        int cpu = smp_processor_id();
+        int err;
+
+        evt->irq = msm_timer_irq;
+        evt->name = "msm_timer";
+        evt->features = CLOCK_EVT_FEAT_ONESHOT;
+        evt->rating = 200;
         evt->set_mode = msm_timer_set_mode;
         evt->set_next_event = msm_timer_set_next_event;
+        evt->cpumask = cpumask_of(cpu);
+
+        clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);
+
+        if (msm_timer_has_ppi) {
+                enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
+        } else {
+                err = request_irq(evt->irq, msm_timer_interrupt,
+                                IRQF_TIMER | IRQF_NOBALANCING |
+                                IRQF_TRIGGER_RISING, "gp_timer", evt);
+                if (err)
+                        pr_err("request_irq failed\n");
+        }
 
-        *__this_cpu_ptr(msm_evt.percpu_evt) = evt;
-        clockevents_config_and_register(evt, GPT_HZ, 4, 0xf0000000);
-        enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
         return 0;
 }
 
@@ -164,11 +164,28 @@ static void msm_local_timer_stop(struct clock_event_device *evt)
         disable_percpu_irq(evt->irq);
 }
 
-static struct local_timer_ops msm_local_timer_ops = {
-        .setup  = msm_local_timer_setup,
-        .stop   = msm_local_timer_stop,
+static int msm_timer_cpu_notify(struct notifier_block *self,
+                                           unsigned long action, void *hcpu)
+{
+        /*
+         * Grab cpu pointer in each case to avoid spurious
+         * preemptible warnings
+         */
+        switch (action & ~CPU_TASKS_FROZEN) {
+        case CPU_STARTING:
+                msm_local_timer_setup(this_cpu_ptr(msm_evt));
+                break;
+        case CPU_DYING:
+                msm_local_timer_stop(this_cpu_ptr(msm_evt));
+                break;
+        }
+
+        return NOTIFY_OK;
+}
+
+static struct notifier_block msm_timer_cpu_nb = {
+        .notifier_call = msm_timer_cpu_notify,
 };
-#endif /* CONFIG_LOCAL_TIMERS */
 
 static notrace u32 msm_sched_clock_read(void)
 {
@@ -178,38 +195,35 @@ static notrace u32 msm_sched_clock_read(void)
 static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
                                   bool percpu)
 {
-        struct clock_event_device *ce = &msm_clockevent;
         struct clocksource *cs = &msm_clocksource;
-        int res;
+        int res = 0;
+
+        msm_timer_irq = irq;
+        msm_timer_has_ppi = percpu;
+
+        msm_evt = alloc_percpu(struct clock_event_device);
+        if (!msm_evt) {
+                pr_err("memory allocation failed for clockevents\n");
+                goto err;
+        }
 
-        ce->cpumask = cpumask_of(0);
-        ce->irq = irq;
+        if (percpu)
+                res = request_percpu_irq(irq, msm_timer_interrupt,
+                                         "gp_timer", msm_evt);
 
-        clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
-        if (percpu) {
-                msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
-                if (!msm_evt.percpu_evt) {
-                        pr_err("memory allocation failed for %s\n", ce->name);
+        if (res) {
+                pr_err("request_percpu_irq failed\n");
+        } else {
+                res = register_cpu_notifier(&msm_timer_cpu_nb);
+                if (res) {
+                        free_percpu_irq(irq, msm_evt);
                         goto err;
                 }
-                *__this_cpu_ptr(msm_evt.percpu_evt) = ce;
-                res = request_percpu_irq(ce->irq, msm_timer_interrupt,
-                                         ce->name, msm_evt.percpu_evt);
-                if (!res) {
-                        enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING);
-#ifdef CONFIG_LOCAL_TIMERS
-                        local_timer_register(&msm_local_timer_ops);
-#endif
-                }
-        } else {
-                msm_evt.evt = ce;
-                res = request_irq(ce->irq, msm_timer_interrupt,
-                                  IRQF_TIMER | IRQF_NOBALANCING |
-                                  IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
+
+                /* Immediately configure the timer on the boot CPU */
+                msm_local_timer_setup(__this_cpu_ptr(msm_evt));
         }
 
-        if (res)
-                pr_err("request_irq failed for %s\n", ce->name);
 err:
         writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
         res = clocksource_register_hz(cs, dgt_hz);
@@ -219,15 +233,8 @@ err:
 }
 
 #ifdef CONFIG_OF
-static const struct of_device_id msm_timer_match[] __initconst = {
-        { .compatible = "qcom,kpss-timer" },
-        { .compatible = "qcom,scss-timer" },
-        { },
-};
-
-void __init msm_dt_timer_init(void)
+static void __init msm_dt_timer_init(struct device_node *np)
 {
-        struct device_node *np;
         u32 freq;
         int irq;
         struct resource res;
@@ -235,12 +242,6 @@ void __init msm_dt_timer_init(void)
         void __iomem *base;
         void __iomem *cpu0_base;
 
-        np = of_find_matching_node(NULL, msm_timer_match);
-        if (!np) {
-                pr_err("Can't find msm timer DT node\n");
-                return;
-        }
-
         base = of_iomap(np, 0);
         if (!base) {
                 pr_err("Failed to map event base\n");
@@ -283,6 +284,8 @@ void __init msm_dt_timer_init(void)
 
         msm_timer_init(freq, 32, irq, !!percpu_offset);
 }
+CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
+CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
 #endif
 
 static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index 594b63db4215..f9c09b75d4d7 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -82,28 +82,11 @@ static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
 
 static void __init armada_xp_smp_init_cpus(void)
 {
-        struct device_node *np;
-        unsigned int i, ncores;
+        unsigned int ncores = num_possible_cpus();
 
-        np = of_find_node_by_name(NULL, "cpus");
-        if (!np)
-                panic("No 'cpus' node found\n");
-
-        ncores = of_get_child_count(np);
         if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS)
                 panic("Invalid number of CPUs in DT\n");
 
-        /* Limit possible CPUs to defconfig */
-        if (ncores > nr_cpu_ids) {
-                pr_warn("SMP: %d CPUs physically present. Only %d configured.",
-                        ncores, nr_cpu_ids);
-                pr_warn("Clipping CPU count to %d\n", nr_cpu_ids);
-                ncores = nr_cpu_ids;
-        }
-
-        for (i = 0; i < ncores; i++)
-                set_cpu_possible(i, true);
-
         set_smp_cross_call(armada_mpic_send_doorbell);
 }
 
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 3ed8acd42ecd..56021c67c89c 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -37,9 +37,8 @@ config ARCH_OMAP4
         select CACHE_L2X0
         select CPU_V7
         select HAVE_ARM_SCU if SMP
-        select HAVE_ARM_TWD if LOCAL_TIMERS
+        select HAVE_ARM_TWD if SMP
         select HAVE_SMP
-        select LOCAL_TIMERS if SMP
         select OMAP_INTERCONNECT
         select PL310_ERRATA_588369
         select PL310_ERRATA_727915
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 8cc2c9e9fb03..543d9a882de3 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -21,7 +21,7 @@
 #include <linux/clk.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
-#include <linux/i2c/pca953x.h>
+#include <linux/platform_data/pca953x.h>
 #include <linux/can/platform/ti_hecc.h>
 #include <linux/davinci_emac.h>
 #include <linux/mmc/host.h>
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index 669ef51b17a8..8538669cc2ad 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -14,439 +14,121 @@
  * published by the Free Software Foundation.
  */
 
-/* Bits shared between registers */
-
-/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
 #define OMAP24XX_EN_CAM_SHIFT                           31
-#define OMAP24XX_EN_CAM_MASK                            (1 << 31)
 #define OMAP24XX_EN_WDT4_SHIFT                          29
-#define OMAP24XX_EN_WDT4_MASK                           (1 << 29)
 #define OMAP2420_EN_WDT3_SHIFT                          28
-#define OMAP2420_EN_WDT3_MASK                           (1 << 28)
 #define OMAP24XX_EN_MSPRO_SHIFT                         27
-#define OMAP24XX_EN_MSPRO_MASK                          (1 << 27)
 #define OMAP24XX_EN_FAC_SHIFT                           25
-#define OMAP24XX_EN_FAC_MASK                            (1 << 25)
 #define OMAP2420_EN_EAC_SHIFT                           24
-#define OMAP2420_EN_EAC_MASK                            (1 << 24)
 #define OMAP24XX_EN_HDQ_SHIFT                           23
-#define OMAP24XX_EN_HDQ_MASK                            (1 << 23)
 #define OMAP2420_EN_I2C2_SHIFT                          20
-#define OMAP2420_EN_I2C2_MASK                           (1 << 20)
 #define OMAP2420_EN_I2C1_SHIFT                          19
-#define OMAP2420_EN_I2C1_MASK                           (1 << 19)
-
-/* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */
 #define OMAP2430_EN_MCBSP5_SHIFT                        5
-#define OMAP2430_EN_MCBSP5_MASK                         (1 << 5)
 #define OMAP2430_EN_MCBSP4_SHIFT                        4
-#define OMAP2430_EN_MCBSP4_MASK                         (1 << 4)
 #define OMAP2430_EN_MCBSP3_SHIFT                        3
-#define OMAP2430_EN_MCBSP3_MASK                         (1 << 3)
 #define OMAP24XX_EN_SSI_SHIFT                           1
-#define OMAP24XX_EN_SSI_MASK                            (1 << 1)
-
-/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
 #define OMAP24XX_EN_MPU_WDT_SHIFT                       3
-#define OMAP24XX_EN_MPU_WDT_MASK                        (1 << 3)
-
-/* Bits specific to each register */
-
-/* CM_IDLEST_MPU */
-/* 2430 only */
-#define OMAP2430_ST_MPU_MASK                            (1 << 0)
-
-/* CM_CLKSEL_MPU */
 #define OMAP24XX_CLKSEL_MPU_SHIFT                       0
-#define OMAP24XX_CLKSEL_MPU_MASK                        (0x1f << 0)
 #define OMAP24XX_CLKSEL_MPU_WIDTH                       5
-
-/* CM_CLKSTCTRL_MPU */
-#define OMAP24XX_AUTOSTATE_MPU_SHIFT                    0
 #define OMAP24XX_AUTOSTATE_MPU_MASK                     (1 << 0)
-
-/* CM_FCLKEN1_CORE specific bits*/
 #define OMAP24XX_EN_TV_SHIFT                            2
-#define OMAP24XX_EN_TV_MASK                             (1 << 2)
 #define OMAP24XX_EN_DSS2_SHIFT                          1
-#define OMAP24XX_EN_DSS2_MASK                           (1 << 1)
 #define OMAP24XX_EN_DSS1_SHIFT                          0
 #define OMAP24XX_EN_DSS1_MASK                           (1 << 0)
-
-/* CM_FCLKEN2_CORE specific bits */
 #define OMAP2430_EN_I2CHS2_SHIFT                        20
-#define OMAP2430_EN_I2CHS2_MASK                         (1 << 20)
 #define OMAP2430_EN_I2CHS1_SHIFT                        19
-#define OMAP2430_EN_I2CHS1_MASK                         (1 << 19)
 #define OMAP2430_EN_MMCHSDB2_SHIFT                      17
-#define OMAP2430_EN_MMCHSDB2_MASK                       (1 << 17)
 #define OMAP2430_EN_MMCHSDB1_SHIFT                      16
-#define OMAP2430_EN_MMCHSDB1_MASK                       (1 << 16)
-
-/* CM_ICLKEN1_CORE specific bits */
 #define OMAP24XX_EN_MAILBOXES_SHIFT                     30
-#define OMAP24XX_EN_MAILBOXES_MASK                      (1 << 30)
-#define OMAP24XX_EN_DSS_SHIFT                           0
-#define OMAP24XX_EN_DSS_MASK                            (1 << 0)
-
-/* CM_ICLKEN2_CORE specific bits */
-
-/* CM_ICLKEN3_CORE */
-/* 2430 only */
 #define OMAP2430_EN_SDRC_SHIFT                          2
-#define OMAP2430_EN_SDRC_MASK                           (1 << 2)
-
-/* CM_ICLKEN4_CORE */
 #define OMAP24XX_EN_PKA_SHIFT                           4
-#define OMAP24XX_EN_PKA_MASK                            (1 << 4)
 #define OMAP24XX_EN_AES_SHIFT                           3
-#define OMAP24XX_EN_AES_MASK                            (1 << 3)
 #define OMAP24XX_EN_RNG_SHIFT                           2
-#define OMAP24XX_EN_RNG_MASK                            (1 << 2)
 #define OMAP24XX_EN_SHA_SHIFT                           1
-#define OMAP24XX_EN_SHA_MASK                            (1 << 1)
 #define OMAP24XX_EN_DES_SHIFT                           0
-#define OMAP24XX_EN_DES_MASK                            (1 << 0)
-
-/* CM_IDLEST1_CORE specific bits */
 #define OMAP24XX_ST_MAILBOXES_SHIFT                     30
-#define OMAP24XX_ST_MAILBOXES_MASK                      (1 << 30)
-#define OMAP24XX_ST_WDT4_SHIFT                          29
-#define OMAP24XX_ST_WDT4_MASK                           (1 << 29)
-#define OMAP2420_ST_WDT3_SHIFT                          28
-#define OMAP2420_ST_WDT3_MASK                           (1 << 28)
-#define OMAP24XX_ST_MSPRO_SHIFT                         27
-#define OMAP24XX_ST_MSPRO_MASK                          (1 << 27)
-#define OMAP24XX_ST_FAC_SHIFT                           25
-#define OMAP24XX_ST_FAC_MASK                            (1 << 25)
-#define OMAP2420_ST_EAC_SHIFT                           24
-#define OMAP2420_ST_EAC_MASK                            (1 << 24)
 #define OMAP24XX_ST_HDQ_SHIFT                           23
-#define OMAP24XX_ST_HDQ_MASK                            (1 << 23)
 #define OMAP2420_ST_I2C2_SHIFT                          20
-#define OMAP2420_ST_I2C2_MASK                           (1 << 20)
 #define OMAP2430_ST_I2CHS1_SHIFT                        19
-#define OMAP2430_ST_I2CHS1_MASK                         (1 << 19)
 #define OMAP2420_ST_I2C1_SHIFT                          19
-#define OMAP2420_ST_I2C1_MASK                           (1 << 19)
 #define OMAP2430_ST_I2CHS2_SHIFT                        20
-#define OMAP2430_ST_I2CHS2_MASK                         (1 << 20)
 #define OMAP24XX_ST_MCBSP2_SHIFT                        16
-#define OMAP24XX_ST_MCBSP2_MASK                         (1 << 16)
 #define OMAP24XX_ST_MCBSP1_SHIFT                        15
-#define OMAP24XX_ST_MCBSP1_MASK                         (1 << 15)
 #define OMAP24XX_ST_DSS_SHIFT                           0
-#define OMAP24XX_ST_DSS_MASK                            (1 << 0)
-
-/* CM_IDLEST2_CORE */
 #define OMAP2430_ST_MCBSP5_SHIFT                        5
-#define OMAP2430_ST_MCBSP5_MASK                         (1 << 5)
 #define OMAP2430_ST_MCBSP4_SHIFT                        4
-#define OMAP2430_ST_MCBSP4_MASK                         (1 << 4)
 #define OMAP2430_ST_MCBSP3_SHIFT                        3
-#define OMAP2430_ST_MCBSP3_MASK                         (1 << 3)
-#define OMAP24XX_ST_SSI_SHIFT                           1
-#define OMAP24XX_ST_SSI_MASK                            (1 << 1)
-
-/* CM_IDLEST3_CORE */
-/* 2430 only */
-#define OMAP2430_ST_SDRC_MASK                           (1 << 2)
-
-/* CM_IDLEST4_CORE */
-#define OMAP24XX_ST_PKA_SHIFT                           4
-#define OMAP24XX_ST_PKA_MASK                            (1 << 4)
 #define OMAP24XX_ST_AES_SHIFT                           3
-#define OMAP24XX_ST_AES_MASK                            (1 << 3)
 #define OMAP24XX_ST_RNG_SHIFT                           2
-#define OMAP24XX_ST_RNG_MASK                            (1 << 2)
 #define OMAP24XX_ST_SHA_SHIFT                           1
-#define OMAP24XX_ST_SHA_MASK                            (1 << 1)
-#define OMAP24XX_ST_DES_SHIFT                           0
-#define OMAP24XX_ST_DES_MASK                            (1 << 0)
-
-/* CM_AUTOIDLE1_CORE */
-#define OMAP24XX_AUTO_CAM_MASK                          (1 << 31)
-#define OMAP24XX_AUTO_MAILBOXES_MASK                    (1 << 30)
-#define OMAP24XX_AUTO_WDT4_MASK                         (1 << 29)
-#define OMAP2420_AUTO_WDT3_MASK                         (1 << 28)
-#define OMAP24XX_AUTO_MSPRO_MASK                        (1 << 27)
-#define OMAP2420_AUTO_MMC_MASK                          (1 << 26)
-#define OMAP24XX_AUTO_FAC_MASK                          (1 << 25)
-#define OMAP2420_AUTO_EAC_MASK                          (1 << 24)
-#define OMAP24XX_AUTO_HDQ_MASK                          (1 << 23)
-#define OMAP24XX_AUTO_UART2_MASK                        (1 << 22)
-#define OMAP24XX_AUTO_UART1_MASK                        (1 << 21)
-#define OMAP24XX_AUTO_I2C2_MASK                         (1 << 20)
-#define OMAP24XX_AUTO_I2C1_MASK                         (1 << 19)
-#define OMAP24XX_AUTO_MCSPI2_MASK                       (1 << 18)
-#define OMAP24XX_AUTO_MCSPI1_MASK                       (1 << 17)
-#define OMAP24XX_AUTO_MCBSP2_MASK                       (1 << 16)
-#define OMAP24XX_AUTO_MCBSP1_MASK                       (1 << 15)
-#define OMAP24XX_AUTO_GPT12_MASK                        (1 << 14)
-#define OMAP24XX_AUTO_GPT11_MASK                        (1 << 13)
-#define OMAP24XX_AUTO_GPT10_MASK                        (1 << 12)
-#define OMAP24XX_AUTO_GPT9_MASK                         (1 << 11)
-#define OMAP24XX_AUTO_GPT8_MASK                         (1 << 10)
-#define OMAP24XX_AUTO_GPT7_MASK                         (1 << 9)
-#define OMAP24XX_AUTO_GPT6_MASK                         (1 << 8)
-#define OMAP24XX_AUTO_GPT5_MASK                         (1 << 7)
-#define OMAP24XX_AUTO_GPT4_MASK                         (1 << 6)
-#define OMAP24XX_AUTO_GPT3_MASK                         (1 << 5)
-#define OMAP24XX_AUTO_GPT2_MASK                         (1 << 4)
-#define OMAP2420_AUTO_VLYNQ_MASK                        (1 << 3)
-#define OMAP24XX_AUTO_DSS_MASK                          (1 << 0)
-
-/* CM_AUTOIDLE2_CORE */
-#define OMAP2430_AUTO_MDM_INTC_MASK                     (1 << 11)
-#define OMAP2430_AUTO_GPIO5_MASK                        (1 << 10)
-#define OMAP2430_AUTO_MCSPI3_MASK                       (1 << 9)
-#define OMAP2430_AUTO_MMCHS2_MASK                       (1 << 8)
-#define OMAP2430_AUTO_MMCHS1_MASK                       (1 << 7)
-#define OMAP2430_AUTO_USBHS_MASK                        (1 << 6)
-#define OMAP2430_AUTO_MCBSP5_MASK                       (1 << 5)
-#define OMAP2430_AUTO_MCBSP4_MASK                       (1 << 4)
-#define OMAP2430_AUTO_MCBSP3_MASK                       (1 << 3)
-#define OMAP24XX_AUTO_UART3_MASK                        (1 << 2)
-#define OMAP24XX_AUTO_SSI_MASK                          (1 << 1)
-#define OMAP24XX_AUTO_USB_MASK                          (1 << 0)
-
-/* CM_AUTOIDLE3_CORE */
 #define OMAP24XX_AUTO_SDRC_SHIFT                        2
-#define OMAP24XX_AUTO_SDRC_MASK                         (1 << 2)
 #define OMAP24XX_AUTO_GPMC_SHIFT                        1
-#define OMAP24XX_AUTO_GPMC_MASK                         (1 << 1)
 #define OMAP24XX_AUTO_SDMA_SHIFT                        0
-#define OMAP24XX_AUTO_SDMA_MASK                         (1 << 0)
-
-/* CM_AUTOIDLE4_CORE */
-#define OMAP24XX_AUTO_PKA_MASK                          (1 << 4)
-#define OMAP24XX_AUTO_AES_MASK                          (1 << 3)
-#define OMAP24XX_AUTO_RNG_MASK                          (1 << 2)
-#define OMAP24XX_AUTO_SHA_MASK                          (1 << 1)
-#define OMAP24XX_AUTO_DES_MASK                          (1 << 0)
-
-/* CM_CLKSEL1_CORE */
-#define OMAP24XX_CLKSEL_USB_SHIFT                       25
 #define OMAP24XX_CLKSEL_USB_MASK                        (0x7 << 25)
-#define OMAP24XX_CLKSEL_SSI_SHIFT                       20
 #define OMAP24XX_CLKSEL_SSI_MASK                        (0x1f << 20)
-#define OMAP2420_CLKSEL_VLYNQ_SHIFT                     15
 #define OMAP2420_CLKSEL_VLYNQ_MASK                      (0x1f << 15)
-#define OMAP24XX_CLKSEL_DSS2_SHIFT                      13
 #define OMAP24XX_CLKSEL_DSS2_MASK                       (0x1 << 13)
-#define OMAP24XX_CLKSEL_DSS1_SHIFT                      8
 #define OMAP24XX_CLKSEL_DSS1_MASK                       (0x1f << 8)
 #define OMAP24XX_CLKSEL_L4_SHIFT                        5
-#define OMAP24XX_CLKSEL_L4_MASK                         (0x3 << 5)
 #define OMAP24XX_CLKSEL_L4_WIDTH                        2
 #define OMAP24XX_CLKSEL_L3_SHIFT                        0
-#define OMAP24XX_CLKSEL_L3_MASK                         (0x1f << 0)
 #define OMAP24XX_CLKSEL_L3_WIDTH                        5
-
-/* CM_CLKSEL2_CORE */
-#define OMAP24XX_CLKSEL_GPT12_SHIFT                     22
 #define OMAP24XX_CLKSEL_GPT12_MASK                      (0x3 << 22)
-#define OMAP24XX_CLKSEL_GPT11_SHIFT                     20
 #define OMAP24XX_CLKSEL_GPT11_MASK                      (0x3 << 20)
-#define OMAP24XX_CLKSEL_GPT10_SHIFT                     18
 #define OMAP24XX_CLKSEL_GPT10_MASK                      (0x3 << 18)
-#define OMAP24XX_CLKSEL_GPT9_SHIFT                      16
 #define OMAP24XX_CLKSEL_GPT9_MASK                       (0x3 << 16)
-#define OMAP24XX_CLKSEL_GPT8_SHIFT                      14
 #define OMAP24XX_CLKSEL_GPT8_MASK                       (0x3 << 14)
-#define OMAP24XX_CLKSEL_GPT7_SHIFT                      12
 #define OMAP24XX_CLKSEL_GPT7_MASK                       (0x3 << 12)
-#define OMAP24XX_CLKSEL_GPT6_SHIFT                      10
 #define OMAP24XX_CLKSEL_GPT6_MASK                       (0x3 << 10)
-#define OMAP24XX_CLKSEL_GPT5_SHIFT                      8
 #define OMAP24XX_CLKSEL_GPT5_MASK                       (0x3 << 8)
-#define OMAP24XX_CLKSEL_GPT4_SHIFT                      6
 #define OMAP24XX_CLKSEL_GPT4_MASK                       (0x3 << 6)
-#define OMAP24XX_CLKSEL_GPT3_SHIFT                      4
 #define OMAP24XX_CLKSEL_GPT3_MASK                       (0x3 << 4)
-#define OMAP24XX_CLKSEL_GPT2_SHIFT                      2
 #define OMAP24XX_CLKSEL_GPT2_MASK                       (0x3 << 2)
-
-/* CM_CLKSTCTRL_CORE */
-#define OMAP24XX_AUTOSTATE_DSS_SHIFT                    2
 #define OMAP24XX_AUTOSTATE_DSS_MASK                     (1 << 2)
-#define OMAP24XX_AUTOSTATE_L4_SHIFT                     1
 #define OMAP24XX_AUTOSTATE_L4_MASK                      (1 << 1)
-#define OMAP24XX_AUTOSTATE_L3_SHIFT                     0
 #define OMAP24XX_AUTOSTATE_L3_MASK                      (1 << 0)
-
-/* CM_FCLKEN_GFX */
 #define OMAP24XX_EN_3D_SHIFT                            2
-#define OMAP24XX_EN_3D_MASK                             (1 << 2)
 #define OMAP24XX_EN_2D_SHIFT                            1
-#define OMAP24XX_EN_2D_MASK                             (1 << 1)
-
-/* CM_ICLKEN_GFX specific bits */
-
-/* CM_IDLEST_GFX specific bits */
-
-/* CM_CLKSEL_GFX specific bits */
-
-/* CM_CLKSTCTRL_GFX */
-#define OMAP24XX_AUTOSTATE_GFX_SHIFT                    0
 #define OMAP24XX_AUTOSTATE_GFX_MASK                     (1 << 0)
-
-/* CM_FCLKEN_WKUP specific bits */
-
-/* CM_ICLKEN_WKUP specific bits */
 #define OMAP2430_EN_ICR_SHIFT                           6
-#define OMAP2430_EN_ICR_MASK                            (1 << 6)
 #define OMAP24XX_EN_OMAPCTRL_SHIFT                      5
-#define OMAP24XX_EN_OMAPCTRL_MASK                       (1 << 5)
 #define OMAP24XX_EN_WDT1_SHIFT                          4
-#define OMAP24XX_EN_WDT1_MASK                           (1 << 4)
 #define OMAP24XX_EN_32KSYNC_SHIFT                       1
-#define OMAP24XX_EN_32KSYNC_MASK                        (1 << 1)
-
-/* CM_IDLEST_WKUP specific bits */
-#define OMAP2430_ST_ICR_SHIFT                           6
-#define OMAP2430_ST_ICR_MASK                            (1 << 6)
-#define OMAP24XX_ST_OMAPCTRL_SHIFT                      5
-#define OMAP24XX_ST_OMAPCTRL_MASK                       (1 << 5)
-#define OMAP24XX_ST_WDT1_SHIFT                          4
-#define OMAP24XX_ST_WDT1_MASK                           (1 << 4)
 #define OMAP24XX_ST_MPU_WDT_SHIFT                       3
-#define OMAP24XX_ST_MPU_WDT_MASK                        (1 << 3)
 #define OMAP24XX_ST_32KSYNC_SHIFT                       1
-#define OMAP24XX_ST_32KSYNC_MASK                        (1 << 1)
-
-/* CM_AUTOIDLE_WKUP */
-#define OMAP24XX_AUTO_OMAPCTRL_MASK                     (1 << 5)
-#define OMAP24XX_AUTO_WDT1_MASK                         (1 << 4)
-#define OMAP24XX_AUTO_MPU_WDT_MASK                      (1 << 3)
-#define OMAP24XX_AUTO_GPIOS_MASK                        (1 << 2)
-#define OMAP24XX_AUTO_32KSYNC_MASK                      (1 << 1)
-#define OMAP24XX_AUTO_GPT1_MASK                         (1 << 0)
-
-/* CM_CLKSEL_WKUP */
-#define OMAP24XX_CLKSEL_GPT1_SHIFT                      0
 #define OMAP24XX_CLKSEL_GPT1_MASK                       (0x3 << 0)
-
-/* CM_CLKEN_PLL */
 #define OMAP24XX_EN_54M_PLL_SHIFT                       6
-#define OMAP24XX_EN_54M_PLL_MASK                        (0x3 << 6)
 #define OMAP24XX_EN_96M_PLL_SHIFT                       2
-#define OMAP24XX_EN_96M_PLL_MASK                        (0x3 << 2)
-#define OMAP24XX_EN_DPLL_SHIFT                          0
 #define OMAP24XX_EN_DPLL_MASK                           (0x3 << 0)
-
-/* CM_IDLEST_CKGEN */
 #define OMAP24XX_ST_54M_APLL_SHIFT                      9
-#define OMAP24XX_ST_54M_APLL_MASK                       (1 << 9)
 #define OMAP24XX_ST_96M_APLL_SHIFT                      8
-#define OMAP24XX_ST_96M_APLL_MASK                       (1 << 8)
-#define OMAP24XX_ST_54M_CLK_MASK                        (1 << 6)
-#define OMAP24XX_ST_12M_CLK_MASK                        (1 << 5)
-#define OMAP24XX_ST_48M_CLK_MASK                        (1 << 4)
-#define OMAP24XX_ST_96M_CLK_MASK                        (1 << 2)
-#define OMAP24XX_ST_CORE_CLK_SHIFT                      0
-#define OMAP24XX_ST_CORE_CLK_MASK                       (0x3 << 0)
-
-/* CM_AUTOIDLE_PLL */
-#define OMAP24XX_AUTO_54M_SHIFT                         6
 #define OMAP24XX_AUTO_54M_MASK                          (0x3 << 6)
-#define OMAP24XX_AUTO_96M_SHIFT                         2
 #define OMAP24XX_AUTO_96M_MASK                          (0x3 << 2)
 #define OMAP24XX_AUTO_DPLL_SHIFT                        0
 #define OMAP24XX_AUTO_DPLL_MASK                         (0x3 << 0)
-
-/* CM_CLKSEL1_PLL */
-#define OMAP2430_MAXDPLLFASTLOCK_SHIFT                  28
-#define OMAP2430_MAXDPLLFASTLOCK_MASK                   (0x7 << 28)
 #define OMAP24XX_APLLS_CLKIN_SHIFT                      23
 #define OMAP24XX_APLLS_CLKIN_MASK                       (0x7 << 23)
-#define OMAP24XX_DPLL_MULT_SHIFT                        12
 #define OMAP24XX_DPLL_MULT_MASK                         (0x3ff << 12)
-#define OMAP24XX_DPLL_DIV_SHIFT                         8
 #define OMAP24XX_DPLL_DIV_MASK                          (0xf << 8)
 #define OMAP24XX_54M_SOURCE_SHIFT                       5
-#define OMAP24XX_54M_SOURCE_MASK                        (1 << 5)
 #define OMAP24XX_54M_SOURCE_WIDTH                       1
 #define OMAP2430_96M_SOURCE_SHIFT                       4
-#define OMAP2430_96M_SOURCE_MASK                        (1 << 4)
 #define OMAP2430_96M_SOURCE_WIDTH                       1
-#define OMAP24XX_48M_SOURCE_SHIFT                       3
 #define OMAP24XX_48M_SOURCE_MASK                        (1 << 3)
-#define OMAP2430_ALTCLK_SOURCE_SHIFT                    0
-#define OMAP2430_ALTCLK_SOURCE_MASK                     (0x7 << 0)
-
-/* CM_CLKSEL2_PLL */
-#define OMAP24XX_CORE_CLK_SRC_SHIFT                     0
 #define OMAP24XX_CORE_CLK_SRC_MASK                      (0x3 << 0)
-
-/* CM_FCLKEN_DSP */
 #define OMAP2420_EN_IVA_COP_SHIFT                       10
-#define OMAP2420_EN_IVA_COP_MASK                        (1 << 10)
 #define OMAP2420_EN_IVA_MPU_SHIFT                       8
-#define OMAP2420_EN_IVA_MPU_MASK                        (1 << 8)
 #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT             0
-#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_MASK              (1 << 0)
-
-/* CM_ICLKEN_DSP */
 #define OMAP2420_EN_DSP_IPI_SHIFT                       1
-#define OMAP2420_EN_DSP_IPI_MASK                        (1 << 1)
-
-/* CM_IDLEST_DSP */
-#define OMAP2420_ST_IVA_MASK                            (1 << 8)
-#define OMAP2420_ST_IPI_MASK                            (1 << 1)
-#define OMAP24XX_ST_DSP_MASK                            (1 << 0)
-
-/* CM_AUTOIDLE_DSP */
-#define OMAP2420_AUTO_DSP_IPI_MASK                      (1 << 1)
-
-/* CM_CLKSEL_DSP */
-#define OMAP2420_SYNC_IVA_MASK                          (1 << 13)
-#define OMAP2420_CLKSEL_IVA_SHIFT                       8
 #define OMAP2420_CLKSEL_IVA_MASK                        (0x1f << 8)
-#define OMAP24XX_SYNC_DSP_MASK                          (1 << 7)
-#define OMAP24XX_CLKSEL_DSP_IF_SHIFT                    5
 #define OMAP24XX_CLKSEL_DSP_IF_MASK                     (0x3 << 5)
-#define OMAP24XX_CLKSEL_DSP_SHIFT                       0
 #define OMAP24XX_CLKSEL_DSP_MASK                        (0x1f << 0)
-
-/* CM_CLKSTCTRL_DSP */
-#define OMAP2420_AUTOSTATE_IVA_SHIFT                    8
 #define OMAP2420_AUTOSTATE_IVA_MASK                     (1 << 8)
-#define OMAP24XX_AUTOSTATE_DSP_SHIFT                    0
 #define OMAP24XX_AUTOSTATE_DSP_MASK                     (1 << 0)
-
-/* CM_FCLKEN_MDM */
-/* 2430 only */
 #define OMAP2430_EN_OSC_SHIFT                           1
-#define OMAP2430_EN_OSC_MASK                            (1 << 1)
-
-/* CM_ICLKEN_MDM */
-/* 2430 only */
 #define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT             0
-#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_MASK              (1 << 0)
-
-/* CM_IDLEST_MDM specific bits */
-/* 2430 only */
-
-/* CM_AUTOIDLE_MDM */
-/* 2430 only */
-#define OMAP2430_AUTO_OSC_MASK                          (1 << 1)
-#define OMAP2430_AUTO_MDM_MASK                          (1 << 0)
-
-/* CM_CLKSEL_MDM */
-/* 2430 only */
-#define OMAP2430_SYNC_MDM_MASK                          (1 << 4)
-#define OMAP2430_CLKSEL_MDM_SHIFT                       0
 #define OMAP2430_CLKSEL_MDM_MASK                        (0xf << 0)
-
-/* CM_CLKSTCTRL_MDM */
-/* 2430 only */
-#define OMAP2430_AUTOSTATE_MDM_SHIFT                    0
 #define OMAP2430_AUTOSTATE_MDM_MASK                     (1 << 0)
-
-/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */
 #define OMAP24XX_CLKSTCTRL_DISABLE_AUTO         0x0
 #define OMAP24XX_CLKSTCTRL_ENABLE_AUTO          0x1
-
-
 #endif
diff --git a/arch/arm/mach-omap2/cm-regbits-33xx.h b/arch/arm/mach-omap2/cm-regbits-33xx.h
index adf7bb79b18f..c0823fd6d5e0 100644
--- a/arch/arm/mach-omap2/cm-regbits-33xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-33xx.h
@@ -20,798 +20,49 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
 
-/*
- * Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP,
- * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER
- */
-#define AM33XX_AUTO_DPLL_MODE_SHIFT                     0
-#define AM33XX_AUTO_DPLL_MODE_WIDTH                     3
-#define AM33XX_AUTO_DPLL_MODE_MASK                      (0x7 << 0)
-
-/* Used by CM_WKUP_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT               14
-#define AM33XX_CLKACTIVITY_ADC_FCLK_WIDTH               1
-#define AM33XX_CLKACTIVITY_ADC_FCLK_MASK                (1 << 16)
-
-/* Used by CM_PER_L4LS_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT                11
-#define AM33XX_CLKACTIVITY_CAN_CLK_WIDTH                1
-#define AM33XX_CLKACTIVITY_CAN_CLK_MASK                 (1 << 11)
-
-/* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT         4
-#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_WIDTH         1
-#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK          (1 << 4)
-
-/* Used by CM_PER_CPSW_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT       4
-#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_WIDTH       1
-#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK        (1 << 4)
-
-/* Used by CM_PER_L4HS_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT       4
-#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_WIDTH       1
-#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK        (1 << 4)
-
-/* Used by CM_PER_L4HS_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT        5
-#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_WIDTH        1
-#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK         (1 << 5)
-
-/* Used by CM_PER_L4HS_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT         6
-#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_WIDTH         1
-#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK          (1 << 6)
-
-/* Used by CM_PER_L3_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT          6
-#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_WIDTH          1
-#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK           (1 << 6)
-
-/* Used by CM_CEFUSE_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT     9
-#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH     1
-#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK      (1 << 9)
-
-/* Used by CM_L3_AON_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT              2
-#define AM33XX_CLKACTIVITY_DBGSYSCLK_WIDTH              1
-#define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK               (1 << 2)
-
-/* Used by CM_L3_AON_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT             4
-#define AM33XX_CLKACTIVITY_DEBUG_CLKA_WIDTH             1
-#define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK              (1 << 4)
-
-/* Used by CM_PER_L3_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT              2
-#define AM33XX_CLKACTIVITY_EMIF_GCLK_WIDTH              1
-#define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK               (1 << 2)
-
-/* Used by CM_GFX_L3_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT               9
-#define AM33XX_CLKACTIVITY_GFX_FCLK_WIDTH               1
-#define AM33XX_CLKACTIVITY_GFX_FCLK_MASK                (1 << 9)
-
-/* Used by CM_GFX_L3_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT            8
-#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_WIDTH            1
-#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK             (1 << 8)
-
-/* Used by CM_WKUP_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT           8
-#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_WIDTH           1
-#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK            (1 << 8)
-
-/* Used by CM_PER_L4LS_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT          19
-#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_WIDTH          1
-#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK           (1 << 19)
-
-/* Used by CM_PER_L4LS_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT          20
-#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_WIDTH          1
-#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK           (1 << 20)
-
-/* Used by CM_PER_L4LS_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT          21
-#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_WIDTH          1
-#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK           (1 << 21)
-
-/* Used by CM_PER_L4LS_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT          22
-#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_WIDTH          1
-#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK           (1 << 22)
-
-/* Used by CM_PER_L4LS_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT          26
-#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_WIDTH          1
-#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK           (1 << 26)
-
-/* Used by CM_PER_L4LS_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT          18
-#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_WIDTH          1
-#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK           (1 << 18)
-
-/* Used by CM_WKUP_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT             11
-#define AM33XX_CLKACTIVITY_I2C0_GFCLK_WIDTH             1
-#define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK              (1 << 11)
-
-/* Used by CM_PER_L4LS_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT               24
-#define AM33XX_CLKACTIVITY_I2C_FCLK_WIDTH               1
-#define AM33XX_CLKACTIVITY_I2C_FCLK_MASK                (1 << 24)
-
-/* Used by CM_PER_PRUSS_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT         5
-#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_WIDTH         1
-#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK          (1 << 5)
-
-/* Used by CM_PER_PRUSS_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT         4
-#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_WIDTH         1
-#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK          (1 << 4)
-
-/* Used by CM_PER_PRUSS_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT        6
-#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_WIDTH        1
-#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK         (1 << 6)
-
-/* Used by CM_PER_L3S_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT               3
-#define AM33XX_CLKACTIVITY_L3S_GCLK_WIDTH               1
-#define AM33XX_CLKACTIVITY_L3S_GCLK_MASK                (1 << 3)
-
-/* Used by CM_L3_AON_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT            3
-#define AM33XX_CLKACTIVITY_L3_AON_GCLK_WIDTH            1
-#define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK             (1 << 3)
-
-/* Used by CM_PER_L3_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT                4
-#define AM33XX_CLKACTIVITY_L3_GCLK_WIDTH                1
-#define AM33XX_CLKACTIVITY_L3_GCLK_MASK                 (1 << 4)
-
-/* Used by CM_PER_L4FW_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT              8
-#define AM33XX_CLKACTIVITY_L4FW_GCLK_WIDTH              1
-#define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK               (1 << 8)
-
-/* Used by CM_PER_L4HS_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT              3
-#define AM33XX_CLKACTIVITY_L4HS_GCLK_WIDTH              1
-#define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK               (1 << 3)
-
-/* Used by CM_PER_L4LS_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT              8
-#define AM33XX_CLKACTIVITY_L4LS_GCLK_WIDTH              1
-#define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK               (1 << 8)
-
-/* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */
-#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT          8
-#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_WIDTH          1
-#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK           (1 << 8)
-
-/* Used by CM_CEFUSE_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT        8
-#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH        1
-#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK         (1 << 8)
-
-/* Used by CM_RTC_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT            8
-#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_WIDTH            1
-#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK             (1 << 8)
-
-/* Used by CM_L4_WKUP_AON_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT       2
-#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_WIDTH       1
-#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK        (1 << 2)
-
-/* Used by CM_WKUP_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT           2
-#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_WIDTH           1
-#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK            (1 << 2)
-
-/* Used by CM_PER_L4LS_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT              17
-#define AM33XX_CLKACTIVITY_LCDC_GCLK_WIDTH              1
-#define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK               (1 << 17)
-
-/* Used by CM_PER_LCDC_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT       4
-#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_WIDTH       1
-#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK        (1 << 4)
-
-/* Used by CM_PER_LCDC_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT       5
-#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_WIDTH       1
-#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK        (1 << 5)
-
-/* Used by CM_PER_L3_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT             7
-#define AM33XX_CLKACTIVITY_MCASP_GCLK_WIDTH             1
-#define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK              (1 << 7)
-
-/* Used by CM_PER_L3_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT               3
-#define AM33XX_CLKACTIVITY_MMC_FCLK_WIDTH               1
-#define AM33XX_CLKACTIVITY_MMC_FCLK_MASK                (1 << 3)
-
-/* Used by CM_MPU_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT                2
-#define AM33XX_CLKACTIVITY_MPU_CLK_WIDTH                1
-#define AM33XX_CLKACTIVITY_MPU_CLK_MASK                 (1 << 2)
-
-/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT          4
-#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_WIDTH          1
-#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK           (1 << 4)
-
-/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT          5
-#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_WIDTH          1
-#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK           (1 << 5)
-
-/* Used by CM_RTC_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT             9
-#define AM33XX_CLKACTIVITY_RTC_32KCLK_WIDTH             1
-#define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK              (1 << 9)
-
-/* Used by CM_PER_L4LS_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT               25
-#define AM33XX_CLKACTIVITY_SPI_GCLK_WIDTH               1
-#define AM33XX_CLKACTIVITY_SPI_GCLK_MASK                (1 << 25)
-
-/* Used by CM_WKUP_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT              3
-#define AM33XX_CLKACTIVITY_SR_SYSCLK_WIDTH              1
-#define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK               (1 << 3)
-
-/* Used by CM_WKUP_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT            10
-#define AM33XX_CLKACTIVITY_TIMER0_GCLK_WIDTH            1
-#define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK             (1 << 10)
-
-/* Used by CM_WKUP_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT            13
-#define AM33XX_CLKACTIVITY_TIMER1_GCLK_WIDTH            1
-#define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK             (1 << 13)
-
-/* Used by CM_PER_L4LS_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT            14
-#define AM33XX_CLKACTIVITY_TIMER2_GCLK_WIDTH            1
-#define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK             (1 << 14)
-
-/* Used by CM_PER_L4LS_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT            15
-#define AM33XX_CLKACTIVITY_TIMER3_GCLK_WIDTH            1
-#define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK             (1 << 15)
-
-/* Used by CM_PER_L4LS_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT            16
-#define AM33XX_CLKACTIVITY_TIMER4_GCLK_WIDTH            1
-#define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK             (1 << 16)
-
-/* Used by CM_PER_L4LS_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT            27
-#define AM33XX_CLKACTIVITY_TIMER5_GCLK_WIDTH            1
-#define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK             (1 << 27)
-
-/* Used by CM_PER_L4LS_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT            28
-#define AM33XX_CLKACTIVITY_TIMER6_GCLK_WIDTH            1
-#define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK             (1 << 28)
-
-/* Used by CM_PER_L4LS_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT            13
-#define AM33XX_CLKACTIVITY_TIMER7_GCLK_WIDTH            1
-#define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK             (1 << 13)
-
-/* Used by CM_WKUP_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT            12
-#define AM33XX_CLKACTIVITY_UART0_GFCLK_WIDTH            1
-#define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK             (1 << 12)
-
-/* Used by CM_PER_L4LS_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT             10
-#define AM33XX_CLKACTIVITY_UART_GFCLK_WIDTH             1
-#define AM33XX_CLKACTIVITY_UART_GFCLK_MASK              (1 << 10)
-
-/* Used by CM_WKUP_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT              9
-#define AM33XX_CLKACTIVITY_WDT0_GCLK_WIDTH              1
-#define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK               (1 << 9)
-
-/* Used by CM_WKUP_CLKSTCTRL */
-#define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT              4
-#define AM33XX_CLKACTIVITY_WDT1_GCLK_WIDTH              1
-#define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK               (1 << 4)
-
-/* Used by CLKSEL_GFX_FCLK */
-#define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT                0
-#define AM33XX_CLKDIV_SEL_GFX_FCLK_WIDTH                1
-#define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK                 (1 << 0)
-
-/* Used by CM_CLKOUT_CTRL */
 #define AM33XX_CLKOUT2DIV_SHIFT                         3
 #define AM33XX_CLKOUT2DIV_WIDTH                         3
-#define AM33XX_CLKOUT2DIV_MASK                          (0x7 << 3)
-
-/* Used by CM_CLKOUT_CTRL */
 #define AM33XX_CLKOUT2EN_SHIFT                          7
-#define AM33XX_CLKOUT2EN_WIDTH                          1
-#define AM33XX_CLKOUT2EN_MASK                           (1 << 7)
-
-/* Used by CM_CLKOUT_CTRL */
-#define AM33XX_CLKOUT2SOURCE_SHIFT                      0
-#define AM33XX_CLKOUT2SOURCE_WIDTH                      3
 #define AM33XX_CLKOUT2SOURCE_MASK                       (0x7 << 0)
-
-/*
- * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK,
- * CLKSEL_TIMER3_CLK, CLKSEL_TIMER4_CLK, CLKSEL_TIMER5_CLK, CLKSEL_TIMER6_CLK,
- * CLKSEL_TIMER7_CLK
- */
-#define AM33XX_CLKSEL_SHIFT                             0
-#define AM33XX_CLKSEL_WIDTH                             1
-#define AM33XX_CLKSEL_MASK                              (0x01 << 0)
-
-/*
- * Renamed from CLKSEL Used by CLKSEL_PRUSS_OCP_CLK, CLKSEL_WDT1_CLK,
- * CM_CPTS_RFT_CLKSEL
- */
 #define AM33XX_CLKSEL_0_0_SHIFT                         0
 #define AM33XX_CLKSEL_0_0_WIDTH                         1
 #define AM33XX_CLKSEL_0_0_MASK                          (1 << 0)
-
-#define AM33XX_CLKSEL_0_1_SHIFT                         0
-#define AM33XX_CLKSEL_0_1_WIDTH                         2
 #define AM33XX_CLKSEL_0_1_MASK                          (3 << 0)
-
-/* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */
-#define AM33XX_CLKSEL_0_2_SHIFT                         0
-#define AM33XX_CLKSEL_0_2_WIDTH                         3
 #define AM33XX_CLKSEL_0_2_MASK                          (7 << 0)
-
-/* Used by CLKSEL_GFX_FCLK */
-#define AM33XX_CLKSEL_GFX_FCLK_SHIFT                    1
-#define AM33XX_CLKSEL_GFX_FCLK_WIDTH                    1
 #define AM33XX_CLKSEL_GFX_FCLK_MASK                     (1 << 1)
-
-/*
- * Used by CM_MPU_CLKSTCTRL, CM_RTC_CLKSTCTRL, CM_PER_CLK_24MHZ_CLKSTCTRL,
- * CM_PER_CPSW_CLKSTCTRL, CM_PER_PRUSS_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL,
- * CM_PER_L3_CLKSTCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_L4HS_CLKSTCTRL,
- * CM_PER_L4LS_CLKSTCTRL, CM_PER_LCDC_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL,
- * CM_L3_AON_CLKSTCTRL, CM_L4_WKUP_AON_CLKSTCTRL, CM_WKUP_CLKSTCTRL,
- * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL
- */
 #define AM33XX_CLKTRCTRL_SHIFT                          0
-#define AM33XX_CLKTRCTRL_WIDTH                          2
 #define AM33XX_CLKTRCTRL_MASK                           (0x3 << 0)
-
-/*
- * Used by CM_SSC_DELTAMSTEP_DPLL_CORE, CM_SSC_DELTAMSTEP_DPLL_DDR,
- * CM_SSC_DELTAMSTEP_DPLL_DISP, CM_SSC_DELTAMSTEP_DPLL_MPU,
- * CM_SSC_DELTAMSTEP_DPLL_PER
- */
-#define AM33XX_DELTAMSTEP_SHIFT                         0
-#define AM33XX_DELTAMSTEP_WIDTH                         20
-#define AM33XX_DELTAMSTEP_MASK                          (0xfffff << 0)
-
-/* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */
-#define AM33XX_DPLL_BYP_CLKSEL_SHIFT                    23
-#define AM33XX_DPLL_BYP_CLKSEL_WIDTH                    1
-#define AM33XX_DPLL_BYP_CLKSEL_MASK                     (1 << 23)
-
-/* Used by CM_CLKDCOLDO_DPLL_PER */
-#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT           8
-#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH           1
-#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK            (1 << 8)
-
-/* Used by CM_CLKDCOLDO_DPLL_PER */
-#define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT                12
-#define AM33XX_DPLL_CLKDCOLDO_PWDN_WIDTH                1
-#define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK                 (1 << 12)
-
-/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
 #define AM33XX_DPLL_CLKOUT_DIV_SHIFT                    0
 #define AM33XX_DPLL_CLKOUT_DIV_WIDTH                    5
-#define AM33XX_DPLL_CLKOUT_DIV_MASK                     (0x1f << 0)
-
-/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */
-#define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT                0
-#define AM33XX_DPLL_CLKOUT_DIV_0_6_WIDTH                7
-#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK                 (0x7f << 0)
-
-/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
-#define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT               5
-#define AM33XX_DPLL_CLKOUT_DIVCHACK_WIDTH               1
-#define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK                (1 << 5)
-
-/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */
-#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT        7
-#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_WIDTH        1
-#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK         (1 << 7)
-
-/*
- * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
- * CM_DIV_M2_DPLL_PER
- */
-#define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT              8
-#define AM33XX_DPLL_CLKOUT_GATE_CTRL_WIDTH              1
-#define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK               (1 << 8)
-
-/*
- * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
- * CM_CLKSEL_DPLL_MPU
- */
-#define AM33XX_DPLL_DIV_SHIFT                           0
-#define AM33XX_DPLL_DIV_WIDTH                           7
 #define AM33XX_DPLL_DIV_MASK                            (0x7f << 0)
-
 #define AM33XX_DPLL_PER_DIV_MASK                        (0xff << 0)
-
-/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */
-#define AM33XX_DPLL_DIV_0_7_SHIFT                       0
-#define AM33XX_DPLL_DIV_0_7_WIDTH                       8
-#define AM33XX_DPLL_DIV_0_7_MASK                        (0xff << 0)
-
-/*
- * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
- * CM_CLKMODE_DPLL_MPU
- */
-#define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT                 8
-#define AM33XX_DPLL_DRIFTGUARD_EN_WIDTH                 1
-#define AM33XX_DPLL_DRIFTGUARD_EN_MASK                  (1 << 8)
-
-/*
- * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
- */
-#define AM33XX_DPLL_EN_SHIFT                            0
-#define AM33XX_DPLL_EN_WIDTH                            3
 #define AM33XX_DPLL_EN_MASK                             (0x7 << 0)
-
-/*
- * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
- * CM_CLKMODE_DPLL_MPU
- */
-#define AM33XX_DPLL_LPMODE_EN_SHIFT                     10
-#define AM33XX_DPLL_LPMODE_EN_WIDTH                     1
-#define AM33XX_DPLL_LPMODE_EN_MASK                      (1 << 10)
-
-/*
- * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
- * CM_CLKSEL_DPLL_MPU
- */
-#define AM33XX_DPLL_MULT_SHIFT                          8
-#define AM33XX_DPLL_MULT_WIDTH                          11
 #define AM33XX_DPLL_MULT_MASK                           (0x7ff << 8)
-
-/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */
-#define AM33XX_DPLL_MULT_PERIPH_SHIFT                   8
-#define AM33XX_DPLL_MULT_PERIPH_WIDTH                   12
 #define AM33XX_DPLL_MULT_PERIPH_MASK                    (0xfff << 8)
-
-/*
- * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
- * CM_CLKMODE_DPLL_MPU
- */
-#define AM33XX_DPLL_REGM4XEN_SHIFT                      11
-#define AM33XX_DPLL_REGM4XEN_WIDTH                      1
-#define AM33XX_DPLL_REGM4XEN_MASK                       (1 << 11)
-
-/* Used by CM_CLKSEL_DPLL_PERIPH */
-#define AM33XX_DPLL_SD_DIV_SHIFT                        24
-#define AM33XX_DPLL_SD_DIV_WIDTH                        8
-#define AM33XX_DPLL_SD_DIV_MASK                         (0xff << 24)
-
-/*
- * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
- */
-#define AM33XX_DPLL_SSC_ACK_SHIFT                       13
-#define AM33XX_DPLL_SSC_ACK_WIDTH                       1
-#define AM33XX_DPLL_SSC_ACK_MASK                        (1 << 13)
-
-/*
- * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
- */
-#define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT                14
-#define AM33XX_DPLL_SSC_DOWNSPREAD_WIDTH                1
-#define AM33XX_DPLL_SSC_DOWNSPREAD_MASK                 (1 << 14)
-
-/*
- * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
- */
-#define AM33XX_DPLL_SSC_EN_SHIFT                        12
-#define AM33XX_DPLL_SSC_EN_WIDTH                        1
-#define AM33XX_DPLL_SSC_EN_MASK                         (1 << 12)
-
-/* Used by CM_DIV_M4_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT              0
 #define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH              5
-#define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK               (0x1f << 0)
-
-/* Used by CM_DIV_M4_DPLL_CORE */
-#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT         5
-#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH         1
-#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK          (1 << 5)
-
-/* Used by CM_DIV_M4_DPLL_CORE */
-#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT        8
-#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH        1
-#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK         (1 << 8)
-
-/* Used by CM_DIV_M4_DPLL_CORE */
-#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT             12
-#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_WIDTH             1
-#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK              (1 << 12)
-
-/* Used by CM_DIV_M5_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT              0
 #define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH              5
-#define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK               (0x1f << 0)
-
-/* Used by CM_DIV_M5_DPLL_CORE */
-#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT         5
-#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH         1
-#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK          (1 << 5)
-
-/* Used by CM_DIV_M5_DPLL_CORE */
-#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT        8
-#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH        1
-#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK         (1 << 8)
-
-/* Used by CM_DIV_M5_DPLL_CORE */
-#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT             12
-#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_WIDTH             1
-#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK              (1 << 12)
-
-/* Used by CM_DIV_M6_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT              0
 #define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH              5
-#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK               (0x1f << 0)
-
-/* Used by CM_DIV_M6_DPLL_CORE */
-#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT         5
-#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH         1
-#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK          (1 << 5)
-
-/* Used by CM_DIV_M6_DPLL_CORE */
-#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT        8
-#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH        1
-#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK         (1 << 8)
-
-/* Used by CM_DIV_M6_DPLL_CORE */
-#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT             12
-#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_WIDTH             1
-#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK              (1 << 12)
-
-/*
- * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
- * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
- * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
- * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
- * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
- * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
- * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
- * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
- * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
- * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
- * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
- * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
- * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
- * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
- * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
- * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
- * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
- * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
- * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
- * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
- * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
- * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
- * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
- * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
- * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
- * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
- * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
- * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
- * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
- * CM_WKUP_WDT1_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL,
- * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL
- */
 #define AM33XX_IDLEST_SHIFT                             16
-#define AM33XX_IDLEST_WIDTH                             2
 #define AM33XX_IDLEST_MASK                              (0x3 << 16)
-
-/* Used by CM_MAC_CLKSEL */
-#define AM33XX_MII_CLK_SEL_SHIFT                        2
-#define AM33XX_MII_CLK_SEL_WIDTH                        1
-#define AM33XX_MII_CLK_SEL_MASK                         (1 << 2)
-
-/*
- * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
- * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
- * CM_SSC_MODFREQDIV_DPLL_PER
- */
-#define AM33XX_MODFREQDIV_EXPONENT_SHIFT                8
-#define AM33XX_MODFREQDIV_EXPONENT_WIDTH                3
-#define AM33XX_MODFREQDIV_EXPONENT_MASK                 (0x7 << 8)
-
-/*
- * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
- * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
- * CM_SSC_MODFREQDIV_DPLL_PER
- */
-#define AM33XX_MODFREQDIV_MANTISSA_SHIFT                0
-#define AM33XX_MODFREQDIV_MANTISSA_WIDTH                7
-#define AM33XX_MODFREQDIV_MANTISSA_MASK                 (0x7f << 0)
-
-/*
- * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
- * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
- * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
- * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
- * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
- * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
- * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
- * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
- * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
- * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
- * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
- * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
- * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
- * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
- * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
- * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
- * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
- * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
- * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
- * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
- * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
- * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
- * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
- * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
- * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
- * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
- * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
- * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
- * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
- * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL,
- * CM_GFX_GFX_CLKCTRL, CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL,
- * CM_CEFUSE_CEFUSE_CLKCTRL
- */
 #define AM33XX_MODULEMODE_SHIFT                         0
-#define AM33XX_MODULEMODE_WIDTH                         2
 #define AM33XX_MODULEMODE_MASK                          (0x3 << 0)
-
-/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT                  30
-#define AM33XX_OPTCLK_DEBUG_CLKA_WIDTH                  1
-#define AM33XX_OPTCLK_DEBUG_CLKA_MASK                   (1 << 30)
-
-/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT                19
-#define AM33XX_OPTFCLKEN_DBGSYSCLK_WIDTH                1
-#define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK                 (1 << 19)
-
-/* Used by CM_WKUP_GPIO0_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT             18
-#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_WIDTH             1
-#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK              (1 << 18)
-
-/* Used by CM_PER_GPIO1_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT            18
-#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_WIDTH            1
-#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK             (1 << 18)
-
-/* Used by CM_PER_GPIO2_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT            18
-#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_WIDTH            1
-#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK             (1 << 18)
-
-/* Used by CM_PER_GPIO3_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT            18
-#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_WIDTH            1
-#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK             (1 << 18)
-
-/* Used by CM_PER_GPIO4_CLKCTRL */
-#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT            18
-#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_WIDTH            1
-#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK             (1 << 18)
-
-/* Used by CM_PER_GPIO5_CLKCTRL */
-#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT            18
-#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_WIDTH            1
-#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK             (1 << 18)
-
-/* Used by CM_PER_GPIO6_CLKCTRL */
-#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT            18
-#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_WIDTH            1
-#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK             (1 << 18)
-
-/*
- * Used by CM_MPU_MPU_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, CM_PER_PRUSS_CLKCTRL,
- * CM_PER_IEEE5000_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MLB_CLKCTRL,
- * CM_PER_MSTR_EXPS_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
- * CM_PER_SPARE_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
- * CM_PER_TPTC2_CLKCTRL, CM_PER_USB0_CLKCTRL, CM_WKUP_DEBUGSS_CLKCTRL,
- * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL
- */
-#define AM33XX_STBYST_SHIFT                             18
-#define AM33XX_STBYST_WIDTH                             1
-#define AM33XX_STBYST_MASK                              (1 << 18)
-
-/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_STM_PMD_CLKDIVSEL_SHIFT                  27
 #define AM33XX_STM_PMD_CLKDIVSEL_WIDTH                  3
-#define AM33XX_STM_PMD_CLKDIVSEL_MASK                   (0x7 << 27)
-
-/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_STM_PMD_CLKSEL_SHIFT                     22
 #define AM33XX_STM_PMD_CLKSEL_WIDTH                     2
-#define AM33XX_STM_PMD_CLKSEL_MASK                      (0x3 << 22)
-
-/*
- * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
- * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
- */
-#define AM33XX_ST_DPLL_CLK_SHIFT                        0
-#define AM33XX_ST_DPLL_CLK_WIDTH                        1
 #define AM33XX_ST_DPLL_CLK_MASK                         (1 << 0)
-
-/* Used by CM_CLKDCOLDO_DPLL_PER */
 #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT                  8
-#define AM33XX_ST_DPLL_CLKDCOLDO_WIDTH                  1
-#define AM33XX_ST_DPLL_CLKDCOLDO_MASK                   (1 << 8)
-
-/*
- * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
- * CM_DIV_M2_DPLL_PER
- */
-#define AM33XX_ST_DPLL_CLKOUT_SHIFT                     9
-#define AM33XX_ST_DPLL_CLKOUT_WIDTH                     1
-#define AM33XX_ST_DPLL_CLKOUT_MASK                      (1 << 9)
-
-/* Used by CM_DIV_M4_DPLL_CORE */
-#define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT               9
-#define AM33XX_ST_HSDIVIDER_CLKOUT1_WIDTH               1
-#define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK                (1 << 9)
-
-/* Used by CM_DIV_M5_DPLL_CORE */
-#define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT               9
-#define AM33XX_ST_HSDIVIDER_CLKOUT2_WIDTH               1
-#define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK                (1 << 9)
-
-/* Used by CM_DIV_M6_DPLL_CORE */
-#define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT               9
-#define AM33XX_ST_HSDIVIDER_CLKOUT3_WIDTH               1
-#define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK                (1 << 9)
-
-/*
- * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
- * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
- */
-#define AM33XX_ST_MN_BYPASS_SHIFT                       8
-#define AM33XX_ST_MN_BYPASS_WIDTH                       1
-#define AM33XX_ST_MN_BYPASS_MASK                        (1 << 8)
-
-/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT                  24
 #define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH                  3
-#define AM33XX_TRC_PMD_CLKDIVSEL_MASK                   (0x7 << 24)
-
-/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_TRC_PMD_CLKSEL_SHIFT                     20
 #define AM33XX_TRC_PMD_CLKSEL_WIDTH                     2
-#define AM33XX_TRC_PMD_CLKSEL_MASK                      (0x3 << 20)
-
-/* Used by CONTROL_SEC_CLK_CTRL */
-#define AM33XX_TIMER0_CLKSEL_WIDTH                      2
-#define AM33XX_TIMER0_CLKSEL_MASK                       (0x3 << 4)
 #endif
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index adf78d325804..04dab2fcf862 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -14,833 +14,201 @@
  * published by the Free Software Foundation.
  */
 
-/* Bits shared between registers */
-
-/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
-#define OMAP3430ES2_EN_MMC3_MASK                        (1 << 30)
 #define OMAP3430ES2_EN_MMC3_SHIFT                       30
-#define OMAP3430_EN_MSPRO_MASK                          (1 << 23)
 #define OMAP3430_EN_MSPRO_SHIFT                         23
-#define OMAP3430_EN_HDQ_MASK                            (1 << 22)
 #define OMAP3430_EN_HDQ_SHIFT                           22
-#define OMAP3430ES1_EN_FSHOSTUSB_MASK                   (1 << 5)
 #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT                  5
-#define OMAP3430ES1_EN_D2D_MASK                         (1 << 3)
 #define OMAP3430ES1_EN_D2D_SHIFT                        3
-#define OMAP3430_EN_SSI_MASK                            (1 << 0)
 #define OMAP3430_EN_SSI_SHIFT                           0
-
-/* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
 #define OMAP3430ES2_EN_USBTLL_SHIFT                     2
-#define OMAP3430ES2_EN_USBTLL_MASK                      (1 << 2)
-
-/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
-#define OMAP3430_EN_WDT2_MASK                           (1 << 5)
 #define OMAP3430_EN_WDT2_SHIFT                          5
-
-/* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
-#define OMAP3430_EN_CAM_MASK                            (1 << 0)
 #define OMAP3430_EN_CAM_SHIFT                           0
-
-/* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
-#define OMAP3430_EN_WDT3_MASK                           (1 << 12)
 #define OMAP3430_EN_WDT3_SHIFT                          12
-
-/* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
-#define OMAP3430_OVERRIDE_ENABLE_MASK                   (1 << 19)
-
-
-/* Bits specific to each register */
-
-/* CM_FCLKEN_IVA2 */
 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK            (1 << 0)
 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT           0
-
-/* CM_CLKEN_PLL_IVA2 */
-#define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT               8
-#define OMAP3430_IVA2_DPLL_RAMPTIME_MASK                (0x3 << 8)
-#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT                4
 #define OMAP3430_IVA2_DPLL_FREQSEL_MASK                 (0xf << 4)
 #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT          3
-#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK           (1 << 3)
-#define OMAP3430_EN_IVA2_DPLL_SHIFT                     0
 #define OMAP3430_EN_IVA2_DPLL_MASK                      (0x7 << 0)
-
-/* CM_IDLEST_IVA2 */
 #define OMAP3430_ST_IVA2_SHIFT                          0
-#define OMAP3430_ST_IVA2_MASK                           (1 << 0)
-
-/* CM_IDLEST_PLL_IVA2 */
-#define OMAP3430_ST_IVA2_CLK_SHIFT                      0
 #define OMAP3430_ST_IVA2_CLK_MASK                       (1 << 0)
-
-/* CM_AUTOIDLE_PLL_IVA2 */
-#define OMAP3430_AUTO_IVA2_DPLL_SHIFT                   0
 #define OMAP3430_AUTO_IVA2_DPLL_MASK                    (0x7 << 0)
-
-/* CM_CLKSEL1_PLL_IVA2 */
 #define OMAP3430_IVA2_CLK_SRC_SHIFT                     19
-#define OMAP3430_IVA2_CLK_SRC_MASK                      (0x7 << 19)
 #define OMAP3430_IVA2_CLK_SRC_WIDTH                     3
-#define OMAP3430_IVA2_DPLL_MULT_SHIFT                   8
 #define OMAP3430_IVA2_DPLL_MULT_MASK                    (0x7ff << 8)
-#define OMAP3430_IVA2_DPLL_DIV_SHIFT                    0
 #define OMAP3430_IVA2_DPLL_DIV_MASK                     (0x7f << 0)
-
-/* CM_CLKSEL2_PLL_IVA2 */
 #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT             0
-#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK              (0x1f << 0)
 #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH             5
-
-/* CM_CLKSTCTRL_IVA2 */
-#define OMAP3430_CLKTRCTRL_IVA2_SHIFT                   0
 #define OMAP3430_CLKTRCTRL_IVA2_MASK                    (0x3 << 0)
-
-/* CM_CLKSTST_IVA2 */
-#define OMAP3430_CLKACTIVITY_IVA2_SHIFT                 0
 #define OMAP3430_CLKACTIVITY_IVA2_MASK                  (1 << 0)
-
-/* CM_REVISION specific bits */
-
-/* CM_SYSCONFIG specific bits */
-
-/* CM_CLKEN_PLL_MPU */
-#define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT                8
-#define OMAP3430_MPU_DPLL_RAMPTIME_MASK                 (0x3 << 8)
-#define OMAP3430_MPU_DPLL_FREQSEL_SHIFT                 4
 #define OMAP3430_MPU_DPLL_FREQSEL_MASK                  (0xf << 4)
 #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT           3
-#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK            (1 << 3)
-#define OMAP3430_EN_MPU_DPLL_SHIFT                      0
 #define OMAP3430_EN_MPU_DPLL_MASK                       (0x7 << 0)
-
-/* CM_IDLEST_MPU */
-#define OMAP3430_ST_MPU_MASK                            (1 << 0)
-
-/* CM_IDLEST_PLL_MPU */
 #define OMAP3430_ST_MPU_CLK_SHIFT                       0
 #define OMAP3430_ST_MPU_CLK_MASK                        (1 << 0)
 #define OMAP3430_ST_MPU_CLK_WIDTH                       1
-
-/* CM_AUTOIDLE_PLL_MPU */
-#define OMAP3430_AUTO_MPU_DPLL_SHIFT                    0
 #define OMAP3430_AUTO_MPU_DPLL_MASK                     (0x7 << 0)
-
-/* CM_CLKSEL1_PLL_MPU */
 #define OMAP3430_MPU_CLK_SRC_SHIFT                      19
-#define OMAP3430_MPU_CLK_SRC_MASK                       (0x7 << 19)
 #define OMAP3430_MPU_CLK_SRC_WIDTH                      3
-#define OMAP3430_MPU_DPLL_MULT_SHIFT                    8
 #define OMAP3430_MPU_DPLL_MULT_MASK                     (0x7ff << 8)
-#define OMAP3430_MPU_DPLL_DIV_SHIFT                     0
 #define OMAP3430_MPU_DPLL_DIV_MASK                      (0x7f << 0)
-
-/* CM_CLKSEL2_PLL_MPU */
 #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT              0
-#define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK               (0x1f << 0)
 #define OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH              5
-
-/* CM_CLKSTCTRL_MPU */
-#define OMAP3430_CLKTRCTRL_MPU_SHIFT                    0
 #define OMAP3430_CLKTRCTRL_MPU_MASK                     (0x3 << 0)
-
-/* CM_CLKSTST_MPU */
-#define OMAP3430_CLKACTIVITY_MPU_SHIFT                  0
-#define OMAP3430_CLKACTIVITY_MPU_MASK                   (1 << 0)
-
-/* CM_FCLKEN1_CORE specific bits */
-#define OMAP3430_EN_MODEM_MASK                          (1 << 31)
 #define OMAP3430_EN_MODEM_SHIFT                         31
-
-/* CM_ICLKEN1_CORE specific bits */
-#define OMAP3430_EN_ICR_MASK                            (1 << 29)
 #define OMAP3430_EN_ICR_SHIFT                           29
-#define OMAP3430_EN_AES2_MASK                           (1 << 28)
 #define OMAP3430_EN_AES2_SHIFT                          28
-#define OMAP3430_EN_SHA12_MASK                          (1 << 27)
 #define OMAP3430_EN_SHA12_SHIFT                         27
-#define OMAP3430_EN_DES2_MASK                           (1 << 26)
 #define OMAP3430_EN_DES2_SHIFT                          26
-#define OMAP3430ES1_EN_FAC_MASK                         (1 << 8)
 #define OMAP3430ES1_EN_FAC_SHIFT                        8
-#define OMAP3430_EN_MAILBOXES_MASK                      (1 << 7)
 #define OMAP3430_EN_MAILBOXES_SHIFT                     7
-#define OMAP3430_EN_OMAPCTRL_MASK                       (1 << 6)
 #define OMAP3430_EN_OMAPCTRL_SHIFT                      6
-#define OMAP3430_EN_SAD2D_MASK                          (1 << 3)
 #define OMAP3430_EN_SAD2D_SHIFT                         3
-#define OMAP3430_EN_SDRC_MASK                           (1 << 1)
 #define OMAP3430_EN_SDRC_SHIFT                          1
-
-/* AM35XX specific CM_ICLKEN1_CORE bits */
-#define AM35XX_EN_IPSS_MASK                             (1 << 4)
 #define AM35XX_EN_IPSS_SHIFT                            4
-
-/* CM_ICLKEN2_CORE */
-#define OMAP3430_EN_PKA_MASK                            (1 << 4)
 #define OMAP3430_EN_PKA_SHIFT                           4
-#define OMAP3430_EN_AES1_MASK                           (1 << 3)
 #define OMAP3430_EN_AES1_SHIFT                          3
-#define OMAP3430_EN_RNG_MASK                            (1 << 2)
 #define OMAP3430_EN_RNG_SHIFT                           2
-#define OMAP3430_EN_SHA11_MASK                          (1 << 1)
 #define OMAP3430_EN_SHA11_SHIFT                         1
-#define OMAP3430_EN_DES1_MASK                           (1 << 0)
 #define OMAP3430_EN_DES1_SHIFT                          0
-
-/* CM_ICLKEN3_CORE */
 #define OMAP3430_EN_MAD2D_SHIFT                         3
-#define OMAP3430_EN_MAD2D_MASK                          (1 << 3)
-
-/* CM_FCLKEN3_CORE specific bits */
 #define OMAP3430ES2_EN_TS_SHIFT                         1
-#define OMAP3430ES2_EN_TS_MASK                          (1 << 1)
 #define OMAP3430ES2_EN_CPEFUSE_SHIFT                    0
-#define OMAP3430ES2_EN_CPEFUSE_MASK                     (1 << 0)
-
-/* CM_IDLEST1_CORE specific bits */
-#define OMAP3430ES2_ST_MMC3_SHIFT                       30
-#define OMAP3430ES2_ST_MMC3_MASK                        (1 << 30)
-#define OMAP3430_ST_ICR_SHIFT                           29
-#define OMAP3430_ST_ICR_MASK                            (1 << 29)
 #define OMAP3430_ST_AES2_SHIFT                          28
-#define OMAP3430_ST_AES2_MASK                           (1 << 28)
 #define OMAP3430_ST_SHA12_SHIFT                         27
-#define OMAP3430_ST_SHA12_MASK                          (1 << 27)
-#define OMAP3430_ST_DES2_SHIFT                          26
-#define OMAP3430_ST_DES2_MASK                           (1 << 26)
-#define OMAP3430_ST_MSPRO_SHIFT                         23
-#define OMAP3430_ST_MSPRO_MASK                          (1 << 23)
 #define AM35XX_ST_UART4_SHIFT                           23
-#define AM35XX_ST_UART4_MASK                            (1 << 23)
 #define OMAP3430_ST_HDQ_SHIFT                           22
-#define OMAP3430_ST_HDQ_MASK                            (1 << 22)
-#define OMAP3430ES1_ST_FAC_SHIFT                        8
-#define OMAP3430ES1_ST_FAC_MASK                         (1 << 8)
 #define OMAP3430ES2_ST_SSI_IDLE_SHIFT                   8
-#define OMAP3430ES2_ST_SSI_IDLE_MASK                    (1 << 8)
 #define OMAP3430_ST_MAILBOXES_SHIFT                     7
-#define OMAP3430_ST_MAILBOXES_MASK                      (1 << 7)
-#define OMAP3430_ST_OMAPCTRL_SHIFT                      6
-#define OMAP3430_ST_OMAPCTRL_MASK                       (1 << 6)
 #define OMAP3430_ST_SAD2D_SHIFT                         3
-#define OMAP3430_ST_SAD2D_MASK                          (1 << 3)
 #define OMAP3430_ST_SDMA_SHIFT                          2
-#define OMAP3430_ST_SDMA_MASK                           (1 << 2)
-#define OMAP3430_ST_SDRC_SHIFT                          1
-#define OMAP3430_ST_SDRC_MASK                           (1 << 1)
-#define OMAP3430_ST_SSI_STDBY_SHIFT                     0
-#define OMAP3430_ST_SSI_STDBY_MASK                      (1 << 0)
-
-/* AM35xx specific CM_IDLEST1_CORE bits */
 #define AM35XX_ST_IPSS_SHIFT                            5
-#define AM35XX_ST_IPSS_MASK                             (1 << 5)
-
-/* CM_IDLEST2_CORE */
-#define OMAP3430_ST_PKA_SHIFT                           4
-#define OMAP3430_ST_PKA_MASK                            (1 << 4)
-#define OMAP3430_ST_AES1_SHIFT                          3
-#define OMAP3430_ST_AES1_MASK                           (1 << 3)
-#define OMAP3430_ST_RNG_SHIFT                           2
-#define OMAP3430_ST_RNG_MASK                            (1 << 2)
-#define OMAP3430_ST_SHA11_SHIFT                         1
-#define OMAP3430_ST_SHA11_MASK                          (1 << 1)
-#define OMAP3430_ST_DES1_SHIFT                          0
-#define OMAP3430_ST_DES1_MASK                           (1 << 0)
-
-/* CM_IDLEST3_CORE */
 #define OMAP3430ES2_ST_USBTLL_SHIFT                     2
-#define OMAP3430ES2_ST_USBTLL_MASK                      (1 << 2)
-#define OMAP3430ES2_ST_CPEFUSE_SHIFT                    0
-#define OMAP3430ES2_ST_CPEFUSE_MASK                     (1 << 0)
-
-/* CM_AUTOIDLE1_CORE */
-#define OMAP3430_AUTO_MODEM_MASK                        (1 << 31)
-#define OMAP3430_AUTO_MODEM_SHIFT                       31
-#define OMAP3430ES2_AUTO_MMC3_MASK                      (1 << 30)
-#define OMAP3430ES2_AUTO_MMC3_SHIFT                     30
-#define OMAP3430ES2_AUTO_ICR_MASK                       (1 << 29)
-#define OMAP3430ES2_AUTO_ICR_SHIFT                      29
-#define OMAP3430_AUTO_AES2_MASK                         (1 << 28)
-#define OMAP3430_AUTO_AES2_SHIFT                        28
-#define OMAP3430_AUTO_SHA12_MASK                        (1 << 27)
-#define OMAP3430_AUTO_SHA12_SHIFT                       27
-#define OMAP3430_AUTO_DES2_MASK                         (1 << 26)
-#define OMAP3430_AUTO_DES2_SHIFT                        26
-#define OMAP3430_AUTO_MMC2_MASK                         (1 << 25)
-#define OMAP3430_AUTO_MMC2_SHIFT                        25
-#define OMAP3430_AUTO_MMC1_MASK                         (1 << 24)
-#define OMAP3430_AUTO_MMC1_SHIFT                        24
-#define OMAP3430_AUTO_MSPRO_MASK                        (1 << 23)
-#define OMAP3430_AUTO_MSPRO_SHIFT                       23
-#define OMAP3430_AUTO_HDQ_MASK                          (1 << 22)
-#define OMAP3430_AUTO_HDQ_SHIFT                         22
-#define OMAP3430_AUTO_MCSPI4_MASK                       (1 << 21)
-#define OMAP3430_AUTO_MCSPI4_SHIFT                      21
-#define OMAP3430_AUTO_MCSPI3_MASK                       (1 << 20)
-#define OMAP3430_AUTO_MCSPI3_SHIFT                      20
-#define OMAP3430_AUTO_MCSPI2_MASK                       (1 << 19)
-#define OMAP3430_AUTO_MCSPI2_SHIFT                      19
-#define OMAP3430_AUTO_MCSPI1_MASK                       (1 << 18)
-#define OMAP3430_AUTO_MCSPI1_SHIFT                      18
-#define OMAP3430_AUTO_I2C3_MASK                         (1 << 17)
-#define OMAP3430_AUTO_I2C3_SHIFT                        17
-#define OMAP3430_AUTO_I2C2_MASK                         (1 << 16)
-#define OMAP3430_AUTO_I2C2_SHIFT                        16
-#define OMAP3430_AUTO_I2C1_MASK                         (1 << 15)
-#define OMAP3430_AUTO_I2C1_SHIFT                        15
-#define OMAP3430_AUTO_UART2_MASK                        (1 << 14)
-#define OMAP3430_AUTO_UART2_SHIFT                       14
-#define OMAP3430_AUTO_UART1_MASK                        (1 << 13)
-#define OMAP3430_AUTO_UART1_SHIFT                       13
-#define OMAP3430_AUTO_GPT11_MASK                        (1 << 12)
-#define OMAP3430_AUTO_GPT11_SHIFT                       12
-#define OMAP3430_AUTO_GPT10_MASK                        (1 << 11)
-#define OMAP3430_AUTO_GPT10_SHIFT                       11
-#define OMAP3430_AUTO_MCBSP5_MASK                       (1 << 10)
-#define OMAP3430_AUTO_MCBSP5_SHIFT                      10
-#define OMAP3430_AUTO_MCBSP1_MASK                       (1 << 9)
-#define OMAP3430_AUTO_MCBSP1_SHIFT                      9
-#define OMAP3430ES1_AUTO_FAC_MASK                       (1 << 8)
-#define OMAP3430ES1_AUTO_FAC_SHIFT                      8
-#define OMAP3430_AUTO_MAILBOXES_MASK                    (1 << 7)
-#define OMAP3430_AUTO_MAILBOXES_SHIFT                   7
-#define OMAP3430_AUTO_OMAPCTRL_MASK                     (1 << 6)
-#define OMAP3430_AUTO_OMAPCTRL_SHIFT                    6
-#define OMAP3430ES1_AUTO_FSHOSTUSB_MASK                 (1 << 5)
-#define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT                5
-#define OMAP3430_AUTO_HSOTGUSB_MASK                     (1 << 4)
-#define OMAP3430_AUTO_HSOTGUSB_SHIFT                    4
-#define OMAP3430ES1_AUTO_D2D_MASK                       (1 << 3)
-#define OMAP3430ES1_AUTO_D2D_SHIFT                      3
-#define OMAP3430_AUTO_SAD2D_MASK                        (1 << 3)
-#define OMAP3430_AUTO_SAD2D_SHIFT                       3
-#define OMAP3430_AUTO_SSI_MASK                          (1 << 0)
-#define OMAP3430_AUTO_SSI_SHIFT                         0
-
-/* CM_AUTOIDLE2_CORE */
-#define OMAP3430_AUTO_PKA_MASK                          (1 << 4)
-#define OMAP3430_AUTO_PKA_SHIFT                         4
-#define OMAP3430_AUTO_AES1_MASK                         (1 << 3)
-#define OMAP3430_AUTO_AES1_SHIFT                        3
-#define OMAP3430_AUTO_RNG_MASK                          (1 << 2)
-#define OMAP3430_AUTO_RNG_SHIFT                         2
-#define OMAP3430_AUTO_SHA11_MASK                        (1 << 1)
-#define OMAP3430_AUTO_SHA11_SHIFT                       1
-#define OMAP3430_AUTO_DES1_MASK                         (1 << 0)
-#define OMAP3430_AUTO_DES1_SHIFT                        0
-
-/* CM_AUTOIDLE3_CORE */
-#define OMAP3430ES2_AUTO_USBHOST                        (1 << 0)
-#define OMAP3430ES2_AUTO_USBHOST_SHIFT                  0
-#define OMAP3430ES2_AUTO_USBTLL                         (1 << 2)
-#define OMAP3430ES2_AUTO_USBTLL_SHIFT                   2
-#define OMAP3430ES2_AUTO_USBTLL_MASK                    (1 << 2)
-#define OMAP3430_AUTO_MAD2D_SHIFT                       3
-#define OMAP3430_AUTO_MAD2D_MASK                        (1 << 3)
-
-/* CM_CLKSEL_CORE */
-#define OMAP3430_CLKSEL_SSI_SHIFT                       8
 #define OMAP3430_CLKSEL_SSI_MASK                        (0xf << 8)
 #define OMAP3430_CLKSEL_GPT11_MASK                      (1 << 7)
-#define OMAP3430_CLKSEL_GPT11_SHIFT                     7
 #define OMAP3430_CLKSEL_GPT10_MASK                      (1 << 6)
-#define OMAP3430_CLKSEL_GPT10_SHIFT                     6
-#define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT              4
 #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK               (0x3 << 4)
 #define OMAP3430_CLKSEL_L4_SHIFT                        2
-#define OMAP3430_CLKSEL_L4_MASK                         (0x3 << 2)
 #define OMAP3430_CLKSEL_L4_WIDTH                        2
 #define OMAP3430_CLKSEL_L3_SHIFT                        0
-#define OMAP3430_CLKSEL_L3_MASK                         (0x3 << 0)
 #define OMAP3430_CLKSEL_L3_WIDTH                        2
-#define OMAP3630_CLKSEL_96M_SHIFT                       12
 #define OMAP3630_CLKSEL_96M_MASK                        (0x3 << 12)
-#define OMAP3630_CLKSEL_96M_WIDTH                       2
-
-/* CM_CLKSTCTRL_CORE */
-#define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT                 4
 #define OMAP3430ES1_CLKTRCTRL_D2D_MASK                  (0x3 << 4)
-#define OMAP3430_CLKTRCTRL_L4_SHIFT                     2
 #define OMAP3430_CLKTRCTRL_L4_MASK                      (0x3 << 2)
-#define OMAP3430_CLKTRCTRL_L3_SHIFT                     0
 #define OMAP3430_CLKTRCTRL_L3_MASK                      (0x3 << 0)
-
-/* CM_CLKSTST_CORE */
-#define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT               2
-#define OMAP3430ES1_CLKACTIVITY_D2D_MASK                (1 << 2)
-#define OMAP3430_CLKACTIVITY_L4_SHIFT                   1
-#define OMAP3430_CLKACTIVITY_L4_MASK                    (1 << 1)
-#define OMAP3430_CLKACTIVITY_L3_SHIFT                   0
-#define OMAP3430_CLKACTIVITY_L3_MASK                    (1 << 0)
-
-/* CM_FCLKEN_GFX */
-#define OMAP3430ES1_EN_3D_MASK                          (1 << 2)
 #define OMAP3430ES1_EN_3D_SHIFT                         2
-#define OMAP3430ES1_EN_2D_MASK                          (1 << 1)
 #define OMAP3430ES1_EN_2D_SHIFT                         1
-
-/* CM_ICLKEN_GFX specific bits */
-
-/* CM_IDLEST_GFX specific bits */
-
-/* CM_CLKSEL_GFX specific bits */
-
-/* CM_SLEEPDEP_GFX specific bits */
-
-/* CM_CLKSTCTRL_GFX */
-#define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT                 0
 #define OMAP3430ES1_CLKTRCTRL_GFX_MASK                  (0x3 << 0)
-
-/* CM_CLKSTST_GFX */
-#define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT               0
-#define OMAP3430ES1_CLKACTIVITY_GFX_MASK                (1 << 0)
-
-/* CM_FCLKEN_SGX */
 #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT          1
-#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK           (1 << 1)
-
-/* CM_IDLEST_SGX */
-#define OMAP3430ES2_ST_SGX_SHIFT                        1
-#define OMAP3430ES2_ST_SGX_MASK                         (1 << 1)
-
-/* CM_ICLKEN_SGX */
 #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT          0
-#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK           (1 << 0)
-
-/* CM_CLKSEL_SGX */
-#define OMAP3430ES2_CLKSEL_SGX_SHIFT                    0
 #define OMAP3430ES2_CLKSEL_SGX_MASK                     (0x7 << 0)
-
-/* CM_CLKSTCTRL_SGX */
-#define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT                 0
 #define OMAP3430ES2_CLKTRCTRL_SGX_MASK                  (0x3 << 0)
-
-/* CM_CLKSTST_SGX */
-#define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT               0
-#define OMAP3430ES2_CLKACTIVITY_SGX_MASK                (1 << 0)
-
-/* CM_FCLKEN_WKUP specific bits */
 #define OMAP3430ES2_EN_USIMOCP_SHIFT                    9
-#define OMAP3430ES2_EN_USIMOCP_MASK                     (1 << 9)
-
-/* CM_ICLKEN_WKUP specific bits */
-#define OMAP3430_EN_WDT1_MASK                           (1 << 4)
 #define OMAP3430_EN_WDT1_SHIFT                          4
-#define OMAP3430_EN_32KSYNC_MASK                        (1 << 2)
 #define OMAP3430_EN_32KSYNC_SHIFT                       2
-
-/* CM_IDLEST_WKUP specific bits */
-#define OMAP3430ES2_ST_USIMOCP_SHIFT                    9
-#define OMAP3430ES2_ST_USIMOCP_MASK                     (1 << 9)
 #define OMAP3430_ST_WDT2_SHIFT                          5
-#define OMAP3430_ST_WDT2_MASK                           (1 << 5)
-#define OMAP3430_ST_WDT1_SHIFT                          4
-#define OMAP3430_ST_WDT1_MASK                           (1 << 4)
 #define OMAP3430_ST_32KSYNC_SHIFT                       2
-#define OMAP3430_ST_32KSYNC_MASK                        (1 << 2)
-
-/* CM_AUTOIDLE_WKUP */
-#define OMAP3430ES2_AUTO_USIMOCP_MASK                   (1 << 9)
-#define OMAP3430ES2_AUTO_USIMOCP_SHIFT                  9
-#define OMAP3430_AUTO_WDT2_MASK                         (1 << 5)
-#define OMAP3430_AUTO_WDT2_SHIFT                        5
-#define OMAP3430_AUTO_WDT1_MASK                         (1 << 4)
-#define OMAP3430_AUTO_WDT1_SHIFT                        4
-#define OMAP3430_AUTO_GPIO1_MASK                        (1 << 3)
-#define OMAP3430_AUTO_GPIO1_SHIFT                       3
-#define OMAP3430_AUTO_32KSYNC_MASK                      (1 << 2)
-#define OMAP3430_AUTO_32KSYNC_SHIFT                     2
-#define OMAP3430_AUTO_GPT12_MASK                        (1 << 1)
-#define OMAP3430_AUTO_GPT12_SHIFT                       1
-#define OMAP3430_AUTO_GPT1_MASK                         (1 << 0)
-#define OMAP3430_AUTO_GPT1_SHIFT                        0
-
-/* CM_CLKSEL_WKUP */
 #define OMAP3430ES2_CLKSEL_USIMOCP_MASK                 (0xf << 3)
 #define OMAP3430_CLKSEL_RM_SHIFT                        1
-#define OMAP3430_CLKSEL_RM_MASK                         (0x3 << 1)
 #define OMAP3430_CLKSEL_RM_WIDTH                        2
-#define OMAP3430_CLKSEL_GPT1_SHIFT                      0
 #define OMAP3430_CLKSEL_GPT1_MASK                       (1 << 0)
-
-/* CM_CLKEN_PLL */
 #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT                 31
 #define OMAP3430_PWRDN_CAM_SHIFT                        30
 #define OMAP3430_PWRDN_DSS1_SHIFT                       29
 #define OMAP3430_PWRDN_TV_SHIFT                         28
 #define OMAP3430_PWRDN_96M_SHIFT                        27
-#define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT             24
-#define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK              (0x3 << 24)
-#define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT              20
 #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK               (0xf << 20)
 #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT        19
-#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK         (1 << 19)
-#define OMAP3430_EN_PERIPH_DPLL_SHIFT                   16
 #define OMAP3430_EN_PERIPH_DPLL_MASK                    (0x7 << 16)
 #define OMAP3430_PWRDN_EMU_CORE_SHIFT                   12
-#define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT               8
-#define OMAP3430_CORE_DPLL_RAMPTIME_MASK                (0x3 << 8)
-#define OMAP3430_CORE_DPLL_FREQSEL_SHIFT                4
 #define OMAP3430_CORE_DPLL_FREQSEL_MASK                 (0xf << 4)
 #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT          3
-#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK           (1 << 3)
-#define OMAP3430_EN_CORE_DPLL_SHIFT                     0
 #define OMAP3430_EN_CORE_DPLL_MASK                      (0x7 << 0)
-
-/* CM_CLKEN2_PLL */
-#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT        10
-#define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK          (0x3 << 8)
-#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT          4
 #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK           (0xf << 4)
 #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT    3
-#define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT               0
 #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK                (0x7 << 0)
-
-/* CM_IDLEST_CKGEN */
-#define OMAP3430_ST_54M_CLK_MASK                        (1 << 5)
-#define OMAP3430_ST_12M_CLK_MASK                        (1 << 4)
-#define OMAP3430_ST_48M_CLK_MASK                        (1 << 3)
-#define OMAP3430_ST_96M_CLK_MASK                        (1 << 2)
-#define OMAP3430_ST_PERIPH_CLK_SHIFT                    1
 #define OMAP3430_ST_PERIPH_CLK_MASK                     (1 << 1)
-#define OMAP3430_ST_CORE_CLK_SHIFT                      0
 #define OMAP3430_ST_CORE_CLK_MASK                       (1 << 0)
-
-/* CM_IDLEST2_CKGEN */
-#define OMAP3430ES2_ST_USIM_CLK_SHIFT                   2
-#define OMAP3430ES2_ST_USIM_CLK_MASK                    (1 << 2)
-#define OMAP3430ES2_ST_120M_CLK_SHIFT                   1
-#define OMAP3430ES2_ST_120M_CLK_MASK                    (1 << 1)
-#define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT                0
 #define OMAP3430ES2_ST_PERIPH2_CLK_MASK                 (1 << 0)
-
-/* CM_AUTOIDLE_PLL */
-#define OMAP3430_AUTO_PERIPH_DPLL_SHIFT                 3
 #define OMAP3430_AUTO_PERIPH_DPLL_MASK                  (0x7 << 3)
-#define OMAP3430_AUTO_CORE_DPLL_SHIFT                   0
 #define OMAP3430_AUTO_CORE_DPLL_MASK                    (0x7 << 0)
-
-/* CM_AUTOIDLE2_PLL */
-#define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT             0
 #define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK              (0x7 << 0)
-
-/* CM_CLKSEL1_PLL */
-/* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
 #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT             27
-#define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK              (0x1f << 27)
 #define OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH             5
-#define OMAP3430_CORE_DPLL_MULT_SHIFT                   16
 #define OMAP3430_CORE_DPLL_MULT_MASK                    (0x7ff << 16)
-#define OMAP3430_CORE_DPLL_DIV_SHIFT                    8
 #define OMAP3430_CORE_DPLL_DIV_MASK                     (0x7f << 8)
 #define OMAP3430_SOURCE_96M_SHIFT                       6
-#define OMAP3430_SOURCE_96M_MASK                        (1 << 6)
 #define OMAP3430_SOURCE_96M_WIDTH                       1
 #define OMAP3430_SOURCE_54M_SHIFT                       5
-#define OMAP3430_SOURCE_54M_MASK                        (1 << 5)
 #define OMAP3430_SOURCE_54M_WIDTH                       1
-#define OMAP3430_SOURCE_48M_SHIFT                       3
 #define OMAP3430_SOURCE_48M_MASK                        (1 << 3)
-
-/* CM_CLKSEL2_PLL */
-#define OMAP3430_PERIPH_DPLL_MULT_SHIFT                 8
 #define OMAP3430_PERIPH_DPLL_MULT_MASK                  (0x7ff << 8)
 #define OMAP3630_PERIPH_DPLL_MULT_MASK                  (0xfff << 8)
-#define OMAP3430_PERIPH_DPLL_DIV_SHIFT                  0
 #define OMAP3430_PERIPH_DPLL_DIV_MASK                   (0x7f << 0)
-#define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT              21
 #define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK               (0x7 << 21)
-#define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT               24
 #define OMAP3630_PERIPH_DPLL_SD_DIV_MASK                (0xff << 24)
-
-/* CM_CLKSEL3_PLL */
 #define OMAP3430_DIV_96M_SHIFT                          0
-#define OMAP3430_DIV_96M_MASK                           (0x1f << 0)
-#define OMAP3430_DIV_96M_WIDTH                          5
-#define OMAP3630_DIV_96M_MASK                           (0x3f << 0)
 #define OMAP3630_DIV_96M_WIDTH                          6
-
-/* CM_CLKSEL4_PLL */
-#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT             8
 #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK              (0x7ff << 8)
-#define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT              0
 #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK               (0x7f << 0)
-
-/* CM_CLKSEL5_PLL */
 #define OMAP3430ES2_DIV_120M_SHIFT                      0
-#define OMAP3430ES2_DIV_120M_MASK                       (0x1f << 0)
 #define OMAP3430ES2_DIV_120M_WIDTH                      5
-
-/* CM_CLKOUT_CTRL */
 #define OMAP3430_CLKOUT2_EN_SHIFT                       7
-#define OMAP3430_CLKOUT2_EN_MASK                        (1 << 7)
 #define OMAP3430_CLKOUT2_DIV_SHIFT                      3
-#define OMAP3430_CLKOUT2_DIV_MASK                       (0x7 << 3)
 #define OMAP3430_CLKOUT2_DIV_WIDTH                      3
-#define OMAP3430_CLKOUT2SOURCE_SHIFT                    0
 #define OMAP3430_CLKOUT2SOURCE_MASK                     (0x3 << 0)
-
-/* CM_FCLKEN_DSS */
-#define OMAP3430_EN_TV_MASK                             (1 << 2)
 #define OMAP3430_EN_TV_SHIFT                            2
-#define OMAP3430_EN_DSS2_MASK                           (1 << 1)
 #define OMAP3430_EN_DSS2_SHIFT                          1
-#define OMAP3430_EN_DSS1_MASK                           (1 << 0)
 #define OMAP3430_EN_DSS1_SHIFT                          0
-
-/* CM_ICLKEN_DSS */
-#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK              (1 << 0)
 #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT             0
-
-/* CM_IDLEST_DSS */
 #define OMAP3430ES2_ST_DSS_IDLE_SHIFT                   1
-#define OMAP3430ES2_ST_DSS_IDLE_MASK                    (1 << 1)
 #define OMAP3430ES2_ST_DSS_STDBY_SHIFT                  0
-#define OMAP3430ES2_ST_DSS_STDBY_MASK                   (1 << 0)
 #define OMAP3430ES1_ST_DSS_SHIFT                        0
-#define OMAP3430ES1_ST_DSS_MASK                         (1 << 0)
-
-/* CM_AUTOIDLE_DSS */
-#define OMAP3430_AUTO_DSS_MASK                          (1 << 0)
-#define OMAP3430_AUTO_DSS_SHIFT                         0
-
-/* CM_CLKSEL_DSS */
 #define OMAP3430_CLKSEL_TV_SHIFT                        8
-#define OMAP3430_CLKSEL_TV_MASK                         (0x1f << 8)
-#define OMAP3430_CLKSEL_TV_WIDTH                        5
-#define OMAP3630_CLKSEL_TV_MASK                         (0x3f << 8)
 #define OMAP3630_CLKSEL_TV_WIDTH                        6
 #define OMAP3430_CLKSEL_DSS1_SHIFT                      0
-#define OMAP3430_CLKSEL_DSS1_MASK                       (0x1f << 0)
-#define OMAP3430_CLKSEL_DSS1_WIDTH                      5
-#define OMAP3630_CLKSEL_DSS1_MASK                       (0x3f << 0)
 #define OMAP3630_CLKSEL_DSS1_WIDTH                      6
-
-/* CM_SLEEPDEP_DSS specific bits */
-
-/* CM_CLKSTCTRL_DSS */
-#define OMAP3430_CLKTRCTRL_DSS_SHIFT                    0
 #define OMAP3430_CLKTRCTRL_DSS_MASK                     (0x3 << 0)
-
-/* CM_CLKSTST_DSS */
-#define OMAP3430_CLKACTIVITY_DSS_SHIFT                  0
-#define OMAP3430_CLKACTIVITY_DSS_MASK                   (1 << 0)
-
-/* CM_FCLKEN_CAM specific bits */
-#define OMAP3430_EN_CSI2_MASK                           (1 << 1)
 #define OMAP3430_EN_CSI2_SHIFT                          1
-
-/* CM_ICLKEN_CAM specific bits */
-
-/* CM_IDLEST_CAM */
-#define OMAP3430_ST_CAM_MASK                            (1 << 0)
-
-/* CM_AUTOIDLE_CAM */
-#define OMAP3430_AUTO_CAM_MASK                          (1 << 0)
-#define OMAP3430_AUTO_CAM_SHIFT                         0
-
-/* CM_CLKSEL_CAM */
 #define OMAP3430_CLKSEL_CAM_SHIFT                       0
-#define OMAP3430_CLKSEL_CAM_MASK                        (0x1f << 0)
-#define OMAP3430_CLKSEL_CAM_WIDTH                       5
-#define OMAP3630_CLKSEL_CAM_MASK                        (0x3f << 0)
 #define OMAP3630_CLKSEL_CAM_WIDTH                       6
-
-/* CM_SLEEPDEP_CAM specific bits */
-
-/* CM_CLKSTCTRL_CAM */
-#define OMAP3430_CLKTRCTRL_CAM_SHIFT                    0
 #define OMAP3430_CLKTRCTRL_CAM_MASK                     (0x3 << 0)
-
-/* CM_CLKSTST_CAM */
-#define OMAP3430_CLKACTIVITY_CAM_SHIFT                  0
-#define OMAP3430_CLKACTIVITY_CAM_MASK                   (1 << 0)
-
-/* CM_FCLKEN_PER specific bits */
-
-/* CM_ICLKEN_PER specific bits */
-
-/* CM_IDLEST_PER */
-#define OMAP3430_ST_WDT3_SHIFT                          12
-#define OMAP3430_ST_WDT3_MASK                           (1 << 12)
 #define OMAP3430_ST_MCBSP4_SHIFT                        2
-#define OMAP3430_ST_MCBSP4_MASK                         (1 << 2)
 #define OMAP3430_ST_MCBSP3_SHIFT                        1
-#define OMAP3430_ST_MCBSP3_MASK                         (1 << 1)
 #define OMAP3430_ST_MCBSP2_SHIFT                        0
-#define OMAP3430_ST_MCBSP2_MASK                         (1 << 0)
-
-/* CM_AUTOIDLE_PER */
-#define OMAP3630_AUTO_UART4_MASK                        (1 << 18)
-#define OMAP3630_AUTO_UART4_SHIFT                       18
-#define OMAP3430_AUTO_GPIO6_MASK                        (1 << 17)
-#define OMAP3430_AUTO_GPIO6_SHIFT                       17
-#define OMAP3430_AUTO_GPIO5_MASK                        (1 << 16)
-#define OMAP3430_AUTO_GPIO5_SHIFT                       16
-#define OMAP3430_AUTO_GPIO4_MASK                        (1 << 15)
-#define OMAP3430_AUTO_GPIO4_SHIFT                       15
-#define OMAP3430_AUTO_GPIO3_MASK                        (1 << 14)
-#define OMAP3430_AUTO_GPIO3_SHIFT                       14
-#define OMAP3430_AUTO_GPIO2_MASK                        (1 << 13)
-#define OMAP3430_AUTO_GPIO2_SHIFT                       13
-#define OMAP3430_AUTO_WDT3_MASK                         (1 << 12)
-#define OMAP3430_AUTO_WDT3_SHIFT                        12
-#define OMAP3430_AUTO_UART3_MASK                        (1 << 11)
-#define OMAP3430_AUTO_UART3_SHIFT                       11
-#define OMAP3430_AUTO_GPT9_MASK                         (1 << 10)
-#define OMAP3430_AUTO_GPT9_SHIFT                        10
-#define OMAP3430_AUTO_GPT8_MASK                         (1 << 9)
-#define OMAP3430_AUTO_GPT8_SHIFT                        9
-#define OMAP3430_AUTO_GPT7_MASK                         (1 << 8)
-#define OMAP3430_AUTO_GPT7_SHIFT                        8
-#define OMAP3430_AUTO_GPT6_MASK                         (1 << 7)
-#define OMAP3430_AUTO_GPT6_SHIFT                        7
-#define OMAP3430_AUTO_GPT5_MASK                         (1 << 6)
-#define OMAP3430_AUTO_GPT5_SHIFT                        6
-#define OMAP3430_AUTO_GPT4_MASK                         (1 << 5)
-#define OMAP3430_AUTO_GPT4_SHIFT                        5
-#define OMAP3430_AUTO_GPT3_MASK                         (1 << 4)
-#define OMAP3430_AUTO_GPT3_SHIFT                        4
-#define OMAP3430_AUTO_GPT2_MASK                         (1 << 3)
-#define OMAP3430_AUTO_GPT2_SHIFT                        3
-#define OMAP3430_AUTO_MCBSP4_MASK                       (1 << 2)
-#define OMAP3430_AUTO_MCBSP4_SHIFT                      2
-#define OMAP3430_AUTO_MCBSP3_MASK                       (1 << 1)
-#define OMAP3430_AUTO_MCBSP3_SHIFT                      1
-#define OMAP3430_AUTO_MCBSP2_MASK                       (1 << 0)
-#define OMAP3430_AUTO_MCBSP2_SHIFT                      0
-
-/* CM_CLKSEL_PER */
 #define OMAP3430_CLKSEL_GPT9_MASK                       (1 << 7)
-#define OMAP3430_CLKSEL_GPT9_SHIFT                      7
 #define OMAP3430_CLKSEL_GPT8_MASK                       (1 << 6)
-#define OMAP3430_CLKSEL_GPT8_SHIFT                      6
 #define OMAP3430_CLKSEL_GPT7_MASK                       (1 << 5)
-#define OMAP3430_CLKSEL_GPT7_SHIFT                      5
 #define OMAP3430_CLKSEL_GPT6_MASK                       (1 << 4)
-#define OMAP3430_CLKSEL_GPT6_SHIFT                      4
 #define OMAP3430_CLKSEL_GPT5_MASK                       (1 << 3)
-#define OMAP3430_CLKSEL_GPT5_SHIFT                      3
 #define OMAP3430_CLKSEL_GPT4_MASK                       (1 << 2)
-#define OMAP3430_CLKSEL_GPT4_SHIFT                      2
 #define OMAP3430_CLKSEL_GPT3_MASK                       (1 << 1)
-#define OMAP3430_CLKSEL_GPT3_SHIFT                      1
 #define OMAP3430_CLKSEL_GPT2_MASK                       (1 << 0)
-#define OMAP3430_CLKSEL_GPT2_SHIFT                      0
-
-/* CM_SLEEPDEP_PER specific bits */
-#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK           (1 << 2)
-
-/* CM_CLKSTCTRL_PER */
-#define OMAP3430_CLKTRCTRL_PER_SHIFT                    0
 #define OMAP3430_CLKTRCTRL_PER_MASK                     (0x3 << 0)
-
-/* CM_CLKSTST_PER */
-#define OMAP3430_CLKACTIVITY_PER_SHIFT                  0
-#define OMAP3430_CLKACTIVITY_PER_MASK                   (1 << 0)
-
-/* CM_CLKSEL1_EMU */
 #define OMAP3430_DIV_DPLL4_SHIFT                        24
-#define OMAP3430_DIV_DPLL4_MASK                         (0x1f << 24)
-#define OMAP3430_DIV_DPLL4_WIDTH                        5
-#define OMAP3630_DIV_DPLL4_MASK                         (0x3f << 24)
 #define OMAP3630_DIV_DPLL4_WIDTH                        6
 #define OMAP3430_DIV_DPLL3_SHIFT                        16
-#define OMAP3430_DIV_DPLL3_MASK                         (0x1f << 16)
 #define OMAP3430_DIV_DPLL3_WIDTH                        5
 #define OMAP3430_CLKSEL_TRACECLK_SHIFT                  11
-#define OMAP3430_CLKSEL_TRACECLK_MASK                   (0x7 << 11)
 #define OMAP3430_CLKSEL_TRACECLK_WIDTH                  3
 #define OMAP3430_CLKSEL_PCLK_SHIFT                      8
-#define OMAP3430_CLKSEL_PCLK_MASK                       (0x7 << 8)
 #define OMAP3430_CLKSEL_PCLK_WIDTH                      3
 #define OMAP3430_CLKSEL_PCLKX2_SHIFT                    6
-#define OMAP3430_CLKSEL_PCLKX2_MASK                     (0x3 << 6)
 #define OMAP3430_CLKSEL_PCLKX2_WIDTH                    2
 #define OMAP3430_CLKSEL_ATCLK_SHIFT                     4
-#define OMAP3430_CLKSEL_ATCLK_MASK                      (0x3 << 4)
 #define OMAP3430_CLKSEL_ATCLK_WIDTH                     2
 #define OMAP3430_TRACE_MUX_CTRL_SHIFT                   2
-#define OMAP3430_TRACE_MUX_CTRL_MASK                    (0x3 << 2)
 #define OMAP3430_TRACE_MUX_CTRL_WIDTH                   2
-#define OMAP3430_MUX_CTRL_SHIFT                         0
 #define OMAP3430_MUX_CTRL_MASK                          (0x3 << 0)
-#define OMAP3430_MUX_CTRL_WIDTH                         2
-
-/* CM_CLKSTCTRL_EMU */
-#define OMAP3430_CLKTRCTRL_EMU_SHIFT                    0
 #define OMAP3430_CLKTRCTRL_EMU_MASK                     (0x3 << 0)
-
-/* CM_CLKSTST_EMU */
-#define OMAP3430_CLKACTIVITY_EMU_SHIFT                  0
-#define OMAP3430_CLKACTIVITY_EMU_MASK                   (1 << 0)
-
-/* CM_CLKSEL2_EMU specific bits */
-#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT               8
-#define OMAP3430_CORE_DPLL_EMU_MULT_MASK                (0x7ff << 8)
-#define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT                0
-#define OMAP3430_CORE_DPLL_EMU_DIV_MASK                 (0x7f << 0)
-
-/* CM_CLKSEL3_EMU specific bits */
-#define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT             8
-#define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK              (0x7ff << 8)
-#define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT              0
-#define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK               (0x7f << 0)
-
-/* CM_POLCTRL */
-#define OMAP3430_CLKOUT2_POL_MASK                       (1 << 0)
-
-/* CM_IDLEST_NEON */
-#define OMAP3430_ST_NEON_MASK                           (1 << 0)
-
-/* CM_CLKSTCTRL_NEON */
-#define OMAP3430_CLKTRCTRL_NEON_SHIFT                   0
 #define OMAP3430_CLKTRCTRL_NEON_MASK                    (0x3 << 0)
-
-/* CM_FCLKEN_USBHOST */
 #define OMAP3430ES2_EN_USBHOST2_SHIFT                   1
-#define OMAP3430ES2_EN_USBHOST2_MASK                    (1 << 1)
 #define OMAP3430ES2_EN_USBHOST1_SHIFT                   0
-#define OMAP3430ES2_EN_USBHOST1_MASK                    (1 << 0)
-
-/* CM_ICLKEN_USBHOST */
 #define OMAP3430ES2_EN_USBHOST_SHIFT                    0
-#define OMAP3430ES2_EN_USBHOST_MASK                     (1 << 0)
-
-/* CM_IDLEST_USBHOST */
 #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT               1
-#define OMAP3430ES2_ST_USBHOST_IDLE_MASK                (1 << 1)
 #define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT              0
-#define OMAP3430ES2_ST_USBHOST_STDBY_MASK               (1 << 0)
-
-/* CM_AUTOIDLE_USBHOST */
-#define OMAP3430ES2_AUTO_USBHOST_SHIFT                  0
-#define OMAP3430ES2_AUTO_USBHOST_MASK                   (1 << 0)
-
-/* CM_SLEEPDEP_USBHOST */
-#define OMAP3430ES2_EN_MPU_SHIFT                        1
-#define OMAP3430ES2_EN_MPU_MASK                         (1 << 1)
-#define OMAP3430ES2_EN_IVA2_SHIFT                       2
-#define OMAP3430ES2_EN_IVA2_MASK                        (1 << 2)
-
-/* CM_CLKSTCTRL_USBHOST */
-#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT             0
 #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK              (3 << 0)
-
-/* CM_CLKSTST_USBHOST */
-#define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT           0
-#define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK            (1 << 0)
-
-/*
- *
- */
-
-/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */
 #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO         0x0
 #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP          0x1
 #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP         0x2
 #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO          0x3
-
-
 #endif
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h
index 4c6c2f7de65b..4dbbd99b6e1e 100644
--- a/arch/arm/mach-omap2/cm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-44xx.h
@@ -22,1683 +22,125 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
 
-/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
-#define OMAP4430_ABE_DYNDEP_SHIFT                               3
-#define OMAP4430_ABE_DYNDEP_WIDTH                               0x1
-#define OMAP4430_ABE_DYNDEP_MASK                                (1 << 3)
-
-/*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
- * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
- */
 #define OMAP4430_ABE_STATDEP_SHIFT                              3
-#define OMAP4430_ABE_STATDEP_WIDTH                              0x1
-#define OMAP4430_ABE_STATDEP_MASK                               (1 << 3)
-
-/* Used by CM_L4CFG_DYNAMICDEP */
-#define OMAP4430_ALWONCORE_DYNDEP_SHIFT                         16
-#define OMAP4430_ALWONCORE_DYNDEP_WIDTH                         0x1
-#define OMAP4430_ALWONCORE_DYNDEP_MASK                          (1 << 16)
-
-/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
-#define OMAP4430_ALWONCORE_STATDEP_SHIFT                        16
-#define OMAP4430_ALWONCORE_STATDEP_WIDTH                        0x1
-#define OMAP4430_ALWONCORE_STATDEP_MASK                         (1 << 16)
-
-/*
- * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
- * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU,
- * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
- */
-#define OMAP4430_AUTO_DPLL_MODE_SHIFT                           0
-#define OMAP4430_AUTO_DPLL_MODE_WIDTH                           0x3
 #define OMAP4430_AUTO_DPLL_MODE_MASK                            (0x7 << 0)
-
-/* Used by CM_L4CFG_DYNAMICDEP */
-#define OMAP4430_CEFUSE_DYNDEP_SHIFT                            17
-#define OMAP4430_CEFUSE_DYNDEP_WIDTH                            0x1
-#define OMAP4430_CEFUSE_DYNDEP_MASK                             (1 << 17)
-
-/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
-#define OMAP4430_CEFUSE_STATDEP_SHIFT                           17
-#define OMAP4430_CEFUSE_STATDEP_WIDTH                           0x1
-#define OMAP4430_CEFUSE_STATDEP_MASK                            (1 << 17)
-
-/* Used by CM1_ABE_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT                13
-#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_WIDTH                0x1
-#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK                 (1 << 13)
-
-/* Used by CM1_ABE_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT            12
-#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_WIDTH            0x1
-#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK             (1 << 12)
-
-/* Used by CM_WKUP_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT                   9
-#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_WIDTH                   0x1
-#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK                    (1 << 9)
-
-/* Used by CM1_ABE_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT                   11
-#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_WIDTH                   0x1
-#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK                    (1 << 11)
-
-/* Used by CM1_ABE_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT                   8
-#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_WIDTH                   0x1
-#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK                    (1 << 8)
-
-/* Used by CM_MEMIF_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT                11
-#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_WIDTH                0x1
-#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK                 (1 << 11)
-
-/* Used by CM_MEMIF_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT               12
-#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_WIDTH               0x1
-#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK                (1 << 12)
-
-/* Used by CM_MEMIF_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT               13
-#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_WIDTH               0x1
-#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK                (1 << 13)
-
-/* Used by CM_CAM_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT            9
-#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_WIDTH            0x1
-#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK             (1 << 9)
-
-/* Used by CM_ALWON_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT         12
-#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_WIDTH         0x1
-#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK          (1 << 12)
-
-/* Used by CM_EMU_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT            9
-#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_WIDTH            0x1
-#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK             (1 << 9)
-
-/* Used by CM_L4CFG_CLKSTCTRL */
-#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT                9
-#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_WIDTH                0x1
-#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK                 (1 << 9)
-
-/* Used by CM_CEFUSE_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT           9
-#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH           0x1
-#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK            (1 << 9)
-
-/* Used by CM_MEMIF_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT                      9
-#define OMAP4430_CLKACTIVITY_DLL_CLK_WIDTH                      0x1
-#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK                       (1 << 9)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT                  9
-#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_WIDTH                  0x1
-#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK                   (1 << 9)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT                  10
-#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_WIDTH                  0x1
-#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK                   (1 << 10)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT                   11
-#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_WIDTH                   0x1
-#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK                    (1 << 11)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT                   12
-#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_WIDTH                   0x1
-#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK                    (1 << 12)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT                   13
-#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_WIDTH                   0x1
-#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK                    (1 << 13)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT                   14
-#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_WIDTH                   0x1
-#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK                    (1 << 14)
-
-/* Used by CM_DSS_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT            10
-#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_WIDTH            0x1
-#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK             (1 << 10)
-
-/* Used by CM_DSS_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT                     9
-#define OMAP4430_CLKACTIVITY_DSS_FCLK_WIDTH                     0x1
-#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK                      (1 << 9)
-
-/* Used by CM_DUCATI_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT                  8
-#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_WIDTH                  0x1
-#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK                   (1 << 8)
-
-/* Used by CM_EMU_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT                  8
-#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_WIDTH                  0x1
-#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK                   (1 << 8)
-
-/* Used by CM_CAM_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT                   10
-#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_WIDTH                   0x1
-#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK                    (1 << 10)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT               15
-#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_WIDTH               0x1
-#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK                (1 << 15)
-
-/* Used by CM1_ABE_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT               10
-#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH               0x1
-#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK                (1 << 10)
-
-/* Used by CM_DSS_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT         11
-#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_WIDTH         0x1
-#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK          (1 << 11)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT           20
-#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH           0x1
-#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK            (1 << 20)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT                26
-#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH                0x1
-#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK                 (1 << 26)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT           21
-#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH           0x1
-#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK            (1 << 21)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT                27
-#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH                0x1
-#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK                 (1 << 27)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT              13
-#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_WIDTH              0x1
-#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK               (1 << 13)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT               12
-#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_WIDTH               0x1
-#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK                (1 << 12)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT            28
-#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_WIDTH            0x1
-#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK             (1 << 28)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT            29
-#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_WIDTH            0x1
-#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK             (1 << 29)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT               11
-#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_WIDTH               0x1
-#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK                (1 << 11)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT               16
-#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_WIDTH               0x1
-#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK                (1 << 16)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT            17
-#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_WIDTH            0x1
-#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK             (1 << 17)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT            18
-#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_WIDTH            0x1
-#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK             (1 << 18)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT            19
-#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_WIDTH            0x1
-#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK             (1 << 19)
-
-/* Used by CM_CAM_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT                     8
-#define OMAP4430_CLKACTIVITY_ISS_GCLK_WIDTH                     0x1
-#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK                      (1 << 8)
-
-/* Used by CM_IVAHD_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT               8
-#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_WIDTH               0x1
-#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK                (1 << 8)
-
-/* Used by CM_D2D_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT               10
-#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_WIDTH               0x1
-#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK                (1 << 10)
-
-/* Used by CM_L3_1_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT                   8
-#define OMAP4430_CLKACTIVITY_L3_1_GICLK_WIDTH                   0x1
-#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK                    (1 << 8)
-
-/* Used by CM_L3_2_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT                   8
-#define OMAP4430_CLKACTIVITY_L3_2_GICLK_WIDTH                   0x1
-#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK                    (1 << 8)
-
-/* Used by CM_D2D_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_WIDTH                 0x1
-#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK                  (1 << 8)
-
-/* Used by CM_SDMA_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_WIDTH                 0x1
-#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK                  (1 << 8)
-
-/* Used by CM_DSS_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_WIDTH                 0x1
-#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK                  (1 << 8)
-
-/* Used by CM_MEMIF_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT                8
-#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_WIDTH                0x1
-#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK                 (1 << 8)
-
-/* Used by CM_GFX_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_WIDTH                 0x1
-#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK                  (1 << 8)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT                8
-#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_WIDTH                0x1
-#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK                 (1 << 8)
-
-/* Used by CM_L3INSTR_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT               8
-#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_WIDTH               0x1
-#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK                (1 << 8)
-
-/* Used by CM_L4SEC_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT              8
-#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_WIDTH              0x1
-#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK               (1 << 8)
-
-/* Used by CM_ALWON_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT                   8
-#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_WIDTH                   0x1
-#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK                    (1 << 8)
-
-/* Used by CM_CEFUSE_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT              8
-#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH              0x1
-#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK               (1 << 8)
-
-/* Used by CM_L4CFG_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_WIDTH                 0x1
-#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK                  (1 << 8)
-
-/* Used by CM_D2D_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT                 9
-#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_WIDTH                 0x1
-#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK                  (1 << 9)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT                9
-#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_WIDTH                0x1
-#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK                 (1 << 9)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_WIDTH                 0x1
-#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK                  (1 << 8)
-
-/* Used by CM_L4SEC_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT              9
-#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_WIDTH              0x1
-#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK               (1 << 9)
-
-/* Used by CM_WKUP_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT                12
-#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_WIDTH                0x1
-#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK                 (1 << 12)
-
-/* Used by CM_MPU_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_WIDTH                 0x1
-#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK                  (1 << 8)
-
-/* Used by CM1_ABE_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT                9
-#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_WIDTH                0x1
-#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK                 (1 << 9)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT               16
-#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_WIDTH               0x1
-#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK                (1 << 16)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT                17
-#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_WIDTH                0x1
-#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK                 (1 << 17)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT                18
-#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_WIDTH                0x1
-#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK                 (1 << 18)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT                19
-#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_WIDTH                0x1
-#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK                 (1 << 19)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT            25
-#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_WIDTH            0x1
-#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK             (1 << 25)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT             20
-#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_WIDTH             0x1
-#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK              (1 << 20)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT             21
-#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK              (1 << 21)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT             22
-#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_WIDTH             0x1
-#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK              (1 << 22)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT                24
-#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_WIDTH                0x1
-#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK                 (1 << 24)
-
-/* Used by CM_MEMIF_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT                 10
-#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_WIDTH                 0x1
-#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK                  (1 << 10)
-
-/* Used by CM_GFX_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT                    9
-#define OMAP4430_CLKACTIVITY_SGX_GFCLK_WIDTH                    0x1
-#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK                     (1 << 9)
-
-/* Used by CM_ALWON_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT               11
-#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_WIDTH               0x1
-#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK                (1 << 11)
-
-/* Used by CM_ALWON_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT                10
-#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_WIDTH                0x1
-#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK                 (1 << 10)
-
-/* Used by CM_ALWON_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT                9
-#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_WIDTH                0x1
-#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK                 (1 << 9)
-
-/* Used by CM_WKUP_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT                      8
-#define OMAP4430_CLKACTIVITY_SYS_CLK_WIDTH                      0x1
-#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK                       (1 << 8)
-
-/* Used by CM_TESLA_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT               8
-#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_WIDTH               0x1
-#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK                (1 << 8)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT                22
-#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH                0x1
-#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK                 (1 << 22)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT                23
-#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH                0x1
-#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK                 (1 << 23)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT                24
-#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH                0x1
-#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK                 (1 << 24)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT              10
-#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_WIDTH              0x1
-#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK               (1 << 10)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT                 14
-#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_WIDTH                 0x1
-#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK                  (1 << 14)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT              15
-#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH              0x1
-#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK               (1 << 15)
-
-/* Used by CM_WKUP_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT                   10
-#define OMAP4430_CLKACTIVITY_USIM_GFCLK_WIDTH                   0x1
-#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK                    (1 << 10)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT                30
-#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH                0x1
-#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK                 (1 << 30)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT              25
-#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH              0x1
-#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK               (1 << 25)
-
-/* Used by CM_WKUP_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT               11
-#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_WIDTH               0x1
-#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK                (1 << 11)
-
-/* Used by CM_WKUP_CLKSTCTRL */
-#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT                13
-#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_WIDTH                0x1
-#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK                 (1 << 13)
-
-/*
- * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL,
- * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
- * CM_L3INIT_MMC2_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
- * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
- * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
- * CM_L4PER_DMTIMER9_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL
- */
 #define OMAP4430_CLKSEL_SHIFT                                   24
 #define OMAP4430_CLKSEL_WIDTH                                   0x1
 #define OMAP4430_CLKSEL_MASK                                    (1 << 24)
-
-/*
- * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL,
- * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL
- */
 #define OMAP4430_CLKSEL_0_0_SHIFT                               0
 #define OMAP4430_CLKSEL_0_0_WIDTH                               0x1
-#define OMAP4430_CLKSEL_0_0_MASK                                (1 << 0)
-
-/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
 #define OMAP4430_CLKSEL_0_1_SHIFT                               0
 #define OMAP4430_CLKSEL_0_1_WIDTH                               0x2
-#define OMAP4430_CLKSEL_0_1_MASK                                (0x3 << 0)
-
-/* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */
 #define OMAP4430_CLKSEL_24_25_SHIFT                             24
 #define OMAP4430_CLKSEL_24_25_WIDTH                             0x2
-#define OMAP4430_CLKSEL_24_25_MASK                              (0x3 << 24)
-
-/* Used by CM_L3INIT_USB_OTG_CLKCTRL */
 #define OMAP4430_CLKSEL_60M_SHIFT                               24
 #define OMAP4430_CLKSEL_60M_WIDTH                               0x1
-#define OMAP4430_CLKSEL_60M_MASK                                (1 << 24)
-
-/* Used by CM_MPU_MPU_CLKCTRL */
-#define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT                      25
-#define OMAP4460_CLKSEL_ABE_DIV_MODE_WIDTH                      0x1
-#define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK                       (1 << 25)
-
-/* Used by CM1_ABE_AESS_CLKCTRL */
 #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT                         24
 #define OMAP4430_CLKSEL_AESS_FCLK_WIDTH                         0x1
-#define OMAP4430_CLKSEL_AESS_FCLK_MASK                          (1 << 24)
-
-/* Used by CM_CLKSEL_CORE */
 #define OMAP4430_CLKSEL_CORE_SHIFT                              0
 #define OMAP4430_CLKSEL_CORE_WIDTH                              0x1
-#define OMAP4430_CLKSEL_CORE_MASK                               (1 << 0)
-
-/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
-#define OMAP4430_CLKSEL_CORE_1_1_SHIFT                          1
-#define OMAP4430_CLKSEL_CORE_1_1_WIDTH                          0x1
-#define OMAP4430_CLKSEL_CORE_1_1_MASK                           (1 << 1)
-
-/* Used by CM_WKUP_USIM_CLKCTRL */
 #define OMAP4430_CLKSEL_DIV_SHIFT                               24
 #define OMAP4430_CLKSEL_DIV_WIDTH                               0x1
-#define OMAP4430_CLKSEL_DIV_MASK                                (1 << 24)
-
-/* Used by CM_MPU_MPU_CLKCTRL */
-#define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT                     24
-#define OMAP4460_CLKSEL_EMIF_DIV_MODE_WIDTH                     0x1
-#define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK                      (1 << 24)
-
-/* Used by CM_CAM_FDIF_CLKCTRL */
 #define OMAP4430_CLKSEL_FCLK_SHIFT                              24
 #define OMAP4430_CLKSEL_FCLK_WIDTH                              0x2
-#define OMAP4430_CLKSEL_FCLK_MASK                               (0x3 << 24)
-
-/* Used by CM_L4PER_MCBSP4_CLKCTRL */
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT                   25
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH                   0x1
-#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK                    (1 << 25)
-
-/*
- * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL,
- * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
- * CM1_ABE_MCBSP3_CLKCTRL
- */
-#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT      26
-#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_WIDTH      0x2
-#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK       (0x3 << 26)
-
-/* Used by CM_CLKSEL_CORE */
 #define OMAP4430_CLKSEL_L3_SHIFT                                4
 #define OMAP4430_CLKSEL_L3_WIDTH                                0x1
-#define OMAP4430_CLKSEL_L3_MASK                                 (1 << 4)
-
-/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
-#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT                         2
-#define OMAP4430_CLKSEL_L3_SHADOW_WIDTH                         0x1
-#define OMAP4430_CLKSEL_L3_SHADOW_MASK                          (1 << 2)
-
-/* Used by CM_CLKSEL_CORE */
 #define OMAP4430_CLKSEL_L4_SHIFT                                8
 #define OMAP4430_CLKSEL_L4_WIDTH                                0x1
-#define OMAP4430_CLKSEL_L4_MASK                                 (1 << 8)
-
-/* Used by CM_CLKSEL_ABE */
 #define OMAP4430_CLKSEL_OPP_SHIFT                               0
 #define OMAP4430_CLKSEL_OPP_WIDTH                               0x2
-#define OMAP4430_CLKSEL_OPP_MASK                                (0x3 << 0)
-
-/* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT                       27
 #define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH                       0x3
-#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK                        (0x7 << 27)
-
-/* Used by CM_EMU_DEBUGSS_CLKCTRL */
-#define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT                     24
-#define OMAP4430_CLKSEL_PMD_TRACE_CLK_WIDTH                     0x3
 #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK                      (0x7 << 24)
-
-/* Used by CM_GFX_GFX_CLKCTRL */
-#define OMAP4430_CLKSEL_SGX_FCLK_SHIFT                          24
-#define OMAP4430_CLKSEL_SGX_FCLK_WIDTH                          0x1
 #define OMAP4430_CLKSEL_SGX_FCLK_MASK                           (1 << 24)
-
-/*
- * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL,
- * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL
- */
-#define OMAP4430_CLKSEL_SOURCE_SHIFT                            24
-#define OMAP4430_CLKSEL_SOURCE_WIDTH                            0x2
 #define OMAP4430_CLKSEL_SOURCE_MASK                             (0x3 << 24)
-
-/* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */
-#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT                      24
-#define OMAP4430_CLKSEL_SOURCE_24_24_WIDTH                      0x1
 #define OMAP4430_CLKSEL_SOURCE_24_24_MASK                       (1 << 24)
-
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_CLKSEL_UTMI_P1_SHIFT                           24
 #define OMAP4430_CLKSEL_UTMI_P1_WIDTH                           0x1
-#define OMAP4430_CLKSEL_UTMI_P1_MASK                            (1 << 24)
-
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_CLKSEL_UTMI_P2_SHIFT                           25
 #define OMAP4430_CLKSEL_UTMI_P2_WIDTH                           0x1
-#define OMAP4430_CLKSEL_UTMI_P2_MASK                            (1 << 25)
-
-/*
- * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL,
- * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL,
- * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL,
- * CM_L3INIT_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL,
- * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL,
- * CM_L4SEC_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_SDMA_CLKSTCTRL,
- * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL
- */
 #define OMAP4430_CLKTRCTRL_SHIFT                                0
-#define OMAP4430_CLKTRCTRL_WIDTH                                0x2
 #define OMAP4430_CLKTRCTRL_MASK                                 (0x3 << 0)
-
-/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
-#define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT                        0
-#define OMAP4430_CORE_DPLL_EMU_DIV_WIDTH                        0x7
-#define OMAP4430_CORE_DPLL_EMU_DIV_MASK                         (0x7f << 0)
-
-/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
-#define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT                       8
-#define OMAP4430_CORE_DPLL_EMU_MULT_WIDTH                       0xb
-#define OMAP4430_CORE_DPLL_EMU_MULT_MASK                        (0x7ff << 8)
-
-/* Used by REVISION_CM1, REVISION_CM2 */
-#define OMAP4430_CUSTOM_SHIFT                                   6
-#define OMAP4430_CUSTOM_WIDTH                                   0x2
-#define OMAP4430_CUSTOM_MASK                                    (0x3 << 6)
-
-/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
-#define OMAP4430_D2D_DYNDEP_SHIFT                               18
-#define OMAP4430_D2D_DYNDEP_WIDTH                               0x1
-#define OMAP4430_D2D_DYNDEP_MASK                                (1 << 18)
-
-/* Used by CM_MPU_STATICDEP */
-#define OMAP4430_D2D_STATDEP_SHIFT                              18
-#define OMAP4430_D2D_STATDEP_WIDTH                              0x1
-#define OMAP4430_D2D_STATDEP_MASK                               (1 << 18)
-
-/* Used by CM_CLKSEL_DPLL_MPU */
-#define OMAP4460_DCC_COUNT_MAX_SHIFT                            24
-#define OMAP4460_DCC_COUNT_MAX_WIDTH                            0x8
-#define OMAP4460_DCC_COUNT_MAX_MASK                             (0xff << 24)
-
-/* Used by CM_CLKSEL_DPLL_MPU */
-#define OMAP4460_DCC_EN_SHIFT                                   22
-#define OMAP4460_DCC_EN_MASK                                    (1 << 22)
-
-/*
- * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
- * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA,
- * CM_SSC_DELTAMSTEP_DPLL_MPU, CM_SSC_DELTAMSTEP_DPLL_PER,
- * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB
- */
-#define OMAP4430_DELTAMSTEP_SHIFT                               0
-#define OMAP4430_DELTAMSTEP_WIDTH                               0x14
-#define OMAP4430_DELTAMSTEP_MASK                                (0xfffff << 0)
-
-/* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */
-#define OMAP4460_DELTAMSTEP_0_20_SHIFT                          0
-#define OMAP4460_DELTAMSTEP_0_20_WIDTH                          0x15
-#define OMAP4460_DELTAMSTEP_0_20_MASK                           (0x1fffff << 0)
-
-/* Used by CM_DLL_CTRL */
-#define OMAP4430_DLL_OVERRIDE_SHIFT                             0
-#define OMAP4430_DLL_OVERRIDE_WIDTH                             0x1
-#define OMAP4430_DLL_OVERRIDE_MASK                              (1 << 0)
-
-/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
-#define OMAP4430_DLL_OVERRIDE_2_2_SHIFT                         2
-#define OMAP4430_DLL_OVERRIDE_2_2_WIDTH                         0x1
-#define OMAP4430_DLL_OVERRIDE_2_2_MASK                          (1 << 2)
-
-/* Used by CM_SHADOW_FREQ_CONFIG1 */
-#define OMAP4430_DLL_RESET_SHIFT                                3
-#define OMAP4430_DLL_RESET_WIDTH                                0x1
-#define OMAP4430_DLL_RESET_MASK                                 (1 << 3)
-
-/*
- * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
- * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
- * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB
- */
 #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT                          23
 #define OMAP4430_DPLL_BYP_CLKSEL_WIDTH                          0x1
-#define OMAP4430_DPLL_BYP_CLKSEL_MASK                           (1 << 23)
-
-/* Used by CM_CLKDCOLDO_DPLL_USB */
-#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT                 8
-#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH                 0x1
-#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK                  (1 << 8)
-
-/* Used by CM_CLKSEL_DPLL_CORE */
-#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT                    20
-#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_WIDTH                    0x1
-#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK                     (1 << 20)
-
-/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
-#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT                       0
-#define OMAP4430_DPLL_CLKOUTHIF_DIV_WIDTH                       0x5
 #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK                        (0x1f << 0)
-
-/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
-#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT                  5
-#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_WIDTH                  0x1
-#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK                   (1 << 5)
-
-/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
 #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT                 8
-#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_WIDTH                 0x1
-#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK                  (1 << 8)
-
-/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
-#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT                  10
-#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_WIDTH                  0x1
 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK                   (1 << 10)
-
-/*
- * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
- * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
- */
 #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT                          0
 #define OMAP4430_DPLL_CLKOUT_DIV_WIDTH                          0x5
 #define OMAP4430_DPLL_CLKOUT_DIV_MASK                           (0x1f << 0)
-
-/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */
-#define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT                      0
-#define OMAP4430_DPLL_CLKOUT_DIV_0_6_WIDTH                      0x7
 #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK                       (0x7f << 0)
-
-/*
- * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
- * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
- */
-#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT                     5
-#define OMAP4430_DPLL_CLKOUT_DIVCHACK_WIDTH                     0x1
-#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK                      (1 << 5)
-
-/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */
-#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT              7
-#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_WIDTH              0x1
-#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK               (1 << 7)
-
-/*
- * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
- * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
- */
-#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT                    8
-#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_WIDTH                    0x1
 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK                     (1 << 8)
-
-/* Used by CM_SHADOW_FREQ_CONFIG1 */
-#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT                        8
-#define OMAP4430_DPLL_CORE_DPLL_EN_WIDTH                        0x3
-#define OMAP4430_DPLL_CORE_DPLL_EN_MASK                         (0x7 << 8)
-
-/* Used by CM_SHADOW_FREQ_CONFIG1 */
-#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT                         11
-#define OMAP4430_DPLL_CORE_M2_DIV_WIDTH                         0x5
-#define OMAP4430_DPLL_CORE_M2_DIV_MASK                          (0x1f << 11)
-
-/* Used by CM_SHADOW_FREQ_CONFIG2 */
-#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT                         3
-#define OMAP4430_DPLL_CORE_M5_DIV_WIDTH                         0x5
-#define OMAP4430_DPLL_CORE_M5_DIV_MASK                          (0x1f << 3)
-
-/*
- * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
- * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
- * CM_CLKSEL_DPLL_UNIPRO
- */
-#define OMAP4430_DPLL_DIV_SHIFT                                 0
-#define OMAP4430_DPLL_DIV_WIDTH                                 0x7
 #define OMAP4430_DPLL_DIV_MASK                                  (0x7f << 0)
-
-/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */
-#define OMAP4430_DPLL_DIV_0_7_SHIFT                             0
-#define OMAP4430_DPLL_DIV_0_7_WIDTH                             0x8
 #define OMAP4430_DPLL_DIV_0_7_MASK                              (0xff << 0)
-
-/*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
- * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
- */
-#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT                       8
-#define OMAP4430_DPLL_DRIFTGUARD_EN_WIDTH                       0x1
-#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK                        (1 << 8)
-
-/* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */
-#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT                   3
-#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_WIDTH                   0x1
-#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK                    (1 << 3)
-
-/*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
- * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
- * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
- */
-#define OMAP4430_DPLL_EN_SHIFT                                  0
-#define OMAP4430_DPLL_EN_WIDTH                                  0x3
 #define OMAP4430_DPLL_EN_MASK                                   (0x7 << 0)
-
-/*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
- * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
- * CM_CLKMODE_DPLL_UNIPRO
- */
-#define OMAP4430_DPLL_LPMODE_EN_SHIFT                           10
-#define OMAP4430_DPLL_LPMODE_EN_WIDTH                           0x1
 #define OMAP4430_DPLL_LPMODE_EN_MASK                            (1 << 10)
-
-/*
- * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
- * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
- * CM_CLKSEL_DPLL_UNIPRO
- */
-#define OMAP4430_DPLL_MULT_SHIFT                                8
-#define OMAP4430_DPLL_MULT_WIDTH                                0xb
 #define OMAP4430_DPLL_MULT_MASK                                 (0x7ff << 8)
-
-/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */
-#define OMAP4430_DPLL_MULT_USB_SHIFT                            8
-#define OMAP4430_DPLL_MULT_USB_WIDTH                            0xc
 #define OMAP4430_DPLL_MULT_USB_MASK                             (0xfff << 8)
-
-/*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
- * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
- * CM_CLKMODE_DPLL_UNIPRO
- */
-#define OMAP4430_DPLL_REGM4XEN_SHIFT                            11
-#define OMAP4430_DPLL_REGM4XEN_WIDTH                            0x1
 #define OMAP4430_DPLL_REGM4XEN_MASK                             (1 << 11)
-
-/* Used by CM_CLKSEL_DPLL_USB */
-#define OMAP4430_DPLL_SD_DIV_SHIFT                              24
-#define OMAP4430_DPLL_SD_DIV_WIDTH                              0x8
 #define OMAP4430_DPLL_SD_DIV_MASK                               (0xff << 24)
-
-/*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
- * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
- * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
- */
-#define OMAP4430_DPLL_SSC_ACK_SHIFT                             13
-#define OMAP4430_DPLL_SSC_ACK_WIDTH                             0x1
-#define OMAP4430_DPLL_SSC_ACK_MASK                              (1 << 13)
-
-/*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
- * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
- * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
- */
-#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT                      14
-#define OMAP4430_DPLL_SSC_DOWNSPREAD_WIDTH                      0x1
-#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK                       (1 << 14)
-
-/*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
- * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
- * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
- */
-#define OMAP4430_DPLL_SSC_EN_SHIFT                              12
-#define OMAP4430_DPLL_SSC_EN_WIDTH                              0x1
-#define OMAP4430_DPLL_SSC_EN_MASK                               (1 << 12)
-
-/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
-#define OMAP4430_DSS_DYNDEP_SHIFT                               8
-#define OMAP4430_DSS_DYNDEP_WIDTH                               0x1
-#define OMAP4430_DSS_DYNDEP_MASK                                (1 << 8)
-
-/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
 #define OMAP4430_DSS_STATDEP_SHIFT                              8
-#define OMAP4430_DSS_STATDEP_WIDTH                              0x1
-#define OMAP4430_DSS_STATDEP_MASK                               (1 << 8)
-
-/* Used by CM_L3_2_DYNAMICDEP */
-#define OMAP4430_DUCATI_DYNDEP_SHIFT                            0
-#define OMAP4430_DUCATI_DYNDEP_WIDTH                            0x1
-#define OMAP4430_DUCATI_DYNDEP_MASK                             (1 << 0)
-
-/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
 #define OMAP4430_DUCATI_STATDEP_SHIFT                           0
-#define OMAP4430_DUCATI_STATDEP_WIDTH                           0x1
-#define OMAP4430_DUCATI_STATDEP_MASK                            (1 << 0)
-
-/* Used by CM_SHADOW_FREQ_CONFIG1 */
-#define OMAP4430_FREQ_UPDATE_SHIFT                              0
-#define OMAP4430_FREQ_UPDATE_WIDTH                              0x1
-#define OMAP4430_FREQ_UPDATE_MASK                               (1 << 0)
-
-/* Used by REVISION_CM1, REVISION_CM2 */
-#define OMAP4430_FUNC_SHIFT                                     16
-#define OMAP4430_FUNC_WIDTH                                     0xc
-#define OMAP4430_FUNC_MASK                                      (0xfff << 16)
-
-/* Used by CM_L3_2_DYNAMICDEP */
-#define OMAP4430_GFX_DYNDEP_SHIFT                               10
-#define OMAP4430_GFX_DYNDEP_WIDTH                               0x1
-#define OMAP4430_GFX_DYNDEP_MASK                                (1 << 10)
-
-/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
 #define OMAP4430_GFX_STATDEP_SHIFT                              10
-#define OMAP4430_GFX_STATDEP_WIDTH                              0x1
-#define OMAP4430_GFX_STATDEP_MASK                               (1 << 10)
-
-/* Used by CM_SHADOW_FREQ_CONFIG2 */
-#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT                         0
-#define OMAP4430_GPMC_FREQ_UPDATE_WIDTH                         0x1
-#define OMAP4430_GPMC_FREQ_UPDATE_MASK                          (1 << 0)
-
-/*
- * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
- * CM_DIV_M4_DPLL_PER
- */
-#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT                    0
-#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_WIDTH                    0x5
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK                     (0x1f << 0)
-
-/*
- * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
- * CM_DIV_M4_DPLL_PER
- */
-#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT               5
-#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH               0x1
-#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK                (1 << 5)
-
-/*
- * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
- * CM_DIV_M4_DPLL_PER
- */
-#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT              8
-#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH              0x1
-#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK               (1 << 8)
-
-/*
- * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
- * CM_DIV_M4_DPLL_PER
- */
-#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT                   12
-#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_WIDTH                   0x1
-#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK                    (1 << 12)
-
-/*
- * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
- * CM_DIV_M5_DPLL_PER
- */
-#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT                    0
-#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_WIDTH                    0x5
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK                     (0x1f << 0)
-
-/*
- * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
- * CM_DIV_M5_DPLL_PER
- */
-#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT               5
-#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH               0x1
-#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK                (1 << 5)
-
-/*
- * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
- * CM_DIV_M5_DPLL_PER
- */
-#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT              8
-#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH              0x1
-#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK               (1 << 8)
-
-/*
- * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
- * CM_DIV_M5_DPLL_PER
- */
-#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT                   12
-#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_WIDTH                   0x1
-#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK                    (1 << 12)
-
-/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
-#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT                    0
-#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_WIDTH                    0x5
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK                     (0x1f << 0)
-
-/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
-#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT               5
-#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH               0x1
-#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK                (1 << 5)
-
-/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
-#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT              8
-#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH              0x1
-#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK               (1 << 8)
-
-/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
-#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT                   12
-#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_WIDTH                   0x1
-#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK                    (1 << 12)
-
-/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
-#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT                    0
-#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_WIDTH                    0x5
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK                     (0x1f << 0)
-
-/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
-#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT               5
-#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_WIDTH               0x1
-#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK                (1 << 5)
-
-/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
-#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT              8
-#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_WIDTH              0x1
-#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK               (1 << 8)
-
-/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
-#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT                   12
-#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_WIDTH                   0x1
-#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK                    (1 << 12)
-
-/*
- * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
- * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
- * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
- * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
- * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL,
- * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
- * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL,
- * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL,
- * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
- * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
- * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
- * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
- * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
- * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
- * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
- * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
- * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
- * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
- * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
- * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
- * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
- * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
- * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
- * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
- * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
- * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
- * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
- * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL,
- * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL,
- * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL,
- * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
- * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
- * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
- * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
- * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
- * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL,
- * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL,
- * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
- */
 #define OMAP4430_IDLEST_SHIFT                                   16
-#define OMAP4430_IDLEST_WIDTH                                   0x2
 #define OMAP4430_IDLEST_MASK                                    (0x3 << 16)
-
-/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
-#define OMAP4430_ISS_DYNDEP_SHIFT                               9
-#define OMAP4430_ISS_DYNDEP_WIDTH                               0x1
-#define OMAP4430_ISS_DYNDEP_MASK                                (1 << 9)
-
-/*
- * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
- * CM_TESLA_STATICDEP
- */
-#define OMAP4430_ISS_STATDEP_SHIFT                              9
-#define OMAP4430_ISS_STATDEP_WIDTH                              0x1
-#define OMAP4430_ISS_STATDEP_MASK                               (1 << 9)
-
-/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
-#define OMAP4430_IVAHD_DYNDEP_SHIFT                             2
-#define OMAP4430_IVAHD_DYNDEP_WIDTH                             0x1
-#define OMAP4430_IVAHD_DYNDEP_MASK                              (1 << 2)
-
-/*
- * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
- * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_L3INIT_STATICDEP,
- * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
- */
 #define OMAP4430_IVAHD_STATDEP_SHIFT                            2
-#define OMAP4430_IVAHD_STATDEP_WIDTH                            0x1
-#define OMAP4430_IVAHD_STATDEP_MASK                             (1 << 2)
-
-/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
-#define OMAP4430_L3INIT_DYNDEP_SHIFT                            7
-#define OMAP4430_L3INIT_DYNDEP_WIDTH                            0x1
-#define OMAP4430_L3INIT_DYNDEP_MASK                             (1 << 7)
-
-/*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_MPU_STATICDEP,
- * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
- */
 #define OMAP4430_L3INIT_STATDEP_SHIFT                           7
-#define OMAP4430_L3INIT_STATDEP_WIDTH                           0x1
-#define OMAP4430_L3INIT_STATDEP_MASK                            (1 << 7)
-
-/*
- * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
- * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
- */
-#define OMAP4430_L3_1_DYNDEP_SHIFT                              5
-#define OMAP4430_L3_1_DYNDEP_WIDTH                              0x1
-#define OMAP4430_L3_1_DYNDEP_MASK                               (1 << 5)
-
-/*
- * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
- * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
- * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
- * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
- */
 #define OMAP4430_L3_1_STATDEP_SHIFT                             5
-#define OMAP4430_L3_1_STATDEP_WIDTH                             0x1
-#define OMAP4430_L3_1_STATDEP_MASK                              (1 << 5)
-
-/*
- * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
- * CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, CM_IVAHD_DYNAMICDEP,
- * CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
- * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
- */
-#define OMAP4430_L3_2_DYNDEP_SHIFT                              6
-#define OMAP4430_L3_2_DYNDEP_WIDTH                              0x1
-#define OMAP4430_L3_2_DYNDEP_MASK                               (1 << 6)
-
-/*
- * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
- * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
- * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
- * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
- */
 #define OMAP4430_L3_2_STATDEP_SHIFT                             6
-#define OMAP4430_L3_2_STATDEP_WIDTH                             0x1
-#define OMAP4430_L3_2_STATDEP_MASK                              (1 << 6)
-
-/* Used by CM_L3_1_DYNAMICDEP */
-#define OMAP4430_L4CFG_DYNDEP_SHIFT                             12
-#define OMAP4430_L4CFG_DYNDEP_WIDTH                             0x1
-#define OMAP4430_L4CFG_DYNDEP_MASK                              (1 << 12)
-
-/*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
- * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
- */
 #define OMAP4430_L4CFG_STATDEP_SHIFT                            12
-#define OMAP4430_L4CFG_STATDEP_WIDTH                            0x1
-#define OMAP4430_L4CFG_STATDEP_MASK                             (1 << 12)
-
-/* Used by CM_L3_2_DYNAMICDEP */
-#define OMAP4430_L4PER_DYNDEP_SHIFT                             13
-#define OMAP4430_L4PER_DYNDEP_WIDTH                             0x1
-#define OMAP4430_L4PER_DYNDEP_MASK                              (1 << 13)
-
-/*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
- * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
- */
 #define OMAP4430_L4PER_STATDEP_SHIFT                            13
-#define OMAP4430_L4PER_STATDEP_WIDTH                            0x1
-#define OMAP4430_L4PER_STATDEP_MASK                             (1 << 13)
-
-/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
-#define OMAP4430_L4SEC_DYNDEP_SHIFT                             14
-#define OMAP4430_L4SEC_DYNDEP_WIDTH                             0x1
-#define OMAP4430_L4SEC_DYNDEP_MASK                              (1 << 14)
-
-/*
- * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
- * CM_SDMA_STATICDEP
- */
 #define OMAP4430_L4SEC_STATDEP_SHIFT                            14
-#define OMAP4430_L4SEC_STATDEP_WIDTH                            0x1
-#define OMAP4430_L4SEC_STATDEP_MASK                             (1 << 14)
-
-/* Used by CM_L4CFG_DYNAMICDEP */
-#define OMAP4430_L4WKUP_DYNDEP_SHIFT                            15
-#define OMAP4430_L4WKUP_DYNDEP_WIDTH                            0x1
-#define OMAP4430_L4WKUP_DYNDEP_MASK                             (1 << 15)
-
-/*
- * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
- * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
- */
 #define OMAP4430_L4WKUP_STATDEP_SHIFT                           15
-#define OMAP4430_L4WKUP_STATDEP_WIDTH                           0x1
-#define OMAP4430_L4WKUP_STATDEP_MASK                            (1 << 15)
-
-/*
- * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
- * CM_MPU_DYNAMICDEP
- */
-#define OMAP4430_MEMIF_DYNDEP_SHIFT                             4
-#define OMAP4430_MEMIF_DYNDEP_WIDTH                             0x1
-#define OMAP4430_MEMIF_DYNDEP_MASK                              (1 << 4)
-
-/*
- * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
- * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
- * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
- * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
- */
 #define OMAP4430_MEMIF_STATDEP_SHIFT                            4
-#define OMAP4430_MEMIF_STATDEP_WIDTH                            0x1
-#define OMAP4430_MEMIF_STATDEP_MASK                             (1 << 4)
-
-/*
- * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
- * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
- * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
- * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
- */
-#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT                      8
-#define OMAP4430_MODFREQDIV_EXPONENT_WIDTH                      0x3
-#define OMAP4430_MODFREQDIV_EXPONENT_MASK                       (0x7 << 8)
-
-/*
- * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
- * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
- * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
- * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
- */
-#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT                      0
-#define OMAP4430_MODFREQDIV_MANTISSA_WIDTH                      0x7
-#define OMAP4430_MODFREQDIV_MANTISSA_MASK                       (0x7f << 0)
-
-/*
- * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
- * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
- * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
- * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
- * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL,
- * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
- * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL,
- * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL,
- * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
- * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
- * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
- * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
- * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
- * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
- * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
- * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
- * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
- * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
- * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
- * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
- * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
- * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
- * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
- * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
- * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
- * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
- * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
- * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL,
- * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL,
- * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL,
- * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
- * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
- * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
- * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
- * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
- * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL,
- * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL,
- * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
- */
 #define OMAP4430_MODULEMODE_SHIFT                               0
-#define OMAP4430_MODULEMODE_WIDTH                               0x2
 #define OMAP4430_MODULEMODE_MASK                                (0x3 << 0)
-
-/* Used by CM_L4CFG_DYNAMICDEP */
-#define OMAP4460_MPU_DYNDEP_SHIFT                               19
-#define OMAP4460_MPU_DYNDEP_WIDTH                               0x1
-#define OMAP4460_MPU_DYNDEP_MASK                                (1 << 19)
-
-/* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT                      9
-#define OMAP4430_OPTFCLKEN_48MHZ_CLK_WIDTH                      0x1
-#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK                       (1 << 9)
-
-/* Used by CM_WKUP_BANDGAP_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT                       8
-#define OMAP4430_OPTFCLKEN_BGAP_32K_WIDTH                       0x1
-#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK                        (1 << 8)
-
-/* Used by CM_ALWON_USBPHY_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT                         8
-#define OMAP4430_OPTFCLKEN_CLK32K_WIDTH                         0x1
-#define OMAP4430_OPTFCLKEN_CLK32K_MASK                          (1 << 8)
-
-/* Used by CM_CAM_ISS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT                        8
-#define OMAP4430_OPTFCLKEN_CTRLCLK_WIDTH                        0x1
-#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK                         (1 << 8)
-
-/*
- * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
- * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
- * CM_WKUP_GPIO1_CLKCTRL
- */
 #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT                          8
-#define OMAP4430_OPTFCLKEN_DBCLK_WIDTH                          0x1
-#define OMAP4430_OPTFCLKEN_DBCLK_MASK                           (1 << 8)
-
-/* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT                        8
-#define OMAP4430_OPTFCLKEN_DLL_CLK_WIDTH                        0x1
-#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK                         (1 << 8)
-
-/* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT                         8
-#define OMAP4430_OPTFCLKEN_DSSCLK_WIDTH                         0x1
-#define OMAP4430_OPTFCLKEN_DSSCLK_MASK                          (1 << 8)
-
-/* Used by CM_WKUP_USIM_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK_SHIFT                           8
-#define OMAP4430_OPTFCLKEN_FCLK_WIDTH                           0x1
-#define OMAP4430_OPTFCLKEN_FCLK_MASK                            (1 << 8)
-
-/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT                          8
-#define OMAP4430_OPTFCLKEN_FCLK0_WIDTH                          0x1
-#define OMAP4430_OPTFCLKEN_FCLK0_MASK                           (1 << 8)
-
-/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT                          9
-#define OMAP4430_OPTFCLKEN_FCLK1_WIDTH                          0x1
-#define OMAP4430_OPTFCLKEN_FCLK1_MASK                           (1 << 9)
-
-/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT                          10
-#define OMAP4430_OPTFCLKEN_FCLK2_WIDTH                          0x1
-#define OMAP4430_OPTFCLKEN_FCLK2_MASK                           (1 << 10)
-
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT                     15
-#define OMAP4430_OPTFCLKEN_FUNC48MCLK_WIDTH                     0x1
-#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK                      (1 << 15)
-
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT                13
-#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH                0x1
-#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK                 (1 << 13)
-
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT                14
-#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH                0x1
-#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK                 (1 << 14)
-
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT                 11
-#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH                 0x1
-#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK                  (1 << 11)
-
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT                 12
-#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH                 0x1
-#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK                  (1 << 12)
-
-/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT                  8
-#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_WIDTH                  0x1
-#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK                   (1 << 8)
-
-/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT                9
-#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_WIDTH                0x1
-#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK                 (1 << 9)
-
-/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT                        8
-#define OMAP4430_OPTFCLKEN_PHY_48M_WIDTH                        0x1
-#define OMAP4430_OPTFCLKEN_PHY_48M_MASK                         (1 << 8)
-
-/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT                    10
-#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_WIDTH                    0x1
-#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK                     (1 << 10)
-
-/* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT              11
-#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_WIDTH              0x1
-#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK               (1 << 11)
-
-/* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT                        10
-#define OMAP4430_OPTFCLKEN_SYS_CLK_WIDTH                        0x1
-#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK                         (1 << 10)
-
-/* Used by CM_WKUP_BANDGAP_CLKCTRL */
 #define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT                        8
-#define OMAP4460_OPTFCLKEN_TS_FCLK_WIDTH                        0x1
-#define OMAP4460_OPTFCLKEN_TS_FCLK_MASK                         (1 << 8)
-
-/* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT                         11
-#define OMAP4430_OPTFCLKEN_TV_CLK_WIDTH                         0x1
-#define OMAP4430_OPTFCLKEN_TV_CLK_MASK                          (1 << 11)
-
-/* Used by CM_L3INIT_UNIPRO1_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT                       8
-#define OMAP4430_OPTFCLKEN_TXPHYCLK_WIDTH                       0x1
-#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK                        (1 << 8)
-
-/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT                    8
-#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_WIDTH                    0x1
-#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK                     (1 << 8)
-
-/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT                    9
-#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_WIDTH                    0x1
-#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK                     (1 << 9)
-
-/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT                    10
-#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_WIDTH                    0x1
-#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK                     (1 << 10)
-
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT                    8
-#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_WIDTH                    0x1
-#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK                     (1 << 8)
-
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT                    9
-#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_WIDTH                    0x1
-#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK                     (1 << 9)
-
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT                    10
-#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_WIDTH                    0x1
-#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK                     (1 << 10)
-
-/* Used by CM_L3INIT_USB_OTG_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_XCLK_SHIFT                           8
-#define OMAP4430_OPTFCLKEN_XCLK_WIDTH                           0x1
-#define OMAP4430_OPTFCLKEN_XCLK_MASK                            (1 << 8)
-
-/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
-#define OMAP4430_OVERRIDE_ENABLE_SHIFT                          19
-#define OMAP4430_OVERRIDE_ENABLE_WIDTH                          0x1
-#define OMAP4430_OVERRIDE_ENABLE_MASK                           (1 << 19)
-
-/* Used by CM_CLKSEL_ABE */
 #define OMAP4430_PAD_CLKS_GATE_SHIFT                            8
-#define OMAP4430_PAD_CLKS_GATE_WIDTH                            0x1
-#define OMAP4430_PAD_CLKS_GATE_MASK                             (1 << 8)
-
-/* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */
-#define OMAP4430_PERF_CURRENT_SHIFT                             0
-#define OMAP4430_PERF_CURRENT_WIDTH                             0x8
-#define OMAP4430_PERF_CURRENT_MASK                              (0xff << 0)
-
-/*
- * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3,
- * CM_CORE_DVFS_PERF4, CM_IVA_DVFS_PERF_ABE, CM_IVA_DVFS_PERF_IVAHD,
- * CM_IVA_DVFS_PERF_TESLA
- */
-#define OMAP4430_PERF_REQ_SHIFT                                 0
-#define OMAP4430_PERF_REQ_WIDTH                                 0x8
-#define OMAP4430_PERF_REQ_MASK                                  (0xff << 0)
-
-/* Used by CM_RESTORE_ST */
-#define OMAP4430_PHASE1_COMPLETED_SHIFT                         0
-#define OMAP4430_PHASE1_COMPLETED_WIDTH                         0x1
-#define OMAP4430_PHASE1_COMPLETED_MASK                          (1 << 0)
-
-/* Used by CM_RESTORE_ST */
-#define OMAP4430_PHASE2A_COMPLETED_SHIFT                        1
-#define OMAP4430_PHASE2A_COMPLETED_WIDTH                        0x1
-#define OMAP4430_PHASE2A_COMPLETED_MASK                         (1 << 1)
-
-/* Used by CM_RESTORE_ST */
-#define OMAP4430_PHASE2B_COMPLETED_SHIFT                        2
-#define OMAP4430_PHASE2B_COMPLETED_WIDTH                        0x1
-#define OMAP4430_PHASE2B_COMPLETED_MASK                         (1 << 2)
-
-/* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT                         20
 #define OMAP4430_PMD_STM_MUX_CTRL_WIDTH                         0x2
-#define OMAP4430_PMD_STM_MUX_CTRL_MASK                          (0x3 << 20)
-
-/* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT                       22
 #define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH                       0x2
-#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK                        (0x3 << 22)
-
-/* Used by CM_DYN_DEP_PRESCAL */
-#define OMAP4430_PRESCAL_SHIFT                                  0
-#define OMAP4430_PRESCAL_WIDTH                                  0x6
-#define OMAP4430_PRESCAL_MASK                                   (0x3f << 0)
-
-/* Used by REVISION_CM1, REVISION_CM2 */
-#define OMAP4430_R_RTL_SHIFT                                    11
-#define OMAP4430_R_RTL_WIDTH                                    0x5
-#define OMAP4430_R_RTL_MASK                                     (0x1f << 11)
-
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */
-#define OMAP4430_SAR_MODE_SHIFT                                 4
-#define OMAP4430_SAR_MODE_WIDTH                                 0x1
-#define OMAP4430_SAR_MODE_MASK                                  (1 << 4)
-
-/* Used by CM_SCALE_FCLK */
 #define OMAP4430_SCALE_FCLK_SHIFT                               0
 #define OMAP4430_SCALE_FCLK_WIDTH                               0x1
-#define OMAP4430_SCALE_FCLK_MASK                                (1 << 0)
-
-/* Used by REVISION_CM1, REVISION_CM2 */
-#define OMAP4430_SCHEME_SHIFT                                   30
-#define OMAP4430_SCHEME_WIDTH                                   0x2
-#define OMAP4430_SCHEME_MASK                                    (0x3 << 30)
-
-/* Used by CM_L4CFG_DYNAMICDEP */
-#define OMAP4430_SDMA_DYNDEP_SHIFT                              11
-#define OMAP4430_SDMA_DYNDEP_WIDTH                              0x1
-#define OMAP4430_SDMA_DYNDEP_MASK                               (1 << 11)
-
-/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
-#define OMAP4430_SDMA_STATDEP_SHIFT                             11
-#define OMAP4430_SDMA_STATDEP_WIDTH                             0x1
-#define OMAP4430_SDMA_STATDEP_MASK                              (1 << 11)
-
-/* Used by CM_CLKSEL_ABE */
 #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT                         10
-#define OMAP4430_SLIMBUS_CLK_GATE_WIDTH                         0x1
-#define OMAP4430_SLIMBUS_CLK_GATE_MASK                          (1 << 10)
-
-/*
- * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL,
- * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
- * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
- * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
- * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
- * CM_L3INIT_USB_OTG_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL,
- * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL
- */
-#define OMAP4430_STBYST_SHIFT                                   18
-#define OMAP4430_STBYST_WIDTH                                   0x1
-#define OMAP4430_STBYST_MASK                                    (1 << 18)
-
-/*
- * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
- * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
- * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
- */
-#define OMAP4430_ST_DPLL_CLK_SHIFT                              0
-#define OMAP4430_ST_DPLL_CLK_WIDTH                              0x1
 #define OMAP4430_ST_DPLL_CLK_MASK                               (1 << 0)
-
-/* Used by CM_CLKDCOLDO_DPLL_USB */
-#define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT                        9
-#define OMAP4430_ST_DPLL_CLKDCOLDO_WIDTH                        0x1
-#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK                         (1 << 9)
-
-/*
- * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
- * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
- */
-#define OMAP4430_ST_DPLL_CLKOUT_SHIFT                           9
-#define OMAP4430_ST_DPLL_CLKOUT_WIDTH                           0x1
-#define OMAP4430_ST_DPLL_CLKOUT_MASK                            (1 << 9)
-
-/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
-#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT                        9
-#define OMAP4430_ST_DPLL_CLKOUTHIF_WIDTH                        0x1
-#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK                         (1 << 9)
-
-/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
-#define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT                         11
-#define OMAP4430_ST_DPLL_CLKOUTX2_WIDTH                         0x1
-#define OMAP4430_ST_DPLL_CLKOUTX2_MASK                          (1 << 11)
-
-/*
- * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
- * CM_DIV_M4_DPLL_PER
- */
-#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT                     9
-#define OMAP4430_ST_HSDIVIDER_CLKOUT1_WIDTH                     0x1
-#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK                      (1 << 9)
-
-/*
- * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
- * CM_DIV_M5_DPLL_PER
- */
-#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT                     9
-#define OMAP4430_ST_HSDIVIDER_CLKOUT2_WIDTH                     0x1
-#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK                      (1 << 9)
-
-/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
-#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT                     9
-#define OMAP4430_ST_HSDIVIDER_CLKOUT3_WIDTH                     0x1
-#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK                      (1 << 9)
-
-/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
-#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT                     9
-#define OMAP4430_ST_HSDIVIDER_CLKOUT4_WIDTH                     0x1
-#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK                      (1 << 9)
-
-/*
- * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
- * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
- * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
- */
-#define OMAP4430_ST_MN_BYPASS_SHIFT                             8
-#define OMAP4430_ST_MN_BYPASS_WIDTH                             0x1
-#define OMAP4430_ST_MN_BYPASS_MASK                              (1 << 8)
-
-/* Used by CM_SYS_CLKSEL */
 #define OMAP4430_SYS_CLKSEL_SHIFT                               0
 #define OMAP4430_SYS_CLKSEL_WIDTH                               0x3
-#define OMAP4430_SYS_CLKSEL_MASK                                (0x7 << 0)
-
-/* Used by CM_L4CFG_DYNAMICDEP */
-#define OMAP4430_TESLA_DYNDEP_SHIFT                             1
-#define OMAP4430_TESLA_DYNDEP_WIDTH                             0x1
-#define OMAP4430_TESLA_DYNDEP_MASK                              (1 << 1)
-
-/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
 #define OMAP4430_TESLA_STATDEP_SHIFT                            1
-#define OMAP4430_TESLA_STATDEP_WIDTH                            0x1
-#define OMAP4430_TESLA_STATDEP_MASK                             (1 << 1)
-
-/*
- * Used by CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP,
- * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
- * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
- */
-#define OMAP4430_WINDOWSIZE_SHIFT                               24
-#define OMAP4430_WINDOWSIZE_WIDTH                               0x4
-#define OMAP4430_WINDOWSIZE_MASK                                (0xf << 24)
-
-/* Used by REVISION_CM1, REVISION_CM2 */
-#define OMAP4430_X_MAJOR_SHIFT                                  8
-#define OMAP4430_X_MAJOR_WIDTH                                  0x3
-#define OMAP4430_X_MAJOR_MASK                                   (0x7 << 8)
-
-/* Used by REVISION_CM1, REVISION_CM2 */
-#define OMAP4430_Y_MINOR_SHIFT                                  0
-#define OMAP4430_Y_MINOR_WIDTH                                  0x6
-#define OMAP4430_Y_MINOR_MASK                                   (0x3f << 0)
 #endif
diff --git a/arch/arm/mach-omap2/cm-regbits-54xx.h b/arch/arm/mach-omap2/cm-regbits-54xx.h
index e83b8e352b6e..896ae9fc4cfb 100644
--- a/arch/arm/mach-omap2/cm-regbits-54xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-54xx.h
@@ -21,1717 +21,84 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H
 
-/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_MPU_DYNAMICDEP */
-#define OMAP54XX_ABE_DYNDEP_SHIFT                                       3
-#define OMAP54XX_ABE_DYNDEP_WIDTH                                       0x1
-#define OMAP54XX_ABE_DYNDEP_MASK                                        (1 << 3)
-
-/*
- * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
- * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
- */
 #define OMAP54XX_ABE_STATDEP_SHIFT                                      3
-#define OMAP54XX_ABE_STATDEP_WIDTH                                      0x1
-#define OMAP54XX_ABE_STATDEP_MASK                                       (1 << 3)
-
-/*
- * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_IVA,
- * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO1,
- * CM_AUTOIDLE_DPLL_UNIPRO2, CM_AUTOIDLE_DPLL_USB
- */
-#define OMAP54XX_AUTO_DPLL_MODE_SHIFT                                   0
-#define OMAP54XX_AUTO_DPLL_MODE_WIDTH                                   0x3
 #define OMAP54XX_AUTO_DPLL_MODE_MASK                                    (0x7 << 0)
-
-/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
-#define OMAP54XX_C2C_DYNDEP_SHIFT                                       18
-#define OMAP54XX_C2C_DYNDEP_WIDTH                                       0x1
-#define OMAP54XX_C2C_DYNDEP_MASK                                        (1 << 18)
-
-/* Used by CM_MPU_STATICDEP */
-#define OMAP54XX_C2C_STATDEP_SHIFT                                      18
-#define OMAP54XX_C2C_STATDEP_WIDTH                                      0x1
-#define OMAP54XX_C2C_STATDEP_MASK                                       (1 << 18)
-
-/* Used by CM_IPU_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
-#define OMAP54XX_CAM_DYNDEP_SHIFT                                       9
-#define OMAP54XX_CAM_DYNDEP_WIDTH                                       0x1
-#define OMAP54XX_CAM_DYNDEP_MASK                                        (1 << 9)
-
-/*
- * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP,
- * CM_MPU_STATICDEP
- */
-#define OMAP54XX_CAM_STATDEP_SHIFT                                      9
-#define OMAP54XX_CAM_STATDEP_WIDTH                                      0x1
-#define OMAP54XX_CAM_STATDEP_MASK                                       (1 << 9)
-
-/* Used by CM_ABE_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_SHIFT                        13
-#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_WIDTH                        0x1
-#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_MASK                         (1 << 13)
-
-/* Used by CM_ABE_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_SHIFT                          12
-#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_WIDTH                          0x1
-#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_MASK                           (1 << 12)
-
-/* Used by CM_ABE_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_ABE_GICLK_SHIFT                            9
-#define OMAP54XX_CLKACTIVITY_ABE_GICLK_WIDTH                            0x1
-#define OMAP54XX_CLKACTIVITY_ABE_GICLK_MASK                             (1 << 9)
-
-/* Used by CM_WKUPAON_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_SHIFT                           9
-#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_WIDTH                           0x1
-#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_MASK                            (1 << 9)
-
-/* Used by CM_ABE_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_SHIFT                          11
-#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_WIDTH                          0x1
-#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_MASK                           (1 << 11)
-
-/* Used by CM_ABE_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_SHIFT                           8
-#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_WIDTH                           0x1
-#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_MASK                            (1 << 8)
-
-/* Used by CM_DSS_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_SHIFT                           13
-#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_WIDTH                           0x1
-#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_MASK                            (1 << 13)
-
-/* Used by CM_C2C_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_SHIFT                            9
-#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_WIDTH                            0x1
-#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_MASK                             (1 << 9)
-
-/* Used by CM_C2C_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_C2C_GICLK_SHIFT                            10
-#define OMAP54XX_CLKACTIVITY_C2C_GICLK_WIDTH                            0x1
-#define OMAP54XX_CLKACTIVITY_C2C_GICLK_MASK                             (1 << 10)
-
-/* Used by CM_C2C_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_SHIFT                         8
-#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_WIDTH                         0x1
-#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_MASK                          (1 << 8)
-
-/* Used by CM_CAM_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_SHIFT                       11
-#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_WIDTH                       0x1
-#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_MASK                        (1 << 11)
-
-/* Used by CM_CAM_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_CAM_GCLK_SHIFT                             8
-#define OMAP54XX_CLKACTIVITY_CAM_GCLK_WIDTH                             0x1
-#define OMAP54XX_CLKACTIVITY_CAM_GCLK_MASK                              (1 << 8)
-
-/* Used by CM_CAM_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_SHIFT                         12
-#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_WIDTH                         0x1
-#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_MASK                          (1 << 12)
-
-/* Used by CM_COREAON_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_SHIFT                    12
-#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_WIDTH                    0x1
-#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_MASK                     (1 << 12)
-
-/* Used by CM_COREAON_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_SHIFT              14
-#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_WIDTH              0x1
-#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_MASK               (1 << 14)
-
-/* Used by CM_COREAON_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_SHIFT                     8
-#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_WIDTH                     0x1
-#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_MASK                      (1 << 8)
-
-/* Used by CM_CAM_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_SHIFT                        9
-#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_WIDTH                        0x1
-#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_MASK                         (1 << 9)
-
-/* Used by CM_CUSTEFUSE_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_SHIFT                   8
-#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_WIDTH                   0x1
-#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_MASK                    (1 << 8)
-
-/* Used by CM_CUSTEFUSE_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_SHIFT                  9
-#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_WIDTH                  0x1
-#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_MASK                   (1 << 9)
-
-/* Used by CM_EMIF_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_DLL_GCLK_SHIFT                             9
-#define OMAP54XX_CLKACTIVITY_DLL_GCLK_WIDTH                             0x1
-#define OMAP54XX_CLKACTIVITY_DLL_GCLK_MASK                              (1 << 9)
-
-/* Used by CM_DMA_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_SHIFT                         8
-#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_WIDTH                         0x1
-#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_MASK                          (1 << 8)
-
-/* Used by CM_DSP_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_DSP_GCLK_SHIFT                             8
-#define OMAP54XX_CLKACTIVITY_DSP_GCLK_WIDTH                             0x1
-#define OMAP54XX_CLKACTIVITY_DSP_GCLK_MASK                              (1 << 8)
-
-/* Used by CM_DSS_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_SHIFT                            9
-#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_WIDTH                            0x1
-#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_MASK                             (1 << 9)
-
-/* Used by CM_DSS_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_SHIFT                         8
-#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_WIDTH                         0x1
-#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_MASK                          (1 << 8)
-
-/* Used by CM_DSS_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_SHIFT                        10
-#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_WIDTH                        0x1
-#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_MASK                         (1 << 10)
-
-/* Used by CM_EMIF_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_SHIFT                        8
-#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_WIDTH                        0x1
-#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_MASK                         (1 << 8)
-
-/* Used by CM_EMIF_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_SHIFT                         11
-#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_WIDTH                         0x1
-#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_MASK                          (1 << 11)
-
-/* Used by CM_EMIF_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_SHIFT                        10
-#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_WIDTH                        0x1
-#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_MASK                         (1 << 10)
-
-/* Used by CM_EMU_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_SHIFT                         8
-#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_WIDTH                         0x1
-#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_MASK                          (1 << 8)
-
-/* Used by CM_CAM_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_SHIFT                            10
-#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_WIDTH                            0x1
-#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_MASK                             (1 << 10)
-
-/* Used by CM_ABE_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT                       10
-#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH                       0x1
-#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_MASK                        (1 << 10)
-
-/* Used by CM_GPU_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_SHIFT                        9
-#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_WIDTH                        0x1
-#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_MASK                         (1 << 9)
-
-/* Used by CM_GPU_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_SHIFT                         10
-#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_WIDTH                         0x1
-#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_MASK                          (1 << 10)
-
-/* Used by CM_GPU_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_SHIFT                         8
-#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_WIDTH                         0x1
-#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_MASK                          (1 << 8)
-
-/* Used by CM_DSS_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_SHIFT                       12
-#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_WIDTH                       0x1
-#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_MASK                        (1 << 12)
-
-/* Used by CM_DSS_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_SHIFT                       11
-#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_WIDTH                       0x1
-#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_MASK                        (1 << 11)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT                   20
-#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH                   0x1
-#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK                    (1 << 20)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT                        26
-#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH                        0x1
-#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_MASK                         (1 << 26)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT                   21
-#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH                   0x1
-#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK                    (1 << 21)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT                        27
-#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH                        0x1
-#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_MASK                         (1 << 27)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_SHIFT                   6
-#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_WIDTH                   0x1
-#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_MASK                    (1 << 6)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_SHIFT                        7
-#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_WIDTH                        0x1
-#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_MASK                         (1 << 7)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_SHIFT                            16
-#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_WIDTH                            0x1
-#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_MASK                             (1 << 16)
-
-/* Used by CM_IPU_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_IPU_GCLK_SHIFT                             8
-#define OMAP54XX_CLKACTIVITY_IPU_GCLK_WIDTH                             0x1
-#define OMAP54XX_CLKACTIVITY_IPU_GCLK_MASK                              (1 << 8)
-
-/* Used by CM_IVA_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_IVA_GCLK_SHIFT                             8
-#define OMAP54XX_CLKACTIVITY_IVA_GCLK_WIDTH                             0x1
-#define OMAP54XX_CLKACTIVITY_IVA_GCLK_MASK                              (1 << 8)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_SHIFT                     12
-#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_WIDTH                     0x1
-#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_MASK                      (1 << 12)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_SHIFT                  28
-#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_WIDTH                  0x1
-#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_MASK                   (1 << 28)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_SHIFT                  29
-#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_WIDTH                  0x1
-#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_MASK                   (1 << 29)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_SHIFT                      8
-#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_WIDTH                      0x1
-#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_MASK                       (1 << 8)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_SHIFT                      9
-#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_WIDTH                      0x1
-#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_MASK                       (1 << 9)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_SHIFT      11
-#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_WIDTH      0x1
-#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_MASK       (1 << 11)
-
-/* Used by CM_L3INSTR_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_SHIFT               9
-#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_WIDTH               0x1
-#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_MASK                (1 << 9)
-
-/* Used by CM_L3INSTR_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_SHIFT                     8
-#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_WIDTH                     0x1
-#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_MASK                      (1 << 8)
-
-/* Used by CM_L3INSTR_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_SHIFT                      10
-#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_WIDTH                      0x1
-#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_MASK                       (1 << 10)
-
-/* Used by CM_L3MAIN1_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_SHIFT                     8
-#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_WIDTH                     0x1
-#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_MASK                      (1 << 8)
-
-/* Used by CM_L3MAIN2_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_SHIFT                     8
-#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_WIDTH                     0x1
-#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_MASK                      (1 << 8)
-
-/* Used by CM_L4CFG_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_SHIFT                       8
-#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_WIDTH                       0x1
-#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_MASK                        (1 << 8)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_SHIFT                       8
-#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_WIDTH                       0x1
-#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_MASK                        (1 << 8)
-
-/* Used by CM_L4SEC_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_SHIFT                       8
-#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_WIDTH                       0x1
-#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_MASK                        (1 << 8)
-
-/* Used by CM_L4SEC_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_SHIFT                       9
-#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_WIDTH                       0x1
-#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_MASK                        (1 << 9)
-
-/* Used by CM_MIPIEXT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_SHIFT                     8
-#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_WIDTH                     0x1
-#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_MASK                      (1 << 8)
-
-/* Used by CM_MIPIEXT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_SHIFT                11
-#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_WIDTH                0x1
-#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_MASK                 (1 << 11)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_SHIFT                       2
-#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_WIDTH                       0x1
-#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_MASK                        (1 << 2)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_SHIFT                           17
-#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_WIDTH                           0x1
-#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_MASK                            (1 << 17)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_SHIFT                           18
-#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_WIDTH                           0x1
-#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_MASK                            (1 << 18)
-
-/* Used by CM_MPU_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_MPU_GCLK_SHIFT                             8
-#define OMAP54XX_CLKACTIVITY_MPU_GCLK_WIDTH                             0x1
-#define OMAP54XX_CLKACTIVITY_MPU_GCLK_MASK                              (1 << 8)
-
-/* Used by CM_ABE_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_PAD_CLKS_SHIFT                             14
-#define OMAP54XX_CLKACTIVITY_PAD_CLKS_WIDTH                             0x1
-#define OMAP54XX_CLKACTIVITY_PAD_CLKS_MASK                              (1 << 14)
-
-/* Used by CM_ABE_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_SHIFT                     15
-#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_WIDTH                     0x1
-#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_MASK                      (1 << 15)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_SHIFT                      3
-#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_WIDTH                      0x1
-#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_MASK                       (1 << 3)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_SHIFT                      4
-#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_WIDTH                      0x1
-#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_MASK                       (1 << 4)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_SHIFT                        15
-#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_WIDTH                        0x1
-#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_MASK                         (1 << 15)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_SHIFT                        17
-#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_WIDTH                        0x1
-#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_MASK                         (1 << 17)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_SHIFT                        18
-#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_WIDTH                        0x1
-#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_MASK                         (1 << 18)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_SHIFT                        19
-#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_WIDTH                        0x1
-#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_MASK                         (1 << 19)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_SHIFT                       19
-#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_WIDTH                       0x1
-#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_MASK                        (1 << 19)
-
-/* Used by CM_COREAON_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_SHIFT                    11
-#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_WIDTH                    0x1
-#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_MASK                     (1 << 11)
-
-/* Used by CM_COREAON_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_SHIFT                      10
-#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_WIDTH                      0x1
-#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_MASK                       (1 << 10)
-
-/* Used by CM_COREAON_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_SHIFT                     9
-#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_WIDTH                     0x1
-#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_MASK                      (1 << 9)
-
-/* Used by CM_WKUPAON_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_SYS_CLK_SHIFT                              8
-#define OMAP54XX_CLKACTIVITY_SYS_CLK_WIDTH                              0x1
-#define OMAP54XX_CLKACTIVITY_SYS_CLK_MASK                               (1 << 8)
-
-/* Used by CM_WKUPAON_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_SHIFT                          15
-#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_WIDTH                          0x1
-#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_MASK                           (1 << 15)
-
-/* Used by CM_WKUPAON_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_SHIFT                         14
-#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_WIDTH                         0x1
-#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_MASK                          (1 << 14)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_SHIFT                        9
-#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_WIDTH                        0x1
-#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_MASK                         (1 << 9)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_SHIFT                        10
-#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_WIDTH                        0x1
-#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_MASK                         (1 << 10)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_SHIFT                         11
-#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_WIDTH                         0x1
-#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_MASK                          (1 << 11)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_SHIFT                         12
-#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_WIDTH                         0x1
-#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_MASK                          (1 << 12)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_SHIFT                         13
-#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_WIDTH                         0x1
-#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_MASK                          (1 << 13)
-
-/* Used by CM_L4PER_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_SHIFT                         14
-#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_WIDTH                         0x1
-#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_MASK                          (1 << 14)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT                        22
-#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH                        0x1
-#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_MASK                         (1 << 22)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT                        23
-#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH                        0x1
-#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_MASK                         (1 << 23)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT                        24
-#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH                        0x1
-#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_MASK                         (1 << 24)
-
-/* Used by CM_MIPIEXT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_SHIFT                     10
-#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_WIDTH                     0x1
-#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_MASK                      (1 << 10)
-
-/* Used by CM_MIPIEXT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_SHIFT                    13
-#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_WIDTH                    0x1
-#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_MASK                     (1 << 13)
-
-/* Used by CM_MIPIEXT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_SHIFT               12
-#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_WIDTH               0x1
-#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_MASK                (1 << 12)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_SHIFT                     10
-#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_WIDTH                     0x1
-#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_MASK                      (1 << 10)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_SHIFT                    13
-#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_WIDTH                    0x1
-#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_MASK                     (1 << 13)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_SHIFT                5
-#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_WIDTH                0x1
-#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_MASK                 (1 << 5)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_SHIFT                         14
-#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_WIDTH                         0x1
-#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_MASK                          (1 << 14)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT                      15
-#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH                      0x1
-#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_MASK                       (1 << 15)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_SHIFT                   31
-#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_WIDTH                   0x1
-#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_MASK                    (1 << 31)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT                        30
-#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH                        0x1
-#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_MASK                         (1 << 30)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT                      25
-#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH                      0x1
-#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK                       (1 << 25)
-
-/* Used by CM_WKUPAON_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_SHIFT                    11
-#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_WIDTH                    0x1
-#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_MASK                     (1 << 11)
-
-/* Used by CM_WKUPAON_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_SHIFT                        12
-#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_WIDTH                        0x1
-#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_MASK                         (1 << 12)
-
-/* Used by CM_WKUPAON_CLKSTCTRL */
-#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_SHIFT              13
-#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_WIDTH              0x1
-#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_MASK               (1 << 13)
-
-/* Used by CM_COREAON_IO_SRCOMP_CLKCTRL, CM_WKUPAON_IO_SRCOMP_CLKCTRL */
-#define OMAP54XX_CLKEN_SRCOMP_FCLK_SHIFT                                8
-#define OMAP54XX_CLKEN_SRCOMP_FCLK_WIDTH                                0x1
-#define OMAP54XX_CLKEN_SRCOMP_FCLK_MASK                                 (1 << 8)
-
-/*
- * Used by CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
- * CM_ABE_TIMER8_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
- * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
- * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL
- */
 #define OMAP54XX_CLKSEL_SHIFT                                           24
 #define OMAP54XX_CLKSEL_WIDTH                                           0x1
-#define OMAP54XX_CLKSEL_MASK                                            (1 << 24)
-
-/*
- * Renamed from CLKSEL Used by CM_CLKSEL_ABE_DSS_SYS, CM_CLKSEL_ABE_PLL_REF,
- * CM_CLKSEL_USB_60MHZ, CM_CLKSEL_WKUPAON
- */
 #define OMAP54XX_CLKSEL_0_0_SHIFT                                       0
 #define OMAP54XX_CLKSEL_0_0_WIDTH                                       0x1
-#define OMAP54XX_CLKSEL_0_0_MASK                                        (1 << 0)
-
-/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
-#define OMAP54XX_CLKSEL_0_1_SHIFT                                       0
-#define OMAP54XX_CLKSEL_0_1_WIDTH                                       0x2
-#define OMAP54XX_CLKSEL_0_1_MASK                                        (0x3 << 0)
-
-/* Renamed from CLKSEL Used by CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL */
-#define OMAP54XX_CLKSEL_24_25_SHIFT                                     24
-#define OMAP54XX_CLKSEL_24_25_WIDTH                                     0x2
-#define OMAP54XX_CLKSEL_24_25_MASK                                      (0x3 << 24)
-
-/* Used by CM_MPU_MPU_CLKCTRL */
-#define OMAP54XX_CLKSEL_ABE_DIV_MODE_SHIFT                              26
-#define OMAP54XX_CLKSEL_ABE_DIV_MODE_WIDTH                              0x1
-#define OMAP54XX_CLKSEL_ABE_DIV_MODE_MASK                               (1 << 26)
-
-/* Used by CM_ABE_AESS_CLKCTRL */
 #define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT                                 24
 #define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH                                 0x1
-#define OMAP54XX_CLKSEL_AESS_FCLK_MASK                                  (1 << 24)
-
-/* Used by CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL */
 #define OMAP54XX_CLKSEL_DIV_SHIFT                                       25
 #define OMAP54XX_CLKSEL_DIV_WIDTH                                       0x1
-#define OMAP54XX_CLKSEL_DIV_MASK                                        (1 << 25)
-
-/* Used by CM_MPU_MPU_CLKCTRL */
-#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_SHIFT                             24
-#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_WIDTH                             0x2
-#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_MASK                              (0x3 << 24)
-
-/* Used by CM_CAM_FDIF_CLKCTRL */
 #define OMAP54XX_CLKSEL_FCLK_SHIFT                                      24
 #define OMAP54XX_CLKSEL_FCLK_WIDTH                                      0x1
-#define OMAP54XX_CLKSEL_FCLK_MASK                                       (1 << 24)
-
-/* Used by CM_GPU_GPU_CLKCTRL */
 #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT                             24
 #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH                             0x1
-#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_MASK                              (1 << 24)
-
-/* Used by CM_GPU_GPU_CLKCTRL */
 #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT                              25
 #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH                              0x1
-#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_MASK                               (1 << 25)
-
-/* Used by CM_GPU_GPU_CLKCTRL */
-#define OMAP54XX_CLKSEL_GPU_SYS_CLK_SHIFT                               26
-#define OMAP54XX_CLKSEL_GPU_SYS_CLK_WIDTH                               0x1
-#define OMAP54XX_CLKSEL_GPU_SYS_CLK_MASK                                (1 << 26)
-
-/*
- * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL,
- * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL
- */
 #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT                           26
 #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH                           0x2
-#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_MASK                            (0x3 << 26)
-
-/* Used by CM_CLKSEL_CORE */
-#define OMAP54XX_CLKSEL_L3_SHIFT                                        4
-#define OMAP54XX_CLKSEL_L3_WIDTH                                        0x1
-#define OMAP54XX_CLKSEL_L3_MASK                                         (1 << 4)
-
-/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
-#define OMAP54XX_CLKSEL_L3_1_1_SHIFT                                    1
-#define OMAP54XX_CLKSEL_L3_1_1_WIDTH                                    0x1
-#define OMAP54XX_CLKSEL_L3_1_1_MASK                                     (1 << 1)
-
-/* Used by CM_CLKSEL_CORE */
-#define OMAP54XX_CLKSEL_L4_SHIFT                                        8
-#define OMAP54XX_CLKSEL_L4_WIDTH                                        0x1
-#define OMAP54XX_CLKSEL_L4_MASK                                         (1 << 8)
-
-/* Used by CM_EMIF_EMIF1_CLKCTRL */
-#define OMAP54XX_CLKSEL_LL_SHIFT                                        24
-#define OMAP54XX_CLKSEL_LL_WIDTH                                        0x1
-#define OMAP54XX_CLKSEL_LL_MASK                                         (1 << 24)
-
-/* Used by CM_CLKSEL_ABE */
 #define OMAP54XX_CLKSEL_OPP_SHIFT                                       0
 #define OMAP54XX_CLKSEL_OPP_WIDTH                                       0x2
-#define OMAP54XX_CLKSEL_OPP_MASK                                        (0x3 << 0)
-
-/* Renamed from CLKSEL_OPP Used by CM_L3INIT_UNIPRO2_CLKCTRL */
-#define OMAP54XX_CLKSEL_OPP_24_24_SHIFT                                 24
-#define OMAP54XX_CLKSEL_OPP_24_24_WIDTH                                 0x1
-#define OMAP54XX_CLKSEL_OPP_24_24_MASK                                  (1 << 24)
-
-/*
- * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL,
- * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL
- */
 #define OMAP54XX_CLKSEL_SOURCE_SHIFT                                    24
 #define OMAP54XX_CLKSEL_SOURCE_WIDTH                                    0x2
-#define OMAP54XX_CLKSEL_SOURCE_MASK                                     (0x3 << 24)
-
-/*
- * Renamed from CLKSEL_SOURCE Used by CM_L3INIT_MMC1_CLKCTRL,
- * CM_L3INIT_MMC2_CLKCTRL
- */
 #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT                        24
 #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH                        0x1
-#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_MASK                         (1 << 24)
-
-/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
 #define OMAP54XX_CLKSEL_UTMI_P1_SHIFT                                   24
 #define OMAP54XX_CLKSEL_UTMI_P1_WIDTH                                   0x1
-#define OMAP54XX_CLKSEL_UTMI_P1_MASK                                    (1 << 24)
-
-/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
 #define OMAP54XX_CLKSEL_UTMI_P2_SHIFT                                   25
 #define OMAP54XX_CLKSEL_UTMI_P2_WIDTH                                   0x1
-#define OMAP54XX_CLKSEL_UTMI_P2_MASK                                    (1 << 25)
-
-/*
- * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER,
- * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER,
- * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE,
- * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE,
- * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE, CM_DIV_M2_DPLL_ABE,
- * CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER,
- * CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2, CM_DIV_M2_DPLL_USB,
- * CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER
- */
-#define OMAP54XX_CLKST_SHIFT                                            9
-#define OMAP54XX_CLKST_WIDTH                                            0x1
-#define OMAP54XX_CLKST_MASK                                             (1 << 9)
-
-/*
- * Used by CM_ABE_CLKSTCTRL, CM_C2C_CLKSTCTRL, CM_CAM_CLKSTCTRL,
- * CM_COREAON_CLKSTCTRL, CM_CUSTEFUSE_CLKSTCTRL, CM_DMA_CLKSTCTRL,
- * CM_DSP_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_EMIF_CLKSTCTRL, CM_EMU_CLKSTCTRL,
- * CM_GPU_CLKSTCTRL, CM_IPU_CLKSTCTRL, CM_IVA_CLKSTCTRL, CM_L3INIT_CLKSTCTRL,
- * CM_L3INSTR_CLKSTCTRL, CM_L3MAIN1_CLKSTCTRL, CM_L3MAIN2_CLKSTCTRL,
- * CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL,
- * CM_MIPIEXT_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_WKUPAON_CLKSTCTRL
- */
-#define OMAP54XX_CLKTRCTRL_SHIFT                                        0
-#define OMAP54XX_CLKTRCTRL_WIDTH                                        0x2
-#define OMAP54XX_CLKTRCTRL_MASK                                         (0x3 << 0)
-
-/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER */
-#define OMAP54XX_CLKX2ST_SHIFT                                          11
-#define OMAP54XX_CLKX2ST_WIDTH                                          0x1
-#define OMAP54XX_CLKX2ST_MASK                                           (1 << 11)
-
-/* Used by CM_L4CFG_DYNAMICDEP */
-#define OMAP54XX_COREAON_DYNDEP_SHIFT                                   16
-#define OMAP54XX_COREAON_DYNDEP_WIDTH                                   0x1
-#define OMAP54XX_COREAON_DYNDEP_MASK                                    (1 << 16)
-
-/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
-#define OMAP54XX_COREAON_STATDEP_SHIFT                                  16
-#define OMAP54XX_COREAON_STATDEP_WIDTH                                  0x1
-#define OMAP54XX_COREAON_STATDEP_MASK                                   (1 << 16)
-
-/* Used by CM_L4CFG_DYNAMICDEP */
-#define OMAP54XX_CUSTEFUSE_DYNDEP_SHIFT                                 17
-#define OMAP54XX_CUSTEFUSE_DYNDEP_WIDTH                                 0x1
-#define OMAP54XX_CUSTEFUSE_DYNDEP_MASK                                  (1 << 17)
-
-/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
-#define OMAP54XX_CUSTEFUSE_STATDEP_SHIFT                                17
-#define OMAP54XX_CUSTEFUSE_STATDEP_WIDTH                                0x1
-#define OMAP54XX_CUSTEFUSE_STATDEP_MASK                                 (1 << 17)
-
-/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
-#define OMAP54XX_CUSTOM_SHIFT                                           6
-#define OMAP54XX_CUSTOM_WIDTH                                           0x2
-#define OMAP54XX_CUSTOM_MASK                                            (0x3 << 6)
-
-/*
- * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
- * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1,
- * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
- */
-#define OMAP54XX_DCC_EN_SHIFT                                           22
-#define OMAP54XX_DCC_EN_WIDTH                                           0x1
-#define OMAP54XX_DCC_EN_MASK                                            (1 << 22)
-
-/*
- * Used by CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS,
- * CM_CORE_AON_DEBUG_DSS_FD_TRANS, CM_CORE_AON_DEBUG_EMIF_FD_TRANS,
- * CM_CORE_AON_DEBUG_L4SEC_FD_TRANS
- */
-#define OMAP54XX_CM_DEBUG_OUT_SHIFT                                     0
-#define OMAP54XX_CM_DEBUG_OUT_WIDTH                                     0xd
-#define OMAP54XX_CM_DEBUG_OUT_MASK                                      (0x1fff << 0)
-
-/*
- * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS,
- * CM_CORE_AON_DEBUG_L3INIT_FD_TRANS, CM_CORE_AON_DEBUG_L4PER_FD_TRANS
- */
-#define OMAP54XX_DEBUG_OUT_0_31_SHIFT                                   0
-#define OMAP54XX_DEBUG_OUT_0_31_WIDTH                                   0x20
-#define OMAP54XX_DEBUG_OUT_0_31_MASK                                    (0xffffffff << 0)
-
-/*
- * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_C2C_FD_TRANS,
- * CM_CORE_AON_DEBUG_COREAON_FD_TRANS, CM_CORE_AON_DEBUG_L4CFG_FD_TRANS
- */
-#define OMAP54XX_DEBUG_OUT_0_8_SHIFT                                    0
-#define OMAP54XX_DEBUG_OUT_0_8_WIDTH                                    0x9
-#define OMAP54XX_DEBUG_OUT_0_8_MASK                                     (0x1ff << 0)
-
-/*
- * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS,
- * CM_CORE_AON_DEBUG_DMA_FD_TRANS, CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS
- */
-#define OMAP54XX_DEBUG_OUT_0_4_SHIFT                                    0
-#define OMAP54XX_DEBUG_OUT_0_4_WIDTH                                    0x5
-#define OMAP54XX_DEBUG_OUT_0_4_MASK                                     (0x1f << 0)
-
-/*
- * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_DSP_FD_TRANS,
- * CM_CORE_AON_DEBUG_IPU_FD_TRANS, CM_CORE_AON_DEBUG_MPU_FD_TRANS
- */
-#define OMAP54XX_DEBUG_OUT_0_5_SHIFT                                    0
-#define OMAP54XX_DEBUG_OUT_0_5_WIDTH                                    0x6
-#define OMAP54XX_DEBUG_OUT_0_5_MASK                                     (0x3f << 0)
-
-/*
- * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CAM_FD_TRANS,
- * CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS
- */
-#define OMAP54XX_DEBUG_OUT_0_10_SHIFT                                   0
-#define OMAP54XX_DEBUG_OUT_0_10_WIDTH                                   0xb
-#define OMAP54XX_DEBUG_OUT_0_10_MASK                                    (0x7ff << 0)
-
-/*
- * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_IVA_FD_TRANS,
- * CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS
- */
-#define OMAP54XX_DEBUG_OUT_0_6_SHIFT                                    0
-#define OMAP54XX_DEBUG_OUT_0_6_WIDTH                                    0x7
-#define OMAP54XX_DEBUG_OUT_0_6_MASK                                     (0x7f << 0)
-
-/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS2 */
-#define OMAP54XX_DEBUG_OUT_0_19_SHIFT                                   0
-#define OMAP54XX_DEBUG_OUT_0_19_WIDTH                                   0x14
-#define OMAP54XX_DEBUG_OUT_0_19_MASK                                    (0xfffff << 0)
-
-/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_GPU_FD_TRANS */
-#define OMAP54XX_DEBUG_OUT_0_9_SHIFT                                    0
-#define OMAP54XX_DEBUG_OUT_0_9_WIDTH                                    0xa
-#define OMAP54XX_DEBUG_OUT_0_9_MASK                                     (0x3ff << 0)
-
-/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2 */
-#define OMAP54XX_DEBUG_OUT_0_26_SHIFT                                   0
-#define OMAP54XX_DEBUG_OUT_0_26_WIDTH                                   0x1b
-#define OMAP54XX_DEBUG_OUT_0_26_MASK                                    (0x7ffffff << 0)
-
-/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS */
-#define OMAP54XX_DEBUG_OUT_0_13_SHIFT                                   0
-#define OMAP54XX_DEBUG_OUT_0_13_WIDTH                                   0xe
-#define OMAP54XX_DEBUG_OUT_0_13_MASK                                    (0x3fff << 0)
-
-/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L4PER_FD_TRANS2 */
-#define OMAP54XX_DEBUG_OUT_0_21_SHIFT                                   0
-#define OMAP54XX_DEBUG_OUT_0_21_WIDTH                                   0x16
-#define OMAP54XX_DEBUG_OUT_0_21_MASK                                    (0x3fffff << 0)
-
-/*
- * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
- * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU,
- * CM_SSC_DELTAMSTEP_DPLL_PER
- */
-#define OMAP54XX_DELTAMSTEP_SHIFT                                       0
-#define OMAP54XX_DELTAMSTEP_WIDTH                                       0x14
-#define OMAP54XX_DELTAMSTEP_MASK                                        (0xfffff << 0)
-
-/*
- * Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_UNIPRO1,
- * CM_SSC_DELTAMSTEP_DPLL_UNIPRO2, CM_SSC_DELTAMSTEP_DPLL_USB
- */
-#define OMAP54XX_DELTAMSTEP_0_20_SHIFT                                  0
-#define OMAP54XX_DELTAMSTEP_0_20_WIDTH                                  0x15
-#define OMAP54XX_DELTAMSTEP_0_20_MASK                                   (0x1fffff << 0)
-
-/*
- * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER,
- * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER,
- * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE,
- * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE,
- * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE
- */
-#define OMAP54XX_DIVHS_SHIFT                                            0
-#define OMAP54XX_DIVHS_WIDTH                                            0x6
 #define OMAP54XX_DIVHS_MASK                                             (0x3f << 0)
-
-/*
- * Renamed from DIVHS Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
- * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M3_DPLL_ABE,
- * CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER
- */
-#define OMAP54XX_DIVHS_0_4_SHIFT                                        0
-#define OMAP54XX_DIVHS_0_4_WIDTH                                        0x5
 #define OMAP54XX_DIVHS_0_4_MASK                                         (0x1f << 0)
-
-/*
- * Renamed from DIVHS Used by CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2,
- * CM_DIV_M2_DPLL_USB
- */
-#define OMAP54XX_DIVHS_0_6_SHIFT                                        0
-#define OMAP54XX_DIVHS_0_6_WIDTH                                        0x7
 #define OMAP54XX_DIVHS_0_6_MASK                                         (0x7f << 0)
-
-/* Used by CM_DLL_CTRL */
-#define OMAP54XX_DLL_OVERRIDE_SHIFT                                     0
-#define OMAP54XX_DLL_OVERRIDE_WIDTH                                     0x1
-#define OMAP54XX_DLL_OVERRIDE_MASK                                      (1 << 0)
-
-/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
-#define OMAP54XX_DLL_OVERRIDE_2_2_SHIFT                                 2
-#define OMAP54XX_DLL_OVERRIDE_2_2_WIDTH                                 0x1
-#define OMAP54XX_DLL_OVERRIDE_2_2_MASK                                  (1 << 2)
-
-/* Used by CM_SHADOW_FREQ_CONFIG1 */
-#define OMAP54XX_DLL_RESET_SHIFT                                        3
-#define OMAP54XX_DLL_RESET_WIDTH                                        0x1
-#define OMAP54XX_DLL_RESET_MASK                                         (1 << 3)
-
-/*
- * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
- * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1,
- * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
- */
-#define OMAP54XX_DPLL_BYP_CLKSEL_SHIFT                                  23
-#define OMAP54XX_DPLL_BYP_CLKSEL_WIDTH                                  0x1
-#define OMAP54XX_DPLL_BYP_CLKSEL_MASK                                   (1 << 23)
-
-/* Used by CM_CLKSEL_DPLL_CORE */
-#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_SHIFT                            20
-#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_WIDTH                            0x1
-#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_MASK                             (1 << 20)
-
-/* Used by CM_SHADOW_FREQ_CONFIG1 */
-#define OMAP54XX_DPLL_CORE_DPLL_EN_SHIFT                                8
-#define OMAP54XX_DPLL_CORE_DPLL_EN_WIDTH                                0x3
-#define OMAP54XX_DPLL_CORE_DPLL_EN_MASK                                 (0x7 << 8)
-
-/* Used by CM_SHADOW_FREQ_CONFIG2 */
-#define OMAP54XX_DPLL_CORE_H12_DIV_SHIFT                                2
-#define OMAP54XX_DPLL_CORE_H12_DIV_WIDTH                                0x6
-#define OMAP54XX_DPLL_CORE_H12_DIV_MASK                                 (0x3f << 2)
-
-/* Used by CM_SHADOW_FREQ_CONFIG1 */
-#define OMAP54XX_DPLL_CORE_M2_DIV_SHIFT                                 11
-#define OMAP54XX_DPLL_CORE_M2_DIV_WIDTH                                 0x5
-#define OMAP54XX_DPLL_CORE_M2_DIV_MASK                                  (0x1f << 11)
-
-/*
- * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
- * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER
- */
-#define OMAP54XX_DPLL_DIV_SHIFT                                         0
-#define OMAP54XX_DPLL_DIV_WIDTH                                         0x7
 #define OMAP54XX_DPLL_DIV_MASK                                          (0x7f << 0)
-
-/*
- * Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_UNIPRO1,
- * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
- */
-#define OMAP54XX_DPLL_DIV_0_7_SHIFT                                     0
-#define OMAP54XX_DPLL_DIV_0_7_WIDTH                                     0x8
-#define OMAP54XX_DPLL_DIV_0_7_MASK                                      (0xff << 0)
-
-/*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
- */
-#define OMAP54XX_DPLL_DRIFTGUARD_EN_SHIFT                               8
-#define OMAP54XX_DPLL_DRIFTGUARD_EN_WIDTH                               0x1
-#define OMAP54XX_DPLL_DRIFTGUARD_EN_MASK                                (1 << 8)
-
-/*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
- * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
- */
-#define OMAP54XX_DPLL_EN_SHIFT                                          0
-#define OMAP54XX_DPLL_EN_WIDTH                                          0x3
 #define OMAP54XX_DPLL_EN_MASK                                           (0x7 << 0)
-
-/*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
- */
-#define OMAP54XX_DPLL_LPMODE_EN_SHIFT                                   10
-#define OMAP54XX_DPLL_LPMODE_EN_WIDTH                                   0x1
 #define OMAP54XX_DPLL_LPMODE_EN_MASK                                    (1 << 10)
-
-/*
- * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
- * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER
- */
-#define OMAP54XX_DPLL_MULT_SHIFT                                        8
-#define OMAP54XX_DPLL_MULT_WIDTH                                        0xb
 #define OMAP54XX_DPLL_MULT_MASK                                         (0x7ff << 8)
-
-/*
- * Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_UNIPRO1,
- * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
- */
-#define OMAP54XX_DPLL_MULT_UNIPRO1_SHIFT                                8
-#define OMAP54XX_DPLL_MULT_UNIPRO1_WIDTH                                0xc
-#define OMAP54XX_DPLL_MULT_UNIPRO1_MASK                                 (0xfff << 8)
-
-/*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
- */
-#define OMAP54XX_DPLL_REGM4XEN_SHIFT                                    11
-#define OMAP54XX_DPLL_REGM4XEN_WIDTH                                    0x1
 #define OMAP54XX_DPLL_REGM4XEN_MASK                                     (1 << 11)
-
-/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */
-#define OMAP54XX_DPLL_SD_DIV_SHIFT                                      24
-#define OMAP54XX_DPLL_SD_DIV_WIDTH                                      0x8
 #define OMAP54XX_DPLL_SD_DIV_MASK                                       (0xff << 24)
-
-/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */
-#define OMAP54XX_DPLL_SELFREQDCO_SHIFT                                  21
-#define OMAP54XX_DPLL_SELFREQDCO_WIDTH                                  0x1
-#define OMAP54XX_DPLL_SELFREQDCO_MASK                                   (1 << 21)
-
-/*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
- * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
- */
-#define OMAP54XX_DPLL_SSC_ACK_SHIFT                                     13
-#define OMAP54XX_DPLL_SSC_ACK_WIDTH                                     0x1
-#define OMAP54XX_DPLL_SSC_ACK_MASK                                      (1 << 13)
-
-/*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
- * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
- */
-#define OMAP54XX_DPLL_SSC_DOWNSPREAD_SHIFT                              14
-#define OMAP54XX_DPLL_SSC_DOWNSPREAD_WIDTH                              0x1
-#define OMAP54XX_DPLL_SSC_DOWNSPREAD_MASK                               (1 << 14)
-
-/*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
- * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
- */
-#define OMAP54XX_DPLL_SSC_EN_SHIFT                                      12
-#define OMAP54XX_DPLL_SSC_EN_WIDTH                                      0x1
-#define OMAP54XX_DPLL_SSC_EN_MASK                                       (1 << 12)
-
-/* Used by CM_L4CFG_DYNAMICDEP */
-#define OMAP54XX_DSP_DYNDEP_SHIFT                                       1
-#define OMAP54XX_DSP_DYNDEP_WIDTH                                       0x1
-#define OMAP54XX_DSP_DYNDEP_MASK                                        (1 << 1)
-
-/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
 #define OMAP54XX_DSP_STATDEP_SHIFT                                      1
-#define OMAP54XX_DSP_STATDEP_WIDTH                                      0x1
-#define OMAP54XX_DSP_STATDEP_MASK                                       (1 << 1)
-
-/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
-#define OMAP54XX_DSS_DYNDEP_SHIFT                                       8
-#define OMAP54XX_DSS_DYNDEP_WIDTH                                       0x1
-#define OMAP54XX_DSS_DYNDEP_MASK                                        (1 << 8)
-
-/* Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
 #define OMAP54XX_DSS_STATDEP_SHIFT                                      8
-#define OMAP54XX_DSS_STATDEP_WIDTH                                      0x1
-#define OMAP54XX_DSS_STATDEP_MASK                                       (1 << 8)
-
-/*
- * Used by CM_C2C_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
- * CM_MIPIEXT_DYNAMICDEP, CM_MPU_DYNAMICDEP
- */
-#define OMAP54XX_EMIF_DYNDEP_SHIFT                                      4
-#define OMAP54XX_EMIF_DYNDEP_WIDTH                                      0x1
-#define OMAP54XX_EMIF_DYNDEP_MASK                                       (1 << 4)
-
-/*
- * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
- * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
- * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
- * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
- */
 #define OMAP54XX_EMIF_STATDEP_SHIFT                                     4
-#define OMAP54XX_EMIF_STATDEP_WIDTH                                     0x1
-#define OMAP54XX_EMIF_STATDEP_MASK                                      (1 << 4)
-
-/* Used by CM_SHADOW_FREQ_CONFIG1 */
-#define OMAP54XX_FREQ_UPDATE_SHIFT                                      0
-#define OMAP54XX_FREQ_UPDATE_WIDTH                                      0x1
-#define OMAP54XX_FREQ_UPDATE_MASK                                       (1 << 0)
-
-/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
-#define OMAP54XX_FUNC_SHIFT                                             16
-#define OMAP54XX_FUNC_WIDTH                                             0xc
-#define OMAP54XX_FUNC_MASK                                              (0xfff << 16)
-
-/* Used by CM_SHADOW_FREQ_CONFIG2 */
-#define OMAP54XX_GPMC_FREQ_UPDATE_SHIFT                                 0
-#define OMAP54XX_GPMC_FREQ_UPDATE_WIDTH                                 0x1
-#define OMAP54XX_GPMC_FREQ_UPDATE_MASK                                  (1 << 0)
-
-/* Used by CM_L3MAIN2_DYNAMICDEP */
-#define OMAP54XX_GPU_DYNDEP_SHIFT                                       10
-#define OMAP54XX_GPU_DYNDEP_WIDTH                                       0x1
-#define OMAP54XX_GPU_DYNDEP_MASK                                        (1 << 10)
-
-/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
 #define OMAP54XX_GPU_STATDEP_SHIFT                                      10
-#define OMAP54XX_GPU_STATDEP_WIDTH                                      0x1
-#define OMAP54XX_GPU_STATDEP_MASK                                       (1 << 10)
-
-/*
- * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL,
- * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL,
- * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL,
- * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
- * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL,
- * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL,
- * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL,
- * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,
- * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,
- * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL,
- * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL,
- * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL,
- * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
- * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL,
- * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL,
- * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
- * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL,
- * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL,
- * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL,
- * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL,
- * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,
- * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
- * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL,
- * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL,
- * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL,
- * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL,
- * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
- * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
- * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
- * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL,
- * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
- * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
- * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
- * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL,
- * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
- * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
- * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
- * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
- * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
- * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
- * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
- * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL,
- * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL,
- * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL,
- * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL,
- * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL,
- * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL,
- * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL
- */
-#define OMAP54XX_IDLEST_SHIFT                                           16
-#define OMAP54XX_IDLEST_WIDTH                                           0x2
-#define OMAP54XX_IDLEST_MASK                                            (0x3 << 16)
-
-/* Used by CM_L3MAIN2_DYNAMICDEP */
-#define OMAP54XX_IPU_DYNDEP_SHIFT                                       0
-#define OMAP54XX_IPU_DYNDEP_WIDTH                                       0x1
-#define OMAP54XX_IPU_DYNDEP_MASK                                        (1 << 0)
-
-/* Used by CM_DMA_STATICDEP, CM_MPU_STATICDEP */
 #define OMAP54XX_IPU_STATDEP_SHIFT                                      0
-#define OMAP54XX_IPU_STATDEP_WIDTH                                      0x1
-#define OMAP54XX_IPU_STATDEP_MASK                                       (1 << 0)
-
-/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP */
-#define OMAP54XX_IVA_DYNDEP_SHIFT                                       2
-#define OMAP54XX_IVA_DYNDEP_WIDTH                                       0x1
-#define OMAP54XX_IVA_DYNDEP_MASK                                        (1 << 2)
-
-/*
- * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
- * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
- * CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
- */
 #define OMAP54XX_IVA_STATDEP_SHIFT                                      2
-#define OMAP54XX_IVA_STATDEP_WIDTH                                      0x1
-#define OMAP54XX_IVA_STATDEP_MASK                                       (1 << 2)
-
-/* Used by CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
-#define OMAP54XX_L3INIT_DYNDEP_SHIFT                                    7
-#define OMAP54XX_L3INIT_DYNDEP_WIDTH                                    0x1
-#define OMAP54XX_L3INIT_DYNDEP_MASK                                     (1 << 7)
-
-/*
- * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
- * CM_IPU_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
- */
 #define OMAP54XX_L3INIT_STATDEP_SHIFT                                   7
-#define OMAP54XX_L3INIT_STATDEP_WIDTH                                   0x1
-#define OMAP54XX_L3INIT_STATDEP_MASK                                    (1 << 7)
-
-/*
- * Used by CM_DSP_DYNAMICDEP, CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP,
- * CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP
- */
-#define OMAP54XX_L3MAIN1_DYNDEP_SHIFT                                   5
-#define OMAP54XX_L3MAIN1_DYNDEP_WIDTH                                   0x1
-#define OMAP54XX_L3MAIN1_DYNDEP_MASK                                    (1 << 5)
-
-/*
- * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
- * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
- * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
- * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
- */
 #define OMAP54XX_L3MAIN1_STATDEP_SHIFT                                  5
-#define OMAP54XX_L3MAIN1_STATDEP_WIDTH                                  0x1
-#define OMAP54XX_L3MAIN1_STATDEP_MASK                                   (1 << 5)
-
-/*
- * Used by CM_C2C_DYNAMICDEP, CM_CAM_DYNAMICDEP, CM_DMA_DYNAMICDEP,
- * CM_DSS_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GPU_DYNAMICDEP, CM_IPU_DYNAMICDEP,
- * CM_IVA_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP,
- * CM_L4CFG_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP
- */
-#define OMAP54XX_L3MAIN2_DYNDEP_SHIFT                                   6
-#define OMAP54XX_L3MAIN2_DYNDEP_WIDTH                                   0x1
-#define OMAP54XX_L3MAIN2_DYNDEP_MASK                                    (1 << 6)
-
-/*
- * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
- * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
- * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
- * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
- */
 #define OMAP54XX_L3MAIN2_STATDEP_SHIFT                                  6
-#define OMAP54XX_L3MAIN2_STATDEP_WIDTH                                  0x1
-#define OMAP54XX_L3MAIN2_STATDEP_MASK                                   (1 << 6)
-
-/* Used by CM_L3MAIN1_DYNAMICDEP */
-#define OMAP54XX_L4CFG_DYNDEP_SHIFT                                     12
-#define OMAP54XX_L4CFG_DYNDEP_WIDTH                                     0x1
-#define OMAP54XX_L4CFG_DYNDEP_MASK                                      (1 << 12)
-
-/*
- * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
- * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
- */
 #define OMAP54XX_L4CFG_STATDEP_SHIFT                                    12
-#define OMAP54XX_L4CFG_STATDEP_WIDTH                                    0x1
-#define OMAP54XX_L4CFG_STATDEP_MASK                                     (1 << 12)
-
-/* Used by CM_L3MAIN2_DYNAMICDEP */
-#define OMAP54XX_L4PER_DYNDEP_SHIFT                                     13
-#define OMAP54XX_L4PER_DYNDEP_WIDTH                                     0x1
-#define OMAP54XX_L4PER_DYNDEP_MASK                                      (1 << 13)
-
-/*
- * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
- * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
- * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
- */
 #define OMAP54XX_L4PER_STATDEP_SHIFT                                    13
-#define OMAP54XX_L4PER_STATDEP_WIDTH                                    0x1
-#define OMAP54XX_L4PER_STATDEP_MASK                                     (1 << 13)
-
-/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
-#define OMAP54XX_L4SEC_DYNDEP_SHIFT                                     14
-#define OMAP54XX_L4SEC_DYNDEP_WIDTH                                     0x1
-#define OMAP54XX_L4SEC_DYNDEP_MASK                                      (1 << 14)
-
-/*
- * Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_L3INIT_STATICDEP,
- * CM_MPU_STATICDEP
- */
 #define OMAP54XX_L4SEC_STATDEP_SHIFT                                    14
-#define OMAP54XX_L4SEC_STATDEP_WIDTH                                    0x1
-#define OMAP54XX_L4SEC_STATDEP_MASK                                     (1 << 14)
-
-/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
-#define OMAP54XX_MIPIEXT_DYNDEP_SHIFT                                   21
-#define OMAP54XX_MIPIEXT_DYNDEP_WIDTH                                   0x1
-#define OMAP54XX_MIPIEXT_DYNDEP_MASK                                    (1 << 21)
-
-/* Used by CM_MPU_STATICDEP */
-#define OMAP54XX_MIPIEXT_STATDEP_SHIFT                                  21
-#define OMAP54XX_MIPIEXT_STATDEP_WIDTH                                  0x1
-#define OMAP54XX_MIPIEXT_STATDEP_MASK                                   (1 << 21)
-
-/*
- * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
- * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
- * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1,
- * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB
- */
-#define OMAP54XX_MODFREQDIV_EXPONENT_SHIFT                              8
-#define OMAP54XX_MODFREQDIV_EXPONENT_WIDTH                              0x3
-#define OMAP54XX_MODFREQDIV_EXPONENT_MASK                               (0x7 << 8)
-
-/*
- * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
- * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
- * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1,
- * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB
- */
-#define OMAP54XX_MODFREQDIV_MANTISSA_SHIFT                              0
-#define OMAP54XX_MODFREQDIV_MANTISSA_WIDTH                              0x7
-#define OMAP54XX_MODFREQDIV_MANTISSA_MASK                               (0x7f << 0)
-
-/*
- * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL,
- * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL,
- * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL,
- * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
- * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL,
- * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL,
- * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL,
- * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,
- * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,
- * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL,
- * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL,
- * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL,
- * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
- * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL,
- * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL,
- * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
- * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL,
- * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL,
- * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL,
- * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL,
- * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,
- * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
- * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL,
- * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL,
- * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL,
- * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL,
- * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
- * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
- * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
- * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL,
- * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
- * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
- * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
- * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL,
- * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
- * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
- * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
- * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
- * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
- * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
- * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
- * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL,
- * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL,
- * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL,
- * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL,
- * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL,
- * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL,
- * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL
- */
-#define OMAP54XX_MODULEMODE_SHIFT                                       0
-#define OMAP54XX_MODULEMODE_WIDTH                                       0x2
-#define OMAP54XX_MODULEMODE_MASK                                        (0x3 << 0)
-
-/* Used by CM_L4CFG_DYNAMICDEP */
-#define OMAP54XX_MPU_DYNDEP_SHIFT                                       19
-#define OMAP54XX_MPU_DYNDEP_WIDTH                                       0x1
-#define OMAP54XX_MPU_DYNDEP_MASK                                        (1 << 19)
-
-/* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT                              11
-#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_WIDTH                              0x1
-#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_MASK                               (1 << 11)
-
-/* Renamed from OPTFCLKEN_32KHZ_CLK Used by CM_L3INIT_MMC1_CLKCTRL */
 #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT                          8
-#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_WIDTH                          0x1
-#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_MASK                           (1 << 8)
-
-/* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT                              9
-#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_WIDTH                              0x1
-#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_MASK                               (1 << 9)
-
-/* Used by CM_COREAON_USB_PHY_CORE_CLKCTRL */
 #define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT                                 8
-#define OMAP54XX_OPTFCLKEN_CLK32K_WIDTH                                 0x1
-#define OMAP54XX_OPTFCLKEN_CLK32K_MASK                                  (1 << 8)
-
-/* Used by CM_CAM_ISS_CLKCTRL */
 #define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT                                8
-#define OMAP54XX_OPTFCLKEN_CTRLCLK_WIDTH                                0x1
-#define OMAP54XX_OPTFCLKEN_CTRLCLK_MASK                                 (1 << 8)
-
-/*
- * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
- * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
- * CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, CM_WKUPAON_GPIO1_CLKCTRL
- */
 #define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT                                  8
-#define OMAP54XX_OPTFCLKEN_DBCLK_WIDTH                                  0x1
-#define OMAP54XX_OPTFCLKEN_DBCLK_MASK                                   (1 << 8)
-
-/* Used by CM_EMIF_EMIF_DLL_CLKCTRL */
-#define OMAP54XX_OPTFCLKEN_DLL_CLK_SHIFT                                8
-#define OMAP54XX_OPTFCLKEN_DLL_CLK_WIDTH                                0x1
-#define OMAP54XX_OPTFCLKEN_DLL_CLK_MASK                                 (1 << 8)
-
-/* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT                                 8
-#define OMAP54XX_OPTFCLKEN_DSSCLK_WIDTH                                 0x1
-#define OMAP54XX_OPTFCLKEN_DSSCLK_MASK                                  (1 << 8)
-
-/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
-#define OMAP54XX_OPTFCLKEN_FCLK0_SHIFT                                  8
-#define OMAP54XX_OPTFCLKEN_FCLK0_WIDTH                                  0x1
-#define OMAP54XX_OPTFCLKEN_FCLK0_MASK                                   (1 << 8)
-
-/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
-#define OMAP54XX_OPTFCLKEN_FCLK1_SHIFT                                  9
-#define OMAP54XX_OPTFCLKEN_FCLK1_WIDTH                                  0x1
-#define OMAP54XX_OPTFCLKEN_FCLK1_MASK                                   (1 << 9)
-
-/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
-#define OMAP54XX_OPTFCLKEN_FCLK2_SHIFT                                  10
-#define OMAP54XX_OPTFCLKEN_FCLK2_WIDTH                                  0x1
-#define OMAP54XX_OPTFCLKEN_FCLK2_MASK                                   (1 << 10)
-
-/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
-#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_SHIFT                            15
-#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_WIDTH                            0x1
-#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_MASK                             (1 << 15)
-
-/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
 #define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT                        13
-#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH                        0x1
-#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_MASK                         (1 << 13)
-
-/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
 #define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT                        14
-#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH                        0x1
-#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_MASK                         (1 << 14)
-
-/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
 #define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT                        7
-#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_WIDTH                        0x1
-#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_MASK                         (1 << 7)
-
-/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
 #define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT                         11
-#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH                         0x1
-#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_MASK                          (1 << 11)
-
-/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
 #define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT                         12
-#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH                         0x1
-#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_MASK                          (1 << 12)
-
-/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
 #define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT                         6
-#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_WIDTH                         0x1
-#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_MASK                          (1 << 6)
-
-/* Used by CM_L3INIT_USB_OTG_SS_CLKCTRL */
 #define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT                             8
-#define OMAP54XX_OPTFCLKEN_REFCLK960M_WIDTH                             0x1
-#define OMAP54XX_OPTFCLKEN_REFCLK960M_MASK                              (1 << 8)
-
-/* Used by CM_L3INIT_SATA_CLKCTRL */
 #define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT                                8
-#define OMAP54XX_OPTFCLKEN_REF_CLK_WIDTH                                0x1
-#define OMAP54XX_OPTFCLKEN_REF_CLK_MASK                                 (1 << 8)
-
-/* Used by CM_WKUPAON_SCRM_CLKCTRL */
-#define OMAP54XX_OPTFCLKEN_SCRM_CORE_SHIFT                              8
-#define OMAP54XX_OPTFCLKEN_SCRM_CORE_WIDTH                              0x1
-#define OMAP54XX_OPTFCLKEN_SCRM_CORE_MASK                               (1 << 8)
-
-/* Used by CM_WKUPAON_SCRM_CLKCTRL */
-#define OMAP54XX_OPTFCLKEN_SCRM_PER_SHIFT                               9
-#define OMAP54XX_OPTFCLKEN_SCRM_PER_WIDTH                               0x1
-#define OMAP54XX_OPTFCLKEN_SCRM_PER_MASK                                (1 << 9)
-
-/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
 #define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT                            11
-#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_WIDTH                            0x1
-#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_MASK                             (1 << 11)
-
-/* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT                                10
-#define OMAP54XX_OPTFCLKEN_SYS_CLK_WIDTH                                0x1
-#define OMAP54XX_OPTFCLKEN_SYS_CLK_MASK                                 (1 << 10)
-
-/* Used by CM_MIPIEXT_LLI_CLKCTRL */
 #define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT                              8
-#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_WIDTH                              0x1
-#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_MASK                               (1 << 8)
-
-/* Used by CM_MIPIEXT_LLI_CLKCTRL */
 #define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT                           9
-#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_WIDTH                           0x1
-#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_MASK                            (1 << 9)
-
-/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
 #define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT                            8
-#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_WIDTH                            0x1
-#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_MASK                             (1 << 8)
-
-/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
 #define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT                            9
-#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_WIDTH                            0x1
-#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_MASK                             (1 << 9)
-
-/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
 #define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT                            10
-#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_WIDTH                            0x1
-#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_MASK                             (1 << 10)
-
-/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
 #define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT                            8
-#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_WIDTH                            0x1
-#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_MASK                             (1 << 8)
-
-/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
 #define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT                            9
-#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_WIDTH                            0x1
-#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_MASK                             (1 << 9)
-
-/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
 #define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT                            10
-#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_WIDTH                            0x1
-#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_MASK                             (1 << 10)
-
-/* Used by CM_CORE_AON_DEBUG_OUT, CM_CORE_DEBUG_OUT */
-#define OMAP54XX_OUTPUT_SHIFT                                           0
-#define OMAP54XX_OUTPUT_WIDTH                                           0x20
-#define OMAP54XX_OUTPUT_MASK                                            (0xffffffff << 0)
-
-/* Used by CM_CLKSEL_ABE */
 #define OMAP54XX_PAD_CLKS_GATE_SHIFT                                    8
-#define OMAP54XX_PAD_CLKS_GATE_WIDTH                                    0x1
-#define OMAP54XX_PAD_CLKS_GATE_MASK                                     (1 << 8)
-
-/* Used by CM_RESTORE_ST */
-#define OMAP54XX_PHASE1_COMPLETED_SHIFT                                 0
-#define OMAP54XX_PHASE1_COMPLETED_WIDTH                                 0x1
-#define OMAP54XX_PHASE1_COMPLETED_MASK                                  (1 << 0)
-
-/* Used by CM_RESTORE_ST */
-#define OMAP54XX_PHASE2A_COMPLETED_SHIFT                                1
-#define OMAP54XX_PHASE2A_COMPLETED_WIDTH                                0x1
-#define OMAP54XX_PHASE2A_COMPLETED_MASK                                 (1 << 1)
-
-/* Used by CM_RESTORE_ST */
-#define OMAP54XX_PHASE2B_COMPLETED_SHIFT                                2
-#define OMAP54XX_PHASE2B_COMPLETED_WIDTH                                0x1
-#define OMAP54XX_PHASE2B_COMPLETED_MASK                                 (1 << 2)
-
-/* Used by CM_DYN_DEP_PRESCAL */
-#define OMAP54XX_PRESCAL_SHIFT                                          0
-#define OMAP54XX_PRESCAL_WIDTH                                          0x6
-#define OMAP54XX_PRESCAL_MASK                                           (0x3f << 0)
-
-/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
-#define OMAP54XX_R_RTL_SHIFT                                            11
-#define OMAP54XX_R_RTL_WIDTH                                            0x5
-#define OMAP54XX_R_RTL_MASK                                             (0x1f << 11)
-
-/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_TLL_HS_CLKCTRL */
-#define OMAP54XX_SAR_MODE_SHIFT                                         4
-#define OMAP54XX_SAR_MODE_WIDTH                                         0x1
-#define OMAP54XX_SAR_MODE_MASK                                          (1 << 4)
-
-/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
-#define OMAP54XX_SCHEME_SHIFT                                           30
-#define OMAP54XX_SCHEME_WIDTH                                           0x2
-#define OMAP54XX_SCHEME_MASK                                            (0x3 << 30)
-
-/* Used by CM_L4CFG_DYNAMICDEP */
-#define OMAP54XX_SDMA_DYNDEP_SHIFT                                      11
-#define OMAP54XX_SDMA_DYNDEP_WIDTH                                      0x1
-#define OMAP54XX_SDMA_DYNDEP_MASK                                       (1 << 11)
-
-/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
-#define OMAP54XX_SDMA_STATDEP_SHIFT                                     11
-#define OMAP54XX_SDMA_STATDEP_WIDTH                                     0x1
-#define OMAP54XX_SDMA_STATDEP_MASK                                      (1 << 11)
-
-/* Used by CM_CORE_AON_DEBUG_CFG */
-#define OMAP54XX_SEL0_SHIFT                                             0
-#define OMAP54XX_SEL0_WIDTH                                             0x7
-#define OMAP54XX_SEL0_MASK                                              (0x7f << 0)
-
-/* Renamed from SEL0 Used by CM_CORE_DEBUG_CFG */
-#define OMAP54XX_SEL0_0_7_SHIFT                                         0
-#define OMAP54XX_SEL0_0_7_WIDTH                                         0x8
-#define OMAP54XX_SEL0_0_7_MASK                                          (0xff << 0)
-
-/* Used by CM_CORE_AON_DEBUG_CFG */
-#define OMAP54XX_SEL1_SHIFT                                             8
-#define OMAP54XX_SEL1_WIDTH                                             0x7
-#define OMAP54XX_SEL1_MASK                                              (0x7f << 8)
-
-/* Renamed from SEL1 Used by CM_CORE_DEBUG_CFG */
-#define OMAP54XX_SEL1_CORE_DEBUG_CFG_SHIFT                              8
-#define OMAP54XX_SEL1_CORE_DEBUG_CFG_WIDTH                              0x8
-#define OMAP54XX_SEL1_CORE_DEBUG_CFG_MASK                               (0xff << 8)
-
-/* Used by CM_CORE_AON_DEBUG_CFG */
-#define OMAP54XX_SEL2_SHIFT                                             16
-#define OMAP54XX_SEL2_WIDTH                                             0x7
-#define OMAP54XX_SEL2_MASK                                              (0x7f << 16)
-
-/* Renamed from SEL2 Used by CM_CORE_DEBUG_CFG */
-#define OMAP54XX_SEL2_CORE_DEBUG_CFG_SHIFT                              16
-#define OMAP54XX_SEL2_CORE_DEBUG_CFG_WIDTH                              0x8
-#define OMAP54XX_SEL2_CORE_DEBUG_CFG_MASK                               (0xff << 16)
-
-/* Used by CM_CORE_AON_DEBUG_CFG */
-#define OMAP54XX_SEL3_SHIFT                                             24
-#define OMAP54XX_SEL3_WIDTH                                             0x7
-#define OMAP54XX_SEL3_MASK                                              (0x7f << 24)
-
-/* Renamed from SEL3 Used by CM_CORE_DEBUG_CFG */
-#define OMAP54XX_SEL3_CORE_DEBUG_CFG_SHIFT                              24
-#define OMAP54XX_SEL3_CORE_DEBUG_CFG_WIDTH                              0x8
-#define OMAP54XX_SEL3_CORE_DEBUG_CFG_MASK                               (0xff << 24)
-
-/* Used by CM_CLKSEL_ABE */
 #define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT                                10
-#define OMAP54XX_SLIMBUS1_CLK_GATE_WIDTH                                0x1
-#define OMAP54XX_SLIMBUS1_CLK_GATE_MASK                                 (1 << 10)
-
-/*
- * Used by CM_ABE_AESS_CLKCTRL, CM_C2C_C2C_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
- * CM_CAM_ISS_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, CM_DSP_DSP_CLKCTRL,
- * CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
- * CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, CM_IVA_IVA_CLKCTRL,
- * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_IEEE1500_2_OCP_CLKCTRL,
- * CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_SATA_CLKCTRL,
- * CM_L3INIT_UNIPRO2_CLKCTRL, CM_L3INIT_USB_HOST_HS_CLKCTRL,
- * CM_L3INIT_USB_OTG_SS_CLKCTRL, CM_L4SEC_DMA_CRYPTO_CLKCTRL,
- * CM_MIPIEXT_LLI_CLKCTRL, CM_MPU_MPU_CLKCTRL
- */
-#define OMAP54XX_STBYST_SHIFT                                           18
-#define OMAP54XX_STBYST_WIDTH                                           0x1
-#define OMAP54XX_STBYST_MASK                                            (1 << 18)
-
-/*
- * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
- * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
- * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
- */
-#define OMAP54XX_ST_DPLL_CLK_SHIFT                                      0
-#define OMAP54XX_ST_DPLL_CLK_WIDTH                                      0x1
 #define OMAP54XX_ST_DPLL_CLK_MASK                                       (1 << 0)
-
-/*
- * Used by CM_CLKDCOLDO_DPLL_UNIPRO1, CM_CLKDCOLDO_DPLL_UNIPRO2,
- * CM_CLKDCOLDO_DPLL_USB
- */
-#define OMAP54XX_ST_DPLL_CLKDCOLDO_SHIFT                                9
-#define OMAP54XX_ST_DPLL_CLKDCOLDO_WIDTH                                0x1
-#define OMAP54XX_ST_DPLL_CLKDCOLDO_MASK                                 (1 << 9)
-
-/*
- * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
- * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
- * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
- */
-#define OMAP54XX_ST_DPLL_INIT_SHIFT                                     4
-#define OMAP54XX_ST_DPLL_INIT_WIDTH                                     0x1
-#define OMAP54XX_ST_DPLL_INIT_MASK                                      (1 << 4)
-
-/*
- * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
- * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
- * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
- */
-#define OMAP54XX_ST_DPLL_MODE_SHIFT                                     1
-#define OMAP54XX_ST_DPLL_MODE_WIDTH                                     0x3
-#define OMAP54XX_ST_DPLL_MODE_MASK                                      (0x7 << 1)
-
-/* Used by CM_CLKSEL_SYS */
 #define OMAP54XX_SYS_CLKSEL_SHIFT                                       0
 #define OMAP54XX_SYS_CLKSEL_WIDTH                                       0x3
-#define OMAP54XX_SYS_CLKSEL_MASK                                        (0x7 << 0)
-
-/*
- * Used by CM_C2C_DYNAMICDEP, CM_DSP_DYNAMICDEP, CM_EMU_DYNAMICDEP,
- * CM_IPU_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP,
- * CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP,
- * CM_MPU_DYNAMICDEP
- */
-#define OMAP54XX_WINDOWSIZE_SHIFT                                       24
-#define OMAP54XX_WINDOWSIZE_WIDTH                                       0x4
-#define OMAP54XX_WINDOWSIZE_MASK                                        (0xf << 24)
-
-/* Used by CM_L3MAIN1_DYNAMICDEP */
-#define OMAP54XX_WKUPAON_DYNDEP_SHIFT                                   15
-#define OMAP54XX_WKUPAON_DYNDEP_WIDTH                                   0x1
-#define OMAP54XX_WKUPAON_DYNDEP_MASK                                    (1 << 15)
-
-/*
- * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP,
- * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP
- */
 #define OMAP54XX_WKUPAON_STATDEP_SHIFT                                  15
-#define OMAP54XX_WKUPAON_STATDEP_WIDTH                                  0x1
-#define OMAP54XX_WKUPAON_STATDEP_MASK                                   (1 << 15)
-
-/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
-#define OMAP54XX_X_MAJOR_SHIFT                                          8
-#define OMAP54XX_X_MAJOR_WIDTH                                          0x3
-#define OMAP54XX_X_MAJOR_MASK                                           (0x7 << 8)
-
-/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
-#define OMAP54XX_Y_MINOR_SHIFT                                          0
-#define OMAP54XX_Y_MINOR_WIDTH                                          0x6
-#define OMAP54XX_Y_MINOR_MASK                                           (0x3f << 0)
 #endif
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
index 3c70f5c1860f..b4d04748576b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -32,7 +32,6 @@
 #include "cm1_54xx.h"
 #include "cm2_54xx.h"
 #include "prm54xx.h"
-#include "prm-regbits-54xx.h"
 #include "i2c.h"
 #include "mmc.h"
 #include "wd_timer.h"
diff --git a/arch/arm/mach-omap2/powerdomains54xx_data.c b/arch/arm/mach-omap2/powerdomains54xx_data.c
index 81f8a7cc26ee..ce1d752af991 100644
--- a/arch/arm/mach-omap2/powerdomains54xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains54xx_data.c
@@ -25,7 +25,6 @@
 
 #include "prcm-common.h"
 #include "prcm44xx.h"
-#include "prm-regbits-54xx.h"
 #include "prm54xx.h"
 #include "prcm_mpu54xx.h"
 
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h
index 91aa5106d637..37fc905c9636 100644
--- a/arch/arm/mach-omap2/prm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-24xx.h
@@ -16,274 +16,27 @@
 
 #include "prm2xxx.h"
 
-/* Bits shared between registers */
-
-/* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */
-#define OMAP24XX_VOLTTRANS_ST_MASK                      (1 << 2)
-#define OMAP24XX_WKUP2_ST_MASK                          (1 << 1)
-#define OMAP24XX_WKUP1_ST_MASK                          (1 << 0)
-
-/* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */
-#define OMAP24XX_VOLTTRANS_EN_MASK                      (1 << 2)
-#define OMAP24XX_WKUP2_EN_MASK                          (1 << 1)
-#define OMAP24XX_WKUP1_EN_MASK                          (1 << 0)
-
-/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */
-#define OMAP24XX_EN_MPU_SHIFT                           1
-#define OMAP24XX_EN_MPU_MASK                            (1 << 1)
 #define OMAP24XX_EN_CORE_SHIFT                          0
-#define OMAP24XX_EN_CORE_MASK                           (1 << 0)
-
-/*
- * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM
- * shared bits
- */
-#define OMAP24XX_MEMONSTATE_SHIFT                       10
-#define OMAP24XX_MEMONSTATE_MASK                        (0x3 << 10)
-#define OMAP24XX_MEMRETSTATE_MASK                       (1 << 3)
-
-/* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */
 #define OMAP24XX_FORCESTATE_MASK                        (1 << 18)
-
-/*
- * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP,
- * PM_PWSTST_MDM shared bits
- */
-#define OMAP24XX_CLKACTIVITY_MASK                       (1 << 19)
-
-/* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */
-#define OMAP24XX_LASTSTATEENTERED_SHIFT                 4
-#define OMAP24XX_LASTSTATEENTERED_MASK                  (0x3 << 4)
-
-/* PM_PWSTST_MPU and PM_PWSTST_DSP shared bits */
-#define OMAP2430_MEMSTATEST_SHIFT                       10
-#define OMAP2430_MEMSTATEST_MASK                        (0x3 << 10)
-
-/* PM_PWSTST_GFX, PM_PWSTST_DSP, PM_PWSTST_MDM shared bits */
-#define OMAP24XX_POWERSTATEST_SHIFT                     0
-#define OMAP24XX_POWERSTATEST_MASK                      (0x3 << 0)
-
-
-/* Bits specific to each register */
-
-/* PRCM_REVISION */
-#define OMAP24XX_REV_SHIFT                              0
-#define OMAP24XX_REV_MASK                               (0xff << 0)
-
-/* PRCM_SYSCONFIG */
 #define OMAP24XX_AUTOIDLE_MASK                          (1 << 0)
-
-/* PRCM_IRQSTATUS_MPU specific bits */
-#define OMAP2430_DPLL_RECAL_ST_MASK                     (1 << 6)
-#define OMAP24XX_TRANSITION_ST_MASK                     (1 << 5)
-#define OMAP24XX_EVGENOFF_ST_MASK                       (1 << 4)
-#define OMAP24XX_EVGENON_ST_MASK                        (1 << 3)
-
-/* PRCM_IRQENABLE_MPU specific bits */
-#define OMAP2430_DPLL_RECAL_EN_MASK                     (1 << 6)
-#define OMAP24XX_TRANSITION_EN_MASK                     (1 << 5)
-#define OMAP24XX_EVGENOFF_EN_MASK                       (1 << 4)
-#define OMAP24XX_EVGENON_EN_MASK                        (1 << 3)
-
-/* PRCM_VOLTCTRL */
 #define OMAP24XX_AUTO_EXTVOLT_MASK                      (1 << 15)
-#define OMAP24XX_FORCE_EXTVOLT_MASK                     (1 << 14)
 #define OMAP24XX_SETOFF_LEVEL_SHIFT                     12
-#define OMAP24XX_SETOFF_LEVEL_MASK                      (0x3 << 12)
 #define OMAP24XX_MEMRETCTRL_MASK                        (1 << 8)
 #define OMAP24XX_SETRET_LEVEL_SHIFT                     6
-#define OMAP24XX_SETRET_LEVEL_MASK                      (0x3 << 6)
 #define OMAP24XX_VOLT_LEVEL_SHIFT                       0
-#define OMAP24XX_VOLT_LEVEL_MASK                        (0x3 << 0)
-
-/* PRCM_VOLTST */
-#define OMAP24XX_ST_VOLTLEVEL_SHIFT                     0
-#define OMAP24XX_ST_VOLTLEVEL_MASK                      (0x3 << 0)
-
-/* PRCM_CLKSRC_CTRL specific bits */
-
-/* PRCM_CLKOUT_CTRL */
 #define OMAP2420_CLKOUT2_EN_SHIFT                       15
-#define OMAP2420_CLKOUT2_EN_MASK                        (1 << 15)
 #define OMAP2420_CLKOUT2_DIV_SHIFT                      11
-#define OMAP2420_CLKOUT2_DIV_MASK                       (0x7 << 11)
 #define OMAP2420_CLKOUT2_DIV_WIDTH                      3
-#define OMAP2420_CLKOUT2_SOURCE_SHIFT                   8
 #define OMAP2420_CLKOUT2_SOURCE_MASK                    (0x3 << 8)
 #define OMAP24XX_CLKOUT_EN_SHIFT                        7
-#define OMAP24XX_CLKOUT_EN_MASK                         (1 << 7)
 #define OMAP24XX_CLKOUT_DIV_SHIFT                       3
-#define OMAP24XX_CLKOUT_DIV_MASK                        (0x7 << 3)
 #define OMAP24XX_CLKOUT_DIV_WIDTH                       3
-#define OMAP24XX_CLKOUT_SOURCE_SHIFT                    0
 #define OMAP24XX_CLKOUT_SOURCE_MASK                     (0x3 << 0)
-
-/* PRCM_CLKEMUL_CTRL */
 #define OMAP24XX_EMULATION_EN_SHIFT                     0
-#define OMAP24XX_EMULATION_EN_MASK                      (1 << 0)
-
-/* PRCM_CLKCFG_CTRL */
-#define OMAP24XX_VALID_CONFIG_MASK                      (1 << 0)
-
-/* PRCM_CLKCFG_STATUS */
-#define OMAP24XX_CONFIG_STATUS_MASK                     (1 << 0)
-
-/* PRCM_VOLTSETUP specific bits */
-
-/* PRCM_CLKSSETUP specific bits */
-
-/* PRCM_POLCTRL */
-#define OMAP2420_CLKOUT2_POL_MASK                       (1 << 10)
-#define OMAP24XX_CLKOUT_POL_MASK                        (1 << 9)
-#define OMAP24XX_CLKREQ_POL_MASK                        (1 << 8)
-#define OMAP2430_USE_POWEROK_MASK                       (1 << 2)
-#define OMAP2430_POWEROK_POL_MASK                       (1 << 1)
-#define OMAP24XX_EXTVOL_POL_MASK                        (1 << 0)
-
-/* RM_RSTST_MPU specific bits */
-/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */
-
-/* PM_WKDEP_MPU specific bits */
 #define OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT              5
-#define OMAP2430_PM_WKDEP_MPU_EN_MDM_MASK               (1 << 5)
 #define OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT              2
-#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_MASK               (1 << 2)
-
-/* PM_EVGENCTRL_MPU specific bits */
-
-/* PM_EVEGENONTIM_MPU specific bits */
-
-/* PM_EVEGENOFFTIM_MPU specific bits */
-
-/* PM_PWSTCTRL_MPU specific bits */
-#define OMAP2430_FORCESTATE_MASK                        (1 << 18)
-
-/* PM_PWSTST_MPU specific bits */
-/* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */
-
-/* PM_WKEN1_CORE specific bits */
-
-/* PM_WKEN2_CORE specific bits */
-
-/* PM_WKST1_CORE specific bits*/
-
-/* PM_WKST2_CORE specific bits */
-
-/* PM_WKDEP_CORE specific bits*/
-#define OMAP2430_PM_WKDEP_CORE_EN_MDM_MASK              (1 << 5)
-#define OMAP24XX_PM_WKDEP_CORE_EN_GFX_MASK              (1 << 3)
-#define OMAP24XX_PM_WKDEP_CORE_EN_DSP_MASK              (1 << 2)
-
-/* PM_PWSTCTRL_CORE specific bits */
-#define OMAP24XX_MEMORYCHANGE_MASK                      (1 << 20)
-#define OMAP24XX_MEM3ONSTATE_SHIFT                      14
-#define OMAP24XX_MEM3ONSTATE_MASK                       (0x3 << 14)
-#define OMAP24XX_MEM2ONSTATE_SHIFT                      12
-#define OMAP24XX_MEM2ONSTATE_MASK                       (0x3 << 12)
-#define OMAP24XX_MEM1ONSTATE_SHIFT                      10
-#define OMAP24XX_MEM1ONSTATE_MASK                       (0x3 << 10)
-#define OMAP24XX_MEM3RETSTATE_MASK                      (1 << 5)
-#define OMAP24XX_MEM2RETSTATE_MASK                      (1 << 4)
-#define OMAP24XX_MEM1RETSTATE_MASK                      (1 << 3)
-
-/* PM_PWSTST_CORE specific bits */
-#define OMAP24XX_MEM3STATEST_SHIFT                      14
-#define OMAP24XX_MEM3STATEST_MASK                       (0x3 << 14)
-#define OMAP24XX_MEM2STATEST_SHIFT                      12
-#define OMAP24XX_MEM2STATEST_MASK                       (0x3 << 12)
-#define OMAP24XX_MEM1STATEST_SHIFT                      10
-#define OMAP24XX_MEM1STATEST_MASK                       (0x3 << 10)
-
-/* RM_RSTCTRL_GFX */
-#define OMAP24XX_GFX_RST_MASK                           (1 << 0)
-
-/* RM_RSTST_GFX specific bits */
-#define OMAP24XX_GFX_SW_RST_MASK                        (1 << 4)
-
-/* PM_PWSTCTRL_GFX specific bits */
-
-/* PM_WKDEP_GFX specific bits */
-/* 2430 often calls EN_WAKEUP "EN_WKUP" */
-
-/* RM_RSTCTRL_WKUP specific bits */
-
-/* RM_RSTTIME_WKUP specific bits */
-
-/* RM_RSTST_WKUP specific bits */
-/* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */
 #define OMAP24XX_EXTWMPU_RST_SHIFT                      6
-#define OMAP24XX_EXTWMPU_RST_MASK                       (1 << 6)
 #define OMAP24XX_SECU_WD_RST_SHIFT                      5
-#define OMAP24XX_SECU_WD_RST_MASK                       (1 << 5)
 #define OMAP24XX_MPU_WD_RST_SHIFT                       4
-#define OMAP24XX_MPU_WD_RST_MASK                        (1 << 4)
 #define OMAP24XX_SECU_VIOL_RST_SHIFT                    3
-#define OMAP24XX_SECU_VIOL_RST_MASK                     (1 << 3)
-
-/* PM_WKEN_WKUP specific bits */
-
-/* PM_WKST_WKUP specific bits */
-
-/* RM_RSTCTRL_DSP */
-#define OMAP2420_RST_IVA_MASK                           (1 << 8)
-#define OMAP24XX_RST2_DSP_MASK                          (1 << 1)
-#define OMAP24XX_RST1_DSP_MASK                          (1 << 0)
-
-/* RM_RSTST_DSP specific bits */
-/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */
-#define OMAP2420_IVA_SW_RST_MASK                        (1 << 8)
-#define OMAP24XX_DSP_SW_RST2_MASK                       (1 << 5)
-#define OMAP24XX_DSP_SW_RST1_MASK                       (1 << 4)
-
-/* PM_WKDEP_DSP specific bits */
-
-/* PM_PWSTCTRL_DSP specific bits */
-/* 2430 only: MEMONSTATE, MEMRETSTATE */
-#define OMAP2420_MEMIONSTATE_SHIFT                      12
-#define OMAP2420_MEMIONSTATE_MASK                       (0x3 << 12)
-#define OMAP2420_MEMIRETSTATE_MASK                      (1 << 4)
-
-/* PM_PWSTST_DSP specific bits */
-/* MEMSTATEST is 2430 only */
-#define OMAP2420_MEMISTATEST_SHIFT                      12
-#define OMAP2420_MEMISTATEST_MASK                       (0x3 << 12)
-
-/* PRCM_IRQSTATUS_DSP specific bits */
-
-/* PRCM_IRQENABLE_DSP specific bits */
-
-/* RM_RSTCTRL_MDM */
-/* 2430 only */
-#define OMAP2430_PWRON1_MDM_MASK                        (1 << 1)
-#define OMAP2430_RST1_MDM_MASK                          (1 << 0)
-
-/* RM_RSTST_MDM specific bits */
-/* 2430 only */
-#define OMAP2430_MDM_SECU_VIOL_MASK                     (1 << 6)
-#define OMAP2430_MDM_SW_PWRON1_MASK                     (1 << 5)
-#define OMAP2430_MDM_SW_RST1_MASK                       (1 << 4)
-
-/* PM_WKEN_MDM */
-/* 2430 only */
-#define OMAP2430_PM_WKEN_MDM_EN_MDM_MASK                (1 << 0)
-
-/* PM_WKST_MDM specific bits */
-/* 2430 only */
-
-/* PM_WKDEP_MDM specific bits */
-/* 2430 only */
-
-/* PM_PWSTCTRL_MDM specific bits */
-/* 2430 only */
-#define OMAP2430_KILLDOMAINWKUP_MASK                    (1 << 19)
-
-/* PM_PWSTST_MDM specific bits */
-/* 2430 only */
-
-/* PRCM_IRQSTATUS_IVA */
-/* 2420 only */
-
-/* PRCM_IRQENABLE_IVA */
-/* 2420 only */
-
 #endif
diff --git a/arch/arm/mach-omap2/prm-regbits-33xx.h b/arch/arm/mach-omap2/prm-regbits-33xx.h
index 0221b5c20e87..84feecee4fe6 100644
--- a/arch/arm/mach-omap2/prm-regbits-33xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-33xx.h
@@ -18,340 +18,35 @@
 
 #include "prm.h"
 
-/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
-#define AM33XX_ABBOFF_ACT_EXPORT_SHIFT                  1
-#define AM33XX_ABBOFF_ACT_EXPORT_MASK                   (1 << 1)
-
-/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
-#define AM33XX_ABBOFF_SLEEP_EXPORT_SHIFT                2
-#define AM33XX_ABBOFF_SLEEP_EXPORT_MASK                 (1 << 2)
-
-/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
-#define AM33XX_AIPOFF_SHIFT                             8
-#define AM33XX_AIPOFF_MASK                              (1 << 8)
-
-/* Used by PM_WKUP_PWRSTST */
-#define AM33XX_DEBUGSS_MEM_STATEST_SHIFT                17
-#define AM33XX_DEBUGSS_MEM_STATEST_MASK                 (0x3 << 17)
-
-/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
-#define AM33XX_DISABLE_RTA_EXPORT_SHIFT                 0
-#define AM33XX_DISABLE_RTA_EXPORT_MASK                  (1 << 0)
-
-/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
-#define AM33XX_DPLL_CORE_RECAL_EN_SHIFT                 12
-#define AM33XX_DPLL_CORE_RECAL_EN_MASK                  (1 << 12)
-
-/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
-#define AM33XX_DPLL_CORE_RECAL_ST_SHIFT                 12
-#define AM33XX_DPLL_CORE_RECAL_ST_MASK                  (1 << 12)
-
-/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
-#define AM33XX_DPLL_DDR_RECAL_EN_SHIFT                  14
-#define AM33XX_DPLL_DDR_RECAL_EN_MASK                   (1 << 14)
-
-/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
-#define AM33XX_DPLL_DDR_RECAL_ST_SHIFT                  14
-#define AM33XX_DPLL_DDR_RECAL_ST_MASK                   (1 << 14)
-
-/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
-#define AM33XX_DPLL_DISP_RECAL_EN_SHIFT                 15
-#define AM33XX_DPLL_DISP_RECAL_EN_MASK                  (1 << 15)
-
-/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
-#define AM33XX_DPLL_DISP_RECAL_ST_SHIFT                 13
-#define AM33XX_DPLL_DISP_RECAL_ST_MASK                  (1 << 13)
-
-/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
-#define AM33XX_DPLL_MPU_RECAL_EN_SHIFT                  11
-#define AM33XX_DPLL_MPU_RECAL_EN_MASK                   (1 << 11)
-
-/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
-#define AM33XX_DPLL_MPU_RECAL_ST_SHIFT                  11
-#define AM33XX_DPLL_MPU_RECAL_ST_MASK                   (1 << 11)
-
-/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
-#define AM33XX_DPLL_PER_RECAL_EN_SHIFT                  13
-#define AM33XX_DPLL_PER_RECAL_EN_MASK                   (1 << 13)
-
-/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
-#define AM33XX_DPLL_PER_RECAL_ST_SHIFT                  15
-#define AM33XX_DPLL_PER_RECAL_ST_MASK                   (1 << 15)
-
-/* Used by RM_WKUP_RSTST */
-#define AM33XX_EMULATION_M3_RST_SHIFT                   6
-#define AM33XX_EMULATION_M3_RST_MASK                    (1 << 6)
-
-/* Used by RM_MPU_RSTST */
-#define AM33XX_EMULATION_MPU_RST_SHIFT                  5
-#define AM33XX_EMULATION_MPU_RST_MASK                   (1 << 5)
-
-/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
-#define AM33XX_ENFUNC1_EXPORT_SHIFT                     3
-#define AM33XX_ENFUNC1_EXPORT_MASK                      (1 << 3)
-
-/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
-#define AM33XX_ENFUNC3_EXPORT_SHIFT                     5
-#define AM33XX_ENFUNC3_EXPORT_MASK                      (1 << 5)
-
-/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
-#define AM33XX_ENFUNC4_SHIFT                            6
-#define AM33XX_ENFUNC4_MASK                             (1 << 6)
-
-/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
-#define AM33XX_ENFUNC5_SHIFT                            7
-#define AM33XX_ENFUNC5_MASK                             (1 << 7)
-
-/* Used by PRM_RSTST */
-#define AM33XX_EXTERNAL_WARM_RST_SHIFT                  5
-#define AM33XX_EXTERNAL_WARM_RST_MASK                   (1 << 5)
-
-/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
-#define AM33XX_FORCEWKUP_EN_SHIFT                       10
-#define AM33XX_FORCEWKUP_EN_MASK                        (1 << 10)
-
-/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
-#define AM33XX_FORCEWKUP_ST_SHIFT                       10
-#define AM33XX_FORCEWKUP_ST_MASK                        (1 << 10)
-
-/* Used by PM_GFX_PWRSTCTRL */
-#define AM33XX_GFX_MEM_ONSTATE_SHIFT                    17
 #define AM33XX_GFX_MEM_ONSTATE_MASK                     (0x3 << 17)
-
-/* Used by PM_GFX_PWRSTCTRL */
-#define AM33XX_GFX_MEM_RETSTATE_SHIFT                   6
 #define AM33XX_GFX_MEM_RETSTATE_MASK                    (1 << 6)
-
-/* Used by PM_GFX_PWRSTST */
-#define AM33XX_GFX_MEM_STATEST_SHIFT                    4
 #define AM33XX_GFX_MEM_STATEST_MASK                     (0x3 << 4)
-
-/* Used by RM_GFX_RSTCTRL, RM_GFX_RSTST */
-#define AM33XX_GFX_RST_SHIFT                            0
-#define AM33XX_GFX_RST_MASK                             (1 << 0)
-
-/* Used by PRM_RSTST */
-#define AM33XX_GLOBAL_COLD_RST_SHIFT                    0
-#define AM33XX_GLOBAL_COLD_RST_MASK                     (1 << 0)
-
-/* Used by PRM_RSTST */
-#define AM33XX_GLOBAL_WARM_SW_RST_SHIFT                 1
 #define AM33XX_GLOBAL_WARM_SW_RST_MASK                  (1 << 1)
-
-/* Used by RM_WKUP_RSTST */
-#define AM33XX_ICECRUSHER_M3_RST_SHIFT                  7
-#define AM33XX_ICECRUSHER_M3_RST_MASK                   (1 << 7)
-
-/* Used by RM_MPU_RSTST */
-#define AM33XX_ICECRUSHER_MPU_RST_SHIFT                 6
-#define AM33XX_ICECRUSHER_MPU_RST_MASK                  (1 << 6)
-
-/* Used by PRM_RSTST */
-#define AM33XX_ICEPICK_RST_SHIFT                        9
-#define AM33XX_ICEPICK_RST_MASK                         (1 << 9)
-
-/* Used by RM_PER_RSTCTRL */
-#define AM33XX_PRUSS_LRST_SHIFT                         1
-#define AM33XX_PRUSS_LRST_MASK                          (1 << 1)
-
-/* Used by PM_PER_PWRSTCTRL */
-#define AM33XX_PRUSS_MEM_ONSTATE_SHIFT                  5
+#define AM33XX_RST_GLOBAL_WARM_SW_MASK                  (1 << 0)
 #define AM33XX_PRUSS_MEM_ONSTATE_MASK                   (0x3 << 5)
-
-/* Used by PM_PER_PWRSTCTRL */
-#define AM33XX_PRUSS_MEM_RETSTATE_SHIFT                 7
 #define AM33XX_PRUSS_MEM_RETSTATE_MASK                  (1 << 7)
-
-/* Used by PM_PER_PWRSTST */
-#define AM33XX_PRUSS_MEM_STATEST_SHIFT                  23
 #define AM33XX_PRUSS_MEM_STATEST_MASK                   (0x3 << 23)
-
-/*
- * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
- * PM_WKUP_PWRSTST, PM_RTC_PWRSTST
- */
-#define AM33XX_INTRANSITION_SHIFT                       20
-#define AM33XX_INTRANSITION_MASK                        (1 << 20)
-
-/* Used by PM_CEFUSE_PWRSTST */
 #define AM33XX_LASTPOWERSTATEENTERED_SHIFT              24
 #define AM33XX_LASTPOWERSTATEENTERED_MASK               (0x3 << 24)
-
-/* Used by PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_RTC_PWRSTCTRL */
-#define AM33XX_LOGICRETSTATE_SHIFT                      2
 #define AM33XX_LOGICRETSTATE_MASK                       (1 << 2)
-
-/* Renamed from LOGICRETSTATE Used by PM_PER_PWRSTCTRL, PM_WKUP_PWRSTCTRL */
-#define AM33XX_LOGICRETSTATE_3_3_SHIFT                  3
 #define AM33XX_LOGICRETSTATE_3_3_MASK                   (1 << 3)
-
-/*
- * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
- * PM_WKUP_PWRSTST, PM_RTC_PWRSTST
- */
 #define AM33XX_LOGICSTATEST_SHIFT                       2
 #define AM33XX_LOGICSTATEST_MASK                        (1 << 2)
-
-/*
- * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
- * PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL
- */
 #define AM33XX_LOWPOWERSTATECHANGE_SHIFT                4
 #define AM33XX_LOWPOWERSTATECHANGE_MASK                 (1 << 4)
-
-/* Used by PM_MPU_PWRSTCTRL */
-#define AM33XX_MPU_L1_ONSTATE_SHIFT                     18
 #define AM33XX_MPU_L1_ONSTATE_MASK                      (0x3 << 18)
-
-/* Used by PM_MPU_PWRSTCTRL */
-#define AM33XX_MPU_L1_RETSTATE_SHIFT                    22
 #define AM33XX_MPU_L1_RETSTATE_MASK                     (1 << 22)
-
-/* Used by PM_MPU_PWRSTST */
-#define AM33XX_MPU_L1_STATEST_SHIFT                     6
 #define AM33XX_MPU_L1_STATEST_MASK                      (0x3 << 6)
-
-/* Used by PM_MPU_PWRSTCTRL */
-#define AM33XX_MPU_L2_ONSTATE_SHIFT                     20
 #define AM33XX_MPU_L2_ONSTATE_MASK                      (0x3 << 20)
-
-/* Used by PM_MPU_PWRSTCTRL */
-#define AM33XX_MPU_L2_RETSTATE_SHIFT                    23
 #define AM33XX_MPU_L2_RETSTATE_MASK                     (1 << 23)
-
-/* Used by PM_MPU_PWRSTST */
-#define AM33XX_MPU_L2_STATEST_SHIFT                     8
 #define AM33XX_MPU_L2_STATEST_MASK                      (0x3 << 8)
-
-/* Used by PM_MPU_PWRSTCTRL */
-#define AM33XX_MPU_RAM_ONSTATE_SHIFT                    16
 #define AM33XX_MPU_RAM_ONSTATE_MASK                     (0x3 << 16)
-
-/* Used by PM_MPU_PWRSTCTRL */
-#define AM33XX_MPU_RAM_RETSTATE_SHIFT                   24
 #define AM33XX_MPU_RAM_RETSTATE_MASK                    (1 << 24)
-
-/* Used by PM_MPU_PWRSTST */
-#define AM33XX_MPU_RAM_STATEST_SHIFT                    4
 #define AM33XX_MPU_RAM_STATEST_MASK                     (0x3 << 4)
-
-/* Used by PRM_RSTST */
-#define AM33XX_MPU_SECURITY_VIOL_RST_SHIFT              2
-#define AM33XX_MPU_SECURITY_VIOL_RST_MASK               (1 << 2)
-
-/* Used by PRM_SRAM_COUNT */
-#define AM33XX_PCHARGECNT_VALUE_SHIFT                   0
-#define AM33XX_PCHARGECNT_VALUE_MASK                    (0x3f << 0)
-
-/* Used by RM_PER_RSTCTRL */
-#define AM33XX_PCI_LRST_SHIFT                           0
-#define AM33XX_PCI_LRST_MASK                            (1 << 0)
-
-/* Renamed from PCI_LRST Used by RM_PER_RSTST */
-#define AM33XX_PCI_LRST_5_5_SHIFT                       5
-#define AM33XX_PCI_LRST_5_5_MASK                        (1 << 5)
-
-/* Used by PM_PER_PWRSTCTRL */
-#define AM33XX_PER_MEM_ONSTATE_SHIFT                    25
 #define AM33XX_PER_MEM_ONSTATE_MASK                     (0x3 << 25)
-
-/* Used by PM_PER_PWRSTCTRL */
-#define AM33XX_PER_MEM_RETSTATE_SHIFT                   29
 #define AM33XX_PER_MEM_RETSTATE_MASK                    (1 << 29)
-
-/* Used by PM_PER_PWRSTST */
-#define AM33XX_PER_MEM_STATEST_SHIFT                    17
 #define AM33XX_PER_MEM_STATEST_MASK                     (0x3 << 17)
-
-/*
- * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
- * PM_MPU_PWRSTCTRL
- */
-#define AM33XX_POWERSTATE_SHIFT                         0
-#define AM33XX_POWERSTATE_MASK                          (0x3 << 0)
-
-/* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST */
-#define AM33XX_POWERSTATEST_SHIFT                       0
-#define AM33XX_POWERSTATEST_MASK                        (0x3 << 0)
-
-/* Used by PM_PER_PWRSTCTRL */
-#define AM33XX_RAM_MEM_ONSTATE_SHIFT                    30
 #define AM33XX_RAM_MEM_ONSTATE_MASK                     (0x3 << 30)
-
-/* Used by PM_PER_PWRSTCTRL */
-#define AM33XX_RAM_MEM_RETSTATE_SHIFT                   27
 #define AM33XX_RAM_MEM_RETSTATE_MASK                    (1 << 27)
-
-/* Used by PM_PER_PWRSTST */
-#define AM33XX_RAM_MEM_STATEST_SHIFT                    21
 #define AM33XX_RAM_MEM_STATEST_MASK                     (0x3 << 21)
-
-/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
-#define AM33XX_RETMODE_ENABLE_SHIFT                     0
-#define AM33XX_RETMODE_ENABLE_MASK                      (1 << 0)
-
-/* Used by REVISION_PRM */
-#define AM33XX_REV_SHIFT                                0
-#define AM33XX_REV_MASK                                 (0xff << 0)
-
-/* Used by PRM_RSTTIME */
-#define AM33XX_RSTTIME1_SHIFT                           0
-#define AM33XX_RSTTIME1_MASK                            (0xff << 0)
-
-/* Used by PRM_RSTTIME */
-#define AM33XX_RSTTIME2_SHIFT                           8
-#define AM33XX_RSTTIME2_MASK                            (0x1f << 8)
-
-/* Used by PRM_RSTCTRL */
-#define AM33XX_RST_GLOBAL_COLD_SW_SHIFT                 1
-#define AM33XX_RST_GLOBAL_COLD_SW_MASK                  (1 << 1)
-
-/* Used by PRM_RSTCTRL */
-#define AM33XX_RST_GLOBAL_WARM_SW_SHIFT                 0
-#define AM33XX_RST_GLOBAL_WARM_SW_MASK                  (1 << 0)
-
-/* Used by PRM_SRAM_COUNT */
-#define AM33XX_SLPCNT_VALUE_SHIFT                       16
-#define AM33XX_SLPCNT_VALUE_MASK                        (0xff << 16)
-
-/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
-#define AM33XX_SRAMLDO_STATUS_SHIFT                     8
-#define AM33XX_SRAMLDO_STATUS_MASK                      (1 << 8)
-
-/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
-#define AM33XX_SRAM_IN_TRANSITION_SHIFT                 9
-#define AM33XX_SRAM_IN_TRANSITION_MASK                  (1 << 9)
-
-/* Used by PRM_SRAM_COUNT */
-#define AM33XX_STARTUP_COUNT_SHIFT                      24
-#define AM33XX_STARTUP_COUNT_MASK                       (0xff << 24)
-
-/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
-#define AM33XX_TRANSITION_EN_SHIFT                      8
-#define AM33XX_TRANSITION_EN_MASK                       (1 << 8)
-
-/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
-#define AM33XX_TRANSITION_ST_SHIFT                      8
-#define AM33XX_TRANSITION_ST_MASK                       (1 << 8)
-
-/* Used by PRM_SRAM_COUNT */
-#define AM33XX_VSETUPCNT_VALUE_SHIFT                    8
-#define AM33XX_VSETUPCNT_VALUE_MASK                     (0xff << 8)
-
-/* Used by PRM_RSTST */
-#define AM33XX_WDT0_RST_SHIFT                           3
-#define AM33XX_WDT0_RST_MASK                            (1 << 3)
-
-/* Used by PRM_RSTST */
-#define AM33XX_WDT1_RST_SHIFT                           4
-#define AM33XX_WDT1_RST_MASK                            (1 << 4)
-
-/* Used by RM_WKUP_RSTCTRL */
-#define AM33XX_WKUP_M3_LRST_SHIFT                       3
-#define AM33XX_WKUP_M3_LRST_MASK                        (1 << 3)
-
-/* Renamed from WKUP_M3_LRST Used by RM_WKUP_RSTST */
-#define AM33XX_WKUP_M3_LRST_5_5_SHIFT                   5
-#define AM33XX_WKUP_M3_LRST_5_5_MASK                    (1 << 5)
-
 #endif
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index b0a2142eeb91..cebad565ed37 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -16,115 +16,25 @@
 
 #include "prm3xxx.h"
 
-/* Shared register bits */
-
-/* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */
-#define OMAP3430_ON_SHIFT                               24
-#define OMAP3430_ON_MASK                                (0xff << 24)
-#define OMAP3430_ONLP_SHIFT                             16
-#define OMAP3430_ONLP_MASK                              (0xff << 16)
-#define OMAP3430_RET_SHIFT                              8
-#define OMAP3430_RET_MASK                               (0xff << 8)
-#define OMAP3430_OFF_SHIFT                              0
-#define OMAP3430_OFF_MASK                               (0xff << 0)
-
-/* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */
-#define OMAP3430_ERROROFFSET_SHIFT                      24
 #define OMAP3430_ERROROFFSET_MASK                       (0xff << 24)
-#define OMAP3430_ERRORGAIN_SHIFT                        16
 #define OMAP3430_ERRORGAIN_MASK                         (0xff << 16)
-#define OMAP3430_INITVOLTAGE_SHIFT                      8
 #define OMAP3430_INITVOLTAGE_MASK                       (0xff << 8)
 #define OMAP3430_TIMEOUTEN_MASK                         (1 << 3)
 #define OMAP3430_INITVDD_MASK                           (1 << 2)
 #define OMAP3430_FORCEUPDATE_MASK                       (1 << 1)
 #define OMAP3430_VPENABLE_MASK                          (1 << 0)
-
-/* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */
 #define OMAP3430_SMPSWAITTIMEMIN_SHIFT                  8
-#define OMAP3430_SMPSWAITTIMEMIN_MASK                   (0xffff << 8)
 #define OMAP3430_VSTEPMIN_SHIFT                         0
-#define OMAP3430_VSTEPMIN_MASK                          (0xff << 0)
-
-/* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */
 #define OMAP3430_SMPSWAITTIMEMAX_SHIFT                  8
-#define OMAP3430_SMPSWAITTIMEMAX_MASK                   (0xffff << 8)
 #define OMAP3430_VSTEPMAX_SHIFT                         0
-#define OMAP3430_VSTEPMAX_MASK                          (0xff << 0)
-
-/* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */
 #define OMAP3430_VDDMAX_SHIFT                           24
-#define OMAP3430_VDDMAX_MASK                            (0xff << 24)
 #define OMAP3430_VDDMIN_SHIFT                           16
-#define OMAP3430_VDDMIN_MASK                            (0xff << 16)
 #define OMAP3430_TIMEOUT_SHIFT                          0
-#define OMAP3430_TIMEOUT_MASK                           (0xffff << 0)
-
-/* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */
-#define OMAP3430_VPVOLTAGE_SHIFT                        0
 #define OMAP3430_VPVOLTAGE_MASK                         (0xff << 0)
-
-/* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */
-#define OMAP3430_VPINIDLE_MASK                          (1 << 0)
-
-/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
 #define OMAP3430_EN_PER_SHIFT                           7
-#define OMAP3430_EN_PER_MASK                            (1 << 7)
-
-/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
-#define OMAP3430_MEMORYCHANGE_MASK                      (1 << 3)
-
-/* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */
 #define OMAP3430_LOGICSTATEST_MASK                      (1 << 2)
-
-/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
 #define OMAP3430_LASTLOGICSTATEENTERED_MASK             (1 << 2)
-
-/*
- * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
- * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM,
- * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits
- */
-#define OMAP3430_LASTPOWERSTATEENTERED_SHIFT            0
 #define OMAP3430_LASTPOWERSTATEENTERED_MASK             (0x3 << 0)
-
-/* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */
-#define OMAP3430_WKUP_ST_MASK                           (1 << 0)
-
-/* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */
-#define OMAP3430_WKUP_EN_MASK                           (1 << 0)
-
-/* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */
-#define OMAP3430_GRPSEL_MMC2_MASK                       (1 << 25)
-#define OMAP3430_GRPSEL_MMC1_MASK                       (1 << 24)
-#define OMAP3430_GRPSEL_MCSPI4_MASK                     (1 << 21)
-#define OMAP3430_GRPSEL_MCSPI3_MASK                     (1 << 20)
-#define OMAP3430_GRPSEL_MCSPI2_MASK                     (1 << 19)
-#define OMAP3430_GRPSEL_MCSPI1_MASK                     (1 << 18)
-#define OMAP3430_GRPSEL_I2C3_SHIFT                      17
-#define OMAP3430_GRPSEL_I2C3_MASK                       (1 << 17)
-#define OMAP3430_GRPSEL_I2C2_SHIFT                      16
-#define OMAP3430_GRPSEL_I2C2_MASK                       (1 << 16)
-#define OMAP3430_GRPSEL_I2C1_SHIFT                      15
-#define OMAP3430_GRPSEL_I2C1_MASK                       (1 << 15)
-#define OMAP3430_GRPSEL_UART2_MASK                      (1 << 14)
-#define OMAP3430_GRPSEL_UART1_MASK                      (1 << 13)
-#define OMAP3430_GRPSEL_GPT11_MASK                      (1 << 12)
-#define OMAP3430_GRPSEL_GPT10_MASK                      (1 << 11)
-#define OMAP3430_GRPSEL_MCBSP5_MASK                     (1 << 10)
-#define OMAP3430_GRPSEL_MCBSP1_MASK                     (1 << 9)
-#define OMAP3430_GRPSEL_HSOTGUSB_MASK                   (1 << 4)
-#define OMAP3430_GRPSEL_D2D_MASK                        (1 << 3)
-
-/*
- * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM,
- * PM_PWSTCTRL_PER shared bits
- */
-#define OMAP3430_MEMONSTATE_SHIFT                       16
-#define OMAP3430_MEMONSTATE_MASK                        (0x3 << 16)
-#define OMAP3430_MEMRETSTATE_MASK                       (1 << 8)
-
-/* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */
 #define OMAP3630_GRPSEL_UART4_MASK                      (1 << 18)
 #define OMAP3430_GRPSEL_GPIO6_MASK                      (1 << 17)
 #define OMAP3430_GRPSEL_GPIO5_MASK                      (1 << 16)
@@ -132,480 +42,89 @@
 #define OMAP3430_GRPSEL_GPIO3_MASK                      (1 << 14)
 #define OMAP3430_GRPSEL_GPIO2_MASK                      (1 << 13)
 #define OMAP3430_GRPSEL_UART3_MASK                      (1 << 11)
-#define OMAP3430_GRPSEL_GPT9_MASK                       (1 << 10)
-#define OMAP3430_GRPSEL_GPT8_MASK                       (1 << 9)
-#define OMAP3430_GRPSEL_GPT7_MASK                       (1 << 8)
-#define OMAP3430_GRPSEL_GPT6_MASK                       (1 << 7)
-#define OMAP3430_GRPSEL_GPT5_MASK                       (1 << 6)
-#define OMAP3430_GRPSEL_GPT4_MASK                       (1 << 5)
-#define OMAP3430_GRPSEL_GPT3_MASK                       (1 << 4)
-#define OMAP3430_GRPSEL_GPT2_MASK                       (1 << 3)
 #define OMAP3430_GRPSEL_MCBSP4_MASK                     (1 << 2)
 #define OMAP3430_GRPSEL_MCBSP3_MASK                     (1 << 1)
 #define OMAP3430_GRPSEL_MCBSP2_MASK                     (1 << 0)
-
-/* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */
-#define OMAP3430_GRPSEL_IO_MASK                         (1 << 8)
-#define OMAP3430_GRPSEL_SR2_MASK                        (1 << 7)
-#define OMAP3430_GRPSEL_SR1_MASK                        (1 << 6)
 #define OMAP3430_GRPSEL_GPIO1_MASK                      (1 << 3)
 #define OMAP3430_GRPSEL_GPT12_MASK                      (1 << 1)
 #define OMAP3430_GRPSEL_GPT1_MASK                       (1 << 0)
-
-/* Bits specific to each register */
-
-/* RM_RSTCTRL_IVA2 */
 #define OMAP3430_RST3_IVA2_MASK                         (1 << 2)
 #define OMAP3430_RST2_IVA2_MASK                         (1 << 1)
 #define OMAP3430_RST1_IVA2_MASK                         (1 << 0)
-
-/* RM_RSTST_IVA2 specific bits */
-#define OMAP3430_EMULATION_VSEQ_RST_MASK                (1 << 13)
-#define OMAP3430_EMULATION_VHWA_RST_MASK                (1 << 12)
-#define OMAP3430_EMULATION_IVA2_RST_MASK                (1 << 11)
-#define OMAP3430_IVA2_SW_RST3_MASK                      (1 << 10)
-#define OMAP3430_IVA2_SW_RST2_MASK                      (1 << 9)
-#define OMAP3430_IVA2_SW_RST1_MASK                      (1 << 8)
-
-/* PM_WKDEP_IVA2 specific bits */
-
-/* PM_PWSTCTRL_IVA2 specific bits */
-#define OMAP3430_L2FLATMEMONSTATE_SHIFT                 22
 #define OMAP3430_L2FLATMEMONSTATE_MASK                  (0x3 << 22)
-#define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT         20
 #define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK          (0x3 << 20)
-#define OMAP3430_L1FLATMEMONSTATE_SHIFT                 18
 #define OMAP3430_L1FLATMEMONSTATE_MASK                  (0x3 << 18)
-#define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT         16
 #define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK          (0x3 << 16)
 #define OMAP3430_L2FLATMEMRETSTATE_MASK                 (1 << 11)
 #define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK         (1 << 10)
 #define OMAP3430_L1FLATMEMRETSTATE_MASK                 (1 << 9)
 #define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK         (1 << 8)
-
-/* PM_PWSTST_IVA2 specific bits */
-#define OMAP3430_L2FLATMEMSTATEST_SHIFT                 10
 #define OMAP3430_L2FLATMEMSTATEST_MASK                  (0x3 << 10)
-#define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT         8
 #define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK          (0x3 << 8)
-#define OMAP3430_L1FLATMEMSTATEST_SHIFT                 6
 #define OMAP3430_L1FLATMEMSTATEST_MASK                  (0x3 << 6)
-#define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT         4
 #define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK          (0x3 << 4)
-
-/* PM_PREPWSTST_IVA2 specific bits */
-#define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT                10
 #define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK                 (0x3 << 10)
-#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT        8
 #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK         (0x3 << 8)
-#define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT                6
-#define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK                 (0x3 << 6)
-#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT        4
-#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK         (0x3 << 4)
-
-/* PRM_IRQSTATUS_IVA2 specific bits */
-#define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST_MASK   (1 << 2)
-#define OMAP3430_FORCEWKUP_ST_MASK                      (1 << 1)
-
-/* PRM_IRQENABLE_IVA2 specific bits */
-#define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN_MASK     (1 << 2)
-#define OMAP3430_FORCEWKUP_EN_MASK                              (1 << 1)
-
-/* PRM_REVISION specific bits */
-
-/* PRM_SYSCONFIG specific bits */
-
-/* PRM_IRQSTATUS_MPU specific bits */
 #define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT            25
-#define OMAP3430ES2_SND_PERIPH_DPLL_ST_MASK             (1 << 25)
-#define OMAP3430_VC_TIMEOUTERR_ST_MASK                  (1 << 24)
-#define OMAP3430_VC_RAERR_ST_MASK                       (1 << 23)
-#define OMAP3430_VC_SAERR_ST_MASK                       (1 << 22)
 #define OMAP3430_VP2_TRANXDONE_ST_MASK                  (1 << 21)
-#define OMAP3430_VP2_EQVALUE_ST_MASK                    (1 << 20)
-#define OMAP3430_VP2_NOSMPSACK_ST_MASK                  (1 << 19)
-#define OMAP3430_VP2_MAXVDD_ST_MASK                     (1 << 18)
-#define OMAP3430_VP2_MINVDD_ST_MASK                     (1 << 17)
-#define OMAP3430_VP2_OPPCHANGEDONE_ST_MASK              (1 << 16)
 #define OMAP3430_VP1_TRANXDONE_ST_MASK                  (1 << 15)
-#define OMAP3430_VP1_EQVALUE_ST_MASK                    (1 << 14)
-#define OMAP3430_VP1_NOSMPSACK_ST_MASK                  (1 << 13)
-#define OMAP3430_VP1_MAXVDD_ST_MASK                     (1 << 12)
-#define OMAP3430_VP1_MINVDD_ST_MASK                     (1 << 11)
-#define OMAP3430_VP1_OPPCHANGEDONE_ST_MASK              (1 << 10)
-#define OMAP3430_IO_ST_MASK                             (1 << 9)
-#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_MASK    (1 << 8)
 #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT   8
-#define OMAP3430_MPU_DPLL_ST_MASK                       (1 << 7)
 #define OMAP3430_MPU_DPLL_ST_SHIFT                      7
-#define OMAP3430_PERIPH_DPLL_ST_MASK                    (1 << 6)
 #define OMAP3430_PERIPH_DPLL_ST_SHIFT                   6
-#define OMAP3430_CORE_DPLL_ST_MASK                      (1 << 5)
 #define OMAP3430_CORE_DPLL_ST_SHIFT                     5
-#define OMAP3430_TRANSITION_ST_MASK                     (1 << 4)
-#define OMAP3430_EVGENOFF_ST_MASK                       (1 << 3)
-#define OMAP3430_EVGENON_ST_MASK                        (1 << 2)
-#define OMAP3430_FS_USB_WKUP_ST_MASK                    (1 << 1)
-
-/* PRM_IRQENABLE_MPU specific bits */
 #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT              25
-#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_MASK               (1 << 25)
-#define OMAP3430_VC_TIMEOUTERR_EN_MASK                          (1 << 24)
-#define OMAP3430_VC_RAERR_EN_MASK                               (1 << 23)
-#define OMAP3430_VC_SAERR_EN_MASK                               (1 << 22)
-#define OMAP3430_VP2_TRANXDONE_EN_MASK                          (1 << 21)
-#define OMAP3430_VP2_EQVALUE_EN_MASK                            (1 << 20)
-#define OMAP3430_VP2_NOSMPSACK_EN_MASK                          (1 << 19)
-#define OMAP3430_VP2_MAXVDD_EN_MASK                             (1 << 18)
-#define OMAP3430_VP2_MINVDD_EN_MASK                             (1 << 17)
-#define OMAP3430_VP2_OPPCHANGEDONE_EN_MASK                      (1 << 16)
-#define OMAP3430_VP1_TRANXDONE_EN_MASK                          (1 << 15)
-#define OMAP3430_VP1_EQVALUE_EN_MASK                            (1 << 14)
-#define OMAP3430_VP1_NOSMPSACK_EN_MASK                          (1 << 13)
-#define OMAP3430_VP1_MAXVDD_EN_MASK                             (1 << 12)
-#define OMAP3430_VP1_MINVDD_EN_MASK                             (1 << 11)
-#define OMAP3430_VP1_OPPCHANGEDONE_EN_MASK                      (1 << 10)
-#define OMAP3430_IO_EN_MASK                                     (1 << 9)
-#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_MASK      (1 << 8)
 #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT     8
-#define OMAP3430_MPU_DPLL_RECAL_EN_MASK                         (1 << 7)
 #define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT                        7
-#define OMAP3430_PERIPH_DPLL_RECAL_EN_MASK                      (1 << 6)
 #define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT                     6
-#define OMAP3430_CORE_DPLL_RECAL_EN_MASK                        (1 << 5)
 #define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT                       5
-#define OMAP3430_TRANSITION_EN_MASK                             (1 << 4)
-#define OMAP3430_EVGENOFF_EN_MASK                               (1 << 3)
-#define OMAP3430_EVGENON_EN_MASK                                (1 << 2)
-#define OMAP3430_FS_USB_WKUP_EN_MASK                            (1 << 1)
-
-/* RM_RSTST_MPU specific bits */
-#define OMAP3430_EMULATION_MPU_RST_MASK                 (1 << 11)
-
-/* PM_WKDEP_MPU specific bits */
 #define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT              5
-#define OMAP3430_PM_WKDEP_MPU_EN_DSS_MASK               (1 << 5)
 #define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT             2
-#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_MASK              (1 << 2)
-
-/* PM_EVGENCTRL_MPU */
-#define OMAP3430_OFFLOADMODE_SHIFT                      3
-#define OMAP3430_OFFLOADMODE_MASK                       (0x3 << 3)
-#define OMAP3430_ONLOADMODE_SHIFT                       1
-#define OMAP3430_ONLOADMODE_MASK                        (0x3 << 1)
-#define OMAP3430_ENABLE_MASK                            (1 << 0)
-
-/* PM_EVGENONTIM_MPU */
-#define OMAP3430_ONTIMEVAL_SHIFT                        0
-#define OMAP3430_ONTIMEVAL_MASK                         (0xffffffff << 0)
-
-/* PM_EVGENOFFTIM_MPU */
-#define OMAP3430_OFFTIMEVAL_SHIFT                       0
-#define OMAP3430_OFFTIMEVAL_MASK                        (0xffffffff << 0)
-
-/* PM_PWSTCTRL_MPU specific bits */
-#define OMAP3430_L2CACHEONSTATE_SHIFT                   16
-#define OMAP3430_L2CACHEONSTATE_MASK                    (0x3 << 16)
-#define OMAP3430_L2CACHERETSTATE_MASK                   (1 << 8)
-#define OMAP3430_LOGICL1CACHERETSTATE_MASK              (1 << 2)
-
-/* PM_PWSTST_MPU specific bits */
-#define OMAP3430_L2CACHESTATEST_SHIFT                   6
-#define OMAP3430_L2CACHESTATEST_MASK                    (0x3 << 6)
-#define OMAP3430_LOGICL1CACHESTATEST_MASK               (1 << 2)
-
-/* PM_PREPWSTST_MPU specific bits */
-#define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT          6
-#define OMAP3430_LASTL2CACHESTATEENTERED_MASK           (0x3 << 6)
-#define OMAP3430_LASTLOGICL1CACHESTATEENTERED_MASK      (1 << 2)
-
-/* RM_RSTCTRL_CORE */
 #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK         (1 << 1)
 #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK              (1 << 0)
-
-/* RM_RSTST_CORE specific bits */
-#define OMAP3430_MODEM_SECURITY_VIOL_RST_MASK           (1 << 10)
-#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON_MASK   (1 << 9)
-#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST_MASK        (1 << 8)
-
-/* PM_WKEN1_CORE specific bits */
-
-/* PM_MPUGRPSEL1_CORE specific bits */
-#define OMAP3430_GRPSEL_FSHOSTUSB_MASK                  (1 << 5)
-
-/* PM_IVA2GRPSEL1_CORE specific bits */
-
-/* PM_WKST1_CORE specific bits */
-
-/* PM_PWSTCTRL_CORE specific bits */
-#define OMAP3430_MEM2ONSTATE_SHIFT                      18
-#define OMAP3430_MEM2ONSTATE_MASK                       (0x3 << 18)
-#define OMAP3430_MEM1ONSTATE_SHIFT                      16
-#define OMAP3430_MEM1ONSTATE_MASK                       (0x3 << 16)
-#define OMAP3430_MEM2RETSTATE_MASK                      (1 << 9)
-#define OMAP3430_MEM1RETSTATE_MASK                      (1 << 8)
-
-/* PM_PWSTST_CORE specific bits */
-#define OMAP3430_MEM2STATEST_SHIFT                      6
-#define OMAP3430_MEM2STATEST_MASK                       (0x3 << 6)
-#define OMAP3430_MEM1STATEST_SHIFT                      4
-#define OMAP3430_MEM1STATEST_MASK                       (0x3 << 4)
-
-/* PM_PREPWSTST_CORE specific bits */
-#define OMAP3430_LASTMEM2STATEENTERED_SHIFT             6
 #define OMAP3430_LASTMEM2STATEENTERED_MASK              (0x3 << 6)
-#define OMAP3430_LASTMEM1STATEENTERED_SHIFT             4
 #define OMAP3430_LASTMEM1STATEENTERED_MASK              (0x3 << 4)
-
-/* RM_RSTST_GFX specific bits */
-
-/* PM_WKDEP_GFX specific bits */
-#define OMAP3430_PM_WKDEP_GFX_EN_IVA2_MASK              (1 << 2)
-
-/* PM_PWSTCTRL_GFX specific bits */
-
-/* PM_PWSTST_GFX specific bits */
-
-/* PM_PREPWSTST_GFX specific bits */
-
-/* PM_WKEN_WKUP specific bits */
 #define OMAP3430_EN_IO_CHAIN_MASK                       (1 << 16)
 #define OMAP3430_EN_IO_MASK                             (1 << 8)
 #define OMAP3430_EN_GPIO1_MASK                          (1 << 3)
-
-/* PM_MPUGRPSEL_WKUP specific bits */
-
-/* PM_IVA2GRPSEL_WKUP specific bits */
-
-/* PM_WKST_WKUP specific bits */
 #define OMAP3430_ST_IO_CHAIN_MASK                       (1 << 16)
 #define OMAP3430_ST_IO_MASK                             (1 << 8)
-
-/* PRM_CLKSEL */
 #define OMAP3430_SYS_CLKIN_SEL_SHIFT                    0
-#define OMAP3430_SYS_CLKIN_SEL_MASK                     (0x7 << 0)
 #define OMAP3430_SYS_CLKIN_SEL_WIDTH                    3
-
-/* PRM_CLKOUT_CTRL */
-#define OMAP3430_CLKOUT_EN_MASK                         (1 << 7)
 #define OMAP3430_CLKOUT_EN_SHIFT                        7
-
-/* RM_RSTST_DSS specific bits */
-
-/* PM_WKEN_DSS */
 #define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK                (1 << 0)
-
-/* PM_WKDEP_DSS specific bits */
-#define OMAP3430_PM_WKDEP_DSS_EN_IVA2_MASK              (1 << 2)
-
-/* PM_PWSTCTRL_DSS specific bits */
-
-/* PM_PWSTST_DSS specific bits */
-
-/* PM_PREPWSTST_DSS specific bits */
-
-/* RM_RSTST_CAM specific bits */
-
-/* PM_WKDEP_CAM specific bits */
-#define OMAP3430_PM_WKDEP_CAM_EN_IVA2_MASK              (1 << 2)
-
-/* PM_PWSTCTRL_CAM specific bits */
-
-/* PM_PWSTST_CAM specific bits */
-
-/* PM_PREPWSTST_CAM specific bits */
-
-/* PM_PWSTCTRL_USBHOST specific bits */
 #define OMAP3430ES2_SAVEANDRESTORE_SHIFT                4
-
-/* RM_RSTST_PER specific bits */
-
-/* PM_WKEN_PER specific bits */
-
-/* PM_MPUGRPSEL_PER specific bits */
-
-/* PM_IVA2GRPSEL_PER specific bits */
-
-/* PM_WKST_PER specific bits */
-
-/* PM_WKDEP_PER specific bits */
-#define OMAP3430_PM_WKDEP_PER_EN_IVA2_MASK              (1 << 2)
-
-/* PM_PWSTCTRL_PER specific bits */
-
-/* PM_PWSTST_PER specific bits */
-
-/* PM_PREPWSTST_PER specific bits */
-
-/* RM_RSTST_EMU specific bits */
-
-/* PM_PWSTST_EMU specific bits */
-
-/* PRM_VC_SMPS_SA */
 #define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT               16
 #define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK                (0x7f << 16)
 #define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT               0
 #define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK                (0x7f << 0)
-
-/* PRM_VC_SMPS_VOL_RA */
-#define OMAP3430_VOLRA1_SHIFT                           16
 #define OMAP3430_VOLRA1_MASK                            (0xff << 16)
-#define OMAP3430_VOLRA0_SHIFT                           0
 #define OMAP3430_VOLRA0_MASK                            (0xff << 0)
-
-/* PRM_VC_SMPS_CMD_RA */
-#define OMAP3430_CMDRA1_SHIFT                           16
 #define OMAP3430_CMDRA1_MASK                            (0xff << 16)
-#define OMAP3430_CMDRA0_SHIFT                           0
 #define OMAP3430_CMDRA0_MASK                            (0xff << 0)
-
-/* PRM_VC_CMD_VAL_0 specific bits */
 #define OMAP3430_VC_CMD_ON_SHIFT                        24
 #define OMAP3430_VC_CMD_ON_MASK                         (0xFF << 24)
 #define OMAP3430_VC_CMD_ONLP_SHIFT                      16
-#define OMAP3430_VC_CMD_ONLP_MASK                       (0xFF << 16)
 #define OMAP3430_VC_CMD_RET_SHIFT                       8
-#define OMAP3430_VC_CMD_RET_MASK                        (0xFF << 8)
 #define OMAP3430_VC_CMD_OFF_SHIFT                       0
-#define OMAP3430_VC_CMD_OFF_MASK                        (0xFF << 0)
-
-/* PRM_VC_CMD_VAL_1 specific bits */
-
-/* PRM_VC_CH_CONF */
-#define OMAP3430_CMD1_MASK                              (1 << 20)
-#define OMAP3430_RACEN1_MASK                            (1 << 19)
-#define OMAP3430_RAC1_MASK                              (1 << 18)
-#define OMAP3430_RAV1_MASK                              (1 << 17)
-#define OMAP3430_PRM_VC_CH_CONF_SA1_MASK                (1 << 16)
-#define OMAP3430_CMD0_MASK                              (1 << 4)
-#define OMAP3430_RACEN0_MASK                            (1 << 3)
-#define OMAP3430_RAC0_MASK                              (1 << 2)
-#define OMAP3430_RAV0_MASK                              (1 << 1)
-#define OMAP3430_PRM_VC_CH_CONF_SA0_MASK                (1 << 0)
-
-/* PRM_VC_I2C_CFG */
-#define OMAP3430_HSMASTER_MASK                          (1 << 5)
-#define OMAP3430_SREN_MASK                              (1 << 4)
 #define OMAP3430_HSEN_MASK                              (1 << 3)
-#define OMAP3430_MCODE_SHIFT                            0
 #define OMAP3430_MCODE_MASK                             (0x7 << 0)
-
-/* PRM_VC_BYPASS_VAL */
 #define OMAP3430_VALID_MASK                             (1 << 24)
 #define OMAP3430_DATA_SHIFT                             16
-#define OMAP3430_DATA_MASK                              (0xff << 16)
 #define OMAP3430_REGADDR_SHIFT                          8
-#define OMAP3430_REGADDR_MASK                           (0xff << 8)
 #define OMAP3430_SLAVEADDR_SHIFT                        0
-#define OMAP3430_SLAVEADDR_MASK                         (0x7f << 0)
-
-/* PRM_RSTCTRL */
-#define OMAP3430_RST_DPLL3_MASK                         (1 << 2)
-#define OMAP3430_RST_GS_MASK                            (1 << 1)
-
-/* PRM_RSTTIME */
-#define OMAP3430_RSTTIME2_SHIFT                         8
-#define OMAP3430_RSTTIME2_MASK                          (0x1f << 8)
-#define OMAP3430_RSTTIME1_SHIFT                         0
-#define OMAP3430_RSTTIME1_MASK                          (0xff << 0)
-
-/* PRM_RSTST */
 #define OMAP3430_ICECRUSHER_RST_SHIFT                   10
-#define OMAP3430_ICECRUSHER_RST_MASK                    (1 << 10)
 #define OMAP3430_ICEPICK_RST_SHIFT                      9
-#define OMAP3430_ICEPICK_RST_MASK                       (1 << 9)
 #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT         8
-#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_MASK          (1 << 8)
 #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT         7
-#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_MASK          (1 << 7)
 #define OMAP3430_EXTERNAL_WARM_RST_SHIFT                6
-#define OMAP3430_EXTERNAL_WARM_RST_MASK                 (1 << 6)
 #define OMAP3430_SECURE_WD_RST_SHIFT                    5
-#define OMAP3430_SECURE_WD_RST_MASK                     (1 << 5)
 #define OMAP3430_MPU_WD_RST_SHIFT                       4
-#define OMAP3430_MPU_WD_RST_MASK                        (1 << 4)
 #define OMAP3430_SECURITY_VIOL_RST_SHIFT                3
-#define OMAP3430_SECURITY_VIOL_RST_MASK                 (1 << 3)
 #define OMAP3430_GLOBAL_SW_RST_SHIFT                    1
-#define OMAP3430_GLOBAL_SW_RST_MASK                     (1 << 1)
 #define OMAP3430_GLOBAL_COLD_RST_SHIFT                  0
 #define OMAP3430_GLOBAL_COLD_RST_MASK                   (1 << 0)
-
-/* PRM_VOLTCTRL */
-#define OMAP3430_SEL_VMODE_MASK                         (1 << 4)
 #define OMAP3430_SEL_OFF_MASK                           (1 << 3)
 #define OMAP3430_AUTO_OFF_MASK                          (1 << 2)
-#define OMAP3430_AUTO_RET_MASK                          (1 << 1)
-#define OMAP3430_AUTO_SLEEP_MASK                        (1 << 0)
-
-/* PRM_SRAM_PCHARGE */
-#define OMAP3430_PCHARGE_TIME_SHIFT                     0
-#define OMAP3430_PCHARGE_TIME_MASK                      (0xff << 0)
-
-/* PRM_CLKSRC_CTRL */
-#define OMAP3430_SYSCLKDIV_SHIFT                        6
-#define OMAP3430_SYSCLKDIV_MASK                         (0x3 << 6)
-#define OMAP3430_AUTOEXTCLKMODE_SHIFT                   3
-#define OMAP3430_AUTOEXTCLKMODE_MASK                    (0x3 << 3)
-#define OMAP3430_SYSCLKSEL_SHIFT                        0
-#define OMAP3430_SYSCLKSEL_MASK                         (0x3 << 0)
-
-/* PRM_VOLTSETUP1 */
-#define OMAP3430_SETUP_TIME2_SHIFT                      16
 #define OMAP3430_SETUP_TIME2_MASK                       (0xffff << 16)
-#define OMAP3430_SETUP_TIME1_SHIFT                      0
 #define OMAP3430_SETUP_TIME1_MASK                       (0xffff << 0)
-
-/* PRM_VOLTOFFSET */
-#define OMAP3430_OFFSET_TIME_SHIFT                      0
-#define OMAP3430_OFFSET_TIME_MASK                       (0xffff << 0)
-
-/* PRM_CLKSETUP */
-#define OMAP3430_SETUP_TIME_SHIFT                       0
-#define OMAP3430_SETUP_TIME_MASK                        (0xffff << 0)
-
-/* PRM_POLCTRL */
-#define OMAP3430_OFFMODE_POL_MASK                       (1 << 3)
-#define OMAP3430_CLKOUT_POL_MASK                        (1 << 2)
-#define OMAP3430_CLKREQ_POL_MASK                        (1 << 1)
-#define OMAP3430_EXTVOL_POL_MASK                        (1 << 0)
-
-/* PRM_VOLTSETUP2 */
-#define OMAP3430_OFFMODESETUPTIME_SHIFT                 0
-#define OMAP3430_OFFMODESETUPTIME_MASK                  (0xffff << 0)
-
-/* PRM_VP1_CONFIG specific bits */
-
-/* PRM_VP1_VSTEPMIN specific bits */
-
-/* PRM_VP1_VSTEPMAX specific bits */
-
-/* PRM_VP1_VLIMITTO specific bits */
-
-/* PRM_VP1_VOLTAGE specific bits */
-
-/* PRM_VP1_STATUS specific bits */
-
-/* PRM_VP2_CONFIG specific bits */
-
-/* PRM_VP2_VSTEPMIN specific bits */
-
-/* PRM_VP2_VSTEPMAX specific bits */
-
-/* PRM_VP2_VLIMITTO specific bits */
-
-/* PRM_VP2_VOLTAGE specific bits */
-
-/* PRM_VP2_STATUS specific bits */
-
-/* RM_RSTST_NEON specific bits */
-
-/* PM_WKDEP_NEON specific bits */
-
-/* PM_PWSTCTRL_NEON specific bits */
-
-/* PM_PWSTST_NEON specific bits */
-
-/* PM_PREPWSTST_NEON specific bits */
-
 #endif
diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h
index 3cb247bebdaa..b1c7a33e00e7 100644
--- a/arch/arm/mach-omap2/prm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-44xx.h
@@ -22,2306 +22,80 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
 #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
 
-
-/*
- * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
- * PRM_LDO_SRAM_MPU_SETUP
- */
-#define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT                                1
-#define OMAP4430_ABBOFF_ACT_EXPORT_MASK                                 (1 << 1)
-
-/*
- * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
- * PRM_LDO_SRAM_MPU_SETUP
- */
-#define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT                              2
-#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK                               (1 << 2)
-
-/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_ABB_IVA_DONE_EN_SHIFT                                  31
-#define OMAP4430_ABB_IVA_DONE_EN_MASK                                   (1 << 31)
-
-/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_ABB_IVA_DONE_ST_SHIFT                                  31
-#define OMAP4430_ABB_IVA_DONE_ST_MASK                                   (1 << 31)
-
-/* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP4430_ABB_MPU_DONE_EN_SHIFT                                  7
-#define OMAP4430_ABB_MPU_DONE_EN_MASK                                   (1 << 7)
-
-/* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP4430_ABB_MPU_DONE_ST_SHIFT                                  7
-#define OMAP4430_ABB_MPU_DONE_ST_MASK                                   (1 << 7)
-
-/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
-#define OMAP4430_ACTIVE_FBB_SEL_SHIFT                                   2
-#define OMAP4430_ACTIVE_FBB_SEL_MASK                                    (1 << 2)
-
-/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
-#define OMAP4430_ACTIVE_RBB_SEL_SHIFT                                   1
-#define OMAP4430_ACTIVE_RBB_SEL_MASK                                    (1 << 1)
-
-/* Used by PM_ABE_PWRSTCTRL */
-#define OMAP4430_AESSMEM_ONSTATE_SHIFT                                  16
-#define OMAP4430_AESSMEM_ONSTATE_MASK                                   (0x3 << 16)
-
-/* Used by PM_ABE_PWRSTCTRL */
-#define OMAP4430_AESSMEM_RETSTATE_SHIFT                                 8
-#define OMAP4430_AESSMEM_RETSTATE_MASK                                  (1 << 8)
-
-/* Used by PM_ABE_PWRSTST */
-#define OMAP4430_AESSMEM_STATEST_SHIFT                                  4
-#define OMAP4430_AESSMEM_STATEST_MASK                                   (0x3 << 4)
-
-/*
- * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
- * PRM_LDO_SRAM_MPU_SETUP
- */
-#define OMAP4430_AIPOFF_SHIFT                                           8
-#define OMAP4430_AIPOFF_MASK                                            (1 << 8)
-
-/* Used by PRM_VOLTCTRL */
-#define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT                             0
-#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK                              (0x3 << 0)
-
-/* Used by PRM_VOLTCTRL */
-#define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT                              4
-#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK                               (0x3 << 4)
-
-/* Used by PRM_VOLTCTRL */
-#define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT                              2
-#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK                               (0x3 << 2)
-
-/* Used by PRM_VC_ERRST */
-#define OMAP4430_BYPS_RA_ERR_SHIFT                                      25
-#define OMAP4430_BYPS_RA_ERR_MASK                                       (1 << 25)
-
-/* Used by PRM_VC_ERRST */
-#define OMAP4430_BYPS_SA_ERR_SHIFT                                      24
-#define OMAP4430_BYPS_SA_ERR_MASK                                       (1 << 24)
-
-/* Used by PRM_VC_ERRST */
-#define OMAP4430_BYPS_TIMEOUT_ERR_SHIFT                                 26
-#define OMAP4430_BYPS_TIMEOUT_ERR_MASK                                  (1 << 26)
-
-/* Used by PRM_RSTST */
 #define OMAP4430_C2C_RST_SHIFT                                          10
-#define OMAP4430_C2C_RST_MASK                                           (1 << 10)
-
-/* Used by PM_CAM_PWRSTCTRL */
-#define OMAP4430_CAM_MEM_ONSTATE_SHIFT                                  16
-#define OMAP4430_CAM_MEM_ONSTATE_MASK                                   (0x3 << 16)
-
-/* Used by PM_CAM_PWRSTST */
-#define OMAP4430_CAM_MEM_STATEST_SHIFT                                  4
-#define OMAP4430_CAM_MEM_STATEST_MASK                                   (0x3 << 4)
-
-/* Used by PRM_CLKREQCTRL */
-#define OMAP4430_CLKREQ_COND_SHIFT                                      0
-#define OMAP4430_CLKREQ_COND_MASK                                       (0x7 << 0)
-
-/* Used by PRM_VC_VAL_SMPS_RA_CMD */
-#define OMAP4430_CMDRA_VDD_CORE_L_SHIFT                                 0
 #define OMAP4430_CMDRA_VDD_CORE_L_MASK                                  (0xff << 0)
-
-/* Used by PRM_VC_VAL_SMPS_RA_CMD */
-#define OMAP4430_CMDRA_VDD_IVA_L_SHIFT                                  8
 #define OMAP4430_CMDRA_VDD_IVA_L_MASK                                   (0xff << 8)
-
-/* Used by PRM_VC_VAL_SMPS_RA_CMD */
-#define OMAP4430_CMDRA_VDD_MPU_L_SHIFT                                  16
 #define OMAP4430_CMDRA_VDD_MPU_L_MASK                                   (0xff << 16)
-
-/* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_CMD_VDD_CORE_L_SHIFT                                   4
-#define OMAP4430_CMD_VDD_CORE_L_MASK                                    (1 << 4)
-
-/* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_CMD_VDD_IVA_L_SHIFT                                    12
-#define OMAP4430_CMD_VDD_IVA_L_MASK                                     (1 << 12)
-
-/* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_CMD_VDD_MPU_L_SHIFT                                    17
-#define OMAP4430_CMD_VDD_MPU_L_MASK                                     (1 << 17)
-
-/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT                              18
-#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK                               (0x3 << 18)
-
-/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT                             9
-#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK                              (1 << 9)
-
-/* Used by PM_CORE_PWRSTST */
-#define OMAP4430_CORE_OCMRAM_STATEST_SHIFT                              6
-#define OMAP4430_CORE_OCMRAM_STATEST_MASK                               (0x3 << 6)
-
-/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT                          16
-#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK                           (0x3 << 16)
-
-/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT                         8
-#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK                          (1 << 8)
-
-/* Used by PM_CORE_PWRSTST */
-#define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT                          4
-#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK                           (0x3 << 4)
-
-/* Used by REVISION_PRM */
-#define OMAP4430_CUSTOM_SHIFT                                           6
-#define OMAP4430_CUSTOM_MASK                                            (0x3 << 6)
-
-/* Used by PRM_VC_VAL_BYPASS */
 #define OMAP4430_DATA_SHIFT                                             16
-#define OMAP4430_DATA_MASK                                              (0xff << 16)
-
-/* Used by PRM_DEVICE_OFF_CTRL */
-#define OMAP4430_DEVICE_OFF_ENABLE_SHIFT                                0
-#define OMAP4430_DEVICE_OFF_ENABLE_MASK                                 (1 << 0)
-
-/* Used by PRM_VC_CFG_I2C_MODE */
-#define OMAP4430_DFILTEREN_SHIFT                                        6
-#define OMAP4430_DFILTEREN_MASK                                         (1 << 6)
-
-/*
- * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
- * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP
- */
-#define OMAP4430_DISABLE_RTA_EXPORT_SHIFT                               0
-#define OMAP4430_DISABLE_RTA_EXPORT_MASK                                (1 << 0)
-
-/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
-#define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT                                4
-#define OMAP4430_DPLL_ABE_RECAL_EN_MASK                                 (1 << 4)
-
-/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
-#define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT                                4
-#define OMAP4430_DPLL_ABE_RECAL_ST_MASK                                 (1 << 4)
-
-/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT                               0
-#define OMAP4430_DPLL_CORE_RECAL_EN_MASK                                (1 << 0)
-
-/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT                               0
-#define OMAP4430_DPLL_CORE_RECAL_ST_MASK                                (1 << 0)
-
-/* Used by PRM_IRQENABLE_MPU */
-#define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT                             6
-#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK                              (1 << 6)
-
-/* Used by PRM_IRQSTATUS_MPU */
-#define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT                             6
-#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK                              (1 << 6)
-
-/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
-#define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT                                2
-#define OMAP4430_DPLL_IVA_RECAL_EN_MASK                                 (1 << 2)
-
-/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
-#define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT                                2
-#define OMAP4430_DPLL_IVA_RECAL_ST_MASK                                 (1 << 2)
-
-/* Used by PRM_IRQENABLE_MPU */
-#define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT                                1
-#define OMAP4430_DPLL_MPU_RECAL_EN_MASK                                 (1 << 1)
-
-/* Used by PRM_IRQSTATUS_MPU */
-#define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT                                1
-#define OMAP4430_DPLL_MPU_RECAL_ST_MASK                                 (1 << 1)
-
-/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_DPLL_PER_RECAL_EN_SHIFT                                3
-#define OMAP4430_DPLL_PER_RECAL_EN_MASK                                 (1 << 3)
-
-/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_DPLL_PER_RECAL_ST_SHIFT                                3
-#define OMAP4430_DPLL_PER_RECAL_ST_MASK                                 (1 << 3)
-
-/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT                             7
-#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK                              (1 << 7)
-
-/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT                             7
-#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK                              (1 << 7)
-
-/* Used by PM_DSS_PWRSTCTRL */
-#define OMAP4430_DSS_MEM_ONSTATE_SHIFT                                  16
-#define OMAP4430_DSS_MEM_ONSTATE_MASK                                   (0x3 << 16)
-
-/* Used by PM_DSS_PWRSTCTRL */
-#define OMAP4430_DSS_MEM_RETSTATE_SHIFT                                 8
-#define OMAP4430_DSS_MEM_RETSTATE_MASK                                  (1 << 8)
-
-/* Used by PM_DSS_PWRSTST */
-#define OMAP4430_DSS_MEM_STATEST_SHIFT                                  4
-#define OMAP4430_DSS_MEM_STATEST_MASK                                   (0x3 << 4)
-
-/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT                             20
-#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK                              (0x3 << 20)
-
-/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT                            10
-#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK                             (1 << 10)
-
-/* Used by PM_CORE_PWRSTST */
-#define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT                             8
-#define OMAP4430_DUCATI_L2RAM_STATEST_MASK                              (0x3 << 8)
-
-/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT                          22
-#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK                           (0x3 << 22)
-
-/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT                         11
-#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK                          (1 << 11)
-
-/* Used by PM_CORE_PWRSTST */
-#define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT                          10
-#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK                           (0x3 << 10)
-
-/* Used by PRM_DEVICE_OFF_CTRL */
-#define OMAP4460_EMIF1_OFFWKUP_DISABLE_SHIFT                            8
-#define OMAP4460_EMIF1_OFFWKUP_DISABLE_MASK                             (1 << 8)
-
-/* Used by PRM_DEVICE_OFF_CTRL */
-#define OMAP4460_EMIF2_OFFWKUP_DISABLE_SHIFT                            9
-#define OMAP4460_EMIF2_OFFWKUP_DISABLE_MASK                             (1 << 9)
-
-/* Used by RM_MPU_RSTST */
-#define OMAP4430_EMULATION_RST_SHIFT                                    0
-#define OMAP4430_EMULATION_RST_MASK                                     (1 << 0)
-
-/* Used by RM_DUCATI_RSTST */
-#define OMAP4430_EMULATION_RST1ST_SHIFT                                 3
-#define OMAP4430_EMULATION_RST1ST_MASK                                  (1 << 3)
-
-/* Used by RM_DUCATI_RSTST */
-#define OMAP4430_EMULATION_RST2ST_SHIFT                                 4
-#define OMAP4430_EMULATION_RST2ST_MASK                                  (1 << 4)
-
-/* Used by RM_IVAHD_RSTST */
-#define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT                            3
-#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK                             (1 << 3)
-
-/* Used by RM_IVAHD_RSTST */
-#define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT                            4
-#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK                             (1 << 4)
-
-/* Used by PM_EMU_PWRSTCTRL */
-#define OMAP4430_EMU_BANK_ONSTATE_SHIFT                                 16
-#define OMAP4430_EMU_BANK_ONSTATE_MASK                                  (0x3 << 16)
-
-/* Used by PM_EMU_PWRSTST */
-#define OMAP4430_EMU_BANK_STATEST_SHIFT                                 4
-#define OMAP4430_EMU_BANK_STATEST_MASK                                  (0x3 << 4)
-
-/*
- * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
- * PRM_LDO_SRAM_MPU_SETUP
- */
-#define OMAP4430_ENFUNC1_EXPORT_SHIFT                                   3
-#define OMAP4430_ENFUNC1_EXPORT_MASK                                    (1 << 3)
-
-/*
- * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
- * PRM_LDO_SRAM_MPU_SETUP
- */
-#define OMAP4430_ENFUNC3_EXPORT_SHIFT                                   5
-#define OMAP4430_ENFUNC3_EXPORT_MASK                                    (1 << 5)
-
-/*
- * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
- * PRM_LDO_SRAM_MPU_SETUP
- */
-#define OMAP4430_ENFUNC4_SHIFT                                          6
-#define OMAP4430_ENFUNC4_MASK                                           (1 << 6)
-
-/*
- * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
- * PRM_LDO_SRAM_MPU_SETUP
- */
-#define OMAP4430_ENFUNC5_SHIFT                                          7
-#define OMAP4430_ENFUNC5_MASK                                           (1 << 7)
-
-/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP4430_ERRORGAIN_SHIFT                                        16
 #define OMAP4430_ERRORGAIN_MASK                                         (0xff << 16)
-
-/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP4430_ERROROFFSET_SHIFT                                      24
 #define OMAP4430_ERROROFFSET_MASK                                       (0xff << 24)
-
-/* Used by PRM_RSTST */
 #define OMAP4430_EXTERNAL_WARM_RST_SHIFT                                5
-#define OMAP4430_EXTERNAL_WARM_RST_MASK                                 (1 << 5)
-
-/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP4430_FORCEUPDATE_SHIFT                                      1
 #define OMAP4430_FORCEUPDATE_MASK                                       (1 << 1)
-
-/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
-#define OMAP4430_FORCEUPDATEWAIT_SHIFT                                  8
-#define OMAP4430_FORCEUPDATEWAIT_MASK                                   (0xffffff << 8)
-
-/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */
-#define OMAP4430_FORCEWKUP_EN_SHIFT                                     10
-#define OMAP4430_FORCEWKUP_EN_MASK                                      (1 << 10)
-
-/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */
-#define OMAP4430_FORCEWKUP_ST_SHIFT                                     10
-#define OMAP4430_FORCEWKUP_ST_MASK                                      (1 << 10)
-
-/* Used by REVISION_PRM */
-#define OMAP4430_FUNC_SHIFT                                             16
-#define OMAP4430_FUNC_MASK                                              (0xfff << 16)
-
-/* Used by PM_GFX_PWRSTCTRL */
-#define OMAP4430_GFX_MEM_ONSTATE_SHIFT                                  16
-#define OMAP4430_GFX_MEM_ONSTATE_MASK                                   (0x3 << 16)
-
-/* Used by PM_GFX_PWRSTST */
-#define OMAP4430_GFX_MEM_STATEST_SHIFT                                  4
-#define OMAP4430_GFX_MEM_STATEST_MASK                                   (0x3 << 4)
-
-/* Used by PRM_RSTST */
 #define OMAP4430_GLOBAL_COLD_RST_SHIFT                                  0
-#define OMAP4430_GLOBAL_COLD_RST_MASK                                   (1 << 0)
-
-/* Used by PRM_RSTST */
 #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT                               1
-#define OMAP4430_GLOBAL_WARM_SW_RST_MASK                                (1 << 1)
-
-/* Used by PRM_IO_PMCTRL */
-#define OMAP4430_GLOBAL_WUEN_SHIFT                                      16
 #define OMAP4430_GLOBAL_WUEN_MASK                                       (1 << 16)
-
-/* Used by PRM_VC_CFG_I2C_MODE */
-#define OMAP4430_HSMCODE_SHIFT                                          0
 #define OMAP4430_HSMCODE_MASK                                           (0x7 << 0)
-
-/* Used by PRM_VC_CFG_I2C_MODE */
-#define OMAP4430_HSMODEEN_SHIFT                                         3
 #define OMAP4430_HSMODEEN_MASK                                          (1 << 3)
-
-/* Used by PRM_VC_CFG_I2C_CLK */
-#define OMAP4430_HSSCLH_SHIFT                                           16
-#define OMAP4430_HSSCLH_MASK                                            (0xff << 16)
-
-/* Used by PRM_VC_CFG_I2C_CLK */
 #define OMAP4430_HSSCLL_SHIFT                                           24
-#define OMAP4430_HSSCLL_MASK                                            (0xff << 24)
-
-/* Used by PM_IVAHD_PWRSTCTRL */
-#define OMAP4430_HWA_MEM_ONSTATE_SHIFT                                  16
-#define OMAP4430_HWA_MEM_ONSTATE_MASK                                   (0x3 << 16)
-
-/* Used by PM_IVAHD_PWRSTCTRL */
-#define OMAP4430_HWA_MEM_RETSTATE_SHIFT                                 8
-#define OMAP4430_HWA_MEM_RETSTATE_MASK                                  (1 << 8)
-
-/* Used by PM_IVAHD_PWRSTST */
-#define OMAP4430_HWA_MEM_STATEST_SHIFT                                  4
-#define OMAP4430_HWA_MEM_STATEST_MASK                                   (0x3 << 4)
-
-/* Used by RM_MPU_RSTST */
-#define OMAP4430_ICECRUSHER_MPU_RST_SHIFT                               1
-#define OMAP4430_ICECRUSHER_MPU_RST_MASK                                (1 << 1)
-
-/* Used by RM_DUCATI_RSTST */
-#define OMAP4430_ICECRUSHER_RST1ST_SHIFT                                5
-#define OMAP4430_ICECRUSHER_RST1ST_MASK                                 (1 << 5)
-
-/* Used by RM_DUCATI_RSTST */
-#define OMAP4430_ICECRUSHER_RST2ST_SHIFT                                6
-#define OMAP4430_ICECRUSHER_RST2ST_MASK                                 (1 << 6)
-
-/* Used by RM_IVAHD_RSTST */
-#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT                           5
-#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK                            (1 << 5)
-
-/* Used by RM_IVAHD_RSTST */
-#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT                           6
-#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK                            (1 << 6)
-
-/* Used by PRM_RSTST */
 #define OMAP4430_ICEPICK_RST_SHIFT                                      9
-#define OMAP4430_ICEPICK_RST_MASK                                       (1 << 9)
-
-/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP4430_INITVDD_SHIFT                                          2
 #define OMAP4430_INITVDD_MASK                                           (1 << 2)
-
-/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP4430_INITVOLTAGE_SHIFT                                      8
 #define OMAP4430_INITVOLTAGE_MASK                                       (0xff << 8)
-
-/*
- * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
- * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
- * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
- */
-#define OMAP4430_INTRANSITION_SHIFT                                     20
-#define OMAP4430_INTRANSITION_MASK                                      (1 << 20)
-
-/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_IO_EN_SHIFT                                            9
-#define OMAP4430_IO_EN_MASK                                             (1 << 9)
-
-/* Used by PRM_IO_PMCTRL */
-#define OMAP4430_IO_ON_STATUS_SHIFT                                     5
-#define OMAP4430_IO_ON_STATUS_MASK                                      (1 << 5)
-
-/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_IO_ST_SHIFT                                            9
-#define OMAP4430_IO_ST_MASK                                             (1 << 9)
-
-/* Used by PRM_IO_PMCTRL */
-#define OMAP4430_ISOCLK_OVERRIDE_SHIFT                                  0
-#define OMAP4430_ISOCLK_OVERRIDE_MASK                                   (1 << 0)
-
-/* Used by PRM_IO_PMCTRL */
-#define OMAP4430_ISOCLK_STATUS_SHIFT                                    1
-#define OMAP4430_ISOCLK_STATUS_MASK                                     (1 << 1)
-
-/* Used by PRM_IO_PMCTRL */
-#define OMAP4430_ISOOVR_EXTEND_SHIFT                                    4
-#define OMAP4430_ISOOVR_EXTEND_MASK                                     (1 << 4)
-
-/* Used by PRM_IO_COUNT */
-#define OMAP4430_ISO_2_ON_TIME_SHIFT                                    0
-#define OMAP4430_ISO_2_ON_TIME_MASK                                     (0xff << 0)
-
-/* Used by PM_L3INIT_PWRSTCTRL */
-#define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT                             16
-#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK                              (0x3 << 16)
-
-/* Used by PM_L3INIT_PWRSTCTRL */
-#define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT                            8
-#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK                             (1 << 8)
-
-/* Used by PM_L3INIT_PWRSTST */
-#define OMAP4430_L3INIT_BANK1_STATEST_SHIFT                             4
-#define OMAP4430_L3INIT_BANK1_STATEST_MASK                              (0x3 << 4)
-
-/*
- * Used by PM_ABE_PWRSTST, PM_CORE_PWRSTST, PM_IVAHD_PWRSTST,
- * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
- */
 #define OMAP4430_LASTPOWERSTATEENTERED_SHIFT                            24
 #define OMAP4430_LASTPOWERSTATEENTERED_MASK                             (0x3 << 24)
-
-/*
- * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL,
- * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
- * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
- */
 #define OMAP4430_LOGICRETSTATE_SHIFT                                    2
 #define OMAP4430_LOGICRETSTATE_MASK                                     (1 << 2)
-
-/*
- * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
- * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
- * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
- */
 #define OMAP4430_LOGICSTATEST_SHIFT                                     2
 #define OMAP4430_LOGICSTATEST_MASK                                      (1 << 2)
-
-/*
- * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT,
- * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT,
- * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT,
- * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT,
- * RM_ABE_WDT3_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, RM_ALWON_SR_CORE_CONTEXT,
- * RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, RM_CAM_FDIF_CONTEXT,
- * RM_CAM_ISS_CONTEXT, RM_CEFUSE_CEFUSE_CONTEXT, RM_D2D_SAD2D_CONTEXT,
- * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT,
- * RM_DUCATI_DUCATI_CONTEXT, RM_EMU_DEBUGSS_CONTEXT, RM_GFX_GFX_CONTEXT,
- * RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT, RM_L3INIT_CCPTX_CONTEXT,
- * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT,
- * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
- * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT,
- * RM_L3INSTR_L3_3_CONTEXT, RM_L3INSTR_L3_INSTR_CONTEXT,
- * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT,
- * RM_L3_2_OCMC_RAM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT,
- * RM_L4PER_ADC_CONTEXT, RM_L4PER_DMTIMER10_CONTEXT,
- * RM_L4PER_DMTIMER11_CONTEXT, RM_L4PER_DMTIMER2_CONTEXT,
- * RM_L4PER_DMTIMER3_CONTEXT, RM_L4PER_DMTIMER4_CONTEXT,
- * RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT,
- * RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, RM_L4PER_I2C2_CONTEXT,
- * RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, RM_L4PER_I2C5_CONTEXT,
- * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, RM_L4PER_MCASP3_CONTEXT,
- * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, RM_L4PER_MCSPI2_CONTEXT,
- * RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, RM_L4PER_MGATE_CONTEXT,
- * RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, RM_L4PER_MMCSD5_CONTEXT,
- * RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT,
- * RM_L4SEC_PKAEIP29_CONTEXT, RM_MEMIF_DLL_CONTEXT, RM_MEMIF_DLL_H_CONTEXT,
- * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT,
- * RM_MEMIF_EMIF_FW_CONTEXT, RM_MPU_MPU_CONTEXT, RM_TESLA_TESLA_CONTEXT,
- * RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, RM_WKUP_L4WKUP_CONTEXT,
- * RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, RM_WKUP_SYNCTIMER_CONTEXT,
- * RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, RM_WKUP_USIM_CONTEXT,
- * RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT
- */
-#define OMAP4430_LOSTCONTEXT_DFF_SHIFT                                  0
 #define OMAP4430_LOSTCONTEXT_DFF_MASK                                   (1 << 0)
-
-/*
- * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT,
- * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DSS_CONTEXT, RM_DUCATI_DUCATI_CONTEXT,
- * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
- * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_USB_HOST_CONTEXT,
- * RM_L3INIT_USB_HOST_FS_CONTEXT, RM_L3INIT_USB_OTG_CONTEXT,
- * RM_L3INIT_USB_TLL_CONTEXT, RM_L3INSTR_L3_3_CONTEXT,
- * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT,
- * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT,
- * RM_L4CFG_MAILBOX_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT,
- * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT,
- * RM_L4PER_I2C1_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT,
- * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
- * RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT,
- * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT,
- * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT,
- * RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT,
- * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_TESLA_TESLA_CONTEXT
- */
-#define OMAP4430_LOSTCONTEXT_RFF_SHIFT                                  1
-#define OMAP4430_LOSTCONTEXT_RFF_MASK                                   (1 << 1)
-
-/* Used by RM_ABE_AESS_CONTEXT */
-#define OMAP4430_LOSTMEM_AESSMEM_SHIFT                                  8
 #define OMAP4430_LOSTMEM_AESSMEM_MASK                                   (1 << 8)
-
-/* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */
-#define OMAP4430_LOSTMEM_CAM_MEM_SHIFT                                  8
-#define OMAP4430_LOSTMEM_CAM_MEM_MASK                                   (1 << 8)
-
-/* Used by RM_L3INSTR_OCP_WP1_CONTEXT */
-#define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT                           8
-#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK                            (1 << 8)
-
-/* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */
-#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT                       9
-#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK                        (1 << 9)
-
-/* Used by RM_L3_2_OCMC_RAM_CONTEXT */
-#define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT                              8
-#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK                               (1 << 8)
-
-/*
- * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT,
- * RM_SDMA_SDMA_CONTEXT
- */
-#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT                          8
-#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK                           (1 << 8)
-
-/* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */
-#define OMAP4430_LOSTMEM_DSS_MEM_SHIFT                                  8
-#define OMAP4430_LOSTMEM_DSS_MEM_MASK                                   (1 << 8)
-
-/* Used by RM_DUCATI_DUCATI_CONTEXT */
-#define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT                             9
-#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK                              (1 << 9)
-
-/* Used by RM_DUCATI_DUCATI_CONTEXT */
-#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT                          8
-#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK                           (1 << 8)
-
-/* Used by RM_EMU_DEBUGSS_CONTEXT */
-#define OMAP4430_LOSTMEM_EMU_BANK_SHIFT                                 8
-#define OMAP4430_LOSTMEM_EMU_BANK_MASK                                  (1 << 8)
-
-/* Used by RM_GFX_GFX_CONTEXT */
-#define OMAP4430_LOSTMEM_GFX_MEM_SHIFT                                  8
-#define OMAP4430_LOSTMEM_GFX_MEM_MASK                                   (1 << 8)
-
-/* Used by RM_IVAHD_IVAHD_CONTEXT */
-#define OMAP4430_LOSTMEM_HWA_MEM_SHIFT                                  10
-#define OMAP4430_LOSTMEM_HWA_MEM_MASK                                   (1 << 10)
-
-/*
- * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT,
- * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
- * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, RM_L3INIT_SATA_CONTEXT,
- * RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
- * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT
- */
-#define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT                             8
-#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK                              (1 << 8)
-
-/* Used by RM_MPU_MPU_CONTEXT */
-#define OMAP4430_LOSTMEM_MPU_L1_SHIFT                                   8
-#define OMAP4430_LOSTMEM_MPU_L1_MASK                                    (1 << 8)
-
-/* Used by RM_MPU_MPU_CONTEXT */
-#define OMAP4430_LOSTMEM_MPU_L2_SHIFT                                   9
-#define OMAP4430_LOSTMEM_MPU_L2_MASK                                    (1 << 9)
-
-/* Used by RM_MPU_MPU_CONTEXT */
-#define OMAP4430_LOSTMEM_MPU_RAM_SHIFT                                  10
-#define OMAP4430_LOSTMEM_MPU_RAM_MASK                                   (1 << 10)
-
-/*
- * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT,
- * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT,
- * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT
- */
-#define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT                         8
-#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK                          (1 << 8)
-
-/*
- * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT,
- * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT
- */
-#define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT                                8
-#define OMAP4430_LOSTMEM_PERIHPMEM_MASK                                 (1 << 8)
-
-/*
- * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT,
- * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
- * RM_L4SEC_CRYPTODMA_CONTEXT
- */
-#define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT                            8
-#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK                             (1 << 8)
-
-/* Used by RM_IVAHD_SL2_CONTEXT */
-#define OMAP4430_LOSTMEM_SL2_MEM_SHIFT                                  8
-#define OMAP4430_LOSTMEM_SL2_MEM_MASK                                   (1 << 8)
-
-/* Used by RM_IVAHD_IVAHD_CONTEXT */
-#define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT                                 8
-#define OMAP4430_LOSTMEM_TCM1_MEM_MASK                                  (1 << 8)
-
-/* Used by RM_IVAHD_IVAHD_CONTEXT */
-#define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT                                 9
-#define OMAP4430_LOSTMEM_TCM2_MEM_MASK                                  (1 << 9)
-
-/* Used by RM_TESLA_TESLA_CONTEXT */
-#define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT                               10
-#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK                                (1 << 10)
-
-/* Used by RM_TESLA_TESLA_CONTEXT */
-#define OMAP4430_LOSTMEM_TESLA_L1_SHIFT                                 8
-#define OMAP4430_LOSTMEM_TESLA_L1_MASK                                  (1 << 8)
-
-/* Used by RM_TESLA_TESLA_CONTEXT */
-#define OMAP4430_LOSTMEM_TESLA_L2_SHIFT                                 9
-#define OMAP4430_LOSTMEM_TESLA_L2_MASK                                  (1 << 9)
-
-/* Used by RM_WKUP_SARRAM_CONTEXT */
-#define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT                                8
-#define OMAP4430_LOSTMEM_WKUP_BANK_MASK                                 (1 << 8)
-
-/*
- * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
- * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_IVAHD_PWRSTCTRL,
- * PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
- */
 #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT                              4
 #define OMAP4430_LOWPOWERSTATECHANGE_MASK                               (1 << 4)
-
-/* Used by PRM_MODEM_IF_CTRL */
-#define OMAP4430_MODEM_READY_SHIFT                                      1
-#define OMAP4430_MODEM_READY_MASK                                       (1 << 1)
-
-/* Used by PRM_MODEM_IF_CTRL */
-#define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT                               9
-#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK                                (1 << 9)
-
-/* Used by PRM_MODEM_IF_CTRL */
-#define OMAP4430_MODEM_SLEEP_ST_SHIFT                                   16
-#define OMAP4430_MODEM_SLEEP_ST_MASK                                    (1 << 16)
-
-/* Used by PRM_MODEM_IF_CTRL */
-#define OMAP4430_MODEM_WAKE_IRQ_SHIFT                                   8
-#define OMAP4430_MODEM_WAKE_IRQ_MASK                                    (1 << 8)
-
-/* Used by PM_MPU_PWRSTCTRL */
-#define OMAP4430_MPU_L1_ONSTATE_SHIFT                                   16
-#define OMAP4430_MPU_L1_ONSTATE_MASK                                    (0x3 << 16)
-
-/* Used by PM_MPU_PWRSTCTRL */
-#define OMAP4430_MPU_L1_RETSTATE_SHIFT                                  8
-#define OMAP4430_MPU_L1_RETSTATE_MASK                                   (1 << 8)
-
-/* Used by PM_MPU_PWRSTST */
-#define OMAP4430_MPU_L1_STATEST_SHIFT                                   4
-#define OMAP4430_MPU_L1_STATEST_MASK                                    (0x3 << 4)
-
-/* Used by PM_MPU_PWRSTCTRL */
-#define OMAP4430_MPU_L2_ONSTATE_SHIFT                                   18
-#define OMAP4430_MPU_L2_ONSTATE_MASK                                    (0x3 << 18)
-
-/* Used by PM_MPU_PWRSTCTRL */
-#define OMAP4430_MPU_L2_RETSTATE_SHIFT                                  9
-#define OMAP4430_MPU_L2_RETSTATE_MASK                                   (1 << 9)
-
-/* Used by PM_MPU_PWRSTST */
-#define OMAP4430_MPU_L2_STATEST_SHIFT                                   6
-#define OMAP4430_MPU_L2_STATEST_MASK                                    (0x3 << 6)
-
-/* Used by PM_MPU_PWRSTCTRL */
-#define OMAP4430_MPU_RAM_ONSTATE_SHIFT                                  20
-#define OMAP4430_MPU_RAM_ONSTATE_MASK                                   (0x3 << 20)
-
-/* Used by PM_MPU_PWRSTCTRL */
-#define OMAP4430_MPU_RAM_RETSTATE_SHIFT                                 10
-#define OMAP4430_MPU_RAM_RETSTATE_MASK                                  (1 << 10)
-
-/* Used by PM_MPU_PWRSTST */
-#define OMAP4430_MPU_RAM_STATEST_SHIFT                                  8
-#define OMAP4430_MPU_RAM_STATEST_MASK                                   (0x3 << 8)
-
-/* Used by PRM_RSTST */
 #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT                            2
-#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK                             (1 << 2)
-
-/* Used by PRM_RSTST */
 #define OMAP4430_MPU_WDT_RST_SHIFT                                      3
-#define OMAP4430_MPU_WDT_RST_MASK                                       (1 << 3)
-
-/* Used by PM_L4PER_PWRSTCTRL */
-#define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT                         18
-#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK                          (0x3 << 18)
-
-/* Used by PM_L4PER_PWRSTCTRL */
-#define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT                        9
-#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK                         (1 << 9)
-
-/* Used by PM_L4PER_PWRSTST */
-#define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT                         6
-#define OMAP4430_NONRETAINED_BANK_STATEST_MASK                          (0x3 << 6)
-
-/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT                            24
 #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK                             (0x3 << 24)
-
-/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT                           12
 #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK                            (1 << 12)
-
-/* Used by PM_CORE_PWRSTST */
-#define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT                            12
 #define OMAP4430_OCP_NRET_BANK_STATEST_MASK                             (0x3 << 12)
-
-/*
- * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
- * PRM_VC_VAL_CMD_VDD_MPU_L
- */
 #define OMAP4430_OFF_SHIFT                                              0
-#define OMAP4430_OFF_MASK                                               (0xff << 0)
-
-/*
- * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
- * PRM_VC_VAL_CMD_VDD_MPU_L
- */
 #define OMAP4430_ON_SHIFT                                               24
 #define OMAP4430_ON_MASK                                                (0xff << 24)
-
-/*
- * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
- * PRM_VC_VAL_CMD_VDD_MPU_L
- */
 #define OMAP4430_ONLP_SHIFT                                             16
-#define OMAP4430_ONLP_MASK                                              (0xff << 16)
-
-/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
-#define OMAP4430_OPP_CHANGE_SHIFT                                       2
-#define OMAP4430_OPP_CHANGE_MASK                                        (1 << 2)
-
-/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
-#define OMAP4430_OPP_SEL_SHIFT                                          0
-#define OMAP4430_OPP_SEL_MASK                                           (0x3 << 0)
-
-/* Used by PRM_SRAM_COUNT */
-#define OMAP4430_PCHARGECNT_VALUE_SHIFT                                 0
-#define OMAP4430_PCHARGECNT_VALUE_MASK                                  (0x3f << 0)
-
-/* Used by PRM_PSCON_COUNT */
-#define OMAP4430_PCHARGE_TIME_SHIFT                                     0
-#define OMAP4430_PCHARGE_TIME_MASK                                      (0xff << 0)
-
-/* Used by PM_ABE_PWRSTCTRL */
-#define OMAP4430_PERIPHMEM_ONSTATE_SHIFT                                20
-#define OMAP4430_PERIPHMEM_ONSTATE_MASK                                 (0x3 << 20)
-
-/* Used by PM_ABE_PWRSTCTRL */
-#define OMAP4430_PERIPHMEM_RETSTATE_SHIFT                               10
-#define OMAP4430_PERIPHMEM_RETSTATE_MASK                                (1 << 10)
-
-/* Used by PM_ABE_PWRSTST */
-#define OMAP4430_PERIPHMEM_STATEST_SHIFT                                8
-#define OMAP4430_PERIPHMEM_STATEST_MASK                                 (0x3 << 8)
-
-/* Used by PRM_PHASE1_CNDP */
-#define OMAP4430_PHASE1_CNDP_SHIFT                                      0
-#define OMAP4430_PHASE1_CNDP_MASK                                       (0xffffffff << 0)
-
-/* Used by PRM_PHASE2A_CNDP */
-#define OMAP4430_PHASE2A_CNDP_SHIFT                                     0
-#define OMAP4430_PHASE2A_CNDP_MASK                                      (0xffffffff << 0)
-
-/* Used by PRM_PHASE2B_CNDP */
-#define OMAP4430_PHASE2B_CNDP_SHIFT                                     0
-#define OMAP4430_PHASE2B_CNDP_MASK                                      (0xffffffff << 0)
-
-/* Used by PRM_PSCON_COUNT */
-#define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT                            8
-#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK                             (0xff << 8)
-
-/*
- * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
- * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EMU_PWRSTCTRL, PM_GFX_PWRSTCTRL,
- * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
- * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
- */
-#define OMAP4430_POWERSTATE_SHIFT                                       0
-#define OMAP4430_POWERSTATE_MASK                                        (0x3 << 0)
-
-/*
- * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
- * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
- * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
- */
-#define OMAP4430_POWERSTATEST_SHIFT                                     0
-#define OMAP4430_POWERSTATEST_MASK                                      (0x3 << 0)
-
-/* Used by PRM_PWRREQCTRL */
-#define OMAP4430_PWRREQ_COND_SHIFT                                      0
-#define OMAP4430_PWRREQ_COND_MASK                                       (0x3 << 0)
-
-/* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_RACEN_VDD_CORE_L_SHIFT                                 3
-#define OMAP4430_RACEN_VDD_CORE_L_MASK                                  (1 << 3)
-
-/* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_RACEN_VDD_IVA_L_SHIFT                                  11
-#define OMAP4430_RACEN_VDD_IVA_L_MASK                                   (1 << 11)
-
-/* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_RACEN_VDD_MPU_L_SHIFT                                  20
-#define OMAP4430_RACEN_VDD_MPU_L_MASK                                   (1 << 20)
-
-/* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_RAC_VDD_CORE_L_SHIFT                                   2
-#define OMAP4430_RAC_VDD_CORE_L_MASK                                    (1 << 2)
-
-/* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_RAC_VDD_IVA_L_SHIFT                                    10
-#define OMAP4430_RAC_VDD_IVA_L_MASK                                     (1 << 10)
-
-/* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_RAC_VDD_MPU_L_SHIFT                                    19
-#define OMAP4430_RAC_VDD_MPU_L_MASK                                     (1 << 19)
-
-/*
- * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
- * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
- * PRM_VOLTSETUP_MPU_RET_SLEEP
- */
 #define OMAP4430_RAMP_DOWN_COUNT_SHIFT                                  16
-#define OMAP4430_RAMP_DOWN_COUNT_MASK                                   (0x3f << 16)
-
-/*
- * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
- * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
- * PRM_VOLTSETUP_MPU_RET_SLEEP
- */
-#define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT                                24
-#define OMAP4430_RAMP_DOWN_PRESCAL_MASK                                 (0x3 << 24)
-
-/*
- * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
- * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
- * PRM_VOLTSETUP_MPU_RET_SLEEP
- */
 #define OMAP4430_RAMP_UP_COUNT_SHIFT                                    0
-#define OMAP4430_RAMP_UP_COUNT_MASK                                     (0x3f << 0)
-
-/*
- * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
- * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
- * PRM_VOLTSETUP_MPU_RET_SLEEP
- */
 #define OMAP4430_RAMP_UP_PRESCAL_SHIFT                                  8
-#define OMAP4430_RAMP_UP_PRESCAL_MASK                                   (0x3 << 8)
-
-/* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_RAV_VDD_CORE_L_SHIFT                                   1
-#define OMAP4430_RAV_VDD_CORE_L_MASK                                    (1 << 1)
-
-/* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_RAV_VDD_IVA_L_SHIFT                                    9
-#define OMAP4430_RAV_VDD_IVA_L_MASK                                     (1 << 9)
-
-/* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_RAV_VDD_MPU_L_SHIFT                                    18
-#define OMAP4430_RAV_VDD_MPU_L_MASK                                     (1 << 18)
-
-/* Used by PRM_VC_VAL_BYPASS */
 #define OMAP4430_REGADDR_SHIFT                                          8
-#define OMAP4430_REGADDR_MASK                                           (0xff << 8)
-
-/*
- * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
- * PRM_VC_VAL_CMD_VDD_MPU_L
- */
 #define OMAP4430_RET_SHIFT                                              8
-#define OMAP4430_RET_MASK                                               (0xff << 8)
-
-/* Used by PM_L4PER_PWRSTCTRL */
-#define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT                            16
-#define OMAP4430_RETAINED_BANK_ONSTATE_MASK                             (0x3 << 16)
-
-/* Used by PM_L4PER_PWRSTCTRL */
-#define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT                           8
-#define OMAP4430_RETAINED_BANK_RETSTATE_MASK                            (1 << 8)
-
-/* Used by PM_L4PER_PWRSTST */
-#define OMAP4430_RETAINED_BANK_STATEST_SHIFT                            4
-#define OMAP4430_RETAINED_BANK_STATEST_MASK                             (0x3 << 4)
-
-/*
- * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
- * PRM_LDO_SRAM_MPU_CTRL
- */
-#define OMAP4430_RETMODE_ENABLE_SHIFT                                   0
-#define OMAP4430_RETMODE_ENABLE_MASK                                    (1 << 0)
-
-/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */
-#define OMAP4430_RST1_SHIFT                                             0
-#define OMAP4430_RST1_MASK                                              (1 << 0)
-
-/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */
-#define OMAP4430_RST1ST_SHIFT                                           0
-#define OMAP4430_RST1ST_MASK                                            (1 << 0)
-
-/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */
-#define OMAP4430_RST2_SHIFT                                             1
-#define OMAP4430_RST2_MASK                                              (1 << 1)
-
-/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */
-#define OMAP4430_RST2ST_SHIFT                                           1
-#define OMAP4430_RST2ST_MASK                                            (1 << 1)
-
-/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */
-#define OMAP4430_RST3_SHIFT                                             2
-#define OMAP4430_RST3_MASK                                              (1 << 2)
-
-/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */
-#define OMAP4430_RST3ST_SHIFT                                           2
-#define OMAP4430_RST3ST_MASK                                            (1 << 2)
-
-/* Used by PRM_RSTTIME */
-#define OMAP4430_RSTTIME1_SHIFT                                         0
-#define OMAP4430_RSTTIME1_MASK                                          (0x3ff << 0)
-
-/* Used by PRM_RSTTIME */
-#define OMAP4430_RSTTIME2_SHIFT                                         10
-#define OMAP4430_RSTTIME2_MASK                                          (0x1f << 10)
-
-/* Used by PRM_RSTCTRL */
-#define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT                               1
-#define OMAP4430_RST_GLOBAL_COLD_SW_MASK                                (1 << 1)
-
-/* Used by PRM_RSTCTRL */
-#define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT                               0
 #define OMAP4430_RST_GLOBAL_WARM_SW_MASK                                (1 << 0)
-
-/* Used by REVISION_PRM */
-#define OMAP4430_R_RTL_SHIFT                                            11
-#define OMAP4430_R_RTL_MASK                                             (0x1f << 11)
-
-/* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_SA_VDD_CORE_L_SHIFT                                    0
-#define OMAP4430_SA_VDD_CORE_L_MASK                                     (1 << 0)
-
-/* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */
-#define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT                                0
 #define OMAP4430_SA_VDD_CORE_L_0_6_MASK                                 (0x7f << 0)
-
-/* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_SA_VDD_IVA_L_SHIFT                                     8
-#define OMAP4430_SA_VDD_IVA_L_MASK                                      (1 << 8)
-
-/* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */
-#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT                      8
 #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK                       (0x7f << 8)
-
-/* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_SA_VDD_MPU_L_SHIFT                                     16
-#define OMAP4430_SA_VDD_MPU_L_MASK                                      (1 << 16)
-
-/* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */
-#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT                      16
 #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK                       (0x7f << 16)
-
-/* Used by REVISION_PRM */
-#define OMAP4430_SCHEME_SHIFT                                           30
-#define OMAP4430_SCHEME_MASK                                            (0x3 << 30)
-
-/* Used by PRM_VC_CFG_I2C_CLK */
 #define OMAP4430_SCLH_SHIFT                                             0
-#define OMAP4430_SCLH_MASK                                              (0xff << 0)
-
-/* Used by PRM_VC_CFG_I2C_CLK */
 #define OMAP4430_SCLL_SHIFT                                             8
-#define OMAP4430_SCLL_MASK                                              (0xff << 8)
-
-/* Used by PRM_RSTST */
 #define OMAP4430_SECURE_WDT_RST_SHIFT                                   4
-#define OMAP4430_SECURE_WDT_RST_MASK                                    (1 << 4)
-
-/* Used by PM_IVAHD_PWRSTCTRL */
-#define OMAP4430_SL2_MEM_ONSTATE_SHIFT                                  18
-#define OMAP4430_SL2_MEM_ONSTATE_MASK                                   (0x3 << 18)
-
-/* Used by PM_IVAHD_PWRSTCTRL */
-#define OMAP4430_SL2_MEM_RETSTATE_SHIFT                                 9
-#define OMAP4430_SL2_MEM_RETSTATE_MASK                                  (1 << 9)
-
-/* Used by PM_IVAHD_PWRSTST */
-#define OMAP4430_SL2_MEM_STATEST_SHIFT                                  6
-#define OMAP4430_SL2_MEM_STATEST_MASK                                   (0x3 << 6)
-
-/* Used by PRM_VC_VAL_BYPASS */
 #define OMAP4430_SLAVEADDR_SHIFT                                        0
-#define OMAP4430_SLAVEADDR_MASK                                         (0x7f << 0)
-
-/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
-#define OMAP4430_SLEEP_RBB_SEL_SHIFT                                    3
-#define OMAP4430_SLEEP_RBB_SEL_MASK                                     (1 << 3)
-
-/* Used by PRM_SRAM_COUNT */
-#define OMAP4430_SLPCNT_VALUE_SHIFT                                     16
-#define OMAP4430_SLPCNT_VALUE_MASK                                      (0xff << 16)
-
-/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
 #define OMAP4430_SMPSWAITTIMEMAX_SHIFT                                  8
-#define OMAP4430_SMPSWAITTIMEMAX_MASK                                   (0xffff << 8)
-
-/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
 #define OMAP4430_SMPSWAITTIMEMIN_SHIFT                                  8
-#define OMAP4430_SMPSWAITTIMEMIN_MASK                                   (0xffff << 8)
-
-/* Used by PRM_VC_ERRST */
-#define OMAP4430_SMPS_RA_ERR_CORE_SHIFT                                 1
-#define OMAP4430_SMPS_RA_ERR_CORE_MASK                                  (1 << 1)
-
-/* Used by PRM_VC_ERRST */
-#define OMAP4430_SMPS_RA_ERR_IVA_SHIFT                                  9
-#define OMAP4430_SMPS_RA_ERR_IVA_MASK                                   (1 << 9)
-
-/* Used by PRM_VC_ERRST */
-#define OMAP4430_SMPS_RA_ERR_MPU_SHIFT                                  17
-#define OMAP4430_SMPS_RA_ERR_MPU_MASK                                   (1 << 17)
-
-/* Used by PRM_VC_ERRST */
-#define OMAP4430_SMPS_SA_ERR_CORE_SHIFT                                 0
-#define OMAP4430_SMPS_SA_ERR_CORE_MASK                                  (1 << 0)
-
-/* Used by PRM_VC_ERRST */
-#define OMAP4430_SMPS_SA_ERR_IVA_SHIFT                                  8
-#define OMAP4430_SMPS_SA_ERR_IVA_MASK                                   (1 << 8)
-
-/* Used by PRM_VC_ERRST */
-#define OMAP4430_SMPS_SA_ERR_MPU_SHIFT                                  16
-#define OMAP4430_SMPS_SA_ERR_MPU_MASK                                   (1 << 16)
-
-/* Used by PRM_VC_ERRST */
-#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_SHIFT                            2
-#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_MASK                             (1 << 2)
-
-/* Used by PRM_VC_ERRST */
-#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_SHIFT                             10
-#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_MASK                              (1 << 10)
-
-/* Used by PRM_VC_ERRST */
-#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_SHIFT                             18
-#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_MASK                              (1 << 18)
-
-/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
-#define OMAP4430_SR2EN_SHIFT                                            0
-#define OMAP4430_SR2EN_MASK                                             (1 << 0)
-
-/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
-#define OMAP4430_SR2_IN_TRANSITION_SHIFT                                6
-#define OMAP4430_SR2_IN_TRANSITION_MASK                                 (1 << 6)
-
-/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
-#define OMAP4430_SR2_STATUS_SHIFT                                       3
-#define OMAP4430_SR2_STATUS_MASK                                        (0x3 << 3)
-
-/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
-#define OMAP4430_SR2_WTCNT_VALUE_SHIFT                                  8
-#define OMAP4430_SR2_WTCNT_VALUE_MASK                                   (0xff << 8)
-
-/*
- * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
- * PRM_LDO_SRAM_MPU_CTRL
- */
-#define OMAP4430_SRAMLDO_STATUS_SHIFT                                   8
-#define OMAP4430_SRAMLDO_STATUS_MASK                                    (1 << 8)
-
-/*
- * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
- * PRM_LDO_SRAM_MPU_CTRL
- */
-#define OMAP4430_SRAM_IN_TRANSITION_SHIFT                               9
-#define OMAP4430_SRAM_IN_TRANSITION_MASK                                (1 << 9)
-
-/* Used by PRM_VC_CFG_I2C_MODE */
-#define OMAP4430_SRMODEEN_SHIFT                                         4
-#define OMAP4430_SRMODEEN_MASK                                          (1 << 4)
-
-/* Used by PRM_VOLTSETUP_WARMRESET */
-#define OMAP4430_STABLE_COUNT_SHIFT                                     0
-#define OMAP4430_STABLE_COUNT_MASK                                      (0x3f << 0)
-
-/* Used by PRM_VOLTSETUP_WARMRESET */
-#define OMAP4430_STABLE_PRESCAL_SHIFT                                   8
-#define OMAP4430_STABLE_PRESCAL_MASK                                    (0x3 << 8)
-
-/* Used by PRM_LDO_BANDGAP_SETUP */
-#define OMAP4430_STARTUP_COUNT_SHIFT                                    0
-#define OMAP4430_STARTUP_COUNT_MASK                                     (0xff << 0)
-
-/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */
-#define OMAP4430_STARTUP_COUNT_24_31_SHIFT                              24
-#define OMAP4430_STARTUP_COUNT_24_31_MASK                               (0xff << 24)
-
-/* Used by PM_IVAHD_PWRSTCTRL */
-#define OMAP4430_TCM1_MEM_ONSTATE_SHIFT                                 20
-#define OMAP4430_TCM1_MEM_ONSTATE_MASK                                  (0x3 << 20)
-
-/* Used by PM_IVAHD_PWRSTCTRL */
-#define OMAP4430_TCM1_MEM_RETSTATE_SHIFT                                10
-#define OMAP4430_TCM1_MEM_RETSTATE_MASK                                 (1 << 10)
-
-/* Used by PM_IVAHD_PWRSTST */
-#define OMAP4430_TCM1_MEM_STATEST_SHIFT                                 8
-#define OMAP4430_TCM1_MEM_STATEST_MASK                                  (0x3 << 8)
-
-/* Used by PM_IVAHD_PWRSTCTRL */
-#define OMAP4430_TCM2_MEM_ONSTATE_SHIFT                                 22
-#define OMAP4430_TCM2_MEM_ONSTATE_MASK                                  (0x3 << 22)
-
-/* Used by PM_IVAHD_PWRSTCTRL */
-#define OMAP4430_TCM2_MEM_RETSTATE_SHIFT                                11
-#define OMAP4430_TCM2_MEM_RETSTATE_MASK                                 (1 << 11)
-
-/* Used by PM_IVAHD_PWRSTST */
-#define OMAP4430_TCM2_MEM_STATEST_SHIFT                                 10
-#define OMAP4430_TCM2_MEM_STATEST_MASK                                  (0x3 << 10)
-
-/* Used by RM_TESLA_RSTST */
-#define OMAP4430_TESLASS_EMU_RSTST_SHIFT                                2
-#define OMAP4430_TESLASS_EMU_RSTST_MASK                                 (1 << 2)
-
-/* Used by RM_TESLA_RSTST */
-#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT                          3
-#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK                           (1 << 3)
-
-/* Used by PM_TESLA_PWRSTCTRL */
-#define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT                               20
-#define OMAP4430_TESLA_EDMA_ONSTATE_MASK                                (0x3 << 20)
-
-/* Used by PM_TESLA_PWRSTCTRL */
-#define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT                              10
-#define OMAP4430_TESLA_EDMA_RETSTATE_MASK                               (1 << 10)
-
-/* Used by PM_TESLA_PWRSTST */
-#define OMAP4430_TESLA_EDMA_STATEST_SHIFT                               8
-#define OMAP4430_TESLA_EDMA_STATEST_MASK                                (0x3 << 8)
-
-/* Used by PM_TESLA_PWRSTCTRL */
-#define OMAP4430_TESLA_L1_ONSTATE_SHIFT                                 16
-#define OMAP4430_TESLA_L1_ONSTATE_MASK                                  (0x3 << 16)
-
-/* Used by PM_TESLA_PWRSTCTRL */
-#define OMAP4430_TESLA_L1_RETSTATE_SHIFT                                8
-#define OMAP4430_TESLA_L1_RETSTATE_MASK                                 (1 << 8)
-
-/* Used by PM_TESLA_PWRSTST */
-#define OMAP4430_TESLA_L1_STATEST_SHIFT                                 4
-#define OMAP4430_TESLA_L1_STATEST_MASK                                  (0x3 << 4)
-
-/* Used by PM_TESLA_PWRSTCTRL */
-#define OMAP4430_TESLA_L2_ONSTATE_SHIFT                                 18
-#define OMAP4430_TESLA_L2_ONSTATE_MASK                                  (0x3 << 18)
-
-/* Used by PM_TESLA_PWRSTCTRL */
-#define OMAP4430_TESLA_L2_RETSTATE_SHIFT                                9
-#define OMAP4430_TESLA_L2_RETSTATE_MASK                                 (1 << 9)
-
-/* Used by PM_TESLA_PWRSTST */
-#define OMAP4430_TESLA_L2_STATEST_SHIFT                                 6
-#define OMAP4430_TESLA_L2_STATEST_MASK                                  (0x3 << 6)
-
-/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
 #define OMAP4430_TIMEOUT_SHIFT                                          0
-#define OMAP4430_TIMEOUT_MASK                                           (0xffff << 0)
-
-/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP4430_TIMEOUTEN_SHIFT                                        3
 #define OMAP4430_TIMEOUTEN_MASK                                         (1 << 3)
-
-/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_TRANSITION_EN_SHIFT                                    8
-#define OMAP4430_TRANSITION_EN_MASK                                     (1 << 8)
-
-/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_TRANSITION_ST_SHIFT                                    8
-#define OMAP4430_TRANSITION_ST_MASK                                     (1 << 8)
-
-/* Used by PRM_VC_VAL_BYPASS */
-#define OMAP4430_VALID_SHIFT                                            24
 #define OMAP4430_VALID_MASK                                             (1 << 24)
-
-/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VC_BYPASSACK_EN_SHIFT                                  14
-#define OMAP4430_VC_BYPASSACK_EN_MASK                                   (1 << 14)
-
-/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VC_BYPASSACK_ST_SHIFT                                  14
-#define OMAP4430_VC_BYPASSACK_ST_MASK                                   (1 << 14)
-
-/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VC_CORE_VPACK_EN_SHIFT                                 22
-#define OMAP4430_VC_CORE_VPACK_EN_MASK                                  (1 << 22)
-
-/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VC_CORE_VPACK_ST_SHIFT                                 22
-#define OMAP4430_VC_CORE_VPACK_ST_MASK                                  (1 << 22)
-
-/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VC_IVA_VPACK_EN_SHIFT                                  30
-#define OMAP4430_VC_IVA_VPACK_EN_MASK                                   (1 << 30)
-
-/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VC_IVA_VPACK_ST_SHIFT                                  30
-#define OMAP4430_VC_IVA_VPACK_ST_MASK                                   (1 << 30)
-
-/* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP4430_VC_MPU_VPACK_EN_SHIFT                                  6
-#define OMAP4430_VC_MPU_VPACK_EN_MASK                                   (1 << 6)
-
-/* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP4430_VC_MPU_VPACK_ST_SHIFT                                  6
-#define OMAP4430_VC_MPU_VPACK_ST_MASK                                   (1 << 6)
-
-/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VC_RAERR_EN_SHIFT                                      12
-#define OMAP4430_VC_RAERR_EN_MASK                                       (1 << 12)
-
-/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VC_RAERR_ST_SHIFT                                      12
-#define OMAP4430_VC_RAERR_ST_MASK                                       (1 << 12)
-
-/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VC_SAERR_EN_SHIFT                                      11
-#define OMAP4430_VC_SAERR_EN_MASK                                       (1 << 11)
-
-/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VC_SAERR_ST_SHIFT                                      11
-#define OMAP4430_VC_SAERR_ST_MASK                                       (1 << 11)
-
-/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VC_TOERR_EN_SHIFT                                      13
-#define OMAP4430_VC_TOERR_EN_MASK                                       (1 << 13)
-
-/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VC_TOERR_ST_SHIFT                                      13
-#define OMAP4430_VC_TOERR_ST_MASK                                       (1 << 13)
-
-/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
 #define OMAP4430_VDDMAX_SHIFT                                           24
-#define OMAP4430_VDDMAX_MASK                                            (0xff << 24)
-
-/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
 #define OMAP4430_VDDMIN_SHIFT                                           16
-#define OMAP4430_VDDMIN_MASK                                            (0xff << 16)
-
-/* Used by PRM_VOLTCTRL */
-#define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT                             12
-#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK                              (1 << 12)
-
-/* Used by PRM_RSTST */
 #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT                            8
-#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK                             (1 << 8)
-
-/* Used by PRM_VOLTCTRL */
-#define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT                              14
-#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK                               (1 << 14)
-
-/* Used by PRM_VOLTCTRL */
-#define OMAP4430_VDD_IVA_PRESENCE_SHIFT                                 9
-#define OMAP4430_VDD_IVA_PRESENCE_MASK                                  (1 << 9)
-
-/* Used by PRM_RSTST */
 #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT                             7
-#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK                              (1 << 7)
-
-/* Used by PRM_VOLTCTRL */
-#define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT                              13
-#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK                               (1 << 13)
-
-/* Used by PRM_VOLTCTRL */
-#define OMAP4430_VDD_MPU_PRESENCE_SHIFT                                 8
-#define OMAP4430_VDD_MPU_PRESENCE_MASK                                  (1 << 8)
-
-/* Used by PRM_RSTST */
 #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT                             6
-#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK                              (1 << 6)
-
-/* Used by PRM_VC_ERRST */
-#define OMAP4430_VFSM_RA_ERR_CORE_SHIFT                                 4
-#define OMAP4430_VFSM_RA_ERR_CORE_MASK                                  (1 << 4)
-
-/* Used by PRM_VC_ERRST */
-#define OMAP4430_VFSM_RA_ERR_IVA_SHIFT                                  12
-#define OMAP4430_VFSM_RA_ERR_IVA_MASK                                   (1 << 12)
-
-/* Used by PRM_VC_ERRST */
-#define OMAP4430_VFSM_RA_ERR_MPU_SHIFT                                  20
-#define OMAP4430_VFSM_RA_ERR_MPU_MASK                                   (1 << 20)
-
-/* Used by PRM_VC_ERRST */
-#define OMAP4430_VFSM_SA_ERR_CORE_SHIFT                                 3
-#define OMAP4430_VFSM_SA_ERR_CORE_MASK                                  (1 << 3)
-
-/* Used by PRM_VC_ERRST */
-#define OMAP4430_VFSM_SA_ERR_IVA_SHIFT                                  11
-#define OMAP4430_VFSM_SA_ERR_IVA_MASK                                   (1 << 11)
-
-/* Used by PRM_VC_ERRST */
-#define OMAP4430_VFSM_SA_ERR_MPU_SHIFT                                  19
-#define OMAP4430_VFSM_SA_ERR_MPU_MASK                                   (1 << 19)
-
-/* Used by PRM_VC_ERRST */
-#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_SHIFT                            5
-#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_MASK                             (1 << 5)
-
-/* Used by PRM_VC_ERRST */
-#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_SHIFT                             13
-#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_MASK                              (1 << 13)
-
-/* Used by PRM_VC_ERRST */
-#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_SHIFT                             21
-#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_MASK                              (1 << 21)
-
-/* Used by PRM_VC_VAL_SMPS_RA_VOL */
-#define OMAP4430_VOLRA_VDD_CORE_L_SHIFT                                 0
 #define OMAP4430_VOLRA_VDD_CORE_L_MASK                                  (0xff << 0)
-
-/* Used by PRM_VC_VAL_SMPS_RA_VOL */
-#define OMAP4430_VOLRA_VDD_IVA_L_SHIFT                                  8
 #define OMAP4430_VOLRA_VDD_IVA_L_MASK                                   (0xff << 8)
-
-/* Used by PRM_VC_VAL_SMPS_RA_VOL */
-#define OMAP4430_VOLRA_VDD_MPU_L_SHIFT                                  16
 #define OMAP4430_VOLRA_VDD_MPU_L_MASK                                   (0xff << 16)
-
-/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP4430_VPENABLE_SHIFT                                         0
 #define OMAP4430_VPENABLE_MASK                                          (1 << 0)
-
-/* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */
-#define OMAP4430_VPINIDLE_SHIFT                                         0
-#define OMAP4430_VPINIDLE_MASK                                          (1 << 0)
-
-/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
-#define OMAP4430_VPVOLTAGE_SHIFT                                        0
 #define OMAP4430_VPVOLTAGE_MASK                                         (0xff << 0)
-
-/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT                               20
-#define OMAP4430_VP_CORE_EQVALUE_EN_MASK                                (1 << 20)
-
-/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT                               20
-#define OMAP4430_VP_CORE_EQVALUE_ST_MASK                                (1 << 20)
-
-/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT                                18
-#define OMAP4430_VP_CORE_MAXVDD_EN_MASK                                 (1 << 18)
-
-/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT                                18
-#define OMAP4430_VP_CORE_MAXVDD_ST_MASK                                 (1 << 18)
-
-/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_CORE_MINVDD_EN_SHIFT                                17
-#define OMAP4430_VP_CORE_MINVDD_EN_MASK                                 (1 << 17)
-
-/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_CORE_MINVDD_ST_SHIFT                                17
-#define OMAP4430_VP_CORE_MINVDD_ST_MASK                                 (1 << 17)
-
-/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT                             19
-#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK                              (1 << 19)
-
-/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT                             19
-#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK                              (1 << 19)
-
-/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT                         16
-#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK                          (1 << 16)
-
-/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT                         16
-#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK                          (1 << 16)
-
-/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT                             21
-#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK                              (1 << 21)
-
-/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT                             21
 #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK                              (1 << 21)
-
-/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT                                28
-#define OMAP4430_VP_IVA_EQVALUE_EN_MASK                                 (1 << 28)
-
-/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT                                28
-#define OMAP4430_VP_IVA_EQVALUE_ST_MASK                                 (1 << 28)
-
-/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT                                 26
-#define OMAP4430_VP_IVA_MAXVDD_EN_MASK                                  (1 << 26)
-
-/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT                                 26
-#define OMAP4430_VP_IVA_MAXVDD_ST_MASK                                  (1 << 26)
-
-/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_IVA_MINVDD_EN_SHIFT                                 25
-#define OMAP4430_VP_IVA_MINVDD_EN_MASK                                  (1 << 25)
-
-/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_IVA_MINVDD_ST_SHIFT                                 25
-#define OMAP4430_VP_IVA_MINVDD_ST_MASK                                  (1 << 25)
-
-/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT                              27
-#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK                               (1 << 27)
-
-/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT                              27
-#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK                               (1 << 27)
-
-/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT                          24
-#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK                           (1 << 24)
-
-/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT                          24
-#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK                           (1 << 24)
-
-/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT                              29
-#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK                               (1 << 29)
-
-/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT                              29
 #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK                               (1 << 29)
-
-/* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT                                4
-#define OMAP4430_VP_MPU_EQVALUE_EN_MASK                                 (1 << 4)
-
-/* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT                                4
-#define OMAP4430_VP_MPU_EQVALUE_ST_MASK                                 (1 << 4)
-
-/* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT                                 2
-#define OMAP4430_VP_MPU_MAXVDD_EN_MASK                                  (1 << 2)
-
-/* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT                                 2
-#define OMAP4430_VP_MPU_MAXVDD_ST_MASK                                  (1 << 2)
-
-/* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP4430_VP_MPU_MINVDD_EN_SHIFT                                 1
-#define OMAP4430_VP_MPU_MINVDD_EN_MASK                                  (1 << 1)
-
-/* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP4430_VP_MPU_MINVDD_ST_SHIFT                                 1
-#define OMAP4430_VP_MPU_MINVDD_ST_MASK                                  (1 << 1)
-
-/* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT                              3
-#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK                               (1 << 3)
-
-/* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT                              3
-#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK                               (1 << 3)
-
-/* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT                          0
-#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK                           (1 << 0)
-
-/* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT                          0
-#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK                           (1 << 0)
-
-/* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT                              5
-#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK                               (1 << 5)
-
-/* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT                              5
 #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK                               (1 << 5)
-
-/* Used by PRM_SRAM_COUNT */
-#define OMAP4430_VSETUPCNT_VALUE_SHIFT                                  8
-#define OMAP4430_VSETUPCNT_VALUE_MASK                                   (0xff << 8)
-
-/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
 #define OMAP4430_VSTEPMAX_SHIFT                                         0
-#define OMAP4430_VSTEPMAX_MASK                                          (0xff << 0)
-
-/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
 #define OMAP4430_VSTEPMIN_SHIFT                                         0
-#define OMAP4430_VSTEPMIN_MASK                                          (0xff << 0)
-
-/* Used by PRM_MODEM_IF_CTRL */
-#define OMAP4430_WAKE_MODEM_SHIFT                                       0
-#define OMAP4430_WAKE_MODEM_MASK                                        (1 << 0)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT                             1
-#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK                              (1 << 1)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_DISPC_MPU_MASK                                 (1 << 0)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT                               3
-#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK                                (1 << 3)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT                              2
-#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK                               (1 << 2)
-
-/* Used by PM_ABE_DMIC_WKDEP */
-#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT                            7
-#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK                             (1 << 7)
-
-/* Used by PM_ABE_DMIC_WKDEP */
-#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT                           6
-#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK                            (1 << 6)
-
-/* Used by PM_ABE_DMIC_WKDEP */
-#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK                              (1 << 0)
-
-/* Used by PM_ABE_DMIC_WKDEP */
-#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT                           2
-#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK                            (1 << 2)
-
-/* Used by PM_L4PER_DMTIMER10_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT                            0
-#define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK                             (1 << 0)
-
-/* Used by PM_L4PER_DMTIMER11_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT                         1
-#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK                          (1 << 1)
-
-/* Used by PM_L4PER_DMTIMER11_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT                            0
-#define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK                             (1 << 0)
-
-/* Used by PM_L4PER_DMTIMER2_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK                              (1 << 0)
-
-/* Used by PM_L4PER_DMTIMER3_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK                           (1 << 1)
-
-/* Used by PM_L4PER_DMTIMER3_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK                              (1 << 0)
-
-/* Used by PM_L4PER_DMTIMER4_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK                           (1 << 1)
-
-/* Used by PM_L4PER_DMTIMER4_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK                              (1 << 0)
-
-/* Used by PM_L4PER_DMTIMER9_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK                           (1 << 1)
-
-/* Used by PM_L4PER_DMTIMER9_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK                              (1 << 0)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT                              5
-#define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK                               (1 << 5)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT                                 4
-#define OMAP4430_WKUPDEP_DSI1_MPU_MASK                                  (1 << 4)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT                                7
-#define OMAP4430_WKUPDEP_DSI1_SDMA_MASK                                 (1 << 7)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT                               6
-#define OMAP4430_WKUPDEP_DSI1_TESLA_MASK                                (1 << 6)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT                              9
-#define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK                               (1 << 9)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT                                 8
-#define OMAP4430_WKUPDEP_DSI2_MPU_MASK                                  (1 << 8)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT                                11
-#define OMAP4430_WKUPDEP_DSI2_SDMA_MASK                                 (1 << 11)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT                               10
-#define OMAP4430_WKUPDEP_DSI2_TESLA_MASK                                (1 << 10)
-
-/* Used by PM_WKUP_GPIO1_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT                        1
-#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK                         (1 << 1)
-
-/* Used by PM_WKUP_GPIO1_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK                            (1 << 0)
-
-/* Used by PM_WKUP_GPIO1_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK                          (1 << 6)
-
-/* Used by PM_L4PER_GPIO2_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT                        1
-#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK                         (1 << 1)
-
-/* Used by PM_L4PER_GPIO2_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK                            (1 << 0)
-
-/* Used by PM_L4PER_GPIO2_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK                          (1 << 6)
-
-/* Used by PM_L4PER_GPIO3_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK                            (1 << 0)
-
-/* Used by PM_L4PER_GPIO3_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK                          (1 << 6)
-
-/* Used by PM_L4PER_GPIO4_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK                            (1 << 0)
-
-/* Used by PM_L4PER_GPIO4_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK                          (1 << 6)
-
-/* Used by PM_L4PER_GPIO5_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK                            (1 << 0)
-
-/* Used by PM_L4PER_GPIO5_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK                          (1 << 6)
-
-/* Used by PM_L4PER_GPIO6_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK                            (1 << 0)
-
-/* Used by PM_L4PER_GPIO6_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK                          (1 << 6)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT                             19
-#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK                              (1 << 19)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT                           13
-#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK                            (1 << 13)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT                              12
-#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK                               (1 << 12)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT                            14
-#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK                             (1 << 14)
-
-/* Used by PM_L4PER_HECC1_WKDEP */
-#define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_HECC1_MPU_MASK                                 (1 << 0)
-
-/* Used by PM_L4PER_HECC2_WKDEP */
-#define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_HECC2_MPU_MASK                                 (1 << 0)
-
-/* Used by PM_L3INIT_HSI_WKDEP */
-#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT                            6
-#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK                             (1 << 6)
-
-/* Used by PM_L3INIT_HSI_WKDEP */
-#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT                           1
-#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK                            (1 << 1)
-
-/* Used by PM_L3INIT_HSI_WKDEP */
-#define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK                               (1 << 0)
-
-/* Used by PM_L4PER_I2C1_WKDEP */
-#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT                            7
-#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK                             (1 << 7)
-
-/* Used by PM_L4PER_I2C1_WKDEP */
-#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK                           (1 << 1)
-
-/* Used by PM_L4PER_I2C1_WKDEP */
-#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK                              (1 << 0)
-
-/* Used by PM_L4PER_I2C2_WKDEP */
-#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT                            7
-#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK                             (1 << 7)
-
-/* Used by PM_L4PER_I2C2_WKDEP */
-#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK                           (1 << 1)
-
-/* Used by PM_L4PER_I2C2_WKDEP */
-#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK                              (1 << 0)
-
-/* Used by PM_L4PER_I2C3_WKDEP */
-#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT                            7
-#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK                             (1 << 7)
-
-/* Used by PM_L4PER_I2C3_WKDEP */
-#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK                           (1 << 1)
-
-/* Used by PM_L4PER_I2C3_WKDEP */
-#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK                              (1 << 0)
-
-/* Used by PM_L4PER_I2C4_WKDEP */
-#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT                            7
-#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK                             (1 << 7)
-
-/* Used by PM_L4PER_I2C4_WKDEP */
-#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK                           (1 << 1)
-
-/* Used by PM_L4PER_I2C4_WKDEP */
-#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK                              (1 << 0)
-
-/* Used by PM_L4PER_I2C5_WKDEP */
-#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT                            7
-#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK                             (1 << 7)
-
-/* Used by PM_L4PER_I2C5_WKDEP */
-#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK                              (1 << 0)
-
-/* Used by PM_WKUP_KEYBOARD_WKDEP */
-#define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK                              (1 << 0)
-
-/* Used by PM_ABE_MCASP_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT                          7
-#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK                           (1 << 7)
-
-/* Used by PM_ABE_MCASP_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK                          (1 << 6)
-
-/* Used by PM_ABE_MCASP_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK                            (1 << 0)
-
-/* Used by PM_ABE_MCASP_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT                         2
-#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK                          (1 << 2)
-
-/* Used by PM_L4PER_MCASP2_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT                          7
-#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK                           (1 << 7)
-
-/* Used by PM_L4PER_MCASP2_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK                          (1 << 6)
-
-/* Used by PM_L4PER_MCASP2_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK                            (1 << 0)
-
-/* Used by PM_L4PER_MCASP2_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT                         2
-#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK                          (1 << 2)
-
-/* Used by PM_L4PER_MCASP3_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT                          7
-#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK                           (1 << 7)
-
-/* Used by PM_L4PER_MCASP3_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK                          (1 << 6)
-
-/* Used by PM_L4PER_MCASP3_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK                            (1 << 0)
-
-/* Used by PM_L4PER_MCASP3_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT                         2
-#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK                          (1 << 2)
-
-/* Used by PM_ABE_MCBSP1_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK                                (1 << 0)
-
-/* Used by PM_ABE_MCBSP1_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK                               (1 << 3)
-
-/* Used by PM_ABE_MCBSP1_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK                              (1 << 2)
-
-/* Used by PM_ABE_MCBSP2_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK                                (1 << 0)
-
-/* Used by PM_ABE_MCBSP2_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK                               (1 << 3)
-
-/* Used by PM_ABE_MCBSP2_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK                              (1 << 2)
-
-/* Used by PM_ABE_MCBSP3_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK                                (1 << 0)
-
-/* Used by PM_ABE_MCBSP3_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK                               (1 << 3)
-
-/* Used by PM_ABE_MCBSP3_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK                              (1 << 2)
-
-/* Used by PM_L4PER_MCBSP4_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK                                (1 << 0)
-
-/* Used by PM_L4PER_MCBSP4_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK                               (1 << 3)
-
-/* Used by PM_L4PER_MCBSP4_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK                              (1 << 2)
-
-/* Used by PM_L4PER_MCSPI1_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT                            1
-#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK                             (1 << 1)
-
-/* Used by PM_L4PER_MCSPI1_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK                                (1 << 0)
-
-/* Used by PM_L4PER_MCSPI1_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK                               (1 << 3)
-
-/* Used by PM_L4PER_MCSPI1_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK                              (1 << 2)
-
-/* Used by PM_L4PER_MCSPI2_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT                            1
-#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK                             (1 << 1)
-
-/* Used by PM_L4PER_MCSPI2_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK                                (1 << 0)
-
-/* Used by PM_L4PER_MCSPI2_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK                               (1 << 3)
-
-/* Used by PM_L4PER_MCSPI3_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK                                (1 << 0)
-
-/* Used by PM_L4PER_MCSPI3_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK                               (1 << 3)
-
-/* Used by PM_L4PER_MCSPI4_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK                                (1 << 0)
-
-/* Used by PM_L4PER_MCSPI4_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK                               (1 << 3)
-
-/* Used by PM_L3INIT_MMC1_WKDEP */
-#define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT                              1
-#define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK                               (1 << 1)
-
-/* Used by PM_L3INIT_MMC1_WKDEP */
-#define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_MMC1_MPU_MASK                                  (1 << 0)
-
-/* Used by PM_L3INIT_MMC1_WKDEP */
-#define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT                                3
-#define OMAP4430_WKUPDEP_MMC1_SDMA_MASK                                 (1 << 3)
-
-/* Used by PM_L3INIT_MMC1_WKDEP */
-#define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT                               2
-#define OMAP4430_WKUPDEP_MMC1_TESLA_MASK                                (1 << 2)
-
-/* Used by PM_L3INIT_MMC2_WKDEP */
-#define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT                              1
-#define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK                               (1 << 1)
-
-/* Used by PM_L3INIT_MMC2_WKDEP */
-#define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_MMC2_MPU_MASK                                  (1 << 0)
-
-/* Used by PM_L3INIT_MMC2_WKDEP */
-#define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT                                3
-#define OMAP4430_WKUPDEP_MMC2_SDMA_MASK                                 (1 << 3)
-
-/* Used by PM_L3INIT_MMC2_WKDEP */
-#define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT                               2
-#define OMAP4430_WKUPDEP_MMC2_TESLA_MASK                                (1 << 2)
-
-/* Used by PM_L3INIT_MMC6_WKDEP */
-#define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT                              1
-#define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK                               (1 << 1)
-
-/* Used by PM_L3INIT_MMC6_WKDEP */
-#define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_MMC6_MPU_MASK                                  (1 << 0)
-
-/* Used by PM_L3INIT_MMC6_WKDEP */
-#define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT                               2
-#define OMAP4430_WKUPDEP_MMC6_TESLA_MASK                                (1 << 2)
-
-/* Used by PM_L4PER_MMCSD3_WKDEP */
-#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT                            1
-#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK                             (1 << 1)
-
-/* Used by PM_L4PER_MMCSD3_WKDEP */
-#define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK                                (1 << 0)
-
-/* Used by PM_L4PER_MMCSD3_WKDEP */
-#define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK                               (1 << 3)
-
-/* Used by PM_L4PER_MMCSD4_WKDEP */
-#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT                            1
-#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK                             (1 << 1)
-
-/* Used by PM_L4PER_MMCSD4_WKDEP */
-#define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK                                (1 << 0)
-
-/* Used by PM_L4PER_MMCSD4_WKDEP */
-#define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK                               (1 << 3)
-
-/* Used by PM_L4PER_MMCSD5_WKDEP */
-#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT                            1
-#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK                             (1 << 1)
-
-/* Used by PM_L4PER_MMCSD5_WKDEP */
-#define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK                                (1 << 0)
-
-/* Used by PM_L4PER_MMCSD5_WKDEP */
-#define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK                               (1 << 3)
-
-/* Used by PM_L3INIT_PCIESS_WKDEP */
-#define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_PCIESS_MPU_MASK                                (1 << 0)
-
-/* Used by PM_L3INIT_PCIESS_WKDEP */
-#define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK                              (1 << 2)
-
-/* Used by PM_ABE_PDM_WKDEP */
-#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT                             7
-#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK                              (1 << 7)
-
-/* Used by PM_ABE_PDM_WKDEP */
-#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT                            6
-#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK                             (1 << 6)
-
-/* Used by PM_ABE_PDM_WKDEP */
-#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK                               (1 << 0)
-
-/* Used by PM_ABE_PDM_WKDEP */
-#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT                            2
-#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK                             (1 << 2)
-
-/* Used by PM_WKUP_RTC_WKDEP */
-#define OMAP4430_WKUPDEP_RTC_MPU_SHIFT                                  0
-#define OMAP4430_WKUPDEP_RTC_MPU_MASK                                   (1 << 0)
-
-/* Used by PM_L3INIT_SATA_WKDEP */
-#define OMAP4430_WKUPDEP_SATA_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_SATA_MPU_MASK                                  (1 << 0)
-
-/* Used by PM_L3INIT_SATA_WKDEP */
-#define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT                               2
-#define OMAP4430_WKUPDEP_SATA_TESLA_MASK                                (1 << 2)
-
-/* Used by PM_ABE_SLIMBUS_WKDEP */
-#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT                        7
-#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK                         (1 << 7)
-
-/* Used by PM_ABE_SLIMBUS_WKDEP */
-#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT                       6
-#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK                        (1 << 6)
-
-/* Used by PM_ABE_SLIMBUS_WKDEP */
-#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT                         0
-#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK                          (1 << 0)
-
-/* Used by PM_ABE_SLIMBUS_WKDEP */
-#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT                       2
-#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK                        (1 << 2)
-
-/* Used by PM_L4PER_SLIMBUS2_WKDEP */
-#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT                        7
-#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK                         (1 << 7)
-
-/* Used by PM_L4PER_SLIMBUS2_WKDEP */
-#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT                       6
-#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK                        (1 << 6)
-
-/* Used by PM_L4PER_SLIMBUS2_WKDEP */
-#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT                         0
-#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK                          (1 << 0)
-
-/* Used by PM_L4PER_SLIMBUS2_WKDEP */
-#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT                       2
-#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK                        (1 << 2)
-
-/* Used by PM_ALWON_SR_CORE_WKDEP */
-#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT                           1
-#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK                            (1 << 1)
-
-/* Used by PM_ALWON_SR_CORE_WKDEP */
-#define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK                               (1 << 0)
-
-/* Used by PM_ALWON_SR_IVA_WKDEP */
-#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT                            1
-#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK                             (1 << 1)
-
-/* Used by PM_ALWON_SR_IVA_WKDEP */
-#define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK                                (1 << 0)
-
-/* Used by PM_ALWON_SR_MPU_WKDEP */
-#define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK                                (1 << 0)
-
-/* Used by PM_WKUP_TIMER12_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_TIMER12_MPU_MASK                               (1 << 0)
-
-/* Used by PM_WKUP_TIMER1_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_TIMER1_MPU_MASK                                (1 << 0)
-
-/* Used by PM_ABE_TIMER5_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_TIMER5_MPU_MASK                                (1 << 0)
-
-/* Used by PM_ABE_TIMER5_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK                              (1 << 2)
-
-/* Used by PM_ABE_TIMER6_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_TIMER6_MPU_MASK                                (1 << 0)
-
-/* Used by PM_ABE_TIMER6_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK                              (1 << 2)
-
-/* Used by PM_ABE_TIMER7_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_TIMER7_MPU_MASK                                (1 << 0)
-
-/* Used by PM_ABE_TIMER7_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK                              (1 << 2)
-
-/* Used by PM_ABE_TIMER8_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_TIMER8_MPU_MASK                                (1 << 0)
-
-/* Used by PM_ABE_TIMER8_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK                              (1 << 2)
-
-/* Used by PM_L4PER_UART1_WKDEP */
-#define OMAP4430_WKUPDEP_UART1_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_UART1_MPU_MASK                                 (1 << 0)
-
-/* Used by PM_L4PER_UART1_WKDEP */
-#define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT                               3
-#define OMAP4430_WKUPDEP_UART1_SDMA_MASK                                (1 << 3)
-
-/* Used by PM_L4PER_UART2_WKDEP */
-#define OMAP4430_WKUPDEP_UART2_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_UART2_MPU_MASK                                 (1 << 0)
-
-/* Used by PM_L4PER_UART2_WKDEP */
-#define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT                               3
-#define OMAP4430_WKUPDEP_UART2_SDMA_MASK                                (1 << 3)
-
-/* Used by PM_L4PER_UART3_WKDEP */
-#define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT                             1
-#define OMAP4430_WKUPDEP_UART3_DUCATI_MASK                              (1 << 1)
-
-/* Used by PM_L4PER_UART3_WKDEP */
-#define OMAP4430_WKUPDEP_UART3_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_UART3_MPU_MASK                                 (1 << 0)
-
-/* Used by PM_L4PER_UART3_WKDEP */
-#define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT                               3
-#define OMAP4430_WKUPDEP_UART3_SDMA_MASK                                (1 << 3)
-
-/* Used by PM_L4PER_UART3_WKDEP */
-#define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT                              2
-#define OMAP4430_WKUPDEP_UART3_TESLA_MASK                               (1 << 2)
-
-/* Used by PM_L4PER_UART4_WKDEP */
-#define OMAP4430_WKUPDEP_UART4_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_UART4_MPU_MASK                                 (1 << 0)
-
-/* Used by PM_L4PER_UART4_WKDEP */
-#define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT                               3
-#define OMAP4430_WKUPDEP_UART4_SDMA_MASK                                (1 << 3)
-
-/* Used by PM_L3INIT_UNIPRO1_WKDEP */
-#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT                           1
-#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK                            (1 << 1)
-
-/* Used by PM_L3INIT_UNIPRO1_WKDEP */
-#define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK                               (1 << 0)
-
-/* Used by PM_L3INIT_USB_HOST_WKDEP */
-#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK                           (1 << 1)
-
-/* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
-#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT                       1
-#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK                        (1 << 1)
-
-/* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
-#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT                          0
-#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK                           (1 << 0)
-
-/* Used by PM_L3INIT_USB_HOST_WKDEP */
-#define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK                              (1 << 0)
-
-/* Used by PM_L3INIT_USB_OTG_WKDEP */
-#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT                           1
-#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK                            (1 << 1)
-
-/* Used by PM_L3INIT_USB_OTG_WKDEP */
-#define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK                               (1 << 0)
-
-/* Used by PM_L3INIT_USB_TLL_WKDEP */
-#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT                           1
-#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK                            (1 << 1)
-
-/* Used by PM_L3INIT_USB_TLL_WKDEP */
-#define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK                               (1 << 0)
-
-/* Used by PM_WKUP_USIM_WKDEP */
-#define OMAP4430_WKUPDEP_USIM_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_USIM_MPU_MASK                                  (1 << 0)
-
-/* Used by PM_WKUP_USIM_WKDEP */
-#define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT                                3
-#define OMAP4430_WKUPDEP_USIM_SDMA_MASK                                 (1 << 3)
-
-/* Used by PM_WKUP_WDT2_WKDEP */
-#define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT                              1
-#define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK                               (1 << 1)
-
-/* Used by PM_WKUP_WDT2_WKDEP */
-#define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_WDT2_MPU_MASK                                  (1 << 0)
-
-/* Used by PM_ABE_WDT3_WKDEP */
-#define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_WDT3_MPU_MASK                                  (1 << 0)
-
-/* Used by PM_L3INIT_HSI_WKDEP */
-#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT                         8
-#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK                          (1 << 8)
-
-/* Used by PM_L3INIT_XHPI_WKDEP */
-#define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT                              1
-#define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK                               (1 << 1)
-
-/* Used by PRM_IO_PMCTRL */
-#define OMAP4430_WUCLK_CTRL_SHIFT                                       8
 #define OMAP4430_WUCLK_CTRL_MASK                                        (1 << 8)
-
-/* Used by PRM_IO_PMCTRL */
 #define OMAP4430_WUCLK_STATUS_SHIFT                                     9
 #define OMAP4430_WUCLK_STATUS_MASK                                      (1 << 9)
-
-/* Used by REVISION_PRM */
-#define OMAP4430_X_MAJOR_SHIFT                                          8
-#define OMAP4430_X_MAJOR_MASK                                           (0x7 << 8)
-
-/* Used by REVISION_PRM */
-#define OMAP4430_Y_MINOR_SHIFT                                          0
-#define OMAP4430_Y_MINOR_MASK                                           (0x3f << 0)
 #endif
diff --git a/arch/arm/mach-omap2/prm-regbits-54xx.h b/arch/arm/mach-omap2/prm-regbits-54xx.h
deleted file mode 100644
index be31b21aa9c6..000000000000
--- a/arch/arm/mach-omap2/prm-regbits-54xx.h
+++ /dev/null
@@ -1,2701 +0,0 @@
-/*
- * OMAP54xx Power Management register bits
- *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
- *
- * Paul Walmsley (paul@pwsan.com)
- * Rajendra Nayak (rnayak@ti.com)
- * Benoit Cousson (b-cousson@ti.com)
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H
-#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H
-
-/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
-#define OMAP54XX_ABBOFF_ACT_SHIFT                                               1
-#define OMAP54XX_ABBOFF_ACT_WIDTH                                               0x1
-#define OMAP54XX_ABBOFF_ACT_MASK                                                (1 << 1)
-
-/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
-#define OMAP54XX_ABBOFF_SLEEP_SHIFT                                             2
-#define OMAP54XX_ABBOFF_SLEEP_WIDTH                                             0x1
-#define OMAP54XX_ABBOFF_SLEEP_MASK                                              (1 << 2)
-
-/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
-#define OMAP54XX_ABB_MM_DONE_EN_SHIFT                                           31
-#define OMAP54XX_ABB_MM_DONE_EN_WIDTH                                           0x1
-#define OMAP54XX_ABB_MM_DONE_EN_MASK                                            (1 << 31)
-
-/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
-#define OMAP54XX_ABB_MM_DONE_ST_SHIFT                                           31
-#define OMAP54XX_ABB_MM_DONE_ST_WIDTH                                           0x1
-#define OMAP54XX_ABB_MM_DONE_ST_MASK                                            (1 << 31)
-
-/* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP54XX_ABB_MPU_DONE_EN_SHIFT                                          7
-#define OMAP54XX_ABB_MPU_DONE_EN_WIDTH                                          0x1
-#define OMAP54XX_ABB_MPU_DONE_EN_MASK                                           (1 << 7)
-
-/* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP54XX_ABB_MPU_DONE_ST_SHIFT                                          7
-#define OMAP54XX_ABB_MPU_DONE_ST_WIDTH                                          0x1
-#define OMAP54XX_ABB_MPU_DONE_ST_MASK                                           (1 << 7)
-
-/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
-#define OMAP54XX_ACTIVE_FBB_SEL_SHIFT                                           2
-#define OMAP54XX_ACTIVE_FBB_SEL_WIDTH                                           0x1
-#define OMAP54XX_ACTIVE_FBB_SEL_MASK                                            (1 << 2)
-
-/* Used by PM_ABE_PWRSTCTRL */
-#define OMAP54XX_AESSMEM_ONSTATE_SHIFT                                          16
-#define OMAP54XX_AESSMEM_ONSTATE_WIDTH                                          0x2
-#define OMAP54XX_AESSMEM_ONSTATE_MASK                                           (0x3 << 16)
-
-/* Used by PM_ABE_PWRSTCTRL */
-#define OMAP54XX_AESSMEM_RETSTATE_SHIFT                                         8
-#define OMAP54XX_AESSMEM_RETSTATE_WIDTH                                         0x1
-#define OMAP54XX_AESSMEM_RETSTATE_MASK                                          (1 << 8)
-
-/* Used by PM_ABE_PWRSTST */
-#define OMAP54XX_AESSMEM_STATEST_SHIFT                                          4
-#define OMAP54XX_AESSMEM_STATEST_WIDTH                                          0x2
-#define OMAP54XX_AESSMEM_STATEST_MASK                                           (0x3 << 4)
-
-/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
-#define OMAP54XX_AIPOFF_SHIFT                                                   8
-#define OMAP54XX_AIPOFF_WIDTH                                                   0x1
-#define OMAP54XX_AIPOFF_MASK                                                    (1 << 8)
-
-/* Used by PRM_VOLTCTRL */
-#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_SHIFT                                     0
-#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_WIDTH                                     0x2
-#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_MASK                                      (0x3 << 0)
-
-/* Used by PRM_VOLTCTRL */
-#define OMAP54XX_AUTO_CTRL_VDD_MM_L_SHIFT                                       4
-#define OMAP54XX_AUTO_CTRL_VDD_MM_L_WIDTH                                       0x2
-#define OMAP54XX_AUTO_CTRL_VDD_MM_L_MASK                                        (0x3 << 4)
-
-/* Used by PRM_VOLTCTRL */
-#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_SHIFT                                      2
-#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_WIDTH                                      0x2
-#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_MASK                                       (0x3 << 2)
-
-/* Used by PRM_VC_BYPASS_ERRST */
-#define OMAP54XX_BYPS_RA_ERR_SHIFT                                              1
-#define OMAP54XX_BYPS_RA_ERR_WIDTH                                              0x1
-#define OMAP54XX_BYPS_RA_ERR_MASK                                               (1 << 1)
-
-/* Used by PRM_VC_BYPASS_ERRST */
-#define OMAP54XX_BYPS_SA_ERR_SHIFT                                              0
-#define OMAP54XX_BYPS_SA_ERR_WIDTH                                              0x1
-#define OMAP54XX_BYPS_SA_ERR_MASK                                               (1 << 0)
-
-/* Used by PRM_VC_BYPASS_ERRST */
-#define OMAP54XX_BYPS_TIMEOUT_ERR_SHIFT                                         2
-#define OMAP54XX_BYPS_TIMEOUT_ERR_WIDTH                                         0x1
-#define OMAP54XX_BYPS_TIMEOUT_ERR_MASK                                          (1 << 2)
-
-/* Used by PRM_RSTST */
-#define OMAP54XX_C2C_RST_SHIFT                                                  10
-#define OMAP54XX_C2C_RST_WIDTH                                                  0x1
-#define OMAP54XX_C2C_RST_MASK                                                   (1 << 10)
-
-/* Used by PM_CAM_PWRSTCTRL */
-#define OMAP54XX_CAM_MEM_ONSTATE_SHIFT                                          16
-#define OMAP54XX_CAM_MEM_ONSTATE_WIDTH                                          0x2
-#define OMAP54XX_CAM_MEM_ONSTATE_MASK                                           (0x3 << 16)
-
-/* Used by PM_CAM_PWRSTST */
-#define OMAP54XX_CAM_MEM_STATEST_SHIFT                                          4
-#define OMAP54XX_CAM_MEM_STATEST_WIDTH                                          0x2
-#define OMAP54XX_CAM_MEM_STATEST_MASK                                           (0x3 << 4)
-
-/* Used by PRM_CLKREQCTRL */
-#define OMAP54XX_CLKREQ_COND_SHIFT                                              0
-#define OMAP54XX_CLKREQ_COND_WIDTH                                              0x3
-#define OMAP54XX_CLKREQ_COND_MASK                                               (0x7 << 0)
-
-/* Used by PRM_VC_SMPS_CORE_CONFIG */
-#define OMAP54XX_CMDRA_VDD_CORE_L_SHIFT                                         16
-#define OMAP54XX_CMDRA_VDD_CORE_L_WIDTH                                         0x8
-#define OMAP54XX_CMDRA_VDD_CORE_L_MASK                                          (0xff << 16)
-
-/* Used by PRM_VC_SMPS_MM_CONFIG */
-#define OMAP54XX_CMDRA_VDD_MM_L_SHIFT                                           16
-#define OMAP54XX_CMDRA_VDD_MM_L_WIDTH                                           0x8
-#define OMAP54XX_CMDRA_VDD_MM_L_MASK                                            (0xff << 16)
-
-/* Used by PRM_VC_SMPS_MPU_CONFIG */
-#define OMAP54XX_CMDRA_VDD_MPU_L_SHIFT                                          16
-#define OMAP54XX_CMDRA_VDD_MPU_L_WIDTH                                          0x8
-#define OMAP54XX_CMDRA_VDD_MPU_L_MASK                                           (0xff << 16)
-
-/* Used by PRM_VC_SMPS_CORE_CONFIG */
-#define OMAP54XX_CMD_VDD_CORE_L_SHIFT                                           28
-#define OMAP54XX_CMD_VDD_CORE_L_WIDTH                                           0x1
-#define OMAP54XX_CMD_VDD_CORE_L_MASK                                            (1 << 28)
-
-/* Used by PRM_VC_SMPS_MM_CONFIG */
-#define OMAP54XX_CMD_VDD_MM_L_SHIFT                                             28
-#define OMAP54XX_CMD_VDD_MM_L_WIDTH                                             0x1
-#define OMAP54XX_CMD_VDD_MM_L_MASK                                              (1 << 28)
-
-/* Used by PRM_VC_SMPS_MPU_CONFIG */
-#define OMAP54XX_CMD_VDD_MPU_L_SHIFT                                            28
-#define OMAP54XX_CMD_VDD_MPU_L_WIDTH                                            0x1
-#define OMAP54XX_CMD_VDD_MPU_L_MASK                                             (1 << 28)
-
-/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP54XX_CORE_OCMRAM_ONSTATE_SHIFT                                      18
-#define OMAP54XX_CORE_OCMRAM_ONSTATE_WIDTH                                      0x2
-#define OMAP54XX_CORE_OCMRAM_ONSTATE_MASK                                       (0x3 << 18)
-
-/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP54XX_CORE_OCMRAM_RETSTATE_SHIFT                                     9
-#define OMAP54XX_CORE_OCMRAM_RETSTATE_WIDTH                                     0x1
-#define OMAP54XX_CORE_OCMRAM_RETSTATE_MASK                                      (1 << 9)
-
-/* Used by PM_CORE_PWRSTST */
-#define OMAP54XX_CORE_OCMRAM_STATEST_SHIFT                                      6
-#define OMAP54XX_CORE_OCMRAM_STATEST_WIDTH                                      0x2
-#define OMAP54XX_CORE_OCMRAM_STATEST_MASK                                       (0x3 << 6)
-
-/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_SHIFT                                  16
-#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_WIDTH                                  0x2
-#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_MASK                                   (0x3 << 16)
-
-/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_SHIFT                                 8
-#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_WIDTH                                 0x1
-#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_MASK                                  (1 << 8)
-
-/* Used by PM_CORE_PWRSTST */
-#define OMAP54XX_CORE_OTHER_BANK_STATEST_SHIFT                                  4
-#define OMAP54XX_CORE_OTHER_BANK_STATEST_WIDTH                                  0x2
-#define OMAP54XX_CORE_OTHER_BANK_STATEST_MASK                                   (0x3 << 4)
-
-/* Used by REVISION_PRM */
-#define OMAP54XX_CUSTOM_SHIFT                                                   6
-#define OMAP54XX_CUSTOM_WIDTH                                                   0x2
-#define OMAP54XX_CUSTOM_MASK                                                    (0x3 << 6)
-
-/* Used by PRM_VC_VAL_BYPASS */
-#define OMAP54XX_DATA_SHIFT                                                     16
-#define OMAP54XX_DATA_WIDTH                                                     0x8
-#define OMAP54XX_DATA_MASK                                                      (0xff << 16)
-
-/* Used by PRM_DEBUG_CORE_RET_TRANS */
-#define OMAP54XX_PRM_DEBUG_OUT_SHIFT                                            0
-#define OMAP54XX_PRM_DEBUG_OUT_WIDTH                                            0x1c
-#define OMAP54XX_PRM_DEBUG_OUT_MASK                                             (0xfffffff << 0)
-
-/* Renamed from DEBUG_OUT Used by PRM_DEBUG_MM_RET_TRANS */
-#define OMAP54XX_DEBUG_OUT_0_9_SHIFT                                            0
-#define OMAP54XX_DEBUG_OUT_0_9_WIDTH                                            0xa
-#define OMAP54XX_DEBUG_OUT_0_9_MASK                                             (0x3ff << 0)
-
-/* Renamed from DEBUG_OUT Used by PRM_DEBUG_MPU_RET_TRANS */
-#define OMAP54XX_DEBUG_OUT_0_6_SHIFT                                            0
-#define OMAP54XX_DEBUG_OUT_0_6_WIDTH                                            0x7
-#define OMAP54XX_DEBUG_OUT_0_6_MASK                                             (0x7f << 0)
-
-/* Renamed from DEBUG_OUT Used by PRM_DEBUG_OFF_TRANS */
-#define OMAP54XX_DEBUG_OUT_0_31_SHIFT                                           0
-#define OMAP54XX_DEBUG_OUT_0_31_WIDTH                                           0x20
-#define OMAP54XX_DEBUG_OUT_0_31_MASK                                            (0xffffffff << 0)
-
-/* Renamed from DEBUG_OUT Used by PRM_DEBUG_WKUPAON_FD_TRANS */
-#define OMAP54XX_DEBUG_OUT_0_11_SHIFT                                           0
-#define OMAP54XX_DEBUG_OUT_0_11_WIDTH                                           0xc
-#define OMAP54XX_DEBUG_OUT_0_11_MASK                                            (0xfff << 0)
-
-/* Used by PRM_DEVICE_OFF_CTRL */
-#define OMAP54XX_DEVICE_OFF_ENABLE_SHIFT                                        0
-#define OMAP54XX_DEVICE_OFF_ENABLE_WIDTH                                        0x1
-#define OMAP54XX_DEVICE_OFF_ENABLE_MASK                                         (1 << 0)
-
-/* Used by PRM_VC_CFG_I2C_MODE */
-#define OMAP54XX_DFILTEREN_SHIFT                                                6
-#define OMAP54XX_DFILTEREN_WIDTH                                                0x1
-#define OMAP54XX_DFILTEREN_MASK                                                 (1 << 6)
-
-/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
-#define OMAP54XX_DPLL_ABE_RECAL_EN_SHIFT                                        4
-#define OMAP54XX_DPLL_ABE_RECAL_EN_WIDTH                                        0x1
-#define OMAP54XX_DPLL_ABE_RECAL_EN_MASK                                         (1 << 4)
-
-/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
-#define OMAP54XX_DPLL_ABE_RECAL_ST_SHIFT                                        4
-#define OMAP54XX_DPLL_ABE_RECAL_ST_WIDTH                                        0x1
-#define OMAP54XX_DPLL_ABE_RECAL_ST_MASK                                         (1 << 4)
-
-/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
-#define OMAP54XX_DPLL_CORE_RECAL_EN_SHIFT                                       0
-#define OMAP54XX_DPLL_CORE_RECAL_EN_WIDTH                                       0x1
-#define OMAP54XX_DPLL_CORE_RECAL_EN_MASK                                        (1 << 0)
-
-/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
-#define OMAP54XX_DPLL_CORE_RECAL_ST_SHIFT                                       0
-#define OMAP54XX_DPLL_CORE_RECAL_ST_WIDTH                                       0x1
-#define OMAP54XX_DPLL_CORE_RECAL_ST_MASK                                        (1 << 0)
-
-/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
-#define OMAP54XX_DPLL_IVA_RECAL_EN_SHIFT                                        2
-#define OMAP54XX_DPLL_IVA_RECAL_EN_WIDTH                                        0x1
-#define OMAP54XX_DPLL_IVA_RECAL_EN_MASK                                         (1 << 2)
-
-/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
-#define OMAP54XX_DPLL_IVA_RECAL_ST_SHIFT                                        2
-#define OMAP54XX_DPLL_IVA_RECAL_ST_WIDTH                                        0x1
-#define OMAP54XX_DPLL_IVA_RECAL_ST_MASK                                         (1 << 2)
-
-/* Used by PRM_IRQENABLE_MPU */
-#define OMAP54XX_DPLL_MPU_RECAL_EN_SHIFT                                        1
-#define OMAP54XX_DPLL_MPU_RECAL_EN_WIDTH                                        0x1
-#define OMAP54XX_DPLL_MPU_RECAL_EN_MASK                                         (1 << 1)
-
-/* Used by PRM_IRQSTATUS_MPU */
-#define OMAP54XX_DPLL_MPU_RECAL_ST_SHIFT                                        1
-#define OMAP54XX_DPLL_MPU_RECAL_ST_WIDTH                                        0x1
-#define OMAP54XX_DPLL_MPU_RECAL_ST_MASK                                         (1 << 1)
-
-/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
-#define OMAP54XX_DPLL_PER_RECAL_EN_SHIFT                                        3
-#define OMAP54XX_DPLL_PER_RECAL_EN_WIDTH                                        0x1
-#define OMAP54XX_DPLL_PER_RECAL_EN_MASK                                         (1 << 3)
-
-/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
-#define OMAP54XX_DPLL_PER_RECAL_ST_SHIFT                                        3
-#define OMAP54XX_DPLL_PER_RECAL_ST_WIDTH                                        0x1
-#define OMAP54XX_DPLL_PER_RECAL_ST_MASK                                         (1 << 3)
-
-/* Used by PM_DSP_PWRSTCTRL */
-#define OMAP54XX_DSP_EDMA_ONSTATE_SHIFT                                         20
-#define OMAP54XX_DSP_EDMA_ONSTATE_WIDTH                                         0x2
-#define OMAP54XX_DSP_EDMA_ONSTATE_MASK                                          (0x3 << 20)
-
-/* Used by PM_DSP_PWRSTCTRL */
-#define OMAP54XX_DSP_EDMA_RETSTATE_SHIFT                                        10
-#define OMAP54XX_DSP_EDMA_RETSTATE_WIDTH                                        0x1
-#define OMAP54XX_DSP_EDMA_RETSTATE_MASK                                         (1 << 10)
-
-/* Used by PM_DSP_PWRSTST */
-#define OMAP54XX_DSP_EDMA_STATEST_SHIFT                                         8
-#define OMAP54XX_DSP_EDMA_STATEST_WIDTH                                         0x2
-#define OMAP54XX_DSP_EDMA_STATEST_MASK                                          (0x3 << 8)
-
-/* Used by PM_DSP_PWRSTCTRL */
-#define OMAP54XX_DSP_L1_ONSTATE_SHIFT                                           16
-#define OMAP54XX_DSP_L1_ONSTATE_WIDTH                                           0x2
-#define OMAP54XX_DSP_L1_ONSTATE_MASK                                            (0x3 << 16)
-
-/* Used by PM_DSP_PWRSTCTRL */
-#define OMAP54XX_DSP_L1_RETSTATE_SHIFT                                          8
-#define OMAP54XX_DSP_L1_RETSTATE_WIDTH                                          0x1
-#define OMAP54XX_DSP_L1_RETSTATE_MASK                                           (1 << 8)
-
-/* Used by PM_DSP_PWRSTST */
-#define OMAP54XX_DSP_L1_STATEST_SHIFT                                           4
-#define OMAP54XX_DSP_L1_STATEST_WIDTH                                           0x2
-#define OMAP54XX_DSP_L1_STATEST_MASK                                            (0x3 << 4)
-
-/* Used by PM_DSP_PWRSTCTRL */
-#define OMAP54XX_DSP_L2_ONSTATE_SHIFT                                           18
-#define OMAP54XX_DSP_L2_ONSTATE_WIDTH                                           0x2
-#define OMAP54XX_DSP_L2_ONSTATE_MASK                                            (0x3 << 18)
-
-/* Used by PM_DSP_PWRSTCTRL */
-#define OMAP54XX_DSP_L2_RETSTATE_SHIFT                                          9
-#define OMAP54XX_DSP_L2_RETSTATE_WIDTH                                          0x1
-#define OMAP54XX_DSP_L2_RETSTATE_MASK                                           (1 << 9)
-
-/* Used by PM_DSP_PWRSTST */
-#define OMAP54XX_DSP_L2_STATEST_SHIFT                                           6
-#define OMAP54XX_DSP_L2_STATEST_WIDTH                                           0x2
-#define OMAP54XX_DSP_L2_STATEST_MASK                                            (0x3 << 6)
-
-/* Used by PM_DSS_PWRSTCTRL */
-#define OMAP54XX_DSS_MEM_ONSTATE_SHIFT                                          16
-#define OMAP54XX_DSS_MEM_ONSTATE_WIDTH                                          0x2
-#define OMAP54XX_DSS_MEM_ONSTATE_MASK                                           (0x3 << 16)
-
-/* Used by PM_DSS_PWRSTCTRL */
-#define OMAP54XX_DSS_MEM_RETSTATE_SHIFT                                         8
-#define OMAP54XX_DSS_MEM_RETSTATE_WIDTH                                         0x1
-#define OMAP54XX_DSS_MEM_RETSTATE_MASK                                          (1 << 8)
-
-/* Used by PM_DSS_PWRSTST */
-#define OMAP54XX_DSS_MEM_STATEST_SHIFT                                          4
-#define OMAP54XX_DSS_MEM_STATEST_WIDTH                                          0x2
-#define OMAP54XX_DSS_MEM_STATEST_MASK                                           (0x3 << 4)
-
-/* Used by PRM_DEVICE_OFF_CTRL */
-#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_SHIFT                                    8
-#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_WIDTH                                    0x1
-#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_MASK                                     (1 << 8)
-
-/* Used by PRM_DEVICE_OFF_CTRL */
-#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_SHIFT                                    9
-#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_WIDTH                                    0x1
-#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_MASK                                     (1 << 9)
-
-/* Used by PM_EMU_PWRSTCTRL */
-#define OMAP54XX_EMU_BANK_ONSTATE_SHIFT                                         16
-#define OMAP54XX_EMU_BANK_ONSTATE_WIDTH                                         0x2
-#define OMAP54XX_EMU_BANK_ONSTATE_MASK                                          (0x3 << 16)
-
-/* Used by PM_EMU_PWRSTST */
-#define OMAP54XX_EMU_BANK_STATEST_SHIFT                                         4
-#define OMAP54XX_EMU_BANK_STATEST_WIDTH                                         0x2
-#define OMAP54XX_EMU_BANK_STATEST_MASK                                          (0x3 << 4)
-
-/*
- * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP,
- * PRM_SRAM_WKUP_SETUP
- */
-#define OMAP54XX_ENABLE_RTA_SHIFT                                               0
-#define OMAP54XX_ENABLE_RTA_WIDTH                                               0x1
-#define OMAP54XX_ENABLE_RTA_MASK                                                (1 << 0)
-
-/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
-#define OMAP54XX_ENFUNC1_SHIFT                                                  3
-#define OMAP54XX_ENFUNC1_WIDTH                                                  0x1
-#define OMAP54XX_ENFUNC1_MASK                                                   (1 << 3)
-
-/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
-#define OMAP54XX_ENFUNC2_SHIFT                                                  4
-#define OMAP54XX_ENFUNC2_WIDTH                                                  0x1
-#define OMAP54XX_ENFUNC2_MASK                                                   (1 << 4)
-
-/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
-#define OMAP54XX_ENFUNC3_SHIFT                                                  5
-#define OMAP54XX_ENFUNC3_WIDTH                                                  0x1
-#define OMAP54XX_ENFUNC3_MASK                                                   (1 << 5)
-
-/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
-#define OMAP54XX_ENFUNC4_SHIFT                                                  6
-#define OMAP54XX_ENFUNC4_WIDTH                                                  0x1
-#define OMAP54XX_ENFUNC4_MASK                                                   (1 << 6)
-
-/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
-#define OMAP54XX_ENFUNC5_SHIFT                                                  7
-#define OMAP54XX_ENFUNC5_WIDTH                                                  0x1
-#define OMAP54XX_ENFUNC5_MASK                                                   (1 << 7)
-
-/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP54XX_ERRORGAIN_SHIFT                                                16
-#define OMAP54XX_ERRORGAIN_WIDTH                                                0x8
-#define OMAP54XX_ERRORGAIN_MASK                                                 (0xff << 16)
-
-/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP54XX_ERROROFFSET_SHIFT                                              24
-#define OMAP54XX_ERROROFFSET_WIDTH                                              0x8
-#define OMAP54XX_ERROROFFSET_MASK                                               (0xff << 24)
-
-/* Used by PRM_RSTST */
-#define OMAP54XX_EXTERNAL_WARM_RST_SHIFT                                        5
-#define OMAP54XX_EXTERNAL_WARM_RST_WIDTH                                        0x1
-#define OMAP54XX_EXTERNAL_WARM_RST_MASK                                         (1 << 5)
-
-/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP54XX_FORCEUPDATE_SHIFT                                              1
-#define OMAP54XX_FORCEUPDATE_WIDTH                                              0x1
-#define OMAP54XX_FORCEUPDATE_MASK                                               (1 << 1)
-
-/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */
-#define OMAP54XX_FORCEUPDATEWAIT_SHIFT                                          8
-#define OMAP54XX_FORCEUPDATEWAIT_WIDTH                                          0x18
-#define OMAP54XX_FORCEUPDATEWAIT_MASK                                           (0xffffff << 8)
-
-/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU */
-#define OMAP54XX_FORCEWKUP_EN_SHIFT                                             10
-#define OMAP54XX_FORCEWKUP_EN_WIDTH                                             0x1
-#define OMAP54XX_FORCEWKUP_EN_MASK                                              (1 << 10)
-
-/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU */
-#define OMAP54XX_FORCEWKUP_ST_SHIFT                                             10
-#define OMAP54XX_FORCEWKUP_ST_WIDTH                                             0x1
-#define OMAP54XX_FORCEWKUP_ST_MASK                                              (1 << 10)
-
-/* Used by REVISION_PRM */
-#define OMAP54XX_FUNC_SHIFT                                                     16
-#define OMAP54XX_FUNC_WIDTH                                                     0xc
-#define OMAP54XX_FUNC_MASK                                                      (0xfff << 16)
-
-/* Used by PRM_RSTST */
-#define OMAP54XX_GLOBAL_COLD_RST_SHIFT                                          0
-#define OMAP54XX_GLOBAL_COLD_RST_WIDTH                                          0x1
-#define OMAP54XX_GLOBAL_COLD_RST_MASK                                           (1 << 0)
-
-/* Used by PRM_RSTST */
-#define OMAP54XX_GLOBAL_WARM_SW_RST_SHIFT                                       1
-#define OMAP54XX_GLOBAL_WARM_SW_RST_WIDTH                                       0x1
-#define OMAP54XX_GLOBAL_WARM_SW_RST_MASK                                        (1 << 1)
-
-/* Used by PRM_IO_PMCTRL */
-#define OMAP54XX_GLOBAL_WUEN_SHIFT                                              16
-#define OMAP54XX_GLOBAL_WUEN_WIDTH                                              0x1
-#define OMAP54XX_GLOBAL_WUEN_MASK                                               (1 << 16)
-
-/* Used by PM_GPU_PWRSTCTRL */
-#define OMAP54XX_GPU_MEM_ONSTATE_SHIFT                                          16
-#define OMAP54XX_GPU_MEM_ONSTATE_WIDTH                                          0x2
-#define OMAP54XX_GPU_MEM_ONSTATE_MASK                                           (0x3 << 16)
-
-/* Used by PM_GPU_PWRSTST */
-#define OMAP54XX_GPU_MEM_STATEST_SHIFT                                          4
-#define OMAP54XX_GPU_MEM_STATEST_WIDTH                                          0x2
-#define OMAP54XX_GPU_MEM_STATEST_MASK                                           (0x3 << 4)
-
-/* Used by PRM_VC_CFG_I2C_MODE */
-#define OMAP54XX_HSMCODE_SHIFT                                                  0
-#define OMAP54XX_HSMCODE_WIDTH                                                  0x3
-#define OMAP54XX_HSMCODE_MASK                                                   (0x7 << 0)
-
-/* Used by PRM_VC_CFG_I2C_MODE */
-#define OMAP54XX_HSMODEEN_SHIFT                                                 3
-#define OMAP54XX_HSMODEEN_WIDTH                                                 0x1
-#define OMAP54XX_HSMODEEN_MASK                                                  (1 << 3)
-
-/* Used by PRM_VC_CFG_I2C_CLK */
-#define OMAP54XX_HSSCLH_SHIFT                                                   16
-#define OMAP54XX_HSSCLH_WIDTH                                                   0x8
-#define OMAP54XX_HSSCLH_MASK                                                    (0xff << 16)
-
-/* Used by PRM_VC_CFG_I2C_CLK */
-#define OMAP54XX_HSSCLL_SHIFT                                                   24
-#define OMAP54XX_HSSCLL_WIDTH                                                   0x8
-#define OMAP54XX_HSSCLL_MASK                                                    (0xff << 24)
-
-/* Used by PM_IVA_PWRSTCTRL */
-#define OMAP54XX_HWA_MEM_ONSTATE_SHIFT                                          16
-#define OMAP54XX_HWA_MEM_ONSTATE_WIDTH                                          0x2
-#define OMAP54XX_HWA_MEM_ONSTATE_MASK                                           (0x3 << 16)
-
-/* Used by PM_IVA_PWRSTCTRL */
-#define OMAP54XX_HWA_MEM_RETSTATE_SHIFT                                         8
-#define OMAP54XX_HWA_MEM_RETSTATE_WIDTH                                         0x1
-#define OMAP54XX_HWA_MEM_RETSTATE_MASK                                          (1 << 8)
-
-/* Used by PM_IVA_PWRSTST */
-#define OMAP54XX_HWA_MEM_STATEST_SHIFT                                          4
-#define OMAP54XX_HWA_MEM_STATEST_WIDTH                                          0x2
-#define OMAP54XX_HWA_MEM_STATEST_MASK                                           (0x3 << 4)
-
-/* Used by PRM_RSTST */
-#define OMAP54XX_ICEPICK_RST_SHIFT                                              9
-#define OMAP54XX_ICEPICK_RST_WIDTH                                              0x1
-#define OMAP54XX_ICEPICK_RST_MASK                                               (1 << 9)
-
-/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP54XX_INITVDD_SHIFT                                                  2
-#define OMAP54XX_INITVDD_WIDTH                                                  0x1
-#define OMAP54XX_INITVDD_MASK                                                   (1 << 2)
-
-/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP54XX_INITVOLTAGE_SHIFT                                              8
-#define OMAP54XX_INITVOLTAGE_WIDTH                                              0x8
-#define OMAP54XX_INITVOLTAGE_MASK                                               (0xff << 8)
-
-/*
- * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
- * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
- * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST,
- * PRM_VOLTST_MM, PRM_VOLTST_MPU
- */
-#define OMAP54XX_INTRANSITION_SHIFT                                             20
-#define OMAP54XX_INTRANSITION_WIDTH                                             0x1
-#define OMAP54XX_INTRANSITION_MASK                                              (1 << 20)
-
-/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
-#define OMAP54XX_IO_EN_SHIFT                                                    9
-#define OMAP54XX_IO_EN_WIDTH                                                    0x1
-#define OMAP54XX_IO_EN_MASK                                                     (1 << 9)
-
-/* Used by PRM_IO_PMCTRL */
-#define OMAP54XX_IO_ON_STATUS_SHIFT                                             5
-#define OMAP54XX_IO_ON_STATUS_WIDTH                                             0x1
-#define OMAP54XX_IO_ON_STATUS_MASK                                              (1 << 5)
-
-/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
-#define OMAP54XX_IO_ST_SHIFT                                                    9
-#define OMAP54XX_IO_ST_WIDTH                                                    0x1
-#define OMAP54XX_IO_ST_MASK                                                     (1 << 9)
-
-/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP54XX_IPU_L2RAM_ONSTATE_SHIFT                                        20
-#define OMAP54XX_IPU_L2RAM_ONSTATE_WIDTH                                        0x2
-#define OMAP54XX_IPU_L2RAM_ONSTATE_MASK                                         (0x3 << 20)
-
-/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP54XX_IPU_L2RAM_RETSTATE_SHIFT                                       10
-#define OMAP54XX_IPU_L2RAM_RETSTATE_WIDTH                                       0x1
-#define OMAP54XX_IPU_L2RAM_RETSTATE_MASK                                        (1 << 10)
-
-/* Used by PM_CORE_PWRSTST */
-#define OMAP54XX_IPU_L2RAM_STATEST_SHIFT                                        8
-#define OMAP54XX_IPU_L2RAM_STATEST_WIDTH                                        0x2
-#define OMAP54XX_IPU_L2RAM_STATEST_MASK                                         (0x3 << 8)
-
-/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP54XX_IPU_UNICACHE_ONSTATE_SHIFT                                     22
-#define OMAP54XX_IPU_UNICACHE_ONSTATE_WIDTH                                     0x2
-#define OMAP54XX_IPU_UNICACHE_ONSTATE_MASK                                      (0x3 << 22)
-
-/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP54XX_IPU_UNICACHE_RETSTATE_SHIFT                                    11
-#define OMAP54XX_IPU_UNICACHE_RETSTATE_WIDTH                                    0x1
-#define OMAP54XX_IPU_UNICACHE_RETSTATE_MASK                                     (1 << 11)
-
-/* Used by PM_CORE_PWRSTST */
-#define OMAP54XX_IPU_UNICACHE_STATEST_SHIFT                                     10
-#define OMAP54XX_IPU_UNICACHE_STATEST_WIDTH                                     0x2
-#define OMAP54XX_IPU_UNICACHE_STATEST_MASK                                      (0x3 << 10)
-
-/* Used by PRM_IO_PMCTRL */
-#define OMAP54XX_ISOCLK_OVERRIDE_SHIFT                                          0
-#define OMAP54XX_ISOCLK_OVERRIDE_WIDTH                                          0x1
-#define OMAP54XX_ISOCLK_OVERRIDE_MASK                                           (1 << 0)
-
-/* Used by PRM_IO_PMCTRL */
-#define OMAP54XX_ISOCLK_STATUS_SHIFT                                            1
-#define OMAP54XX_ISOCLK_STATUS_WIDTH                                            0x1
-#define OMAP54XX_ISOCLK_STATUS_MASK                                             (1 << 1)
-
-/* Used by PRM_IO_PMCTRL */
-#define OMAP54XX_ISOOVR_EXTEND_SHIFT                                            4
-#define OMAP54XX_ISOOVR_EXTEND_WIDTH                                            0x1
-#define OMAP54XX_ISOOVR_EXTEND_MASK                                             (1 << 4)
-
-/* Used by PRM_IO_COUNT */
-#define OMAP54XX_ISO_2_ON_TIME_SHIFT                                            0
-#define OMAP54XX_ISO_2_ON_TIME_WIDTH                                            0x8
-#define OMAP54XX_ISO_2_ON_TIME_MASK                                             (0xff << 0)
-
-/* Used by PM_L3INIT_PWRSTCTRL */
-#define OMAP54XX_L3INIT_BANK1_ONSTATE_SHIFT                                     16
-#define OMAP54XX_L3INIT_BANK1_ONSTATE_WIDTH                                     0x2
-#define OMAP54XX_L3INIT_BANK1_ONSTATE_MASK                                      (0x3 << 16)
-
-/* Used by PM_L3INIT_PWRSTCTRL */
-#define OMAP54XX_L3INIT_BANK1_RETSTATE_SHIFT                                    8
-#define OMAP54XX_L3INIT_BANK1_RETSTATE_WIDTH                                    0x1
-#define OMAP54XX_L3INIT_BANK1_RETSTATE_MASK                                     (1 << 8)
-
-/* Used by PM_L3INIT_PWRSTST */
-#define OMAP54XX_L3INIT_BANK1_STATEST_SHIFT                                     4
-#define OMAP54XX_L3INIT_BANK1_STATEST_WIDTH                                     0x2
-#define OMAP54XX_L3INIT_BANK1_STATEST_MASK                                      (0x3 << 4)
-
-/* Used by PM_L3INIT_PWRSTCTRL */
-#define OMAP54XX_L3INIT_BANK2_ONSTATE_SHIFT                                     18
-#define OMAP54XX_L3INIT_BANK2_ONSTATE_WIDTH                                     0x2
-#define OMAP54XX_L3INIT_BANK2_ONSTATE_MASK                                      (0x3 << 18)
-
-/* Used by PM_L3INIT_PWRSTCTRL */
-#define OMAP54XX_L3INIT_BANK2_RETSTATE_SHIFT                                    9
-#define OMAP54XX_L3INIT_BANK2_RETSTATE_WIDTH                                    0x1
-#define OMAP54XX_L3INIT_BANK2_RETSTATE_MASK                                     (1 << 9)
-
-/* Used by PM_L3INIT_PWRSTST */
-#define OMAP54XX_L3INIT_BANK2_STATEST_SHIFT                                     6
-#define OMAP54XX_L3INIT_BANK2_STATEST_WIDTH                                     0x2
-#define OMAP54XX_L3INIT_BANK2_STATEST_MASK                                      (0x3 << 6)
-
-/*
- * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
- * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
- * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST
- */
-#define OMAP54XX_LASTPOWERSTATEENTERED_SHIFT                                    24
-#define OMAP54XX_LASTPOWERSTATEENTERED_WIDTH                                    0x2
-#define OMAP54XX_LASTPOWERSTATEENTERED_MASK                                     (0x3 << 24)
-
-/* Used by PRM_RSTST */
-#define OMAP54XX_LLI_RST_SHIFT                                                  14
-#define OMAP54XX_LLI_RST_WIDTH                                                  0x1
-#define OMAP54XX_LLI_RST_MASK                                                   (1 << 14)
-
-/*
- * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSP_PWRSTCTRL,
- * PM_DSS_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL
- */
-#define OMAP54XX_LOGICRETSTATE_SHIFT                                            2
-#define OMAP54XX_LOGICRETSTATE_WIDTH                                            0x1
-#define OMAP54XX_LOGICRETSTATE_MASK                                             (1 << 2)
-
-/*
- * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
- * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
- * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST
- */
-#define OMAP54XX_LOGICSTATEST_SHIFT                                             2
-#define OMAP54XX_LOGICSTATEST_WIDTH                                             0x1
-#define OMAP54XX_LOGICSTATEST_MASK                                              (1 << 2)
-
-/*
- * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT,
- * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT,
- * RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT, RM_ABE_TIMER5_CONTEXT,
- * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT,
- * RM_ABE_WD_TIMER3_CONTEXT, RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT,
- * RM_CAM_CAL_CONTEXT, RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT,
- * RM_COREAON_SMARTREFLEX_CORE_CONTEXT, RM_COREAON_SMARTREFLEX_MM_CONTEXT,
- * RM_COREAON_SMARTREFLEX_MPU_CONTEXT, RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT,
- * RM_DSP_DSP_CONTEXT, RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT,
- * RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT, RM_EMIF_EMIF2_CONTEXT,
- * RM_EMIF_EMIF_DLL_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT,
- * RM_EMU_DEBUGSS_CONTEXT, RM_GPU_GPU_CONTEXT, RM_IPU_IPU_CONTEXT,
- * RM_IVA_IVA_CONTEXT, RM_IVA_SL2_CONTEXT, RM_L3INIT_IEEE1500_2_OCP_CONTEXT,
- * RM_L3INIT_OCP2SCP1_CONTEXT, RM_L3INIT_OCP2SCP3_CONTEXT,
- * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT,
- * RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT,
- * RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT,
- * RM_L3MAIN2_L3_MAIN_2_CONTEXT, RM_L3MAIN2_OCMC_RAM_CONTEXT,
- * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_OCP2SCP2_CONTEXT,
- * RM_L4CFG_SAR_ROM_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT,
- * RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT,
- * RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCSPI1_CONTEXT,
- * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT,
- * RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT,
- * RM_L4PER_TIMER10_CONTEXT, RM_L4PER_TIMER11_CONTEXT, RM_L4PER_TIMER2_CONTEXT,
- * RM_L4PER_TIMER3_CONTEXT, RM_L4PER_TIMER4_CONTEXT, RM_L4PER_TIMER9_CONTEXT,
- * RM_L4SEC_FPKA_CONTEXT, RM_MIPIEXT_LLI_CONTEXT,
- * RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT,
- * RM_WKUPAON_COUNTER_32K_CONTEXT, RM_WKUPAON_GPIO1_CONTEXT,
- * RM_WKUPAON_KBD_CONTEXT, RM_WKUPAON_L4_WKUP_CONTEXT,
- * RM_WKUPAON_SAR_RAM_CONTEXT, RM_WKUPAON_TIMER12_CONTEXT,
- * RM_WKUPAON_TIMER1_CONTEXT, RM_WKUPAON_WD_TIMER1_CONTEXT,
- * RM_WKUPAON_WD_TIMER2_CONTEXT
- */
-#define OMAP54XX_LOSTCONTEXT_DFF_SHIFT                                          0
-#define OMAP54XX_LOSTCONTEXT_DFF_WIDTH                                          0x1
-#define OMAP54XX_LOSTCONTEXT_DFF_MASK                                           (1 << 0)
-
-/*
- * Used by RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT,
- * RM_C2C_MODEM_ICR_CONTEXT, RM_DMA_DMA_SYSTEM_CONTEXT, RM_DSP_DSP_CONTEXT,
- * RM_DSS_DSS_CONTEXT, RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT,
- * RM_EMIF_EMIF2_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT, RM_IPU_IPU_CONTEXT,
- * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
- * RM_L3INIT_USB_HOST_HS_CONTEXT, RM_L3INIT_USB_OTG_SS_CONTEXT,
- * RM_L3INIT_USB_TLL_HS_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT,
- * RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT,
- * RM_L3MAIN2_GPMC_CONTEXT, RM_L3MAIN2_L3_MAIN_2_CONTEXT,
- * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_MAILBOX_CONTEXT,
- * RM_L4CFG_SPINLOCK_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT,
- * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT,
- * RM_L4PER_GPIO7_CONTEXT, RM_L4PER_GPIO8_CONTEXT, RM_L4PER_I2C1_CONTEXT,
- * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT,
- * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT,
- * RM_L4PER_UART6_CONTEXT, RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT,
- * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT, RM_L4SEC_RNG_CONTEXT,
- * RM_L4SEC_SHA2MD5_CONTEXT, RM_MIPIEXT_LLI_CONTEXT,
- * RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT
- */
-#define OMAP54XX_LOSTCONTEXT_RFF_SHIFT                                          1
-#define OMAP54XX_LOSTCONTEXT_RFF_WIDTH                                          0x1
-#define OMAP54XX_LOSTCONTEXT_RFF_MASK                                           (1 << 1)
-
-/* Used by RM_ABE_AESS_CONTEXT */
-#define OMAP54XX_LOSTMEM_AESSMEM_SHIFT                                          8
-#define OMAP54XX_LOSTMEM_AESSMEM_WIDTH                                          0x1
-#define OMAP54XX_LOSTMEM_AESSMEM_MASK                                           (1 << 8)
-
-/* Used by RM_CAM_CAL_CONTEXT */
-#define OMAP54XX_LOSTMEM_CAL_MEM_SHIFT                                          8
-#define OMAP54XX_LOSTMEM_CAL_MEM_WIDTH                                          0x1
-#define OMAP54XX_LOSTMEM_CAL_MEM_MASK                                           (1 << 8)
-
-/* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */
-#define OMAP54XX_LOSTMEM_CAM_MEM_SHIFT                                          8
-#define OMAP54XX_LOSTMEM_CAM_MEM_WIDTH                                          0x1
-#define OMAP54XX_LOSTMEM_CAM_MEM_MASK                                           (1 << 8)
-
-/* Used by RM_EMIF_DMM_CONTEXT */
-#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_SHIFT                                   9
-#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_WIDTH                                   0x1
-#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_MASK                                    (1 << 9)
-
-/* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_L3INSTR_OCP_WP_NOC_CONTEXT */
-#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_SHIFT                               8
-#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_WIDTH                               0x1
-#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_MASK                                (1 << 8)
-
-/* Used by RM_L3MAIN2_OCMC_RAM_CONTEXT */
-#define OMAP54XX_LOSTMEM_CORE_OCMRAM_SHIFT                                      8
-#define OMAP54XX_LOSTMEM_CORE_OCMRAM_WIDTH                                      0x1
-#define OMAP54XX_LOSTMEM_CORE_OCMRAM_MASK                                       (1 << 8)
-
-/* Used by RM_DMA_DMA_SYSTEM_CONTEXT, RM_EMIF_DMM_CONTEXT */
-#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_SHIFT                                  8
-#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_WIDTH                                  0x1
-#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_MASK                                   (1 << 8)
-
-/* Used by RM_DSP_DSP_CONTEXT */
-#define OMAP54XX_LOSTMEM_DSP_EDMA_SHIFT                                         10
-#define OMAP54XX_LOSTMEM_DSP_EDMA_WIDTH                                         0x1
-#define OMAP54XX_LOSTMEM_DSP_EDMA_MASK                                          (1 << 10)
-
-/* Used by RM_DSP_DSP_CONTEXT */
-#define OMAP54XX_LOSTMEM_DSP_L1_SHIFT                                           8
-#define OMAP54XX_LOSTMEM_DSP_L1_WIDTH                                           0x1
-#define OMAP54XX_LOSTMEM_DSP_L1_MASK                                            (1 << 8)
-
-/* Used by RM_DSP_DSP_CONTEXT */
-#define OMAP54XX_LOSTMEM_DSP_L2_SHIFT                                           9
-#define OMAP54XX_LOSTMEM_DSP_L2_WIDTH                                           0x1
-#define OMAP54XX_LOSTMEM_DSP_L2_MASK                                            (1 << 9)
-
-/* Used by RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT */
-#define OMAP54XX_LOSTMEM_DSS_MEM_SHIFT                                          8
-#define OMAP54XX_LOSTMEM_DSS_MEM_WIDTH                                          0x1
-#define OMAP54XX_LOSTMEM_DSS_MEM_MASK                                           (1 << 8)
-
-/* Used by RM_EMU_DEBUGSS_CONTEXT */
-#define OMAP54XX_LOSTMEM_EMU_BANK_SHIFT                                         8
-#define OMAP54XX_LOSTMEM_EMU_BANK_WIDTH                                         0x1
-#define OMAP54XX_LOSTMEM_EMU_BANK_MASK                                          (1 << 8)
-
-/* Used by RM_GPU_GPU_CONTEXT */
-#define OMAP54XX_LOSTMEM_GPU_MEM_SHIFT                                          8
-#define OMAP54XX_LOSTMEM_GPU_MEM_WIDTH                                          0x1
-#define OMAP54XX_LOSTMEM_GPU_MEM_MASK                                           (1 << 8)
-
-/* Used by RM_IVA_IVA_CONTEXT */
-#define OMAP54XX_LOSTMEM_HWA_MEM_SHIFT                                          10
-#define OMAP54XX_LOSTMEM_HWA_MEM_WIDTH                                          0x1
-#define OMAP54XX_LOSTMEM_HWA_MEM_MASK                                           (1 << 10)
-
-/* Used by RM_IPU_IPU_CONTEXT */
-#define OMAP54XX_LOSTMEM_IPU_L2RAM_SHIFT                                        9
-#define OMAP54XX_LOSTMEM_IPU_L2RAM_WIDTH                                        0x1
-#define OMAP54XX_LOSTMEM_IPU_L2RAM_MASK                                         (1 << 9)
-
-/* Used by RM_IPU_IPU_CONTEXT */
-#define OMAP54XX_LOSTMEM_IPU_UNICACHE_SHIFT                                     8
-#define OMAP54XX_LOSTMEM_IPU_UNICACHE_WIDTH                                     0x1
-#define OMAP54XX_LOSTMEM_IPU_UNICACHE_MASK                                      (1 << 8)
-
-/*
- * Used by RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT,
- * RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT,
- * RM_L3INIT_USB_OTG_SS_CONTEXT
- */
-#define OMAP54XX_LOSTMEM_L3INIT_BANK1_SHIFT                                     8
-#define OMAP54XX_LOSTMEM_L3INIT_BANK1_WIDTH                                     0x1
-#define OMAP54XX_LOSTMEM_L3INIT_BANK1_MASK                                      (1 << 8)
-
-/* Used by RM_MPU_MPU_CONTEXT */
-#define OMAP54XX_LOSTMEM_MPU_L2_SHIFT                                           9
-#define OMAP54XX_LOSTMEM_MPU_L2_WIDTH                                           0x1
-#define OMAP54XX_LOSTMEM_MPU_L2_MASK                                            (1 << 9)
-
-/* Used by RM_MPU_MPU_CONTEXT */
-#define OMAP54XX_LOSTMEM_MPU_RAM_SHIFT                                          10
-#define OMAP54XX_LOSTMEM_MPU_RAM_WIDTH                                          0x1
-#define OMAP54XX_LOSTMEM_MPU_RAM_MASK                                           (1 << 10)
-
-/*
- * Used by RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT,
- * RM_L4SEC_FPKA_CONTEXT
- */
-#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_SHIFT                                 8
-#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_WIDTH                                 0x1
-#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_MASK                                  (1 << 8)
-
-/*
- * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT,
- * RM_ABE_MCBSP3_CONTEXT, RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT
- */
-#define OMAP54XX_LOSTMEM_PERIHPMEM_SHIFT                                        8
-#define OMAP54XX_LOSTMEM_PERIHPMEM_WIDTH                                        0x1
-#define OMAP54XX_LOSTMEM_PERIHPMEM_MASK                                         (1 << 8)
-
-/*
- * Used by RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT,
- * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT,
- * RM_L4PER_UART6_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT
- */
-#define OMAP54XX_LOSTMEM_RETAINED_BANK_SHIFT                                    8
-#define OMAP54XX_LOSTMEM_RETAINED_BANK_WIDTH                                    0x1
-#define OMAP54XX_LOSTMEM_RETAINED_BANK_MASK                                     (1 << 8)
-
-/* Used by RM_IVA_SL2_CONTEXT */
-#define OMAP54XX_LOSTMEM_SL2_MEM_SHIFT                                          8
-#define OMAP54XX_LOSTMEM_SL2_MEM_WIDTH                                          0x1
-#define OMAP54XX_LOSTMEM_SL2_MEM_MASK                                           (1 << 8)
-
-/* Used by RM_IVA_IVA_CONTEXT */
-#define OMAP54XX_LOSTMEM_TCM1_MEM_SHIFT                                         8
-#define OMAP54XX_LOSTMEM_TCM1_MEM_WIDTH                                         0x1
-#define OMAP54XX_LOSTMEM_TCM1_MEM_MASK                                          (1 << 8)
-
-/* Used by RM_IVA_IVA_CONTEXT */
-#define OMAP54XX_LOSTMEM_TCM2_MEM_SHIFT                                         9
-#define OMAP54XX_LOSTMEM_TCM2_MEM_WIDTH                                         0x1
-#define OMAP54XX_LOSTMEM_TCM2_MEM_MASK                                          (1 << 9)
-
-/* Used by RM_WKUPAON_SAR_RAM_CONTEXT */
-#define OMAP54XX_LOSTMEM_WKUP_BANK_SHIFT                                        8
-#define OMAP54XX_LOSTMEM_WKUP_BANK_WIDTH                                        0x1
-#define OMAP54XX_LOSTMEM_WKUP_BANK_MASK                                         (1 << 8)
-
-/*
- * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL,
- * PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL,
- * PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL
- */
-#define OMAP54XX_LOWPOWERSTATECHANGE_SHIFT                                      4
-#define OMAP54XX_LOWPOWERSTATECHANGE_WIDTH                                      0x1
-#define OMAP54XX_LOWPOWERSTATECHANGE_MASK                                       (1 << 4)
-
-/* Used by PRM_DEBUG_TRANS_CFG */
-#define OMAP54XX_MODE_SHIFT                                                     0
-#define OMAP54XX_MODE_WIDTH                                                     0x2
-#define OMAP54XX_MODE_MASK                                                      (0x3 << 0)
-
-/* Used by PRM_MODEM_IF_CTRL */
-#define OMAP54XX_MODEM_SHUTDOWN_IRQ_SHIFT                                       9
-#define OMAP54XX_MODEM_SHUTDOWN_IRQ_WIDTH                                       0x1
-#define OMAP54XX_MODEM_SHUTDOWN_IRQ_MASK                                        (1 << 9)
-
-/* Used by PRM_MODEM_IF_CTRL */
-#define OMAP54XX_MODEM_WAKE_IRQ_SHIFT                                           8
-#define OMAP54XX_MODEM_WAKE_IRQ_WIDTH                                           0x1
-#define OMAP54XX_MODEM_WAKE_IRQ_MASK                                            (1 << 8)
-
-/* Used by PM_MPU_PWRSTCTRL */
-#define OMAP54XX_MPU_L2_ONSTATE_SHIFT                                           18
-#define OMAP54XX_MPU_L2_ONSTATE_WIDTH                                           0x2
-#define OMAP54XX_MPU_L2_ONSTATE_MASK                                            (0x3 << 18)
-
-/* Used by PM_MPU_PWRSTCTRL */
-#define OMAP54XX_MPU_L2_RETSTATE_SHIFT                                          9
-#define OMAP54XX_MPU_L2_RETSTATE_WIDTH                                          0x1
-#define OMAP54XX_MPU_L2_RETSTATE_MASK                                           (1 << 9)
-
-/* Used by PM_MPU_PWRSTST */
-#define OMAP54XX_MPU_L2_STATEST_SHIFT                                           6
-#define OMAP54XX_MPU_L2_STATEST_WIDTH                                           0x2
-#define OMAP54XX_MPU_L2_STATEST_MASK                                            (0x3 << 6)
-
-/* Used by PM_MPU_PWRSTCTRL */
-#define OMAP54XX_MPU_RAM_ONSTATE_SHIFT                                          20
-#define OMAP54XX_MPU_RAM_ONSTATE_WIDTH                                          0x2
-#define OMAP54XX_MPU_RAM_ONSTATE_MASK                                           (0x3 << 20)
-
-/* Used by PM_MPU_PWRSTCTRL */
-#define OMAP54XX_MPU_RAM_RETSTATE_SHIFT                                         10
-#define OMAP54XX_MPU_RAM_RETSTATE_WIDTH                                         0x1
-#define OMAP54XX_MPU_RAM_RETSTATE_MASK                                          (1 << 10)
-
-/* Used by PM_MPU_PWRSTST */
-#define OMAP54XX_MPU_RAM_STATEST_SHIFT                                          8
-#define OMAP54XX_MPU_RAM_STATEST_WIDTH                                          0x2
-#define OMAP54XX_MPU_RAM_STATEST_MASK                                           (0x3 << 8)
-
-/* Used by PRM_RSTST */
-#define OMAP54XX_MPU_SECURITY_VIOL_RST_SHIFT                                    2
-#define OMAP54XX_MPU_SECURITY_VIOL_RST_WIDTH                                    0x1
-#define OMAP54XX_MPU_SECURITY_VIOL_RST_MASK                                     (1 << 2)
-
-/* Used by PRM_RSTST */
-#define OMAP54XX_MPU_WDT_RST_SHIFT                                              3
-#define OMAP54XX_MPU_WDT_RST_WIDTH                                              0x1
-#define OMAP54XX_MPU_WDT_RST_MASK                                               (1 << 3)
-
-/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
-#define OMAP54XX_NOCAP_SHIFT                                                    4
-#define OMAP54XX_NOCAP_WIDTH                                                    0x1
-#define OMAP54XX_NOCAP_MASK                                                     (1 << 4)
-
-/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP54XX_OCP_NRET_BANK_ONSTATE_SHIFT                                    24
-#define OMAP54XX_OCP_NRET_BANK_ONSTATE_WIDTH                                    0x2
-#define OMAP54XX_OCP_NRET_BANK_ONSTATE_MASK                                     (0x3 << 24)
-
-/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP54XX_OCP_NRET_BANK_RETSTATE_SHIFT                                   12
-#define OMAP54XX_OCP_NRET_BANK_RETSTATE_WIDTH                                   0x1
-#define OMAP54XX_OCP_NRET_BANK_RETSTATE_MASK                                    (1 << 12)
-
-/* Used by PM_CORE_PWRSTST */
-#define OMAP54XX_OCP_NRET_BANK_STATEST_SHIFT                                    12
-#define OMAP54XX_OCP_NRET_BANK_STATEST_WIDTH                                    0x2
-#define OMAP54XX_OCP_NRET_BANK_STATEST_MASK                                     (0x3 << 12)
-
-/*
- * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
- * PRM_VC_VAL_CMD_VDD_MPU_L
- */
-#define OMAP54XX_OFF_SHIFT                                                      0
-#define OMAP54XX_OFF_WIDTH                                                      0x8
-#define OMAP54XX_OFF_MASK                                                       (0xff << 0)
-
-/*
- * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
- * PRM_VC_VAL_CMD_VDD_MPU_L
- */
-#define OMAP54XX_ON_SHIFT                                                       24
-#define OMAP54XX_ON_WIDTH                                                       0x8
-#define OMAP54XX_ON_MASK                                                        (0xff << 24)
-
-/*
- * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
- * PRM_VC_VAL_CMD_VDD_MPU_L
- */
-#define OMAP54XX_ONLP_SHIFT                                                     16
-#define OMAP54XX_ONLP_WIDTH                                                     0x8
-#define OMAP54XX_ONLP_MASK                                                      (0xff << 16)
-
-/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
-#define OMAP54XX_OPP_CHANGE_SHIFT                                               2
-#define OMAP54XX_OPP_CHANGE_WIDTH                                               0x1
-#define OMAP54XX_OPP_CHANGE_MASK                                                (1 << 2)
-
-/* Used by PRM_VC_VAL_BYPASS */
-#define OMAP54XX_OPP_CHANGE_EMIF_LVL_SHIFT                                      25
-#define OMAP54XX_OPP_CHANGE_EMIF_LVL_WIDTH                                      0x1
-#define OMAP54XX_OPP_CHANGE_EMIF_LVL_MASK                                       (1 << 25)
-
-/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
-#define OMAP54XX_OPP_SEL_SHIFT                                                  0
-#define OMAP54XX_OPP_SEL_WIDTH                                                  0x2
-#define OMAP54XX_OPP_SEL_MASK                                                   (0x3 << 0)
-
-/* Used by PRM_DEBUG_OUT */
-#define OMAP54XX_OUTPUT_SHIFT                                                   0
-#define OMAP54XX_OUTPUT_WIDTH                                                   0x20
-#define OMAP54XX_OUTPUT_MASK                                                    (0xffffffff << 0)
-
-/* Used by PRM_SRAM_COUNT */
-#define OMAP54XX_PCHARGECNT_VALUE_SHIFT                                         0
-#define OMAP54XX_PCHARGECNT_VALUE_WIDTH                                         0x6
-#define OMAP54XX_PCHARGECNT_VALUE_MASK                                          (0x3f << 0)
-
-/* Used by PRM_PSCON_COUNT */
-#define OMAP54XX_PCHARGE_TIME_SHIFT                                             0
-#define OMAP54XX_PCHARGE_TIME_WIDTH                                             0x8
-#define OMAP54XX_PCHARGE_TIME_MASK                                              (0xff << 0)
-
-/* Used by PM_ABE_PWRSTCTRL */
-#define OMAP54XX_PERIPHMEM_ONSTATE_SHIFT                                        20
-#define OMAP54XX_PERIPHMEM_ONSTATE_WIDTH                                        0x2
-#define OMAP54XX_PERIPHMEM_ONSTATE_MASK                                         (0x3 << 20)
-
-/* Used by PM_ABE_PWRSTCTRL */
-#define OMAP54XX_PERIPHMEM_RETSTATE_SHIFT                                       10
-#define OMAP54XX_PERIPHMEM_RETSTATE_WIDTH                                       0x1
-#define OMAP54XX_PERIPHMEM_RETSTATE_MASK                                        (1 << 10)
-
-/* Used by PM_ABE_PWRSTST */
-#define OMAP54XX_PERIPHMEM_STATEST_SHIFT                                        8
-#define OMAP54XX_PERIPHMEM_STATEST_WIDTH                                        0x2
-#define OMAP54XX_PERIPHMEM_STATEST_MASK                                         (0x3 << 8)
-
-/* Used by PRM_PHASE1_CNDP */
-#define OMAP54XX_PHASE1_CNDP_SHIFT                                              0
-#define OMAP54XX_PHASE1_CNDP_WIDTH                                              0x20
-#define OMAP54XX_PHASE1_CNDP_MASK                                               (0xffffffff << 0)
-
-/* Used by PRM_PHASE2A_CNDP */
-#define OMAP54XX_PHASE2A_CNDP_SHIFT                                             0
-#define OMAP54XX_PHASE2A_CNDP_WIDTH                                             0x20
-#define OMAP54XX_PHASE2A_CNDP_MASK                                              (0xffffffff << 0)
-
-/* Used by PRM_PHASE2B_CNDP */
-#define OMAP54XX_PHASE2B_CNDP_SHIFT                                             0
-#define OMAP54XX_PHASE2B_CNDP_WIDTH                                             0x20
-#define OMAP54XX_PHASE2B_CNDP_MASK                                              (0xffffffff << 0)
-
-/* Used by PRM_PSCON_COUNT */
-#define OMAP54XX_PONOUT_2_PGOODIN_TIME_SHIFT                                    8
-#define OMAP54XX_PONOUT_2_PGOODIN_TIME_WIDTH                                    0x8
-#define OMAP54XX_PONOUT_2_PGOODIN_TIME_MASK                                     (0xff << 8)
-
-/*
- * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL,
- * PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL,
- * PM_EMU_PWRSTCTRL, PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL,
- * PM_MPU_PWRSTCTRL
- */
-#define OMAP54XX_POWERSTATE_SHIFT                                               0
-#define OMAP54XX_POWERSTATE_WIDTH                                               0x2
-#define OMAP54XX_POWERSTATE_MASK                                                (0x3 << 0)
-
-/*
- * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
- * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
- * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST
- */
-#define OMAP54XX_POWERSTATEST_SHIFT                                             0
-#define OMAP54XX_POWERSTATEST_WIDTH                                             0x2
-#define OMAP54XX_POWERSTATEST_MASK                                              (0x3 << 0)
-
-/* Used by PRM_PWRREQCTRL */
-#define OMAP54XX_PWRREQ_COND_SHIFT                                              0
-#define OMAP54XX_PWRREQ_COND_WIDTH                                              0x2
-#define OMAP54XX_PWRREQ_COND_MASK                                               (0x3 << 0)
-
-/* Used by PRM_VC_SMPS_CORE_CONFIG */
-#define OMAP54XX_RACEN_VDD_CORE_L_SHIFT                                         27
-#define OMAP54XX_RACEN_VDD_CORE_L_WIDTH                                         0x1
-#define OMAP54XX_RACEN_VDD_CORE_L_MASK                                          (1 << 27)
-
-/* Used by PRM_VC_SMPS_MM_CONFIG */
-#define OMAP54XX_RACEN_VDD_MM_L_SHIFT                                           27
-#define OMAP54XX_RACEN_VDD_MM_L_WIDTH                                           0x1
-#define OMAP54XX_RACEN_VDD_MM_L_MASK                                            (1 << 27)
-
-/* Used by PRM_VC_SMPS_MPU_CONFIG */
-#define OMAP54XX_RACEN_VDD_MPU_L_SHIFT                                          27
-#define OMAP54XX_RACEN_VDD_MPU_L_WIDTH                                          0x1
-#define OMAP54XX_RACEN_VDD_MPU_L_MASK                                           (1 << 27)
-
-/* Used by PRM_VC_SMPS_CORE_CONFIG */
-#define OMAP54XX_RAC_VDD_CORE_L_SHIFT                                           26
-#define OMAP54XX_RAC_VDD_CORE_L_WIDTH                                           0x1
-#define OMAP54XX_RAC_VDD_CORE_L_MASK                                            (1 << 26)
-
-/* Used by PRM_VC_SMPS_MM_CONFIG */
-#define OMAP54XX_RAC_VDD_MM_L_SHIFT                                             26
-#define OMAP54XX_RAC_VDD_MM_L_WIDTH                                             0x1
-#define OMAP54XX_RAC_VDD_MM_L_MASK                                              (1 << 26)
-
-/* Used by PRM_VC_SMPS_MPU_CONFIG */
-#define OMAP54XX_RAC_VDD_MPU_L_SHIFT                                            26
-#define OMAP54XX_RAC_VDD_MPU_L_WIDTH                                            0x1
-#define OMAP54XX_RAC_VDD_MPU_L_MASK                                             (1 << 26)
-
-/*
- * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
- * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
- * PRM_VOLTSETUP_MPU_RET_SLEEP
- */
-#define OMAP54XX_RAMP_DOWN_COUNT_SHIFT                                          16
-#define OMAP54XX_RAMP_DOWN_COUNT_WIDTH                                          0x6
-#define OMAP54XX_RAMP_DOWN_COUNT_MASK                                           (0x3f << 16)
-
-/*
- * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
- * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
- * PRM_VOLTSETUP_MPU_RET_SLEEP
- */
-#define OMAP54XX_RAMP_DOWN_PRESCAL_SHIFT                                        24
-#define OMAP54XX_RAMP_DOWN_PRESCAL_WIDTH                                        0x2
-#define OMAP54XX_RAMP_DOWN_PRESCAL_MASK                                         (0x3 << 24)
-
-/*
- * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
- * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
- * PRM_VOLTSETUP_MPU_RET_SLEEP
- */
-#define OMAP54XX_RAMP_UP_COUNT_SHIFT                                            0
-#define OMAP54XX_RAMP_UP_COUNT_WIDTH                                            0x6
-#define OMAP54XX_RAMP_UP_COUNT_MASK                                             (0x3f << 0)
-
-/*
- * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
- * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
- * PRM_VOLTSETUP_MPU_RET_SLEEP
- */
-#define OMAP54XX_RAMP_UP_PRESCAL_SHIFT                                          8
-#define OMAP54XX_RAMP_UP_PRESCAL_WIDTH                                          0x2
-#define OMAP54XX_RAMP_UP_PRESCAL_MASK                                           (0x3 << 8)
-
-/* Used by PRM_VC_SMPS_CORE_CONFIG */
-#define OMAP54XX_RAV_VDD_CORE_L_SHIFT                                           25
-#define OMAP54XX_RAV_VDD_CORE_L_WIDTH                                           0x1
-#define OMAP54XX_RAV_VDD_CORE_L_MASK                                            (1 << 25)
-
-/* Used by PRM_VC_SMPS_MM_CONFIG */
-#define OMAP54XX_RAV_VDD_MM_L_SHIFT                                             25
-#define OMAP54XX_RAV_VDD_MM_L_WIDTH                                             0x1
-#define OMAP54XX_RAV_VDD_MM_L_MASK                                              (1 << 25)
-
-/* Used by PRM_VC_SMPS_MPU_CONFIG */
-#define OMAP54XX_RAV_VDD_MPU_L_SHIFT                                            25
-#define OMAP54XX_RAV_VDD_MPU_L_WIDTH                                            0x1
-#define OMAP54XX_RAV_VDD_MPU_L_MASK                                             (1 << 25)
-
-/* Used by PRM_VC_VAL_BYPASS */
-#define OMAP54XX_REGADDR_SHIFT                                                  8
-#define OMAP54XX_REGADDR_WIDTH                                                  0x8
-#define OMAP54XX_REGADDR_MASK                                                   (0xff << 8)
-
-/*
- * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
- * PRM_VC_VAL_CMD_VDD_MPU_L
- */
-#define OMAP54XX_RET_SHIFT                                                      8
-#define OMAP54XX_RET_WIDTH                                                      0x8
-#define OMAP54XX_RET_MASK                                                       (0xff << 8)
-
-/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */
-#define OMAP54XX_RETMODE_ENABLE_SHIFT                                           0
-#define OMAP54XX_RETMODE_ENABLE_WIDTH                                           0x1
-#define OMAP54XX_RETMODE_ENABLE_MASK                                            (1 << 0)
-
-/* Used by PRM_RSTTIME */
-#define OMAP54XX_RSTTIME1_SHIFT                                                 0
-#define OMAP54XX_RSTTIME1_WIDTH                                                 0xa
-#define OMAP54XX_RSTTIME1_MASK                                                  (0x3ff << 0)
-
-/* Used by PRM_RSTTIME */
-#define OMAP54XX_RSTTIME2_SHIFT                                                 10
-#define OMAP54XX_RSTTIME2_WIDTH                                                 0x5
-#define OMAP54XX_RSTTIME2_MASK                                                  (0x1f << 10)
-
-/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */
-#define OMAP54XX_RST_CPU0_SHIFT                                                 0
-#define OMAP54XX_RST_CPU0_WIDTH                                                 0x1
-#define OMAP54XX_RST_CPU0_MASK                                                  (1 << 0)
-
-/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */
-#define OMAP54XX_RST_CPU1_SHIFT                                                 1
-#define OMAP54XX_RST_CPU1_WIDTH                                                 0x1
-#define OMAP54XX_RST_CPU1_MASK                                                  (1 << 1)
-
-/* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */
-#define OMAP54XX_RST_DSP_SHIFT                                                  0
-#define OMAP54XX_RST_DSP_WIDTH                                                  0x1
-#define OMAP54XX_RST_DSP_MASK                                                   (1 << 0)
-
-/* Used by RM_DSP_RSTST */
-#define OMAP54XX_RST_DSP_EMU_SHIFT                                              2
-#define OMAP54XX_RST_DSP_EMU_WIDTH                                              0x1
-#define OMAP54XX_RST_DSP_EMU_MASK                                               (1 << 2)
-
-/* Used by RM_DSP_RSTST */
-#define OMAP54XX_RST_DSP_EMU_REQ_SHIFT                                          3
-#define OMAP54XX_RST_DSP_EMU_REQ_WIDTH                                          0x1
-#define OMAP54XX_RST_DSP_EMU_REQ_MASK                                           (1 << 3)
-
-/* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */
-#define OMAP54XX_RST_DSP_MMU_CACHE_SHIFT                                        1
-#define OMAP54XX_RST_DSP_MMU_CACHE_WIDTH                                        0x1
-#define OMAP54XX_RST_DSP_MMU_CACHE_MASK                                         (1 << 1)
-
-/* Used by RM_IPU_RSTST */
-#define OMAP54XX_RST_EMULATION_CPU0_SHIFT                                       3
-#define OMAP54XX_RST_EMULATION_CPU0_WIDTH                                       0x1
-#define OMAP54XX_RST_EMULATION_CPU0_MASK                                        (1 << 3)
-
-/* Used by RM_IPU_RSTST */
-#define OMAP54XX_RST_EMULATION_CPU1_SHIFT                                       4
-#define OMAP54XX_RST_EMULATION_CPU1_WIDTH                                       0x1
-#define OMAP54XX_RST_EMULATION_CPU1_MASK                                        (1 << 4)
-
-/* Used by RM_IVA_RSTST */
-#define OMAP54XX_RST_EMULATION_SEQ1_SHIFT                                       3
-#define OMAP54XX_RST_EMULATION_SEQ1_WIDTH                                       0x1
-#define OMAP54XX_RST_EMULATION_SEQ1_MASK                                        (1 << 3)
-
-/* Used by RM_IVA_RSTST */
-#define OMAP54XX_RST_EMULATION_SEQ2_SHIFT                                       4
-#define OMAP54XX_RST_EMULATION_SEQ2_WIDTH                                       0x1
-#define OMAP54XX_RST_EMULATION_SEQ2_MASK                                        (1 << 4)
-
-/* Used by PRM_RSTCTRL */
-#define OMAP54XX_RST_GLOBAL_COLD_SW_SHIFT                                       1
-#define OMAP54XX_RST_GLOBAL_COLD_SW_WIDTH                                       0x1
-#define OMAP54XX_RST_GLOBAL_COLD_SW_MASK                                        (1 << 1)
-
-/* Used by PRM_RSTCTRL */
-#define OMAP54XX_RST_GLOBAL_WARM_SW_SHIFT                                       0
-#define OMAP54XX_RST_GLOBAL_WARM_SW_WIDTH                                       0x1
-#define OMAP54XX_RST_GLOBAL_WARM_SW_MASK                                        (1 << 0)
-
-/* Used by RM_IPU_RSTST */
-#define OMAP54XX_RST_ICECRUSHER_CPU0_SHIFT                                      5
-#define OMAP54XX_RST_ICECRUSHER_CPU0_WIDTH                                      0x1
-#define OMAP54XX_RST_ICECRUSHER_CPU0_MASK                                       (1 << 5)
-
-/* Used by RM_IPU_RSTST */
-#define OMAP54XX_RST_ICECRUSHER_CPU1_SHIFT                                      6
-#define OMAP54XX_RST_ICECRUSHER_CPU1_WIDTH                                      0x1
-#define OMAP54XX_RST_ICECRUSHER_CPU1_MASK                                       (1 << 6)
-
-/* Used by RM_IVA_RSTST */
-#define OMAP54XX_RST_ICECRUSHER_SEQ1_SHIFT                                      5
-#define OMAP54XX_RST_ICECRUSHER_SEQ1_WIDTH                                      0x1
-#define OMAP54XX_RST_ICECRUSHER_SEQ1_MASK                                       (1 << 5)
-
-/* Used by RM_IVA_RSTST */
-#define OMAP54XX_RST_ICECRUSHER_SEQ2_SHIFT                                      6
-#define OMAP54XX_RST_ICECRUSHER_SEQ2_WIDTH                                      0x1
-#define OMAP54XX_RST_ICECRUSHER_SEQ2_MASK                                       (1 << 6)
-
-/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */
-#define OMAP54XX_RST_IPU_MMU_CACHE_SHIFT                                        2
-#define OMAP54XX_RST_IPU_MMU_CACHE_WIDTH                                        0x1
-#define OMAP54XX_RST_IPU_MMU_CACHE_MASK                                         (1 << 2)
-
-/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
-#define OMAP54XX_RST_LOGIC_SHIFT                                                2
-#define OMAP54XX_RST_LOGIC_WIDTH                                                0x1
-#define OMAP54XX_RST_LOGIC_MASK                                                 (1 << 2)
-
-/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
-#define OMAP54XX_RST_SEQ1_SHIFT                                                 0
-#define OMAP54XX_RST_SEQ1_WIDTH                                                 0x1
-#define OMAP54XX_RST_SEQ1_MASK                                                  (1 << 0)
-
-/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
-#define OMAP54XX_RST_SEQ2_SHIFT                                                 1
-#define OMAP54XX_RST_SEQ2_WIDTH                                                 0x1
-#define OMAP54XX_RST_SEQ2_MASK                                                  (1 << 1)
-
-/* Used by REVISION_PRM */
-#define OMAP54XX_R_RTL_SHIFT                                                    11
-#define OMAP54XX_R_RTL_WIDTH                                                    0x5
-#define OMAP54XX_R_RTL_MASK                                                     (0x1f << 11)
-
-/* Used by PRM_VC_SMPS_CORE_CONFIG */
-#define OMAP54XX_SA_VDD_CORE_L_SHIFT                                            0
-#define OMAP54XX_SA_VDD_CORE_L_WIDTH                                            0x7
-#define OMAP54XX_SA_VDD_CORE_L_MASK                                             (0x7f << 0)
-
-/* Used by PRM_VC_SMPS_MM_CONFIG */
-#define OMAP54XX_SA_VDD_MM_L_SHIFT                                              0
-#define OMAP54XX_SA_VDD_MM_L_WIDTH                                              0x7
-#define OMAP54XX_SA_VDD_MM_L_MASK                                               (0x7f << 0)
-
-/* Used by PRM_VC_SMPS_MPU_CONFIG */
-#define OMAP54XX_SA_VDD_MPU_L_SHIFT                                             0
-#define OMAP54XX_SA_VDD_MPU_L_WIDTH                                             0x7
-#define OMAP54XX_SA_VDD_MPU_L_MASK                                              (0x7f << 0)
-
-/* Used by REVISION_PRM */
-#define OMAP54XX_SCHEME_SHIFT                                                   30
-#define OMAP54XX_SCHEME_WIDTH                                                   0x2
-#define OMAP54XX_SCHEME_MASK                                                    (0x3 << 30)
-
-/* Used by PRM_VC_CFG_I2C_CLK */
-#define OMAP54XX_SCLH_SHIFT                                                     0
-#define OMAP54XX_SCLH_WIDTH                                                     0x8
-#define OMAP54XX_SCLH_MASK                                                      (0xff << 0)
-
-/* Used by PRM_VC_CFG_I2C_CLK */
-#define OMAP54XX_SCLL_SHIFT                                                     8
-#define OMAP54XX_SCLL_WIDTH                                                     0x8
-#define OMAP54XX_SCLL_MASK                                                      (0xff << 8)
-
-/* Used by PRM_RSTST */
-#define OMAP54XX_SECURE_WDT_RST_SHIFT                                           4
-#define OMAP54XX_SECURE_WDT_RST_WIDTH                                           0x1
-#define OMAP54XX_SECURE_WDT_RST_MASK                                            (1 << 4)
-
-/* Used by PRM_VC_SMPS_CORE_CONFIG */
-#define OMAP54XX_SEL_SA_VDD_CORE_L_SHIFT                                        24
-#define OMAP54XX_SEL_SA_VDD_CORE_L_WIDTH                                        0x1
-#define OMAP54XX_SEL_SA_VDD_CORE_L_MASK                                         (1 << 24)
-
-/* Used by PRM_VC_SMPS_MM_CONFIG */
-#define OMAP54XX_SEL_SA_VDD_MM_L_SHIFT                                          24
-#define OMAP54XX_SEL_SA_VDD_MM_L_WIDTH                                          0x1
-#define OMAP54XX_SEL_SA_VDD_MM_L_MASK                                           (1 << 24)
-
-/* Used by PRM_VC_SMPS_MPU_CONFIG */
-#define OMAP54XX_SEL_SA_VDD_MPU_L_SHIFT                                         24
-#define OMAP54XX_SEL_SA_VDD_MPU_L_WIDTH                                         0x1
-#define OMAP54XX_SEL_SA_VDD_MPU_L_MASK                                          (1 << 24)
-
-/* Used by PM_IVA_PWRSTCTRL */
-#define OMAP54XX_SL2_MEM_ONSTATE_SHIFT                                          18
-#define OMAP54XX_SL2_MEM_ONSTATE_WIDTH                                          0x2
-#define OMAP54XX_SL2_MEM_ONSTATE_MASK                                           (0x3 << 18)
-
-/* Used by PM_IVA_PWRSTCTRL */
-#define OMAP54XX_SL2_MEM_RETSTATE_SHIFT                                         9
-#define OMAP54XX_SL2_MEM_RETSTATE_WIDTH                                         0x1
-#define OMAP54XX_SL2_MEM_RETSTATE_MASK                                          (1 << 9)
-
-/* Used by PM_IVA_PWRSTST */
-#define OMAP54XX_SL2_MEM_STATEST_SHIFT                                          6
-#define OMAP54XX_SL2_MEM_STATEST_WIDTH                                          0x2
-#define OMAP54XX_SL2_MEM_STATEST_MASK                                           (0x3 << 6)
-
-/* Used by PRM_VC_VAL_BYPASS */
-#define OMAP54XX_SLAVEADDR_SHIFT                                                0
-#define OMAP54XX_SLAVEADDR_WIDTH                                                0x7
-#define OMAP54XX_SLAVEADDR_MASK                                                 (0x7f << 0)
-
-/* Used by PRM_SRAM_COUNT */
-#define OMAP54XX_SLPCNT_VALUE_SHIFT                                             16
-#define OMAP54XX_SLPCNT_VALUE_WIDTH                                             0x8
-#define OMAP54XX_SLPCNT_VALUE_MASK                                              (0xff << 16)
-
-/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
-#define OMAP54XX_SMPSWAITTIMEMAX_SHIFT                                          8
-#define OMAP54XX_SMPSWAITTIMEMAX_WIDTH                                          0x10
-#define OMAP54XX_SMPSWAITTIMEMAX_MASK                                           (0xffff << 8)
-
-/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
-#define OMAP54XX_SMPSWAITTIMEMIN_SHIFT                                          8
-#define OMAP54XX_SMPSWAITTIMEMIN_WIDTH                                          0x10
-#define OMAP54XX_SMPSWAITTIMEMIN_MASK                                           (0xffff << 8)
-
-/* Used by PRM_VC_CORE_ERRST */
-#define OMAP54XX_SMPS_RA_ERR_CORE_SHIFT                                         1
-#define OMAP54XX_SMPS_RA_ERR_CORE_WIDTH                                         0x1
-#define OMAP54XX_SMPS_RA_ERR_CORE_MASK                                          (1 << 1)
-
-/* Used by PRM_VC_MM_ERRST */
-#define OMAP54XX_SMPS_RA_ERR_MM_SHIFT                                           1
-#define OMAP54XX_SMPS_RA_ERR_MM_WIDTH                                           0x1
-#define OMAP54XX_SMPS_RA_ERR_MM_MASK                                            (1 << 1)
-
-/* Used by PRM_VC_MPU_ERRST */
-#define OMAP54XX_SMPS_RA_ERR_MPU_SHIFT                                          1
-#define OMAP54XX_SMPS_RA_ERR_MPU_WIDTH                                          0x1
-#define OMAP54XX_SMPS_RA_ERR_MPU_MASK                                           (1 << 1)
-
-/* Used by PRM_VC_CORE_ERRST */
-#define OMAP54XX_SMPS_SA_ERR_CORE_SHIFT                                         0
-#define OMAP54XX_SMPS_SA_ERR_CORE_WIDTH                                         0x1
-#define OMAP54XX_SMPS_SA_ERR_CORE_MASK                                          (1 << 0)
-
-/* Used by PRM_VC_MM_ERRST */
-#define OMAP54XX_SMPS_SA_ERR_MM_SHIFT                                           0
-#define OMAP54XX_SMPS_SA_ERR_MM_WIDTH                                           0x1
-#define OMAP54XX_SMPS_SA_ERR_MM_MASK                                            (1 << 0)
-
-/* Used by PRM_VC_MPU_ERRST */
-#define OMAP54XX_SMPS_SA_ERR_MPU_SHIFT                                          0
-#define OMAP54XX_SMPS_SA_ERR_MPU_WIDTH                                          0x1
-#define OMAP54XX_SMPS_SA_ERR_MPU_MASK                                           (1 << 0)
-
-/* Used by PRM_VC_CORE_ERRST */
-#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_SHIFT                                    2
-#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_WIDTH                                    0x1
-#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_MASK                                     (1 << 2)
-
-/* Used by PRM_VC_MM_ERRST */
-#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_SHIFT                                      2
-#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_WIDTH                                      0x1
-#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_MASK                                       (1 << 2)
-
-/* Used by PRM_VC_MPU_ERRST */
-#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_SHIFT                                     2
-#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_WIDTH                                     0x1
-#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_MASK                                      (1 << 2)
-
-/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
-#define OMAP54XX_SR2EN_SHIFT                                                    0
-#define OMAP54XX_SR2EN_WIDTH                                                    0x1
-#define OMAP54XX_SR2EN_MASK                                                     (1 << 0)
-
-/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
-#define OMAP54XX_SR2_IN_TRANSITION_SHIFT                                        6
-#define OMAP54XX_SR2_IN_TRANSITION_WIDTH                                        0x1
-#define OMAP54XX_SR2_IN_TRANSITION_MASK                                         (1 << 6)
-
-/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
-#define OMAP54XX_SR2_STATUS_SHIFT                                               3
-#define OMAP54XX_SR2_STATUS_WIDTH                                               0x2
-#define OMAP54XX_SR2_STATUS_MASK                                                (0x3 << 3)
-
-/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
-#define OMAP54XX_SR2_WTCNT_VALUE_SHIFT                                          8
-#define OMAP54XX_SR2_WTCNT_VALUE_WIDTH                                          0x8
-#define OMAP54XX_SR2_WTCNT_VALUE_MASK                                           (0xff << 8)
-
-/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */
-#define OMAP54XX_SRAMLDO_STATUS_SHIFT                                           8
-#define OMAP54XX_SRAMLDO_STATUS_WIDTH                                           0x1
-#define OMAP54XX_SRAMLDO_STATUS_MASK                                            (1 << 8)
-
-/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */
-#define OMAP54XX_SRAM_IN_TRANSITION_SHIFT                                       9
-#define OMAP54XX_SRAM_IN_TRANSITION_WIDTH                                       0x1
-#define OMAP54XX_SRAM_IN_TRANSITION_MASK                                        (1 << 9)
-
-/* Used by PRM_VC_CFG_I2C_MODE */
-#define OMAP54XX_SRMODEEN_SHIFT                                                 4
-#define OMAP54XX_SRMODEEN_WIDTH                                                 0x1
-#define OMAP54XX_SRMODEEN_MASK                                                  (1 << 4)
-
-/* Used by PRM_VOLTSETUP_WARMRESET */
-#define OMAP54XX_STABLE_COUNT_SHIFT                                             0
-#define OMAP54XX_STABLE_COUNT_WIDTH                                             0x6
-#define OMAP54XX_STABLE_COUNT_MASK                                              (0x3f << 0)
-
-/* Used by PRM_VOLTSETUP_WARMRESET */
-#define OMAP54XX_STABLE_PRESCAL_SHIFT                                           8
-#define OMAP54XX_STABLE_PRESCAL_WIDTH                                           0x2
-#define OMAP54XX_STABLE_PRESCAL_MASK                                            (0x3 << 8)
-
-/* Used by PRM_BANDGAP_SETUP */
-#define OMAP54XX_STARTUP_COUNT_SHIFT                                            0
-#define OMAP54XX_STARTUP_COUNT_WIDTH                                            0x8
-#define OMAP54XX_STARTUP_COUNT_MASK                                             (0xff << 0)
-
-/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */
-#define OMAP54XX_STARTUP_COUNT_24_31_SHIFT                                      24
-#define OMAP54XX_STARTUP_COUNT_24_31_WIDTH                                      0x8
-#define OMAP54XX_STARTUP_COUNT_24_31_MASK                                       (0xff << 24)
-
-/* Used by PM_IVA_PWRSTCTRL */
-#define OMAP54XX_TCM1_MEM_ONSTATE_SHIFT                                         20
-#define OMAP54XX_TCM1_MEM_ONSTATE_WIDTH                                         0x2
-#define OMAP54XX_TCM1_MEM_ONSTATE_MASK                                          (0x3 << 20)
-
-/* Used by PM_IVA_PWRSTCTRL */
-#define OMAP54XX_TCM1_MEM_RETSTATE_SHIFT                                        10
-#define OMAP54XX_TCM1_MEM_RETSTATE_WIDTH                                        0x1
-#define OMAP54XX_TCM1_MEM_RETSTATE_MASK                                         (1 << 10)
-
-/* Used by PM_IVA_PWRSTST */
-#define OMAP54XX_TCM1_MEM_STATEST_SHIFT                                         8
-#define OMAP54XX_TCM1_MEM_STATEST_WIDTH                                         0x2
-#define OMAP54XX_TCM1_MEM_STATEST_MASK                                          (0x3 << 8)
-
-/* Used by PM_IVA_PWRSTCTRL */
-#define OMAP54XX_TCM2_MEM_ONSTATE_SHIFT                                         22
-#define OMAP54XX_TCM2_MEM_ONSTATE_WIDTH                                         0x2
-#define OMAP54XX_TCM2_MEM_ONSTATE_MASK                                          (0x3 << 22)
-
-/* Used by PM_IVA_PWRSTCTRL */
-#define OMAP54XX_TCM2_MEM_RETSTATE_SHIFT                                        11
-#define OMAP54XX_TCM2_MEM_RETSTATE_WIDTH                                        0x1
-#define OMAP54XX_TCM2_MEM_RETSTATE_MASK                                         (1 << 11)
-
-/* Used by PM_IVA_PWRSTST */
-#define OMAP54XX_TCM2_MEM_STATEST_SHIFT                                         10
-#define OMAP54XX_TCM2_MEM_STATEST_WIDTH                                         0x2
-#define OMAP54XX_TCM2_MEM_STATEST_MASK                                          (0x3 << 10)
-
-/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */
-#define OMAP54XX_TIMEOUT_SHIFT                                                  0
-#define OMAP54XX_TIMEOUT_WIDTH                                                  0x10
-#define OMAP54XX_TIMEOUT_MASK                                                   (0xffff << 0)
-
-/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP54XX_TIMEOUTEN_SHIFT                                                3
-#define OMAP54XX_TIMEOUTEN_WIDTH                                                0x1
-#define OMAP54XX_TIMEOUTEN_MASK                                                 (1 << 3)
-
-/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
-#define OMAP54XX_TRANSITION_EN_SHIFT                                            8
-#define OMAP54XX_TRANSITION_EN_WIDTH                                            0x1
-#define OMAP54XX_TRANSITION_EN_MASK                                             (1 << 8)
-
-/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
-#define OMAP54XX_TRANSITION_ST_SHIFT                                            8
-#define OMAP54XX_TRANSITION_ST_WIDTH                                            0x1
-#define OMAP54XX_TRANSITION_ST_MASK                                             (1 << 8)
-
-/* Used by PRM_DEBUG_TRANS_CFG */
-#define OMAP54XX_TRIGGER_CLEAR_SHIFT                                            2
-#define OMAP54XX_TRIGGER_CLEAR_WIDTH                                            0x1
-#define OMAP54XX_TRIGGER_CLEAR_MASK                                             (1 << 2)
-
-/* Used by PRM_RSTST */
-#define OMAP54XX_TSHUT_CORE_RST_SHIFT                                           13
-#define OMAP54XX_TSHUT_CORE_RST_WIDTH                                           0x1
-#define OMAP54XX_TSHUT_CORE_RST_MASK                                            (1 << 13)
-
-/* Used by PRM_RSTST */
-#define OMAP54XX_TSHUT_MM_RST_SHIFT                                             12
-#define OMAP54XX_TSHUT_MM_RST_WIDTH                                             0x1
-#define OMAP54XX_TSHUT_MM_RST_MASK                                              (1 << 12)
-
-/* Used by PRM_RSTST */
-#define OMAP54XX_TSHUT_MPU_RST_SHIFT                                            11
-#define OMAP54XX_TSHUT_MPU_RST_WIDTH                                            0x1
-#define OMAP54XX_TSHUT_MPU_RST_MASK                                             (1 << 11)
-
-/* Used by PRM_VC_VAL_BYPASS */
-#define OMAP54XX_VALID_SHIFT                                                    24
-#define OMAP54XX_VALID_WIDTH                                                    0x1
-#define OMAP54XX_VALID_MASK                                                     (1 << 24)
-
-/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
-#define OMAP54XX_VC_BYPASSACK_EN_SHIFT                                          14
-#define OMAP54XX_VC_BYPASSACK_EN_WIDTH                                          0x1
-#define OMAP54XX_VC_BYPASSACK_EN_MASK                                           (1 << 14)
-
-/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
-#define OMAP54XX_VC_BYPASSACK_ST_SHIFT                                          14
-#define OMAP54XX_VC_BYPASSACK_ST_WIDTH                                          0x1
-#define OMAP54XX_VC_BYPASSACK_ST_MASK                                           (1 << 14)
-
-/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
-#define OMAP54XX_VC_CORE_VPACK_EN_SHIFT                                         22
-#define OMAP54XX_VC_CORE_VPACK_EN_WIDTH                                         0x1
-#define OMAP54XX_VC_CORE_VPACK_EN_MASK                                          (1 << 22)
-
-/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
-#define OMAP54XX_VC_CORE_VPACK_ST_SHIFT                                         22
-#define OMAP54XX_VC_CORE_VPACK_ST_WIDTH                                         0x1
-#define OMAP54XX_VC_CORE_VPACK_ST_MASK                                          (1 << 22)
-
-/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
-#define OMAP54XX_VC_MM_VPACK_EN_SHIFT                                           30
-#define OMAP54XX_VC_MM_VPACK_EN_WIDTH                                           0x1
-#define OMAP54XX_VC_MM_VPACK_EN_MASK                                            (1 << 30)
-
-/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
-#define OMAP54XX_VC_MM_VPACK_ST_SHIFT                                           30
-#define OMAP54XX_VC_MM_VPACK_ST_WIDTH                                           0x1
-#define OMAP54XX_VC_MM_VPACK_ST_MASK                                            (1 << 30)
-
-/* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP54XX_VC_MPU_VPACK_EN_SHIFT                                          6
-#define OMAP54XX_VC_MPU_VPACK_EN_WIDTH                                          0x1
-#define OMAP54XX_VC_MPU_VPACK_EN_MASK                                           (1 << 6)
-
-/* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP54XX_VC_MPU_VPACK_ST_SHIFT                                          6
-#define OMAP54XX_VC_MPU_VPACK_ST_WIDTH                                          0x1
-#define OMAP54XX_VC_MPU_VPACK_ST_MASK                                           (1 << 6)
-
-/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
-#define OMAP54XX_VC_RAERR_EN_SHIFT                                              12
-#define OMAP54XX_VC_RAERR_EN_WIDTH                                              0x1
-#define OMAP54XX_VC_RAERR_EN_MASK                                               (1 << 12)
-
-/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
-#define OMAP54XX_VC_RAERR_ST_SHIFT                                              12
-#define OMAP54XX_VC_RAERR_ST_WIDTH                                              0x1
-#define OMAP54XX_VC_RAERR_ST_MASK                                               (1 << 12)
-
-/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
-#define OMAP54XX_VC_SAERR_EN_SHIFT                                              11
-#define OMAP54XX_VC_SAERR_EN_WIDTH                                              0x1
-#define OMAP54XX_VC_SAERR_EN_MASK                                               (1 << 11)
-
-/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
-#define OMAP54XX_VC_SAERR_ST_SHIFT                                              11
-#define OMAP54XX_VC_SAERR_ST_WIDTH                                              0x1
-#define OMAP54XX_VC_SAERR_ST_MASK                                               (1 << 11)
-
-/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
-#define OMAP54XX_VC_TOERR_EN_SHIFT                                              13
-#define OMAP54XX_VC_TOERR_EN_WIDTH                                              0x1
-#define OMAP54XX_VC_TOERR_EN_MASK                                               (1 << 13)
-
-/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
-#define OMAP54XX_VC_TOERR_ST_SHIFT                                              13
-#define OMAP54XX_VC_TOERR_ST_WIDTH                                              0x1
-#define OMAP54XX_VC_TOERR_ST_MASK                                               (1 << 13)
-
-/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */
-#define OMAP54XX_VDDMAX_SHIFT                                                   24
-#define OMAP54XX_VDDMAX_WIDTH                                                   0x8
-#define OMAP54XX_VDDMAX_MASK                                                    (0xff << 24)
-
-/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */
-#define OMAP54XX_VDDMIN_SHIFT                                                   16
-#define OMAP54XX_VDDMIN_WIDTH                                                   0x8
-#define OMAP54XX_VDDMIN_MASK                                                    (0xff << 16)
-
-/* Used by PRM_VOLTCTRL */
-#define OMAP54XX_VDD_CORE_I2C_DISABLE_SHIFT                                     12
-#define OMAP54XX_VDD_CORE_I2C_DISABLE_WIDTH                                     0x1
-#define OMAP54XX_VDD_CORE_I2C_DISABLE_MASK                                      (1 << 12)
-
-/* Used by PRM_RSTST */
-#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_SHIFT                                    8
-#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_WIDTH                                    0x1
-#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_MASK                                     (1 << 8)
-
-/* Used by PRM_VOLTCTRL */
-#define OMAP54XX_VDD_MM_I2C_DISABLE_SHIFT                                       14
-#define OMAP54XX_VDD_MM_I2C_DISABLE_WIDTH                                       0x1
-#define OMAP54XX_VDD_MM_I2C_DISABLE_MASK                                        (1 << 14)
-
-/* Used by PRM_VOLTCTRL */
-#define OMAP54XX_VDD_MM_PRESENCE_SHIFT                                          9
-#define OMAP54XX_VDD_MM_PRESENCE_WIDTH                                          0x1
-#define OMAP54XX_VDD_MM_PRESENCE_MASK                                           (1 << 9)
-
-/* Used by PRM_RSTST */
-#define OMAP54XX_VDD_MM_VOLT_MGR_RST_SHIFT                                      7
-#define OMAP54XX_VDD_MM_VOLT_MGR_RST_WIDTH                                      0x1
-#define OMAP54XX_VDD_MM_VOLT_MGR_RST_MASK                                       (1 << 7)
-
-/* Used by PRM_VOLTCTRL */
-#define OMAP54XX_VDD_MPU_I2C_DISABLE_SHIFT                                      13
-#define OMAP54XX_VDD_MPU_I2C_DISABLE_WIDTH                                      0x1
-#define OMAP54XX_VDD_MPU_I2C_DISABLE_MASK                                       (1 << 13)
-
-/* Used by PRM_VOLTCTRL */
-#define OMAP54XX_VDD_MPU_PRESENCE_SHIFT                                         8
-#define OMAP54XX_VDD_MPU_PRESENCE_WIDTH                                         0x1
-#define OMAP54XX_VDD_MPU_PRESENCE_MASK                                          (1 << 8)
-
-/* Used by PRM_RSTST */
-#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_SHIFT                                     6
-#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_WIDTH                                     0x1
-#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_MASK                                      (1 << 6)
-
-/* Used by PRM_VC_CORE_ERRST */
-#define OMAP54XX_VFSM_RA_ERR_CORE_SHIFT                                         4
-#define OMAP54XX_VFSM_RA_ERR_CORE_WIDTH                                         0x1
-#define OMAP54XX_VFSM_RA_ERR_CORE_MASK                                          (1 << 4)
-
-/* Used by PRM_VC_MM_ERRST */
-#define OMAP54XX_VFSM_RA_ERR_MM_SHIFT                                           4
-#define OMAP54XX_VFSM_RA_ERR_MM_WIDTH                                           0x1
-#define OMAP54XX_VFSM_RA_ERR_MM_MASK                                            (1 << 4)
-
-/* Used by PRM_VC_MPU_ERRST */
-#define OMAP54XX_VFSM_RA_ERR_MPU_SHIFT                                          4
-#define OMAP54XX_VFSM_RA_ERR_MPU_WIDTH                                          0x1
-#define OMAP54XX_VFSM_RA_ERR_MPU_MASK                                           (1 << 4)
-
-/* Used by PRM_VC_CORE_ERRST */
-#define OMAP54XX_VFSM_SA_ERR_CORE_SHIFT                                         3
-#define OMAP54XX_VFSM_SA_ERR_CORE_WIDTH                                         0x1
-#define OMAP54XX_VFSM_SA_ERR_CORE_MASK                                          (1 << 3)
-
-/* Used by PRM_VC_MM_ERRST */
-#define OMAP54XX_VFSM_SA_ERR_MM_SHIFT                                           3
-#define OMAP54XX_VFSM_SA_ERR_MM_WIDTH                                           0x1
-#define OMAP54XX_VFSM_SA_ERR_MM_MASK                                            (1 << 3)
-
-/* Used by PRM_VC_MPU_ERRST */
-#define OMAP54XX_VFSM_SA_ERR_MPU_SHIFT                                          3
-#define OMAP54XX_VFSM_SA_ERR_MPU_WIDTH                                          0x1
-#define OMAP54XX_VFSM_SA_ERR_MPU_MASK                                           (1 << 3)
-
-/* Used by PRM_VC_CORE_ERRST */
-#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_SHIFT                                    5
-#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_WIDTH                                    0x1
-#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_MASK                                     (1 << 5)
-
-/* Used by PRM_VC_MM_ERRST */
-#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_SHIFT                                      5
-#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_WIDTH                                      0x1
-#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_MASK                                       (1 << 5)
-
-/* Used by PRM_VC_MPU_ERRST */
-#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_SHIFT                                     5
-#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_WIDTH                                     0x1
-#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_MASK                                      (1 << 5)
-
-/* Used by PRM_VC_SMPS_CORE_CONFIG */
-#define OMAP54XX_VOLRA_VDD_CORE_L_SHIFT                                         8
-#define OMAP54XX_VOLRA_VDD_CORE_L_WIDTH                                         0x8
-#define OMAP54XX_VOLRA_VDD_CORE_L_MASK                                          (0xff << 8)
-
-/* Used by PRM_VC_SMPS_MM_CONFIG */
-#define OMAP54XX_VOLRA_VDD_MM_L_SHIFT                                           8
-#define OMAP54XX_VOLRA_VDD_MM_L_WIDTH                                           0x8
-#define OMAP54XX_VOLRA_VDD_MM_L_MASK                                            (0xff << 8)
-
-/* Used by PRM_VC_SMPS_MPU_CONFIG */
-#define OMAP54XX_VOLRA_VDD_MPU_L_SHIFT                                          8
-#define OMAP54XX_VOLRA_VDD_MPU_L_WIDTH                                          0x8
-#define OMAP54XX_VOLRA_VDD_MPU_L_MASK                                           (0xff << 8)
-
-/* Used by PRM_VOLTST_MM, PRM_VOLTST_MPU */
-#define OMAP54XX_VOLTSTATEST_SHIFT                                              0
-#define OMAP54XX_VOLTSTATEST_WIDTH                                              0x2
-#define OMAP54XX_VOLTSTATEST_MASK                                               (0x3 << 0)
-
-/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP54XX_VPENABLE_SHIFT                                                 0
-#define OMAP54XX_VPENABLE_WIDTH                                                 0x1
-#define OMAP54XX_VPENABLE_MASK                                                  (1 << 0)
-
-/* Used by PRM_VP_CORE_STATUS, PRM_VP_MM_STATUS, PRM_VP_MPU_STATUS */
-#define OMAP54XX_VPINIDLE_SHIFT                                                 0
-#define OMAP54XX_VPINIDLE_WIDTH                                                 0x1
-#define OMAP54XX_VPINIDLE_MASK                                                  (1 << 0)
-
-/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */
-#define OMAP54XX_VPVOLTAGE_SHIFT                                                0
-#define OMAP54XX_VPVOLTAGE_WIDTH                                                0x8
-#define OMAP54XX_VPVOLTAGE_MASK                                                 (0xff << 0)
-
-/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
-#define OMAP54XX_VP_CORE_EQVALUE_EN_SHIFT                                       20
-#define OMAP54XX_VP_CORE_EQVALUE_EN_WIDTH                                       0x1
-#define OMAP54XX_VP_CORE_EQVALUE_EN_MASK                                        (1 << 20)
-
-/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
-#define OMAP54XX_VP_CORE_EQVALUE_ST_SHIFT                                       20
-#define OMAP54XX_VP_CORE_EQVALUE_ST_WIDTH                                       0x1
-#define OMAP54XX_VP_CORE_EQVALUE_ST_MASK                                        (1 << 20)
-
-/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
-#define OMAP54XX_VP_CORE_MAXVDD_EN_SHIFT                                        18
-#define OMAP54XX_VP_CORE_MAXVDD_EN_WIDTH                                        0x1
-#define OMAP54XX_VP_CORE_MAXVDD_EN_MASK                                         (1 << 18)
-
-/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
-#define OMAP54XX_VP_CORE_MAXVDD_ST_SHIFT                                        18
-#define OMAP54XX_VP_CORE_MAXVDD_ST_WIDTH                                        0x1
-#define OMAP54XX_VP_CORE_MAXVDD_ST_MASK                                         (1 << 18)
-
-/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
-#define OMAP54XX_VP_CORE_MINVDD_EN_SHIFT                                        17
-#define OMAP54XX_VP_CORE_MINVDD_EN_WIDTH                                        0x1
-#define OMAP54XX_VP_CORE_MINVDD_EN_MASK                                         (1 << 17)
-
-/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
-#define OMAP54XX_VP_CORE_MINVDD_ST_SHIFT                                        17
-#define OMAP54XX_VP_CORE_MINVDD_ST_WIDTH                                        0x1
-#define OMAP54XX_VP_CORE_MINVDD_ST_MASK                                         (1 << 17)
-
-/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
-#define OMAP54XX_VP_CORE_NOSMPSACK_EN_SHIFT                                     19
-#define OMAP54XX_VP_CORE_NOSMPSACK_EN_WIDTH                                     0x1
-#define OMAP54XX_VP_CORE_NOSMPSACK_EN_MASK                                      (1 << 19)
-
-/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
-#define OMAP54XX_VP_CORE_NOSMPSACK_ST_SHIFT                                     19
-#define OMAP54XX_VP_CORE_NOSMPSACK_ST_WIDTH                                     0x1
-#define OMAP54XX_VP_CORE_NOSMPSACK_ST_MASK                                      (1 << 19)
-
-/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
-#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_SHIFT                                 16
-#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_WIDTH                                 0x1
-#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_MASK                                  (1 << 16)
-
-/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
-#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_SHIFT                                 16
-#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_WIDTH                                 0x1
-#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_MASK                                  (1 << 16)
-
-/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
-#define OMAP54XX_VP_CORE_TRANXDONE_EN_SHIFT                                     21
-#define OMAP54XX_VP_CORE_TRANXDONE_EN_WIDTH                                     0x1
-#define OMAP54XX_VP_CORE_TRANXDONE_EN_MASK                                      (1 << 21)
-
-/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
-#define OMAP54XX_VP_CORE_TRANXDONE_ST_SHIFT                                     21
-#define OMAP54XX_VP_CORE_TRANXDONE_ST_WIDTH                                     0x1
-#define OMAP54XX_VP_CORE_TRANXDONE_ST_MASK                                      (1 << 21)
-
-/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
-#define OMAP54XX_VP_MM_EQVALUE_EN_SHIFT                                         28
-#define OMAP54XX_VP_MM_EQVALUE_EN_WIDTH                                         0x1
-#define OMAP54XX_VP_MM_EQVALUE_EN_MASK                                          (1 << 28)
-
-/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
-#define OMAP54XX_VP_MM_EQVALUE_ST_SHIFT                                         28
-#define OMAP54XX_VP_MM_EQVALUE_ST_WIDTH                                         0x1
-#define OMAP54XX_VP_MM_EQVALUE_ST_MASK                                          (1 << 28)
-
-/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
-#define OMAP54XX_VP_MM_MAXVDD_EN_SHIFT                                          26
-#define OMAP54XX_VP_MM_MAXVDD_EN_WIDTH                                          0x1
-#define OMAP54XX_VP_MM_MAXVDD_EN_MASK                                           (1 << 26)
-
-/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
-#define OMAP54XX_VP_MM_MAXVDD_ST_SHIFT                                          26
-#define OMAP54XX_VP_MM_MAXVDD_ST_WIDTH                                          0x1
-#define OMAP54XX_VP_MM_MAXVDD_ST_MASK                                           (1 << 26)
-
-/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
-#define OMAP54XX_VP_MM_MINVDD_EN_SHIFT                                          25
-#define OMAP54XX_VP_MM_MINVDD_EN_WIDTH                                          0x1
-#define OMAP54XX_VP_MM_MINVDD_EN_MASK                                           (1 << 25)
-
-/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
-#define OMAP54XX_VP_MM_MINVDD_ST_SHIFT                                          25
-#define OMAP54XX_VP_MM_MINVDD_ST_WIDTH                                          0x1
-#define OMAP54XX_VP_MM_MINVDD_ST_MASK                                           (1 << 25)
-
-/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
-#define OMAP54XX_VP_MM_NOSMPSACK_EN_SHIFT                                       27
-#define OMAP54XX_VP_MM_NOSMPSACK_EN_WIDTH                                       0x1
-#define OMAP54XX_VP_MM_NOSMPSACK_EN_MASK                                        (1 << 27)
-
-/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
-#define OMAP54XX_VP_MM_NOSMPSACK_ST_SHIFT                                       27
-#define OMAP54XX_VP_MM_NOSMPSACK_ST_WIDTH                                       0x1
-#define OMAP54XX_VP_MM_NOSMPSACK_ST_MASK                                        (1 << 27)
-
-/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
-#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_SHIFT                                   24
-#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_WIDTH                                   0x1
-#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_MASK                                    (1 << 24)
-
-/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
-#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_SHIFT                                   24
-#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_WIDTH                                   0x1
-#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_MASK                                    (1 << 24)
-
-/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
-#define OMAP54XX_VP_MM_TRANXDONE_EN_SHIFT                                       29
-#define OMAP54XX_VP_MM_TRANXDONE_EN_WIDTH                                       0x1
-#define OMAP54XX_VP_MM_TRANXDONE_EN_MASK                                        (1 << 29)
-
-/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
-#define OMAP54XX_VP_MM_TRANXDONE_ST_SHIFT                                       29
-#define OMAP54XX_VP_MM_TRANXDONE_ST_WIDTH                                       0x1
-#define OMAP54XX_VP_MM_TRANXDONE_ST_MASK                                        (1 << 29)
-
-/* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP54XX_VP_MPU_EQVALUE_EN_SHIFT                                        4
-#define OMAP54XX_VP_MPU_EQVALUE_EN_WIDTH                                        0x1
-#define OMAP54XX_VP_MPU_EQVALUE_EN_MASK                                         (1 << 4)
-
-/* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP54XX_VP_MPU_EQVALUE_ST_SHIFT                                        4
-#define OMAP54XX_VP_MPU_EQVALUE_ST_WIDTH                                        0x1
-#define OMAP54XX_VP_MPU_EQVALUE_ST_MASK                                         (1 << 4)
-
-/* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP54XX_VP_MPU_MAXVDD_EN_SHIFT                                         2
-#define OMAP54XX_VP_MPU_MAXVDD_EN_WIDTH                                         0x1
-#define OMAP54XX_VP_MPU_MAXVDD_EN_MASK                                          (1 << 2)
-
-/* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP54XX_VP_MPU_MAXVDD_ST_SHIFT                                         2
-#define OMAP54XX_VP_MPU_MAXVDD_ST_WIDTH                                         0x1
-#define OMAP54XX_VP_MPU_MAXVDD_ST_MASK                                          (1 << 2)
-
-/* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP54XX_VP_MPU_MINVDD_EN_SHIFT                                         1
-#define OMAP54XX_VP_MPU_MINVDD_EN_WIDTH                                         0x1
-#define OMAP54XX_VP_MPU_MINVDD_EN_MASK                                          (1 << 1)
-
-/* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP54XX_VP_MPU_MINVDD_ST_SHIFT                                         1
-#define OMAP54XX_VP_MPU_MINVDD_ST_WIDTH                                         0x1
-#define OMAP54XX_VP_MPU_MINVDD_ST_MASK                                          (1 << 1)
-
-/* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP54XX_VP_MPU_NOSMPSACK_EN_SHIFT                                      3
-#define OMAP54XX_VP_MPU_NOSMPSACK_EN_WIDTH                                      0x1
-#define OMAP54XX_VP_MPU_NOSMPSACK_EN_MASK                                       (1 << 3)
-
-/* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP54XX_VP_MPU_NOSMPSACK_ST_SHIFT                                      3
-#define OMAP54XX_VP_MPU_NOSMPSACK_ST_WIDTH                                      0x1
-#define OMAP54XX_VP_MPU_NOSMPSACK_ST_MASK                                       (1 << 3)
-
-/* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_SHIFT                                  0
-#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_WIDTH                                  0x1
-#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_MASK                                   (1 << 0)
-
-/* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_SHIFT                                  0
-#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_WIDTH                                  0x1
-#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_MASK                                   (1 << 0)
-
-/* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP54XX_VP_MPU_TRANXDONE_EN_SHIFT                                      5
-#define OMAP54XX_VP_MPU_TRANXDONE_EN_WIDTH                                      0x1
-#define OMAP54XX_VP_MPU_TRANXDONE_EN_MASK                                       (1 << 5)
-
-/* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP54XX_VP_MPU_TRANXDONE_ST_SHIFT                                      5
-#define OMAP54XX_VP_MPU_TRANXDONE_ST_WIDTH                                      0x1
-#define OMAP54XX_VP_MPU_TRANXDONE_ST_MASK                                       (1 << 5)
-
-/* Used by PRM_SRAM_COUNT */
-#define OMAP54XX_VSETUPCNT_VALUE_SHIFT                                          8
-#define OMAP54XX_VSETUPCNT_VALUE_WIDTH                                          0x8
-#define OMAP54XX_VSETUPCNT_VALUE_MASK                                           (0xff << 8)
-
-/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
-#define OMAP54XX_VSTEPMAX_SHIFT                                                 0
-#define OMAP54XX_VSTEPMAX_WIDTH                                                 0x8
-#define OMAP54XX_VSTEPMAX_MASK                                                  (0xff << 0)
-
-/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
-#define OMAP54XX_VSTEPMIN_SHIFT                                                 0
-#define OMAP54XX_VSTEPMIN_WIDTH                                                 0x8
-#define OMAP54XX_VSTEPMIN_MASK                                                  (0xff << 0)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP54XX_WKUPDEP_DISPC_DSP_SHIFT                                        2
-#define OMAP54XX_WKUPDEP_DISPC_DSP_WIDTH                                        0x1
-#define OMAP54XX_WKUPDEP_DISPC_DSP_MASK                                         (1 << 2)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP54XX_WKUPDEP_DISPC_IPU_SHIFT                                        1
-#define OMAP54XX_WKUPDEP_DISPC_IPU_WIDTH                                        0x1
-#define OMAP54XX_WKUPDEP_DISPC_IPU_MASK                                         (1 << 1)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP54XX_WKUPDEP_DISPC_MPU_SHIFT                                        0
-#define OMAP54XX_WKUPDEP_DISPC_MPU_WIDTH                                        0x1
-#define OMAP54XX_WKUPDEP_DISPC_MPU_MASK                                         (1 << 0)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP54XX_WKUPDEP_DISPC_SDMA_SHIFT                                       3
-#define OMAP54XX_WKUPDEP_DISPC_SDMA_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_DISPC_SDMA_MASK                                        (1 << 3)
-
-/* Used by PM_ABE_DMIC_WKDEP */
-#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_SHIFT                                     6
-#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_WIDTH                                     0x1
-#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_MASK                                      (1 << 6)
-
-/* Used by PM_ABE_DMIC_WKDEP */
-#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_SHIFT                                    7
-#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_WIDTH                                    0x1
-#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_MASK                                     (1 << 7)
-
-/* Used by PM_ABE_DMIC_WKDEP */
-#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_SHIFT                                     2
-#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_WIDTH                                     0x1
-#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_MASK                                      (1 << 2)
-
-/* Used by PM_ABE_DMIC_WKDEP */
-#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_SHIFT                                     0
-#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_WIDTH                                     0x1
-#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_MASK                                      (1 << 0)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP54XX_WKUPDEP_DSI1_A_DSP_SHIFT                                       6
-#define OMAP54XX_WKUPDEP_DSI1_A_DSP_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_DSI1_A_DSP_MASK                                        (1 << 6)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP54XX_WKUPDEP_DSI1_A_IPU_SHIFT                                       5
-#define OMAP54XX_WKUPDEP_DSI1_A_IPU_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_DSI1_A_IPU_MASK                                        (1 << 5)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP54XX_WKUPDEP_DSI1_A_MPU_SHIFT                                       4
-#define OMAP54XX_WKUPDEP_DSI1_A_MPU_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_DSI1_A_MPU_MASK                                        (1 << 4)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_SHIFT                                      7
-#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_WIDTH                                      0x1
-#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_MASK                                       (1 << 7)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP54XX_WKUPDEP_DSI1_B_DSP_SHIFT                                       10
-#define OMAP54XX_WKUPDEP_DSI1_B_DSP_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_DSI1_B_DSP_MASK                                        (1 << 10)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP54XX_WKUPDEP_DSI1_B_IPU_SHIFT                                       9
-#define OMAP54XX_WKUPDEP_DSI1_B_IPU_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_DSI1_B_IPU_MASK                                        (1 << 9)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP54XX_WKUPDEP_DSI1_B_MPU_SHIFT                                       8
-#define OMAP54XX_WKUPDEP_DSI1_B_MPU_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_DSI1_B_MPU_MASK                                        (1 << 8)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_SHIFT                                      11
-#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_WIDTH                                      0x1
-#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_MASK                                       (1 << 11)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP54XX_WKUPDEP_DSI1_C_DSP_SHIFT                                       17
-#define OMAP54XX_WKUPDEP_DSI1_C_DSP_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_DSI1_C_DSP_MASK                                        (1 << 17)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP54XX_WKUPDEP_DSI1_C_IPU_SHIFT                                       16
-#define OMAP54XX_WKUPDEP_DSI1_C_IPU_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_DSI1_C_IPU_MASK                                        (1 << 16)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP54XX_WKUPDEP_DSI1_C_MPU_SHIFT                                       15
-#define OMAP54XX_WKUPDEP_DSI1_C_MPU_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_DSI1_C_MPU_MASK                                        (1 << 15)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_SHIFT                                      18
-#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_WIDTH                                      0x1
-#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_MASK                                       (1 << 18)
-
-/* Used by PM_WKUPAON_GPIO1_WKDEP */
-#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_SHIFT                                   1
-#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_WIDTH                                   0x1
-#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_MASK                                    (1 << 1)
-
-/* Used by PM_WKUPAON_GPIO1_WKDEP */
-#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT                                   0
-#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_WIDTH                                   0x1
-#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_MASK                                    (1 << 0)
-
-/* Used by PM_WKUPAON_GPIO1_WKDEP */
-#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_SHIFT                                   6
-#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_WIDTH                                   0x1
-#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_MASK                                    (1 << 6)
-
-/* Used by PM_L4PER_GPIO2_WKDEP */
-#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_SHIFT                                   1
-#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_WIDTH                                   0x1
-#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_MASK                                    (1 << 1)
-
-/* Used by PM_L4PER_GPIO2_WKDEP */
-#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT                                   0
-#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_WIDTH                                   0x1
-#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_MASK                                    (1 << 0)
-
-/* Used by PM_L4PER_GPIO2_WKDEP */
-#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_SHIFT                                   6
-#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_WIDTH                                   0x1
-#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_MASK                                    (1 << 6)
-
-/* Used by PM_L4PER_GPIO3_WKDEP */
-#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT                                   0
-#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_WIDTH                                   0x1
-#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_MASK                                    (1 << 0)
-
-/* Used by PM_L4PER_GPIO3_WKDEP */
-#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_SHIFT                                   6
-#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_WIDTH                                   0x1
-#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_MASK                                    (1 << 6)
-
-/* Used by PM_L4PER_GPIO4_WKDEP */
-#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT                                   0
-#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_WIDTH                                   0x1
-#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_MASK                                    (1 << 0)
-
-/* Used by PM_L4PER_GPIO4_WKDEP */
-#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_SHIFT                                   6
-#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_WIDTH                                   0x1
-#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_MASK                                    (1 << 6)
-
-/* Used by PM_L4PER_GPIO5_WKDEP */
-#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT                                   0
-#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_WIDTH                                   0x1
-#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_MASK                                    (1 << 0)
-
-/* Used by PM_L4PER_GPIO5_WKDEP */
-#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_SHIFT                                   6
-#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_WIDTH                                   0x1
-#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_MASK                                    (1 << 6)
-
-/* Used by PM_L4PER_GPIO6_WKDEP */
-#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT                                   0
-#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_WIDTH                                   0x1
-#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_MASK                                    (1 << 0)
-
-/* Used by PM_L4PER_GPIO6_WKDEP */
-#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_SHIFT                                   6
-#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_WIDTH                                   0x1
-#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_MASK                                    (1 << 6)
-
-/* Used by PM_L4PER_GPIO7_WKDEP */
-#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_SHIFT                                   0
-#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_WIDTH                                   0x1
-#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_MASK                                    (1 << 0)
-
-/* Used by PM_L4PER_GPIO8_WKDEP */
-#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_SHIFT                                   0
-#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_WIDTH                                   0x1
-#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_MASK                                    (1 << 0)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_SHIFT                                     19
-#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_WIDTH                                     0x1
-#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_MASK                                      (1 << 19)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_SHIFT                                      14
-#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_WIDTH                                      0x1
-#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_MASK                                       (1 << 14)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_SHIFT                                      13
-#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_WIDTH                                      0x1
-#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_MASK                                       (1 << 13)
-
-/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_SHIFT                                      12
-#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_WIDTH                                      0x1
-#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_MASK                                       (1 << 12)
-
-/* Used by PM_L3INIT_HSI_WKDEP */
-#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_SHIFT                                      6
-#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_WIDTH                                      0x1
-#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_MASK                                       (1 << 6)
-
-/* Used by PM_L3INIT_HSI_WKDEP */
-#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_SHIFT                                      1
-#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_WIDTH                                      0x1
-#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_MASK                                       (1 << 1)
-
-/* Used by PM_L3INIT_HSI_WKDEP */
-#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_SHIFT                                      0
-#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_WIDTH                                      0x1
-#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_MASK                                       (1 << 0)
-
-/* Used by PM_L4PER_I2C1_WKDEP */
-#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_SHIFT                                    7
-#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_WIDTH                                    0x1
-#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_MASK                                     (1 << 7)
-
-/* Used by PM_L4PER_I2C1_WKDEP */
-#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_SHIFT                                     1
-#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_WIDTH                                     0x1
-#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_MASK                                      (1 << 1)
-
-/* Used by PM_L4PER_I2C1_WKDEP */
-#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_SHIFT                                     0
-#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_WIDTH                                     0x1
-#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_MASK                                      (1 << 0)
-
-/* Used by PM_L4PER_I2C2_WKDEP */
-#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_SHIFT                                    7
-#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_WIDTH                                    0x1
-#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_MASK                                     (1 << 7)
-
-/* Used by PM_L4PER_I2C2_WKDEP */
-#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_SHIFT                                     1
-#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_WIDTH                                     0x1
-#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_MASK                                      (1 << 1)
-
-/* Used by PM_L4PER_I2C2_WKDEP */
-#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_SHIFT                                     0
-#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_WIDTH                                     0x1
-#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_MASK                                      (1 << 0)
-
-/* Used by PM_L4PER_I2C3_WKDEP */
-#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_SHIFT                                    7
-#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_WIDTH                                    0x1
-#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_MASK                                     (1 << 7)
-
-/* Used by PM_L4PER_I2C3_WKDEP */
-#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_SHIFT                                     1
-#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_WIDTH                                     0x1
-#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_MASK                                      (1 << 1)
-
-/* Used by PM_L4PER_I2C3_WKDEP */
-#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_SHIFT                                     0
-#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_WIDTH                                     0x1
-#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_MASK                                      (1 << 0)
-
-/* Used by PM_L4PER_I2C4_WKDEP */
-#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_SHIFT                                    7
-#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_WIDTH                                    0x1
-#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_MASK                                     (1 << 7)
-
-/* Used by PM_L4PER_I2C4_WKDEP */
-#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_SHIFT                                     1
-#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_WIDTH                                     0x1
-#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_MASK                                      (1 << 1)
-
-/* Used by PM_L4PER_I2C4_WKDEP */
-#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_SHIFT                                     0
-#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_WIDTH                                     0x1
-#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_MASK                                      (1 << 0)
-
-/* Used by PM_L4PER_I2C5_WKDEP */
-#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_SHIFT                                     0
-#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_WIDTH                                     0x1
-#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_MASK                                      (1 << 0)
-
-/* Used by PM_WKUPAON_KBD_WKDEP */
-#define OMAP54XX_WKUPDEP_KBD_MPU_SHIFT                                          0
-#define OMAP54XX_WKUPDEP_KBD_MPU_WIDTH                                          0x1
-#define OMAP54XX_WKUPDEP_KBD_MPU_MASK                                           (1 << 0)
-
-/* Used by PM_ABE_MCASP_WKDEP */
-#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_SHIFT                                    6
-#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_WIDTH                                    0x1
-#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_MASK                                     (1 << 6)
-
-/* Used by PM_ABE_MCASP_WKDEP */
-#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_SHIFT                                   7
-#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_WIDTH                                   0x1
-#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_MASK                                    (1 << 7)
-
-/* Used by PM_ABE_MCASP_WKDEP */
-#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_SHIFT                                    2
-#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_WIDTH                                    0x1
-#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_MASK                                     (1 << 2)
-
-/* Used by PM_ABE_MCASP_WKDEP */
-#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_SHIFT                                    0
-#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_WIDTH                                    0x1
-#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_MASK                                     (1 << 0)
-
-/* Used by PM_ABE_MCBSP1_WKDEP */
-#define OMAP54XX_WKUPDEP_MCBSP1_DSP_SHIFT                                       2
-#define OMAP54XX_WKUPDEP_MCBSP1_DSP_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_MCBSP1_DSP_MASK                                        (1 << 2)
-
-/* Used by PM_ABE_MCBSP1_WKDEP */
-#define OMAP54XX_WKUPDEP_MCBSP1_MPU_SHIFT                                       0
-#define OMAP54XX_WKUPDEP_MCBSP1_MPU_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_MCBSP1_MPU_MASK                                        (1 << 0)
-
-/* Used by PM_ABE_MCBSP1_WKDEP */
-#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_SHIFT                                      3
-#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_WIDTH                                      0x1
-#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_MASK                                       (1 << 3)
-
-/* Used by PM_ABE_MCBSP2_WKDEP */
-#define OMAP54XX_WKUPDEP_MCBSP2_DSP_SHIFT                                       2
-#define OMAP54XX_WKUPDEP_MCBSP2_DSP_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_MCBSP2_DSP_MASK                                        (1 << 2)
-
-/* Used by PM_ABE_MCBSP2_WKDEP */
-#define OMAP54XX_WKUPDEP_MCBSP2_MPU_SHIFT                                       0
-#define OMAP54XX_WKUPDEP_MCBSP2_MPU_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_MCBSP2_MPU_MASK                                        (1 << 0)
-
-/* Used by PM_ABE_MCBSP2_WKDEP */
-#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_SHIFT                                      3
-#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_WIDTH                                      0x1
-#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_MASK                                       (1 << 3)
-
-/* Used by PM_ABE_MCBSP3_WKDEP */
-#define OMAP54XX_WKUPDEP_MCBSP3_DSP_SHIFT                                       2
-#define OMAP54XX_WKUPDEP_MCBSP3_DSP_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_MCBSP3_DSP_MASK                                        (1 << 2)
-
-/* Used by PM_ABE_MCBSP3_WKDEP */
-#define OMAP54XX_WKUPDEP_MCBSP3_MPU_SHIFT                                       0
-#define OMAP54XX_WKUPDEP_MCBSP3_MPU_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_MCBSP3_MPU_MASK                                        (1 << 0)
-
-/* Used by PM_ABE_MCBSP3_WKDEP */
-#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_SHIFT                                      3
-#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_WIDTH                                      0x1
-#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_MASK                                       (1 << 3)
-
-/* Used by PM_ABE_MCPDM_WKDEP */
-#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_SHIFT                                    6
-#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_WIDTH                                    0x1
-#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_MASK                                     (1 << 6)
-
-/* Used by PM_ABE_MCPDM_WKDEP */
-#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_SHIFT                                   7
-#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_WIDTH                                   0x1
-#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_MASK                                    (1 << 7)
-
-/* Used by PM_ABE_MCPDM_WKDEP */
-#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_SHIFT                                    2
-#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_WIDTH                                    0x1
-#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_MASK                                     (1 << 2)
-
-/* Used by PM_ABE_MCPDM_WKDEP */
-#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_SHIFT                                    0
-#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_WIDTH                                    0x1
-#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_MASK                                     (1 << 0)
-
-/* Used by PM_L4PER_MCSPI1_WKDEP */
-#define OMAP54XX_WKUPDEP_MCSPI1_DSP_SHIFT                                       2
-#define OMAP54XX_WKUPDEP_MCSPI1_DSP_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_MCSPI1_DSP_MASK                                        (1 << 2)
-
-/* Used by PM_L4PER_MCSPI1_WKDEP */
-#define OMAP54XX_WKUPDEP_MCSPI1_IPU_SHIFT                                       1
-#define OMAP54XX_WKUPDEP_MCSPI1_IPU_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_MCSPI1_IPU_MASK                                        (1 << 1)
-
-/* Used by PM_L4PER_MCSPI1_WKDEP */
-#define OMAP54XX_WKUPDEP_MCSPI1_MPU_SHIFT                                       0
-#define OMAP54XX_WKUPDEP_MCSPI1_MPU_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_MCSPI1_MPU_MASK                                        (1 << 0)
-
-/* Used by PM_L4PER_MCSPI1_WKDEP */
-#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_SHIFT                                      3
-#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_WIDTH                                      0x1
-#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_MASK                                       (1 << 3)
-
-/* Used by PM_L4PER_MCSPI2_WKDEP */
-#define OMAP54XX_WKUPDEP_MCSPI2_IPU_SHIFT                                       1
-#define OMAP54XX_WKUPDEP_MCSPI2_IPU_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_MCSPI2_IPU_MASK                                        (1 << 1)
-
-/* Used by PM_L4PER_MCSPI2_WKDEP */
-#define OMAP54XX_WKUPDEP_MCSPI2_MPU_SHIFT                                       0
-#define OMAP54XX_WKUPDEP_MCSPI2_MPU_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_MCSPI2_MPU_MASK                                        (1 << 0)
-
-/* Used by PM_L4PER_MCSPI2_WKDEP */
-#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_SHIFT                                      3
-#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_WIDTH                                      0x1
-#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_MASK                                       (1 << 3)
-
-/* Used by PM_L4PER_MCSPI3_WKDEP */
-#define OMAP54XX_WKUPDEP_MCSPI3_MPU_SHIFT                                       0
-#define OMAP54XX_WKUPDEP_MCSPI3_MPU_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_MCSPI3_MPU_MASK                                        (1 << 0)
-
-/* Used by PM_L4PER_MCSPI3_WKDEP */
-#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_SHIFT                                      3
-#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_WIDTH                                      0x1
-#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_MASK                                       (1 << 3)
-
-/* Used by PM_L4PER_MCSPI4_WKDEP */
-#define OMAP54XX_WKUPDEP_MCSPI4_MPU_SHIFT                                       0
-#define OMAP54XX_WKUPDEP_MCSPI4_MPU_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_MCSPI4_MPU_MASK                                        (1 << 0)
-
-/* Used by PM_L4PER_MCSPI4_WKDEP */
-#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_SHIFT                                      3
-#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_WIDTH                                      0x1
-#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_MASK                                       (1 << 3)
-
-/* Used by PM_L3INIT_MMC1_WKDEP */
-#define OMAP54XX_WKUPDEP_MMC1_DSP_SHIFT                                         2
-#define OMAP54XX_WKUPDEP_MMC1_DSP_WIDTH                                         0x1
-#define OMAP54XX_WKUPDEP_MMC1_DSP_MASK                                          (1 << 2)
-
-/* Used by PM_L3INIT_MMC1_WKDEP */
-#define OMAP54XX_WKUPDEP_MMC1_IPU_SHIFT                                         1
-#define OMAP54XX_WKUPDEP_MMC1_IPU_WIDTH                                         0x1
-#define OMAP54XX_WKUPDEP_MMC1_IPU_MASK                                          (1 << 1)
-
-/* Used by PM_L3INIT_MMC1_WKDEP */
-#define OMAP54XX_WKUPDEP_MMC1_MPU_SHIFT                                         0
-#define OMAP54XX_WKUPDEP_MMC1_MPU_WIDTH                                         0x1
-#define OMAP54XX_WKUPDEP_MMC1_MPU_MASK                                          (1 << 0)
-
-/* Used by PM_L3INIT_MMC1_WKDEP */
-#define OMAP54XX_WKUPDEP_MMC1_SDMA_SHIFT                                        3
-#define OMAP54XX_WKUPDEP_MMC1_SDMA_WIDTH                                        0x1
-#define OMAP54XX_WKUPDEP_MMC1_SDMA_MASK                                         (1 << 3)
-
-/* Used by PM_L3INIT_MMC2_WKDEP */
-#define OMAP54XX_WKUPDEP_MMC2_DSP_SHIFT                                         2
-#define OMAP54XX_WKUPDEP_MMC2_DSP_WIDTH                                         0x1
-#define OMAP54XX_WKUPDEP_MMC2_DSP_MASK                                          (1 << 2)
-
-/* Used by PM_L3INIT_MMC2_WKDEP */
-#define OMAP54XX_WKUPDEP_MMC2_IPU_SHIFT                                         1
-#define OMAP54XX_WKUPDEP_MMC2_IPU_WIDTH                                         0x1
-#define OMAP54XX_WKUPDEP_MMC2_IPU_MASK                                          (1 << 1)
-
-/* Used by PM_L3INIT_MMC2_WKDEP */
-#define OMAP54XX_WKUPDEP_MMC2_MPU_SHIFT                                         0
-#define OMAP54XX_WKUPDEP_MMC2_MPU_WIDTH                                         0x1
-#define OMAP54XX_WKUPDEP_MMC2_MPU_MASK                                          (1 << 0)
-
-/* Used by PM_L3INIT_MMC2_WKDEP */
-#define OMAP54XX_WKUPDEP_MMC2_SDMA_SHIFT                                        3
-#define OMAP54XX_WKUPDEP_MMC2_SDMA_WIDTH                                        0x1
-#define OMAP54XX_WKUPDEP_MMC2_SDMA_MASK                                         (1 << 3)
-
-/* Used by PM_L4PER_MMC3_WKDEP */
-#define OMAP54XX_WKUPDEP_MMC3_IPU_SHIFT                                         1
-#define OMAP54XX_WKUPDEP_MMC3_IPU_WIDTH                                         0x1
-#define OMAP54XX_WKUPDEP_MMC3_IPU_MASK                                          (1 << 1)
-
-/* Used by PM_L4PER_MMC3_WKDEP */
-#define OMAP54XX_WKUPDEP_MMC3_MPU_SHIFT                                         0
-#define OMAP54XX_WKUPDEP_MMC3_MPU_WIDTH                                         0x1
-#define OMAP54XX_WKUPDEP_MMC3_MPU_MASK                                          (1 << 0)
-
-/* Used by PM_L4PER_MMC3_WKDEP */
-#define OMAP54XX_WKUPDEP_MMC3_SDMA_SHIFT                                        3
-#define OMAP54XX_WKUPDEP_MMC3_SDMA_WIDTH                                        0x1
-#define OMAP54XX_WKUPDEP_MMC3_SDMA_MASK                                         (1 << 3)
-
-/* Used by PM_L4PER_MMC4_WKDEP */
-#define OMAP54XX_WKUPDEP_MMC4_MPU_SHIFT                                         0
-#define OMAP54XX_WKUPDEP_MMC4_MPU_WIDTH                                         0x1
-#define OMAP54XX_WKUPDEP_MMC4_MPU_MASK                                          (1 << 0)
-
-/* Used by PM_L4PER_MMC4_WKDEP */
-#define OMAP54XX_WKUPDEP_MMC4_SDMA_SHIFT                                        3
-#define OMAP54XX_WKUPDEP_MMC4_SDMA_WIDTH                                        0x1
-#define OMAP54XX_WKUPDEP_MMC4_SDMA_MASK                                         (1 << 3)
-
-/* Used by PM_L4PER_MMC5_WKDEP */
-#define OMAP54XX_WKUPDEP_MMC5_MPU_SHIFT                                         0
-#define OMAP54XX_WKUPDEP_MMC5_MPU_WIDTH                                         0x1
-#define OMAP54XX_WKUPDEP_MMC5_MPU_MASK                                          (1 << 0)
-
-/* Used by PM_L4PER_MMC5_WKDEP */
-#define OMAP54XX_WKUPDEP_MMC5_SDMA_SHIFT                                        3
-#define OMAP54XX_WKUPDEP_MMC5_SDMA_WIDTH                                        0x1
-#define OMAP54XX_WKUPDEP_MMC5_SDMA_MASK                                         (1 << 3)
-
-/* Used by PM_L3INIT_SATA_WKDEP */
-#define OMAP54XX_WKUPDEP_SATA_MPU_SHIFT                                         0
-#define OMAP54XX_WKUPDEP_SATA_MPU_WIDTH                                         0x1
-#define OMAP54XX_WKUPDEP_SATA_MPU_MASK                                          (1 << 0)
-
-/* Used by PM_ABE_SLIMBUS1_WKDEP */
-#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_SHIFT                                 6
-#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_WIDTH                                 0x1
-#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_MASK                                  (1 << 6)
-
-/* Used by PM_ABE_SLIMBUS1_WKDEP */
-#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT                                7
-#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_WIDTH                                0x1
-#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK                                 (1 << 7)
-
-/* Used by PM_ABE_SLIMBUS1_WKDEP */
-#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_SHIFT                                 2
-#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_WIDTH                                 0x1
-#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_MASK                                  (1 << 2)
-
-/* Used by PM_ABE_SLIMBUS1_WKDEP */
-#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT                                 0
-#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_WIDTH                                 0x1
-#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK                                  (1 << 0)
-
-/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
-#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_SHIFT                             1
-#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_WIDTH                             0x1
-#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_MASK                              (1 << 1)
-
-/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
-#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_SHIFT                             0
-#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_WIDTH                             0x1
-#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_MASK                              (1 << 0)
-
-/* Used by PM_COREAON_SMARTREFLEX_MM_WKDEP */
-#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_SHIFT                               0
-#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_WIDTH                               0x1
-#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_MASK                                (1 << 0)
-
-/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
-#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_SHIFT                              0
-#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_WIDTH                              0x1
-#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_MASK                               (1 << 0)
-
-/* Used by PM_L4PER_TIMER10_WKDEP */
-#define OMAP54XX_WKUPDEP_TIMER10_MPU_SHIFT                                      0
-#define OMAP54XX_WKUPDEP_TIMER10_MPU_WIDTH                                      0x1
-#define OMAP54XX_WKUPDEP_TIMER10_MPU_MASK                                       (1 << 0)
-
-/* Used by PM_L4PER_TIMER11_WKDEP */
-#define OMAP54XX_WKUPDEP_TIMER11_IPU_SHIFT                                      1
-#define OMAP54XX_WKUPDEP_TIMER11_IPU_WIDTH                                      0x1
-#define OMAP54XX_WKUPDEP_TIMER11_IPU_MASK                                       (1 << 1)
-
-/* Used by PM_L4PER_TIMER11_WKDEP */
-#define OMAP54XX_WKUPDEP_TIMER11_MPU_SHIFT                                      0
-#define OMAP54XX_WKUPDEP_TIMER11_MPU_WIDTH                                      0x1
-#define OMAP54XX_WKUPDEP_TIMER11_MPU_MASK                                       (1 << 0)
-
-/* Used by PM_WKUPAON_TIMER12_WKDEP */
-#define OMAP54XX_WKUPDEP_TIMER12_MPU_SHIFT                                      0
-#define OMAP54XX_WKUPDEP_TIMER12_MPU_WIDTH                                      0x1
-#define OMAP54XX_WKUPDEP_TIMER12_MPU_MASK                                       (1 << 0)
-
-/* Used by PM_WKUPAON_TIMER1_WKDEP */
-#define OMAP54XX_WKUPDEP_TIMER1_MPU_SHIFT                                       0
-#define OMAP54XX_WKUPDEP_TIMER1_MPU_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_TIMER1_MPU_MASK                                        (1 << 0)
-
-/* Used by PM_L4PER_TIMER2_WKDEP */
-#define OMAP54XX_WKUPDEP_TIMER2_MPU_SHIFT                                       0
-#define OMAP54XX_WKUPDEP_TIMER2_MPU_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_TIMER2_MPU_MASK                                        (1 << 0)
-
-/* Used by PM_L4PER_TIMER3_WKDEP */
-#define OMAP54XX_WKUPDEP_TIMER3_IPU_SHIFT                                       1
-#define OMAP54XX_WKUPDEP_TIMER3_IPU_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_TIMER3_IPU_MASK                                        (1 << 1)
-
-/* Used by PM_L4PER_TIMER3_WKDEP */
-#define OMAP54XX_WKUPDEP_TIMER3_MPU_SHIFT                                       0
-#define OMAP54XX_WKUPDEP_TIMER3_MPU_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_TIMER3_MPU_MASK                                        (1 << 0)
-
-/* Used by PM_L4PER_TIMER4_WKDEP */
-#define OMAP54XX_WKUPDEP_TIMER4_IPU_SHIFT                                       1
-#define OMAP54XX_WKUPDEP_TIMER4_IPU_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_TIMER4_IPU_MASK                                        (1 << 1)
-
-/* Used by PM_L4PER_TIMER4_WKDEP */
-#define OMAP54XX_WKUPDEP_TIMER4_MPU_SHIFT                                       0
-#define OMAP54XX_WKUPDEP_TIMER4_MPU_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_TIMER4_MPU_MASK                                        (1 << 0)
-
-/* Used by PM_ABE_TIMER5_WKDEP */
-#define OMAP54XX_WKUPDEP_TIMER5_DSP_SHIFT                                       2
-#define OMAP54XX_WKUPDEP_TIMER5_DSP_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_TIMER5_DSP_MASK                                        (1 << 2)
-
-/* Used by PM_ABE_TIMER5_WKDEP */
-#define OMAP54XX_WKUPDEP_TIMER5_MPU_SHIFT                                       0
-#define OMAP54XX_WKUPDEP_TIMER5_MPU_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_TIMER5_MPU_MASK                                        (1 << 0)
-
-/* Used by PM_ABE_TIMER6_WKDEP */
-#define OMAP54XX_WKUPDEP_TIMER6_DSP_SHIFT                                       2
-#define OMAP54XX_WKUPDEP_TIMER6_DSP_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_TIMER6_DSP_MASK                                        (1 << 2)
-
-/* Used by PM_ABE_TIMER6_WKDEP */
-#define OMAP54XX_WKUPDEP_TIMER6_MPU_SHIFT                                       0
-#define OMAP54XX_WKUPDEP_TIMER6_MPU_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_TIMER6_MPU_MASK                                        (1 << 0)
-
-/* Used by PM_ABE_TIMER7_WKDEP */
-#define OMAP54XX_WKUPDEP_TIMER7_DSP_SHIFT                                       2
-#define OMAP54XX_WKUPDEP_TIMER7_DSP_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_TIMER7_DSP_MASK                                        (1 << 2)
-
-/* Used by PM_ABE_TIMER7_WKDEP */
-#define OMAP54XX_WKUPDEP_TIMER7_MPU_SHIFT                                       0
-#define OMAP54XX_WKUPDEP_TIMER7_MPU_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_TIMER7_MPU_MASK                                        (1 << 0)
-
-/* Used by PM_ABE_TIMER8_WKDEP */
-#define OMAP54XX_WKUPDEP_TIMER8_DSP_SHIFT                                       2
-#define OMAP54XX_WKUPDEP_TIMER8_DSP_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_TIMER8_DSP_MASK                                        (1 << 2)
-
-/* Used by PM_ABE_TIMER8_WKDEP */
-#define OMAP54XX_WKUPDEP_TIMER8_MPU_SHIFT                                       0
-#define OMAP54XX_WKUPDEP_TIMER8_MPU_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_TIMER8_MPU_MASK                                        (1 << 0)
-
-/* Used by PM_L4PER_TIMER9_WKDEP */
-#define OMAP54XX_WKUPDEP_TIMER9_IPU_SHIFT                                       1
-#define OMAP54XX_WKUPDEP_TIMER9_IPU_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_TIMER9_IPU_MASK                                        (1 << 1)
-
-/* Used by PM_L4PER_TIMER9_WKDEP */
-#define OMAP54XX_WKUPDEP_TIMER9_MPU_SHIFT                                       0
-#define OMAP54XX_WKUPDEP_TIMER9_MPU_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_TIMER9_MPU_MASK                                        (1 << 0)
-
-/* Used by PM_L4PER_UART1_WKDEP */
-#define OMAP54XX_WKUPDEP_UART1_MPU_SHIFT                                        0
-#define OMAP54XX_WKUPDEP_UART1_MPU_WIDTH                                        0x1
-#define OMAP54XX_WKUPDEP_UART1_MPU_MASK                                         (1 << 0)
-
-/* Used by PM_L4PER_UART1_WKDEP */
-#define OMAP54XX_WKUPDEP_UART1_SDMA_SHIFT                                       3
-#define OMAP54XX_WKUPDEP_UART1_SDMA_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_UART1_SDMA_MASK                                        (1 << 3)
-
-/* Used by PM_L4PER_UART2_WKDEP */
-#define OMAP54XX_WKUPDEP_UART2_MPU_SHIFT                                        0
-#define OMAP54XX_WKUPDEP_UART2_MPU_WIDTH                                        0x1
-#define OMAP54XX_WKUPDEP_UART2_MPU_MASK                                         (1 << 0)
-
-/* Used by PM_L4PER_UART2_WKDEP */
-#define OMAP54XX_WKUPDEP_UART2_SDMA_SHIFT                                       3
-#define OMAP54XX_WKUPDEP_UART2_SDMA_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_UART2_SDMA_MASK                                        (1 << 3)
-
-/* Used by PM_L4PER_UART3_WKDEP */
-#define OMAP54XX_WKUPDEP_UART3_DSP_SHIFT                                        2
-#define OMAP54XX_WKUPDEP_UART3_DSP_WIDTH                                        0x1
-#define OMAP54XX_WKUPDEP_UART3_DSP_MASK                                         (1 << 2)
-
-/* Used by PM_L4PER_UART3_WKDEP */
-#define OMAP54XX_WKUPDEP_UART3_IPU_SHIFT                                        1
-#define OMAP54XX_WKUPDEP_UART3_IPU_WIDTH                                        0x1
-#define OMAP54XX_WKUPDEP_UART3_IPU_MASK                                         (1 << 1)
-
-/* Used by PM_L4PER_UART3_WKDEP */
-#define OMAP54XX_WKUPDEP_UART3_MPU_SHIFT                                        0
-#define OMAP54XX_WKUPDEP_UART3_MPU_WIDTH                                        0x1
-#define OMAP54XX_WKUPDEP_UART3_MPU_MASK                                         (1 << 0)
-
-/* Used by PM_L4PER_UART3_WKDEP */
-#define OMAP54XX_WKUPDEP_UART3_SDMA_SHIFT                                       3
-#define OMAP54XX_WKUPDEP_UART3_SDMA_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_UART3_SDMA_MASK                                        (1 << 3)
-
-/* Used by PM_L4PER_UART4_WKDEP */
-#define OMAP54XX_WKUPDEP_UART4_MPU_SHIFT                                        0
-#define OMAP54XX_WKUPDEP_UART4_MPU_WIDTH                                        0x1
-#define OMAP54XX_WKUPDEP_UART4_MPU_MASK                                         (1 << 0)
-
-/* Used by PM_L4PER_UART4_WKDEP */
-#define OMAP54XX_WKUPDEP_UART4_SDMA_SHIFT                                       3
-#define OMAP54XX_WKUPDEP_UART4_SDMA_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_UART4_SDMA_MASK                                        (1 << 3)
-
-/* Used by PM_L4PER_UART5_WKDEP */
-#define OMAP54XX_WKUPDEP_UART5_MPU_SHIFT                                        0
-#define OMAP54XX_WKUPDEP_UART5_MPU_WIDTH                                        0x1
-#define OMAP54XX_WKUPDEP_UART5_MPU_MASK                                         (1 << 0)
-
-/* Used by PM_L4PER_UART5_WKDEP */
-#define OMAP54XX_WKUPDEP_UART5_SDMA_SHIFT                                       3
-#define OMAP54XX_WKUPDEP_UART5_SDMA_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_UART5_SDMA_MASK                                        (1 << 3)
-
-/* Used by PM_L4PER_UART6_WKDEP */
-#define OMAP54XX_WKUPDEP_UART6_MPU_SHIFT                                        0
-#define OMAP54XX_WKUPDEP_UART6_MPU_WIDTH                                        0x1
-#define OMAP54XX_WKUPDEP_UART6_MPU_MASK                                         (1 << 0)
-
-/* Used by PM_L4PER_UART6_WKDEP */
-#define OMAP54XX_WKUPDEP_UART6_SDMA_SHIFT                                       3
-#define OMAP54XX_WKUPDEP_UART6_SDMA_WIDTH                                       0x1
-#define OMAP54XX_WKUPDEP_UART6_SDMA_MASK                                        (1 << 3)
-
-/* Used by PM_L3INIT_UNIPRO2_WKDEP */
-#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_SHIFT                                      0
-#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_WIDTH                                      0x1
-#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_MASK                                       (1 << 0)
-
-/* Used by PM_L3INIT_USB_HOST_HS_WKDEP */
-#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_SHIFT                                  1
-#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_WIDTH                                  0x1
-#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_MASK                                   (1 << 1)
-
-/* Used by PM_L3INIT_USB_HOST_HS_WKDEP */
-#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_SHIFT                                  0
-#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_WIDTH                                  0x1
-#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_MASK                                   (1 << 0)
-
-/* Used by PM_L3INIT_USB_OTG_SS_WKDEP */
-#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_SHIFT                                   1
-#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_WIDTH                                   0x1
-#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_MASK                                    (1 << 1)
-
-/* Used by PM_L3INIT_USB_OTG_SS_WKDEP */
-#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_SHIFT                                   0
-#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_WIDTH                                   0x1
-#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_MASK                                    (1 << 0)
-
-/* Used by PM_L3INIT_USB_TLL_HS_WKDEP */
-#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_SHIFT                                   1
-#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_WIDTH                                   0x1
-#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_MASK                                    (1 << 1)
-
-/* Used by PM_L3INIT_USB_TLL_HS_WKDEP */
-#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_SHIFT                                   0
-#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_WIDTH                                   0x1
-#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_MASK                                    (1 << 0)
-
-/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
-#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_SHIFT                                    0
-#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_WIDTH                                    0x1
-#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_MASK                                     (1 << 0)
-
-/* Used by PM_ABE_WD_TIMER3_WKDEP */
-#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_SHIFT                                    0
-#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_WIDTH                                    0x1
-#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_MASK                                     (1 << 0)
-
-/* Used by PRM_IO_PMCTRL */
-#define OMAP54XX_WUCLK_CTRL_SHIFT                                               8
-#define OMAP54XX_WUCLK_CTRL_WIDTH                                               0x1
-#define OMAP54XX_WUCLK_CTRL_MASK                                                (1 << 8)
-
-/* Used by PRM_IO_PMCTRL */
-#define OMAP54XX_WUCLK_STATUS_SHIFT                                             9
-#define OMAP54XX_WUCLK_STATUS_WIDTH                                             0x1
-#define OMAP54XX_WUCLK_STATUS_MASK                                              (1 << 9)
-
-/* Used by REVISION_PRM */
-#define OMAP54XX_X_MAJOR_SHIFT                                                  8
-#define OMAP54XX_X_MAJOR_WIDTH                                                  0x3
-#define OMAP54XX_X_MAJOR_MASK                                                   (0x7 << 8)
-
-/* Used by REVISION_PRM */
-#define OMAP54XX_Y_MINOR_SHIFT                                                  0
-#define OMAP54XX_Y_MINOR_WIDTH                                                  0x6
-#define OMAP54XX_Y_MINOR_MASK                                                   (0x3f << 0)
-#endif
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 9265e031fa2f..801287ee4d98 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -600,7 +600,7 @@ static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon",
 #endif
 
 #ifdef CONFIG_ARCH_OMAP4
-#ifdef CONFIG_LOCAL_TIMERS
+#ifdef CONFIG_HAVE_ARM_TWD
 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29);
 void __init omap4_local_timer_init(void)
 {
@@ -619,12 +619,12 @@ void __init omap4_local_timer_init(void)
                         pr_err("twd_local_timer_register failed %d\n", err);
         }
 }
-#else /* CONFIG_LOCAL_TIMERS */
+#else
 void __init omap4_local_timer_init(void)
 {
         omap4_sync32k_timer_init();
 }
-#endif /* CONFIG_LOCAL_TIMERS */
+#endif /* CONFIG_HAVE_ARM_TWD */
 #endif /* CONFIG_ARCH_OMAP4 */
 
 #ifdef CONFIG_SOC_OMAP5
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index 8091aac89edf..f9423493ed36 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -29,7 +29,7 @@
 #include <linux/pwm_backlight.h>
 
 #include <linux/i2c.h>
-#include <linux/i2c/pca953x.h>
+#include <linux/platform_data/pca953x.h>
 #include <linux/i2c/pxa-i2c.h>
 
 #include <linux/mfd/da903x.h>
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 3a3362fa793e..8eb4e23c561d 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -30,7 +30,7 @@
 #include <linux/power_supply.h>
 #include <linux/apm-emulation.h>
 #include <linux/i2c.h>
-#include <linux/i2c/pca953x.h>
+#include <linux/platform_data/pca953x.h>
 #include <linux/i2c/pxa-i2c.h>
 #include <linux/regulator/userspace-consumer.h>
 
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index 13e5b00eae90..3133ba82c508 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -408,7 +408,7 @@ struct pxacamera_platform_data pcm990_pxacamera_platform_data = {
         .mclk_10khz = 1000,
 };
 
-#include <linux/i2c/pca953x.h>
+#include <linux/platform_data/pca953x.h>
 
 static struct pca953x_platform_data pca9536_data = {
         .gpio_base      = PXA_NR_BUILTIN_GPIO,
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 4c29173026e8..0b11c1af51c4 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -20,7 +20,7 @@
 #include <linux/leds.h>
 #include <linux/i2c.h>
 #include <linux/i2c/pxa-i2c.h>
-#include <linux/i2c/pca953x.h>
+#include <linux/platform_data/pca953x.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 #include <linux/spi/corgi_lcd.h>
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index 04a0aea23873..b19d1c361cab 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -26,7 +26,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/i2c.h>
 #include <linux/i2c/pxa-i2c.h>
-#include <linux/i2c/pca953x.h>
+#include <linux/platform_data/pca953x.h>
 #include <linux/apm-emulation.h>
 #include <linux/can/platform/mcp251x.h>
 #include <linux/regulator/fixed.h>
diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c
index 86e59c043de2..869bce7c3f24 100644
--- a/arch/arm/mach-pxa/zylonite_pxa300.c
+++ b/arch/arm/mach-pxa/zylonite_pxa300.c
@@ -18,7 +18,7 @@
 #include <linux/init.h>
 #include <linux/i2c.h>
 #include <linux/i2c/pxa-i2c.h>
-#include <linux/i2c/pca953x.h>
+#include <linux/platform_data/pca953x.h>
 #include <linux/gpio.h>
 
 #include <mach/pxa300.h>
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index d210c0f9c2c4..9db2029aa632 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -13,7 +13,7 @@ config REALVIEW_EB_A9MP
         depends on MACH_REALVIEW_EB
         select CPU_V7
         select HAVE_ARM_SCU if SMP
-        select HAVE_ARM_TWD if LOCAL_TIMERS
+        select HAVE_ARM_TWD if SMP
         select HAVE_SMP
         select MIGHT_HAVE_CACHE_L2X0
         help
@@ -26,7 +26,7 @@ config REALVIEW_EB_ARM11MP
         select ARCH_HAS_BARRIERS if SMP
         select CPU_V6K
         select HAVE_ARM_SCU if SMP
-        select HAVE_ARM_TWD if LOCAL_TIMERS
+        select HAVE_ARM_TWD if SMP
         select HAVE_SMP
         select MIGHT_HAVE_CACHE_L2X0
         help
@@ -48,7 +48,7 @@ config MACH_REALVIEW_PB11MP
         select ARM_GIC
         select CPU_V6K
         select HAVE_ARM_SCU if SMP
-        select HAVE_ARM_TWD if LOCAL_TIMERS
+        select HAVE_ARM_TWD if SMP
         select HAVE_PATA_PLATFORM
         select HAVE_SMP
         select MIGHT_HAVE_CACHE_L2X0
@@ -92,7 +92,7 @@ config MACH_REALVIEW_PBX
         select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET
         select ARM_GIC
         select HAVE_ARM_SCU if SMP
-        select HAVE_ARM_TWD if LOCAL_TIMERS
+        select HAVE_ARM_TWD if SMP
         select HAVE_PATA_PLATFORM
         select HAVE_SMP
         select MIGHT_HAVE_CACHE_L2X0
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 7791ac76f945..dba2173e70f3 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -30,7 +30,6 @@ config CPU_S3C2410
         select S3C2410_CLOCK
         select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ
         select S3C2410_PM if PM
-        select SAMSUNG_HRT
         select SAMSUNG_WDT_RESET
         help
           Support for S3C2410 and S3C2410A family from the S3C24XX line
@@ -42,7 +41,6 @@ config CPU_S3C2412
         select CPU_LLSERIAL_S3C2440
         select S3C2412_DMA if S3C24XX_DMA
         select S3C2412_PM if PM
-        select SAMSUNG_HRT
         help
           Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
 
@@ -54,7 +52,6 @@ config CPU_S3C2416
         select S3C2443_COMMON
         select S3C2443_DMA if S3C24XX_DMA
         select SAMSUNG_CLKSRC
-        select SAMSUNG_HRT
         help
           Support for the S3C2416 SoC from the S3C24XX line
 
@@ -65,7 +62,6 @@ config CPU_S3C2440
         select S3C2410_CLOCK
         select S3C2410_PM if PM
         select S3C2440_DMA if S3C24XX_DMA
-        select SAMSUNG_HRT
         help
           Support for S3C2440 Samsung Mobile CPU based systems.
 
@@ -75,7 +71,6 @@ config CPU_S3C2442
         select CPU_LLSERIAL_S3C2440
         select S3C2410_CLOCK
         select S3C2410_PM if PM
-        select SAMSUNG_HRT
         help
           Support for S3C2442 Samsung Mobile CPU based systems.
 
@@ -91,7 +86,6 @@ config CPU_S3C2443
         select S3C2443_COMMON
         select S3C2443_DMA if S3C24XX_DMA
         select SAMSUNG_CLKSRC
-        select SAMSUNG_HRT
         help
           Support for the S3C2443 SoC from the S3C24XX line
 
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2410.c b/arch/arm/mach-s3c24xx/clock-s3c2410.c
index 564553694b54..d39d3c787580 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2410.c
@@ -281,6 +281,5 @@ int __init s3c2410_baseclk_add(void)
                (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
                (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
 
-        s3c_pwmclk_init();
         return 0;
 }
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2412.c b/arch/arm/mach-s3c24xx/clock-s3c2412.c
index 2cc017da88fe..d8f253f2b486 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2412.c
@@ -757,6 +757,5 @@ int __init s3c2412_baseclk_add(void)
         }
 
         clkdev_add_table(s3c2412_clk_lookup, ARRAY_SIZE(s3c2412_clk_lookup));
-        s3c_pwmclk_init();
         return 0;
 }
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c
index 036056cea57c..d421a72920a5 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2416.c
@@ -168,6 +168,4 @@ void __init s3c2416_init_clocks(int xtal)
         s3c24xx_register_clock(&hsmmc0_clk);
         clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup));
 
-        s3c_pwmclk_init();
-
 }
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c
index 0a53051b0787..76cd31f7804e 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c
@@ -209,6 +209,4 @@ void __init s3c2443_init_clocks(int xtal)
         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
         clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup));
-
-        s3c_pwmclk_init();
 }
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index c157103ed8eb..457261c98433 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -27,6 +27,7 @@
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/serial_core.h>
+#include <clocksource/samsung_pwm.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/io.h>
@@ -49,6 +50,7 @@
 #include <plat/clock.h>
 #include <plat/cpu-freq.h>
 #include <plat/pll.h>
+#include <plat/pwm-core.h>
 
 #include "common.h"
 
@@ -216,6 +218,13 @@ static void s3c24xx_default_idle(void)
                      S3C2410_CLKCON);
 }
 
+static struct samsung_pwm_variant s3c24xx_pwm_variant = {
+        .bits           = 16,
+        .div_base       = 1,
+        .has_tint_cstat = false,
+        .tclk_mask      = (1 << 4),
+};
+
 void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
 {
         arm_pm_idle = s3c24xx_default_idle;
@@ -232,6 +241,24 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
         s3c24xx_init_cpu();
 
         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
+
+        samsung_pwm_set_platdata(&s3c24xx_pwm_variant);
+}
+
+void __init samsung_set_timer_source(unsigned int event, unsigned int source)
+{
+        s3c24xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
+        s3c24xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
+}
+
+void __init samsung_timer_init(void)
+{
+        unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
+                IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2, IRQ_TIMER3, IRQ_TIMER4,
+        };
+
+        samsung_pwm_clocksource_init(S3C_VA_TIMER,
+                                        timer_irqs, &s3c24xx_pwm_variant);
 }
 
 /* Serial port registrations */
diff --git a/arch/arm/mach-s3c24xx/include/mach/map.h b/arch/arm/mach-s3c24xx/include/mach/map.h
index 8ba381f2dbe1..444793f0f5f1 100644
--- a/arch/arm/mach-s3c24xx/include/mach/map.h
+++ b/arch/arm/mach-s3c24xx/include/mach/map.h
@@ -167,4 +167,6 @@
 #define S3C_PA_SPI0             S3C2443_PA_SPI0
 #define S3C_PA_SPI1             S3C2443_PA_SPI1
 
+#define SAMSUNG_PA_TIMER        S3C2410_PA_TIMER
+
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index af4334d6b4d5..74dd47988b41 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -512,7 +512,7 @@ static struct platform_pwm_backlight_data backlight_data = {
 static struct platform_device h1940_backlight = {
         .name = "pwm-backlight",
         .dev  = {
-                .parent = &s3c_device_timer[0].dev,
+                .parent = &samsung_device_pwm.dev,
                 .platform_data = &backlight_data,
         },
         .id   = -1,
@@ -632,7 +632,7 @@ static struct platform_device *h1940_devices[] __initdata = {
         &h1940_device_bluetooth,
         &s3c_device_sdi,
         &s3c_device_rtc,
-        &s3c_device_timer[0],
+        &samsung_device_pwm,
         &h1940_backlight,
         &h1940_lcd_powerdev,
         &s3c_device_adc,
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index 44ca018e1f96..206b1f7546d1 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -530,7 +530,7 @@ static struct platform_pwm_backlight_data rx1950_backlight_data = {
 static struct platform_device rx1950_backlight = {
         .name = "pwm-backlight",
         .dev = {
-                .parent = &s3c_device_timer[0].dev,
+                .parent = &samsung_device_pwm.dev,
                 .platform_data = &rx1950_backlight_data,
         },
 };
@@ -717,8 +717,7 @@ static struct platform_device *rx1950_devices[] __initdata = {
         &s3c_device_sdi,
         &s3c_device_adc,
         &s3c_device_ts,
-        &s3c_device_timer[0],
-        &s3c_device_timer[1],
+        &samsung_device_pwm,
         &rx1950_backlight,
         &rx1950_device_gpiokeys,
         &power_supply,
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 20578536aec7..041da5172423 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -17,13 +17,11 @@ config PLAT_S3C64XX
 # Configuration options for the S3C6410 CPU
 
 config CPU_S3C6400
-        select SAMSUNG_HRT
         bool
         help
           Enable S3C6400 CPU support
 
 config CPU_S3C6410
-        select SAMSUNG_HRT
         bool
         help
           Enable S3C6410 CPU support
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 8499415be9cd..c1bcc4a6d3a8 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -1004,6 +1004,4 @@ void __init s3c64xx_register_clocks(unsigned long xtal,
         for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
                 s3c_register_clksrc(clksrc_cdev[cnt], 1);
         clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup));
-
-        s3c_pwmclk_init();
 }
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index 3f62e467b129..73d79cf5e141 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -27,6 +27,7 @@
 #include <linux/irq.h>
 #include <linux/gpio.h>
 #include <linux/irqchip/arm-vic.h>
+#include <clocksource/samsung_pwm.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -42,7 +43,7 @@
 #include <plat/pm.h>
 #include <plat/gpio-cfg.h>
 #include <plat/irq-uart.h>
-#include <plat/irq-vic-timer.h>
+#include <plat/pwm-core.h>
 #include <plat/regs-irqtype.h>
 #include <plat/regs-serial.h>
 #include <plat/watchdog-reset.h>
@@ -149,6 +150,30 @@ static struct device s3c64xx_dev = {
         .bus    = &s3c64xx_subsys,
 };
 
+static struct samsung_pwm_variant s3c64xx_pwm_variant = {
+        .bits           = 32,
+        .div_base       = 0,
+        .has_tint_cstat = true,
+        .tclk_mask      = (1 << 7) | (1 << 6) | (1 << 5),
+};
+
+void __init samsung_set_timer_source(unsigned int event, unsigned int source)
+{
+        s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
+        s3c64xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
+}
+
+void __init samsung_timer_init(void)
+{
+        unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
+                IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
+                IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
+        };
+
+        samsung_pwm_clocksource_init(S3C_VA_TIMER,
+                                        timer_irqs, &s3c64xx_pwm_variant);
+}
+
 /* read cpu identification code */
 
 void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
@@ -161,6 +186,8 @@ void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
         s3c64xx_init_cpu();
 
         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
+
+        samsung_pwm_set_platdata(&s3c64xx_pwm_variant);
 }
 
 static __init int s3c64xx_dev_init(void)
@@ -195,9 +222,6 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
         /* initialise the pair of VICs */
         vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
         vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
-
-        /* add the timer sub-irqs */
-        s3c_init_vic_timer_irq(5, IRQ_TIMER0);
 }
 
 #define eint_offset(irq)        ((irq) - IRQ_EINT(0))
diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h
index 96d60e0d9372..67bbd1dd04c2 100644
--- a/arch/arm/mach-s3c64xx/include/mach/irqs.h
+++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h
@@ -107,14 +107,6 @@
 #define IRQ_TC                  IRQ_PENDN
 #define IRQ_ADC                 S3C64XX_IRQ_VIC1(31)
 
-#define S3C64XX_TIMER_IRQ(x)    S3C_IRQ(64 + (x))
-
-#define IRQ_TIMER0              S3C64XX_TIMER_IRQ(0)
-#define IRQ_TIMER1              S3C64XX_TIMER_IRQ(1)
-#define IRQ_TIMER2              S3C64XX_TIMER_IRQ(2)
-#define IRQ_TIMER3              S3C64XX_TIMER_IRQ(3)
-#define IRQ_TIMER4              S3C64XX_TIMER_IRQ(4)
-
 /* compatibility for device defines */
 
 #define IRQ_IIC1                IRQ_S3C6410_IIC1
diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h
index 8e2097bb208a..f55ccb1ce893 100644
--- a/arch/arm/mach-s3c64xx/include/mach/map.h
+++ b/arch/arm/mach-s3c64xx/include/mach/map.h
@@ -121,5 +121,6 @@
 #define SAMSUNG_PA_ADC          S3C64XX_PA_ADC
 #define SAMSUNG_PA_CFCON        S3C64XX_PA_CFCON
 #define SAMSUNG_PA_KEYPAD       S3C64XX_PA_KEYPAD
+#define SAMSUNG_PA_TIMER        S3C64XX_PA_TIMER
 
 #endif /* __ASM_ARCH_6400_MAP_H */
diff --git a/arch/arm/mach-s3c64xx/irq-pm.c b/arch/arm/mach-s3c64xx/irq-pm.c
index 0c7e1d960ca4..c3da1b68d03e 100644
--- a/arch/arm/mach-s3c64xx/irq-pm.c
+++ b/arch/arm/mach-s3c64xx/irq-pm.c
@@ -22,7 +22,6 @@
 #include <mach/map.h>
 
 #include <plat/regs-serial.h>
-#include <plat/regs-timer.h>
 #include <mach/regs-gpio.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
@@ -43,7 +42,6 @@ static struct sleep_save irq_save[] = {
         SAVE_ITEM(S3C64XX_EINT0FLTCON2),
         SAVE_ITEM(S3C64XX_EINT0FLTCON3),
         SAVE_ITEM(S3C64XX_EINT0MASK),
-        SAVE_ITEM(S3C64XX_TINT_CSTAT),
 };
 
 static struct irq_grp_save {
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 8ad88ace795a..eb8e5a1aca42 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -30,7 +30,7 @@
 #include <linux/basic_mmio_gpio.h>
 #include <linux/spi/spi.h>
 
-#include <linux/i2c/pca953x.h>
+#include <linux/platform_data/pca953x.h>
 #include <linux/platform_data/s3c-hsotg.h>
 
 #include <video/platform_lcd.h>
@@ -120,7 +120,7 @@ static struct platform_device crag6410_backlight_device = {
         .name           = "pwm-backlight",
         .id             = -1,
         .dev            = {
-                .parent = &s3c_device_timer[0].dev,
+                .parent = &samsung_device_pwm.dev,
                 .platform_data = &crag6410_backlight_data,
         },
 };
@@ -375,7 +375,7 @@ static struct platform_device *crag6410_devices[] __initdata = {
         &s3c_device_fb,
         &s3c_device_ohci,
         &s3c_device_usb_hsotg,
-        &s3c_device_timer[0],
+        &samsung_device_pwm,
         &s3c64xx_device_iis0,
         &s3c64xx_device_iis1,
         &samsung_device_keypad,
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index 5b7f357d8c22..f39569e0f2e6 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -123,7 +123,7 @@ static struct platform_pwm_backlight_data hmt_backlight_data = {
 static struct platform_device hmt_backlight_device = {
         .name           = "pwm-backlight",
         .dev            = {
-                .parent = &s3c_device_timer[1].dev,
+                .parent = &samsung_device_pwm.dev,
                 .platform_data = &hmt_backlight_data,
         },
 };
@@ -239,7 +239,7 @@ static struct platform_device *hmt_devices[] __initdata = {
         &s3c_device_nand,
         &s3c_device_fb,
         &s3c_device_ohci,
-        &s3c_device_timer[1],
+        &samsung_device_pwm,
         &hmt_backlight_device,
         &hmt_leds_device,
 };
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index 58ac99041274..86d980b448fd 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -157,7 +157,7 @@ static struct platform_pwm_backlight_data smartq_backlight_data = {
 static struct platform_device smartq_backlight_device = {
         .name           = "pwm-backlight",
         .dev            = {
-                .parent = &s3c_device_timer[1].dev,
+                .parent = &samsung_device_pwm.dev,
                 .platform_data = &smartq_backlight_data,
         },
 };
@@ -246,7 +246,7 @@ static struct platform_device *smartq_devices[] __initdata = {
         &s3c_device_i2c0,
         &s3c_device_ohci,
         &s3c_device_rtc,
-        &s3c_device_timer[1],
+        &samsung_device_pwm,
         &s3c_device_ts,
         &s3c_device_usb_hsotg,
         &s3c64xx_device_iis0,
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index bd3295a19ad7..d90b450c5645 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -274,6 +274,7 @@ static struct platform_device *smdk6410_devices[] __initdata = {
         &s3c_device_i2c1,
         &s3c_device_fb,
         &s3c_device_ohci,
+        &samsung_device_pwm,
         &s3c_device_usb_hsotg,
         &s3c64xx_device_iisv4,
         &samsung_device_keypad,
@@ -691,9 +692,9 @@ static void __init smdk6410_machine_init(void)
 
         s3c_ide_set_platdata(&smdk6410_ide_pdata);
 
-        samsung_bl_set(&smdk6410_bl_gpio_info, &smdk6410_bl_data);
-
         platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
+
+        samsung_bl_set(&smdk6410_bl_gpio_info, &smdk6410_bl_data);
 }
 
 MACHINE_START(SMDK6410, "SMDK6410")
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index 5a707bdb9ea0..bb2111b3751e 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -11,14 +11,12 @@ config CPU_S5P6440
         bool
         select S5P_SLEEP if PM
         select SAMSUNG_DMADEV
-        select SAMSUNG_HRT
         select SAMSUNG_WAKEMASK if PM
         help
           Enable S5P6440 CPU support
 
 config CPU_S5P6450
         bool
-        select SAMSUNG_HRT
         select S5P_SLEEP if PM
         select SAMSUNG_DMADEV
         select SAMSUNG_WAKEMASK if PM
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index 3537815247f1..ae34a1d5e10a 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -629,6 +629,4 @@ void __init s5p6440_register_clocks(void)
         clkdev_add_table(s5p6440_clk_lookup, ARRAY_SIZE(s5p6440_clk_lookup));
 
         s3c24xx_register_clock(&dummy_apb_pclk);
-
-        s3c_pwmclk_init();
 }
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index af384ddd2dcf..0b3ca2ed53e9 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -698,6 +698,4 @@ void __init s5p6450_register_clocks(void)
         clkdev_add_table(s5p6450_clk_lookup, ARRAY_SIZE(s5p6450_clk_lookup));
 
         s3c24xx_register_clock(&dummy_apb_pclk);
-
-        s3c_pwmclk_init();
 }
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
index dfdfdc320ce7..42e14f2e7ca7 100644
--- a/arch/arm/mach-s5p64x0/common.c
+++ b/arch/arm/mach-s5p64x0/common.c
@@ -19,6 +19,7 @@
 #include <linux/io.h>
 #include <linux/device.h>
 #include <linux/serial_core.h>
+#include <clocksource/samsung_pwm.h>
 #include <linux/platform_device.h>
 #include <linux/sched.h>
 #include <linux/dma-mapping.h>
@@ -47,6 +48,7 @@
 #include <plat/fb-core.h>
 #include <plat/spi-core.h>
 #include <plat/gpio-cfg.h>
+#include <plat/pwm-core.h>
 #include <plat/regs-irqtype.h>
 #include <plat/regs-serial.h>
 #include <plat/watchdog-reset.h>
@@ -157,6 +159,30 @@ static void s5p64x0_idle(void)
         cpu_do_idle();
 }
 
+static struct samsung_pwm_variant s5p64x0_pwm_variant = {
+        .bits           = 32,
+        .div_base       = 0,
+        .has_tint_cstat = true,
+        .tclk_mask      = 0,
+};
+
+void __init samsung_set_timer_source(unsigned int event, unsigned int source)
+{
+        s5p64x0_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
+        s5p64x0_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
+}
+
+void __init samsung_timer_init(void)
+{
+        unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
+                IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
+                IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
+        };
+
+        samsung_pwm_clocksource_init(S3C_VA_TIMER,
+                                        timer_irqs, &s5p64x0_pwm_variant);
+}
+
 /*
  * s5p64x0_map_io
  *
@@ -176,6 +202,7 @@ void __init s5p64x0_init_io(struct map_desc *mach_desc, int size)
         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
         samsung_wdt_reset_init(S3C_VA_WATCHDOG);
 
+        samsung_pwm_set_platdata(&s5p64x0_pwm_variant);
 }
 
 void __init s5p6440_map_io(void)
diff --git a/arch/arm/mach-s5p64x0/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h
index 5b845e849b30..53982db9d259 100644
--- a/arch/arm/mach-s5p64x0/include/mach/irqs.h
+++ b/arch/arm/mach-s5p64x0/include/mach/irqs.h
@@ -141,8 +141,6 @@
 
 #define IRQ_EINT_GROUP(grp, x)  (IRQ_EINT_GROUP##grp##_BASE + (x))
 
-#define IRQ_TIMER_BASE          (11)
-
 /* Set the default NR_IRQS */
 
 #define NR_IRQS                 (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
index 0c0175dbfa34..50a6e96d6389 100644
--- a/arch/arm/mach-s5p64x0/include/mach/map.h
+++ b/arch/arm/mach-s5p64x0/include/mach/map.h
@@ -76,6 +76,7 @@
 #define S5P_PA_TIMER            S5P64X0_PA_TIMER
 
 #define SAMSUNG_PA_ADC          S5P64X0_PA_ADC
+#define SAMSUNG_PA_TIMER        S5P64X0_PA_TIMER
 
 /* UART */
 
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 73f71a698a34..0b00304c1e91 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -162,6 +162,7 @@ static struct platform_device *smdk6440_devices[] __initdata = {
         &s3c_device_rtc,
         &s3c_device_i2c0,
         &s3c_device_i2c1,
+        &samsung_device_pwm,
         &s3c_device_ts,
         &s3c_device_wdt,
         &s5p6440_device_iis,
@@ -254,8 +255,6 @@ static void __init smdk6440_machine_init(void)
         i2c_register_board_info(1, smdk6440_i2c_devs1,
                         ARRAY_SIZE(smdk6440_i2c_devs1));
 
-        samsung_bl_set(&smdk6440_bl_gpio_info, &smdk6440_bl_data);
-
         s5p6440_set_lcd_interface();
         s3c_fb_set_platdata(&smdk6440_lcd_pdata);
 
@@ -264,6 +263,8 @@ static void __init smdk6440_machine_init(void)
         s3c_sdhci2_set_platdata(&smdk6440_hsmmc2_pdata);
 
         platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices));
+
+        samsung_bl_set(&smdk6440_bl_gpio_info, &smdk6440_bl_data);
 }
 
 MACHINE_START(SMDK6440, "SMDK6440")
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index 18303e12019f..5949296e88fd 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -180,6 +180,7 @@ static struct platform_device *smdk6450_devices[] __initdata = {
         &s3c_device_rtc,
         &s3c_device_i2c0,
         &s3c_device_i2c1,
+        &samsung_device_pwm,
         &s3c_device_ts,
         &s3c_device_wdt,
         &s5p6450_device_iis0,
@@ -273,8 +274,6 @@ static void __init smdk6450_machine_init(void)
         i2c_register_board_info(1, smdk6450_i2c_devs1,
                         ARRAY_SIZE(smdk6450_i2c_devs1));
 
-        samsung_bl_set(&smdk6450_bl_gpio_info, &smdk6450_bl_data);
-
         s5p6450_set_lcd_interface();
         s3c_fb_set_platdata(&smdk6450_lcd_pdata);
 
@@ -283,6 +282,8 @@ static void __init smdk6450_machine_init(void)
         s3c_sdhci2_set_platdata(&smdk6450_hsmmc2_pdata);
 
         platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices));
+
+        samsung_bl_set(&smdk6450_bl_gpio_info, &smdk6450_bl_data);
 }
 
 MACHINE_START(SMDK6450, "SMDK6450")
diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c
index 97c2a08ad490..861e15cea691 100644
--- a/arch/arm/mach-s5p64x0/pm.c
+++ b/arch/arm/mach-s5p64x0/pm.c
@@ -18,7 +18,6 @@
 
 #include <plat/cpu.h>
 #include <plat/pm.h>
-#include <plat/regs-timer.h>
 #include <plat/wakeup-mask.h>
 
 #include <mach/regs-clock.h>
@@ -48,8 +47,6 @@ static struct sleep_save s5p64x0_misc_save[] = {
         SAVE_ITEM(S5P64X0_MEM0CONSLP1),
         SAVE_ITEM(S5P64X0_MEM0DRVCON),
         SAVE_ITEM(S5P64X0_MEM1DRVCON),
-
-        SAVE_ITEM(S3C64XX_TINT_CSTAT),
 };
 
 /* DPLL is present only in S5P6450 */
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index 2f456a4533ba..15170be97a74 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -11,7 +11,6 @@ config CPU_S5PC100
         bool
         select S5P_EXT_INT
         select SAMSUNG_DMADEV
-        select SAMSUNG_HRT
         help
           Enable S5PC100 CPU support
 
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index a206dc35eff1..d0dc10ee7729 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -1358,6 +1358,4 @@ void __init s5pc100_register_clocks(void)
                 s3c_disable_clocks(clk_cdev[ptr], 1);
 
         s3c24xx_register_clock(&dummy_apb_pclk);
-
-        s3c_pwmclk_init();
 }
diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c
index 4bdfecf6d024..c5a8eeacf81c 100644
--- a/arch/arm/mach-s5pc100/common.c
+++ b/arch/arm/mach-s5pc100/common.c
@@ -22,6 +22,7 @@
 #include <linux/io.h>
 #include <linux/device.h>
 #include <linux/serial_core.h>
+#include <clocksource/samsung_pwm.h>
 #include <linux/platform_device.h>
 #include <linux/sched.h>
 #include <linux/reboot.h>
@@ -46,6 +47,7 @@
 #include <plat/fb-core.h>
 #include <plat/iic-core.h>
 #include <plat/onenand-core.h>
+#include <plat/pwm-core.h>
 #include <plat/spi-core.h>
 #include <plat/regs-serial.h>
 #include <plat/watchdog-reset.h>
@@ -132,6 +134,30 @@ static struct map_desc s5pc100_iodesc[] __initdata = {
         }
 };
 
+static struct samsung_pwm_variant s5pc100_pwm_variant = {
+        .bits           = 32,
+        .div_base       = 0,
+        .has_tint_cstat = true,
+        .tclk_mask      = (1 << 5),
+};
+
+void __init samsung_set_timer_source(unsigned int event, unsigned int source)
+{
+        s5pc100_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
+        s5pc100_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
+}
+
+void __init samsung_timer_init(void)
+{
+        unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
+                IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
+                IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
+        };
+
+        samsung_pwm_clocksource_init(S3C_VA_TIMER,
+                                        timer_irqs, &s5pc100_pwm_variant);
+}
+
 /*
  * s5pc100_map_io
  *
@@ -149,6 +175,8 @@ void __init s5pc100_init_io(struct map_desc *mach_desc, int size)
         s5p_init_cpu(S5P_VA_CHIPID);
 
         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
+
+        samsung_pwm_set_platdata(&s5pc100_pwm_variant);
 }
 
 void __init s5pc100_map_io(void)
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h
index 2870f12c7926..d2eb4757381f 100644
--- a/arch/arm/mach-s5pc100/include/mach/irqs.h
+++ b/arch/arm/mach-s5pc100/include/mach/irqs.h
@@ -97,8 +97,6 @@
 #define IRQ_SDMFIQ              S5P_IRQ_VIC2(31)
 #define IRQ_VIC_END             S5P_IRQ_VIC2(31)
 
-#define IRQ_TIMER_BASE          (11)
-
 #define S5P_EINT_BASE1          (S5P_IRQ_VIC0(0))
 #define S5P_EINT_BASE2          (IRQ_VIC_END + 1)
 
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index 54bc4f82e17a..2550b6112b82 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -116,6 +116,7 @@
 #define SAMSUNG_PA_ADC                  S5PC100_PA_TSADC
 #define SAMSUNG_PA_CFCON                S5PC100_PA_CFCON
 #define SAMSUNG_PA_KEYPAD               S5PC100_PA_KEYPAD
+#define SAMSUNG_PA_TIMER                S5PC100_PA_TIMER
 
 #define S5PC100_VA_OTHERS               (S3C_VA_SYS + 0x10000)
 
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 8c880f76f274..7c57a221785e 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -194,6 +194,7 @@ static struct platform_device *smdkc100_devices[] __initdata = {
         &s3c_device_hsmmc0,
         &s3c_device_hsmmc1,
         &s3c_device_hsmmc2,
+        &samsung_device_pwm,
         &s3c_device_ts,
         &s3c_device_wdt,
         &smdkc100_lcd_powerdev,
@@ -246,9 +247,9 @@ static void __init smdkc100_machine_init(void)
         gpio_request(S5PC100_GPH0(6), "GPH0");
         smdkc100_lcd_power_set(&smdkc100_lcd_power_data, 0);
 
-        samsung_bl_set(&smdkc100_bl_gpio_info, &smdkc100_bl_data);
-
         platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices));
+
+        samsung_bl_set(&smdkc100_bl_gpio_info, &smdkc100_bl_data);
 }
 
 MACHINE_START(SMDKC100, "SMDKC100")
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 0963283a7c5d..caaedafbbf5f 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -15,7 +15,6 @@ config CPU_S5PV210
         select S5P_PM if PM
         select S5P_SLEEP if PM
         select SAMSUNG_DMADEV
-        select SAMSUNG_HRT
         help
           Enable S5PV210 CPU support
 
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index f051f53e35b7..ca463724a3df 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -1362,5 +1362,4 @@ void __init s5pv210_register_clocks(void)
         for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
                 s3c_disable_clocks(clk_cdev[ptr], 1);
 
-        s3c_pwmclk_init();
 }
diff --git a/arch/arm/mach-s5pv210/common.c b/arch/arm/mach-s5pv210/common.c
index 023f1a796a9c..26027a29b8a1 100644
--- a/arch/arm/mach-s5pv210/common.c
+++ b/arch/arm/mach-s5pv210/common.c
@@ -19,6 +19,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/device.h>
+#include <clocksource/samsung_pwm.h>
 #include <linux/platform_device.h>
 #include <linux/sched.h>
 #include <linux/dma-mapping.h>
@@ -42,6 +43,7 @@
 #include <plat/fimc-core.h>
 #include <plat/iic-core.h>
 #include <plat/keypad-core.h>
+#include <plat/pwm-core.h>
 #include <plat/tv-core.h>
 #include <plat/spi-core.h>
 #include <plat/regs-serial.h>
@@ -148,6 +150,30 @@ void s5pv210_restart(enum reboot_mode mode, const char *cmd)
         __raw_writel(0x1, S5P_SWRESET);
 }
 
+static struct samsung_pwm_variant s5pv210_pwm_variant = {
+        .bits           = 32,
+        .div_base       = 0,
+        .has_tint_cstat = true,
+        .tclk_mask      = (1 << 5),
+};
+
+void __init samsung_set_timer_source(unsigned int event, unsigned int source)
+{
+        s5pv210_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
+        s5pv210_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
+}
+
+void __init samsung_timer_init(void)
+{
+        unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
+                IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
+                IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
+        };
+
+        samsung_pwm_clocksource_init(S3C_VA_TIMER,
+                                        timer_irqs, &s5pv210_pwm_variant);
+}
+
 /*
  * s5pv210_map_io
  *
@@ -165,6 +191,8 @@ void __init s5pv210_init_io(struct map_desc *mach_desc, int size)
         s5p_init_cpu(S5P_VA_CHIPID);
 
         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
+
+        samsung_pwm_set_platdata(&s5pv210_pwm_variant);
 }
 
 void __init s5pv210_map_io(void)
diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h
index e777e010ed2e..5e0de3a31f3d 100644
--- a/arch/arm/mach-s5pv210/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv210/include/mach/irqs.h
@@ -118,8 +118,6 @@
 #define IRQ_MDNIE3              S5P_IRQ_VIC3(8)
 #define IRQ_VIC_END             S5P_IRQ_VIC3(31)
 
-#define IRQ_TIMER_BASE          (11)
-
 #define S5P_EINT_BASE1          (S5P_IRQ_VIC0(0))
 #define S5P_EINT_BASE2          (IRQ_VIC_END + 1)
 
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index b7c8a1917ffc..763929aca52d 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -139,6 +139,7 @@
 #define SAMSUNG_PA_ADC                  S5PV210_PA_ADC
 #define SAMSUNG_PA_CFCON                S5PV210_PA_CFCON
 #define SAMSUNG_PA_KEYPAD               S5PV210_PA_KEYPAD
+#define SAMSUNG_PA_TIMER                S5PV210_PA_TIMER
 
 /* UART */
 
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index d50b6f124465..6d72bb992e38 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -218,6 +218,7 @@ static struct platform_device *smdkv210_devices[] __initdata = {
         &s3c_device_i2c0,
         &s3c_device_i2c1,
         &s3c_device_i2c2,
+        &samsung_device_pwm,
         &s3c_device_rtc,
         &s3c_device_ts,
         &s3c_device_usb_hsotg,
@@ -316,11 +317,11 @@ static void __init smdkv210_machine_init(void)
 
         s3c_fb_set_platdata(&smdkv210_lcd0_pdata);
 
-        samsung_bl_set(&smdkv210_bl_gpio_info, &smdkv210_bl_data);
-
         s3c_hsotg_set_platdata(&smdkv210_hsotg_pdata);
 
         platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices));
+
+        samsung_bl_set(&smdkv210_bl_gpio_info, &smdkv210_bl_data);
 }
 
 MACHINE_START(SMDKV210, "SMDKV210")
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
index 2b68a67b6e95..3cf3f9c8ddd1 100644
--- a/arch/arm/mach-s5pv210/pm.c
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -21,7 +21,6 @@
 
 #include <plat/cpu.h>
 #include <plat/pm.h>
-#include <plat/regs-timer.h>
 
 #include <mach/regs-irq.h>
 #include <mach/regs-clock.h>
@@ -77,15 +76,6 @@ static struct sleep_save s5pv210_core_save[] = {
         /* Clock ETC */
         SAVE_ITEM(S5P_CLK_OUT),
         SAVE_ITEM(S5P_MDNIE_SEL),
-
-        /* PWM Register */
-        SAVE_ITEM(S3C2410_TCFG0),
-        SAVE_ITEM(S3C2410_TCFG1),
-        SAVE_ITEM(S3C64XX_TINT_CSTAT),
-        SAVE_ITEM(S3C2410_TCON),
-        SAVE_ITEM(S3C2410_TCNTB(0)),
-        SAVE_ITEM(S3C2410_TCMPB(0)),
-        SAVE_ITEM(S3C2410_TCNTO(0)),
 };
 
 static int s5pv210_cpu_suspend(unsigned long arg)
diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
index 5eb0caa6a7d0..1fbc39a14e25 100644
--- a/arch/arm/mach-shmobile/board-ape6evm.c
+++ b/arch/arm/mach-shmobile/board-ape6evm.c
@@ -20,7 +20,6 @@
 
 #include <linux/gpio.h>
 #include <linux/interrupt.h>
-#include <linux/irqchip.h>
 #include <linux/kernel.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/platform_device.h>
@@ -102,7 +101,6 @@ static const char *ape6evm_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(APE6EVM_DT, "ape6evm")
-        .init_irq       = irqchip_init,
         .init_time      = shmobile_timer_init,
         .init_machine   = ape6evm_add_standard_devices,
         .dt_compat      = ape6evm_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 3a6ffa250fb1..4e3670a28a7c 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -678,15 +678,6 @@ static struct platform_device vcc_sdhi1 = {
 };
 
 /* SDHI0 */
-/*
- * FIXME
- *
- * It use polling mode here, since
- * CD (= Card Detect) pin is not connected to SDHI0_CD.
- * We can use IRQ31 as card detect irq,
- * but it needs chattering removal operation
- */
-#define IRQ31   irq_pin(31)
 static struct sh_mobile_sdhi_info sdhi0_info = {
         .dma_slave_tx   = SHDMA_SLAVE_SDHI0_TX,
         .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c
index 4368000e1127..15900f1f8af7 100644
--- a/arch/arm/mach-shmobile/board-kzm9d.c
+++ b/arch/arm/mach-shmobile/board-kzm9d.c
@@ -85,7 +85,7 @@ static const char *kzm9d_boards_compat_dt[] __initdata = {
 DT_MACHINE_START(KZM9D_DT, "kzm9d")
         .smp            = smp_ops(emev2_smp_ops),
         .map_io         = emev2_map_io,
-        .init_early     = emev2_add_early_devices,
+        .init_early     = emev2_init_delay,
         .nr_irqs        = NR_IRQS_LEGACY,
         .init_irq       = emev2_init_irq,
         .init_machine   = kzm9d_add_standard_devices,
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
index 44055fe8a45c..41092bb01ee5 100644
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -24,7 +24,6 @@
 #include <linux/gpio.h>
 #include <linux/io.h>
 #include <linux/irq.h>
-#include <linux/irqchip.h>
 #include <linux/input.h>
 #include <linux/of_platform.h>
 #include <linux/pinctrl/machine.h>
@@ -99,7 +98,6 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g-reference")
         .map_io         = sh73a0_map_io,
         .init_early     = sh73a0_init_delay,
         .nr_irqs        = NR_IRQS_LEGACY,
-        .init_irq       = irqchip_init,
         .init_machine   = kzm_init,
         .init_time      = shmobile_timer_init,
         .dt_compat      = kzm9g_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index 8d6bd5c5efb9..78d92d34665d 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -22,7 +22,6 @@
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <linux/interrupt.h>
-#include <linux/irqchip.h>
 #include <linux/kernel.h>
 #include <linux/leds.h>
 #include <linux/pinctrl/machine.h>
@@ -103,7 +102,6 @@ static const char *lager_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(LAGER_DT, "lager")
-        .init_irq       = irqchip_init,
         .init_time      = r8a7790_timer_init,
         .init_machine   = lager_add_standard_devices,
         .dt_compat      = lager_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/clock-emev2.c b/arch/arm/mach-shmobile/clock-emev2.c
index 4710f1847bb7..56dd0cfcddc7 100644
--- a/arch/arm/mach-shmobile/clock-emev2.c
+++ b/arch/arm/mach-shmobile/clock-emev2.c
@@ -221,7 +221,7 @@ void __init emev2_clock_init(void)
         smu_base = ioremap(EMEV2_SMU_BASE, PAGE_SIZE);
         BUG_ON(!smu_base);
 
-        /* setup STI timer to run on 37.768 kHz and deassert reset */
+        /* setup STI timer to run on 32.768 kHz and deassert reset */
         emev2_smu_write(0, STI_CLKSEL);
         emev2_smu_write(1, STI_RSTCTRL);
 
diff --git a/arch/arm/mach-shmobile/include/mach/dma.h b/arch/arm/mach-shmobile/include/mach/dma.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-shmobile/include/mach/dma.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-shmobile/include/mach/emev2.h b/arch/arm/mach-shmobile/include/mach/emev2.h
index ac3751705cab..3e0c0441c782 100644
--- a/arch/arm/mach-shmobile/include/mach/emev2.h
+++ b/arch/arm/mach-shmobile/include/mach/emev2.h
@@ -3,7 +3,7 @@
 
 extern void emev2_map_io(void);
 extern void emev2_init_irq(void);
-extern void emev2_add_early_devices(void);
+extern void emev2_init_delay(void);
 extern void emev2_add_standard_devices(void);
 extern void emev2_clock_init(void);
 extern void emev2_set_boot_vector(unsigned long value);
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h
index a7c6d151cdd5..2866704e7afd 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h
@@ -36,7 +36,6 @@ extern void r8a7778_add_vin_device(int id,
 
 extern void r8a7778_init_late(void);
 extern void r8a7778_init_delay(void);
-extern void r8a7778_init_irq(void);
 extern void r8a7778_init_irq_dt(void);
 extern void r8a7778_clock_init(void);
 extern void r8a7778_init_irq_extpin(int irlm);
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index 1ccddd228112..e4b46930db52 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -20,7 +20,6 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
-#include <linux/irqchip.h>
 #include <linux/platform_device.h>
 #include <linux/platform_data/gpio-em.h>
 #include <linux/of_platform.h>
@@ -63,102 +62,40 @@ void __init emev2_map_io(void)
 
 /* UART */
 static struct resource uart0_resources[] = {
-        [0]     = {
-                .start  = 0xe1020000,
-                .end    = 0xe1020037,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1]     = {
-                .start  = 40,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-static struct platform_device uart0_device = {
-        .name           = "serial8250-em",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(uart0_resources),
-        .resource       = uart0_resources,
+        DEFINE_RES_MEM(0xe1020000, 0x38),
+        DEFINE_RES_IRQ(40),
 };
 
 static struct resource uart1_resources[] = {
-        [0]     = {
-                .start  = 0xe1030000,
-                .end    = 0xe1030037,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1]     = {
-                .start  = 41,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-static struct platform_device uart1_device = {
-        .name           = "serial8250-em",
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(uart1_resources),
-        .resource       = uart1_resources,
+        DEFINE_RES_MEM(0xe1030000, 0x38),
+        DEFINE_RES_IRQ(41),
 };
 
 static struct resource uart2_resources[] = {
-        [0]     = {
-                .start  = 0xe1040000,
-                .end    = 0xe1040037,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1]     = {
-                .start  = 42,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-static struct platform_device uart2_device = {
-        .name           = "serial8250-em",
-        .id             = 2,
-        .num_resources  = ARRAY_SIZE(uart2_resources),
-        .resource       = uart2_resources,
+        DEFINE_RES_MEM(0xe1040000, 0x38),
+        DEFINE_RES_IRQ(42),
 };
 
 static struct resource uart3_resources[] = {
-        [0]     = {
-                .start  = 0xe1050000,
-                .end    = 0xe1050037,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1]     = {
-                .start  = 43,
-                .flags  = IORESOURCE_IRQ,
-        }
+        DEFINE_RES_MEM(0xe1050000, 0x38),
+        DEFINE_RES_IRQ(43),
 };
 
-static struct platform_device uart3_device = {
-        .name           = "serial8250-em",
-        .id             = 3,
-        .num_resources  = ARRAY_SIZE(uart3_resources),
-        .resource       = uart3_resources,
-};
+#define emev2_register_uart(idx)                                        \
+        platform_device_register_simple("serial8250-em", idx,           \
+                                        uart##idx##_resources,          \
+                                        ARRAY_SIZE(uart##idx##_resources))
 
 /* STI */
 static struct resource sti_resources[] = {
-        [0] = {
-                .name   = "STI",
-                .start  = 0xe0180000,
-                .end    = 0xe0180053,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = 157,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device sti_device = {
-        .name           = "em_sti",
-        .id             = 0,
-        .resource       = sti_resources,
-        .num_resources  = ARRAY_SIZE(sti_resources),
+        DEFINE_RES_MEM(0xe0180000, 0x54),
+        DEFINE_RES_IRQ(157),
 };
 
+#define emev2_register_sti()                                    \
+        platform_device_register_simple("em_sti", 0,            \
+                                        sti_resources,          \
+                                        ARRAY_SIZE(sti_resources))
 
 /* GIO */
 static struct gpio_em_config gio0_config = {
@@ -168,36 +105,10 @@ static struct gpio_em_config gio0_config = {
 };
 
 static struct resource gio0_resources[] = {
-        [0] = {
-                .name   = "GIO_000",
-                .start  = 0xe0050000,
-                .end    = 0xe005002b,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .name   = "GIO_000",
-                .start  = 0xe0050040,
-                .end    = 0xe005005f,
-                .flags  = IORESOURCE_MEM,
-        },
-        [2] = {
-                .start  = 99,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
-                .start  = 100,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device gio0_device = {
-        .name           = "em_gio",
-        .id             = 0,
-        .resource       = gio0_resources,
-        .num_resources  = ARRAY_SIZE(gio0_resources),
-        .dev            = {
-                .platform_data  = &gio0_config,
-        },
+        DEFINE_RES_MEM(0xe0050000, 0x2c),
+        DEFINE_RES_MEM(0xe0050040, 0x20),
+        DEFINE_RES_IRQ(99),
+        DEFINE_RES_IRQ(100),
 };
 
 static struct gpio_em_config gio1_config = {
@@ -207,36 +118,10 @@ static struct gpio_em_config gio1_config = {
 };
 
 static struct resource gio1_resources[] = {
-        [0] = {
-                .name   = "GIO_032",
-                .start  = 0xe0050080,
-                .end    = 0xe00500ab,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .name   = "GIO_032",
-                .start  = 0xe00500c0,
-                .end    = 0xe00500df,
-                .flags  = IORESOURCE_MEM,
-        },
-        [2] = {
-                .start  = 101,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
-                .start  = 102,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device gio1_device = {
-        .name           = "em_gio",
-        .id             = 1,
-        .resource       = gio1_resources,
-        .num_resources  = ARRAY_SIZE(gio1_resources),
-        .dev            = {
-                .platform_data  = &gio1_config,
-        },
+        DEFINE_RES_MEM(0xe0050080, 0x2c),
+        DEFINE_RES_MEM(0xe00500c0, 0x20),
+        DEFINE_RES_IRQ(101),
+        DEFINE_RES_IRQ(102),
 };
 
 static struct gpio_em_config gio2_config = {
@@ -246,36 +131,10 @@ static struct gpio_em_config gio2_config = {
 };
 
 static struct resource gio2_resources[] = {
-        [0] = {
-                .name   = "GIO_064",
-                .start  = 0xe0050100,
-                .end    = 0xe005012b,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .name   = "GIO_064",
-                .start  = 0xe0050140,
-                .end    = 0xe005015f,
-                .flags  = IORESOURCE_MEM,
-        },
-        [2] = {
-                .start  = 103,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
-                .start  = 104,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device gio2_device = {
-        .name           = "em_gio",
-        .id             = 2,
-        .resource       = gio2_resources,
-        .num_resources  = ARRAY_SIZE(gio2_resources),
-        .dev            = {
-                .platform_data  = &gio2_config,
-        },
+        DEFINE_RES_MEM(0xe0050100, 0x2c),
+        DEFINE_RES_MEM(0xe0050140, 0x20),
+        DEFINE_RES_IRQ(103),
+        DEFINE_RES_IRQ(104),
 };
 
 static struct gpio_em_config gio3_config = {
@@ -285,36 +144,10 @@ static struct gpio_em_config gio3_config = {
 };
 
 static struct resource gio3_resources[] = {
-        [0] = {
-                .name   = "GIO_096",
-                .start  = 0xe0050180,
-                .end    = 0xe00501ab,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .name   = "GIO_096",
-                .start  = 0xe00501c0,
-                .end    = 0xe00501df,
-                .flags  = IORESOURCE_MEM,
-        },
-        [2] = {
-                .start  = 105,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
-                .start  = 106,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device gio3_device = {
-        .name           = "em_gio",
-        .id             = 3,
-        .resource       = gio3_resources,
-        .num_resources  = ARRAY_SIZE(gio3_resources),
-        .dev            = {
-                .platform_data  = &gio3_config,
-        },
+        DEFINE_RES_MEM(0xe0050180, 0x2c),
+        DEFINE_RES_MEM(0xe00501c0, 0x20),
+        DEFINE_RES_IRQ(105),
+        DEFINE_RES_IRQ(106),
 };
 
 static struct gpio_em_config gio4_config = {
@@ -324,102 +157,51 @@ static struct gpio_em_config gio4_config = {
 };
 
 static struct resource gio4_resources[] = {
-        [0] = {
-                .name   = "GIO_128",
-                .start  = 0xe0050200,
-                .end    = 0xe005022b,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .name   = "GIO_128",
-                .start  = 0xe0050240,
-                .end    = 0xe005025f,
-                .flags  = IORESOURCE_MEM,
-        },
-        [2] = {
-                .start  = 107,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
-                .start  = 108,
-                .flags  = IORESOURCE_IRQ,
-        },
+        DEFINE_RES_MEM(0xe0050200, 0x2c),
+        DEFINE_RES_MEM(0xe0050240, 0x20),
+        DEFINE_RES_IRQ(107),
+        DEFINE_RES_IRQ(108),
 };
 
-static struct platform_device gio4_device = {
-        .name           = "em_gio",
-        .id             = 4,
-        .resource       = gio4_resources,
-        .num_resources  = ARRAY_SIZE(gio4_resources),
-        .dev            = {
-                .platform_data  = &gio4_config,
-        },
-};
+#define emev2_register_gio(idx)                                         \
+        platform_device_register_resndata(&platform_bus, "em_gio",      \
+                                          idx, gio##idx##_resources,    \
+                                          ARRAY_SIZE(gio##idx##_resources), \
+                                          &gio##idx##_config,           \
+                                          sizeof(struct gpio_em_config))
 
 static struct resource pmu_resources[] = {
-        [0] = {
-                .start  = 152,
-                .end    = 152,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = 153,
-                .end    = 153,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device pmu_device = {
-        .name           = "arm-pmu",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(pmu_resources),
-        .resource       = pmu_resources,
-};
-
-static struct platform_device *emev2_early_devices[] __initdata = {
-        &uart0_device,
-        &uart1_device,
-        &uart2_device,
-        &uart3_device,
+        DEFINE_RES_IRQ(152),
+        DEFINE_RES_IRQ(153),
 };
 
-static struct platform_device *emev2_late_devices[] __initdata = {
-        &sti_device,
-        &gio0_device,
-        &gio1_device,
-        &gio2_device,
-        &gio3_device,
-        &gio4_device,
-        &pmu_device,
-};
+#define emev2_register_pmu()                                    \
+        platform_device_register_simple("arm-pmu", -1,          \
+                                        pmu_resources,          \
+                                        ARRAY_SIZE(pmu_resources))
 
 void __init emev2_add_standard_devices(void)
 {
         emev2_clock_init();
 
-        platform_add_devices(emev2_early_devices,
-                             ARRAY_SIZE(emev2_early_devices));
-
-        platform_add_devices(emev2_late_devices,
-                             ARRAY_SIZE(emev2_late_devices));
+        emev2_register_uart(0);
+        emev2_register_uart(1);
+        emev2_register_uart(2);
+        emev2_register_uart(3);
+        emev2_register_sti();
+        emev2_register_gio(0);
+        emev2_register_gio(1);
+        emev2_register_gio(2);
+        emev2_register_gio(3);
+        emev2_register_gio(4);
+        emev2_register_pmu();
 }
 
-static void __init emev2_init_delay(void)
+void __init emev2_init_delay(void)
 {
         shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */
 }
 
-void __init emev2_add_early_devices(void)
-{
-        emev2_init_delay();
-
-        early_platform_add_devices(emev2_early_devices,
-                                   ARRAY_SIZE(emev2_early_devices));
-
-        /* setup early console here as well */
-        shmobile_setup_console();
-}
-
 void __init emev2_init_irq(void)
 {
         void __iomem *gic_dist_base;
@@ -435,15 +217,6 @@ void __init emev2_init_irq(void)
 }
 
 #ifdef CONFIG_USE_OF
-static const struct of_dev_auxdata emev2_auxdata_lookup[] __initconst = {
-        { }
-};
-
-static void __init emev2_add_standard_devices_dt(void)
-{
-        of_platform_populate(NULL, of_default_bus_match_table,
-                             emev2_auxdata_lookup, NULL);
-}
 
 static const char *emev2_boards_compat_dt[] __initdata = {
         "renesas,emev2",
@@ -454,8 +227,6 @@ DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
         .smp            = smp_ops(emev2_smp_ops),
         .init_early     = emev2_init_delay,
         .nr_irqs        = NR_IRQS_LEGACY,
-        .init_irq       = irqchip_init,
-        .init_machine   = emev2_add_standard_devices_dt,
         .dt_compat      = emev2_boards_compat_dt,
 MACHINE_END
 
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index 7f45c2edbca9..a8c4e41bf27a 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -18,7 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 #include <linux/irq.h>
-#include <linux/irqchip.h>
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
 #include <linux/platform_data/irq-renesas-irqc.h>
@@ -194,7 +193,6 @@ static const char *r8a73a4_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
-        .init_irq       = irqchip_init,
         .init_machine   = r8a73a4_add_standard_devices_dt,
         .init_time      = shmobile_timer_init,
         .dt_compat      = r8a73a4_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 00c5a707238b..ac29c2ee011f 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -986,16 +986,22 @@ void __init r8a7740_add_early_devices(void)
 
 #ifdef CONFIG_USE_OF
 
-static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = {
-        { }
-};
+void __init r8a7740_add_early_devices_dt(void)
+{
+        shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
+
+        early_platform_add_devices(r8a7740_early_devices,
+                                   ARRAY_SIZE(r8a7740_early_devices));
+
+        /* setup early console here as well */
+        shmobile_setup_console();
+}
 
 void __init r8a7740_add_standard_devices_dt(void)
 {
         platform_add_devices(r8a7740_devices_dt,
                             ARRAY_SIZE(r8a7740_devices_dt));
-        of_platform_populate(NULL, of_default_bus_match_table,
-                             r8a7740_auxdata_lookup, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 void __init r8a7740_init_delay(void)
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 0174f059eac3..203becfc6e31 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -53,7 +53,7 @@
         .irqs           = SCIx_IRQ_MUXED(irq),                  \
 }
 
-static struct plat_sci_port scif_platform_data[] = {
+static struct plat_sci_port scif_platform_data[] __initdata = {
         SCIF_INFO(0xffe40000, gic_iid(0x66)),
         SCIF_INFO(0xffe41000, gic_iid(0x67)),
         SCIF_INFO(0xffe42000, gic_iid(0x68)),
@@ -63,24 +63,24 @@ static struct plat_sci_port scif_platform_data[] = {
 };
 
 /* TMU */
-static struct resource sh_tmu0_resources[] = {
+static struct resource sh_tmu0_resources[] __initdata = {
         DEFINE_RES_MEM(0xffd80008, 12),
         DEFINE_RES_IRQ(gic_iid(0x40)),
 };
 
-static struct sh_timer_config sh_tmu0_platform_data = {
+static struct sh_timer_config sh_tmu0_platform_data __initdata = {
         .name                   = "TMU00",
         .channel_offset         = 0x4,
         .timer_bit              = 0,
         .clockevent_rating      = 200,
 };
 
-static struct resource sh_tmu1_resources[] = {
+static struct resource sh_tmu1_resources[] __initdata = {
         DEFINE_RES_MEM(0xffd80014, 12),
         DEFINE_RES_IRQ(gic_iid(0x41)),
 };
 
-static struct sh_timer_config sh_tmu1_platform_data = {
+static struct sh_timer_config sh_tmu1_platform_data __initdata = {
         .name                   = "TMU01",
         .channel_offset         = 0x10,
         .timer_bit              = 1,
@@ -189,7 +189,7 @@ USB_PLATFORM_INFO(ehci);
 USB_PLATFORM_INFO(ohci);
 
 /* Ether */
-static struct resource ether_resources[] = {
+static struct resource ether_resources[] __initdata = {
         DEFINE_RES_MEM(0xfde00000, 0x400),
         DEFINE_RES_IRQ(gic_iid(0x89)),
 };
@@ -203,17 +203,17 @@ void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
 }
 
 /* PFC/GPIO */
-static struct resource pfc_resources[] = {
+static struct resource pfc_resources[] __initdata = {
         DEFINE_RES_MEM(0xfffc0000, 0x118),
 };
 
 #define R8A7778_GPIO(idx)                                               \
-static struct resource r8a7778_gpio##idx##_resources[] = {              \
+static struct resource r8a7778_gpio##idx##_resources[] __initdata = {   \
         DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30),              \
         DEFINE_RES_IRQ(gic_iid(0x87)),                                  \
 };                                                                      \
                                                                         \
-static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data = {    \
+static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data __initdata = { \
         .gpio_base      = 32 * (idx),                                   \
         .irq_base       = GPIO_IRQ_BASE(idx),                           \
         .number_of_pins = 32,                                           \
@@ -249,7 +249,7 @@ void __init r8a7778_pinmux_init(void)
 };
 
 /* SDHI */
-static struct resource sdhi_resources[] = {
+static struct resource sdhi_resources[] __initdata = {
         /* SDHI0 */
         DEFINE_RES_MEM(0xFFE4C000, 0x100),
         DEFINE_RES_IRQ(gic_iid(0x77)),
@@ -399,12 +399,12 @@ void __init r8a7778_init_late(void)
         platform_device_register_full(&ohci_info);
 }
 
-static struct renesas_intc_irqpin_config irqpin_platform_data = {
+static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = {
         .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
         .sense_bitfield_width = 2,
 };
 
-static struct resource irqpin_resources[] = {
+static struct resource irqpin_resources[] __initdata = {
         DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
         DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
         DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
@@ -442,17 +442,25 @@ void __init r8a7778_init_irq_extpin(int irlm)
                         &irqpin_platform_data, sizeof(irqpin_platform_data));
 }
 
+void __init r8a7778_init_delay(void)
+{
+        shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
+}
+
+#ifdef CONFIG_USE_OF
 #define INT2SMSKCR0     0x82288 /* 0xfe782288 */
 #define INT2SMSKCR1     0x8228c /* 0xfe78228c */
 
 #define INT2NTSR0       0x00018 /* 0xfe700018 */
 #define INT2NTSR1       0x0002c /* 0xfe70002c */
-static void __init r8a7778_init_irq_common(void)
+void __init r8a7778_init_irq_dt(void)
 {
         void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
 
         BUG_ON(!base);
 
+        irqchip_init();
+
         /* route all interrupts to ARM */
         __raw_writel(0x73ffffff, base + INT2NTSR0);
         __raw_writel(0xffffffff, base + INT2NTSR1);
@@ -464,43 +472,6 @@ static void __init r8a7778_init_irq_common(void)
         iounmap(base);
 }
 
-void __init r8a7778_init_irq(void)
-{
-        void __iomem *gic_dist_base;
-        void __iomem *gic_cpu_base;
-
-        gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE);
-        gic_cpu_base  = ioremap_nocache(0xfe430000, PAGE_SIZE);
-        BUG_ON(!gic_dist_base || !gic_cpu_base);
-
-        /* use GIC to handle interrupts */
-        gic_init(0, 29, gic_dist_base, gic_cpu_base);
-
-        r8a7778_init_irq_common();
-}
-
-void __init r8a7778_init_delay(void)
-{
-        shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
-}
-
-#ifdef CONFIG_USE_OF
-void __init r8a7778_init_irq_dt(void)
-{
-        irqchip_init();
-        r8a7778_init_irq_common();
-}
-
-static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = {
-        {},
-};
-
-void __init r8a7778_add_standard_devices_dt(void)
-{
-        of_platform_populate(NULL, of_default_bus_match_table,
-                             r8a7778_auxdata_lookup, NULL);
-}
-
 static const char *r8a7778_compat_dt[] __initdata = {
         "renesas,r8a7778",
         NULL,
@@ -509,7 +480,6 @@ static const char *r8a7778_compat_dt[] __initdata = {
 DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
         .init_early     = r8a7778_init_delay,
         .init_irq       = r8a7778_init_irq_dt,
-        .init_machine   = r8a7778_add_standard_devices_dt,
         .init_time      = shmobile_timer_init,
         .dt_compat      = r8a7778_compat_dt,
         .init_late      = r8a7778_init_late,
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 3d8928895503..41bab625341e 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -702,10 +702,6 @@ void __init r8a7779_init_delay(void)
         shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */
 }
 
-static const struct of_dev_auxdata r8a7779_auxdata_lookup[] __initconst = {
-        {},
-};
-
 void __init r8a7779_add_standard_devices_dt(void)
 {
         /* clocks are setup late during boot in the case of DT */
@@ -713,8 +709,7 @@ void __init r8a7779_add_standard_devices_dt(void)
 
         platform_add_devices(r8a7779_devices_dt,
                              ARRAY_SIZE(r8a7779_devices_dt));
-        of_platform_populate(NULL, of_default_bus_match_table,
-                             r8a7779_auxdata_lookup, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 static const char *r8a7779_compat_dt[] __initdata = {
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index 28f94752b8ff..b7e78b9a7fdf 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -19,7 +19,6 @@
  */
 
 #include <linux/irq.h>
-#include <linux/irqchip.h>
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
 #include <linux/serial_sci.h>
@@ -177,10 +176,6 @@ void __init r8a7790_timer_init(void)
 }
 
 #ifdef CONFIG_USE_OF
-void __init r8a7790_add_standard_devices_dt(void)
-{
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
 
 static const char *r8a7790_boards_compat_dt[] __initdata = {
         "renesas,r8a7790",
@@ -188,8 +183,6 @@ static const char *r8a7790_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
-        .init_irq       = irqchip_init,
-        .init_machine   = r8a7790_add_standard_devices_dt,
         .init_time      = r8a7790_timer_init,
         .dt_compat      = r8a7790_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 5502d624aca6..13e6fdbde0a5 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -1147,10 +1147,6 @@ void __init sh7372_add_early_devices_dt(void)
         shmobile_setup_console();
 }
 
-static const struct of_dev_auxdata sh7372_auxdata_lookup[] __initconst = {
-        { }
-};
-
 void __init sh7372_add_standard_devices_dt(void)
 {
         /* clocks are setup late during boot in the case of DT */
@@ -1159,8 +1155,7 @@ void __init sh7372_add_standard_devices_dt(void)
         platform_add_devices(sh7372_early_devices,
                             ARRAY_SIZE(sh7372_early_devices));
 
-        of_platform_populate(NULL, of_default_bus_match_table,
-                             sh7372_auxdata_lookup, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 static const char *sh7372_boards_compat_dt[] __initdata = {
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 96e7ca1e4e11..516c2391b47a 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -22,7 +22,6 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
-#include <linux/irqchip.h>
 #include <linux/platform_device.h>
 #include <linux/of_platform.h>
 #include <linux/delay.h>
@@ -61,29 +60,16 @@ void __init sh73a0_map_io(void)
         iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
 }
 
-static struct resource sh73a0_pfc_resources[] = {
-        [0] = {
-                .start  = 0xe6050000,
-                .end    = 0xe6057fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = 0xe605801c,
-                .end    = 0xe6058027,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-
-static struct platform_device sh73a0_pfc_device = {
-        .name           = "pfc-sh73a0",
-        .id             = -1,
-        .resource       = sh73a0_pfc_resources,
-        .num_resources  = ARRAY_SIZE(sh73a0_pfc_resources),
+/* PFC */
+static struct resource pfc_resources[] __initdata = {
+        DEFINE_RES_MEM(0xe6050000, 0x8000),
+        DEFINE_RES_MEM(0xe605801c, 0x000c),
 };
 
 void __init sh73a0_pinmux_init(void)
 {
-        platform_device_register(&sh73a0_pfc_device);
+        platform_device_register_simple("pfc-sh73a0", -1, pfc_resources,
+                                        ARRAY_SIZE(pfc_resources));
 }
 
 static struct plat_sci_port scif0_platform_data = {
@@ -958,10 +944,6 @@ void __init sh73a0_add_early_devices(void)
 
 #ifdef CONFIG_USE_OF
 
-static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
-        {},
-};
-
 void __init sh73a0_add_standard_devices_dt(void)
 {
         struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, };
@@ -971,8 +953,7 @@ void __init sh73a0_add_standard_devices_dt(void)
 
         platform_add_devices(sh73a0_devices_dt,
                              ARRAY_SIZE(sh73a0_devices_dt));
-        of_platform_populate(NULL, of_default_bus_match_table,
-                             sh73a0_auxdata_lookup, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 
         /* Instantiate cpufreq-cpu0 */
         platform_device_register_full(&devinfo);
@@ -988,7 +969,6 @@ DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
         .map_io         = sh73a0_map_io,
         .init_early     = sh73a0_init_delay,
         .nr_irqs        = NR_IRQS_LEGACY,
-        .init_irq       = irqchip_init,
         .init_machine   = sh73a0_add_standard_devices_dt,
         .dt_compat      = sh73a0_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index 442917eedff3..df0d59afeb40 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -23,7 +23,7 @@ config ARCH_SPEAR13XX
         select CPU_V7
         select GPIO_SPEAR_SPICS
         select HAVE_ARM_SCU if SMP
-        select HAVE_ARM_TWD if LOCAL_TIMERS
+        select HAVE_ARM_TWD if SMP
         select HAVE_SMP
         select MIGHT_HAVE_CACHE_L2X0
         select PINCTRL
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index ef3a8da49b2d..59925cc896fb 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -8,7 +8,7 @@ config ARCH_TEGRA
         select COMMON_CLK
         select GENERIC_CLOCKEVENTS
         select HAVE_ARM_SCU if SMP
-        select HAVE_ARM_TWD if LOCAL_TIMERS
+        select HAVE_ARM_TWD if SMP
         select HAVE_CLK
         select HAVE_SMP
         select MIGHT_HAVE_CACHE_L2X0
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index b19b07204aaf..99a28d628297 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -8,7 +8,7 @@ config ARCH_U8500
         select CPU_V7
         select GENERIC_CLOCKEVENTS
         select HAVE_ARM_SCU if SMP
-        select HAVE_ARM_TWD if LOCAL_TIMERS
+        select HAVE_ARM_TWD if SMP
         select HAVE_SMP
         select MIGHT_HAVE_CACHE_L2X0
         help
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index b8bbabec6310..83c8677bb181 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -10,7 +10,7 @@ config ARCH_VEXPRESS
         select CPU_V7
         select GENERIC_CLOCKEVENTS
         select HAVE_ARM_SCU if SMP
-        select HAVE_ARM_TWD if LOCAL_TIMERS
+        select HAVE_ARM_TWD if SMP
         select HAVE_CLK
         select HAVE_PATA_PLATFORM
         select HAVE_SMP
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index c1d61f281e68..04f8a4a6e755 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -6,7 +6,7 @@ config ARCH_ZYNQ
         select CPU_V7
         select GENERIC_CLOCKEVENTS
         select HAVE_ARM_SCU if SMP
-        select HAVE_ARM_TWD if LOCAL_TIMERS
+        select HAVE_ARM_TWD if SMP
         select ICST
         select MIGHT_HAVE_CACHE_L2X0
         select USE_OF
diff --git a/arch/arm/mach-zynq/hotplug.c b/arch/arm/mach-zynq/hotplug.c
index c89672bd1de2..5052c70326e4 100644
--- a/arch/arm/mach-zynq/hotplug.c
+++ b/arch/arm/mach-zynq/hotplug.c
@@ -40,44 +40,6 @@ static inline void zynq_cpu_enter_lowpower(void)
           : "cc");
 }
 
-static inline void zynq_cpu_leave_lowpower(void)
-{
-        unsigned int v;
-
-        asm volatile(
-        "       mrc     p15, 0, %0, c1, c0, 0\n"
-        "       orr     %0, %0, %1\n"
-        "       mcr     p15, 0, %0, c1, c0, 0\n"
-        "       mrc     p15, 0, %0, c1, c0, 1\n"
-        "       orr     %0, %0, #0x40\n"
-        "       mcr     p15, 0, %0, c1, c0, 1\n"
-          : "=&r" (v)
-          : "Ir" (CR_C)
-          : "cc");
-}
-
-static inline void zynq_platform_do_lowpower(unsigned int cpu, int *spurious)
-{
-        /*
-         * there is no power-control hardware on this platform, so all
-         * we can do is put the core into WFI; this is safe as the calling
-         * code will have already disabled interrupts
-         */
-        for (;;) {
-                dsb();
-                wfi();
-
-                /*
-                 * Getting here, means that we have come out of WFI without
-                 * having been woken up - this shouldn't happen
-                 *
-                 * Just note it happening - when we're woken, we can report
-                 * its occurrence.
-                 */
-                (*spurious)++;
-        }
-}
-
 /*
  * platform-specific code to shutdown a CPU
  *
@@ -85,20 +47,13 @@ static inline void zynq_platform_do_lowpower(unsigned int cpu, int *spurious)
  */
 void zynq_platform_cpu_die(unsigned int cpu)
 {
-        int spurious = 0;
-
-        /*
-         * we're ready for shutdown now, so do it
-         */
         zynq_cpu_enter_lowpower();
-        zynq_platform_do_lowpower(cpu, &spurious);
 
         /*
-         * bring this CPU back into the world of cache
-         * coherency, and then restore interrupts
+         * there is no power-control hardware on this platform, so all
+         * we can do is put the core into WFI; this is safe as the calling
+         * code will have already disabled interrupts
          */
-        zynq_cpu_leave_lowpower();
-
-        if (spurious)
-                pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
+        for (;;)
+                cpu_do_idle();
 }
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index 50d008d8f87f..1836d5a34606 100644
--- a/arch/arm/mach-zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -14,32 +14,21 @@
  * 02139, USA.
  */
 
-#include <linux/export.h>
 #include <linux/io.h>
-#include <linux/fs.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
 #include <linux/of_address.h>
-#include <linux/uaccess.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/string.h>
 #include <linux/clk/zynq.h>
 #include "common.h"
 
-#define SLCR_UNLOCK_MAGIC               0xDF0D
-#define SLCR_UNLOCK                     0x8   /* SCLR unlock register */
-
+/* register offsets */
+#define SLCR_UNLOCK_OFFSET              0x8   /* SCLR unlock register */
 #define SLCR_PS_RST_CTRL_OFFSET         0x200 /* PS Software Reset Control */
+#define SLCR_A9_CPU_RST_CTRL_OFFSET     0x244 /* CPU Software Reset Control */
+#define SLCR_REBOOT_STATUS_OFFSET       0x258 /* PS Reboot Status */
 
+#define SLCR_UNLOCK_MAGIC               0xDF0D
 #define SLCR_A9_CPU_CLKSTOP             0x10
 #define SLCR_A9_CPU_RST                 0x1
 
-#define SLCR_A9_CPU_RST_CTRL            0x244 /* CPU Software Reset Control */
-#define SLCR_REBOOT_STATUS              0x258 /* PS Reboot Status */
-
 void __iomem *zynq_slcr_base;
 
 /**
@@ -54,15 +43,15 @@ void zynq_slcr_system_reset(void)
          * Note that this seems to require raw i/o
          * functions or there's a lockup?
          */
-        writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK);
+        writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);
 
         /*
          * Clear 0x0F000000 bits of reboot status register to workaround
          * the FSBL not loading the bitstream after soft-reboot
          * This is a temporary solution until we know more.
          */
-        reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS);
-        writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS);
+        reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
+        writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
         writel(1, zynq_slcr_base + SLCR_PS_RST_CTRL_OFFSET);
 }
 
@@ -72,11 +61,11 @@ void zynq_slcr_system_reset(void)
  */
 void zynq_slcr_cpu_start(int cpu)
 {
-        /* enable CPUn */
-        writel(SLCR_A9_CPU_CLKSTOP << cpu,
-               zynq_slcr_base + SLCR_A9_CPU_RST_CTRL);
-        /* enable CLK for CPUn */
-        writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL);
+        u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+        reg &= ~(SLCR_A9_CPU_RST << cpu);
+        writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+        reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
+        writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
 }
 
 /**
@@ -85,9 +74,9 @@ void zynq_slcr_cpu_start(int cpu)
  */
 void zynq_slcr_cpu_stop(int cpu)
 {
-        /* stop CLK and reset CPUn */
-        writel((SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu,
-               zynq_slcr_base + SLCR_A9_CPU_RST_CTRL);
+        u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+        reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;
+        writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
 }
 
 /**
@@ -113,7 +102,7 @@ int __init zynq_slcr_init(void)
         }
 
         /* unlock the SLCR so that registers can be changed */
-        writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK);
+        writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);
 
         pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
 
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index a5b5ff6e68d2..7dfba937d8fc 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -25,7 +25,6 @@ config PLAT_S5P
         select S5P_GPIO_DRVSTR
         select SAMSUNG_CLKSRC if !COMMON_CLK
         select SAMSUNG_GPIOLIB_4BIT
-        select SAMSUNG_IRQ_VIC_TIMER
         help
           Base platform code for Samsung's S5P series SoC.
 
@@ -79,14 +78,6 @@ config SAMSUNG_ATAGS
 
 if SAMSUNG_ATAGS
 
-# timer options
-
-config SAMSUNG_HRT
-        bool
-        select SAMSUNG_DEV_PWM
-        help
-          Use the High Resolution timer support
-
 # clock options
 
 config SAMSUNG_CLOCK
@@ -106,11 +97,6 @@ config S5P_CLOCK
 
 # options for IRQ support
 
-config SAMSUNG_IRQ_VIC_TIMER
-       bool
-       help
-         Internal configuration to build the VIC timer interrupt code.
-
 config S5P_IRQ
         def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
         help
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 199bbe304d02..498c7c23e9f4 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -12,15 +12,12 @@ obj-				:=
 # Objects we always build independent of SoC choice
 
 obj-y                           += init.o cpu.o
-obj-$(CONFIG_SAMSUNG_HRT)       += samsung-time.o
 
 obj-$(CONFIG_SAMSUNG_CLOCK)     += clock.o
-obj-$(CONFIG_SAMSUNG_CLOCK)     += pwm-clock.o
 
 obj-$(CONFIG_SAMSUNG_CLKSRC)    += clock-clksrc.o
 obj-$(CONFIG_S5P_CLOCK)         += s5p-clock.o
 
-obj-$(CONFIG_SAMSUNG_IRQ_VIC_TIMER) += irq-vic-timer.o
 obj-$(CONFIG_S5P_IRQ)           += s5p-irq.o
 obj-$(CONFIG_S5P_EXT_INT)       += s5p-irq-eint.o
 obj-$(CONFIG_S5P_GPIO_INT)      += s5p-irq-gpioint.o
diff --git a/arch/arm/plat-samsung/dev-backlight.c b/arch/arm/plat-samsung/dev-backlight.c
index 5f197dcaf10c..d51f9565567c 100644
--- a/arch/arm/plat-samsung/dev-backlight.c
+++ b/arch/arm/plat-samsung/dev-backlight.c
@@ -20,13 +20,18 @@
 #include <plat/gpio-cfg.h>
 #include <plat/backlight.h>
 
+struct samsung_bl_drvdata {
+        struct platform_pwm_backlight_data plat_data;
+        struct samsung_bl_gpio_info *gpio_info;
+};
+
 static int samsung_bl_init(struct device *dev)
 {
         int ret = 0;
-        struct platform_device *timer_dev =
-                        container_of(dev->parent, struct platform_device, dev);
-        struct samsung_bl_gpio_info *bl_gpio_info =
-                        timer_dev->dev.platform_data;
+        struct platform_pwm_backlight_data *pdata = dev->platform_data;
+        struct samsung_bl_drvdata *drvdata = container_of(pdata,
+                                        struct samsung_bl_drvdata, plat_data);
+        struct samsung_bl_gpio_info *bl_gpio_info = drvdata->gpio_info;
 
         ret = gpio_request(bl_gpio_info->no, "Backlight");
         if (ret) {
@@ -42,10 +47,10 @@ static int samsung_bl_init(struct device *dev)
 
 static void samsung_bl_exit(struct device *dev)
 {
-        struct platform_device *timer_dev =
-                        container_of(dev->parent, struct platform_device, dev);
-        struct samsung_bl_gpio_info *bl_gpio_info =
-                        timer_dev->dev.platform_data;
+        struct platform_pwm_backlight_data *pdata = dev->platform_data;
+        struct samsung_bl_drvdata *drvdata = container_of(pdata,
+                                        struct samsung_bl_drvdata, plat_data);
+        struct samsung_bl_gpio_info *bl_gpio_info = drvdata->gpio_info;
 
         s3c_gpio_cfgpin(bl_gpio_info->no, S3C_GPIO_OUTPUT);
         gpio_free(bl_gpio_info->no);
@@ -60,12 +65,14 @@ static void samsung_bl_exit(struct device *dev)
  * for their specific boards
  */
 
-static struct platform_pwm_backlight_data samsung_dfl_bl_data __initdata = {
-        .max_brightness = 255,
-        .dft_brightness = 255,
-        .pwm_period_ns  = 78770,
-        .init           = samsung_bl_init,
-        .exit           = samsung_bl_exit,
+static struct samsung_bl_drvdata samsung_dfl_bl_data __initdata = {
+        .plat_data = {
+                .max_brightness = 255,
+                .dft_brightness = 255,
+                .pwm_period_ns  = 78770,
+                .init           = samsung_bl_init,
+                .exit           = samsung_bl_exit,
+        },
 };
 
 static struct platform_device samsung_dfl_bl_device __initdata = {
@@ -82,6 +89,7 @@ void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info,
 {
         int ret = 0;
         struct platform_device *samsung_bl_device;
+        struct samsung_bl_drvdata *samsung_bl_drvdata;
         struct platform_pwm_backlight_data *samsung_bl_data;
 
         samsung_bl_device = kmemdup(&samsung_dfl_bl_device,
@@ -91,17 +99,19 @@ void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info,
                 return;
         }
 
-        samsung_bl_data = s3c_set_platdata(&samsung_dfl_bl_data,
-                sizeof(struct platform_pwm_backlight_data), samsung_bl_device);
-        if (!samsung_bl_data) {
+        samsung_bl_drvdata = kmemdup(&samsung_dfl_bl_data,
+                                sizeof(samsung_dfl_bl_data), GFP_KERNEL);
+        if (!samsung_bl_drvdata) {
                 printk(KERN_ERR "%s: no memory for platform dev\n", __func__);
                 goto err_data;
         }
+        samsung_bl_device->dev.platform_data = &samsung_bl_drvdata->plat_data;
+        samsung_bl_drvdata->gpio_info = gpio_info;
+        samsung_bl_data = &samsung_bl_drvdata->plat_data;
 
         /* Copy board specific data provided by user */
         samsung_bl_data->pwm_id = bl_data->pwm_id;
-        samsung_bl_device->dev.parent =
-                        &s3c_device_timer[samsung_bl_data->pwm_id].dev;
+        samsung_bl_device->dev.parent = &samsung_device_pwm.dev;
 
         if (bl_data->max_brightness)
                 samsung_bl_data->max_brightness = bl_data->max_brightness;
@@ -122,17 +132,6 @@ void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info,
         if (bl_data->check_fb)
                 samsung_bl_data->check_fb = bl_data->check_fb;
 
-        /* Keep the GPIO info for future use */
-        s3c_device_timer[samsung_bl_data->pwm_id].dev.platform_data = gpio_info;
-
-        /* Register the specific PWM timer dev for Backlight control */
-        ret = platform_device_register(
-                        &s3c_device_timer[samsung_bl_data->pwm_id]);
-        if (ret) {
-                printk(KERN_ERR "failed to register pwm timer for backlight: %d\n", ret);
-                goto err_plat_reg1;
-        }
-
         /* Register the Backlight dev */
         ret = platform_device_register(samsung_bl_device);
         if (ret) {
@@ -143,8 +142,6 @@ void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info,
         return;
 
 err_plat_reg2:
-        platform_device_unregister(&s3c_device_timer[samsung_bl_data->pwm_id]);
-err_plat_reg1:
         kfree(samsung_bl_data);
 err_data:
         kfree(samsung_bl_device);
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 0f9c3f431a5f..8ce0ac007eb9 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -58,6 +58,7 @@
 #include <plat/keypad.h>
 #include <linux/platform_data/mmc-s3cmci.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
+#include <plat/pwm-core.h>
 #include <plat/sdhci.h>
 #include <linux/platform_data/touchscreen-s3c2410.h>
 #include <linux/platform_data/usb-s3c2410_udc.h>
@@ -1097,36 +1098,21 @@ arch_initcall(s5p_pmu_init);
 /* PWM Timer */
 
 #ifdef CONFIG_SAMSUNG_DEV_PWM
+static struct resource samsung_pwm_resource[] = {
+        DEFINE_RES_MEM(SAMSUNG_PA_TIMER, SZ_4K),
+};
 
-#define TIMER_RESOURCE_SIZE (1)
-
-#define TIMER_RESOURCE(_tmr, _irq)                      \
-        (struct resource [TIMER_RESOURCE_SIZE]) {       \
-                [0] = {                                 \
-                        .start  = _irq,                 \
-                        .end    = _irq,                 \
-                        .flags  = IORESOURCE_IRQ        \
-                }                                       \
-        }
-
-#define DEFINE_S3C_TIMER(_tmr_no, _irq)                 \
-        .name           = "s3c24xx-pwm",                \
-        .id             = _tmr_no,                      \
-        .num_resources  = TIMER_RESOURCE_SIZE,          \
-        .resource       = TIMER_RESOURCE(_tmr_no, _irq),        \
-
-/*
- * since we already have an static mapping for the timer,
- * we do not bother setting any IO resource for the base.
- */
-
-struct platform_device s3c_device_timer[] = {
-        [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) },
-        [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) },
-        [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) },
-        [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) },
-        [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) },
+struct platform_device samsung_device_pwm = {
+        .name           = "samsung-pwm",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(samsung_pwm_resource),
+        .resource       = samsung_pwm_resource,
 };
+
+void __init samsung_pwm_set_platdata(struct samsung_pwm_variant *pd)
+{
+        samsung_device_pwm.dev.platform_data = pd;
+}
 #endif /* CONFIG_SAMSUNG_DEV_PWM */
 
 /* RTC */
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index df45d6edc98d..63239f409807 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -145,10 +145,6 @@ extern int s3c2443_clkcon_enable_s(struct clk *clk, int enable);
 
 extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable);
 
-/* Init for pwm clock code */
-
-extern void s3c_pwmclk_init(void);
-
 /* Global watchdog clock used by arch_wtd_reset() callback */
 
 extern struct clk *s3c2410_wdtclk;
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 87d501ff3328..0dc4ac4909b0 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -134,6 +134,7 @@ extern struct platform_device exynos4_device_spdif;
 
 extern struct platform_device samsung_asoc_idma;
 extern struct platform_device samsung_device_keypad;
+extern struct platform_device samsung_device_pwm;
 
 /* s3c2440 specific devices */
 
diff --git a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h
deleted file mode 100644
index 5b9c42fd32d7..000000000000
--- a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* arch/arm/plat-samsung/include/plat/irq-vic-timer.h
- *
- * Copyright (c) 2010 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for Samsung SoC IRQ VIC timer
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-extern void s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq);
diff --git a/arch/arm/plat-samsung/include/plat/irqs.h b/arch/arm/plat-samsung/include/plat/irqs.h
index df46b776976a..039001c0ef05 100644
--- a/arch/arm/plat-samsung/include/plat/irqs.h
+++ b/arch/arm/plat-samsung/include/plat/irqs.h
@@ -44,15 +44,6 @@
 #define S5P_IRQ_VIC2(x)         (S5P_VIC2_BASE + (x))
 #define S5P_IRQ_VIC3(x)         (S5P_VIC3_BASE + (x))
 
-#define S5P_TIMER_IRQ(x)        (IRQ_TIMER_BASE + (x))
-
-#define IRQ_TIMER0              S5P_TIMER_IRQ(0)
-#define IRQ_TIMER1              S5P_TIMER_IRQ(1)
-#define IRQ_TIMER2              S5P_TIMER_IRQ(2)
-#define IRQ_TIMER3              S5P_TIMER_IRQ(3)
-#define IRQ_TIMER4              S5P_TIMER_IRQ(4)
-#define IRQ_TIMER_COUNT         (5)
-
 #define IRQ_EINT(x)             ((x) < 16 ? ((x) + S5P_EINT_BASE1) \
                                         : ((x) - 16 + S5P_EINT_BASE2))
 
diff --git a/arch/arm/plat-samsung/include/plat/pwm-clock.h b/arch/arm/plat-samsung/include/plat/pwm-clock.h
deleted file mode 100644
index bf6a60eb6237..000000000000
--- a/arch/arm/plat-samsung/include/plat/pwm-clock.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/pwm-clock.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * SAMSUNG - pwm clock and timer support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_PLAT_PWM_CLOCK_H
-#define __ASM_PLAT_PWM_CLOCK_H __FILE__
-
-/**
- * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
- * @tcfg: The timer TCFG1 register bits shifted down to 0.
- *
- * Return true if the given configuration from TCFG1 is a TCLK instead
- * any of the TDIV clocks.
- */
-static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
-{
-        if (soc_is_s3c24xx())
-                return tcfg == S3C2410_TCFG1_MUX_TCLK;
-        else if (soc_is_s3c64xx() || soc_is_s5pc100())
-                return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
-        else if (soc_is_s5p6440() || soc_is_s5p6450())
-                return 0;
-        else
-                return tcfg == S3C64XX_TCFG1_MUX_TCLK;
-}
-
-/**
- * tcfg_to_divisor() - convert tcfg1 setting to a divisor
- * @tcfg1: The tcfg1 setting, shifted down.
- *
- * Get the divisor value for the given tcfg1 setting. We assume the
- * caller has already checked to see if this is not a TCLK source.
- */
-static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
-{
-        if (soc_is_s3c24xx())
-                return 1 << (tcfg1 + 1);
-        else
-                return 1 << tcfg1;
-}
-
-/**
- * pwm_tdiv_has_div1() - does the tdiv setting have a /1
- *
- * Return true if we have a /1 in the tdiv setting.
- */
-static inline unsigned int pwm_tdiv_has_div1(void)
-{
-        if (soc_is_s3c24xx())
-                return 0;
-        else
-                return 1;
-}
-
-/**
- * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
- * @div: The divisor to calculate the bit information for.
- *
- * Turn a divisor into the necessary bit field for TCFG1.
- */
-static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
-{
-        if (soc_is_s3c24xx())
-                return ilog2(div) - 1;
-        else
-                return ilog2(div);
-}
-#endif /* __ASM_PLAT_PWM_CLOCK_H */
diff --git a/arch/arm/plat-samsung/include/plat/pwm-core.h b/arch/arm/plat-samsung/include/plat/pwm-core.h
new file mode 100644
index 000000000000..5bff1facb672
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/pwm-core.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2013 Tomasz Figa <tomasz.figa@gmail.com>
+ *
+ * Samsung PWM controller platform data helpers.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_PWM_CORE_H
+#define __ASM_ARCH_PWM_CORE_H __FILE__
+
+#include <clocksource/samsung_pwm.h>
+
+#ifdef CONFIG_SAMSUNG_DEV_PWM
+extern void samsung_pwm_set_platdata(struct samsung_pwm_variant *pd);
+#else
+static inline void samsung_pwm_set_platdata(struct samsung_pwm_variant *pd) { }
+#endif
+
+#endif /* __ASM_ARCH_PWM_CORE_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-timer.h b/arch/arm/plat-samsung/include/plat/regs-timer.h
deleted file mode 100644
index d097d92f8cc7..000000000000
--- a/arch/arm/plat-samsung/include/plat/regs-timer.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-timer.h
- *
- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 Timer configuration
-*/
-
-#ifndef __ASM_ARCH_REGS_TIMER_H
-#define __ASM_ARCH_REGS_TIMER_H
-
-#define S3C_TIMERREG(x) (S3C_VA_TIMER + (x))
-#define S3C_TIMERREG2(tmr,reg) S3C_TIMERREG((reg)+0x0c+((tmr)*0x0c))
-
-#define S3C2410_TCFG0         S3C_TIMERREG(0x00)
-#define S3C2410_TCFG1         S3C_TIMERREG(0x04)
-#define S3C2410_TCON          S3C_TIMERREG(0x08)
-
-#define S3C64XX_TINT_CSTAT    S3C_TIMERREG(0x44)
-
-#define S3C2410_TCFG_PRESCALER0_MASK (255<<0)
-#define S3C2410_TCFG_PRESCALER1_MASK (255<<8)
-#define S3C2410_TCFG_PRESCALER1_SHIFT (8)
-#define S3C2410_TCFG_DEADZONE_MASK   (255<<16)
-#define S3C2410_TCFG_DEADZONE_SHIFT  (16)
-
-#define S3C2410_TCFG1_MUX4_DIV2   (0<<16)
-#define S3C2410_TCFG1_MUX4_DIV4   (1<<16)
-#define S3C2410_TCFG1_MUX4_DIV8   (2<<16)
-#define S3C2410_TCFG1_MUX4_DIV16  (3<<16)
-#define S3C2410_TCFG1_MUX4_TCLK1  (4<<16)
-#define S3C2410_TCFG1_MUX4_MASK   (15<<16)
-#define S3C2410_TCFG1_MUX4_SHIFT  (16)
-
-#define S3C2410_TCFG1_MUX3_DIV2   (0<<12)
-#define S3C2410_TCFG1_MUX3_DIV4   (1<<12)
-#define S3C2410_TCFG1_MUX3_DIV8   (2<<12)
-#define S3C2410_TCFG1_MUX3_DIV16  (3<<12)
-#define S3C2410_TCFG1_MUX3_TCLK1  (4<<12)
-#define S3C2410_TCFG1_MUX3_MASK   (15<<12)
-
-
-#define S3C2410_TCFG1_MUX2_DIV2   (0<<8)
-#define S3C2410_TCFG1_MUX2_DIV4   (1<<8)
-#define S3C2410_TCFG1_MUX2_DIV8   (2<<8)
-#define S3C2410_TCFG1_MUX2_DIV16  (3<<8)
-#define S3C2410_TCFG1_MUX2_TCLK1  (4<<8)
-#define S3C2410_TCFG1_MUX2_MASK   (15<<8)
-
-
-#define S3C2410_TCFG1_MUX1_DIV2   (0<<4)
-#define S3C2410_TCFG1_MUX1_DIV4   (1<<4)
-#define S3C2410_TCFG1_MUX1_DIV8   (2<<4)
-#define S3C2410_TCFG1_MUX1_DIV16  (3<<4)
-#define S3C2410_TCFG1_MUX1_TCLK0  (4<<4)
-#define S3C2410_TCFG1_MUX1_MASK   (15<<4)
-
-#define S3C2410_TCFG1_MUX0_DIV2   (0<<0)
-#define S3C2410_TCFG1_MUX0_DIV4   (1<<0)
-#define S3C2410_TCFG1_MUX0_DIV8   (2<<0)
-#define S3C2410_TCFG1_MUX0_DIV16  (3<<0)
-#define S3C2410_TCFG1_MUX0_TCLK0  (4<<0)
-#define S3C2410_TCFG1_MUX0_MASK   (15<<0)
-
-#define S3C2410_TCFG1_MUX_DIV2    (0<<0)
-#define S3C2410_TCFG1_MUX_DIV4    (1<<0)
-#define S3C2410_TCFG1_MUX_DIV8    (2<<0)
-#define S3C2410_TCFG1_MUX_DIV16   (3<<0)
-#define S3C2410_TCFG1_MUX_TCLK    (4<<0)
-#define S3C2410_TCFG1_MUX_MASK    (15<<0)
-
-#define S3C64XX_TCFG1_MUX_DIV1    (0<<0)
-#define S3C64XX_TCFG1_MUX_DIV2    (1<<0)
-#define S3C64XX_TCFG1_MUX_DIV4    (2<<0)
-#define S3C64XX_TCFG1_MUX_DIV8    (3<<0)
-#define S3C64XX_TCFG1_MUX_DIV16   (4<<0)
-#define S3C64XX_TCFG1_MUX_TCLK    (5<<0)  /* 3 sets of TCLK */
-#define S3C64XX_TCFG1_MUX_MASK    (15<<0)
-
-#define S3C2410_TCFG1_SHIFT(x)    ((x) * 4)
-
-/* for each timer, we have an count buffer, an compare buffer and
- * an observation buffer
-*/
-
-/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */
-
-#define S3C2410_TCNTB(tmr)    S3C_TIMERREG2(tmr, 0x00)
-#define S3C2410_TCMPB(tmr)    S3C_TIMERREG2(tmr, 0x04)
-#define S3C2410_TCNTO(tmr)    S3C_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
-
-#define S3C2410_TCON_T4RELOAD     (1<<22)
-#define S3C2410_TCON_T4MANUALUPD  (1<<21)
-#define S3C2410_TCON_T4START      (1<<20)
-
-#define S3C2410_TCON_T3RELOAD     (1<<19)
-#define S3C2410_TCON_T3INVERT     (1<<18)
-#define S3C2410_TCON_T3MANUALUPD  (1<<17)
-#define S3C2410_TCON_T3START      (1<<16)
-
-#define S3C2410_TCON_T2RELOAD     (1<<15)
-#define S3C2410_TCON_T2INVERT     (1<<14)
-#define S3C2410_TCON_T2MANUALUPD  (1<<13)
-#define S3C2410_TCON_T2START      (1<<12)
-
-#define S3C2410_TCON_T1RELOAD     (1<<11)
-#define S3C2410_TCON_T1INVERT     (1<<10)
-#define S3C2410_TCON_T1MANUALUPD  (1<<9)
-#define S3C2410_TCON_T1START      (1<<8)
-
-#define S3C2410_TCON_T0DEADZONE   (1<<4)
-#define S3C2410_TCON_T0RELOAD     (1<<3)
-#define S3C2410_TCON_T0INVERT     (1<<2)
-#define S3C2410_TCON_T0MANUALUPD  (1<<1)
-#define S3C2410_TCON_T0START      (1<<0)
-
-#endif /*  __ASM_ARCH_REGS_TIMER_H */
-
-
-
diff --git a/arch/arm/plat-samsung/include/plat/samsung-time.h b/arch/arm/plat-samsung/include/plat/samsung-time.h
index 4cc99bb1f176..209464adef97 100644
--- a/arch/arm/plat-samsung/include/plat/samsung-time.h
+++ b/arch/arm/plat-samsung/include/plat/samsung-time.h
@@ -22,29 +22,6 @@ enum samsung_timer_mode {
         SAMSUNG_PWM4,
 };
 
-struct samsung_timer_source {
-        unsigned int event_id;
-        unsigned int source_id;
-};
-
-/* Be able to sleep for atleast 4 seconds (usually more) */
-#define SAMSUNG_TIMER_MIN_RANGE 4
-
-#if defined(CONFIG_ARCH_S3C24XX) || defined(CONFIG_ARCH_S5PC100)
-#define TCNT_MAX                0xffff
-#define TSCALER_DIV             25
-#define TDIV                    50
-#define TSIZE                   16
-#else
-#define TCNT_MAX                0xffffffff
-#define TSCALER_DIV             2
-#define TDIV                    2
-#define TSIZE                   32
-#endif
-
-#define NON_PERIODIC            0
-#define PERIODIC                1
-
 extern void __init samsung_set_timer_source(enum samsung_timer_mode event,
                                         enum samsung_timer_mode source);
 
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index ce1d0f785efd..bf650218b40e 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -260,44 +260,6 @@ static inline void s5pv210_default_sdhci3(void) { }
 
 #endif /* CONFIG_S5PV210_SETUP_SDHCI */
 
-/* EXYNOS4 SDHCI setup */
-#ifdef CONFIG_EXYNOS4_SETUP_SDHCI
-static inline void exynos4_default_sdhci0(void)
-{
-#ifdef CONFIG_S3C_DEV_HSMMC
-        s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio;
-#endif
-}
-
-static inline void exynos4_default_sdhci1(void)
-{
-#ifdef CONFIG_S3C_DEV_HSMMC1
-        s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio;
-#endif
-}
-
-static inline void exynos4_default_sdhci2(void)
-{
-#ifdef CONFIG_S3C_DEV_HSMMC2
-        s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio;
-#endif
-}
-
-static inline void exynos4_default_sdhci3(void)
-{
-#ifdef CONFIG_S3C_DEV_HSMMC3
-        s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio;
-#endif
-}
-
-#else
-static inline void exynos4_default_sdhci0(void) { }
-static inline void exynos4_default_sdhci1(void) { }
-static inline void exynos4_default_sdhci2(void) { }
-static inline void exynos4_default_sdhci3(void) { }
-
-#endif /* CONFIG_EXYNOS4_SETUP_SDHCI */
-
 static inline void s3c_sdhci_setname(int id, char *name)
 {
         switch (id) {
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c
deleted file mode 100644
index 0fceb4273824..000000000000
--- a/arch/arm/plat-samsung/irq-vic-timer.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/* arch/arm/plat-samsung/irq-vic-timer.c
- *      originally part of arch/arm/plat-s3c64xx/irq.c
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C64XX - Interrupt handling
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/irqchip/chained_irq.h>
-#include <linux/io.h>
-
-#include <mach/map.h>
-#include <mach/irqs.h>
-#include <plat/cpu.h>
-#include <plat/irq-vic-timer.h>
-#include <plat/regs-timer.h>
-
-static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc)
-{
-        struct irq_chip *chip = irq_get_chip(irq);
-        chained_irq_enter(chip, desc);
-        generic_handle_irq((int)desc->irq_data.handler_data);
-        chained_irq_exit(chip, desc);
-}
-
-/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
-static void s3c_irq_timer_ack(struct irq_data *d)
-{
-        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-        u32 mask = (1 << 5) << (d->irq - gc->irq_base);
-
-        irq_reg_writel(mask | gc->mask_cache, gc->reg_base);
-}
-
-/**
- * s3c_init_vic_timer_irq() - initialise timer irq chanined off VIC.\
- * @num: Number of timers to initialize
- * @timer_irq: Base IRQ number to be used for the timers.
- *
- * Register the necessary IRQ chaining and support for the timer IRQs
- * chained of the VIC.
- */
-void __init s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq)
-{
-        unsigned int pirq[5] = { IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
-                                 IRQ_TIMER3_VIC, IRQ_TIMER4_VIC };
-        struct irq_chip_generic *s3c_tgc;
-        struct irq_chip_type *ct;
-        unsigned int i;
-
-#ifdef CONFIG_ARCH_EXYNOS
-        if (soc_is_exynos5250()) {
-                pirq[0] = EXYNOS5_IRQ_TIMER0_VIC;
-                pirq[1] = EXYNOS5_IRQ_TIMER1_VIC;
-                pirq[2] = EXYNOS5_IRQ_TIMER2_VIC;
-                pirq[3] = EXYNOS5_IRQ_TIMER3_VIC;
-                pirq[4] = EXYNOS5_IRQ_TIMER4_VIC;
-        } else {
-                pirq[0] = EXYNOS4_IRQ_TIMER0_VIC;
-                pirq[1] = EXYNOS4_IRQ_TIMER1_VIC;
-                pirq[2] = EXYNOS4_IRQ_TIMER2_VIC;
-                pirq[3] = EXYNOS4_IRQ_TIMER3_VIC;
-                pirq[4] = EXYNOS4_IRQ_TIMER4_VIC;
-        }
-#endif
-        s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq,
-                                         S3C64XX_TINT_CSTAT, handle_level_irq);
-
-        if (!s3c_tgc) {
-                pr_err("%s: irq_alloc_generic_chip for IRQ %d failed\n",
-                       __func__, timer_irq);
-                return;
-        }
-
-        ct = s3c_tgc->chip_types;
-        ct->chip.irq_mask = irq_gc_mask_clr_bit;
-        ct->chip.irq_unmask = irq_gc_mask_set_bit;
-        ct->chip.irq_ack = s3c_irq_timer_ack;
-        irq_setup_generic_chip(s3c_tgc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
-                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
-        /* Clear the upper bits of the mask_cache*/
-        s3c_tgc->mask_cache &= 0x1f;
-
-        for (i = 0; i < num; i++, timer_irq++) {
-                irq_set_chained_handler(pirq[i], s3c_irq_demux_vic_timer);
-                irq_set_handler_data(pirq[i], (void *)timer_irq);
-        }
-}
diff --git a/arch/arm/plat-samsung/pwm-clock.c b/arch/arm/plat-samsung/pwm-clock.c
deleted file mode 100644
index a35ff3bcffe4..000000000000
--- a/arch/arm/plat-samsung/pwm-clock.c
+++ /dev/null
@@ -1,474 +0,0 @@
-/* linux/arch/arm/plat-s3c24xx/pwm-clock.c
- *
- * Copyright (c) 2007 Simtec Electronics
- * Copyright (c) 2007, 2008 Ben Dooks
- *      Ben Dooks <ben-linux@fluff.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License.
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/log2.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <asm/irq.h>
-
-#include <plat/clock.h>
-#include <plat/cpu.h>
-
-#include <plat/regs-timer.h>
-#include <plat/pwm-clock.h>
-
-/* Each of the timers 0 through 5 go through the following
- * clock tree, with the inputs depending on the timers.
- *
- * pclk ---- [ prescaler 0 ] -+---> timer 0
- *                            +---> timer 1
- *
- * pclk ---- [ prescaler 1 ] -+---> timer 2
- *                            +---> timer 3
- *                            \---> timer 4
- *
- * Which are fed into the timers as so:
- *
- * prescaled 0 ---- [ div 2,4,8,16 ] ---\
- *                                     [mux] -> timer 0
- * tclk 0 ------------------------------/
- *
- * prescaled 0 ---- [ div 2,4,8,16 ] ---\
- *                                     [mux] -> timer 1
- * tclk 0 ------------------------------/
- *
- *
- * prescaled 1 ---- [ div 2,4,8,16 ] ---\
- *                                     [mux] -> timer 2
- * tclk 1 ------------------------------/
- *
- * prescaled 1 ---- [ div 2,4,8,16 ] ---\
- *                                     [mux] -> timer 3
- * tclk 1 ------------------------------/
- *
- * prescaled 1 ---- [ div 2,4,8, 16 ] --\
- *                                     [mux] -> timer 4
- * tclk 1 ------------------------------/
- *
- * Since the mux and the divider are tied together in the
- * same register space, it is impossible to set the parent
- * and the rate at the same time. To avoid this, we add an
- * intermediate 'prescaled-and-divided' clock to select
- * as the parent for the timer input clock called tdiv.
- *
- * prescaled clk --> pwm-tdiv ---\
- *                             [ mux ] --> timer X
- * tclk -------------------------/
-*/
-
-static struct clk clk_timer_scaler[];
-
-static unsigned long clk_pwm_scaler_get_rate(struct clk *clk)
-{
-        unsigned long tcfg0 = __raw_readl(S3C2410_TCFG0);
-
-        if (clk == &clk_timer_scaler[1]) {
-                tcfg0 &= S3C2410_TCFG_PRESCALER1_MASK;
-                tcfg0 >>= S3C2410_TCFG_PRESCALER1_SHIFT;
-        } else {
-                tcfg0 &= S3C2410_TCFG_PRESCALER0_MASK;
-        }
-
-        return clk_get_rate(clk->parent) / (tcfg0 + 1);
-}
-
-static unsigned long clk_pwm_scaler_round_rate(struct clk *clk,
-                                               unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long divisor = parent_rate / rate;
-
-        if (divisor > 256)
-                divisor = 256;
-        else if (divisor < 2)
-                divisor = 2;
-
-        return parent_rate / divisor;
-}
-
-static int clk_pwm_scaler_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long round = clk_pwm_scaler_round_rate(clk, rate);
-        unsigned long tcfg0;
-        unsigned long divisor;
-        unsigned long flags;
-
-        divisor = clk_get_rate(clk->parent) / round;
-        divisor--;
-
-        local_irq_save(flags);
-        tcfg0 = __raw_readl(S3C2410_TCFG0);
-
-        if (clk == &clk_timer_scaler[1]) {
-                tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
-                tcfg0 |= divisor << S3C2410_TCFG_PRESCALER1_SHIFT;
-        } else {
-                tcfg0 &= ~S3C2410_TCFG_PRESCALER0_MASK;
-                tcfg0 |= divisor;
-        }
-
-        __raw_writel(tcfg0, S3C2410_TCFG0);
-        local_irq_restore(flags);
-
-        return 0;
-}
-
-static struct clk_ops clk_pwm_scaler_ops = {
-        .get_rate       = clk_pwm_scaler_get_rate,
-        .set_rate       = clk_pwm_scaler_set_rate,
-        .round_rate     = clk_pwm_scaler_round_rate,
-};
-
-static struct clk clk_timer_scaler[] = {
-        [0]     = {
-                .name           = "pwm-scaler0",
-                .id             = -1,
-                .ops            = &clk_pwm_scaler_ops,
-        },
-        [1]     = {
-                .name           = "pwm-scaler1",
-                .id             = -1,
-                .ops            = &clk_pwm_scaler_ops,
-        },
-};
-
-static struct clk clk_timer_tclk[] = {
-        [0]     = {
-                .name           = "pwm-tclk0",
-                .id             = -1,
-        },
-        [1]     = {
-                .name           = "pwm-tclk1",
-                .id             = -1,
-        },
-};
-
-struct pwm_tdiv_clk {
-        struct clk      clk;
-        unsigned int    divisor;
-};
-
-static inline struct pwm_tdiv_clk *to_tdiv(struct clk *clk)
-{
-        return container_of(clk, struct pwm_tdiv_clk, clk);
-}
-
-static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk)
-{
-        unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
-        unsigned int divisor;
-
-        tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
-        tcfg1 &= S3C2410_TCFG1_MUX_MASK;
-
-        if (pwm_cfg_src_is_tclk(tcfg1))
-                divisor = to_tdiv(clk)->divisor;
-        else
-                divisor = tcfg_to_divisor(tcfg1);
-
-        return clk_get_rate(clk->parent) / divisor;
-}
-
-static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk,
-                                             unsigned long rate)
-{
-        unsigned long parent_rate;
-        unsigned long divisor;
-
-        parent_rate = clk_get_rate(clk->parent);
-        divisor = parent_rate / rate;
-
-        if (divisor <= 1 && pwm_tdiv_has_div1())
-                divisor = 1;
-        else if (divisor <= 2)
-                divisor = 2;
-        else if (divisor <= 4)
-                divisor = 4;
-        else if (divisor <= 8)
-                divisor = 8;
-        else
-                divisor = 16;
-
-        return parent_rate / divisor;
-}
-
-static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk)
-{
-        return pwm_tdiv_div_bits(divclk->divisor);
-}
-
-static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk)
-{
-        unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
-        unsigned long bits = clk_pwm_tdiv_bits(divclk);
-        unsigned long flags;
-        unsigned long shift =  S3C2410_TCFG1_SHIFT(divclk->clk.id);
-
-        local_irq_save(flags);
-
-        tcfg1 = __raw_readl(S3C2410_TCFG1);
-        tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
-        tcfg1 |= bits << shift;
-        __raw_writel(tcfg1, S3C2410_TCFG1);
-
-        local_irq_restore(flags);
-}
-
-static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate)
-{
-        struct pwm_tdiv_clk *divclk = to_tdiv(clk);
-        unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long divisor;
-
-        tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
-        tcfg1 &= S3C2410_TCFG1_MUX_MASK;
-
-        rate = clk_round_rate(clk, rate);
-        divisor = parent_rate / rate;
-
-        if (divisor > 16)
-                return -EINVAL;
-
-        divclk->divisor = divisor;
-
-        /* Update the current MUX settings if we are currently
-         * selected as the clock source for this clock. */
-
-        if (!pwm_cfg_src_is_tclk(tcfg1))
-                clk_pwm_tdiv_update(divclk);
-
-        return 0;
-}
-
-static struct clk_ops clk_tdiv_ops = {
-        .get_rate       = clk_pwm_tdiv_get_rate,
-        .set_rate       = clk_pwm_tdiv_set_rate,
-        .round_rate     = clk_pwm_tdiv_round_rate,
-};
-
-static struct pwm_tdiv_clk clk_timer_tdiv[] = {
-        [0]     = {
-                .clk    = {
-                        .name   = "pwm-tdiv",
-                        .devname        = "s3c24xx-pwm.0",
-                        .ops    = &clk_tdiv_ops,
-                        .parent = &clk_timer_scaler[0],
-                },
-        },
-        [1]     = {
-                .clk    = {
-                        .name   = "pwm-tdiv",
-                        .devname        = "s3c24xx-pwm.1",
-                        .ops    = &clk_tdiv_ops,
-                        .parent = &clk_timer_scaler[0],
-                }
-        },
-        [2]     = {
-                .clk    = {
-                        .name   = "pwm-tdiv",
-                        .devname        = "s3c24xx-pwm.2",
-                        .ops    = &clk_tdiv_ops,
-                        .parent = &clk_timer_scaler[1],
-                },
-        },
-        [3]     = {
-                .clk    = {
-                        .name   = "pwm-tdiv",
-                        .devname        = "s3c24xx-pwm.3",
-                        .ops    = &clk_tdiv_ops,
-                        .parent = &clk_timer_scaler[1],
-                },
-        },
-        [4]     = {
-                .clk    = {
-                        .name   = "pwm-tdiv",
-                        .devname        = "s3c24xx-pwm.4",
-                        .ops    = &clk_tdiv_ops,
-                        .parent = &clk_timer_scaler[1],
-                },
-        },
-};
-
-static int __init clk_pwm_tdiv_register(unsigned int id)
-{
-        struct pwm_tdiv_clk *divclk = &clk_timer_tdiv[id];
-        unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
-
-        tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
-        tcfg1 &= S3C2410_TCFG1_MUX_MASK;
-
-        divclk->clk.id = id;
-        divclk->divisor = tcfg_to_divisor(tcfg1);
-
-        return s3c24xx_register_clock(&divclk->clk);
-}
-
-static inline struct clk *s3c24xx_pwmclk_tclk(unsigned int id)
-{
-        return (id >= 2) ? &clk_timer_tclk[1] : &clk_timer_tclk[0];
-}
-
-static inline struct clk *s3c24xx_pwmclk_tdiv(unsigned int id)
-{
-        return &clk_timer_tdiv[id].clk;
-}
-
-static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent)
-{
-        unsigned int id = clk->id;
-        unsigned long tcfg1;
-        unsigned long flags;
-        unsigned long bits;
-        unsigned long shift = S3C2410_TCFG1_SHIFT(id);
-
-        unsigned long mux_tclk;
-
-        if (soc_is_s3c24xx())
-                mux_tclk = S3C2410_TCFG1_MUX_TCLK;
-        else if (soc_is_s5p6440() || soc_is_s5p6450())
-                mux_tclk = 0;
-        else
-                mux_tclk = S3C64XX_TCFG1_MUX_TCLK;
-
-        if (parent == s3c24xx_pwmclk_tclk(id))
-                bits = mux_tclk << shift;
-        else if (parent == s3c24xx_pwmclk_tdiv(id))
-                bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift;
-        else
-                return -EINVAL;
-
-        clk->parent = parent;
-
-        local_irq_save(flags);
-
-        tcfg1 = __raw_readl(S3C2410_TCFG1);
-        tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
-        __raw_writel(tcfg1 | bits, S3C2410_TCFG1);
-
-        local_irq_restore(flags);
-
-        return 0;
-}
-
-static struct clk_ops clk_tin_ops = {
-        .set_parent     = clk_pwm_tin_set_parent,
-};
-
-static struct clk clk_tin[] = {
-        [0]     = {
-                .name   = "pwm-tin",
-                .devname        = "s3c24xx-pwm.0",
-                .id     = 0,
-                .ops    = &clk_tin_ops,
-        },
-        [1]     = {
-                .name   = "pwm-tin",
-                .devname        = "s3c24xx-pwm.1",
-                .id     = 1,
-                .ops    = &clk_tin_ops,
-        },
-        [2]     = {
-                .name   = "pwm-tin",
-                .devname        = "s3c24xx-pwm.2",
-                .id     = 2,
-                .ops    = &clk_tin_ops,
-        },
-        [3]     = {
-                .name   = "pwm-tin",
-                .devname        = "s3c24xx-pwm.3",
-                .id     = 3,
-                .ops    = &clk_tin_ops,
-        },
-        [4]     = {
-                .name   = "pwm-tin",
-                .devname        = "s3c24xx-pwm.4",
-                .id     = 4,
-                .ops    = &clk_tin_ops,
-        },
-};
-
-static __init int clk_pwm_tin_register(struct clk *pwm)
-{
-        unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
-        unsigned int id = pwm->id;
-
-        struct clk *parent;
-        int ret;
-
-        ret = s3c24xx_register_clock(pwm);
-        if (ret < 0)
-                return ret;
-
-        tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
-        tcfg1 &= S3C2410_TCFG1_MUX_MASK;
-
-        if (pwm_cfg_src_is_tclk(tcfg1))
-                parent = s3c24xx_pwmclk_tclk(id);
-        else
-                parent = s3c24xx_pwmclk_tdiv(id);
-
-        return clk_set_parent(pwm, parent);
-}
-
-/**
- * s3c_pwmclk_init() - initialise pwm clocks
- *
- * Initialise and register the clocks which provide the inputs for the
- * pwm timer blocks.
- *
- * Note, this call is required by the time core, so must be called after
- * the base clocks are added and before any of the initcalls are run.
- */
-__init void s3c_pwmclk_init(void)
-{
-        struct clk *clk_timers;
-        unsigned int clk;
-        int ret;
-
-        clk_timers = clk_get(NULL, "timers");
-        if (IS_ERR(clk_timers)) {
-                printk(KERN_ERR "%s: no parent clock\n", __func__);
-                return;
-        }
-
-        for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++)
-                clk_timer_scaler[clk].parent = clk_timers;
-
-        s3c_register_clocks(clk_timer_scaler, ARRAY_SIZE(clk_timer_scaler));
-        s3c_register_clocks(clk_timer_tclk, ARRAY_SIZE(clk_timer_tclk));
-
-        for (clk = 0; clk < ARRAY_SIZE(clk_timer_tdiv); clk++) {
-                ret = clk_pwm_tdiv_register(clk);
-
-                if (ret < 0) {
-                        printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk);
-                        return;
-                }
-        }
-
-        for (clk = 0; clk < ARRAY_SIZE(clk_tin); clk++) {
-                ret = clk_pwm_tin_register(&clk_tin[clk]);
-                if (ret < 0) {
-                        printk(KERN_ERR "error adding pwm%d tin clock\n", clk);
-                        return;
-                }
-        }
-}
diff --git a/arch/arm/plat-samsung/s5p-irq.c b/arch/arm/plat-samsung/s5p-irq.c
index ff1a76011b1e..ddfaca9c79d8 100644
--- a/arch/arm/plat-samsung/s5p-irq.c
+++ b/arch/arm/plat-samsung/s5p-irq.c
@@ -17,9 +17,7 @@
 
 #include <mach/irqs.h>
 #include <mach/map.h>
-#include <plat/regs-timer.h>
 #include <plat/cpu.h>
-#include <plat/irq-vic-timer.h>
 
 void __init s5p_init_irq(u32 *vic, u32 num_vic)
 {
@@ -30,6 +28,4 @@ void __init s5p_init_irq(u32 *vic, u32 num_vic)
         for (irq = 0; irq < num_vic; irq++)
                 vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0);
 #endif
-
-        s3c_init_vic_timer_irq(5, IRQ_TIMER0);
 }
diff --git a/arch/arm/plat-samsung/samsung-time.c b/arch/arm/plat-samsung/samsung-time.c
deleted file mode 100644
index 2957075ca836..000000000000
--- a/arch/arm/plat-samsung/samsung-time.c
+++ /dev/null
@@ -1,394 +0,0 @@
-/*
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * samsung - Common hr-timer support (s3c and s5p)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/clockchips.h>
-#include <linux/platform_device.h>
-#include <linux/sched_clock.h>
-
-#include <asm/smp_twd.h>
-#include <asm/mach/time.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <mach/map.h>
-#include <plat/devs.h>
-#include <plat/regs-timer.h>
-#include <plat/samsung-time.h>
-
-static struct clk *tin_event;
-static struct clk *tin_source;
-static struct clk *tdiv_event;
-static struct clk *tdiv_source;
-static struct clk *timerclk;
-static struct samsung_timer_source timer_source;
-static unsigned long clock_count_per_tick;
-static void samsung_timer_resume(void);
-
-static void samsung_time_stop(enum samsung_timer_mode mode)
-{
-        unsigned long tcon;
-
-        tcon = __raw_readl(S3C2410_TCON);
-
-        switch (mode) {
-        case SAMSUNG_PWM0:
-                tcon &= ~S3C2410_TCON_T0START;
-                break;
-
-        case SAMSUNG_PWM1:
-                tcon &= ~S3C2410_TCON_T1START;
-                break;
-
-        case SAMSUNG_PWM2:
-                tcon &= ~S3C2410_TCON_T2START;
-                break;
-
-        case SAMSUNG_PWM3:
-                tcon &= ~S3C2410_TCON_T3START;
-                break;
-
-        case SAMSUNG_PWM4:
-                tcon &= ~S3C2410_TCON_T4START;
-                break;
-
-        default:
-                printk(KERN_ERR "Invalid Timer %d\n", mode);
-                break;
-        }
-        __raw_writel(tcon, S3C2410_TCON);
-}
-
-static void samsung_time_setup(enum samsung_timer_mode mode, unsigned long tcnt)
-{
-        unsigned long tcon;
-
-        tcon = __raw_readl(S3C2410_TCON);
-
-        tcnt--;
-
-        switch (mode) {
-        case SAMSUNG_PWM0:
-                tcon &= ~(0x0f << 0);
-                tcon |= S3C2410_TCON_T0MANUALUPD;
-                break;
-
-        case SAMSUNG_PWM1:
-                tcon &= ~(0x0f << 8);
-                tcon |= S3C2410_TCON_T1MANUALUPD;
-                break;
-
-        case SAMSUNG_PWM2:
-                tcon &= ~(0x0f << 12);
-                tcon |= S3C2410_TCON_T2MANUALUPD;
-                break;
-
-        case SAMSUNG_PWM3:
-                tcon &= ~(0x0f << 16);
-                tcon |= S3C2410_TCON_T3MANUALUPD;
-                break;
-
-        case SAMSUNG_PWM4:
-                tcon &= ~(0x07 << 20);
-                tcon |= S3C2410_TCON_T4MANUALUPD;
-                break;
-
-        default:
-                printk(KERN_ERR "Invalid Timer %d\n", mode);
-                break;
-        }
-
-        __raw_writel(tcnt, S3C2410_TCNTB(mode));
-        __raw_writel(tcnt, S3C2410_TCMPB(mode));
-        __raw_writel(tcon, S3C2410_TCON);
-}
-
-static void samsung_time_start(enum samsung_timer_mode mode, bool periodic)
-{
-        unsigned long tcon;
-
-        tcon  = __raw_readl(S3C2410_TCON);
-
-        switch (mode) {
-        case SAMSUNG_PWM0:
-                tcon |= S3C2410_TCON_T0START;
-                tcon &= ~S3C2410_TCON_T0MANUALUPD;
-
-                if (periodic)
-                        tcon |= S3C2410_TCON_T0RELOAD;
-                else
-                        tcon &= ~S3C2410_TCON_T0RELOAD;
-                break;
-
-        case SAMSUNG_PWM1:
-                tcon |= S3C2410_TCON_T1START;
-                tcon &= ~S3C2410_TCON_T1MANUALUPD;
-
-                if (periodic)
-                        tcon |= S3C2410_TCON_T1RELOAD;
-                else
-                        tcon &= ~S3C2410_TCON_T1RELOAD;
-                break;
-
-        case SAMSUNG_PWM2:
-                tcon |= S3C2410_TCON_T2START;
-                tcon &= ~S3C2410_TCON_T2MANUALUPD;
-
-                if (periodic)
-                        tcon |= S3C2410_TCON_T2RELOAD;
-                else
-                        tcon &= ~S3C2410_TCON_T2RELOAD;
-                break;
-
-        case SAMSUNG_PWM3:
-                tcon |= S3C2410_TCON_T3START;
-                tcon &= ~S3C2410_TCON_T3MANUALUPD;
-
-                if (periodic)
-                        tcon |= S3C2410_TCON_T3RELOAD;
-                else
-                        tcon &= ~S3C2410_TCON_T3RELOAD;
-                break;
-
-        case SAMSUNG_PWM4:
-                tcon |= S3C2410_TCON_T4START;
-                tcon &= ~S3C2410_TCON_T4MANUALUPD;
-
-                if (periodic)
-                        tcon |= S3C2410_TCON_T4RELOAD;
-                else
-                        tcon &= ~S3C2410_TCON_T4RELOAD;
-                break;
-
-        default:
-                printk(KERN_ERR "Invalid Timer %d\n", mode);
-                break;
-        }
-        __raw_writel(tcon, S3C2410_TCON);
-}
-
-static int samsung_set_next_event(unsigned long cycles,
-                                struct clock_event_device *evt)
-{
-        samsung_time_setup(timer_source.event_id, cycles);
-        samsung_time_start(timer_source.event_id, NON_PERIODIC);
-
-        return 0;
-}
-
-static void samsung_set_mode(enum clock_event_mode mode,
-                                struct clock_event_device *evt)
-{
-        samsung_time_stop(timer_source.event_id);
-
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                samsung_time_setup(timer_source.event_id, clock_count_per_tick);
-                samsung_time_start(timer_source.event_id, PERIODIC);
-                break;
-
-        case CLOCK_EVT_MODE_ONESHOT:
-                break;
-
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_SHUTDOWN:
-                break;
-
-        case CLOCK_EVT_MODE_RESUME:
-                samsung_timer_resume();
-                break;
-        }
-}
-
-static void samsung_timer_resume(void)
-{
-        /* event timer restart */
-        samsung_time_setup(timer_source.event_id, clock_count_per_tick);
-        samsung_time_start(timer_source.event_id, PERIODIC);
-
-        /* source timer restart */
-        samsung_time_setup(timer_source.source_id, TCNT_MAX);
-        samsung_time_start(timer_source.source_id, PERIODIC);
-}
-
-void __init samsung_set_timer_source(enum samsung_timer_mode event,
-                                 enum samsung_timer_mode source)
-{
-        s3c_device_timer[event].dev.bus = &platform_bus_type;
-        s3c_device_timer[source].dev.bus = &platform_bus_type;
-
-        timer_source.event_id = event;
-        timer_source.source_id = source;
-}
-
-static struct clock_event_device time_event_device = {
-        .name           = "samsung_event_timer",
-        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        .rating         = 200,
-        .set_next_event = samsung_set_next_event,
-        .set_mode       = samsung_set_mode,
-};
-
-static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
-{
-        struct clock_event_device *evt = dev_id;
-
-        evt->event_handler(evt);
-
-        return IRQ_HANDLED;
-}
-
-static struct irqaction samsung_clock_event_irq = {
-        .name           = "samsung_time_irq",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = samsung_clock_event_isr,
-        .dev_id         = &time_event_device,
-};
-
-static void __init samsung_clockevent_init(void)
-{
-        unsigned long pclk;
-        unsigned long clock_rate;
-        unsigned int irq_number;
-        struct clk *tscaler;
-
-        pclk = clk_get_rate(timerclk);
-
-        tscaler = clk_get_parent(tdiv_event);
-
-        clk_set_rate(tscaler, pclk / TSCALER_DIV);
-        clk_set_rate(tdiv_event, pclk / TDIV);
-        clk_set_parent(tin_event, tdiv_event);
-
-        clock_rate = clk_get_rate(tin_event);
-        clock_count_per_tick = clock_rate / HZ;
-
-        time_event_device.cpumask = cpumask_of(0);
-        clockevents_config_and_register(&time_event_device, clock_rate, 1, -1);
-
-        irq_number = timer_source.event_id + IRQ_TIMER0;
-        setup_irq(irq_number, &samsung_clock_event_irq);
-}
-
-static void __iomem *samsung_timer_reg(void)
-{
-        unsigned long offset = 0;
-
-        switch (timer_source.source_id) {
-        case SAMSUNG_PWM0:
-        case SAMSUNG_PWM1:
-        case SAMSUNG_PWM2:
-        case SAMSUNG_PWM3:
-                offset = (timer_source.source_id * 0x0c) + 0x14;
-                break;
-
-        case SAMSUNG_PWM4:
-                offset = 0x40;
-                break;
-
-        default:
-                printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id);
-                return NULL;
-        }
-
-        return S3C_TIMERREG(offset);
-}
-
-/*
- * Override the global weak sched_clock symbol with this
- * local implementation which uses the clocksource to get some
- * better resolution when scheduling the kernel. We accept that
- * this wraps around for now, since it is just a relative time
- * stamp. (Inspired by U300 implementation.)
- */
-static u32 notrace samsung_read_sched_clock(void)
-{
-        void __iomem *reg = samsung_timer_reg();
-
-        if (!reg)
-                return 0;
-
-        return ~__raw_readl(reg);
-}
-
-static void __init samsung_clocksource_init(void)
-{
-        unsigned long pclk;
-        unsigned long clock_rate;
-
-        pclk = clk_get_rate(timerclk);
-
-        clk_set_rate(tdiv_source, pclk / TDIV);
-        clk_set_parent(tin_source, tdiv_source);
-
-        clock_rate = clk_get_rate(tin_source);
-
-        samsung_time_setup(timer_source.source_id, TCNT_MAX);
-        samsung_time_start(timer_source.source_id, PERIODIC);
-
-        setup_sched_clock(samsung_read_sched_clock, TSIZE, clock_rate);
-
-        if (clocksource_mmio_init(samsung_timer_reg(), "samsung_clocksource_timer",
-                        clock_rate, 250, TSIZE, clocksource_mmio_readl_down))
-                panic("samsung_clocksource_timer: can't register clocksource\n");
-}
-
-static void __init samsung_timer_resources(void)
-{
-
-        unsigned long event_id = timer_source.event_id;
-        unsigned long source_id = timer_source.source_id;
-        char devname[15];
-
-        timerclk = clk_get(NULL, "timers");
-        if (IS_ERR(timerclk))
-                panic("failed to get timers clock for timer");
-
-        clk_enable(timerclk);
-
-        sprintf(devname, "s3c24xx-pwm.%lu", event_id);
-        s3c_device_timer[event_id].id = event_id;
-        s3c_device_timer[event_id].dev.init_name = devname;
-
-        tin_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tin");
-        if (IS_ERR(tin_event))
-                panic("failed to get pwm-tin clock for event timer");
-
-        tdiv_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tdiv");
-        if (IS_ERR(tdiv_event))
-                panic("failed to get pwm-tdiv clock for event timer");
-
-        clk_enable(tin_event);
-
-        sprintf(devname, "s3c24xx-pwm.%lu", source_id);
-        s3c_device_timer[source_id].id = source_id;
-        s3c_device_timer[source_id].dev.init_name = devname;
-
-        tin_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tin");
-        if (IS_ERR(tin_source))
-                panic("failed to get pwm-tin clock for source timer");
-
-        tdiv_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tdiv");
-        if (IS_ERR(tdiv_source))
-                panic("failed to get pwm-tdiv clock for source timer");
-
-        clk_enable(tin_source);
-}
-
-void __init samsung_timer_init(void)
-{
-        samsung_timer_resources();
-        samsung_clockevent_init();
-        samsung_clocksource_init();
-}