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authorPaul Walmsley <paul@pwsan.com>2008-12-10 20:36:34 -0500
committerTony Lindgren <tony@atomide.com>2008-12-10 20:36:34 -0500
commit64ce2907b1966593d3b4ce5396adb17d7348637d (patch)
treeea044c1216d5b15621d69ca4bb566ffe5ff90d65 /arch/arm
parenta94b9e5a81d7f69297bb1681c5130a185e047f57 (diff)
ARM: OMAP2: skip unnecessary TLDR write during non-autoreload for gptimer
The GPTIMER TLDR register does not need to be written if the GPTIMER is not in autoreload mode. This is the usual case for dynamic tick-enabled kernels. Simulation data indicate that skipping the read that occurs as part of the write should save at least 300-320 ns for each GPTIMER1 timer reprogram. (This assumes L4-Wakeup is at 19MHz and GPTIMER write posting is enabled.) Skipping the write itself probably won't have much impact since it should be posted on the OCP interconnect. Tested on 2430SDP and 3430SDP. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Richard Woodruff <r-woodruff2@ti.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/plat-omap/dmtimer.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 595e3d5092c9..e4f0ce04ba92 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -549,14 +549,15 @@ void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
549 u32 l; 549 u32 l;
550 550
551 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 551 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
552 if (autoreload) 552 if (autoreload) {
553 l |= OMAP_TIMER_CTRL_AR; 553 l |= OMAP_TIMER_CTRL_AR;
554 else 554 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
555 } else {
555 l &= ~OMAP_TIMER_CTRL_AR; 556 l &= ~OMAP_TIMER_CTRL_AR;
557 }
556 l |= OMAP_TIMER_CTRL_ST; 558 l |= OMAP_TIMER_CTRL_ST;
557 559
558 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, load); 560 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, load);
559 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
560 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); 561 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
561} 562}
562 563