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authorOlof Johansson <olof@lixom.net>2013-04-13 02:55:05 -0400
committerOlof Johansson <olof@lixom.net>2013-04-13 02:55:05 -0400
commit567b1b0839150e8d701553cbb586365b1f2ed36c (patch)
tree5e697c8d1f65b552fdb12f9f240abcf6baf1d245 /arch/arm
parentf6940610c76e9a6dbb23cef51b64fd48877b68df (diff)
parent80f72d2d33263429ac6a50b84b2ec5fa681a5e84 (diff)
Merge tag 'imx-soc-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc2
From Shawn Guo: The imx soc changes for 3.10: * Enable anatop, well bisa and RBC for suspend to optimize the power consumption a little bit * Clock changes for TVE, LDB, PATA, SRTC support * Add System Reset Controller (SRC) support for imx5 and imx6 * Add initial imx6dl support based on imx6q code * Kconfig for cpufreq-cpu0, defconfig updates and few other changes * tag 'imx-soc-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6: (275 commits) ARM i.MX53: set CLK_SET_RATE_PARENT flag on the tve_ext_sel clock ARM i.MX53: tve_di clock is not part of the CCM, but of TVE ARM i.MX53: make tve_ext_sel propagate rate change to PLL ARM i.MX53: Remove unused tve_gate clkdev entry ARM i.MX5: Remove tve_sel clock from i.MX53 clock tree ARM: i.MX5: Add PATA and SRTC clocks ARM: imx: do not bring up unavailable cores ARM: imx: add initial imx6dl support ARM: imx1: mm: add call to mxc_device_init ARM: imx_v4_v5_defconfig: Add CONFIG_GPIO_SYSFS ARM: imx_v6_v7_defconfig: Select CONFIG_PERF_EVENTS ARM: i.MX53 Add the cko1, cko2 clock outputs. staging: drm/imx: Use SRC to reset IPU ARM i.MX6q: Add GPU, VPU, IPU, and OpenVG resets to System Reset Controller (SRC) ARM: imx: do not use regmap_read for ANADIG_DIGPROG ARM i.MX6q: set the LDB serial clock parent to the video PLL ARM i.MX6q: Add audio/video PLL post dividers for i.MX6q rev 1.1 ARM i.MX6q: fix ldb di divider and selector clocks ARM i.MX53: fix ldb di divider and selector clocks ARM i.MX: Add imx_clk_divider_flags and imx_clk_mux_flags ... Signed-off-by: Olof Johansson <olof@lixom.net> Trivial change/change conflict in arch/arm/mach-imx/mach-imx6q.c resolved.
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig21
-rw-r--r--arch/arm/Kconfig.debug4
-rw-r--r--arch/arm/boot/dts/armada-370-mirabox.dts2
-rw-r--r--arch/arm/boot/dts/armada-370.dtsi6
-rw-r--r--arch/arm/boot/dts/dbx5x0.dtsi4
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi1
-rw-r--r--arch/arm/boot/dts/kirkwood-goflexnet.dts1
-rw-r--r--arch/arm/boot/dts/orion5x.dtsi9
-rw-r--r--arch/arm/configs/imx_v4_v5_defconfig1
-rw-r--r--arch/arm/configs/imx_v6_v7_defconfig1
-rw-r--r--arch/arm/include/asm/delay.h2
-rw-r--r--arch/arm/include/asm/highmem.h7
-rw-r--r--arch/arm/include/asm/mmu_context.h2
-rw-r--r--arch/arm/include/asm/tlbflush.h15
-rw-r--r--arch/arm/kernel/entry-common.S12
-rw-r--r--arch/arm/kernel/head.S2
-rw-r--r--arch/arm/kernel/hw_breakpoint.c6
-rw-r--r--arch/arm/kernel/setup.c24
-rw-r--r--arch/arm/kernel/smp.c3
-rw-r--r--arch/arm/kernel/smp_tlb.c66
-rw-r--r--arch/arm/kvm/vgic.c35
-rw-r--r--arch/arm/lib/delay.c8
-rw-r--r--arch/arm/mach-cns3xxx/core.c16
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/cns3xxx.h16
-rw-r--r--arch/arm/mach-ep93xx/include/mach/uncompress.h10
-rw-r--r--arch/arm/mach-imx/Kconfig28
-rw-r--r--arch/arm/mach-imx/Makefile4
-rw-r--r--arch/arm/mach-imx/Makefile.boot35
-rw-r--r--arch/arm/mach-imx/anatop.c103
-rw-r--r--arch/arm/mach-imx/avic.c4
-rw-r--r--arch/arm/mach-imx/clk-imx27.c2
-rw-r--r--arch/arm/mach-imx/clk-imx35.c2
-rw-r--r--arch/arm/mach-imx/clk-imx51-imx53.c75
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c129
-rw-r--r--arch/arm/mach-imx/clk.h17
-rw-r--r--arch/arm/mach-imx/common.h15
-rw-r--r--arch/arm/mach-imx/cpu_op-mx51.c31
-rw-r--r--arch/arm/mach-imx/cpu_op-mx51.h14
-rw-r--r--arch/arm/mach-imx/cpufreq.c206
-rw-r--r--arch/arm/mach-imx/devices/Kconfig4
-rw-r--r--arch/arm/mach-imx/devices/Makefile1
-rw-r--r--arch/arm/mach-imx/devices/devices-common.h10
-rw-r--r--arch/arm/mach-imx/devices/platform-ahci-imx.c157
-rw-r--r--arch/arm/mach-imx/gpc.c23
-rw-r--r--arch/arm/mach-imx/hardware.h1
-rw-r--r--arch/arm/mach-imx/hotplug.c12
-rw-r--r--arch/arm/mach-imx/mach-cpuimx51sd.c5
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c74
-rw-r--r--arch/arm/mach-imx/mach-mx51_babbage.c4
-rw-r--r--arch/arm/mach-imx/mm-imx1.c2
-rw-r--r--arch/arm/mach-imx/mx6q.h31
-rw-r--r--arch/arm/mach-imx/mxc.h11
-rw-r--r--arch/arm/mach-imx/platsmp.c4
-rw-r--r--arch/arm/mach-imx/pm-imx6q.c4
-rw-r--r--arch/arm/mach-imx/src.c77
-rw-r--r--arch/arm/mach-kirkwood/guruplug-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/openrd-setup.c1
-rw-r--r--arch/arm/mach-kirkwood/rd88f6281-setup.c1
-rw-r--r--arch/arm/mach-msm/timer.c5
-rw-r--r--arch/arm/mach-mvebu/irq-armada-370-xp.c8
-rw-r--r--arch/arm/mach-omap1/clock_data.c12
-rw-r--r--arch/arm/mach-omap2/cclock44xx_data.c20
-rw-r--r--arch/arm/mach-omap2/common.h3
-rw-r--r--arch/arm/mach-omap2/io.c18
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c7
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.h9
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c7
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c6
-rw-r--r--arch/arm/mach-omap2/timer.c4
-rw-r--r--arch/arm/mach-ux500/board-mop500-sdi.c1
-rw-r--r--arch/arm/mach-ux500/board-mop500.c12
-rw-r--r--arch/arm/mach-ux500/board-mop500.h1
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c5
-rw-r--r--arch/arm/mm/cache-l2x0.c11
-rw-r--r--arch/arm/mm/context.c3
-rw-r--r--arch/arm/mm/mmu.c73
-rw-r--r--arch/arm/mm/proc-v7.S19
77 files changed, 838 insertions, 749 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 11680092e407..8d39c8ba9691 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1183,9 +1183,9 @@ config ARM_NR_BANKS
1183 default 8 1183 default 8
1184 1184
1185config IWMMXT 1185config IWMMXT
1186 bool "Enable iWMMXt support" 1186 bool "Enable iWMMXt support" if !CPU_PJ4
1187 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 1187 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1188 default y if PXA27x || PXA3xx || ARCH_MMP 1188 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1189 help 1189 help
1190 Enable support for iWMMXt context switching at run time if 1190 Enable support for iWMMXt context switching at run time if
1191 running on a CPU that supports it. 1191 running on a CPU that supports it.
@@ -1439,6 +1439,16 @@ config ARM_ERRATA_775420
1439 to deadlock. This workaround puts DSB before executing ISB if 1439 to deadlock. This workaround puts DSB before executing ISB if
1440 an abort may occur on cache maintenance. 1440 an abort may occur on cache maintenance.
1441 1441
1442config ARM_ERRATA_798181
1443 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1444 depends on CPU_V7 && SMP
1445 help
1446 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1447 adequately shooting down all use of the old entries. This
1448 option enables the Linux kernel workaround for this erratum
1449 which sends an IPI to the CPUs that are running the same ASID
1450 as the one being invalidated.
1451
1442endmenu 1452endmenu
1443 1453
1444source "arch/arm/common/Kconfig" 1454source "arch/arm/common/Kconfig"
@@ -2154,13 +2164,6 @@ if ARCH_HAS_CPUFREQ
2154 2164
2155source "drivers/cpufreq/Kconfig" 2165source "drivers/cpufreq/Kconfig"
2156 2166
2157config CPU_FREQ_IMX
2158 tristate "CPUfreq driver for i.MX CPUs"
2159 depends on ARCH_MXC && CPU_FREQ
2160 select CPU_FREQ_TABLE
2161 help
2162 This enables the CPUfreq driver for i.MX CPUs.
2163
2164config CPU_FREQ_SA1100 2167config CPU_FREQ_SA1100
2165 bool 2168 bool
2166 2169
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 9b31f4311ea2..7e911fd4dd89 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -234,11 +234,11 @@ choice
234 on i.MX53. 234 on i.MX53.
235 235
236 config DEBUG_IMX6Q_UART 236 config DEBUG_IMX6Q_UART
237 bool "i.MX6Q Debug UART" 237 bool "i.MX6Q/DL Debug UART"
238 depends on SOC_IMX6Q 238 depends on SOC_IMX6Q
239 help 239 help
240 Say Y here if you want kernel low-level debugging support 240 Say Y here if you want kernel low-level debugging support
241 on i.MX6Q. 241 on i.MX6Q/DL.
242 242
243 config DEBUG_MMP_UART2 243 config DEBUG_MMP_UART2
244 bool "Kernel low-level debugging message via MMP UART2" 244 bool "Kernel low-level debugging message via MMP UART2"
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index dd0c57dd9f30..3234875824dc 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -54,7 +54,7 @@
54 }; 54 };
55 55
56 mvsdio@d00d4000 { 56 mvsdio@d00d4000 {
57 pinctrl-0 = <&sdio_pins2>; 57 pinctrl-0 = <&sdio_pins3>;
58 pinctrl-names = "default"; 58 pinctrl-names = "default";
59 status = "okay"; 59 status = "okay";
60 /* 60 /*
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 8188d138020e..a195debb67d3 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -59,6 +59,12 @@
59 "mpp50", "mpp51", "mpp52"; 59 "mpp50", "mpp51", "mpp52";
60 marvell,function = "sd0"; 60 marvell,function = "sd0";
61 }; 61 };
62
63 sdio_pins3: sdio-pins3 {
64 marvell,pins = "mpp48", "mpp49", "mpp50",
65 "mpp51", "mpp52", "mpp53";
66 marvell,function = "sd0";
67 };
62 }; 68 };
63 69
64 gpio0: gpio@d0018100 { 70 gpio0: gpio@d0018100 {
diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 9de93096601a..aaa63d0a8096 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -191,8 +191,8 @@
191 191
192 prcmu: prcmu@80157000 { 192 prcmu: prcmu@80157000 {
193 compatible = "stericsson,db8500-prcmu"; 193 compatible = "stericsson,db8500-prcmu";
194 reg = <0x80157000 0x1000>; 194 reg = <0x80157000 0x1000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
195 reg-names = "prcmu"; 195 reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
196 interrupts = <0 47 0x4>; 196 interrupts = <0 47 0x4>;
197 #address-cells = <1>; 197 #address-cells = <1>;
198 #size-cells = <1>; 198 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 06ec460b4581..281a223591ff 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -91,6 +91,7 @@
91 compatible = "arm,cortex-a9-twd-timer"; 91 compatible = "arm,cortex-a9-twd-timer";
92 reg = <0x00a00600 0x20>; 92 reg = <0x00a00600 0x20>;
93 interrupts = <1 13 0xf01>; 93 interrupts = <1 13 0xf01>;
94 clocks = <&clks 15>;
94 }; 95 };
95 96
96 L2: l2-cache@00a02000 { 97 L2: l2-cache@00a02000 {
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
index bd83b8fc7c83..c3573be7b92c 100644
--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
@@ -77,6 +77,7 @@
77 }; 77 };
78 78
79 nand@3000000 { 79 nand@3000000 {
80 chip-delay = <40>;
80 status = "okay"; 81 status = "okay";
81 82
82 partition@0 { 83 partition@0 {
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index 8aad00f81ed9..f7bec3b1ba32 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -13,6 +13,9 @@
13 compatible = "marvell,orion5x"; 13 compatible = "marvell,orion5x";
14 interrupt-parent = <&intc>; 14 interrupt-parent = <&intc>;
15 15
16 aliases {
17 gpio0 = &gpio0;
18 };
16 intc: interrupt-controller { 19 intc: interrupt-controller {
17 compatible = "marvell,orion-intc", "marvell,intc"; 20 compatible = "marvell,orion-intc", "marvell,intc";
18 interrupt-controller; 21 interrupt-controller;
@@ -32,7 +35,9 @@
32 #gpio-cells = <2>; 35 #gpio-cells = <2>;
33 gpio-controller; 36 gpio-controller;
34 reg = <0x10100 0x40>; 37 reg = <0x10100 0x40>;
35 ngpio = <32>; 38 ngpios = <32>;
39 interrupt-controller;
40 #interrupt-cells = <2>;
36 interrupts = <6>, <7>, <8>, <9>; 41 interrupts = <6>, <7>, <8>, <9>;
37 }; 42 };
38 43
@@ -91,7 +96,7 @@
91 reg = <0x90000 0x10000>, 96 reg = <0x90000 0x10000>,
92 <0xf2200000 0x800>; 97 <0xf2200000 0x800>;
93 reg-names = "regs", "sram"; 98 reg-names = "regs", "sram";
94 interrupts = <22>; 99 interrupts = <28>;
95 status = "okay"; 100 status = "okay";
96 }; 101 };
97 }; 102 };
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index 02c657af4005..f07a847b00c9 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -109,6 +109,7 @@ CONFIG_I2C_IMX=y
109CONFIG_SPI=y 109CONFIG_SPI=y
110CONFIG_SPI_IMX=y 110CONFIG_SPI_IMX=y
111CONFIG_SPI_SPIDEV=y 111CONFIG_SPI_SPIDEV=y
112CONFIG_GPIO_SYSFS=y
112CONFIG_W1=y 113CONFIG_W1=y
113CONFIG_W1_MASTER_MXC=y 114CONFIG_W1_MASTER_MXC=y
114CONFIG_W1_SLAVE_THERM=y 115CONFIG_W1_SLAVE_THERM=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index e36b01025321..12f50c7963fd 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -9,6 +9,7 @@ CONFIG_CGROUPS=y
9CONFIG_RELAY=y 9CONFIG_RELAY=y
10CONFIG_BLK_DEV_INITRD=y 10CONFIG_BLK_DEV_INITRD=y
11CONFIG_EXPERT=y 11CONFIG_EXPERT=y
12CONFIG_PERF_EVENTS=y
12# CONFIG_SLUB_DEBUG is not set 13# CONFIG_SLUB_DEBUG is not set
13# CONFIG_COMPAT_BRK is not set 14# CONFIG_COMPAT_BRK is not set
14CONFIG_MODULES=y 15CONFIG_MODULES=y
diff --git a/arch/arm/include/asm/delay.h b/arch/arm/include/asm/delay.h
index 720799fd3a81..dff714d886d5 100644
--- a/arch/arm/include/asm/delay.h
+++ b/arch/arm/include/asm/delay.h
@@ -24,7 +24,7 @@ extern struct arm_delay_ops {
24 void (*delay)(unsigned long); 24 void (*delay)(unsigned long);
25 void (*const_udelay)(unsigned long); 25 void (*const_udelay)(unsigned long);
26 void (*udelay)(unsigned long); 26 void (*udelay)(unsigned long);
27 bool const_clock; 27 unsigned long ticks_per_jiffy;
28} arm_delay_ops; 28} arm_delay_ops;
29 29
30#define __delay(n) arm_delay_ops.delay(n) 30#define __delay(n) arm_delay_ops.delay(n)
diff --git a/arch/arm/include/asm/highmem.h b/arch/arm/include/asm/highmem.h
index 8c5e828f484d..91b99abe7a95 100644
--- a/arch/arm/include/asm/highmem.h
+++ b/arch/arm/include/asm/highmem.h
@@ -41,6 +41,13 @@ extern void kunmap_high(struct page *page);
41#endif 41#endif
42#endif 42#endif
43 43
44/*
45 * Needed to be able to broadcast the TLB invalidation for kmap.
46 */
47#ifdef CONFIG_ARM_ERRATA_798181
48#undef ARCH_NEEDS_KMAP_HIGH_GET
49#endif
50
44#ifdef ARCH_NEEDS_KMAP_HIGH_GET 51#ifdef ARCH_NEEDS_KMAP_HIGH_GET
45extern void *kmap_high_get(struct page *page); 52extern void *kmap_high_get(struct page *page);
46#else 53#else
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h
index 863a6611323c..a7b85e0d0cc1 100644
--- a/arch/arm/include/asm/mmu_context.h
+++ b/arch/arm/include/asm/mmu_context.h
@@ -27,6 +27,8 @@ void __check_vmalloc_seq(struct mm_struct *mm);
27void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk); 27void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk);
28#define init_new_context(tsk,mm) ({ atomic64_set(&mm->context.id, 0); 0; }) 28#define init_new_context(tsk,mm) ({ atomic64_set(&mm->context.id, 0); 0; })
29 29
30DECLARE_PER_CPU(atomic64_t, active_asids);
31
30#else /* !CONFIG_CPU_HAS_ASID */ 32#else /* !CONFIG_CPU_HAS_ASID */
31 33
32#ifdef CONFIG_MMU 34#ifdef CONFIG_MMU
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 4db8c8820f0d..9e9c041358ca 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -450,6 +450,21 @@ static inline void local_flush_bp_all(void)
450 isb(); 450 isb();
451} 451}
452 452
453#ifdef CONFIG_ARM_ERRATA_798181
454static inline void dummy_flush_tlb_a15_erratum(void)
455{
456 /*
457 * Dummy TLBIMVAIS. Using the unmapped address 0 and ASID 0.
458 */
459 asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0));
460 dsb();
461}
462#else
463static inline void dummy_flush_tlb_a15_erratum(void)
464{
465}
466#endif
467
453/* 468/*
454 * flush_pmd_entry 469 * flush_pmd_entry
455 * 470 *
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 3248cde504ed..fefd7f971437 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -276,7 +276,13 @@ ENDPROC(ftrace_graph_caller_old)
276 */ 276 */
277 277
278.macro mcount_enter 278.macro mcount_enter
279/*
280 * This pad compensates for the push {lr} at the call site. Note that we are
281 * unable to unwind through a function which does not otherwise save its lr.
282 */
283 UNWIND(.pad #4)
279 stmdb sp!, {r0-r3, lr} 284 stmdb sp!, {r0-r3, lr}
285 UNWIND(.save {r0-r3, lr})
280.endm 286.endm
281 287
282.macro mcount_get_lr reg 288.macro mcount_get_lr reg
@@ -289,6 +295,7 @@ ENDPROC(ftrace_graph_caller_old)
289.endm 295.endm
290 296
291ENTRY(__gnu_mcount_nc) 297ENTRY(__gnu_mcount_nc)
298UNWIND(.fnstart)
292#ifdef CONFIG_DYNAMIC_FTRACE 299#ifdef CONFIG_DYNAMIC_FTRACE
293 mov ip, lr 300 mov ip, lr
294 ldmia sp!, {lr} 301 ldmia sp!, {lr}
@@ -296,17 +303,22 @@ ENTRY(__gnu_mcount_nc)
296#else 303#else
297 __mcount 304 __mcount
298#endif 305#endif
306UNWIND(.fnend)
299ENDPROC(__gnu_mcount_nc) 307ENDPROC(__gnu_mcount_nc)
300 308
301#ifdef CONFIG_DYNAMIC_FTRACE 309#ifdef CONFIG_DYNAMIC_FTRACE
302ENTRY(ftrace_caller) 310ENTRY(ftrace_caller)
311UNWIND(.fnstart)
303 __ftrace_caller 312 __ftrace_caller
313UNWIND(.fnend)
304ENDPROC(ftrace_caller) 314ENDPROC(ftrace_caller)
305#endif 315#endif
306 316
307#ifdef CONFIG_FUNCTION_GRAPH_TRACER 317#ifdef CONFIG_FUNCTION_GRAPH_TRACER
308ENTRY(ftrace_graph_caller) 318ENTRY(ftrace_graph_caller)
319UNWIND(.fnstart)
309 __ftrace_graph_caller 320 __ftrace_graph_caller
321UNWIND(.fnend)
310ENDPROC(ftrace_graph_caller) 322ENDPROC(ftrace_graph_caller)
311#endif 323#endif
312 324
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index e0eb9a1cae77..8bac553fe213 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -267,7 +267,7 @@ __create_page_tables:
267 addne r6, r6, #1 << SECTION_SHIFT 267 addne r6, r6, #1 << SECTION_SHIFT
268 strne r6, [r3] 268 strne r6, [r3]
269 269
270#if defined(CONFIG_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8) 270#if defined(CONFIG_ARM_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8)
271 sub r4, r4, #4 @ Fixup page table pointer 271 sub r4, r4, #4 @ Fixup page table pointer
272 @ for 64-bit descriptors 272 @ for 64-bit descriptors
273#endif 273#endif
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index 96093b75ab90..5dc1aa6f0f7d 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -966,7 +966,7 @@ static void reset_ctrl_regs(void *unused)
966 } 966 }
967 967
968 if (err) { 968 if (err) {
969 pr_warning("CPU %d debug is powered down!\n", cpu); 969 pr_warn_once("CPU %d debug is powered down!\n", cpu);
970 cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu)); 970 cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
971 return; 971 return;
972 } 972 }
@@ -987,7 +987,7 @@ clear_vcr:
987 isb(); 987 isb();
988 988
989 if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) { 989 if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
990 pr_warning("CPU %d failed to disable vector catch\n", cpu); 990 pr_warn_once("CPU %d failed to disable vector catch\n", cpu);
991 return; 991 return;
992 } 992 }
993 993
@@ -1007,7 +1007,7 @@ clear_vcr:
1007 } 1007 }
1008 1008
1009 if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) { 1009 if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
1010 pr_warning("CPU %d failed to clear debug register pairs\n", cpu); 1010 pr_warn_once("CPU %d failed to clear debug register pairs\n", cpu);
1011 return; 1011 return;
1012 } 1012 }
1013 1013
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 3f6cbb2e3eda..d343a6c3a6d1 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -353,6 +353,23 @@ void __init early_print(const char *str, ...)
353 printk("%s", buf); 353 printk("%s", buf);
354} 354}
355 355
356static void __init cpuid_init_hwcaps(void)
357{
358 unsigned int divide_instrs;
359
360 if (cpu_architecture() < CPU_ARCH_ARMv7)
361 return;
362
363 divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
364
365 switch (divide_instrs) {
366 case 2:
367 elf_hwcap |= HWCAP_IDIVA;
368 case 1:
369 elf_hwcap |= HWCAP_IDIVT;
370 }
371}
372
356static void __init feat_v6_fixup(void) 373static void __init feat_v6_fixup(void)
357{ 374{
358 int id = read_cpuid_id(); 375 int id = read_cpuid_id();
@@ -483,8 +500,11 @@ static void __init setup_processor(void)
483 snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c", 500 snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
484 list->elf_name, ENDIANNESS); 501 list->elf_name, ENDIANNESS);
485 elf_hwcap = list->elf_hwcap; 502 elf_hwcap = list->elf_hwcap;
503
504 cpuid_init_hwcaps();
505
486#ifndef CONFIG_ARM_THUMB 506#ifndef CONFIG_ARM_THUMB
487 elf_hwcap &= ~HWCAP_THUMB; 507 elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT);
488#endif 508#endif
489 509
490 feat_v6_fixup(); 510 feat_v6_fixup();
@@ -524,7 +544,7 @@ int __init arm_add_memory(phys_addr_t start, phys_addr_t size)
524 size -= start & ~PAGE_MASK; 544 size -= start & ~PAGE_MASK;
525 bank->start = PAGE_ALIGN(start); 545 bank->start = PAGE_ALIGN(start);
526 546
527#ifndef CONFIG_LPAE 547#ifndef CONFIG_ARM_LPAE
528 if (bank->start + size < bank->start) { 548 if (bank->start + size < bank->start) {
529 printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in " 549 printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in "
530 "32-bit physical address space\n", (long long)start); 550 "32-bit physical address space\n", (long long)start);
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 79078edbb9bc..1f2ccccaf009 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -673,9 +673,6 @@ static int cpufreq_callback(struct notifier_block *nb,
673 if (freq->flags & CPUFREQ_CONST_LOOPS) 673 if (freq->flags & CPUFREQ_CONST_LOOPS)
674 return NOTIFY_OK; 674 return NOTIFY_OK;
675 675
676 if (arm_delay_ops.const_clock)
677 return NOTIFY_OK;
678
679 if (!per_cpu(l_p_j_ref, cpu)) { 676 if (!per_cpu(l_p_j_ref, cpu)) {
680 per_cpu(l_p_j_ref, cpu) = 677 per_cpu(l_p_j_ref, cpu) =
681 per_cpu(cpu_data, cpu).loops_per_jiffy; 678 per_cpu(cpu_data, cpu).loops_per_jiffy;
diff --git a/arch/arm/kernel/smp_tlb.c b/arch/arm/kernel/smp_tlb.c
index bd0300531399..e82e1d248772 100644
--- a/arch/arm/kernel/smp_tlb.c
+++ b/arch/arm/kernel/smp_tlb.c
@@ -12,6 +12,7 @@
12 12
13#include <asm/smp_plat.h> 13#include <asm/smp_plat.h>
14#include <asm/tlbflush.h> 14#include <asm/tlbflush.h>
15#include <asm/mmu_context.h>
15 16
16/**********************************************************************/ 17/**********************************************************************/
17 18
@@ -69,12 +70,72 @@ static inline void ipi_flush_bp_all(void *ignored)
69 local_flush_bp_all(); 70 local_flush_bp_all();
70} 71}
71 72
73#ifdef CONFIG_ARM_ERRATA_798181
74static int erratum_a15_798181(void)
75{
76 unsigned int midr = read_cpuid_id();
77
78 /* Cortex-A15 r0p0..r3p2 affected */
79 if ((midr & 0xff0ffff0) != 0x410fc0f0 || midr > 0x413fc0f2)
80 return 0;
81 return 1;
82}
83#else
84static int erratum_a15_798181(void)
85{
86 return 0;
87}
88#endif
89
90static void ipi_flush_tlb_a15_erratum(void *arg)
91{
92 dmb();
93}
94
95static void broadcast_tlb_a15_erratum(void)
96{
97 if (!erratum_a15_798181())
98 return;
99
100 dummy_flush_tlb_a15_erratum();
101 smp_call_function_many(cpu_online_mask, ipi_flush_tlb_a15_erratum,
102 NULL, 1);
103}
104
105static void broadcast_tlb_mm_a15_erratum(struct mm_struct *mm)
106{
107 int cpu;
108 cpumask_t mask = { CPU_BITS_NONE };
109
110 if (!erratum_a15_798181())
111 return;
112
113 dummy_flush_tlb_a15_erratum();
114 for_each_online_cpu(cpu) {
115 if (cpu == smp_processor_id())
116 continue;
117 /*
118 * We only need to send an IPI if the other CPUs are running
119 * the same ASID as the one being invalidated. There is no
120 * need for locking around the active_asids check since the
121 * switch_mm() function has at least one dmb() (as required by
122 * this workaround) in case a context switch happens on
123 * another CPU after the condition below.
124 */
125 if (atomic64_read(&mm->context.id) ==
126 atomic64_read(&per_cpu(active_asids, cpu)))
127 cpumask_set_cpu(cpu, &mask);
128 }
129 smp_call_function_many(&mask, ipi_flush_tlb_a15_erratum, NULL, 1);
130}
131
72void flush_tlb_all(void) 132void flush_tlb_all(void)
73{ 133{
74 if (tlb_ops_need_broadcast()) 134 if (tlb_ops_need_broadcast())
75 on_each_cpu(ipi_flush_tlb_all, NULL, 1); 135 on_each_cpu(ipi_flush_tlb_all, NULL, 1);
76 else 136 else
77 local_flush_tlb_all(); 137 local_flush_tlb_all();
138 broadcast_tlb_a15_erratum();
78} 139}
79 140
80void flush_tlb_mm(struct mm_struct *mm) 141void flush_tlb_mm(struct mm_struct *mm)
@@ -83,6 +144,7 @@ void flush_tlb_mm(struct mm_struct *mm)
83 on_each_cpu_mask(mm_cpumask(mm), ipi_flush_tlb_mm, mm, 1); 144 on_each_cpu_mask(mm_cpumask(mm), ipi_flush_tlb_mm, mm, 1);
84 else 145 else
85 local_flush_tlb_mm(mm); 146 local_flush_tlb_mm(mm);
147 broadcast_tlb_mm_a15_erratum(mm);
86} 148}
87 149
88void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) 150void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
@@ -95,6 +157,7 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
95 &ta, 1); 157 &ta, 1);
96 } else 158 } else
97 local_flush_tlb_page(vma, uaddr); 159 local_flush_tlb_page(vma, uaddr);
160 broadcast_tlb_mm_a15_erratum(vma->vm_mm);
98} 161}
99 162
100void flush_tlb_kernel_page(unsigned long kaddr) 163void flush_tlb_kernel_page(unsigned long kaddr)
@@ -105,6 +168,7 @@ void flush_tlb_kernel_page(unsigned long kaddr)
105 on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1); 168 on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1);
106 } else 169 } else
107 local_flush_tlb_kernel_page(kaddr); 170 local_flush_tlb_kernel_page(kaddr);
171 broadcast_tlb_a15_erratum();
108} 172}
109 173
110void flush_tlb_range(struct vm_area_struct *vma, 174void flush_tlb_range(struct vm_area_struct *vma,
@@ -119,6 +183,7 @@ void flush_tlb_range(struct vm_area_struct *vma,
119 &ta, 1); 183 &ta, 1);
120 } else 184 } else
121 local_flush_tlb_range(vma, start, end); 185 local_flush_tlb_range(vma, start, end);
186 broadcast_tlb_mm_a15_erratum(vma->vm_mm);
122} 187}
123 188
124void flush_tlb_kernel_range(unsigned long start, unsigned long end) 189void flush_tlb_kernel_range(unsigned long start, unsigned long end)
@@ -130,6 +195,7 @@ void flush_tlb_kernel_range(unsigned long start, unsigned long end)
130 on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1); 195 on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1);
131 } else 196 } else
132 local_flush_tlb_kernel_range(start, end); 197 local_flush_tlb_kernel_range(start, end);
198 broadcast_tlb_a15_erratum();
133} 199}
134 200
135void flush_bp_all(void) 201void flush_bp_all(void)
diff --git a/arch/arm/kvm/vgic.c b/arch/arm/kvm/vgic.c
index c9a17316e9fe..0e4cfe123b38 100644
--- a/arch/arm/kvm/vgic.c
+++ b/arch/arm/kvm/vgic.c
@@ -883,8 +883,7 @@ static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
883 lr, irq, vgic_cpu->vgic_lr[lr]); 883 lr, irq, vgic_cpu->vgic_lr[lr]);
884 BUG_ON(!test_bit(lr, vgic_cpu->lr_used)); 884 BUG_ON(!test_bit(lr, vgic_cpu->lr_used));
885 vgic_cpu->vgic_lr[lr] |= GICH_LR_PENDING_BIT; 885 vgic_cpu->vgic_lr[lr] |= GICH_LR_PENDING_BIT;
886 886 return true;
887 goto out;
888 } 887 }
889 888
890 /* Try to use another LR for this interrupt */ 889 /* Try to use another LR for this interrupt */
@@ -898,7 +897,6 @@ static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
898 vgic_cpu->vgic_irq_lr_map[irq] = lr; 897 vgic_cpu->vgic_irq_lr_map[irq] = lr;
899 set_bit(lr, vgic_cpu->lr_used); 898 set_bit(lr, vgic_cpu->lr_used);
900 899
901out:
902 if (!vgic_irq_is_edge(vcpu, irq)) 900 if (!vgic_irq_is_edge(vcpu, irq))
903 vgic_cpu->vgic_lr[lr] |= GICH_LR_EOI; 901 vgic_cpu->vgic_lr[lr] |= GICH_LR_EOI;
904 902
@@ -1018,21 +1016,6 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
1018 1016
1019 kvm_debug("MISR = %08x\n", vgic_cpu->vgic_misr); 1017 kvm_debug("MISR = %08x\n", vgic_cpu->vgic_misr);
1020 1018
1021 /*
1022 * We do not need to take the distributor lock here, since the only
1023 * action we perform is clearing the irq_active_bit for an EOIed
1024 * level interrupt. There is a potential race with
1025 * the queuing of an interrupt in __kvm_vgic_flush_hwstate(), where we
1026 * check if the interrupt is already active. Two possibilities:
1027 *
1028 * - The queuing is occurring on the same vcpu: cannot happen,
1029 * as we're already in the context of this vcpu, and
1030 * executing the handler
1031 * - The interrupt has been migrated to another vcpu, and we
1032 * ignore this interrupt for this run. Big deal. It is still
1033 * pending though, and will get considered when this vcpu
1034 * exits.
1035 */
1036 if (vgic_cpu->vgic_misr & GICH_MISR_EOI) { 1019 if (vgic_cpu->vgic_misr & GICH_MISR_EOI) {
1037 /* 1020 /*
1038 * Some level interrupts have been EOIed. Clear their 1021 * Some level interrupts have been EOIed. Clear their
@@ -1054,6 +1037,13 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
1054 } else { 1037 } else {
1055 vgic_cpu_irq_clear(vcpu, irq); 1038 vgic_cpu_irq_clear(vcpu, irq);
1056 } 1039 }
1040
1041 /*
1042 * Despite being EOIed, the LR may not have
1043 * been marked as empty.
1044 */
1045 set_bit(lr, (unsigned long *)vgic_cpu->vgic_elrsr);
1046 vgic_cpu->vgic_lr[lr] &= ~GICH_LR_ACTIVE_BIT;
1057 } 1047 }
1058 } 1048 }
1059 1049
@@ -1064,9 +1054,8 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
1064} 1054}
1065 1055
1066/* 1056/*
1067 * Sync back the VGIC state after a guest run. We do not really touch 1057 * Sync back the VGIC state after a guest run. The distributor lock is
1068 * the distributor here (the irq_pending_on_cpu bit is safe to set), 1058 * needed so we don't get preempted in the middle of the state processing.
1069 * so there is no need for taking its lock.
1070 */ 1059 */
1071static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) 1060static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
1072{ 1061{
@@ -1112,10 +1101,14 @@ void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
1112 1101
1113void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) 1102void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
1114{ 1103{
1104 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1105
1115 if (!irqchip_in_kernel(vcpu->kvm)) 1106 if (!irqchip_in_kernel(vcpu->kvm))
1116 return; 1107 return;
1117 1108
1109 spin_lock(&dist->lock);
1118 __kvm_vgic_sync_hwstate(vcpu); 1110 __kvm_vgic_sync_hwstate(vcpu);
1111 spin_unlock(&dist->lock);
1119} 1112}
1120 1113
1121int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu) 1114int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
diff --git a/arch/arm/lib/delay.c b/arch/arm/lib/delay.c
index 6b93f6a1a3c7..64dbfa57204a 100644
--- a/arch/arm/lib/delay.c
+++ b/arch/arm/lib/delay.c
@@ -58,7 +58,7 @@ static void __timer_delay(unsigned long cycles)
58static void __timer_const_udelay(unsigned long xloops) 58static void __timer_const_udelay(unsigned long xloops)
59{ 59{
60 unsigned long long loops = xloops; 60 unsigned long long loops = xloops;
61 loops *= loops_per_jiffy; 61 loops *= arm_delay_ops.ticks_per_jiffy;
62 __timer_delay(loops >> UDELAY_SHIFT); 62 __timer_delay(loops >> UDELAY_SHIFT);
63} 63}
64 64
@@ -73,11 +73,13 @@ void __init register_current_timer_delay(const struct delay_timer *timer)
73 pr_info("Switching to timer-based delay loop\n"); 73 pr_info("Switching to timer-based delay loop\n");
74 delay_timer = timer; 74 delay_timer = timer;
75 lpj_fine = timer->freq / HZ; 75 lpj_fine = timer->freq / HZ;
76 loops_per_jiffy = lpj_fine; 76
77 /* cpufreq may scale loops_per_jiffy, so keep a private copy */
78 arm_delay_ops.ticks_per_jiffy = lpj_fine;
77 arm_delay_ops.delay = __timer_delay; 79 arm_delay_ops.delay = __timer_delay;
78 arm_delay_ops.const_udelay = __timer_const_udelay; 80 arm_delay_ops.const_udelay = __timer_const_udelay;
79 arm_delay_ops.udelay = __timer_udelay; 81 arm_delay_ops.udelay = __timer_udelay;
80 arm_delay_ops.const_clock = true; 82
81 delay_calibrated = true; 83 delay_calibrated = true;
82 } else { 84 } else {
83 pr_info("Ignoring duplicate/late registration of read_current_timer delay\n"); 85 pr_info("Ignoring duplicate/late registration of read_current_timer delay\n");
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index e698f26cc0cb..52e4bb5cf12d 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -22,19 +22,9 @@
22 22
23static struct map_desc cns3xxx_io_desc[] __initdata = { 23static struct map_desc cns3xxx_io_desc[] __initdata = {
24 { 24 {
25 .virtual = CNS3XXX_TC11MP_TWD_BASE_VIRT, 25 .virtual = CNS3XXX_TC11MP_SCU_BASE_VIRT,
26 .pfn = __phys_to_pfn(CNS3XXX_TC11MP_TWD_BASE), 26 .pfn = __phys_to_pfn(CNS3XXX_TC11MP_SCU_BASE),
27 .length = SZ_4K, 27 .length = SZ_8K,
28 .type = MT_DEVICE,
29 }, {
30 .virtual = CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT,
31 .pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_CPU_BASE),
32 .length = SZ_4K,
33 .type = MT_DEVICE,
34 }, {
35 .virtual = CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT,
36 .pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_DIST_BASE),
37 .length = SZ_4K,
38 .type = MT_DEVICE, 28 .type = MT_DEVICE,
39 }, { 29 }, {
40 .virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT, 30 .virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT,
diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
index 191c8e57f289..b1021aafa481 100644
--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
@@ -94,10 +94,10 @@
94#define RTC_INTR_STS_OFFSET 0x34 94#define RTC_INTR_STS_OFFSET 0x34
95 95
96#define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */ 96#define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */
97#define CNS3XXX_MISC_BASE_VIRT 0xFFF07000 /* Misc Control */ 97#define CNS3XXX_MISC_BASE_VIRT 0xFB000000 /* Misc Control */
98 98
99#define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */ 99#define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */
100#define CNS3XXX_PM_BASE_VIRT 0xFFF08000 100#define CNS3XXX_PM_BASE_VIRT 0xFB001000
101 101
102#define PM_CLK_GATE_OFFSET 0x00 102#define PM_CLK_GATE_OFFSET 0x00
103#define PM_SOFT_RST_OFFSET 0x04 103#define PM_SOFT_RST_OFFSET 0x04
@@ -109,7 +109,7 @@
109#define PM_PLL_HM_PD_OFFSET 0x1C 109#define PM_PLL_HM_PD_OFFSET 0x1C
110 110
111#define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */ 111#define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */
112#define CNS3XXX_UART0_BASE_VIRT 0xFFF09000 112#define CNS3XXX_UART0_BASE_VIRT 0xFB002000
113 113
114#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */ 114#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */
115#define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000 115#define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000
@@ -130,7 +130,7 @@
130#define CNS3XXX_I2S_BASE_VIRT 0xFFF10000 130#define CNS3XXX_I2S_BASE_VIRT 0xFFF10000
131 131
132#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */ 132#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */
133#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFFF10800 133#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFB003000
134 134
135#define TIMER1_COUNTER_OFFSET 0x00 135#define TIMER1_COUNTER_OFFSET 0x00
136#define TIMER1_AUTO_RELOAD_OFFSET 0x04 136#define TIMER1_AUTO_RELOAD_OFFSET 0x04
@@ -227,16 +227,16 @@
227 * Testchip peripheral and fpga gic regions 227 * Testchip peripheral and fpga gic regions
228 */ 228 */
229#define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */ 229#define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */
230#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFF000000 230#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFB004000
231 231
232#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */ 232#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */
233#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT 0xFF000100 233#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x100)
234 234
235#define CNS3XXX_TC11MP_TWD_BASE 0x90000600 235#define CNS3XXX_TC11MP_TWD_BASE 0x90000600
236#define CNS3XXX_TC11MP_TWD_BASE_VIRT 0xFF000600 236#define CNS3XXX_TC11MP_TWD_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x600)
237 237
238#define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */ 238#define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */
239#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT 0xFF001000 239#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000)
240 240
241#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */ 241#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */
242#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000 242#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000
diff --git a/arch/arm/mach-ep93xx/include/mach/uncompress.h b/arch/arm/mach-ep93xx/include/mach/uncompress.h
index d2afb4dd82ab..b5cc77d2380b 100644
--- a/arch/arm/mach-ep93xx/include/mach/uncompress.h
+++ b/arch/arm/mach-ep93xx/include/mach/uncompress.h
@@ -47,9 +47,13 @@ static void __raw_writel(unsigned int value, unsigned int ptr)
47 47
48static inline void putc(int c) 48static inline void putc(int c)
49{ 49{
50 /* Transmit fifo not full? */ 50 int i;
51 while (__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF) 51
52 ; 52 for (i = 0; i < 10000; i++) {
53 /* Transmit fifo not full? */
54 if (!(__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF))
55 break;
56 }
53 57
54 __raw_writeb(c, PHYS_UART_DATA); 58 __raw_writeb(c, PHYS_UART_DATA);
55} 59}
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 4c9c6f9d2c55..2b09a0471d7b 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -65,6 +65,9 @@ config IRAM_ALLOC
65 bool 65 bool
66 select GENERIC_ALLOCATOR 66 select GENERIC_ALLOCATOR
67 67
68config HAVE_IMX_ANATOP
69 bool
70
68config HAVE_IMX_GPC 71config HAVE_IMX_GPC
69 bool 72 bool
70 73
@@ -73,6 +76,7 @@ config HAVE_IMX_MMDC
73 76
74config HAVE_IMX_SRC 77config HAVE_IMX_SRC
75 def_bool y if SMP 78 def_bool y if SMP
79 select ARCH_HAS_RESET_CONTROLLER
76 80
77config IMX_HAVE_IOMUX_V1 81config IMX_HAVE_IOMUX_V1
78 bool 82 bool
@@ -83,24 +87,12 @@ config ARCH_MXC_IOMUX_V3
83config ARCH_MX1 87config ARCH_MX1
84 bool 88 bool
85 89
86config MACH_MX21
87 bool
88
89config ARCH_MX25 90config ARCH_MX25
90 bool 91 bool
91 92
92config MACH_MX27 93config MACH_MX27
93 bool 94 bool
94 95
95config ARCH_MX5
96 bool
97
98config ARCH_MX51
99 bool
100
101config ARCH_MX53
102 bool
103
104config SOC_IMX1 96config SOC_IMX1
105 bool 97 bool
106 select ARCH_MX1 98 select ARCH_MX1
@@ -114,7 +106,6 @@ config SOC_IMX21
114 select COMMON_CLK 106 select COMMON_CLK
115 select CPU_ARM926T 107 select CPU_ARM926T
116 select IMX_HAVE_IOMUX_V1 108 select IMX_HAVE_IOMUX_V1
117 select MACH_MX21
118 select MXC_AVIC 109 select MXC_AVIC
119 110
120config SOC_IMX25 111config SOC_IMX25
@@ -128,6 +119,8 @@ config SOC_IMX25
128 119
129config SOC_IMX27 120config SOC_IMX27
130 bool 121 bool
122 select ARCH_HAS_CPUFREQ
123 select ARCH_HAS_OPP
131 select COMMON_CLK 124 select COMMON_CLK
132 select CPU_ARM926T 125 select CPU_ARM926T
133 select IMX_HAVE_IOMUX_V1 126 select IMX_HAVE_IOMUX_V1
@@ -155,7 +148,7 @@ config SOC_IMX35
155config SOC_IMX5 148config SOC_IMX5
156 bool 149 bool
157 select ARCH_HAS_CPUFREQ 150 select ARCH_HAS_CPUFREQ
158 select ARCH_MX5 151 select ARCH_HAS_OPP
159 select ARCH_MXC_IOMUX_V3 152 select ARCH_MXC_IOMUX_V3
160 select COMMON_CLK 153 select COMMON_CLK
161 select CPU_V7 154 select CPU_V7
@@ -163,8 +156,6 @@ config SOC_IMX5
163 156
164config SOC_IMX51 157config SOC_IMX51
165 bool 158 bool
166 select ARCH_MX5
167 select ARCH_MX51
168 select PINCTRL 159 select PINCTRL
169 select PINCTRL_IMX51 160 select PINCTRL_IMX51
170 select SOC_IMX5 161 select SOC_IMX5
@@ -789,8 +780,6 @@ comment "Device tree only"
789 780
790config SOC_IMX53 781config SOC_IMX53
791 bool "i.MX53 support" 782 bool "i.MX53 support"
792 select ARCH_MX5
793 select ARCH_MX53
794 select HAVE_CAN_FLEXCAN if CAN 783 select HAVE_CAN_FLEXCAN if CAN
795 select IMX_HAVE_PLATFORM_IMX2_WDT 784 select IMX_HAVE_PLATFORM_IMX2_WDT
796 select PINCTRL 785 select PINCTRL
@@ -801,7 +790,7 @@ config SOC_IMX53
801 This enables support for Freescale i.MX53 processor. 790 This enables support for Freescale i.MX53 processor.
802 791
803config SOC_IMX6Q 792config SOC_IMX6Q
804 bool "i.MX6 Quad support" 793 bool "i.MX6 Quad/DualLite support"
805 select ARCH_HAS_CPUFREQ 794 select ARCH_HAS_CPUFREQ
806 select ARCH_HAS_OPP 795 select ARCH_HAS_OPP
807 select ARM_CPU_SUSPEND if PM 796 select ARM_CPU_SUSPEND if PM
@@ -813,6 +802,7 @@ config SOC_IMX6Q
813 select CPU_V7 802 select CPU_V7
814 select HAVE_ARM_SCU 803 select HAVE_ARM_SCU
815 select HAVE_CAN_FLEXCAN if CAN 804 select HAVE_CAN_FLEXCAN if CAN
805 select HAVE_IMX_ANATOP
816 select HAVE_IMX_GPC 806 select HAVE_IMX_GPC
817 select HAVE_IMX_MMDC 807 select HAVE_IMX_MMDC
818 select HAVE_IMX_SRC 808 select HAVE_IMX_SRC
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index c4ce0906d76a..b16eb39b9f5d 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -12,7 +12,7 @@ obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-
12obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o 12obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
13 13
14imx5-pm-$(CONFIG_PM) += pm-imx5.o 14imx5-pm-$(CONFIG_PM) += pm-imx5.o
15obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o 15obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y)
16 16
17obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \ 17obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
18 clk-pfd.o clk-busy.o clk.o 18 clk-pfd.o clk-busy.o clk.o
@@ -27,7 +27,6 @@ obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
27obj-$(CONFIG_MXC_ULPI) += ulpi.o 27obj-$(CONFIG_MXC_ULPI) += ulpi.o
28obj-$(CONFIG_MXC_USE_EPIT) += epit.o 28obj-$(CONFIG_MXC_USE_EPIT) += epit.o
29obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o 29obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
30obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o
31 30
32ifeq ($(CONFIG_CPU_IDLE),y) 31ifeq ($(CONFIG_CPU_IDLE),y)
33obj-y += cpuidle.o 32obj-y += cpuidle.o
@@ -92,6 +91,7 @@ obj-$(CONFIG_MACH_EUKREA_CPUIMX35SD) += mach-cpuimx35.o
92obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o 91obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
93obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o 92obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
94 93
94obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o
95obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o 95obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
96obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o 96obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
97obj-$(CONFIG_HAVE_IMX_SRC) += src.o 97obj-$(CONFIG_HAVE_IMX_SRC) += src.o
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
deleted file mode 100644
index 41ba1bb0437b..000000000000
--- a/arch/arm/mach-imx/Makefile.boot
+++ /dev/null
@@ -1,35 +0,0 @@
1zreladdr-$(CONFIG_SOC_IMX1) += 0x08008000
2params_phys-$(CONFIG_SOC_IMX1) := 0x08000100
3initrd_phys-$(CONFIG_SOC_IMX1) := 0x08800000
4
5zreladdr-$(CONFIG_SOC_IMX21) += 0xC0008000
6params_phys-$(CONFIG_SOC_IMX21) := 0xC0000100
7initrd_phys-$(CONFIG_SOC_IMX21) := 0xC0800000
8
9zreladdr-$(CONFIG_SOC_IMX25) += 0x80008000
10params_phys-$(CONFIG_SOC_IMX25) := 0x80000100
11initrd_phys-$(CONFIG_SOC_IMX25) := 0x80800000
12
13zreladdr-$(CONFIG_SOC_IMX27) += 0xA0008000
14params_phys-$(CONFIG_SOC_IMX27) := 0xA0000100
15initrd_phys-$(CONFIG_SOC_IMX27) := 0xA0800000
16
17zreladdr-$(CONFIG_SOC_IMX31) += 0x80008000
18params_phys-$(CONFIG_SOC_IMX31) := 0x80000100
19initrd_phys-$(CONFIG_SOC_IMX31) := 0x80800000
20
21zreladdr-$(CONFIG_SOC_IMX35) += 0x80008000
22params_phys-$(CONFIG_SOC_IMX35) := 0x80000100
23initrd_phys-$(CONFIG_SOC_IMX35) := 0x80800000
24
25zreladdr-$(CONFIG_SOC_IMX51) += 0x90008000
26params_phys-$(CONFIG_SOC_IMX51) := 0x90000100
27initrd_phys-$(CONFIG_SOC_IMX51) := 0x90800000
28
29zreladdr-$(CONFIG_SOC_IMX53) += 0x70008000
30params_phys-$(CONFIG_SOC_IMX53) := 0x70000100
31initrd_phys-$(CONFIG_SOC_IMX53) := 0x70800000
32
33zreladdr-$(CONFIG_SOC_IMX6Q) += 0x10008000
34params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100
35initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c
new file mode 100644
index 000000000000..0cfa07dd9aa4
--- /dev/null
+++ b/arch/arm/mach-imx/anatop.c
@@ -0,0 +1,103 @@
1/*
2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/err.h>
13#include <linux/io.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/mfd/syscon.h>
17#include <linux/regmap.h>
18#include "common.h"
19
20#define REG_SET 0x4
21#define REG_CLR 0x8
22
23#define ANADIG_REG_2P5 0x130
24#define ANADIG_REG_CORE 0x140
25#define ANADIG_ANA_MISC0 0x150
26#define ANADIG_USB1_CHRG_DETECT 0x1b0
27#define ANADIG_USB2_CHRG_DETECT 0x210
28#define ANADIG_DIGPROG 0x260
29
30#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000
31#define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000
32#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000
33#define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x80000
34#define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x100000
35
36static struct regmap *anatop;
37
38static void imx_anatop_enable_weak2p5(bool enable)
39{
40 u32 reg, val;
41
42 regmap_read(anatop, ANADIG_ANA_MISC0, &val);
43
44 /* can only be enabled when stop_mode_config is clear. */
45 reg = ANADIG_REG_2P5;
46 reg += (enable && (val & BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) == 0) ?
47 REG_SET : REG_CLR;
48 regmap_write(anatop, reg, BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG);
49}
50
51static void imx_anatop_enable_fet_odrive(bool enable)
52{
53 regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR),
54 BM_ANADIG_REG_CORE_FET_ODRIVE);
55}
56
57void imx_anatop_pre_suspend(void)
58{
59 imx_anatop_enable_weak2p5(true);
60 imx_anatop_enable_fet_odrive(true);
61}
62
63void imx_anatop_post_resume(void)
64{
65 imx_anatop_enable_fet_odrive(false);
66 imx_anatop_enable_weak2p5(false);
67}
68
69void imx_anatop_usb_chrg_detect_disable(void)
70{
71 regmap_write(anatop, ANADIG_USB1_CHRG_DETECT,
72 BM_ANADIG_USB_CHRG_DETECT_EN_B
73 | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
74 regmap_write(anatop, ANADIG_USB2_CHRG_DETECT,
75 BM_ANADIG_USB_CHRG_DETECT_EN_B |
76 BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
77}
78
79u32 imx_anatop_get_digprog(void)
80{
81 struct device_node *np;
82 void __iomem *anatop_base;
83 static u32 digprog;
84
85 if (digprog)
86 return digprog;
87
88 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
89 anatop_base = of_iomap(np, 0);
90 WARN_ON(!anatop_base);
91 digprog = readl_relaxed(anatop_base + ANADIG_DIGPROG);
92
93 return digprog;
94}
95
96void __init imx_anatop_init(void)
97{
98 anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
99 if (IS_ERR(anatop)) {
100 pr_err("%s: failed to find imx6q-anatop regmap!\n", __func__);
101 return;
102 }
103}
diff --git a/arch/arm/mach-imx/avic.c b/arch/arm/mach-imx/avic.c
index 0eff23ed92b9..49c87e7aa817 100644
--- a/arch/arm/mach-imx/avic.c
+++ b/arch/arm/mach-imx/avic.c
@@ -54,8 +54,6 @@
54void __iomem *avic_base; 54void __iomem *avic_base;
55static struct irq_domain *domain; 55static struct irq_domain *domain;
56 56
57static u32 avic_saved_mask_reg[2];
58
59#ifdef CONFIG_MXC_IRQ_PRIOR 57#ifdef CONFIG_MXC_IRQ_PRIOR
60static int avic_irq_set_priority(unsigned char irq, unsigned char prio) 58static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
61{ 59{
@@ -113,6 +111,8 @@ static struct mxc_extra_irq avic_extra_irq = {
113}; 111};
114 112
115#ifdef CONFIG_PM 113#ifdef CONFIG_PM
114static u32 avic_saved_mask_reg[2];
115
116static void avic_irq_suspend(struct irq_data *d) 116static void avic_irq_suspend(struct irq_data *d)
117{ 117{
118 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 118 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index 30b3242a7d49..8e3b65719106 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -278,8 +278,6 @@ int __init mx27_clocks_init(unsigned long fref)
278 clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL); 278 clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL);
279 clk_register_clkdev(clk[cpu_div], "cpu", NULL); 279 clk_register_clkdev(clk[cpu_div], "cpu", NULL);
280 clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL); 280 clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL);
281 clk_register_clkdev(clk[ssi1_baud_gate], "bitrate" , "imx-ssi.0");
282 clk_register_clkdev(clk[ssi2_baud_gate], "bitrate" , "imx-ssi.1");
283 281
284 mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1); 282 mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
285 283
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index e13a8fa5e62c..2193c834f55c 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -257,6 +257,7 @@ int __init mx35_clocks_init(void)
257 clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0"); 257 clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
258 clk_register_clkdev(clk[nfc_div], NULL, "imx25-nand.0"); 258 clk_register_clkdev(clk[nfc_div], NULL, "imx25-nand.0");
259 clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0"); 259 clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
260 clk_register_clkdev(clk[admux_gate], "audmux", NULL);
260 261
261 clk_prepare_enable(clk[spba_gate]); 262 clk_prepare_enable(clk[spba_gate]);
262 clk_prepare_enable(clk[gpio1_gate]); 263 clk_prepare_enable(clk[gpio1_gate]);
@@ -265,6 +266,7 @@ int __init mx35_clocks_init(void)
265 clk_prepare_enable(clk[iim_gate]); 266 clk_prepare_enable(clk[iim_gate]);
266 clk_prepare_enable(clk[emi_gate]); 267 clk_prepare_enable(clk[emi_gate]);
267 clk_prepare_enable(clk[max_gate]); 268 clk_prepare_enable(clk[max_gate]);
269 clk_prepare_enable(clk[iomuxc_gate]);
268 270
269 /* 271 /*
270 * SCC is needed to boot via mmc after a watchdog reset. The clock code 272 * SCC is needed to boot via mmc after a watchdog reset. The clock code
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 0f39f8c93b94..41dd4d6e5b91 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -45,16 +45,40 @@ static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "
45static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", }; 45static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };
46static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", }; 46static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };
47static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", }; 47static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };
48static const char *tve_sel[] = { "tve_pred", "tve_ext_sel", }; 48static const char *mx51_tve_sel[] = { "tve_pred", "tve_ext_sel", };
49static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", }; 49static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
50static const char *gpu3d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" };
51static const char *gpu2d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" };
50static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", }; 52static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
51static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", }; 53static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", };
54static const char *mx53_cko1_sel[] = {
55 "cpu_podf", "pll1_sw", "pll2_sw", "pll3_sw",
56 "emi_slow_podf", "pll4_sw", "nfc_podf", "dummy",
57 "di_pred", "dummy", "dummy", "ahb",
58 "ipg", "per_root", "ckil", "dummy",};
59static const char *mx53_cko2_sel[] = {
60 "dummy"/* dptc_core */, "dummy"/* dptc_perich */,
61 "dummy", "esdhc_a_podf",
62 "usboh3_podf", "dummy"/* wrck_clk_root */,
63 "ecspi_podf", "dummy"/* pll1_ref_clk */,
64 "esdhc_b_podf", "dummy"/* ddr_clk_root */,
65 "dummy"/* arm_axi_clk_root */, "dummy"/* usb_phy_out */,
66 "vpu_sel", "ipu_sel",
67 "osc", "ckih1",
68 "dummy", "esdhc_c_sel",
69 "ssi1_root_podf", "ssi2_root_podf",
70 "dummy", "dummy",
71 "dummy"/* lpsr_clk_root */, "dummy"/* pgc_clk_root */,
72 "dummy"/* tve_out */, "usb_phy_sel",
73 "tve_sel", "lp_apm",
74 "uart_root", "dummy"/* spdif0_clk_root */,
75 "dummy", "dummy", };
52 76
53enum imx5_clks { 77enum imx5_clks {
54 dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred, 78 dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
55 uart_root, esdhc_a_pred, esdhc_b_pred, esdhc_c_s, esdhc_d_s, 79 uart_root, esdhc_a_pred, esdhc_b_pred, esdhc_c_s, esdhc_d_s,
56 emi_sel, emi_slow_podf, nfc_podf, ecspi_pred, ecspi_podf, usboh3_pred, 80 emi_sel, emi_slow_podf, nfc_podf, ecspi_pred, ecspi_podf, usboh3_pred,
57 usboh3_podf, usb_phy_pred, usb_phy_podf, cpu_podf, di_pred, tve_di, 81 usboh3_podf, usb_phy_pred, usb_phy_podf, cpu_podf, di_pred, tve_di_unused,
58 tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate, 82 tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate,
59 uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate, 83 uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate,
60 gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate, 84 gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate,
@@ -83,7 +107,10 @@ enum imx5_clks {
83 ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate, 107 ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
84 epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate, 108 epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
85 can_sel, can1_serial_gate, can1_ipg_gate, 109 can_sel, can1_serial_gate, can1_ipg_gate,
86 owire_gate, 110 owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate,
111 cko1_sel, cko1_podf, cko1,
112 cko2_sel, cko2_podf, cko2,
113 srtc_gate, pata_gate,
87 clk_max 114 clk_max
88}; 115};
89 116
@@ -160,8 +187,6 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
160 usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str)); 187 usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
161 clk[cpu_podf] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3); 188 clk[cpu_podf] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3);
162 clk[di_pred] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3); 189 clk[di_pred] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
163 clk[tve_di] = imx_clk_fixed("tve_di", 65000000); /* FIXME */
164 clk[tve_s] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1, tve_sel, ARRAY_SIZE(tve_sel));
165 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30); 190 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
166 clk[uart1_ipg_gate] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6); 191 clk[uart1_ipg_gate] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
167 clk[uart1_per_gate] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8); 192 clk[uart1_per_gate] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8);
@@ -200,6 +225,11 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
200 clk[nfc_gate] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20); 225 clk[nfc_gate] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20);
201 clk[ipu_di0_gate] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10); 226 clk[ipu_di0_gate] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10);
202 clk[ipu_di1_gate] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12); 227 clk[ipu_di1_gate] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12);
228 clk[gpu3d_s] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel));
229 clk[gpu2d_s] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel));
230 clk[gpu3d_gate] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2);
231 clk[garb_gate] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4);
232 clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14);
203 clk[vpu_s] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel)); 233 clk[vpu_s] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
204 clk[vpu_gate] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6); 234 clk[vpu_gate] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
205 clk[vpu_reference_gate] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8); 235 clk[vpu_reference_gate] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
@@ -235,6 +265,8 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
235 clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6); 265 clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
236 clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8); 266 clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
237 clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22); 267 clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
268 clk[srtc_gate] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
269 clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
238 270
239 for (i = 0; i < ARRAY_SIZE(clk); i++) 271 for (i = 0; i < ARRAY_SIZE(clk); i++)
240 if (IS_ERR(clk[i])) 272 if (IS_ERR(clk[i]))
@@ -286,7 +318,6 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
286 clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0"); 318 clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0");
287 clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1"); 319 clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1");
288 clk_register_clkdev(clk[dummy], NULL, "imx-keypad"); 320 clk_register_clkdev(clk[dummy], NULL, "imx-keypad");
289 clk_register_clkdev(clk[tve_gate], NULL, "imx-tve.0");
290 clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0"); 321 clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0");
291 clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL); 322 clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL);
292 clk_register_clkdev(clk[epit1_ipg_gate], "ipg", "imx-epit.0"); 323 clk_register_clkdev(clk[epit1_ipg_gate], "ipg", "imx-epit.0");
@@ -331,8 +362,10 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
331 mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel)); 362 mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
332 clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3, 363 clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
333 mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel)); 364 mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
334 clk[tve_ext_sel] = imx_clk_mux("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1, 365 clk[tve_ext_sel] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
335 mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel)); 366 mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT);
367 clk[tve_s] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1,
368 mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));
336 clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30); 369 clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
337 clk[tve_pred] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3); 370 clk[tve_pred] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
338 clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); 371 clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
@@ -423,23 +456,23 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
423 clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE); 456 clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
424 clk[pll4_sw] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE); 457 clk[pll4_sw] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE);
425 458
426 clk[ldb_di1_sel] = imx_clk_mux("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
427 mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel));
428 clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); 459 clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
429 clk[ldb_di1_div] = imx_clk_divider("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1); 460 clk[ldb_di1_div] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0);
461 clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
462 mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT);
430 clk[di_pll4_podf] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3); 463 clk[di_pll4_podf] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3);
431 clk[ldb_di0_sel] = imx_clk_mux("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
432 mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel));
433 clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); 464 clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
434 clk[ldb_di0_div] = imx_clk_divider("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1); 465 clk[ldb_di0_div] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0);
466 clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
467 mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT);
435 clk[ldb_di0_gate] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28); 468 clk[ldb_di0_gate] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
436 clk[ldb_di1_gate] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30); 469 clk[ldb_di1_gate] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
437 clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, 470 clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
438 mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel)); 471 mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
439 clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3, 472 clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
440 mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel)); 473 mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
441 clk[tve_ext_sel] = imx_clk_mux("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1, 474 clk[tve_ext_sel] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
442 mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel)); 475 mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);
443 clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30); 476 clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
444 clk[tve_pred] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3); 477 clk[tve_pred] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
445 clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); 478 clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
@@ -456,6 +489,16 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
456 clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6); 489 clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
457 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); 490 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
458 491
492 clk[cko1_sel] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
493 mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
494 clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
495 clk[cko1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
496
497 clk[cko2_sel] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
498 mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
499 clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
500 clk[cko2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
501
459 for (i = 0; i < ARRAY_SIZE(clk); i++) 502 for (i = 0; i < ARRAY_SIZE(clk); i++)
460 if (IS_ERR(clk[i])) 503 if (IS_ERR(clk[i]))
461 pr_err("i.MX53 clk %d: register failed with %ld\n", 504 pr_err("i.MX53 clk %d: register failed with %ld\n",
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 2f9ff93a4e61..151259003086 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2011 Freescale Semiconductor, Inc. 2 * Copyright 2011-2013 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd. 3 * Copyright 2011 Linaro Ltd.
4 * 4 *
5 * The code contained herein is licensed under the GNU General Public 5 * The code contained herein is licensed under the GNU General Public
@@ -14,6 +14,7 @@
14#include <linux/types.h> 14#include <linux/types.h>
15#include <linux/clk.h> 15#include <linux/clk.h>
16#include <linux/clkdev.h> 16#include <linux/clkdev.h>
17#include <linux/delay.h>
17#include <linux/err.h> 18#include <linux/err.h>
18#include <linux/io.h> 19#include <linux/io.h>
19#include <linux/of.h> 20#include <linux/of.h>
@@ -22,6 +23,12 @@
22 23
23#include "clk.h" 24#include "clk.h"
24#include "common.h" 25#include "common.h"
26#include "hardware.h"
27
28#define CCR 0x0
29#define BM_CCR_WB_COUNT (0x7 << 16)
30#define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21)
31#define BM_CCR_RBC_EN (0x1 << 27)
25 32
26#define CCGR0 0x68 33#define CCGR0 0x68
27#define CCGR1 0x6c 34#define CCGR1 0x6c
@@ -67,6 +74,67 @@ void imx6q_set_chicken_bit(void)
67 writel_relaxed(val, ccm_base + CGPR); 74 writel_relaxed(val, ccm_base + CGPR);
68} 75}
69 76
77static void imx6q_enable_rbc(bool enable)
78{
79 u32 val;
80 static bool last_rbc_mode;
81
82 if (last_rbc_mode == enable)
83 return;
84 /*
85 * need to mask all interrupts in GPC before
86 * operating RBC configurations
87 */
88 imx_gpc_mask_all();
89
90 /* configure RBC enable bit */
91 val = readl_relaxed(ccm_base + CCR);
92 val &= ~BM_CCR_RBC_EN;
93 val |= enable ? BM_CCR_RBC_EN : 0;
94 writel_relaxed(val, ccm_base + CCR);
95
96 /* configure RBC count */
97 val = readl_relaxed(ccm_base + CCR);
98 val &= ~BM_CCR_RBC_BYPASS_COUNT;
99 val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
100 writel(val, ccm_base + CCR);
101
102 /*
103 * need to delay at least 2 cycles of CKIL(32K)
104 * due to hardware design requirement, which is
105 * ~61us, here we use 65us for safe
106 */
107 udelay(65);
108
109 /* restore GPC interrupt mask settings */
110 imx_gpc_restore_all();
111
112 last_rbc_mode = enable;
113}
114
115static void imx6q_enable_wb(bool enable)
116{
117 u32 val;
118 static bool last_wb_mode;
119
120 if (last_wb_mode == enable)
121 return;
122
123 /* configure well bias enable bit */
124 val = readl_relaxed(ccm_base + CLPCR);
125 val &= ~BM_CLPCR_WB_PER_AT_LPM;
126 val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
127 writel_relaxed(val, ccm_base + CLPCR);
128
129 /* configure well bias count */
130 val = readl_relaxed(ccm_base + CCR);
131 val &= ~BM_CCR_WB_COUNT;
132 val |= enable ? BM_CCR_WB_COUNT : 0;
133 writel_relaxed(val, ccm_base + CCR);
134
135 last_wb_mode = enable;
136}
137
70int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) 138int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
71{ 139{
72 u32 val = readl_relaxed(ccm_base + CLPCR); 140 u32 val = readl_relaxed(ccm_base + CLPCR);
@@ -74,6 +142,8 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
74 val &= ~BM_CLPCR_LPM; 142 val &= ~BM_CLPCR_LPM;
75 switch (mode) { 143 switch (mode) {
76 case WAIT_CLOCKED: 144 case WAIT_CLOCKED:
145 imx6q_enable_wb(false);
146 imx6q_enable_rbc(false);
77 break; 147 break;
78 case WAIT_UNCLOCKED: 148 case WAIT_UNCLOCKED:
79 val |= 0x1 << BP_CLPCR_LPM; 149 val |= 0x1 << BP_CLPCR_LPM;
@@ -92,6 +162,8 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
92 val |= 0x3 << BP_CLPCR_STBY_COUNT; 162 val |= 0x3 << BP_CLPCR_STBY_COUNT;
93 val |= BM_CLPCR_VSTBY; 163 val |= BM_CLPCR_VSTBY;
94 val |= BM_CLPCR_SBYOS; 164 val |= BM_CLPCR_SBYOS;
165 imx6q_enable_wb(true);
166 imx6q_enable_rbc(true);
95 break; 167 break;
96 default: 168 default:
97 return -EINVAL; 169 return -EINVAL;
@@ -109,29 +181,29 @@ static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", };
109static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; 181static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
110static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; 182static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
111static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "pll3_pfd1_540m", }; 183static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "pll3_pfd1_540m", };
112static const char *audio_sels[] = { "pll4_audio", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", }; 184static const char *audio_sels[] = { "pll4_post_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
113static const char *gpu_axi_sels[] = { "axi", "ahb", }; 185static const char *gpu_axi_sels[] = { "axi", "ahb", };
114static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", }; 186static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
115static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", }; 187static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
116static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd9_720m", }; 188static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd9_720m", };
117static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; 189static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
118static const char *ldb_di_sels[] = { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_pfd1_540m", }; 190static const char *ldb_di_sels[] = { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", };
119static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", }; 191static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
120static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; 192static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
121static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; 193static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
122static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; 194static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
123static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; 195static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
124static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", }; 196static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", };
125static const char *pcie_axi_sels[] = { "axi", "ahb", }; 197static const char *pcie_axi_sels[] = { "axi", "ahb", };
126static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio", }; 198static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_post_div", };
127static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; 199static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
128static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", }; 200static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
129static const char *emi_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", }; 201static const char *emi_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
130static const char *vdo_axi_sels[] = { "axi", "ahb", }; 202static const char *vdo_axi_sels[] = { "axi", "ahb", };
131static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", }; 203static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
132static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video", 204static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
133 "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0", 205 "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
134 "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio", }; 206 "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_post_div", };
135 207
136enum mx6q_clks { 208enum mx6q_clks {
137 dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m, 209 dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
@@ -165,7 +237,7 @@ enum mx6q_clks {
165 pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg, 237 pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
166 ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, 238 ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
167 sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, 239 sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
168 usbphy2_gate, clk_max 240 usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, clk_max
169}; 241};
170 242
171static struct clk *clk[clk_max]; 243static struct clk *clk[clk_max];
@@ -182,6 +254,21 @@ static struct clk_div_table clk_enet_ref_table[] = {
182 { .val = 3, .div = 4, }, 254 { .val = 3, .div = 4, },
183}; 255};
184 256
257static struct clk_div_table post_div_table[] = {
258 { .val = 2, .div = 1, },
259 { .val = 1, .div = 2, },
260 { .val = 0, .div = 4, },
261 { }
262};
263
264static struct clk_div_table video_div_table[] = {
265 { .val = 0, .div = 1, },
266 { .val = 1, .div = 2, },
267 { .val = 2, .div = 1, },
268 { .val = 3, .div = 4, },
269 { }
270};
271
185int __init mx6q_clocks_init(void) 272int __init mx6q_clocks_init(void)
186{ 273{
187 struct device_node *np; 274 struct device_node *np;
@@ -208,6 +295,14 @@ int __init mx6q_clocks_init(void)
208 base = of_iomap(np, 0); 295 base = of_iomap(np, 0);
209 WARN_ON(!base); 296 WARN_ON(!base);
210 297
298 /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */
299 if (cpu_is_imx6q() && imx6q_revision() == IMX_CHIP_REVISION_1_0) {
300 post_div_table[1].div = 1;
301 post_div_table[2].div = 1;
302 video_div_table[1].div = 1;
303 video_div_table[2].div = 1;
304 };
305
211 /* type name parent_name base div_mask */ 306 /* type name parent_name base div_mask */
212 clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f); 307 clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
213 clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1); 308 clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
@@ -260,6 +355,10 @@ int __init mx6q_clocks_init(void)
260 clk[pll3_60m] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); 355 clk[pll3_60m] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
261 clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2); 356 clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2);
262 357
358 clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
359 clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
360 clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
361
263 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ccm"); 362 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ccm");
264 base = of_iomap(np, 0); 363 base = of_iomap(np, 0);
265 WARN_ON(!base); 364 WARN_ON(!base);
@@ -283,8 +382,8 @@ int __init mx6q_clocks_init(void)
283 clk[gpu3d_shader_sel] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); 382 clk[gpu3d_shader_sel] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
284 clk[ipu1_sel] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); 383 clk[ipu1_sel] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
285 clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); 384 clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
286 clk[ldb_di0_sel] = imx_clk_mux("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); 385 clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
287 clk[ldb_di1_sel] = imx_clk_mux("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); 386 clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
288 clk[ipu1_di0_pre_sel] = imx_clk_mux("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); 387 clk[ipu1_di0_pre_sel] = imx_clk_mux("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
289 clk[ipu1_di1_pre_sel] = imx_clk_mux("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); 388 clk[ipu1_di1_pre_sel] = imx_clk_mux("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
290 clk[ipu2_di0_pre_sel] = imx_clk_mux("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); 389 clk[ipu2_di0_pre_sel] = imx_clk_mux("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
@@ -332,9 +431,9 @@ int __init mx6q_clocks_init(void)
332 clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3); 431 clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3);
333 clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3); 432 clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3);
334 clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); 433 clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
335 clk[ldb_di0_podf] = imx_clk_divider("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1); 434 clk[ldb_di0_podf] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0);
336 clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); 435 clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
337 clk[ldb_di1_podf] = imx_clk_divider("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1); 436 clk[ldb_di1_podf] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0);
338 clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3); 437 clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3);
339 clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3); 438 clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3);
340 clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3); 439 clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3);
@@ -443,12 +542,16 @@ int __init mx6q_clocks_init(void)
443 542
444 clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0"); 543 clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
445 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); 544 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
446 clk_register_clkdev(clk[twd], NULL, "smp_twd");
447 clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL); 545 clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
448 clk_register_clkdev(clk[ahb], "ahb", NULL); 546 clk_register_clkdev(clk[ahb], "ahb", NULL);
449 clk_register_clkdev(clk[cko1], "cko1", NULL); 547 clk_register_clkdev(clk[cko1], "cko1", NULL);
450 clk_register_clkdev(clk[arm], NULL, "cpu0"); 548 clk_register_clkdev(clk[arm], NULL, "cpu0");
451 549
550 if (imx6q_revision() != IMX_CHIP_REVISION_1_0) {
551 clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
552 clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
553 }
554
452 /* 555 /*
453 * The gpmi needs 100MHz frequency in the EDO/Sync mode, 556 * The gpmi needs 100MHz frequency in the EDO/Sync mode,
454 * We can not get the 100MHz from the pll2_pfd0_352m. 557 * We can not get the 100MHz from the pll2_pfd0_352m.
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 9d1f3b99d1d3..d9d9d9c66dff 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -59,6 +59,14 @@ static inline struct clk *imx_clk_divider(const char *name, const char *parent,
59 reg, shift, width, 0, &imx_ccm_lock); 59 reg, shift, width, 0, &imx_ccm_lock);
60} 60}
61 61
62static inline struct clk *imx_clk_divider_flags(const char *name,
63 const char *parent, void __iomem *reg, u8 shift, u8 width,
64 unsigned long flags)
65{
66 return clk_register_divider(NULL, name, parent, flags,
67 reg, shift, width, 0, &imx_ccm_lock);
68}
69
62static inline struct clk *imx_clk_gate(const char *name, const char *parent, 70static inline struct clk *imx_clk_gate(const char *name, const char *parent,
63 void __iomem *reg, u8 shift) 71 void __iomem *reg, u8 shift)
64{ 72{
@@ -73,6 +81,15 @@ static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
73 width, 0, &imx_ccm_lock); 81 width, 0, &imx_ccm_lock);
74} 82}
75 83
84static inline struct clk *imx_clk_mux_flags(const char *name,
85 void __iomem *reg, u8 shift, u8 width, const char **parents,
86 int num_parents, unsigned long flags)
87{
88 return clk_register_mux(NULL, name, parents, num_parents,
89 flags, reg, shift, width, 0,
90 &imx_ccm_lock);
91}
92
76static inline struct clk *imx_clk_fixed_factor(const char *name, 93static inline struct clk *imx_clk_fixed_factor(const char *name,
77 const char *parent, unsigned int mult, unsigned int div) 94 const char *parent, unsigned int mult, unsigned int div)
78{ 95{
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 5a800bfcec5b..4cba7dbb079f 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
3 */ 3 */
4 4
5/* 5/*
@@ -74,6 +74,7 @@ extern void mxc_set_cpu_type(unsigned int type);
74extern void mxc_restart(char, const char *); 74extern void mxc_restart(char, const char *);
75extern void mxc_arch_reset_init(void __iomem *); 75extern void mxc_arch_reset_init(void __iomem *);
76extern int mx53_revision(void); 76extern int mx53_revision(void);
77extern int imx6q_revision(void);
77extern int mx53_display_revision(void); 78extern int mx53_display_revision(void);
78extern void imx_set_aips(void __iomem *); 79extern void imx_set_aips(void __iomem *);
79extern int mxc_device_init(void); 80extern int mxc_device_init(void);
@@ -110,8 +111,9 @@ void tzic_handle_irq(struct pt_regs *);
110 111
111extern void imx_enable_cpu(int cpu, bool enable); 112extern void imx_enable_cpu(int cpu, bool enable);
112extern void imx_set_cpu_jump(int cpu, void *jump_addr); 113extern void imx_set_cpu_jump(int cpu, void *jump_addr);
114extern u32 imx_get_cpu_arg(int cpu);
115extern void imx_set_cpu_arg(int cpu, u32 arg);
113extern void v7_cpu_resume(void); 116extern void v7_cpu_resume(void);
114extern u32 *pl310_get_save_ptr(void);
115#ifdef CONFIG_SMP 117#ifdef CONFIG_SMP
116extern void v7_secondary_startup(void); 118extern void v7_secondary_startup(void);
117extern void imx_scu_map_io(void); 119extern void imx_scu_map_io(void);
@@ -122,13 +124,18 @@ static inline void imx_scu_map_io(void) {}
122static inline void imx_smp_prepare(void) {} 124static inline void imx_smp_prepare(void) {}
123static inline void imx_scu_standby_enable(void) {} 125static inline void imx_scu_standby_enable(void) {}
124#endif 126#endif
125extern void imx_enable_cpu(int cpu, bool enable);
126extern void imx_set_cpu_jump(int cpu, void *jump_addr);
127extern void imx_src_init(void); 127extern void imx_src_init(void);
128extern void imx_src_prepare_restart(void); 128extern void imx_src_prepare_restart(void);
129extern void imx_gpc_init(void); 129extern void imx_gpc_init(void);
130extern void imx_gpc_pre_suspend(void); 130extern void imx_gpc_pre_suspend(void);
131extern void imx_gpc_post_resume(void); 131extern void imx_gpc_post_resume(void);
132extern void imx_gpc_mask_all(void);
133extern void imx_gpc_restore_all(void);
134extern void imx_anatop_init(void);
135extern void imx_anatop_pre_suspend(void);
136extern void imx_anatop_post_resume(void);
137extern void imx_anatop_usb_chrg_detect_disable(void);
138extern u32 imx_anatop_get_digprog(void);
132extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); 139extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
133extern void imx6q_set_chicken_bit(void); 140extern void imx6q_set_chicken_bit(void);
134 141
diff --git a/arch/arm/mach-imx/cpu_op-mx51.c b/arch/arm/mach-imx/cpu_op-mx51.c
deleted file mode 100644
index b9ef692b61a2..000000000000
--- a/arch/arm/mach-imx/cpu_op-mx51.c
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#include <linux/bug.h>
15#include <linux/types.h>
16#include <linux/kernel.h>
17
18#include "hardware.h"
19
20static struct cpu_op mx51_cpu_op[] = {
21 {
22 .cpu_rate = 160000000,},
23 {
24 .cpu_rate = 800000000,},
25};
26
27struct cpu_op *mx51_get_cpu_op(int *op)
28{
29 *op = ARRAY_SIZE(mx51_cpu_op);
30 return mx51_cpu_op;
31}
diff --git a/arch/arm/mach-imx/cpu_op-mx51.h b/arch/arm/mach-imx/cpu_op-mx51.h
deleted file mode 100644
index 97477fecb469..000000000000
--- a/arch/arm/mach-imx/cpu_op-mx51.h
+++ /dev/null
@@ -1,14 +0,0 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14extern struct cpu_op *mx51_get_cpu_op(int *op);
diff --git a/arch/arm/mach-imx/cpufreq.c b/arch/arm/mach-imx/cpufreq.c
deleted file mode 100644
index d8c75c3c925d..000000000000
--- a/arch/arm/mach-imx/cpufreq.c
+++ /dev/null
@@ -1,206 +0,0 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/*
15 * A driver for the Freescale Semiconductor i.MXC CPUfreq module.
16 * The CPUFREQ driver is for controlling CPU frequency. It allows you to change
17 * the CPU clock speed on the fly.
18 */
19
20#include <linux/module.h>
21#include <linux/cpufreq.h>
22#include <linux/clk.h>
23#include <linux/err.h>
24#include <linux/slab.h>
25
26#include "hardware.h"
27
28#define CLK32_FREQ 32768
29#define NANOSECOND (1000 * 1000 * 1000)
30
31struct cpu_op *(*get_cpu_op)(int *op);
32
33static int cpu_freq_khz_min;
34static int cpu_freq_khz_max;
35
36static struct clk *cpu_clk;
37static struct cpufreq_frequency_table *imx_freq_table;
38
39static int cpu_op_nr;
40static struct cpu_op *cpu_op_tbl;
41
42static int set_cpu_freq(int freq)
43{
44 int ret = 0;
45 int org_cpu_rate;
46
47 org_cpu_rate = clk_get_rate(cpu_clk);
48 if (org_cpu_rate == freq)
49 return ret;
50
51 ret = clk_set_rate(cpu_clk, freq);
52 if (ret != 0) {
53 printk(KERN_DEBUG "cannot set CPU clock rate\n");
54 return ret;
55 }
56
57 return ret;
58}
59
60static int mxc_verify_speed(struct cpufreq_policy *policy)
61{
62 if (policy->cpu != 0)
63 return -EINVAL;
64
65 return cpufreq_frequency_table_verify(policy, imx_freq_table);
66}
67
68static unsigned int mxc_get_speed(unsigned int cpu)
69{
70 if (cpu)
71 return 0;
72
73 return clk_get_rate(cpu_clk) / 1000;
74}
75
76static int mxc_set_target(struct cpufreq_policy *policy,
77 unsigned int target_freq, unsigned int relation)
78{
79 struct cpufreq_freqs freqs;
80 int freq_Hz;
81 int ret = 0;
82 unsigned int index;
83
84 cpufreq_frequency_table_target(policy, imx_freq_table,
85 target_freq, relation, &index);
86 freq_Hz = imx_freq_table[index].frequency * 1000;
87
88 freqs.old = clk_get_rate(cpu_clk) / 1000;
89 freqs.new = freq_Hz / 1000;
90 freqs.cpu = 0;
91 freqs.flags = 0;
92 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
93
94 ret = set_cpu_freq(freq_Hz);
95
96 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
97
98 return ret;
99}
100
101static int mxc_cpufreq_init(struct cpufreq_policy *policy)
102{
103 int ret;
104 int i;
105
106 printk(KERN_INFO "i.MXC CPU frequency driver\n");
107
108 if (policy->cpu != 0)
109 return -EINVAL;
110
111 if (!get_cpu_op)
112 return -EINVAL;
113
114 cpu_clk = clk_get(NULL, "cpu_clk");
115 if (IS_ERR(cpu_clk)) {
116 printk(KERN_ERR "%s: failed to get cpu clock\n", __func__);
117 return PTR_ERR(cpu_clk);
118 }
119
120 cpu_op_tbl = get_cpu_op(&cpu_op_nr);
121
122 cpu_freq_khz_min = cpu_op_tbl[0].cpu_rate / 1000;
123 cpu_freq_khz_max = cpu_op_tbl[0].cpu_rate / 1000;
124
125 imx_freq_table = kmalloc(
126 sizeof(struct cpufreq_frequency_table) * (cpu_op_nr + 1),
127 GFP_KERNEL);
128 if (!imx_freq_table) {
129 ret = -ENOMEM;
130 goto err1;
131 }
132
133 for (i = 0; i < cpu_op_nr; i++) {
134 imx_freq_table[i].index = i;
135 imx_freq_table[i].frequency = cpu_op_tbl[i].cpu_rate / 1000;
136
137 if ((cpu_op_tbl[i].cpu_rate / 1000) < cpu_freq_khz_min)
138 cpu_freq_khz_min = cpu_op_tbl[i].cpu_rate / 1000;
139
140 if ((cpu_op_tbl[i].cpu_rate / 1000) > cpu_freq_khz_max)
141 cpu_freq_khz_max = cpu_op_tbl[i].cpu_rate / 1000;
142 }
143
144 imx_freq_table[i].index = i;
145 imx_freq_table[i].frequency = CPUFREQ_TABLE_END;
146
147 policy->cur = clk_get_rate(cpu_clk) / 1000;
148 policy->min = policy->cpuinfo.min_freq = cpu_freq_khz_min;
149 policy->max = policy->cpuinfo.max_freq = cpu_freq_khz_max;
150
151 /* Manual states, that PLL stabilizes in two CLK32 periods */
152 policy->cpuinfo.transition_latency = 2 * NANOSECOND / CLK32_FREQ;
153
154 ret = cpufreq_frequency_table_cpuinfo(policy, imx_freq_table);
155
156 if (ret < 0) {
157 printk(KERN_ERR "%s: failed to register i.MXC CPUfreq with error code %d\n",
158 __func__, ret);
159 goto err;
160 }
161
162 cpufreq_frequency_table_get_attr(imx_freq_table, policy->cpu);
163 return 0;
164err:
165 kfree(imx_freq_table);
166err1:
167 clk_put(cpu_clk);
168 return ret;
169}
170
171static int mxc_cpufreq_exit(struct cpufreq_policy *policy)
172{
173 cpufreq_frequency_table_put_attr(policy->cpu);
174
175 set_cpu_freq(cpu_freq_khz_max * 1000);
176 clk_put(cpu_clk);
177 kfree(imx_freq_table);
178 return 0;
179}
180
181static struct cpufreq_driver mxc_driver = {
182 .flags = CPUFREQ_STICKY,
183 .verify = mxc_verify_speed,
184 .target = mxc_set_target,
185 .get = mxc_get_speed,
186 .init = mxc_cpufreq_init,
187 .exit = mxc_cpufreq_exit,
188 .name = "imx",
189};
190
191static int mxc_cpufreq_driver_init(void)
192{
193 return cpufreq_register_driver(&mxc_driver);
194}
195
196static void mxc_cpufreq_driver_exit(void)
197{
198 cpufreq_unregister_driver(&mxc_driver);
199}
200
201module_init(mxc_cpufreq_driver_init);
202module_exit(mxc_cpufreq_driver_exit);
203
204MODULE_AUTHOR("Freescale Semiconductor Inc. Yong Shen <yong.shen@linaro.org>");
205MODULE_DESCRIPTION("CPUfreq driver for i.MX");
206MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig
index 9b9ba1f4ffe1..3dd2b1b041d1 100644
--- a/arch/arm/mach-imx/devices/Kconfig
+++ b/arch/arm/mach-imx/devices/Kconfig
@@ -86,7 +86,3 @@ config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
86 86
87config IMX_HAVE_PLATFORM_SPI_IMX 87config IMX_HAVE_PLATFORM_SPI_IMX
88 bool 88 bool
89
90config IMX_HAVE_PLATFORM_AHCI
91 bool
92 default y if ARCH_MX53
diff --git a/arch/arm/mach-imx/devices/Makefile b/arch/arm/mach-imx/devices/Makefile
index 6acf37e0c119..67416fb1dc69 100644
--- a/arch/arm/mach-imx/devices/Makefile
+++ b/arch/arm/mach-imx/devices/Makefile
@@ -29,5 +29,4 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o
29obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o 29obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
30obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o 30obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o
31obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o 31obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o
32obj-$(CONFIG_IMX_HAVE_PLATFORM_AHCI) += platform-ahci-imx.o
33obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_EMMA) += platform-mx2-emma.o 32obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_EMMA) += platform-mx2-emma.o
diff --git a/arch/arm/mach-imx/devices/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h
index 9bd5777ff0e7..453e20bc2657 100644
--- a/arch/arm/mach-imx/devices/devices-common.h
+++ b/arch/arm/mach-imx/devices/devices-common.h
@@ -344,13 +344,3 @@ struct platform_device *imx_add_imx_dma(char *name, resource_size_t iobase,
344 int irq, int irq_err); 344 int irq, int irq_err);
345struct platform_device *imx_add_imx_sdma(char *name, 345struct platform_device *imx_add_imx_sdma(char *name,
346 resource_size_t iobase, int irq, struct sdma_platform_data *pdata); 346 resource_size_t iobase, int irq, struct sdma_platform_data *pdata);
347
348#include <linux/ahci_platform.h>
349struct imx_ahci_imx_data {
350 const char *devid;
351 resource_size_t iobase;
352 resource_size_t irq;
353};
354struct platform_device *__init imx_add_ahci_imx(
355 const struct imx_ahci_imx_data *data,
356 const struct ahci_platform_data *pdata);
diff --git a/arch/arm/mach-imx/devices/platform-ahci-imx.c b/arch/arm/mach-imx/devices/platform-ahci-imx.c
deleted file mode 100644
index 3d87dd9c284a..000000000000
--- a/arch/arm/mach-imx/devices/platform-ahci-imx.c
+++ /dev/null
@@ -1,157 +0,0 @@
1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/io.h>
22#include <linux/clk.h>
23#include <linux/err.h>
24#include <linux/device.h>
25#include <linux/dma-mapping.h>
26#include <asm/sizes.h>
27
28#include "../hardware.h"
29#include "devices-common.h"
30
31#define imx_ahci_imx_data_entry_single(soc, _devid) \
32 { \
33 .devid = _devid, \
34 .iobase = soc ## _SATA_BASE_ADDR, \
35 .irq = soc ## _INT_SATA, \
36 }
37
38#ifdef CONFIG_SOC_IMX53
39const struct imx_ahci_imx_data imx53_ahci_imx_data __initconst =
40 imx_ahci_imx_data_entry_single(MX53, "imx53-ahci");
41#endif
42
43enum {
44 HOST_CAP = 0x00,
45 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
46 HOST_PORTS_IMPL = 0x0c,
47 HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
48};
49
50static struct clk *sata_clk, *sata_ref_clk;
51
52/* AHCI module Initialization, if return 0, initialization is successful. */
53static int imx_sata_init(struct device *dev, void __iomem *addr)
54{
55 u32 tmpdata;
56 int ret = 0;
57 struct clk *clk;
58
59 sata_clk = clk_get(dev, "ahci");
60 if (IS_ERR(sata_clk)) {
61 dev_err(dev, "no sata clock.\n");
62 return PTR_ERR(sata_clk);
63 }
64 ret = clk_prepare_enable(sata_clk);
65 if (ret) {
66 dev_err(dev, "can't prepare/enable sata clock.\n");
67 goto put_sata_clk;
68 }
69
70 /* Get the AHCI SATA PHY CLK */
71 sata_ref_clk = clk_get(dev, "ahci_phy");
72 if (IS_ERR(sata_ref_clk)) {
73 dev_err(dev, "no sata ref clock.\n");
74 ret = PTR_ERR(sata_ref_clk);
75 goto release_sata_clk;
76 }
77 ret = clk_prepare_enable(sata_ref_clk);
78 if (ret) {
79 dev_err(dev, "can't prepare/enable sata ref clock.\n");
80 goto put_sata_ref_clk;
81 }
82
83 /* Get the AHB clock rate, and configure the TIMER1MS reg later */
84 clk = clk_get(dev, "ahci_dma");
85 if (IS_ERR(clk)) {
86 dev_err(dev, "no dma clock.\n");
87 ret = PTR_ERR(clk);
88 goto release_sata_ref_clk;
89 }
90 tmpdata = clk_get_rate(clk) / 1000;
91 clk_put(clk);
92
93 writel(tmpdata, addr + HOST_TIMER1MS);
94
95 tmpdata = readl(addr + HOST_CAP);
96 if (!(tmpdata & HOST_CAP_SSS)) {
97 tmpdata |= HOST_CAP_SSS;
98 writel(tmpdata, addr + HOST_CAP);
99 }
100
101 if (!(readl(addr + HOST_PORTS_IMPL) & 0x1))
102 writel((readl(addr + HOST_PORTS_IMPL) | 0x1),
103 addr + HOST_PORTS_IMPL);
104
105 return 0;
106
107release_sata_ref_clk:
108 clk_disable_unprepare(sata_ref_clk);
109put_sata_ref_clk:
110 clk_put(sata_ref_clk);
111release_sata_clk:
112 clk_disable_unprepare(sata_clk);
113put_sata_clk:
114 clk_put(sata_clk);
115
116 return ret;
117}
118
119static void imx_sata_exit(struct device *dev)
120{
121 clk_disable_unprepare(sata_ref_clk);
122 clk_put(sata_ref_clk);
123
124 clk_disable_unprepare(sata_clk);
125 clk_put(sata_clk);
126
127}
128struct platform_device *__init imx_add_ahci_imx(
129 const struct imx_ahci_imx_data *data,
130 const struct ahci_platform_data *pdata)
131{
132 struct resource res[] = {
133 {
134 .start = data->iobase,
135 .end = data->iobase + SZ_4K - 1,
136 .flags = IORESOURCE_MEM,
137 }, {
138 .start = data->irq,
139 .end = data->irq,
140 .flags = IORESOURCE_IRQ,
141 },
142 };
143
144 return imx_add_platform_device_dmamask(data->devid, 0,
145 res, ARRAY_SIZE(res),
146 pdata, sizeof(*pdata), DMA_BIT_MASK(32));
147}
148
149struct platform_device *__init imx53_add_ahci_imx(void)
150{
151 struct ahci_platform_data pdata = {
152 .init = imx_sata_init,
153 .exit = imx_sata_exit,
154 };
155
156 return imx_add_ahci_imx(&imx53_ahci_imx_data, &pdata);
157}
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index a96ccc7f5012..c20445c56032 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2011 Freescale Semiconductor, Inc. 2 * Copyright 2011-2013 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd. 3 * Copyright 2011 Linaro Ltd.
4 * 4 *
5 * The code contained herein is licensed under the GNU General Public 5 * The code contained herein is licensed under the GNU General Public
@@ -68,6 +68,27 @@ static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
68 return 0; 68 return 0;
69} 69}
70 70
71void imx_gpc_mask_all(void)
72{
73 void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
74 int i;
75
76 for (i = 0; i < IMR_NUM; i++) {
77 gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
78 writel_relaxed(~0, reg_imr1 + i * 4);
79 }
80
81}
82
83void imx_gpc_restore_all(void)
84{
85 void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
86 int i;
87
88 for (i = 0; i < IMR_NUM; i++)
89 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
90}
91
71static void imx_gpc_irq_unmask(struct irq_data *d) 92static void imx_gpc_irq_unmask(struct irq_data *d)
72{ 93{
73 void __iomem *reg; 94 void __iomem *reg;
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
index 911e9b31b03f..356131f7b591 100644
--- a/arch/arm/mach-imx/hardware.h
+++ b/arch/arm/mach-imx/hardware.h
@@ -102,7 +102,6 @@
102 102
103#include "mxc.h" 103#include "mxc.h"
104 104
105#include "mx6q.h"
106#include "mx51.h" 105#include "mx51.h"
107#include "mx53.h" 106#include "mx53.h"
108#include "mx3x.h" 107#include "mx3x.h"
diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
index 7bc5fe15dda2..361a253e2b63 100644
--- a/arch/arm/mach-imx/hotplug.c
+++ b/arch/arm/mach-imx/hotplug.c
@@ -46,11 +46,23 @@ static inline void cpu_enter_lowpower(void)
46void imx_cpu_die(unsigned int cpu) 46void imx_cpu_die(unsigned int cpu)
47{ 47{
48 cpu_enter_lowpower(); 48 cpu_enter_lowpower();
49 /*
50 * We use the cpu jumping argument register to sync with
51 * imx_cpu_kill() which is running on cpu0 and waiting for
52 * the register being cleared to kill the cpu.
53 */
54 imx_set_cpu_arg(cpu, ~0);
49 cpu_do_idle(); 55 cpu_do_idle();
50} 56}
51 57
52int imx_cpu_kill(unsigned int cpu) 58int imx_cpu_kill(unsigned int cpu)
53{ 59{
60 unsigned long timeout = jiffies + msecs_to_jiffies(50);
61
62 while (imx_get_cpu_arg(cpu) == 0)
63 if (time_after(jiffies, timeout))
64 return 0;
54 imx_enable_cpu(cpu, false); 65 imx_enable_cpu(cpu, false);
66 imx_set_cpu_arg(cpu, 0);
55 return 1; 67 return 1;
56} 68}
diff --git a/arch/arm/mach-imx/mach-cpuimx51sd.c b/arch/arm/mach-imx/mach-cpuimx51sd.c
index 9b7393234f6f..9b5ddf5bbd33 100644
--- a/arch/arm/mach-imx/mach-cpuimx51sd.c
+++ b/arch/arm/mach-imx/mach-cpuimx51sd.c
@@ -33,7 +33,6 @@
33 33
34#include "common.h" 34#include "common.h"
35#include "devices-imx51.h" 35#include "devices-imx51.h"
36#include "cpu_op-mx51.h"
37#include "eukrea-baseboards.h" 36#include "eukrea-baseboards.h"
38#include "hardware.h" 37#include "hardware.h"
39#include "iomux-mx51.h" 38#include "iomux-mx51.h"
@@ -285,10 +284,6 @@ static void __init eukrea_cpuimx51sd_init(void)
285 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads, 284 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
286 ARRAY_SIZE(eukrea_cpuimx51sd_pads)); 285 ARRAY_SIZE(eukrea_cpuimx51sd_pads));
287 286
288#if defined(CONFIG_CPU_FREQ_IMX)
289 get_cpu_op = mx51_get_cpu_op;
290#endif
291
292 imx51_add_imx_uart(0, &uart_pdata); 287 imx51_add_imx_uart(0, &uart_pdata);
293 imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info); 288 imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
294 imx51_add_imx2_wdt(0); 289 imx51_add_imx2_wdt(0);
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index b59ddcb57c78..7230aede4ca2 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2011 Freescale Semiconductor, Inc. 2 * Copyright 2011-2013 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd. 3 * Copyright 2011 Linaro Ltd.
4 * 4 *
5 * The code contained herein is licensed under the GNU General Public 5 * The code contained herein is licensed under the GNU General Public
@@ -38,38 +38,32 @@
38#include "cpuidle.h" 38#include "cpuidle.h"
39#include "hardware.h" 39#include "hardware.h"
40 40
41#define IMX6Q_ANALOG_DIGPROG 0x260 41static u32 chip_revision;
42 42
43static int imx6q_revision(void) 43int imx6q_revision(void)
44{ 44{
45 struct device_node *np; 45 return chip_revision;
46 void __iomem *base; 46}
47 static u32 rev; 47
48 48static void __init imx6q_init_revision(void)
49 if (!rev) { 49{
50 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); 50 u32 rev = imx_anatop_get_digprog();
51 if (!np)
52 return IMX_CHIP_REVISION_UNKNOWN;
53 base = of_iomap(np, 0);
54 if (!base) {
55 of_node_put(np);
56 return IMX_CHIP_REVISION_UNKNOWN;
57 }
58 rev = readl_relaxed(base + IMX6Q_ANALOG_DIGPROG);
59 iounmap(base);
60 of_node_put(np);
61 }
62 51
63 switch (rev & 0xff) { 52 switch (rev & 0xff) {
64 case 0: 53 case 0:
65 return IMX_CHIP_REVISION_1_0; 54 chip_revision = IMX_CHIP_REVISION_1_0;
55 break;
66 case 1: 56 case 1:
67 return IMX_CHIP_REVISION_1_1; 57 chip_revision = IMX_CHIP_REVISION_1_1;
58 break;
68 case 2: 59 case 2:
69 return IMX_CHIP_REVISION_1_2; 60 chip_revision = IMX_CHIP_REVISION_1_2;
61 break;
70 default: 62 default:
71 return IMX_CHIP_REVISION_UNKNOWN; 63 chip_revision = IMX_CHIP_REVISION_UNKNOWN;
72 } 64 }
65
66 mxc_set_cpu_type(rev >> 16 & 0xff);
73} 67}
74 68
75void imx6q_restart(char mode, const char *cmd) 69void imx6q_restart(char mode, const char *cmd)
@@ -164,29 +158,7 @@ static void __init imx6q_1588_init(void)
164} 158}
165static void __init imx6q_usb_init(void) 159static void __init imx6q_usb_init(void)
166{ 160{
167 struct regmap *anatop; 161 imx_anatop_usb_chrg_detect_disable();
168
169#define HW_ANADIG_USB1_CHRG_DETECT 0x000001b0
170#define HW_ANADIG_USB2_CHRG_DETECT 0x00000210
171
172#define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x00100000
173#define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x00080000
174
175 anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
176 if (!IS_ERR(anatop)) {
177 /*
178 * The external charger detector needs to be disabled,
179 * or the signal at DP will be poor
180 */
181 regmap_write(anatop, HW_ANADIG_USB1_CHRG_DETECT,
182 BM_ANADIG_USB_CHRG_DETECT_EN_B
183 | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
184 regmap_write(anatop, HW_ANADIG_USB2_CHRG_DETECT,
185 BM_ANADIG_USB_CHRG_DETECT_EN_B |
186 BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
187 } else {
188 pr_warn("failed to find fsl,imx6q-anatop regmap\n");
189 }
190} 162}
191 163
192static void __init imx6q_init_machine(void) 164static void __init imx6q_init_machine(void)
@@ -196,6 +168,7 @@ static void __init imx6q_init_machine(void)
196 168
197 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 169 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
198 170
171 imx_anatop_init();
199 imx6q_pm_init(); 172 imx6q_pm_init();
200 imx6q_usb_init(); 173 imx6q_usb_init();
201 imx6q_1588_init(); 174 imx6q_1588_init();
@@ -282,6 +255,7 @@ static void __init imx6q_map_io(void)
282 255
283static void __init imx6q_init_irq(void) 256static void __init imx6q_init_irq(void)
284{ 257{
258 imx6q_init_revision();
285 l2x0_of_init(0, ~0UL); 259 l2x0_of_init(0, ~0UL);
286 imx_src_init(); 260 imx_src_init();
287 imx_gpc_init(); 261 imx_gpc_init();
@@ -292,15 +266,17 @@ static void __init imx6q_timer_init(void)
292{ 266{
293 mx6q_clocks_init(); 267 mx6q_clocks_init();
294 clocksource_of_init(); 268 clocksource_of_init();
295 imx_print_silicon_rev("i.MX6Q", imx6q_revision()); 269 imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
270 imx6q_revision());
296} 271}
297 272
298static const char *imx6q_dt_compat[] __initdata = { 273static const char *imx6q_dt_compat[] __initdata = {
274 "fsl,imx6dl",
299 "fsl,imx6q", 275 "fsl,imx6q",
300 NULL, 276 NULL,
301}; 277};
302 278
303DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad (Device Tree)") 279DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
304 .smp = smp_ops(imx_smp_ops), 280 .smp = smp_ops(imx_smp_ops),
305 .map_io = imx6q_map_io, 281 .map_io = imx6q_map_io,
306 .init_irq = imx6q_init_irq, 282 .init_irq = imx6q_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c
index 6c4d7feb4520..f3d264a636fa 100644
--- a/arch/arm/mach-imx/mach-mx51_babbage.c
+++ b/arch/arm/mach-imx/mach-mx51_babbage.c
@@ -27,7 +27,6 @@
27 27
28#include "common.h" 28#include "common.h"
29#include "devices-imx51.h" 29#include "devices-imx51.h"
30#include "cpu_op-mx51.h"
31#include "hardware.h" 30#include "hardware.h"
32#include "iomux-mx51.h" 31#include "iomux-mx51.h"
33 32
@@ -371,9 +370,6 @@ static void __init mx51_babbage_init(void)
371 370
372 imx51_soc_init(); 371 imx51_soc_init();
373 372
374#if defined(CONFIG_CPU_FREQ_IMX)
375 get_cpu_op = mx51_get_cpu_op;
376#endif
377 imx51_babbage_common_init(); 373 imx51_babbage_common_init();
378 374
379 imx51_add_imx_uart(0, &uart_pdata); 375 imx51_add_imx_uart(0, &uart_pdata);
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index 7a146671e65a..3c609c52d3eb 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -51,6 +51,8 @@ void __init mx1_init_irq(void)
51 51
52void __init imx1_soc_init(void) 52void __init imx1_soc_init(void)
53{ 53{
54 mxc_device_init();
55
54 mxc_register_gpio("imx1-gpio", 0, MX1_GPIO1_BASE_ADDR, SZ_256, 56 mxc_register_gpio("imx1-gpio", 0, MX1_GPIO1_BASE_ADDR, SZ_256,
55 MX1_GPIO_INT_PORTA, 0); 57 MX1_GPIO_INT_PORTA, 0);
56 mxc_register_gpio("imx1-gpio", 1, MX1_GPIO2_BASE_ADDR, SZ_256, 58 mxc_register_gpio("imx1-gpio", 1, MX1_GPIO2_BASE_ADDR, SZ_256,
diff --git a/arch/arm/mach-imx/mx6q.h b/arch/arm/mach-imx/mx6q.h
deleted file mode 100644
index 19d3f54db5af..000000000000
--- a/arch/arm/mach-imx/mx6q.h
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#ifndef __MACH_MX6Q_H__
14#define __MACH_MX6Q_H__
15
16#define MX6Q_IO_P2V(x) IMX_IO_P2V(x)
17#define MX6Q_IO_ADDRESS(x) IOMEM(MX6Q_IO_P2V(x))
18
19/*
20 * The following are the blocks that need to be statically mapped.
21 * For other blocks, the base address really should be retrieved from
22 * device tree.
23 */
24#define MX6Q_SCU_BASE_ADDR 0x00a00000
25#define MX6Q_SCU_SIZE 0x1000
26#define MX6Q_CCM_BASE_ADDR 0x020c4000
27#define MX6Q_CCM_SIZE 0x4000
28#define MX6Q_ANATOP_BASE_ADDR 0x020c8000
29#define MX6Q_ANATOP_SIZE 0x1000
30
31#endif /* __MACH_MX6Q_H__ */
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
index 7dce17a9fe6c..8629e5be7ecd 100644
--- a/arch/arm/mach-imx/mxc.h
+++ b/arch/arm/mach-imx/mxc.h
@@ -34,6 +34,8 @@
34#define MXC_CPU_MX35 35 34#define MXC_CPU_MX35 35
35#define MXC_CPU_MX51 51 35#define MXC_CPU_MX51 51
36#define MXC_CPU_MX53 53 36#define MXC_CPU_MX53 53
37#define MXC_CPU_IMX6DL 0x61
38#define MXC_CPU_IMX6Q 0x63
37 39
38#define IMX_CHIP_REVISION_1_0 0x10 40#define IMX_CHIP_REVISION_1_0 0x10
39#define IMX_CHIP_REVISION_1_1 0x11 41#define IMX_CHIP_REVISION_1_1 0x11
@@ -150,6 +152,15 @@ extern unsigned int __mxc_cpu_type;
150#endif 152#endif
151 153
152#ifndef __ASSEMBLY__ 154#ifndef __ASSEMBLY__
155static inline bool cpu_is_imx6dl(void)
156{
157 return __mxc_cpu_type == MXC_CPU_IMX6DL;
158}
159
160static inline bool cpu_is_imx6q(void)
161{
162 return __mxc_cpu_type == MXC_CPU_IMX6Q;
163}
153 164
154struct cpu_op { 165struct cpu_op {
155 u32 cpu_rate; 166 u32 cpu_rate;
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 77e9a25ed0f6..4a69305db65e 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -68,8 +68,8 @@ static void __init imx_smp_init_cpus(void)
68 68
69 ncores = scu_get_core_count(scu_base); 69 ncores = scu_get_core_count(scu_base);
70 70
71 for (i = 0; i < ncores; i++) 71 for (i = ncores; i < NR_CPUS; i++)
72 set_cpu_possible(i, true); 72 set_cpu_possible(i, false);
73} 73}
74 74
75void imx_smp_prepare(void) 75void imx_smp_prepare(void)
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
index 5faba7a3c95f..204942749e21 100644
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ b/arch/arm/mach-imx/pm-imx6q.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2011 Freescale Semiconductor, Inc. 2 * Copyright 2011-2013 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd. 3 * Copyright 2011 Linaro Ltd.
4 * 4 *
5 * The code contained herein is licensed under the GNU General Public 5 * The code contained herein is licensed under the GNU General Public
@@ -34,10 +34,12 @@ static int imx6q_pm_enter(suspend_state_t state)
34 case PM_SUSPEND_MEM: 34 case PM_SUSPEND_MEM:
35 imx6q_set_lpm(STOP_POWER_OFF); 35 imx6q_set_lpm(STOP_POWER_OFF);
36 imx_gpc_pre_suspend(); 36 imx_gpc_pre_suspend();
37 imx_anatop_pre_suspend();
37 imx_set_cpu_jump(0, v7_cpu_resume); 38 imx_set_cpu_jump(0, v7_cpu_resume);
38 /* Zzz ... */ 39 /* Zzz ... */
39 cpu_suspend(0, imx6q_suspend_finish); 40 cpu_suspend(0, imx6q_suspend_finish);
40 imx_smp_prepare(); 41 imx_smp_prepare();
42 imx_anatop_post_resume();
41 imx_gpc_post_resume(); 43 imx_gpc_post_resume();
42 imx6q_set_lpm(WAIT_CLOCKED); 44 imx6q_set_lpm(WAIT_CLOCKED);
43 break; 45 break;
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index e15f1555c59b..dec641108b54 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -14,16 +14,72 @@
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/of.h> 15#include <linux/of.h>
16#include <linux/of_address.h> 16#include <linux/of_address.h>
17#include <linux/reset-controller.h>
17#include <linux/smp.h> 18#include <linux/smp.h>
18#include <asm/smp_plat.h> 19#include <asm/smp_plat.h>
19 20
20#define SRC_SCR 0x000 21#define SRC_SCR 0x000
21#define SRC_GPR1 0x020 22#define SRC_GPR1 0x020
22#define BP_SRC_SCR_WARM_RESET_ENABLE 0 23#define BP_SRC_SCR_WARM_RESET_ENABLE 0
24#define BP_SRC_SCR_SW_GPU_RST 1
25#define BP_SRC_SCR_SW_VPU_RST 2
26#define BP_SRC_SCR_SW_IPU1_RST 3
27#define BP_SRC_SCR_SW_OPEN_VG_RST 4
28#define BP_SRC_SCR_SW_IPU2_RST 12
23#define BP_SRC_SCR_CORE1_RST 14 29#define BP_SRC_SCR_CORE1_RST 14
24#define BP_SRC_SCR_CORE1_ENABLE 22 30#define BP_SRC_SCR_CORE1_ENABLE 22
25 31
26static void __iomem *src_base; 32static void __iomem *src_base;
33static DEFINE_SPINLOCK(scr_lock);
34
35static const int sw_reset_bits[5] = {
36 BP_SRC_SCR_SW_GPU_RST,
37 BP_SRC_SCR_SW_VPU_RST,
38 BP_SRC_SCR_SW_IPU1_RST,
39 BP_SRC_SCR_SW_OPEN_VG_RST,
40 BP_SRC_SCR_SW_IPU2_RST
41};
42
43static int imx_src_reset_module(struct reset_controller_dev *rcdev,
44 unsigned long sw_reset_idx)
45{
46 unsigned long timeout;
47 unsigned long flags;
48 int bit;
49 u32 val;
50
51 if (!src_base)
52 return -ENODEV;
53
54 if (sw_reset_idx >= ARRAY_SIZE(sw_reset_bits))
55 return -EINVAL;
56
57 bit = 1 << sw_reset_bits[sw_reset_idx];
58
59 spin_lock_irqsave(&scr_lock, flags);
60 val = readl_relaxed(src_base + SRC_SCR);
61 val |= bit;
62 writel_relaxed(val, src_base + SRC_SCR);
63 spin_unlock_irqrestore(&scr_lock, flags);
64
65 timeout = jiffies + msecs_to_jiffies(1000);
66 while (readl(src_base + SRC_SCR) & bit) {
67 if (time_after(jiffies, timeout))
68 return -ETIME;
69 cpu_relax();
70 }
71
72 return 0;
73}
74
75static struct reset_control_ops imx_src_ops = {
76 .reset = imx_src_reset_module,
77};
78
79static struct reset_controller_dev imx_reset_controller = {
80 .ops = &imx_src_ops,
81 .nr_resets = ARRAY_SIZE(sw_reset_bits),
82};
27 83
28void imx_enable_cpu(int cpu, bool enable) 84void imx_enable_cpu(int cpu, bool enable)
29{ 85{
@@ -31,9 +87,11 @@ void imx_enable_cpu(int cpu, bool enable)
31 87
32 cpu = cpu_logical_map(cpu); 88 cpu = cpu_logical_map(cpu);
33 mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1); 89 mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1);
90 spin_lock(&scr_lock);
34 val = readl_relaxed(src_base + SRC_SCR); 91 val = readl_relaxed(src_base + SRC_SCR);
35 val = enable ? val | mask : val & ~mask; 92 val = enable ? val | mask : val & ~mask;
36 writel_relaxed(val, src_base + SRC_SCR); 93 writel_relaxed(val, src_base + SRC_SCR);
94 spin_unlock(&scr_lock);
37} 95}
38 96
39void imx_set_cpu_jump(int cpu, void *jump_addr) 97void imx_set_cpu_jump(int cpu, void *jump_addr)
@@ -43,14 +101,28 @@ void imx_set_cpu_jump(int cpu, void *jump_addr)
43 src_base + SRC_GPR1 + cpu * 8); 101 src_base + SRC_GPR1 + cpu * 8);
44} 102}
45 103
104u32 imx_get_cpu_arg(int cpu)
105{
106 cpu = cpu_logical_map(cpu);
107 return readl_relaxed(src_base + SRC_GPR1 + cpu * 8 + 4);
108}
109
110void imx_set_cpu_arg(int cpu, u32 arg)
111{
112 cpu = cpu_logical_map(cpu);
113 writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4);
114}
115
46void imx_src_prepare_restart(void) 116void imx_src_prepare_restart(void)
47{ 117{
48 u32 val; 118 u32 val;
49 119
50 /* clear enable bits of secondary cores */ 120 /* clear enable bits of secondary cores */
121 spin_lock(&scr_lock);
51 val = readl_relaxed(src_base + SRC_SCR); 122 val = readl_relaxed(src_base + SRC_SCR);
52 val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE); 123 val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE);
53 writel_relaxed(val, src_base + SRC_SCR); 124 writel_relaxed(val, src_base + SRC_SCR);
125 spin_unlock(&scr_lock);
54 126
55 /* clear persistent entry register of primary core */ 127 /* clear persistent entry register of primary core */
56 writel_relaxed(0, src_base + SRC_GPR1); 128 writel_relaxed(0, src_base + SRC_GPR1);
@@ -65,11 +137,16 @@ void __init imx_src_init(void)
65 src_base = of_iomap(np, 0); 137 src_base = of_iomap(np, 0);
66 WARN_ON(!src_base); 138 WARN_ON(!src_base);
67 139
140 imx_reset_controller.of_node = np;
141 reset_controller_register(&imx_reset_controller);
142
68 /* 143 /*
69 * force warm reset sources to generate cold reset 144 * force warm reset sources to generate cold reset
70 * for a more reliable restart 145 * for a more reliable restart
71 */ 146 */
147 spin_lock(&scr_lock);
72 val = readl_relaxed(src_base + SRC_SCR); 148 val = readl_relaxed(src_base + SRC_SCR);
73 val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE); 149 val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE);
74 writel_relaxed(val, src_base + SRC_SCR); 150 writel_relaxed(val, src_base + SRC_SCR);
151 spin_unlock(&scr_lock);
75} 152}
diff --git a/arch/arm/mach-kirkwood/guruplug-setup.c b/arch/arm/mach-kirkwood/guruplug-setup.c
index 1c6e736cbbf8..08dd739aa709 100644
--- a/arch/arm/mach-kirkwood/guruplug-setup.c
+++ b/arch/arm/mach-kirkwood/guruplug-setup.c
@@ -53,6 +53,8 @@ static struct mv_sata_platform_data guruplug_sata_data = {
53 53
54static struct mvsdio_platform_data guruplug_mvsdio_data = { 54static struct mvsdio_platform_data guruplug_mvsdio_data = {
55 /* unfortunately the CD signal has not been connected */ 55 /* unfortunately the CD signal has not been connected */
56 .gpio_card_detect = -1,
57 .gpio_write_protect = -1,
56}; 58};
57 59
58static struct gpio_led guruplug_led_pins[] = { 60static struct gpio_led guruplug_led_pins[] = {
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index 8ddd69fdc937..6a6eb548307d 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -55,6 +55,7 @@ static struct mv_sata_platform_data openrd_sata_data = {
55 55
56static struct mvsdio_platform_data openrd_mvsdio_data = { 56static struct mvsdio_platform_data openrd_mvsdio_data = {
57 .gpio_card_detect = 29, /* MPP29 used as SD card detect */ 57 .gpio_card_detect = 29, /* MPP29 used as SD card detect */
58 .gpio_write_protect = -1,
58}; 59};
59 60
60static unsigned int openrd_mpp_config[] __initdata = { 61static unsigned int openrd_mpp_config[] __initdata = {
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index c7d93b48926b..d24223166e06 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -69,6 +69,7 @@ static struct mv_sata_platform_data rd88f6281_sata_data = {
69 69
70static struct mvsdio_platform_data rd88f6281_mvsdio_data = { 70static struct mvsdio_platform_data rd88f6281_mvsdio_data = {
71 .gpio_card_detect = 28, 71 .gpio_card_detect = 28,
72 .gpio_write_protect = -1,
72}; 73};
73 74
74static unsigned int rd88f6281_mpp_config[] __initdata = { 75static unsigned int rd88f6281_mpp_config[] __initdata = {
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 2969027f02fa..f9fd77e8f1f5 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -62,7 +62,10 @@ static int msm_timer_set_next_event(unsigned long cycles,
62{ 62{
63 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); 63 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
64 64
65 writel_relaxed(0, event_base + TIMER_CLEAR); 65 ctrl &= ~TIMER_ENABLE_EN;
66 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
67
68 writel_relaxed(ctrl, event_base + TIMER_CLEAR);
66 writel_relaxed(cycles, event_base + TIMER_MATCH_VAL); 69 writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
67 writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE); 70 writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
68 return 0; 71 return 0;
diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c
index 274ff58271de..6a9195e10579 100644
--- a/arch/arm/mach-mvebu/irq-armada-370-xp.c
+++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c
@@ -44,6 +44,8 @@
44 44
45#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28) 45#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
46 46
47#define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5)
48
47#define ACTIVE_DOORBELLS (8) 49#define ACTIVE_DOORBELLS (8)
48 50
49static DEFINE_RAW_SPINLOCK(irq_controller_lock); 51static DEFINE_RAW_SPINLOCK(irq_controller_lock);
@@ -62,7 +64,7 @@ static void armada_370_xp_irq_mask(struct irq_data *d)
62#ifdef CONFIG_SMP 64#ifdef CONFIG_SMP
63 irq_hw_number_t hwirq = irqd_to_hwirq(d); 65 irq_hw_number_t hwirq = irqd_to_hwirq(d);
64 66
65 if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS) 67 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
66 writel(hwirq, main_int_base + 68 writel(hwirq, main_int_base +
67 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS); 69 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
68 else 70 else
@@ -79,7 +81,7 @@ static void armada_370_xp_irq_unmask(struct irq_data *d)
79#ifdef CONFIG_SMP 81#ifdef CONFIG_SMP
80 irq_hw_number_t hwirq = irqd_to_hwirq(d); 82 irq_hw_number_t hwirq = irqd_to_hwirq(d);
81 83
82 if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS) 84 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
83 writel(hwirq, main_int_base + 85 writel(hwirq, main_int_base +
84 ARMADA_370_XP_INT_SET_ENABLE_OFFS); 86 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
85 else 87 else
@@ -147,7 +149,7 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
147 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); 149 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
148 irq_set_status_flags(virq, IRQ_LEVEL); 150 irq_set_status_flags(virq, IRQ_LEVEL);
149 151
150 if (hw < ARMADA_370_XP_MAX_PER_CPU_IRQS) { 152 if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
151 irq_set_percpu_devid(virq); 153 irq_set_percpu_devid(virq);
152 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, 154 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
153 handle_percpu_devid_irq); 155 handle_percpu_devid_irq);
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index cb7c6ae2e3fc..6c4f766365a2 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -543,15 +543,6 @@ static struct clk usb_dc_ck = {
543 /* Direct from ULPD, no parent */ 543 /* Direct from ULPD, no parent */
544 .rate = 48000000, 544 .rate = 48000000,
545 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), 545 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
546 .enable_bit = USB_REQ_EN_SHIFT,
547};
548
549static struct clk usb_dc_ck7xx = {
550 .name = "usb_dc_ck",
551 .ops = &clkops_generic,
552 /* Direct from ULPD, no parent */
553 .rate = 48000000,
554 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
555 .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT, 546 .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT,
556}; 547};
557 548
@@ -727,8 +718,7 @@ static struct omap_clk omap_clks[] = {
727 CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310), 718 CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310),
728 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310), 719 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310),
729 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX), 720 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX),
730 CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX), 721 CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX | CK_7XX),
731 CLK(NULL, "usb_dc_ck", &usb_dc_ck7xx, CK_7XX),
732 CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310), 722 CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310),
733 CLK(NULL, "mclk", &mclk_16xx, CK_16XX), 723 CLK(NULL, "mclk", &mclk_16xx, CK_16XX),
734 CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310), 724 CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310),
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index 3d58f335f173..0c6834ae1fc4 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -52,6 +52,13 @@
52 */ 52 */
53#define OMAP4_DPLL_ABE_DEFFREQ 98304000 53#define OMAP4_DPLL_ABE_DEFFREQ 98304000
54 54
55/*
56 * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
57 * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
58 * locked frequency for the USB DPLL is 960MHz.
59 */
60#define OMAP4_DPLL_USB_DEFFREQ 960000000
61
55/* Root clocks */ 62/* Root clocks */
56 63
57DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0); 64DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
@@ -1011,6 +1018,10 @@ DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
1011 OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK, 1018 OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
1012 hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops); 1019 hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
1013 1020
1021DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
1022 OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
1023 OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
1024
1014DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0, 1025DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
1015 OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, 1026 OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
1016 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); 1027 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
@@ -1538,6 +1549,7 @@ static struct omap_clk omap44xx_clks[] = {
1538 CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk, CK_443X), 1549 CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk, CK_443X),
1539 CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk, CK_443X), 1550 CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk, CK_443X),
1540 CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk, CK_443X), 1551 CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk, CK_443X),
1552 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
1541 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), 1553 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
1542 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), 1554 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X),
1543 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), 1555 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X),
@@ -1705,5 +1717,13 @@ int __init omap4xxx_clk_init(void)
1705 if (rc) 1717 if (rc)
1706 pr_err("%s: failed to configure ABE DPLL!\n", __func__); 1718 pr_err("%s: failed to configure ABE DPLL!\n", __func__);
1707 1719
1720 /*
1721 * Lock USB DPLL on OMAP4 devices so that the L3INIT power
1722 * domain can transition to retention state when not in use.
1723 */
1724 rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
1725 if (rc)
1726 pr_err("%s: failed to configure USB DPLL!\n", __func__);
1727
1708 return 0; 1728 return 0;
1709} 1729}
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 40f4a03d728f..d6ba13e1c540 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -293,5 +293,8 @@ extern void omap_reserve(void);
293struct omap_hwmod; 293struct omap_hwmod;
294extern int omap_dss_reset(struct omap_hwmod *); 294extern int omap_dss_reset(struct omap_hwmod *);
295 295
296/* SoC specific clock initializer */
297extern int (*omap_clk_init)(void);
298
296#endif /* __ASSEMBLER__ */ 299#endif /* __ASSEMBLER__ */
297#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */ 300#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 2c3fdd65387b..5c445ca1e271 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -55,6 +55,12 @@
55#include "prm44xx.h" 55#include "prm44xx.h"
56 56
57/* 57/*
58 * omap_clk_init: points to a function that does the SoC-specific
59 * clock initializations
60 */
61int (*omap_clk_init)(void);
62
63/*
58 * The machine specific code may provide the extra mapping besides the 64 * The machine specific code may provide the extra mapping besides the
59 * default mapping provided here. 65 * default mapping provided here.
60 */ 66 */
@@ -397,7 +403,7 @@ void __init omap2420_init_early(void)
397 omap242x_clockdomains_init(); 403 omap242x_clockdomains_init();
398 omap2420_hwmod_init(); 404 omap2420_hwmod_init();
399 omap_hwmod_init_postsetup(); 405 omap_hwmod_init_postsetup();
400 omap2420_clk_init(); 406 omap_clk_init = omap2420_clk_init;
401} 407}
402 408
403void __init omap2420_init_late(void) 409void __init omap2420_init_late(void)
@@ -427,7 +433,7 @@ void __init omap2430_init_early(void)
427 omap243x_clockdomains_init(); 433 omap243x_clockdomains_init();
428 omap2430_hwmod_init(); 434 omap2430_hwmod_init();
429 omap_hwmod_init_postsetup(); 435 omap_hwmod_init_postsetup();
430 omap2430_clk_init(); 436 omap_clk_init = omap2430_clk_init;
431} 437}
432 438
433void __init omap2430_init_late(void) 439void __init omap2430_init_late(void)
@@ -462,7 +468,7 @@ void __init omap3_init_early(void)
462 omap3xxx_clockdomains_init(); 468 omap3xxx_clockdomains_init();
463 omap3xxx_hwmod_init(); 469 omap3xxx_hwmod_init();
464 omap_hwmod_init_postsetup(); 470 omap_hwmod_init_postsetup();
465 omap3xxx_clk_init(); 471 omap_clk_init = omap3xxx_clk_init;
466} 472}
467 473
468void __init omap3430_init_early(void) 474void __init omap3430_init_early(void)
@@ -500,7 +506,7 @@ void __init ti81xx_init_early(void)
500 omap3xxx_clockdomains_init(); 506 omap3xxx_clockdomains_init();
501 omap3xxx_hwmod_init(); 507 omap3xxx_hwmod_init();
502 omap_hwmod_init_postsetup(); 508 omap_hwmod_init_postsetup();
503 omap3xxx_clk_init(); 509 omap_clk_init = omap3xxx_clk_init;
504} 510}
505 511
506void __init omap3_init_late(void) 512void __init omap3_init_late(void)
@@ -568,7 +574,7 @@ void __init am33xx_init_early(void)
568 am33xx_clockdomains_init(); 574 am33xx_clockdomains_init();
569 am33xx_hwmod_init(); 575 am33xx_hwmod_init();
570 omap_hwmod_init_postsetup(); 576 omap_hwmod_init_postsetup();
571 am33xx_clk_init(); 577 omap_clk_init = am33xx_clk_init;
572} 578}
573#endif 579#endif
574 580
@@ -593,7 +599,7 @@ void __init omap4430_init_early(void)
593 omap44xx_clockdomains_init(); 599 omap44xx_clockdomains_init();
594 omap44xx_hwmod_init(); 600 omap44xx_hwmod_init();
595 omap_hwmod_init_postsetup(); 601 omap_hwmod_init_postsetup();
596 omap4xxx_clk_init(); 602 omap_clk_init = omap4xxx_clk_init;
597} 603}
598 604
599void __init omap4430_init_late(void) 605void __init omap4430_init_late(void)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index c2c798c08c2b..a202a4785104 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1368,7 +1368,9 @@ static void _enable_sysc(struct omap_hwmod *oh)
1368 } 1368 }
1369 1369
1370 if (sf & SYSC_HAS_MIDLEMODE) { 1370 if (sf & SYSC_HAS_MIDLEMODE) {
1371 if (oh->flags & HWMOD_SWSUP_MSTANDBY) { 1371 if (oh->flags & HWMOD_FORCE_MSTANDBY) {
1372 idlemode = HWMOD_IDLEMODE_FORCE;
1373 } else if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
1372 idlemode = HWMOD_IDLEMODE_NO; 1374 idlemode = HWMOD_IDLEMODE_NO;
1373 } else { 1375 } else {
1374 if (sf & SYSC_HAS_ENAWAKEUP) 1376 if (sf & SYSC_HAS_ENAWAKEUP)
@@ -1440,7 +1442,8 @@ static void _idle_sysc(struct omap_hwmod *oh)
1440 } 1442 }
1441 1443
1442 if (sf & SYSC_HAS_MIDLEMODE) { 1444 if (sf & SYSC_HAS_MIDLEMODE) {
1443 if (oh->flags & HWMOD_SWSUP_MSTANDBY) { 1445 if ((oh->flags & HWMOD_SWSUP_MSTANDBY) ||
1446 (oh->flags & HWMOD_FORCE_MSTANDBY)) {
1444 idlemode = HWMOD_IDLEMODE_FORCE; 1447 idlemode = HWMOD_IDLEMODE_FORCE;
1445 } else { 1448 } else {
1446 if (sf & SYSC_HAS_ENAWAKEUP) 1449 if (sf & SYSC_HAS_ENAWAKEUP)
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index d43d9b608eda..d5dc935f6060 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -427,8 +427,8 @@ struct omap_hwmod_omap4_prcm {
427 * 427 *
428 * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out 428 * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out
429 * of idle, rather than relying on module smart-idle 429 * of idle, rather than relying on module smart-idle
430 * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out 430 * HWMOD_SWSUP_MSTANDBY: omap_hwmod code should manually bring module in and
431 * of standby, rather than relying on module smart-standby 431 * out of standby, rather than relying on module smart-standby
432 * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for 432 * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
433 * SDRAM controller, etc. XXX probably belongs outside the main hwmod file 433 * SDRAM controller, etc. XXX probably belongs outside the main hwmod file
434 * XXX Should be HWMOD_SETUP_NO_RESET 434 * XXX Should be HWMOD_SETUP_NO_RESET
@@ -459,6 +459,10 @@ struct omap_hwmod_omap4_prcm {
459 * correctly, or this is being abused to deal with some PM latency 459 * correctly, or this is being abused to deal with some PM latency
460 * issues -- but we're currently suffering from a shortage of 460 * issues -- but we're currently suffering from a shortage of
461 * folks who are able to track these issues down properly. 461 * folks who are able to track these issues down properly.
462 * HWMOD_FORCE_MSTANDBY: Always keep MIDLEMODE bits cleared so that device
463 * is kept in force-standby mode. Failing to do so causes PM problems
464 * with musb on OMAP3630 at least. Note that musb has a dedicated register
465 * to control MSTANDBY signal when MIDLEMODE is set to force-standby.
462 */ 466 */
463#define HWMOD_SWSUP_SIDLE (1 << 0) 467#define HWMOD_SWSUP_SIDLE (1 << 0)
464#define HWMOD_SWSUP_MSTANDBY (1 << 1) 468#define HWMOD_SWSUP_MSTANDBY (1 << 1)
@@ -471,6 +475,7 @@ struct omap_hwmod_omap4_prcm {
471#define HWMOD_16BIT_REG (1 << 8) 475#define HWMOD_16BIT_REG (1 << 8)
472#define HWMOD_EXT_OPT_MAIN_CLK (1 << 9) 476#define HWMOD_EXT_OPT_MAIN_CLK (1 << 9)
473#define HWMOD_BLOCK_WFI (1 << 10) 477#define HWMOD_BLOCK_WFI (1 << 10)
478#define HWMOD_FORCE_MSTANDBY (1 << 11)
474 479
475/* 480/*
476 * omap_hwmod._int_flags definitions 481 * omap_hwmod._int_flags definitions
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index ac7e03ec952f..5112d04e7b79 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1707,9 +1707,14 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1707 * Erratum ID: i479 idle_req / idle_ack mechanism potentially 1707 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1708 * broken when autoidle is enabled 1708 * broken when autoidle is enabled
1709 * workaround is to disable the autoidle bit at module level. 1709 * workaround is to disable the autoidle bit at module level.
1710 *
1711 * Enabling the device in any other MIDLEMODE setting but force-idle
1712 * causes core_pwrdm not enter idle states at least on OMAP3630.
1713 * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
1714 * signal when MIDLEMODE is set to force-idle.
1710 */ 1715 */
1711 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE 1716 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1712 | HWMOD_SWSUP_MSTANDBY, 1717 | HWMOD_FORCE_MSTANDBY,
1713}; 1718};
1714 1719
1715/* usb_otg_hs */ 1720/* usb_otg_hs */
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 0e47d2e1687c..9e0576569e07 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -2714,6 +2714,10 @@ static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
2714 { } 2714 { }
2715}; 2715};
2716 2716
2717static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
2718 { .role = "48mhz", .clk = "ocp2scp_usb_phy_phy_48m" },
2719};
2720
2717/* ocp2scp_usb_phy */ 2721/* ocp2scp_usb_phy */
2718static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { 2722static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2719 .name = "ocp2scp_usb_phy", 2723 .name = "ocp2scp_usb_phy",
@@ -2728,6 +2732,8 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2728 }, 2732 },
2729 }, 2733 },
2730 .dev_attr = ocp2scp_dev_attr, 2734 .dev_attr = ocp2scp_dev_attr,
2735 .opt_clks = ocp2scp_usb_phy_opt_clks,
2736 .opt_clks_cnt = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
2731}; 2737};
2732 2738
2733/* 2739/*
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 4fd80257c73e..ee7a6bf67c9e 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -547,6 +547,8 @@ static inline void __init realtime_counter_init(void)
547 clksrc_nr, clksrc_src) \ 547 clksrc_nr, clksrc_src) \
548void __init omap##name##_gptimer_timer_init(void) \ 548void __init omap##name##_gptimer_timer_init(void) \
549{ \ 549{ \
550 if (omap_clk_init) \
551 omap_clk_init(); \
550 omap_dmtimer_init(); \ 552 omap_dmtimer_init(); \
551 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ 553 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
552 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src); \ 554 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src); \
@@ -556,6 +558,8 @@ void __init omap##name##_gptimer_timer_init(void) \
556 clksrc_nr, clksrc_src) \ 558 clksrc_nr, clksrc_src) \
557void __init omap##name##_sync32k_timer_init(void) \ 559void __init omap##name##_sync32k_timer_init(void) \
558{ \ 560{ \
561 if (omap_clk_init) \
562 omap_clk_init(); \
559 omap_dmtimer_init(); \ 563 omap_dmtimer_init(); \
560 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ 564 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
561 /* Enable the use of clocksource="gp_timer" kernel parameter */ \ 565 /* Enable the use of clocksource="gp_timer" kernel parameter */ \
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 051b62c27102..7f2cb6c5e2c1 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -81,7 +81,6 @@ static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
81#endif 81#endif
82 82
83struct mmci_platform_data mop500_sdi0_data = { 83struct mmci_platform_data mop500_sdi0_data = {
84 .ios_handler = mop500_sdi0_ios_handler,
85 .ocr_mask = MMC_VDD_29_30, 84 .ocr_mask = MMC_VDD_29_30,
86 .f_max = 50000000, 85 .f_max = 50000000,
87 .capabilities = MMC_CAP_4_BIT_DATA | 86 .capabilities = MMC_CAP_4_BIT_DATA |
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index b03457881c4b..87d2d7b38ce9 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -12,6 +12,7 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/interrupt.h> 13#include <linux/interrupt.h>
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/clk.h>
15#include <linux/io.h> 16#include <linux/io.h>
16#include <linux/i2c.h> 17#include <linux/i2c.h>
17#include <linux/platform_data/i2c-nomadik.h> 18#include <linux/platform_data/i2c-nomadik.h>
@@ -439,6 +440,15 @@ static void mop500_prox_deactivate(struct device *dev)
439 regulator_put(prox_regulator); 440 regulator_put(prox_regulator);
440} 441}
441 442
443void mop500_snowball_ethernet_clock_enable(void)
444{
445 struct clk *clk;
446
447 clk = clk_get_sys("fsmc", NULL);
448 if (!IS_ERR(clk))
449 clk_prepare_enable(clk);
450}
451
442static struct cryp_platform_data u8500_cryp1_platform_data = { 452static struct cryp_platform_data u8500_cryp1_platform_data = {
443 .mem_to_engine = { 453 .mem_to_engine = {
444 .dir = STEDMA40_MEM_TO_PERIPH, 454 .dir = STEDMA40_MEM_TO_PERIPH,
@@ -683,6 +693,8 @@ static void __init snowball_init_machine(void)
683 mop500_audio_init(parent); 693 mop500_audio_init(parent);
684 mop500_uart_init(parent); 694 mop500_uart_init(parent);
685 695
696 mop500_snowball_ethernet_clock_enable();
697
686 /* This board has full regulator constraints */ 698 /* This board has full regulator constraints */
687 regulator_has_full_constraints(); 699 regulator_has_full_constraints();
688} 700}
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index eaa605f5d90d..d38951be70df 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -104,6 +104,7 @@ void __init mop500_pinmaps_init(void);
104void __init snowball_pinmaps_init(void); 104void __init snowball_pinmaps_init(void);
105void __init hrefv60_pinmaps_init(void); 105void __init hrefv60_pinmaps_init(void);
106void mop500_audio_init(struct device *parent); 106void mop500_audio_init(struct device *parent);
107void mop500_snowball_ethernet_clock_enable(void);
107 108
108int __init mop500_uib_init(void); 109int __init mop500_uib_init(void);
109void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info, 110void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 19235cf7bbe3..f1a581844372 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -312,9 +312,10 @@ static void __init u8500_init_machine(void)
312 /* Pinmaps must be in place before devices register */ 312 /* Pinmaps must be in place before devices register */
313 if (of_machine_is_compatible("st-ericsson,mop500")) 313 if (of_machine_is_compatible("st-ericsson,mop500"))
314 mop500_pinmaps_init(); 314 mop500_pinmaps_init();
315 else if (of_machine_is_compatible("calaosystems,snowball-a9500")) 315 else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
316 snowball_pinmaps_init(); 316 snowball_pinmaps_init();
317 else if (of_machine_is_compatible("st-ericsson,hrefv60+")) 317 mop500_snowball_ethernet_clock_enable();
318 } else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
318 hrefv60_pinmaps_init(); 319 hrefv60_pinmaps_init();
319 else if (of_machine_is_compatible("st-ericsson,ccu9540")) {} 320 else if (of_machine_is_compatible("st-ericsson,ccu9540")) {}
320 /* TODO: Add pinmaps for ccu9540 board. */ 321 /* TODO: Add pinmaps for ccu9540 board. */
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index c2f37390308a..c465faca51b0 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -299,7 +299,7 @@ static void l2x0_unlock(u32 cache_id)
299 int lockregs; 299 int lockregs;
300 int i; 300 int i;
301 301
302 switch (cache_id) { 302 switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
303 case L2X0_CACHE_ID_PART_L310: 303 case L2X0_CACHE_ID_PART_L310:
304 lockregs = 8; 304 lockregs = 8;
305 break; 305 break;
@@ -333,15 +333,14 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
333 if (cache_id_part_number_from_dt) 333 if (cache_id_part_number_from_dt)
334 cache_id = cache_id_part_number_from_dt; 334 cache_id = cache_id_part_number_from_dt;
335 else 335 else
336 cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID) 336 cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
337 & L2X0_CACHE_ID_PART_MASK;
338 aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); 337 aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
339 338
340 aux &= aux_mask; 339 aux &= aux_mask;
341 aux |= aux_val; 340 aux |= aux_val;
342 341
343 /* Determine the number of ways */ 342 /* Determine the number of ways */
344 switch (cache_id) { 343 switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
345 case L2X0_CACHE_ID_PART_L310: 344 case L2X0_CACHE_ID_PART_L310:
346 if (aux & (1 << 16)) 345 if (aux & (1 << 16))
347 ways = 16; 346 ways = 16;
@@ -725,7 +724,6 @@ static const struct l2x0_of_data pl310_data = {
725 .flush_all = l2x0_flush_all, 724 .flush_all = l2x0_flush_all,
726 .inv_all = l2x0_inv_all, 725 .inv_all = l2x0_inv_all,
727 .disable = l2x0_disable, 726 .disable = l2x0_disable,
728 .set_debug = pl310_set_debug,
729 }, 727 },
730}; 728};
731 729
@@ -814,9 +812,8 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
814 data->save(); 812 data->save();
815 813
816 of_init = true; 814 of_init = true;
817 l2x0_init(l2x0_base, aux_val, aux_mask);
818
819 memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache)); 815 memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache));
816 l2x0_init(l2x0_base, aux_val, aux_mask);
820 817
821 return 0; 818 return 0;
822} 819}
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index a5a4b2bc42ba..2ac37372ef52 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -48,7 +48,7 @@ static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
48static atomic64_t asid_generation = ATOMIC64_INIT(ASID_FIRST_VERSION); 48static atomic64_t asid_generation = ATOMIC64_INIT(ASID_FIRST_VERSION);
49static DECLARE_BITMAP(asid_map, NUM_USER_ASIDS); 49static DECLARE_BITMAP(asid_map, NUM_USER_ASIDS);
50 50
51static DEFINE_PER_CPU(atomic64_t, active_asids); 51DEFINE_PER_CPU(atomic64_t, active_asids);
52static DEFINE_PER_CPU(u64, reserved_asids); 52static DEFINE_PER_CPU(u64, reserved_asids);
53static cpumask_t tlb_flush_pending; 53static cpumask_t tlb_flush_pending;
54 54
@@ -215,6 +215,7 @@ void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk)
215 if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending)) { 215 if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending)) {
216 local_flush_bp_all(); 216 local_flush_bp_all();
217 local_flush_tlb_all(); 217 local_flush_tlb_all();
218 dummy_flush_tlb_a15_erratum();
218 } 219 }
219 220
220 atomic64_set(&per_cpu(active_asids, cpu), asid); 221 atomic64_set(&per_cpu(active_asids, cpu), asid);
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index e95a996ab78f..78978945492a 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -598,39 +598,60 @@ static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
598 } while (pte++, addr += PAGE_SIZE, addr != end); 598 } while (pte++, addr += PAGE_SIZE, addr != end);
599} 599}
600 600
601static void __init alloc_init_section(pud_t *pud, unsigned long addr, 601static void __init map_init_section(pmd_t *pmd, unsigned long addr,
602 unsigned long end, phys_addr_t phys, 602 unsigned long end, phys_addr_t phys,
603 const struct mem_type *type) 603 const struct mem_type *type)
604{ 604{
605 pmd_t *pmd = pmd_offset(pud, addr); 605#ifndef CONFIG_ARM_LPAE
606
607 /* 606 /*
608 * Try a section mapping - end, addr and phys must all be aligned 607 * In classic MMU format, puds and pmds are folded in to
609 * to a section boundary. Note that PMDs refer to the individual 608 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
610 * L1 entries, whereas PGDs refer to a group of L1 entries making 609 * group of L1 entries making up one logical pointer to
611 * up one logical pointer to an L2 table. 610 * an L2 table (2MB), where as PMDs refer to the individual
611 * L1 entries (1MB). Hence increment to get the correct
612 * offset for odd 1MB sections.
613 * (See arch/arm/include/asm/pgtable-2level.h)
612 */ 614 */
613 if (type->prot_sect && ((addr | end | phys) & ~SECTION_MASK) == 0) { 615 if (addr & SECTION_SIZE)
614 pmd_t *p = pmd; 616 pmd++;
615
616#ifndef CONFIG_ARM_LPAE
617 if (addr & SECTION_SIZE)
618 pmd++;
619#endif 617#endif
618 do {
619 *pmd = __pmd(phys | type->prot_sect);
620 phys += SECTION_SIZE;
621 } while (pmd++, addr += SECTION_SIZE, addr != end);
620 622
621 do { 623 flush_pmd_entry(pmd);
622 *pmd = __pmd(phys | type->prot_sect); 624}
623 phys += SECTION_SIZE;
624 } while (pmd++, addr += SECTION_SIZE, addr != end);
625 625
626 flush_pmd_entry(p); 626static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
627 } else { 627 unsigned long end, phys_addr_t phys,
628 const struct mem_type *type)
629{
630 pmd_t *pmd = pmd_offset(pud, addr);
631 unsigned long next;
632
633 do {
628 /* 634 /*
629 * No need to loop; pte's aren't interested in the 635 * With LPAE, we must loop over to map
630 * individual L1 entries. 636 * all the pmds for the given range.
631 */ 637 */
632 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type); 638 next = pmd_addr_end(addr, end);
633 } 639
640 /*
641 * Try a section mapping - addr, next and phys must all be
642 * aligned to a section boundary.
643 */
644 if (type->prot_sect &&
645 ((addr | next | phys) & ~SECTION_MASK) == 0) {
646 map_init_section(pmd, addr, next, phys, type);
647 } else {
648 alloc_init_pte(pmd, addr, next,
649 __phys_to_pfn(phys), type);
650 }
651
652 phys += next - addr;
653
654 } while (pmd++, addr = next, addr != end);
634} 655}
635 656
636static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr, 657static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
@@ -641,7 +662,7 @@ static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
641 662
642 do { 663 do {
643 next = pud_addr_end(addr, end); 664 next = pud_addr_end(addr, end);
644 alloc_init_section(pud, addr, next, phys, type); 665 alloc_init_pmd(pud, addr, next, phys, type);
645 phys += next - addr; 666 phys += next - addr;
646 } while (pud++, addr = next, addr != end); 667 } while (pud++, addr = next, addr != end);
647} 668}
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 3a3c015f8d5c..f584d3f5b37c 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -420,7 +420,7 @@ __v7_pj4b_proc_info:
420__v7_ca7mp_proc_info: 420__v7_ca7mp_proc_info:
421 .long 0x410fc070 421 .long 0x410fc070
422 .long 0xff0ffff0 422 .long 0xff0ffff0
423 __v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV 423 __v7_proc __v7_ca7mp_setup
424 .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info 424 .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
425 425
426 /* 426 /*
@@ -430,10 +430,25 @@ __v7_ca7mp_proc_info:
430__v7_ca15mp_proc_info: 430__v7_ca15mp_proc_info:
431 .long 0x410fc0f0 431 .long 0x410fc0f0
432 .long 0xff0ffff0 432 .long 0xff0ffff0
433 __v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV 433 __v7_proc __v7_ca15mp_setup
434 .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info 434 .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
435 435
436 /* 436 /*
437 * Qualcomm Inc. Krait processors.
438 */
439 .type __krait_proc_info, #object
440__krait_proc_info:
441 .long 0x510f0400 @ Required ID value
442 .long 0xff0ffc00 @ Mask for ID
443 /*
444 * Some Krait processors don't indicate support for SDIV and UDIV
445 * instructions in the ARM instruction set, even though they actually
446 * do support them.
447 */
448 __v7_proc __v7_setup, hwcaps = HWCAP_IDIV
449 .size __krait_proc_info, . - __krait_proc_info
450
451 /*
437 * Match any ARMv7 processor core. 452 * Match any ARMv7 processor core.
438 */ 453 */
439 .type __v7_proc_info, #object 454 .type __v7_proc_info, #object
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-14 19:53:19 -0500