diff options
| author | Heiko Stuebner <heiko@sntech.de> | 2015-05-13 09:47:03 -0400 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2015-05-13 09:47:03 -0400 |
| commit | 3f937cf3db466093c533efbcd601952509727a9d (patch) | |
| tree | 1bf06e4dfdbb1487cc40c17fd13509ea2077910d /arch/arm | |
| parent | 2a9fe3ca84afff6259820c4f62e579f41476becc (diff) | |
Revert "ARM: rockchip: fix undefined instruction of reset_ctrl_regs"
This reverts commit b403125d3bbf8046c1186e1a49cb17bb5551db14.
As reported by Chris, both commits
b403125 "ARM: rockchip: fix undefined instruction of reset_ctrl_regs"
0ea001d "ARM: rockchip: disable dapswjdp during suspend"
actually fix the same issue and b403125 is the older one, which got
superseded by 0ea001d. Therefore revert the obsolete one again.
Reported-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-rockchip/pm.c | 26 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/pm.h | 4 |
2 files changed, 0 insertions, 30 deletions
diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c index 22812fe06460..b0dcbe28f78c 100644 --- a/arch/arm/mach-rockchip/pm.c +++ b/arch/arm/mach-rockchip/pm.c | |||
| @@ -44,11 +44,9 @@ static void __iomem *rk3288_bootram_base; | |||
| 44 | static phys_addr_t rk3288_bootram_phy; | 44 | static phys_addr_t rk3288_bootram_phy; |
| 45 | 45 | ||
| 46 | static struct regmap *pmu_regmap; | 46 | static struct regmap *pmu_regmap; |
| 47 | static struct regmap *grf_regmap; | ||
| 48 | static struct regmap *sgrf_regmap; | 47 | static struct regmap *sgrf_regmap; |
| 49 | 48 | ||
| 50 | static u32 rk3288_pmu_pwr_mode_con; | 49 | static u32 rk3288_pmu_pwr_mode_con; |
| 51 | static u32 rk3288_grf_soc_con0; | ||
| 52 | static u32 rk3288_sgrf_soc_con0; | 50 | static u32 rk3288_sgrf_soc_con0; |
| 53 | 51 | ||
| 54 | static inline u32 rk3288_l2_config(void) | 52 | static inline u32 rk3288_l2_config(void) |
| @@ -72,26 +70,12 @@ static void rk3288_slp_mode_set(int level) | |||
| 72 | { | 70 | { |
| 73 | u32 mode_set, mode_set1; | 71 | u32 mode_set, mode_set1; |
| 74 | 72 | ||
| 75 | regmap_read(grf_regmap, RK3288_GRF_SOC_CON0, &rk3288_grf_soc_con0); | ||
| 76 | |||
| 77 | regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0); | 73 | regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0); |
| 78 | 74 | ||
| 79 | regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON, | 75 | regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON, |
| 80 | &rk3288_pmu_pwr_mode_con); | 76 | &rk3288_pmu_pwr_mode_con); |
| 81 | 77 | ||
| 82 | /* | 78 | /* |
| 83 | * We need set this bit GRF_FORCE_JTAG here, for the debug module, | ||
| 84 | * otherwise, it may become inaccessible after resume. | ||
| 85 | * This creates a potential security issue, as the sdmmc pins may | ||
| 86 | * accept jtag data for a short time during resume if no card is | ||
| 87 | * inserted. | ||
| 88 | * But this is of course also true for the regular boot, before we | ||
| 89 | * turn of the jtag/sdmmc autodetect. | ||
| 90 | */ | ||
| 91 | regmap_write(grf_regmap, RK3288_GRF_SOC_CON0, GRF_FORCE_JTAG | | ||
| 92 | GRF_FORCE_JTAG_WRITE); | ||
| 93 | |||
| 94 | /* | ||
| 95 | * SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR | 79 | * SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR |
| 96 | * PCLK_WDT_GATE - disable WDT during suspend. | 80 | * PCLK_WDT_GATE - disable WDT during suspend. |
| 97 | */ | 81 | */ |
| @@ -151,9 +135,6 @@ static void rk3288_slp_mode_set_resume(void) | |||
| 151 | regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0, | 135 | regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0, |
| 152 | rk3288_sgrf_soc_con0 | SGRF_PCLK_WDT_GATE_WRITE | 136 | rk3288_sgrf_soc_con0 | SGRF_PCLK_WDT_GATE_WRITE |
| 153 | | SGRF_FAST_BOOT_EN_WRITE); | 137 | | SGRF_FAST_BOOT_EN_WRITE); |
| 154 | |||
| 155 | regmap_write(grf_regmap, RK3288_GRF_SOC_CON0, rk3288_grf_soc_con0 | | ||
| 156 | GRF_FORCE_JTAG_WRITE); | ||
| 157 | } | 138 | } |
| 158 | 139 | ||
| 159 | static int rockchip_lpmode_enter(unsigned long arg) | 140 | static int rockchip_lpmode_enter(unsigned long arg) |
| @@ -212,13 +193,6 @@ static int rk3288_suspend_init(struct device_node *np) | |||
| 212 | return PTR_ERR(pmu_regmap); | 193 | return PTR_ERR(pmu_regmap); |
| 213 | } | 194 | } |
| 214 | 195 | ||
| 215 | grf_regmap = syscon_regmap_lookup_by_compatible( | ||
| 216 | "rockchip,rk3288-grf"); | ||
| 217 | if (IS_ERR(grf_regmap)) { | ||
| 218 | pr_err("%s: could not find grf regmap\n", __func__); | ||
| 219 | return PTR_ERR(pmu_regmap); | ||
| 220 | } | ||
| 221 | |||
| 222 | sram_np = of_find_compatible_node(NULL, NULL, | 196 | sram_np = of_find_compatible_node(NULL, NULL, |
| 223 | "rockchip,rk3288-pmu-sram"); | 197 | "rockchip,rk3288-pmu-sram"); |
| 224 | if (!sram_np) { | 198 | if (!sram_np) { |
diff --git a/arch/arm/mach-rockchip/pm.h b/arch/arm/mach-rockchip/pm.h index f8a747bc1437..3e8d39c0c3d5 100644 --- a/arch/arm/mach-rockchip/pm.h +++ b/arch/arm/mach-rockchip/pm.h | |||
| @@ -48,10 +48,6 @@ static inline void rockchip_suspend_init(void) | |||
| 48 | #define RK3288_PMU_WAKEUP_RST_CLR_CNT 0x44 | 48 | #define RK3288_PMU_WAKEUP_RST_CLR_CNT 0x44 |
| 49 | #define RK3288_PMU_PWRMODE_CON1 0x90 | 49 | #define RK3288_PMU_PWRMODE_CON1 0x90 |
| 50 | 50 | ||
| 51 | #define RK3288_GRF_SOC_CON0 0x244 | ||
| 52 | #define GRF_FORCE_JTAG BIT(12) | ||
| 53 | #define GRF_FORCE_JTAG_WRITE BIT(28) | ||
| 54 | |||
| 55 | #define RK3288_SGRF_SOC_CON0 (0x0000) | 51 | #define RK3288_SGRF_SOC_CON0 (0x0000) |
| 56 | #define RK3288_SGRF_FAST_BOOT_ADDR (0x0120) | 52 | #define RK3288_SGRF_FAST_BOOT_ADDR (0x0120) |
| 57 | #define SGRF_PCLK_WDT_GATE BIT(6) | 53 | #define SGRF_PCLK_WDT_GATE BIT(6) |