diff options
author | Grant Likely <grant.likely@secretlab.ca> | 2012-02-27 16:04:40 -0500 |
---|---|---|
committer | Grant Likely <grant.likely@secretlab.ca> | 2012-02-27 16:04:40 -0500 |
commit | 29f141fed01a09050207c4d41fc5811520d81146 (patch) | |
tree | c55a51dca4a0e4da9fdc2b904eefbde37d2a5b03 /arch/arm | |
parent | 2261cc627f5453004042b4f694612edae27e492e (diff) | |
parent | 14cd3c15cfc8118586262a79bfa3b3123f13e2c2 (diff) |
Merge branch 'fixes-for-grant' of git://sources.calxeda.com/kernel/linux into devicetree/merge
Diffstat (limited to 'arch/arm')
244 files changed, 1739 insertions, 2820 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 24626b0419ee..a48aecc17eac 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -754,7 +754,7 @@ config ARCH_SA1100 | |||
754 | select ARCH_HAS_CPUFREQ | 754 | select ARCH_HAS_CPUFREQ |
755 | select CPU_FREQ | 755 | select CPU_FREQ |
756 | select GENERIC_CLOCKEVENTS | 756 | select GENERIC_CLOCKEVENTS |
757 | select CLKDEV_LOOKUP | 757 | select HAVE_CLK |
758 | select HAVE_SCHED_CLOCK | 758 | select HAVE_SCHED_CLOCK |
759 | select TICK_ONESHOT | 759 | select TICK_ONESHOT |
760 | select ARCH_REQUIRE_GPIOLIB | 760 | select ARCH_REQUIRE_GPIOLIB |
@@ -825,7 +825,6 @@ config ARCH_S5PC100 | |||
825 | select HAVE_CLK | 825 | select HAVE_CLK |
826 | select CLKDEV_LOOKUP | 826 | select CLKDEV_LOOKUP |
827 | select CPU_V7 | 827 | select CPU_V7 |
828 | select ARM_L1_CACHE_SHIFT_6 | ||
829 | select ARCH_USES_GETTIMEOFFSET | 828 | select ARCH_USES_GETTIMEOFFSET |
830 | select HAVE_S3C2410_I2C if I2C | 829 | select HAVE_S3C2410_I2C if I2C |
831 | select HAVE_S3C_RTC if RTC_CLASS | 830 | select HAVE_S3C_RTC if RTC_CLASS |
@@ -842,7 +841,6 @@ config ARCH_S5PV210 | |||
842 | select HAVE_CLK | 841 | select HAVE_CLK |
843 | select CLKDEV_LOOKUP | 842 | select CLKDEV_LOOKUP |
844 | select CLKSRC_MMIO | 843 | select CLKSRC_MMIO |
845 | select ARM_L1_CACHE_SHIFT_6 | ||
846 | select ARCH_HAS_CPUFREQ | 844 | select ARCH_HAS_CPUFREQ |
847 | select GENERIC_CLOCKEVENTS | 845 | select GENERIC_CLOCKEVENTS |
848 | select HAVE_SCHED_CLOCK | 846 | select HAVE_SCHED_CLOCK |
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 40319d91bb7f..1683bfb9166f 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
@@ -160,7 +160,6 @@ machine-$(CONFIG_ARCH_MSM) := msm | |||
160 | machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 | 160 | machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 |
161 | machine-$(CONFIG_ARCH_IMX_V4_V5) := imx | 161 | machine-$(CONFIG_ARCH_IMX_V4_V5) := imx |
162 | machine-$(CONFIG_ARCH_IMX_V6_V7) := imx | 162 | machine-$(CONFIG_ARCH_IMX_V6_V7) := imx |
163 | machine-$(CONFIG_ARCH_MX5) := mx5 | ||
164 | machine-$(CONFIG_ARCH_MXS) := mxs | 163 | machine-$(CONFIG_ARCH_MXS) := mxs |
165 | machine-$(CONFIG_ARCH_NETX) := netx | 164 | machine-$(CONFIG_ARCH_NETX) := netx |
166 | machine-$(CONFIG_ARCH_NOMADIK) := nomadik | 165 | machine-$(CONFIG_ARCH_NOMADIK) := nomadik |
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 63d7578856c1..a1dd2ee83753 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi | |||
@@ -29,6 +29,7 @@ | |||
29 | compatible = "arm,cortex-a9-gic"; | 29 | compatible = "arm,cortex-a9-gic"; |
30 | #interrupt-cells = <3>; | 30 | #interrupt-cells = <3>; |
31 | interrupt-controller; | 31 | interrupt-controller; |
32 | cpu-offset = <0x8000>; | ||
32 | reg = <0x10490000 0x1000>, <0x10480000 0x100>; | 33 | reg = <0x10490000 0x1000>, <0x10480000 0x100>; |
33 | }; | 34 | }; |
34 | 35 | ||
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts index 1a1d7023b69b..825d2957da0b 100644 --- a/arch/arm/boot/dts/tegra-paz00.dts +++ b/arch/arm/boot/dts/tegra-paz00.dts | |||
@@ -46,11 +46,11 @@ | |||
46 | }; | 46 | }; |
47 | 47 | ||
48 | serial@70006200 { | 48 | serial@70006200 { |
49 | status = "disable"; | 49 | clock-frequency = <216000000>; |
50 | }; | 50 | }; |
51 | 51 | ||
52 | serial@70006300 { | 52 | serial@70006300 { |
53 | clock-frequency = <216000000>; | 53 | status = "disable"; |
54 | }; | 54 | }; |
55 | 55 | ||
56 | serial@70006400 { | 56 | serial@70006400 { |
@@ -60,7 +60,7 @@ | |||
60 | sdhci@c8000000 { | 60 | sdhci@c8000000 { |
61 | cd-gpios = <&gpio 173 0>; /* gpio PV5 */ | 61 | cd-gpios = <&gpio 173 0>; /* gpio PV5 */ |
62 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ | 62 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ |
63 | power-gpios = <&gpio 155 0>; /* gpio PT3 */ | 63 | power-gpios = <&gpio 169 0>; /* gpio PV1 */ |
64 | }; | 64 | }; |
65 | 65 | ||
66 | sdhci@c8000200 { | 66 | sdhci@c8000200 { |
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index b2dc2dd7f1df..c47d6199b784 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c | |||
@@ -41,6 +41,7 @@ | |||
41 | 41 | ||
42 | #include <asm/irq.h> | 42 | #include <asm/irq.h> |
43 | #include <asm/exception.h> | 43 | #include <asm/exception.h> |
44 | #include <asm/smp_plat.h> | ||
44 | #include <asm/mach/irq.h> | 45 | #include <asm/mach/irq.h> |
45 | #include <asm/hardware/gic.h> | 46 | #include <asm/hardware/gic.h> |
46 | 47 | ||
@@ -352,11 +353,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic) | |||
352 | unsigned int gic_irqs = gic->gic_irqs; | 353 | unsigned int gic_irqs = gic->gic_irqs; |
353 | struct irq_domain *domain = &gic->domain; | 354 | struct irq_domain *domain = &gic->domain; |
354 | void __iomem *base = gic_data_dist_base(gic); | 355 | void __iomem *base = gic_data_dist_base(gic); |
355 | u32 cpu = 0; | 356 | u32 cpu = cpu_logical_map(smp_processor_id()); |
356 | |||
357 | #ifdef CONFIG_SMP | ||
358 | cpu = cpu_logical_map(smp_processor_id()); | ||
359 | #endif | ||
360 | 357 | ||
361 | cpumask = 1 << cpu; | 358 | cpumask = 1 << cpu; |
362 | cpumask |= cpumask << 8; | 359 | cpumask |= cpumask << 8; |
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c index d1bcd7b13ebc..fb1f1cfce60c 100644 --- a/arch/arm/common/it8152.c +++ b/arch/arm/common/it8152.c | |||
@@ -320,13 +320,6 @@ err0: | |||
320 | return -EBUSY; | 320 | return -EBUSY; |
321 | } | 321 | } |
322 | 322 | ||
323 | /* | ||
324 | * If we set up a device for bus mastering, we need to check the latency | ||
325 | * timer as we don't have even crappy BIOSes to set it properly. | ||
326 | * The implementation is from arch/i386/pci/i386.c | ||
327 | */ | ||
328 | unsigned int pcibios_max_latency = 255; | ||
329 | |||
330 | /* ITE bridge requires setting latency timer to avoid early bus access | 323 | /* ITE bridge requires setting latency timer to avoid early bus access |
331 | termination by PCI bus master devices | 324 | termination by PCI bus master devices |
332 | */ | 325 | */ |
diff --git a/arch/arm/common/pl330.c b/arch/arm/common/pl330.c index d8e44a43047c..ff3ad2244824 100644 --- a/arch/arm/common/pl330.c +++ b/arch/arm/common/pl330.c | |||
@@ -1502,12 +1502,13 @@ int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op) | |||
1502 | struct pl330_thread *thrd = ch_id; | 1502 | struct pl330_thread *thrd = ch_id; |
1503 | struct pl330_dmac *pl330; | 1503 | struct pl330_dmac *pl330; |
1504 | unsigned long flags; | 1504 | unsigned long flags; |
1505 | int ret = 0, active = thrd->req_running; | 1505 | int ret = 0, active; |
1506 | 1506 | ||
1507 | if (!thrd || thrd->free || thrd->dmac->state == DYING) | 1507 | if (!thrd || thrd->free || thrd->dmac->state == DYING) |
1508 | return -EINVAL; | 1508 | return -EINVAL; |
1509 | 1509 | ||
1510 | pl330 = thrd->dmac; | 1510 | pl330 = thrd->dmac; |
1511 | active = thrd->req_running; | ||
1511 | 1512 | ||
1512 | spin_lock_irqsave(&pl330->lock, flags); | 1513 | spin_lock_irqsave(&pl330->lock, flags); |
1513 | 1514 | ||
diff --git a/arch/arm/configs/mx5_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index d0d8dfece37e..3a4fb2e5fc68 100644 --- a/arch/arm/configs/mx5_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig | |||
@@ -3,6 +3,7 @@ CONFIG_EXPERIMENTAL=y | |||
3 | CONFIG_KERNEL_LZO=y | 3 | CONFIG_KERNEL_LZO=y |
4 | CONFIG_SYSVIPC=y | 4 | CONFIG_SYSVIPC=y |
5 | CONFIG_LOG_BUF_SHIFT=18 | 5 | CONFIG_LOG_BUF_SHIFT=18 |
6 | CONFIG_CGROUPS=y | ||
6 | CONFIG_RELAY=y | 7 | CONFIG_RELAY=y |
7 | CONFIG_EXPERT=y | 8 | CONFIG_EXPERT=y |
8 | # CONFIG_SLUB_DEBUG is not set | 9 | # CONFIG_SLUB_DEBUG is not set |
@@ -14,20 +15,31 @@ CONFIG_MODULE_SRCVERSION_ALL=y | |||
14 | # CONFIG_LBDAF is not set | 15 | # CONFIG_LBDAF is not set |
15 | # CONFIG_BLK_DEV_BSG is not set | 16 | # CONFIG_BLK_DEV_BSG is not set |
16 | CONFIG_ARCH_MXC=y | 17 | CONFIG_ARCH_MXC=y |
17 | CONFIG_ARCH_MX5=y | 18 | CONFIG_MACH_MX31LILLY=y |
18 | CONFIG_MACH_MX51_BABBAGE=y | 19 | CONFIG_MACH_MX31LITE=y |
20 | CONFIG_MACH_PCM037=y | ||
21 | CONFIG_MACH_PCM037_EET=y | ||
22 | CONFIG_MACH_MX31_3DS=y | ||
23 | CONFIG_MACH_MX31MOBOARD=y | ||
24 | CONFIG_MACH_QONG=y | ||
25 | CONFIG_MACH_ARMADILLO5X0=y | ||
26 | CONFIG_MACH_KZM_ARM11_01=y | ||
27 | CONFIG_MACH_PCM043=y | ||
28 | CONFIG_MACH_MX35_3DS=y | ||
29 | CONFIG_MACH_EUKREA_CPUIMX35=y | ||
30 | CONFIG_MACH_VPR200=y | ||
31 | CONFIG_MACH_IMX51_DT=y | ||
19 | CONFIG_MACH_MX51_3DS=y | 32 | CONFIG_MACH_MX51_3DS=y |
20 | CONFIG_MACH_EUKREA_CPUIMX51=y | 33 | CONFIG_MACH_EUKREA_CPUIMX51=y |
21 | CONFIG_MACH_EUKREA_CPUIMX51SD=y | 34 | CONFIG_MACH_EUKREA_CPUIMX51SD=y |
22 | CONFIG_MACH_MX51_EFIKAMX=y | 35 | CONFIG_MACH_MX51_EFIKAMX=y |
23 | CONFIG_MACH_MX51_EFIKASB=y | 36 | CONFIG_MACH_MX51_EFIKASB=y |
24 | CONFIG_MACH_MX53_EVK=y | 37 | CONFIG_MACH_IMX53_DT=y |
25 | CONFIG_MACH_MX53_SMD=y | 38 | CONFIG_SOC_IMX6Q=y |
26 | CONFIG_MACH_MX53_LOCO=y | ||
27 | CONFIG_MACH_MX53_ARD=y | ||
28 | CONFIG_MXC_PWM=y | 39 | CONFIG_MXC_PWM=y |
29 | CONFIG_NO_HZ=y | 40 | CONFIG_NO_HZ=y |
30 | CONFIG_HIGH_RES_TIMERS=y | 41 | CONFIG_HIGH_RES_TIMERS=y |
42 | CONFIG_SMP=y | ||
31 | CONFIG_VMSPLIT_2G=y | 43 | CONFIG_VMSPLIT_2G=y |
32 | CONFIG_PREEMPT_VOLUNTARY=y | 44 | CONFIG_PREEMPT_VOLUNTARY=y |
33 | CONFIG_AEABI=y | 45 | CONFIG_AEABI=y |
@@ -49,7 +61,7 @@ CONFIG_IP_PNP_DHCP=y | |||
49 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | 61 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
50 | # CONFIG_INET_XFRM_MODE_BEET is not set | 62 | # CONFIG_INET_XFRM_MODE_BEET is not set |
51 | # CONFIG_INET_LRO is not set | 63 | # CONFIG_INET_LRO is not set |
52 | # CONFIG_IPV6 is not set | 64 | CONFIG_IPV6=y |
53 | # CONFIG_WIRELESS is not set | 65 | # CONFIG_WIRELESS is not set |
54 | CONFIG_DEVTMPFS=y | 66 | CONFIG_DEVTMPFS=y |
55 | CONFIG_DEVTMPFS_MOUNT=y | 67 | CONFIG_DEVTMPFS_MOUNT=y |
@@ -68,24 +80,20 @@ CONFIG_SCSI_SCAN_ASYNC=y | |||
68 | CONFIG_ATA=y | 80 | CONFIG_ATA=y |
69 | CONFIG_PATA_IMX=y | 81 | CONFIG_PATA_IMX=y |
70 | CONFIG_NETDEVICES=y | 82 | CONFIG_NETDEVICES=y |
71 | CONFIG_MII=m | 83 | # CONFIG_NET_VENDOR_BROADCOM is not set |
72 | CONFIG_MARVELL_PHY=y | 84 | # CONFIG_NET_VENDOR_CHELSIO is not set |
73 | CONFIG_DAVICOM_PHY=y | 85 | # CONFIG_NET_VENDOR_FARADAY is not set |
74 | CONFIG_QSEMI_PHY=y | 86 | CONFIG_FEC=y |
75 | CONFIG_LXT_PHY=y | 87 | # CONFIG_NET_VENDOR_INTEL is not set |
76 | CONFIG_CICADA_PHY=y | 88 | # CONFIG_NET_VENDOR_MARVELL is not set |
77 | CONFIG_VITESSE_PHY=y | 89 | # CONFIG_NET_VENDOR_MICREL is not set |
78 | CONFIG_SMSC_PHY=y | 90 | # CONFIG_NET_VENDOR_MICROCHIP is not set |
79 | CONFIG_BROADCOM_PHY=y | 91 | # CONFIG_NET_VENDOR_NATSEMI is not set |
80 | CONFIG_ICPLUS_PHY=y | 92 | # CONFIG_NET_VENDOR_SEEQ is not set |
81 | CONFIG_REALTEK_PHY=y | 93 | CONFIG_SMC91X=y |
82 | CONFIG_NATIONAL_PHY=y | 94 | CONFIG_SMC911X=y |
83 | CONFIG_STE10XP=y | 95 | CONFIG_SMSC911X=y |
84 | CONFIG_LSI_ET1011C_PHY=y | 96 | # CONFIG_NET_VENDOR_STMICRO is not set |
85 | CONFIG_MICREL_PHY=y | ||
86 | CONFIG_NET_ETHERNET=y | ||
87 | # CONFIG_NETDEV_1000 is not set | ||
88 | # CONFIG_NETDEV_10000 is not set | ||
89 | # CONFIG_WLAN is not set | 97 | # CONFIG_WLAN is not set |
90 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | 98 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set |
91 | CONFIG_INPUT_EVDEV=y | 99 | CONFIG_INPUT_EVDEV=y |
@@ -124,7 +132,6 @@ CONFIG_USB_EHCI_HCD=y | |||
124 | CONFIG_USB_EHCI_MXC=y | 132 | CONFIG_USB_EHCI_MXC=y |
125 | CONFIG_USB_STORAGE=y | 133 | CONFIG_USB_STORAGE=y |
126 | CONFIG_MMC=y | 134 | CONFIG_MMC=y |
127 | CONFIG_MMC_BLOCK=m | ||
128 | CONFIG_MMC_SDHCI=y | 135 | CONFIG_MMC_SDHCI=y |
129 | CONFIG_MMC_SDHCI_PLTFM=y | 136 | CONFIG_MMC_SDHCI_PLTFM=y |
130 | CONFIG_MMC_SDHCI_ESDHC_IMX=y | 137 | CONFIG_MMC_SDHCI_ESDHC_IMX=y |
@@ -133,6 +140,8 @@ CONFIG_LEDS_CLASS=y | |||
133 | CONFIG_RTC_CLASS=y | 140 | CONFIG_RTC_CLASS=y |
134 | CONFIG_RTC_INTF_DEV_UIE_EMUL=y | 141 | CONFIG_RTC_INTF_DEV_UIE_EMUL=y |
135 | CONFIG_RTC_MXC=y | 142 | CONFIG_RTC_MXC=y |
143 | CONFIG_DMADEVICES=y | ||
144 | CONFIG_IMX_SDMA=y | ||
136 | CONFIG_EXT2_FS=y | 145 | CONFIG_EXT2_FS=y |
137 | CONFIG_EXT2_FS_XATTR=y | 146 | CONFIG_EXT2_FS_XATTR=y |
138 | CONFIG_EXT2_FS_POSIX_ACL=y | 147 | CONFIG_EXT2_FS_POSIX_ACL=y |
diff --git a/arch/arm/configs/mx3_defconfig b/arch/arm/configs/mx3_defconfig deleted file mode 100644 index cb0717fbb03d..000000000000 --- a/arch/arm/configs/mx3_defconfig +++ /dev/null | |||
@@ -1,144 +0,0 @@ | |||
1 | CONFIG_EXPERIMENTAL=y | ||
2 | CONFIG_SYSVIPC=y | ||
3 | CONFIG_IKCONFIG=y | ||
4 | CONFIG_IKCONFIG_PROC=y | ||
5 | CONFIG_LOG_BUF_SHIFT=14 | ||
6 | CONFIG_EXPERT=y | ||
7 | CONFIG_SLAB=y | ||
8 | CONFIG_MODULES=y | ||
9 | CONFIG_MODULE_UNLOAD=y | ||
10 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
11 | CONFIG_MODVERSIONS=y | ||
12 | # CONFIG_BLK_DEV_BSG is not set | ||
13 | CONFIG_ARCH_MXC=y | ||
14 | CONFIG_MACH_MX31ADS_WM1133_EV1=y | ||
15 | CONFIG_MACH_MX31LILLY=y | ||
16 | CONFIG_MACH_MX31LITE=y | ||
17 | CONFIG_MACH_PCM037=y | ||
18 | CONFIG_MACH_PCM037_EET=y | ||
19 | CONFIG_MACH_MX31_3DS=y | ||
20 | CONFIG_MACH_MX31MOBOARD=y | ||
21 | CONFIG_MACH_QONG=y | ||
22 | CONFIG_MACH_ARMADILLO5X0=y | ||
23 | CONFIG_MACH_KZM_ARM11_01=y | ||
24 | CONFIG_MACH_PCM043=y | ||
25 | CONFIG_MACH_MX35_3DS=y | ||
26 | CONFIG_MACH_EUKREA_CPUIMX35=y | ||
27 | CONFIG_MXC_IRQ_PRIOR=y | ||
28 | CONFIG_MXC_PWM=y | ||
29 | CONFIG_ARM_ERRATA_411920=y | ||
30 | CONFIG_NO_HZ=y | ||
31 | CONFIG_HIGH_RES_TIMERS=y | ||
32 | CONFIG_PREEMPT=y | ||
33 | CONFIG_AEABI=y | ||
34 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
35 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
36 | CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw ip=off" | ||
37 | CONFIG_VFP=y | ||
38 | CONFIG_PM_DEBUG=y | ||
39 | CONFIG_NET=y | ||
40 | CONFIG_PACKET=y | ||
41 | CONFIG_UNIX=y | ||
42 | CONFIG_INET=y | ||
43 | CONFIG_IP_PNP=y | ||
44 | CONFIG_IP_PNP_DHCP=y | ||
45 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
46 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
47 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
48 | # CONFIG_INET_LRO is not set | ||
49 | # CONFIG_INET_DIAG is not set | ||
50 | # CONFIG_IPV6 is not set | ||
51 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
52 | CONFIG_FW_LOADER=m | ||
53 | CONFIG_MTD=y | ||
54 | CONFIG_MTD_CMDLINE_PARTS=y | ||
55 | CONFIG_MTD_CHAR=y | ||
56 | CONFIG_MTD_BLOCK=y | ||
57 | CONFIG_MTD_CFI=y | ||
58 | CONFIG_MTD_PHYSMAP=y | ||
59 | CONFIG_MTD_NAND=y | ||
60 | CONFIG_MTD_NAND_MXC=y | ||
61 | CONFIG_MTD_UBI=y | ||
62 | # CONFIG_BLK_DEV is not set | ||
63 | CONFIG_MISC_DEVICES=y | ||
64 | CONFIG_EEPROM_AT24=y | ||
65 | CONFIG_NETDEVICES=y | ||
66 | CONFIG_SMSC_PHY=y | ||
67 | CONFIG_NET_ETHERNET=y | ||
68 | CONFIG_SMSC911X=y | ||
69 | CONFIG_DNET=y | ||
70 | # CONFIG_NETDEV_1000 is not set | ||
71 | # CONFIG_NETDEV_10000 is not set | ||
72 | # CONFIG_INPUT_MOUSEDEV is not set | ||
73 | # CONFIG_KEYBOARD_ATKBD is not set | ||
74 | CONFIG_KEYBOARD_IMX=y | ||
75 | # CONFIG_INPUT_MOUSE is not set | ||
76 | # CONFIG_SERIO is not set | ||
77 | # CONFIG_VT is not set | ||
78 | # CONFIG_LEGACY_PTYS is not set | ||
79 | CONFIG_SERIAL_8250=m | ||
80 | CONFIG_SERIAL_8250_EXTENDED=y | ||
81 | CONFIG_SERIAL_8250_SHARE_IRQ=y | ||
82 | CONFIG_SERIAL_IMX=y | ||
83 | CONFIG_SERIAL_IMX_CONSOLE=y | ||
84 | # CONFIG_HW_RANDOM is not set | ||
85 | CONFIG_I2C=y | ||
86 | CONFIG_I2C_CHARDEV=y | ||
87 | CONFIG_I2C_IMX=y | ||
88 | CONFIG_SPI=y | ||
89 | CONFIG_W1=y | ||
90 | CONFIG_W1_MASTER_MXC=y | ||
91 | CONFIG_W1_SLAVE_THERM=y | ||
92 | # CONFIG_HWMON is not set | ||
93 | CONFIG_WATCHDOG=y | ||
94 | CONFIG_IMX2_WDT=y | ||
95 | CONFIG_MFD_WM8350_I2C=y | ||
96 | CONFIG_REGULATOR=y | ||
97 | CONFIG_REGULATOR_WM8350=y | ||
98 | CONFIG_MEDIA_SUPPORT=y | ||
99 | CONFIG_VIDEO_DEV=y | ||
100 | # CONFIG_RC_CORE is not set | ||
101 | # CONFIG_MEDIA_TUNER_CUSTOMISE is not set | ||
102 | CONFIG_SOC_CAMERA=y | ||
103 | CONFIG_SOC_CAMERA_MT9M001=y | ||
104 | CONFIG_SOC_CAMERA_MT9M111=y | ||
105 | CONFIG_SOC_CAMERA_MT9T031=y | ||
106 | CONFIG_SOC_CAMERA_MT9V022=y | ||
107 | CONFIG_SOC_CAMERA_TW9910=y | ||
108 | CONFIG_SOC_CAMERA_OV772X=y | ||
109 | CONFIG_VIDEO_MX3=y | ||
110 | # CONFIG_RADIO_ADAPTERS is not set | ||
111 | CONFIG_FB=y | ||
112 | CONFIG_SOUND=y | ||
113 | CONFIG_SND=y | ||
114 | # CONFIG_SND_ARM is not set | ||
115 | # CONFIG_SND_SPI is not set | ||
116 | CONFIG_SND_SOC=y | ||
117 | CONFIG_SND_IMX_SOC=y | ||
118 | CONFIG_SND_MXC_SOC_WM1133_EV1=y | ||
119 | CONFIG_SND_SOC_PHYCORE_AC97=y | ||
120 | CONFIG_SND_SOC_EUKREA_TLV320=y | ||
121 | CONFIG_USB=y | ||
122 | CONFIG_USB_EHCI_HCD=y | ||
123 | CONFIG_USB_EHCI_MXC=y | ||
124 | CONFIG_USB_GADGET=m | ||
125 | CONFIG_USB_FSL_USB2=m | ||
126 | CONFIG_USB_G_SERIAL=m | ||
127 | CONFIG_USB_ULPI=y | ||
128 | CONFIG_MMC=y | ||
129 | CONFIG_MMC_MXC=y | ||
130 | CONFIG_RTC_CLASS=y | ||
131 | CONFIG_RTC_MXC=y | ||
132 | CONFIG_DMADEVICES=y | ||
133 | # CONFIG_DNOTIFY is not set | ||
134 | CONFIG_TMPFS=y | ||
135 | CONFIG_JFFS2_FS=y | ||
136 | CONFIG_UBIFS_FS=y | ||
137 | CONFIG_NFS_FS=y | ||
138 | CONFIG_NFS_V3=y | ||
139 | CONFIG_NFS_V4=y | ||
140 | CONFIG_ROOT_NFS=y | ||
141 | # CONFIG_ENABLE_WARN_DEPRECATED is not set | ||
142 | # CONFIG_ENABLE_MUST_CHECK is not set | ||
143 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
144 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index b6e65dedfd71..23371b17b23e 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h | |||
@@ -137,6 +137,11 @@ | |||
137 | disable_irq | 137 | disable_irq |
138 | .endm | 138 | .endm |
139 | 139 | ||
140 | .macro save_and_disable_irqs_notrace, oldcpsr | ||
141 | mrs \oldcpsr, cpsr | ||
142 | disable_irq_notrace | ||
143 | .endm | ||
144 | |||
140 | /* | 145 | /* |
141 | * Restore interrupt state previously stored in a register. We don't | 146 | * Restore interrupt state previously stored in a register. We don't |
142 | * guarantee that this will preserve the flags. | 147 | * guarantee that this will preserve the flags. |
@@ -237,7 +242,7 @@ | |||
237 | */ | 242 | */ |
238 | #ifdef CONFIG_THUMB2_KERNEL | 243 | #ifdef CONFIG_THUMB2_KERNEL |
239 | 244 | ||
240 | .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=T() | 245 | .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER() |
241 | 9999: | 246 | 9999: |
242 | .if \inc == 1 | 247 | .if \inc == 1 |
243 | \instr\cond\()b\()\t\().w \reg, [\ptr, #\off] | 248 | \instr\cond\()b\()\t\().w \reg, [\ptr, #\off] |
@@ -277,7 +282,7 @@ | |||
277 | 282 | ||
278 | #else /* !CONFIG_THUMB2_KERNEL */ | 283 | #else /* !CONFIG_THUMB2_KERNEL */ |
279 | 284 | ||
280 | .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=T() | 285 | .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER() |
281 | .rept \rept | 286 | .rept \rept |
282 | 9999: | 287 | 9999: |
283 | .if \inc == 1 | 288 | .if \inc == 1 |
diff --git a/arch/arm/include/asm/domain.h b/arch/arm/include/asm/domain.h index af18ceaacf5d..b5dc173d336f 100644 --- a/arch/arm/include/asm/domain.h +++ b/arch/arm/include/asm/domain.h | |||
@@ -83,9 +83,9 @@ | |||
83 | * instructions (inline assembly) | 83 | * instructions (inline assembly) |
84 | */ | 84 | */ |
85 | #ifdef CONFIG_CPU_USE_DOMAINS | 85 | #ifdef CONFIG_CPU_USE_DOMAINS |
86 | #define T(instr) #instr "t" | 86 | #define TUSER(instr) #instr "t" |
87 | #else | 87 | #else |
88 | #define T(instr) #instr | 88 | #define TUSER(instr) #instr |
89 | #endif | 89 | #endif |
90 | 90 | ||
91 | #else /* __ASSEMBLY__ */ | 91 | #else /* __ASSEMBLY__ */ |
@@ -95,9 +95,9 @@ | |||
95 | * instructions | 95 | * instructions |
96 | */ | 96 | */ |
97 | #ifdef CONFIG_CPU_USE_DOMAINS | 97 | #ifdef CONFIG_CPU_USE_DOMAINS |
98 | #define T(instr) instr ## t | 98 | #define TUSER(instr) instr ## t |
99 | #else | 99 | #else |
100 | #define T(instr) instr | 100 | #define TUSER(instr) instr |
101 | #endif | 101 | #endif |
102 | 102 | ||
103 | #endif /* __ASSEMBLY__ */ | 103 | #endif /* __ASSEMBLY__ */ |
diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h index 253cc86318bf..7be54690aeec 100644 --- a/arch/arm/include/asm/futex.h +++ b/arch/arm/include/asm/futex.h | |||
@@ -75,9 +75,9 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, | |||
75 | 75 | ||
76 | #define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \ | 76 | #define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \ |
77 | __asm__ __volatile__( \ | 77 | __asm__ __volatile__( \ |
78 | "1: " T(ldr) " %1, [%3]\n" \ | 78 | "1: " TUSER(ldr) " %1, [%3]\n" \ |
79 | " " insn "\n" \ | 79 | " " insn "\n" \ |
80 | "2: " T(str) " %0, [%3]\n" \ | 80 | "2: " TUSER(str) " %0, [%3]\n" \ |
81 | " mov %0, #0\n" \ | 81 | " mov %0, #0\n" \ |
82 | __futex_atomic_ex_table("%5") \ | 82 | __futex_atomic_ex_table("%5") \ |
83 | : "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \ | 83 | : "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \ |
@@ -95,10 +95,10 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, | |||
95 | return -EFAULT; | 95 | return -EFAULT; |
96 | 96 | ||
97 | __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n" | 97 | __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n" |
98 | "1: " T(ldr) " %1, [%4]\n" | 98 | "1: " TUSER(ldr) " %1, [%4]\n" |
99 | " teq %1, %2\n" | 99 | " teq %1, %2\n" |
100 | " it eq @ explicit IT needed for the 2b label\n" | 100 | " it eq @ explicit IT needed for the 2b label\n" |
101 | "2: " T(streq) " %3, [%4]\n" | 101 | "2: " TUSER(streq) " %3, [%4]\n" |
102 | __futex_atomic_ex_table("%5") | 102 | __futex_atomic_ex_table("%5") |
103 | : "+r" (ret), "=&r" (val) | 103 | : "+r" (ret), "=&r" (val) |
104 | : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT) | 104 | : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT) |
diff --git a/arch/arm/include/asm/hardware/pl330.h b/arch/arm/include/asm/hardware/pl330.h index 575fa8186ca0..c1821385abfa 100644 --- a/arch/arm/include/asm/hardware/pl330.h +++ b/arch/arm/include/asm/hardware/pl330.h | |||
@@ -41,7 +41,7 @@ enum pl330_dstcachectrl { | |||
41 | DCCTRL1, /* Bufferable only */ | 41 | DCCTRL1, /* Bufferable only */ |
42 | DCCTRL2, /* Cacheable, but do not allocate */ | 42 | DCCTRL2, /* Cacheable, but do not allocate */ |
43 | DCCTRL3, /* Cacheable and bufferable, but do not allocate */ | 43 | DCCTRL3, /* Cacheable and bufferable, but do not allocate */ |
44 | DINVALID1 = 8, | 44 | DINVALID1, /* AWCACHE = 0x1000 */ |
45 | DINVALID2, | 45 | DINVALID2, |
46 | DCCTRL6, /* Cacheable write-through, allocate on writes only */ | 46 | DCCTRL6, /* Cacheable write-through, allocate on writes only */ |
47 | DCCTRL7, /* Cacheable write-back, allocate on writes only */ | 47 | DCCTRL7, /* Cacheable write-back, allocate on writes only */ |
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h index ce280b8d613c..cb8d638924fd 100644 --- a/arch/arm/include/asm/processor.h +++ b/arch/arm/include/asm/processor.h | |||
@@ -22,6 +22,7 @@ | |||
22 | #include <asm/hw_breakpoint.h> | 22 | #include <asm/hw_breakpoint.h> |
23 | #include <asm/ptrace.h> | 23 | #include <asm/ptrace.h> |
24 | #include <asm/types.h> | 24 | #include <asm/types.h> |
25 | #include <asm/system.h> | ||
25 | 26 | ||
26 | #ifdef __KERNEL__ | 27 | #ifdef __KERNEL__ |
27 | #define STACK_TOP ((current->personality & ADDR_LIMIT_32BIT) ? \ | 28 | #define STACK_TOP ((current->personality & ADDR_LIMIT_32BIT) ? \ |
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h index 1e5717afc4ac..ae29293270a3 100644 --- a/arch/arm/include/asm/smp.h +++ b/arch/arm/include/asm/smp.h | |||
@@ -71,12 +71,6 @@ extern void platform_secondary_init(unsigned int cpu); | |||
71 | extern void platform_smp_prepare_cpus(unsigned int); | 71 | extern void platform_smp_prepare_cpus(unsigned int); |
72 | 72 | ||
73 | /* | 73 | /* |
74 | * Logical CPU mapping. | ||
75 | */ | ||
76 | extern int __cpu_logical_map[NR_CPUS]; | ||
77 | #define cpu_logical_map(cpu) __cpu_logical_map[cpu] | ||
78 | |||
79 | /* | ||
80 | * Initial data for bringing up a secondary CPU. | 74 | * Initial data for bringing up a secondary CPU. |
81 | */ | 75 | */ |
82 | struct secondary_data { | 76 | struct secondary_data { |
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h index f24c1b9e211d..558d6c80aca9 100644 --- a/arch/arm/include/asm/smp_plat.h +++ b/arch/arm/include/asm/smp_plat.h | |||
@@ -43,4 +43,10 @@ static inline int cache_ops_need_broadcast(void) | |||
43 | } | 43 | } |
44 | #endif | 44 | #endif |
45 | 45 | ||
46 | /* | ||
47 | * Logical CPU mapping. | ||
48 | */ | ||
49 | extern int __cpu_logical_map[]; | ||
50 | #define cpu_logical_map(cpu) __cpu_logical_map[cpu] | ||
51 | |||
46 | #endif | 52 | #endif |
diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h index 5d3ed7e38561..314d4664eae7 100644 --- a/arch/arm/include/asm/tlb.h +++ b/arch/arm/include/asm/tlb.h | |||
@@ -198,7 +198,15 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, | |||
198 | unsigned long addr) | 198 | unsigned long addr) |
199 | { | 199 | { |
200 | pgtable_page_dtor(pte); | 200 | pgtable_page_dtor(pte); |
201 | tlb_add_flush(tlb, addr); | 201 | |
202 | /* | ||
203 | * With the classic ARM MMU, a pte page has two corresponding pmd | ||
204 | * entries, each covering 1MB. | ||
205 | */ | ||
206 | addr &= PMD_MASK; | ||
207 | tlb_add_flush(tlb, addr + SZ_1M - PAGE_SIZE); | ||
208 | tlb_add_flush(tlb, addr + SZ_1M); | ||
209 | |||
202 | tlb_remove_page(tlb, pte); | 210 | tlb_remove_page(tlb, pte); |
203 | } | 211 | } |
204 | 212 | ||
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h index b293616a1a1a..2958976d867b 100644 --- a/arch/arm/include/asm/uaccess.h +++ b/arch/arm/include/asm/uaccess.h | |||
@@ -227,7 +227,7 @@ do { \ | |||
227 | 227 | ||
228 | #define __get_user_asm_byte(x,addr,err) \ | 228 | #define __get_user_asm_byte(x,addr,err) \ |
229 | __asm__ __volatile__( \ | 229 | __asm__ __volatile__( \ |
230 | "1: " T(ldrb) " %1,[%2],#0\n" \ | 230 | "1: " TUSER(ldrb) " %1,[%2],#0\n" \ |
231 | "2:\n" \ | 231 | "2:\n" \ |
232 | " .pushsection .fixup,\"ax\"\n" \ | 232 | " .pushsection .fixup,\"ax\"\n" \ |
233 | " .align 2\n" \ | 233 | " .align 2\n" \ |
@@ -263,7 +263,7 @@ do { \ | |||
263 | 263 | ||
264 | #define __get_user_asm_word(x,addr,err) \ | 264 | #define __get_user_asm_word(x,addr,err) \ |
265 | __asm__ __volatile__( \ | 265 | __asm__ __volatile__( \ |
266 | "1: " T(ldr) " %1,[%2],#0\n" \ | 266 | "1: " TUSER(ldr) " %1,[%2],#0\n" \ |
267 | "2:\n" \ | 267 | "2:\n" \ |
268 | " .pushsection .fixup,\"ax\"\n" \ | 268 | " .pushsection .fixup,\"ax\"\n" \ |
269 | " .align 2\n" \ | 269 | " .align 2\n" \ |
@@ -308,7 +308,7 @@ do { \ | |||
308 | 308 | ||
309 | #define __put_user_asm_byte(x,__pu_addr,err) \ | 309 | #define __put_user_asm_byte(x,__pu_addr,err) \ |
310 | __asm__ __volatile__( \ | 310 | __asm__ __volatile__( \ |
311 | "1: " T(strb) " %1,[%2],#0\n" \ | 311 | "1: " TUSER(strb) " %1,[%2],#0\n" \ |
312 | "2:\n" \ | 312 | "2:\n" \ |
313 | " .pushsection .fixup,\"ax\"\n" \ | 313 | " .pushsection .fixup,\"ax\"\n" \ |
314 | " .align 2\n" \ | 314 | " .align 2\n" \ |
@@ -341,7 +341,7 @@ do { \ | |||
341 | 341 | ||
342 | #define __put_user_asm_word(x,__pu_addr,err) \ | 342 | #define __put_user_asm_word(x,__pu_addr,err) \ |
343 | __asm__ __volatile__( \ | 343 | __asm__ __volatile__( \ |
344 | "1: " T(str) " %1,[%2],#0\n" \ | 344 | "1: " TUSER(str) " %1,[%2],#0\n" \ |
345 | "2:\n" \ | 345 | "2:\n" \ |
346 | " .pushsection .fixup,\"ax\"\n" \ | 346 | " .pushsection .fixup,\"ax\"\n" \ |
347 | " .align 2\n" \ | 347 | " .align 2\n" \ |
@@ -366,10 +366,10 @@ do { \ | |||
366 | 366 | ||
367 | #define __put_user_asm_dword(x,__pu_addr,err) \ | 367 | #define __put_user_asm_dword(x,__pu_addr,err) \ |
368 | __asm__ __volatile__( \ | 368 | __asm__ __volatile__( \ |
369 | ARM( "1: " T(str) " " __reg_oper1 ", [%1], #4\n" ) \ | 369 | ARM( "1: " TUSER(str) " " __reg_oper1 ", [%1], #4\n" ) \ |
370 | ARM( "2: " T(str) " " __reg_oper0 ", [%1]\n" ) \ | 370 | ARM( "2: " TUSER(str) " " __reg_oper0 ", [%1]\n" ) \ |
371 | THUMB( "1: " T(str) " " __reg_oper1 ", [%1]\n" ) \ | 371 | THUMB( "1: " TUSER(str) " " __reg_oper1 ", [%1]\n" ) \ |
372 | THUMB( "2: " T(str) " " __reg_oper0 ", [%1, #4]\n" ) \ | 372 | THUMB( "2: " TUSER(str) " " __reg_oper0 ", [%1, #4]\n" ) \ |
373 | "3:\n" \ | 373 | "3:\n" \ |
374 | " .pushsection .fixup,\"ax\"\n" \ | 374 | " .pushsection .fixup,\"ax\"\n" \ |
375 | " .align 2\n" \ | 375 | " .align 2\n" \ |
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 3a456c6c7005..be16a48007b4 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S | |||
@@ -790,7 +790,7 @@ __kuser_cmpxchg64: @ 0xffff0f60 | |||
790 | smp_dmb arm | 790 | smp_dmb arm |
791 | rsbs r0, r3, #0 @ set returned val and C flag | 791 | rsbs r0, r3, #0 @ set returned val and C flag |
792 | ldmfd sp!, {r4, r5, r6, r7} | 792 | ldmfd sp!, {r4, r5, r6, r7} |
793 | bx lr | 793 | usr_ret lr |
794 | 794 | ||
795 | #elif !defined(CONFIG_SMP) | 795 | #elif !defined(CONFIG_SMP) |
796 | 796 | ||
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 520889cf1b5b..9fd0ba90c1d2 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S | |||
@@ -149,6 +149,11 @@ ENDPROC(ret_from_fork) | |||
149 | #endif | 149 | #endif |
150 | #endif | 150 | #endif |
151 | 151 | ||
152 | .macro mcount_adjust_addr rd, rn | ||
153 | bic \rd, \rn, #1 @ clear the Thumb bit if present | ||
154 | sub \rd, \rd, #MCOUNT_INSN_SIZE | ||
155 | .endm | ||
156 | |||
152 | .macro __mcount suffix | 157 | .macro __mcount suffix |
153 | mcount_enter | 158 | mcount_enter |
154 | ldr r0, =ftrace_trace_function | 159 | ldr r0, =ftrace_trace_function |
@@ -173,8 +178,7 @@ ENDPROC(ret_from_fork) | |||
173 | mcount_exit | 178 | mcount_exit |
174 | 179 | ||
175 | 1: mcount_get_lr r1 @ lr of instrumented func | 180 | 1: mcount_get_lr r1 @ lr of instrumented func |
176 | mov r0, lr @ instrumented function | 181 | mcount_adjust_addr r0, lr @ instrumented function |
177 | sub r0, r0, #MCOUNT_INSN_SIZE | ||
178 | adr lr, BSYM(2f) | 182 | adr lr, BSYM(2f) |
179 | mov pc, r2 | 183 | mov pc, r2 |
180 | 2: mcount_exit | 184 | 2: mcount_exit |
@@ -184,8 +188,7 @@ ENDPROC(ret_from_fork) | |||
184 | mcount_enter | 188 | mcount_enter |
185 | 189 | ||
186 | mcount_get_lr r1 @ lr of instrumented func | 190 | mcount_get_lr r1 @ lr of instrumented func |
187 | mov r0, lr @ instrumented function | 191 | mcount_adjust_addr r0, lr @ instrumented function |
188 | sub r0, r0, #MCOUNT_INSN_SIZE | ||
189 | 192 | ||
190 | .globl ftrace_call\suffix | 193 | .globl ftrace_call\suffix |
191 | ftrace_call\suffix: | 194 | ftrace_call\suffix: |
@@ -205,11 +208,11 @@ ftrace_graph_call\suffix: | |||
205 | #ifdef CONFIG_DYNAMIC_FTRACE | 208 | #ifdef CONFIG_DYNAMIC_FTRACE |
206 | @ called from __ftrace_caller, saved in mcount_enter | 209 | @ called from __ftrace_caller, saved in mcount_enter |
207 | ldr r1, [sp, #16] @ instrumented routine (func) | 210 | ldr r1, [sp, #16] @ instrumented routine (func) |
211 | mcount_adjust_addr r1, r1 | ||
208 | #else | 212 | #else |
209 | @ called from __mcount, untouched in lr | 213 | @ called from __mcount, untouched in lr |
210 | mov r1, lr @ instrumented routine (func) | 214 | mcount_adjust_addr r1, lr @ instrumented routine (func) |
211 | #endif | 215 | #endif |
212 | sub r1, r1, #MCOUNT_INSN_SIZE | ||
213 | mov r2, fp @ frame pointer | 216 | mov r2, fp @ frame pointer |
214 | bl prepare_ftrace_return | 217 | bl prepare_ftrace_return |
215 | mcount_exit | 218 | mcount_exit |
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c index 460bbbb6b885..6933244c68f9 100644 --- a/arch/arm/kernel/perf_event_v7.c +++ b/arch/arm/kernel/perf_event_v7.c | |||
@@ -469,6 +469,20 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | |||
469 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | 469 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, |
470 | }, | 470 | }, |
471 | }, | 471 | }, |
472 | [C(NODE)] = { | ||
473 | [C(OP_READ)] = { | ||
474 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
475 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
476 | }, | ||
477 | [C(OP_WRITE)] = { | ||
478 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
479 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
480 | }, | ||
481 | [C(OP_PREFETCH)] = { | ||
482 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
483 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
484 | }, | ||
485 | }, | ||
472 | }; | 486 | }; |
473 | 487 | ||
474 | /* | 488 | /* |
@@ -579,6 +593,20 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | |||
579 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | 593 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, |
580 | }, | 594 | }, |
581 | }, | 595 | }, |
596 | [C(NODE)] = { | ||
597 | [C(OP_READ)] = { | ||
598 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
599 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
600 | }, | ||
601 | [C(OP_WRITE)] = { | ||
602 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
603 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
604 | }, | ||
605 | [C(OP_PREFETCH)] = { | ||
606 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
607 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
608 | }, | ||
609 | }, | ||
582 | }; | 610 | }; |
583 | 611 | ||
584 | /* | 612 | /* |
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c index e1d5e1929fbd..ede6443c34d9 100644 --- a/arch/arm/kernel/ptrace.c +++ b/arch/arm/kernel/ptrace.c | |||
@@ -23,6 +23,7 @@ | |||
23 | #include <linux/perf_event.h> | 23 | #include <linux/perf_event.h> |
24 | #include <linux/hw_breakpoint.h> | 24 | #include <linux/hw_breakpoint.h> |
25 | #include <linux/regset.h> | 25 | #include <linux/regset.h> |
26 | #include <linux/audit.h> | ||
26 | 27 | ||
27 | #include <asm/pgtable.h> | 28 | #include <asm/pgtable.h> |
28 | #include <asm/system.h> | 29 | #include <asm/system.h> |
@@ -699,10 +700,13 @@ static int vfp_set(struct task_struct *target, | |||
699 | { | 700 | { |
700 | int ret; | 701 | int ret; |
701 | struct thread_info *thread = task_thread_info(target); | 702 | struct thread_info *thread = task_thread_info(target); |
702 | struct vfp_hard_struct new_vfp = thread->vfpstate.hard; | 703 | struct vfp_hard_struct new_vfp; |
703 | const size_t user_fpregs_offset = offsetof(struct user_vfp, fpregs); | 704 | const size_t user_fpregs_offset = offsetof(struct user_vfp, fpregs); |
704 | const size_t user_fpscr_offset = offsetof(struct user_vfp, fpscr); | 705 | const size_t user_fpscr_offset = offsetof(struct user_vfp, fpscr); |
705 | 706 | ||
707 | vfp_sync_hwstate(thread); | ||
708 | new_vfp = thread->vfpstate.hard; | ||
709 | |||
706 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | 710 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
707 | &new_vfp.fpregs, | 711 | &new_vfp.fpregs, |
708 | user_fpregs_offset, | 712 | user_fpregs_offset, |
@@ -723,9 +727,8 @@ static int vfp_set(struct task_struct *target, | |||
723 | if (ret) | 727 | if (ret) |
724 | return ret; | 728 | return ret; |
725 | 729 | ||
726 | vfp_sync_hwstate(thread); | ||
727 | thread->vfpstate.hard = new_vfp; | ||
728 | vfp_flush_hwstate(thread); | 730 | vfp_flush_hwstate(thread); |
731 | thread->vfpstate.hard = new_vfp; | ||
729 | 732 | ||
730 | return 0; | 733 | return 0; |
731 | } | 734 | } |
@@ -902,6 +905,12 @@ long arch_ptrace(struct task_struct *child, long request, | |||
902 | return ret; | 905 | return ret; |
903 | } | 906 | } |
904 | 907 | ||
908 | #ifdef __ARMEB__ | ||
909 | #define AUDIT_ARCH_NR AUDIT_ARCH_ARMEB | ||
910 | #else | ||
911 | #define AUDIT_ARCH_NR AUDIT_ARCH_ARM | ||
912 | #endif | ||
913 | |||
905 | asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno) | 914 | asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno) |
906 | { | 915 | { |
907 | unsigned long ip; | 916 | unsigned long ip; |
@@ -916,7 +925,7 @@ asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno) | |||
916 | if (!ip) | 925 | if (!ip) |
917 | audit_syscall_exit(regs); | 926 | audit_syscall_exit(regs); |
918 | else | 927 | else |
919 | audit_syscall_entry(AUDIT_ARCH_ARMEB, scno, regs->ARM_r0, | 928 | audit_syscall_entry(AUDIT_ARCH_NR, scno, regs->ARM_r0, |
920 | regs->ARM_r1, regs->ARM_r2, regs->ARM_r3); | 929 | regs->ARM_r1, regs->ARM_r2, regs->ARM_r3); |
921 | 930 | ||
922 | if (!test_thread_flag(TIF_SYSCALL_TRACE)) | 931 | if (!test_thread_flag(TIF_SYSCALL_TRACE)) |
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 129fbd55bde8..a255c39612ca 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c | |||
@@ -21,7 +21,6 @@ | |||
21 | #include <linux/init.h> | 21 | #include <linux/init.h> |
22 | #include <linux/kexec.h> | 22 | #include <linux/kexec.h> |
23 | #include <linux/of_fdt.h> | 23 | #include <linux/of_fdt.h> |
24 | #include <linux/crash_dump.h> | ||
25 | #include <linux/root_dev.h> | 24 | #include <linux/root_dev.h> |
26 | #include <linux/cpu.h> | 25 | #include <linux/cpu.h> |
27 | #include <linux/interrupt.h> | 26 | #include <linux/interrupt.h> |
@@ -160,7 +159,7 @@ static struct resource mem_res[] = { | |||
160 | .flags = IORESOURCE_MEM | 159 | .flags = IORESOURCE_MEM |
161 | }, | 160 | }, |
162 | { | 161 | { |
163 | .name = "Kernel text", | 162 | .name = "Kernel code", |
164 | .start = 0, | 163 | .start = 0, |
165 | .end = 0, | 164 | .end = 0, |
166 | .flags = IORESOURCE_MEM | 165 | .flags = IORESOURCE_MEM |
@@ -427,6 +426,20 @@ void cpu_init(void) | |||
427 | : "r14"); | 426 | : "r14"); |
428 | } | 427 | } |
429 | 428 | ||
429 | int __cpu_logical_map[NR_CPUS]; | ||
430 | |||
431 | void __init smp_setup_processor_id(void) | ||
432 | { | ||
433 | int i; | ||
434 | u32 cpu = is_smp() ? read_cpuid_mpidr() & 0xff : 0; | ||
435 | |||
436 | cpu_logical_map(0) = cpu; | ||
437 | for (i = 1; i < NR_CPUS; ++i) | ||
438 | cpu_logical_map(i) = i == cpu ? 0 : i; | ||
439 | |||
440 | printk(KERN_INFO "Booting Linux on physical CPU %d\n", cpu); | ||
441 | } | ||
442 | |||
430 | static void __init setup_processor(void) | 443 | static void __init setup_processor(void) |
431 | { | 444 | { |
432 | struct proc_info_list *list; | 445 | struct proc_info_list *list; |
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index 0340224cf73c..9e617bd4a146 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c | |||
@@ -227,6 +227,8 @@ static int restore_vfp_context(struct vfp_sigframe __user *frame) | |||
227 | if (magic != VFP_MAGIC || size != VFP_STORAGE_SIZE) | 227 | if (magic != VFP_MAGIC || size != VFP_STORAGE_SIZE) |
228 | return -EINVAL; | 228 | return -EINVAL; |
229 | 229 | ||
230 | vfp_flush_hwstate(thread); | ||
231 | |||
230 | /* | 232 | /* |
231 | * Copy the floating point registers. There can be unused | 233 | * Copy the floating point registers. There can be unused |
232 | * registers see asm/hwcap.h for details. | 234 | * registers see asm/hwcap.h for details. |
@@ -251,9 +253,6 @@ static int restore_vfp_context(struct vfp_sigframe __user *frame) | |||
251 | __get_user_error(h->fpinst, &frame->ufp_exc.fpinst, err); | 253 | __get_user_error(h->fpinst, &frame->ufp_exc.fpinst, err); |
252 | __get_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err); | 254 | __get_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err); |
253 | 255 | ||
254 | if (!err) | ||
255 | vfp_flush_hwstate(thread); | ||
256 | |||
257 | return err ? -EFAULT : 0; | 256 | return err ? -EFAULT : 0; |
258 | } | 257 | } |
259 | 258 | ||
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 57db122a4f62..cdeb727527d3 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c | |||
@@ -233,20 +233,6 @@ void __ref cpu_die(void) | |||
233 | } | 233 | } |
234 | #endif /* CONFIG_HOTPLUG_CPU */ | 234 | #endif /* CONFIG_HOTPLUG_CPU */ |
235 | 235 | ||
236 | int __cpu_logical_map[NR_CPUS]; | ||
237 | |||
238 | void __init smp_setup_processor_id(void) | ||
239 | { | ||
240 | int i; | ||
241 | u32 cpu = is_smp() ? read_cpuid_mpidr() & 0xff : 0; | ||
242 | |||
243 | cpu_logical_map(0) = cpu; | ||
244 | for (i = 1; i < NR_CPUS; ++i) | ||
245 | cpu_logical_map(i) = i == cpu ? 0 : i; | ||
246 | |||
247 | printk(KERN_INFO "Booting Linux on physical CPU %d\n", cpu); | ||
248 | } | ||
249 | |||
250 | /* | 236 | /* |
251 | * Called by both boot and secondaries to move global data into | 237 | * Called by both boot and secondaries to move global data into |
252 | * per-processor storage. | 238 | * per-processor storage. |
@@ -443,9 +429,7 @@ static DEFINE_PER_CPU(struct clock_event_device, percpu_clockevent); | |||
443 | static void ipi_timer(void) | 429 | static void ipi_timer(void) |
444 | { | 430 | { |
445 | struct clock_event_device *evt = &__get_cpu_var(percpu_clockevent); | 431 | struct clock_event_device *evt = &__get_cpu_var(percpu_clockevent); |
446 | irq_enter(); | ||
447 | evt->event_handler(evt); | 432 | evt->event_handler(evt); |
448 | irq_exit(); | ||
449 | } | 433 | } |
450 | 434 | ||
451 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST | 435 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
@@ -548,7 +532,9 @@ void handle_IPI(int ipinr, struct pt_regs *regs) | |||
548 | 532 | ||
549 | switch (ipinr) { | 533 | switch (ipinr) { |
550 | case IPI_TIMER: | 534 | case IPI_TIMER: |
535 | irq_enter(); | ||
551 | ipi_timer(); | 536 | ipi_timer(); |
537 | irq_exit(); | ||
552 | break; | 538 | break; |
553 | 539 | ||
554 | case IPI_RESCHEDULE: | 540 | case IPI_RESCHEDULE: |
@@ -556,15 +542,21 @@ void handle_IPI(int ipinr, struct pt_regs *regs) | |||
556 | break; | 542 | break; |
557 | 543 | ||
558 | case IPI_CALL_FUNC: | 544 | case IPI_CALL_FUNC: |
545 | irq_enter(); | ||
559 | generic_smp_call_function_interrupt(); | 546 | generic_smp_call_function_interrupt(); |
547 | irq_exit(); | ||
560 | break; | 548 | break; |
561 | 549 | ||
562 | case IPI_CALL_FUNC_SINGLE: | 550 | case IPI_CALL_FUNC_SINGLE: |
551 | irq_enter(); | ||
563 | generic_smp_call_function_single_interrupt(); | 552 | generic_smp_call_function_single_interrupt(); |
553 | irq_exit(); | ||
564 | break; | 554 | break; |
565 | 555 | ||
566 | case IPI_CPU_STOP: | 556 | case IPI_CPU_STOP: |
557 | irq_enter(); | ||
567 | ipi_cpu_stop(cpu); | 558 | ipi_cpu_stop(cpu); |
559 | irq_exit(); | ||
568 | break; | 560 | break; |
569 | 561 | ||
570 | default: | 562 | default: |
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index c8e938553d47..7a79b24597b2 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c | |||
@@ -129,7 +129,7 @@ static struct notifier_block twd_cpufreq_nb = { | |||
129 | 129 | ||
130 | static int twd_cpufreq_init(void) | 130 | static int twd_cpufreq_init(void) |
131 | { | 131 | { |
132 | if (!IS_ERR(twd_clk)) | 132 | if (twd_evt && *__this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk)) |
133 | return cpufreq_register_notifier(&twd_cpufreq_nb, | 133 | return cpufreq_register_notifier(&twd_cpufreq_nb, |
134 | CPUFREQ_TRANSITION_NOTIFIER); | 134 | CPUFREQ_TRANSITION_NOTIFIER); |
135 | 135 | ||
@@ -252,6 +252,8 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk) | |||
252 | else | 252 | else |
253 | twd_calibrate_rate(); | 253 | twd_calibrate_rate(); |
254 | 254 | ||
255 | __raw_writel(0, twd_base + TWD_TIMER_CONTROL); | ||
256 | |||
255 | clk->name = "local_timer"; | 257 | clk->name = "local_timer"; |
256 | clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | | 258 | clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
257 | CLOCK_EVT_FEAT_C3STOP; | 259 | CLOCK_EVT_FEAT_C3STOP; |
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 99a572702509..f84dfe67724f 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c | |||
@@ -266,6 +266,7 @@ void die(const char *str, struct pt_regs *regs, int err) | |||
266 | { | 266 | { |
267 | struct thread_info *thread = current_thread_info(); | 267 | struct thread_info *thread = current_thread_info(); |
268 | int ret; | 268 | int ret; |
269 | enum bug_trap_type bug_type = BUG_TRAP_TYPE_NONE; | ||
269 | 270 | ||
270 | oops_enter(); | 271 | oops_enter(); |
271 | 272 | ||
@@ -273,7 +274,9 @@ void die(const char *str, struct pt_regs *regs, int err) | |||
273 | console_verbose(); | 274 | console_verbose(); |
274 | bust_spinlocks(1); | 275 | bust_spinlocks(1); |
275 | if (!user_mode(regs)) | 276 | if (!user_mode(regs)) |
276 | report_bug(regs->ARM_pc, regs); | 277 | bug_type = report_bug(regs->ARM_pc, regs); |
278 | if (bug_type != BUG_TRAP_TYPE_NONE) | ||
279 | str = "Oops - BUG"; | ||
277 | ret = __die(str, err, thread, regs); | 280 | ret = __die(str, err, thread, regs); |
278 | 281 | ||
279 | if (regs && kexec_should_crash(thread->task)) | 282 | if (regs && kexec_should_crash(thread->task)) |
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index f76e75548670..43a31fb06318 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S | |||
@@ -4,11 +4,13 @@ | |||
4 | */ | 4 | */ |
5 | 5 | ||
6 | #include <asm-generic/vmlinux.lds.h> | 6 | #include <asm-generic/vmlinux.lds.h> |
7 | #include <asm/cache.h> | ||
7 | #include <asm/thread_info.h> | 8 | #include <asm/thread_info.h> |
8 | #include <asm/memory.h> | 9 | #include <asm/memory.h> |
9 | #include <asm/page.h> | 10 | #include <asm/page.h> |
10 | 11 | ||
11 | #define PROC_INFO \ | 12 | #define PROC_INFO \ |
13 | . = ALIGN(4); \ | ||
12 | VMLINUX_SYMBOL(__proc_info_begin) = .; \ | 14 | VMLINUX_SYMBOL(__proc_info_begin) = .; \ |
13 | *(.proc.info.init) \ | 15 | *(.proc.info.init) \ |
14 | VMLINUX_SYMBOL(__proc_info_end) = .; | 16 | VMLINUX_SYMBOL(__proc_info_end) = .; |
@@ -181,7 +183,7 @@ SECTIONS | |||
181 | } | 183 | } |
182 | #endif | 184 | #endif |
183 | 185 | ||
184 | PERCPU_SECTION(32) | 186 | PERCPU_SECTION(L1_CACHE_BYTES) |
185 | 187 | ||
186 | #ifdef CONFIG_XIP_KERNEL | 188 | #ifdef CONFIG_XIP_KERNEL |
187 | __data_loc = ALIGN(4); /* location in binary */ | 189 | __data_loc = ALIGN(4); /* location in binary */ |
@@ -212,13 +214,13 @@ SECTIONS | |||
212 | #endif | 214 | #endif |
213 | 215 | ||
214 | NOSAVE_DATA | 216 | NOSAVE_DATA |
215 | CACHELINE_ALIGNED_DATA(32) | 217 | CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES) |
216 | READ_MOSTLY_DATA(32) | 218 | READ_MOSTLY_DATA(L1_CACHE_BYTES) |
217 | 219 | ||
218 | /* | 220 | /* |
219 | * The exception fixup table (might need resorting at runtime) | 221 | * The exception fixup table (might need resorting at runtime) |
220 | */ | 222 | */ |
221 | . = ALIGN(32); | 223 | . = ALIGN(4); |
222 | __start___ex_table = .; | 224 | __start___ex_table = .; |
223 | #ifdef CONFIG_MMU | 225 | #ifdef CONFIG_MMU |
224 | *(__ex_table) | 226 | *(__ex_table) |
diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S index 1b049cd7a49a..11093a7c3e32 100644 --- a/arch/arm/lib/getuser.S +++ b/arch/arm/lib/getuser.S | |||
@@ -31,18 +31,18 @@ | |||
31 | #include <asm/domain.h> | 31 | #include <asm/domain.h> |
32 | 32 | ||
33 | ENTRY(__get_user_1) | 33 | ENTRY(__get_user_1) |
34 | 1: T(ldrb) r2, [r0] | 34 | 1: TUSER(ldrb) r2, [r0] |
35 | mov r0, #0 | 35 | mov r0, #0 |
36 | mov pc, lr | 36 | mov pc, lr |
37 | ENDPROC(__get_user_1) | 37 | ENDPROC(__get_user_1) |
38 | 38 | ||
39 | ENTRY(__get_user_2) | 39 | ENTRY(__get_user_2) |
40 | #ifdef CONFIG_THUMB2_KERNEL | 40 | #ifdef CONFIG_THUMB2_KERNEL |
41 | 2: T(ldrb) r2, [r0] | 41 | 2: TUSER(ldrb) r2, [r0] |
42 | 3: T(ldrb) r3, [r0, #1] | 42 | 3: TUSER(ldrb) r3, [r0, #1] |
43 | #else | 43 | #else |
44 | 2: T(ldrb) r2, [r0], #1 | 44 | 2: TUSER(ldrb) r2, [r0], #1 |
45 | 3: T(ldrb) r3, [r0] | 45 | 3: TUSER(ldrb) r3, [r0] |
46 | #endif | 46 | #endif |
47 | #ifndef __ARMEB__ | 47 | #ifndef __ARMEB__ |
48 | orr r2, r2, r3, lsl #8 | 48 | orr r2, r2, r3, lsl #8 |
@@ -54,7 +54,7 @@ ENTRY(__get_user_2) | |||
54 | ENDPROC(__get_user_2) | 54 | ENDPROC(__get_user_2) |
55 | 55 | ||
56 | ENTRY(__get_user_4) | 56 | ENTRY(__get_user_4) |
57 | 4: T(ldr) r2, [r0] | 57 | 4: TUSER(ldr) r2, [r0] |
58 | mov r0, #0 | 58 | mov r0, #0 |
59 | mov pc, lr | 59 | mov pc, lr |
60 | ENDPROC(__get_user_4) | 60 | ENDPROC(__get_user_4) |
diff --git a/arch/arm/lib/putuser.S b/arch/arm/lib/putuser.S index c023fc11e86c..7db25990c589 100644 --- a/arch/arm/lib/putuser.S +++ b/arch/arm/lib/putuser.S | |||
@@ -31,7 +31,7 @@ | |||
31 | #include <asm/domain.h> | 31 | #include <asm/domain.h> |
32 | 32 | ||
33 | ENTRY(__put_user_1) | 33 | ENTRY(__put_user_1) |
34 | 1: T(strb) r2, [r0] | 34 | 1: TUSER(strb) r2, [r0] |
35 | mov r0, #0 | 35 | mov r0, #0 |
36 | mov pc, lr | 36 | mov pc, lr |
37 | ENDPROC(__put_user_1) | 37 | ENDPROC(__put_user_1) |
@@ -40,19 +40,19 @@ ENTRY(__put_user_2) | |||
40 | mov ip, r2, lsr #8 | 40 | mov ip, r2, lsr #8 |
41 | #ifdef CONFIG_THUMB2_KERNEL | 41 | #ifdef CONFIG_THUMB2_KERNEL |
42 | #ifndef __ARMEB__ | 42 | #ifndef __ARMEB__ |
43 | 2: T(strb) r2, [r0] | 43 | 2: TUSER(strb) r2, [r0] |
44 | 3: T(strb) ip, [r0, #1] | 44 | 3: TUSER(strb) ip, [r0, #1] |
45 | #else | 45 | #else |
46 | 2: T(strb) ip, [r0] | 46 | 2: TUSER(strb) ip, [r0] |
47 | 3: T(strb) r2, [r0, #1] | 47 | 3: TUSER(strb) r2, [r0, #1] |
48 | #endif | 48 | #endif |
49 | #else /* !CONFIG_THUMB2_KERNEL */ | 49 | #else /* !CONFIG_THUMB2_KERNEL */ |
50 | #ifndef __ARMEB__ | 50 | #ifndef __ARMEB__ |
51 | 2: T(strb) r2, [r0], #1 | 51 | 2: TUSER(strb) r2, [r0], #1 |
52 | 3: T(strb) ip, [r0] | 52 | 3: TUSER(strb) ip, [r0] |
53 | #else | 53 | #else |
54 | 2: T(strb) ip, [r0], #1 | 54 | 2: TUSER(strb) ip, [r0], #1 |
55 | 3: T(strb) r2, [r0] | 55 | 3: TUSER(strb) r2, [r0] |
56 | #endif | 56 | #endif |
57 | #endif /* CONFIG_THUMB2_KERNEL */ | 57 | #endif /* CONFIG_THUMB2_KERNEL */ |
58 | mov r0, #0 | 58 | mov r0, #0 |
@@ -60,18 +60,18 @@ ENTRY(__put_user_2) | |||
60 | ENDPROC(__put_user_2) | 60 | ENDPROC(__put_user_2) |
61 | 61 | ||
62 | ENTRY(__put_user_4) | 62 | ENTRY(__put_user_4) |
63 | 4: T(str) r2, [r0] | 63 | 4: TUSER(str) r2, [r0] |
64 | mov r0, #0 | 64 | mov r0, #0 |
65 | mov pc, lr | 65 | mov pc, lr |
66 | ENDPROC(__put_user_4) | 66 | ENDPROC(__put_user_4) |
67 | 67 | ||
68 | ENTRY(__put_user_8) | 68 | ENTRY(__put_user_8) |
69 | #ifdef CONFIG_THUMB2_KERNEL | 69 | #ifdef CONFIG_THUMB2_KERNEL |
70 | 5: T(str) r2, [r0] | 70 | 5: TUSER(str) r2, [r0] |
71 | 6: T(str) r3, [r0, #4] | 71 | 6: TUSER(str) r3, [r0, #4] |
72 | #else | 72 | #else |
73 | 5: T(str) r2, [r0], #4 | 73 | 5: TUSER(str) r2, [r0], #4 |
74 | 6: T(str) r3, [r0] | 74 | 6: TUSER(str) r3, [r0] |
75 | #endif | 75 | #endif |
76 | mov r0, #0 | 76 | mov r0, #0 |
77 | mov pc, lr | 77 | mov pc, lr |
diff --git a/arch/arm/lib/uaccess.S b/arch/arm/lib/uaccess.S index d0ece2aeb70d..5c908b1cb8ed 100644 --- a/arch/arm/lib/uaccess.S +++ b/arch/arm/lib/uaccess.S | |||
@@ -32,11 +32,11 @@ | |||
32 | rsb ip, ip, #4 | 32 | rsb ip, ip, #4 |
33 | cmp ip, #2 | 33 | cmp ip, #2 |
34 | ldrb r3, [r1], #1 | 34 | ldrb r3, [r1], #1 |
35 | USER( T(strb) r3, [r0], #1) @ May fault | 35 | USER( TUSER( strb) r3, [r0], #1) @ May fault |
36 | ldrgeb r3, [r1], #1 | 36 | ldrgeb r3, [r1], #1 |
37 | USER( T(strgeb) r3, [r0], #1) @ May fault | 37 | USER( TUSER( strgeb) r3, [r0], #1) @ May fault |
38 | ldrgtb r3, [r1], #1 | 38 | ldrgtb r3, [r1], #1 |
39 | USER( T(strgtb) r3, [r0], #1) @ May fault | 39 | USER( TUSER( strgtb) r3, [r0], #1) @ May fault |
40 | sub r2, r2, ip | 40 | sub r2, r2, ip |
41 | b .Lc2u_dest_aligned | 41 | b .Lc2u_dest_aligned |
42 | 42 | ||
@@ -59,7 +59,7 @@ ENTRY(__copy_to_user) | |||
59 | addmi ip, r2, #4 | 59 | addmi ip, r2, #4 |
60 | bmi .Lc2u_0nowords | 60 | bmi .Lc2u_0nowords |
61 | ldr r3, [r1], #4 | 61 | ldr r3, [r1], #4 |
62 | USER( T(str) r3, [r0], #4) @ May fault | 62 | USER( TUSER( str) r3, [r0], #4) @ May fault |
63 | mov ip, r0, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction | 63 | mov ip, r0, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction |
64 | rsb ip, ip, #0 | 64 | rsb ip, ip, #0 |
65 | movs ip, ip, lsr #32 - PAGE_SHIFT | 65 | movs ip, ip, lsr #32 - PAGE_SHIFT |
@@ -88,18 +88,18 @@ USER( T(str) r3, [r0], #4) @ May fault | |||
88 | stmneia r0!, {r3 - r4} @ Shouldnt fault | 88 | stmneia r0!, {r3 - r4} @ Shouldnt fault |
89 | tst ip, #4 | 89 | tst ip, #4 |
90 | ldrne r3, [r1], #4 | 90 | ldrne r3, [r1], #4 |
91 | T(strne) r3, [r0], #4 @ Shouldnt fault | 91 | TUSER( strne) r3, [r0], #4 @ Shouldnt fault |
92 | ands ip, ip, #3 | 92 | ands ip, ip, #3 |
93 | beq .Lc2u_0fupi | 93 | beq .Lc2u_0fupi |
94 | .Lc2u_0nowords: teq ip, #0 | 94 | .Lc2u_0nowords: teq ip, #0 |
95 | beq .Lc2u_finished | 95 | beq .Lc2u_finished |
96 | .Lc2u_nowords: cmp ip, #2 | 96 | .Lc2u_nowords: cmp ip, #2 |
97 | ldrb r3, [r1], #1 | 97 | ldrb r3, [r1], #1 |
98 | USER( T(strb) r3, [r0], #1) @ May fault | 98 | USER( TUSER( strb) r3, [r0], #1) @ May fault |
99 | ldrgeb r3, [r1], #1 | 99 | ldrgeb r3, [r1], #1 |
100 | USER( T(strgeb) r3, [r0], #1) @ May fault | 100 | USER( TUSER( strgeb) r3, [r0], #1) @ May fault |
101 | ldrgtb r3, [r1], #1 | 101 | ldrgtb r3, [r1], #1 |
102 | USER( T(strgtb) r3, [r0], #1) @ May fault | 102 | USER( TUSER( strgtb) r3, [r0], #1) @ May fault |
103 | b .Lc2u_finished | 103 | b .Lc2u_finished |
104 | 104 | ||
105 | .Lc2u_not_enough: | 105 | .Lc2u_not_enough: |
@@ -120,7 +120,7 @@ USER( T(strgtb) r3, [r0], #1) @ May fault | |||
120 | mov r3, r7, pull #8 | 120 | mov r3, r7, pull #8 |
121 | ldr r7, [r1], #4 | 121 | ldr r7, [r1], #4 |
122 | orr r3, r3, r7, push #24 | 122 | orr r3, r3, r7, push #24 |
123 | USER( T(str) r3, [r0], #4) @ May fault | 123 | USER( TUSER( str) r3, [r0], #4) @ May fault |
124 | mov ip, r0, lsl #32 - PAGE_SHIFT | 124 | mov ip, r0, lsl #32 - PAGE_SHIFT |
125 | rsb ip, ip, #0 | 125 | rsb ip, ip, #0 |
126 | movs ip, ip, lsr #32 - PAGE_SHIFT | 126 | movs ip, ip, lsr #32 - PAGE_SHIFT |
@@ -155,18 +155,18 @@ USER( T(str) r3, [r0], #4) @ May fault | |||
155 | movne r3, r7, pull #8 | 155 | movne r3, r7, pull #8 |
156 | ldrne r7, [r1], #4 | 156 | ldrne r7, [r1], #4 |
157 | orrne r3, r3, r7, push #24 | 157 | orrne r3, r3, r7, push #24 |
158 | T(strne) r3, [r0], #4 @ Shouldnt fault | 158 | TUSER( strne) r3, [r0], #4 @ Shouldnt fault |
159 | ands ip, ip, #3 | 159 | ands ip, ip, #3 |
160 | beq .Lc2u_1fupi | 160 | beq .Lc2u_1fupi |
161 | .Lc2u_1nowords: mov r3, r7, get_byte_1 | 161 | .Lc2u_1nowords: mov r3, r7, get_byte_1 |
162 | teq ip, #0 | 162 | teq ip, #0 |
163 | beq .Lc2u_finished | 163 | beq .Lc2u_finished |
164 | cmp ip, #2 | 164 | cmp ip, #2 |
165 | USER( T(strb) r3, [r0], #1) @ May fault | 165 | USER( TUSER( strb) r3, [r0], #1) @ May fault |
166 | movge r3, r7, get_byte_2 | 166 | movge r3, r7, get_byte_2 |
167 | USER( T(strgeb) r3, [r0], #1) @ May fault | 167 | USER( TUSER( strgeb) r3, [r0], #1) @ May fault |
168 | movgt r3, r7, get_byte_3 | 168 | movgt r3, r7, get_byte_3 |
169 | USER( T(strgtb) r3, [r0], #1) @ May fault | 169 | USER( TUSER( strgtb) r3, [r0], #1) @ May fault |
170 | b .Lc2u_finished | 170 | b .Lc2u_finished |
171 | 171 | ||
172 | .Lc2u_2fupi: subs r2, r2, #4 | 172 | .Lc2u_2fupi: subs r2, r2, #4 |
@@ -175,7 +175,7 @@ USER( T(strgtb) r3, [r0], #1) @ May fault | |||
175 | mov r3, r7, pull #16 | 175 | mov r3, r7, pull #16 |
176 | ldr r7, [r1], #4 | 176 | ldr r7, [r1], #4 |
177 | orr r3, r3, r7, push #16 | 177 | orr r3, r3, r7, push #16 |
178 | USER( T(str) r3, [r0], #4) @ May fault | 178 | USER( TUSER( str) r3, [r0], #4) @ May fault |
179 | mov ip, r0, lsl #32 - PAGE_SHIFT | 179 | mov ip, r0, lsl #32 - PAGE_SHIFT |
180 | rsb ip, ip, #0 | 180 | rsb ip, ip, #0 |
181 | movs ip, ip, lsr #32 - PAGE_SHIFT | 181 | movs ip, ip, lsr #32 - PAGE_SHIFT |
@@ -210,18 +210,18 @@ USER( T(str) r3, [r0], #4) @ May fault | |||
210 | movne r3, r7, pull #16 | 210 | movne r3, r7, pull #16 |
211 | ldrne r7, [r1], #4 | 211 | ldrne r7, [r1], #4 |
212 | orrne r3, r3, r7, push #16 | 212 | orrne r3, r3, r7, push #16 |
213 | T(strne) r3, [r0], #4 @ Shouldnt fault | 213 | TUSER( strne) r3, [r0], #4 @ Shouldnt fault |
214 | ands ip, ip, #3 | 214 | ands ip, ip, #3 |
215 | beq .Lc2u_2fupi | 215 | beq .Lc2u_2fupi |
216 | .Lc2u_2nowords: mov r3, r7, get_byte_2 | 216 | .Lc2u_2nowords: mov r3, r7, get_byte_2 |
217 | teq ip, #0 | 217 | teq ip, #0 |
218 | beq .Lc2u_finished | 218 | beq .Lc2u_finished |
219 | cmp ip, #2 | 219 | cmp ip, #2 |
220 | USER( T(strb) r3, [r0], #1) @ May fault | 220 | USER( TUSER( strb) r3, [r0], #1) @ May fault |
221 | movge r3, r7, get_byte_3 | 221 | movge r3, r7, get_byte_3 |
222 | USER( T(strgeb) r3, [r0], #1) @ May fault | 222 | USER( TUSER( strgeb) r3, [r0], #1) @ May fault |
223 | ldrgtb r3, [r1], #0 | 223 | ldrgtb r3, [r1], #0 |
224 | USER( T(strgtb) r3, [r0], #1) @ May fault | 224 | USER( TUSER( strgtb) r3, [r0], #1) @ May fault |
225 | b .Lc2u_finished | 225 | b .Lc2u_finished |
226 | 226 | ||
227 | .Lc2u_3fupi: subs r2, r2, #4 | 227 | .Lc2u_3fupi: subs r2, r2, #4 |
@@ -230,7 +230,7 @@ USER( T(strgtb) r3, [r0], #1) @ May fault | |||
230 | mov r3, r7, pull #24 | 230 | mov r3, r7, pull #24 |
231 | ldr r7, [r1], #4 | 231 | ldr r7, [r1], #4 |
232 | orr r3, r3, r7, push #8 | 232 | orr r3, r3, r7, push #8 |
233 | USER( T(str) r3, [r0], #4) @ May fault | 233 | USER( TUSER( str) r3, [r0], #4) @ May fault |
234 | mov ip, r0, lsl #32 - PAGE_SHIFT | 234 | mov ip, r0, lsl #32 - PAGE_SHIFT |
235 | rsb ip, ip, #0 | 235 | rsb ip, ip, #0 |
236 | movs ip, ip, lsr #32 - PAGE_SHIFT | 236 | movs ip, ip, lsr #32 - PAGE_SHIFT |
@@ -265,18 +265,18 @@ USER( T(str) r3, [r0], #4) @ May fault | |||
265 | movne r3, r7, pull #24 | 265 | movne r3, r7, pull #24 |
266 | ldrne r7, [r1], #4 | 266 | ldrne r7, [r1], #4 |
267 | orrne r3, r3, r7, push #8 | 267 | orrne r3, r3, r7, push #8 |
268 | T(strne) r3, [r0], #4 @ Shouldnt fault | 268 | TUSER( strne) r3, [r0], #4 @ Shouldnt fault |
269 | ands ip, ip, #3 | 269 | ands ip, ip, #3 |
270 | beq .Lc2u_3fupi | 270 | beq .Lc2u_3fupi |
271 | .Lc2u_3nowords: mov r3, r7, get_byte_3 | 271 | .Lc2u_3nowords: mov r3, r7, get_byte_3 |
272 | teq ip, #0 | 272 | teq ip, #0 |
273 | beq .Lc2u_finished | 273 | beq .Lc2u_finished |
274 | cmp ip, #2 | 274 | cmp ip, #2 |
275 | USER( T(strb) r3, [r0], #1) @ May fault | 275 | USER( TUSER( strb) r3, [r0], #1) @ May fault |
276 | ldrgeb r3, [r1], #1 | 276 | ldrgeb r3, [r1], #1 |
277 | USER( T(strgeb) r3, [r0], #1) @ May fault | 277 | USER( TUSER( strgeb) r3, [r0], #1) @ May fault |
278 | ldrgtb r3, [r1], #0 | 278 | ldrgtb r3, [r1], #0 |
279 | USER( T(strgtb) r3, [r0], #1) @ May fault | 279 | USER( TUSER( strgtb) r3, [r0], #1) @ May fault |
280 | b .Lc2u_finished | 280 | b .Lc2u_finished |
281 | ENDPROC(__copy_to_user) | 281 | ENDPROC(__copy_to_user) |
282 | 282 | ||
@@ -295,11 +295,11 @@ ENDPROC(__copy_to_user) | |||
295 | .Lcfu_dest_not_aligned: | 295 | .Lcfu_dest_not_aligned: |
296 | rsb ip, ip, #4 | 296 | rsb ip, ip, #4 |
297 | cmp ip, #2 | 297 | cmp ip, #2 |
298 | USER( T(ldrb) r3, [r1], #1) @ May fault | 298 | USER( TUSER( ldrb) r3, [r1], #1) @ May fault |
299 | strb r3, [r0], #1 | 299 | strb r3, [r0], #1 |
300 | USER( T(ldrgeb) r3, [r1], #1) @ May fault | 300 | USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault |
301 | strgeb r3, [r0], #1 | 301 | strgeb r3, [r0], #1 |
302 | USER( T(ldrgtb) r3, [r1], #1) @ May fault | 302 | USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault |
303 | strgtb r3, [r0], #1 | 303 | strgtb r3, [r0], #1 |
304 | sub r2, r2, ip | 304 | sub r2, r2, ip |
305 | b .Lcfu_dest_aligned | 305 | b .Lcfu_dest_aligned |
@@ -322,7 +322,7 @@ ENTRY(__copy_from_user) | |||
322 | .Lcfu_0fupi: subs r2, r2, #4 | 322 | .Lcfu_0fupi: subs r2, r2, #4 |
323 | addmi ip, r2, #4 | 323 | addmi ip, r2, #4 |
324 | bmi .Lcfu_0nowords | 324 | bmi .Lcfu_0nowords |
325 | USER( T(ldr) r3, [r1], #4) | 325 | USER( TUSER( ldr) r3, [r1], #4) |
326 | str r3, [r0], #4 | 326 | str r3, [r0], #4 |
327 | mov ip, r1, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction | 327 | mov ip, r1, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction |
328 | rsb ip, ip, #0 | 328 | rsb ip, ip, #0 |
@@ -351,18 +351,18 @@ USER( T(ldr) r3, [r1], #4) | |||
351 | ldmneia r1!, {r3 - r4} @ Shouldnt fault | 351 | ldmneia r1!, {r3 - r4} @ Shouldnt fault |
352 | stmneia r0!, {r3 - r4} | 352 | stmneia r0!, {r3 - r4} |
353 | tst ip, #4 | 353 | tst ip, #4 |
354 | T(ldrne) r3, [r1], #4 @ Shouldnt fault | 354 | TUSER( ldrne) r3, [r1], #4 @ Shouldnt fault |
355 | strne r3, [r0], #4 | 355 | strne r3, [r0], #4 |
356 | ands ip, ip, #3 | 356 | ands ip, ip, #3 |
357 | beq .Lcfu_0fupi | 357 | beq .Lcfu_0fupi |
358 | .Lcfu_0nowords: teq ip, #0 | 358 | .Lcfu_0nowords: teq ip, #0 |
359 | beq .Lcfu_finished | 359 | beq .Lcfu_finished |
360 | .Lcfu_nowords: cmp ip, #2 | 360 | .Lcfu_nowords: cmp ip, #2 |
361 | USER( T(ldrb) r3, [r1], #1) @ May fault | 361 | USER( TUSER( ldrb) r3, [r1], #1) @ May fault |
362 | strb r3, [r0], #1 | 362 | strb r3, [r0], #1 |
363 | USER( T(ldrgeb) r3, [r1], #1) @ May fault | 363 | USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault |
364 | strgeb r3, [r0], #1 | 364 | strgeb r3, [r0], #1 |
365 | USER( T(ldrgtb) r3, [r1], #1) @ May fault | 365 | USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault |
366 | strgtb r3, [r0], #1 | 366 | strgtb r3, [r0], #1 |
367 | b .Lcfu_finished | 367 | b .Lcfu_finished |
368 | 368 | ||
@@ -375,7 +375,7 @@ USER( T(ldrgtb) r3, [r1], #1) @ May fault | |||
375 | 375 | ||
376 | .Lcfu_src_not_aligned: | 376 | .Lcfu_src_not_aligned: |
377 | bic r1, r1, #3 | 377 | bic r1, r1, #3 |
378 | USER( T(ldr) r7, [r1], #4) @ May fault | 378 | USER( TUSER( ldr) r7, [r1], #4) @ May fault |
379 | cmp ip, #2 | 379 | cmp ip, #2 |
380 | bgt .Lcfu_3fupi | 380 | bgt .Lcfu_3fupi |
381 | beq .Lcfu_2fupi | 381 | beq .Lcfu_2fupi |
@@ -383,7 +383,7 @@ USER( T(ldr) r7, [r1], #4) @ May fault | |||
383 | addmi ip, r2, #4 | 383 | addmi ip, r2, #4 |
384 | bmi .Lcfu_1nowords | 384 | bmi .Lcfu_1nowords |
385 | mov r3, r7, pull #8 | 385 | mov r3, r7, pull #8 |
386 | USER( T(ldr) r7, [r1], #4) @ May fault | 386 | USER( TUSER( ldr) r7, [r1], #4) @ May fault |
387 | orr r3, r3, r7, push #24 | 387 | orr r3, r3, r7, push #24 |
388 | str r3, [r0], #4 | 388 | str r3, [r0], #4 |
389 | mov ip, r1, lsl #32 - PAGE_SHIFT | 389 | mov ip, r1, lsl #32 - PAGE_SHIFT |
@@ -418,7 +418,7 @@ USER( T(ldr) r7, [r1], #4) @ May fault | |||
418 | stmneia r0!, {r3 - r4} | 418 | stmneia r0!, {r3 - r4} |
419 | tst ip, #4 | 419 | tst ip, #4 |
420 | movne r3, r7, pull #8 | 420 | movne r3, r7, pull #8 |
421 | USER( T(ldrne) r7, [r1], #4) @ May fault | 421 | USER( TUSER( ldrne) r7, [r1], #4) @ May fault |
422 | orrne r3, r3, r7, push #24 | 422 | orrne r3, r3, r7, push #24 |
423 | strne r3, [r0], #4 | 423 | strne r3, [r0], #4 |
424 | ands ip, ip, #3 | 424 | ands ip, ip, #3 |
@@ -438,7 +438,7 @@ USER( T(ldrne) r7, [r1], #4) @ May fault | |||
438 | addmi ip, r2, #4 | 438 | addmi ip, r2, #4 |
439 | bmi .Lcfu_2nowords | 439 | bmi .Lcfu_2nowords |
440 | mov r3, r7, pull #16 | 440 | mov r3, r7, pull #16 |
441 | USER( T(ldr) r7, [r1], #4) @ May fault | 441 | USER( TUSER( ldr) r7, [r1], #4) @ May fault |
442 | orr r3, r3, r7, push #16 | 442 | orr r3, r3, r7, push #16 |
443 | str r3, [r0], #4 | 443 | str r3, [r0], #4 |
444 | mov ip, r1, lsl #32 - PAGE_SHIFT | 444 | mov ip, r1, lsl #32 - PAGE_SHIFT |
@@ -474,7 +474,7 @@ USER( T(ldr) r7, [r1], #4) @ May fault | |||
474 | stmneia r0!, {r3 - r4} | 474 | stmneia r0!, {r3 - r4} |
475 | tst ip, #4 | 475 | tst ip, #4 |
476 | movne r3, r7, pull #16 | 476 | movne r3, r7, pull #16 |
477 | USER( T(ldrne) r7, [r1], #4) @ May fault | 477 | USER( TUSER( ldrne) r7, [r1], #4) @ May fault |
478 | orrne r3, r3, r7, push #16 | 478 | orrne r3, r3, r7, push #16 |
479 | strne r3, [r0], #4 | 479 | strne r3, [r0], #4 |
480 | ands ip, ip, #3 | 480 | ands ip, ip, #3 |
@@ -486,7 +486,7 @@ USER( T(ldrne) r7, [r1], #4) @ May fault | |||
486 | strb r3, [r0], #1 | 486 | strb r3, [r0], #1 |
487 | movge r3, r7, get_byte_3 | 487 | movge r3, r7, get_byte_3 |
488 | strgeb r3, [r0], #1 | 488 | strgeb r3, [r0], #1 |
489 | USER( T(ldrgtb) r3, [r1], #0) @ May fault | 489 | USER( TUSER( ldrgtb) r3, [r1], #0) @ May fault |
490 | strgtb r3, [r0], #1 | 490 | strgtb r3, [r0], #1 |
491 | b .Lcfu_finished | 491 | b .Lcfu_finished |
492 | 492 | ||
@@ -494,7 +494,7 @@ USER( T(ldrgtb) r3, [r1], #0) @ May fault | |||
494 | addmi ip, r2, #4 | 494 | addmi ip, r2, #4 |
495 | bmi .Lcfu_3nowords | 495 | bmi .Lcfu_3nowords |
496 | mov r3, r7, pull #24 | 496 | mov r3, r7, pull #24 |
497 | USER( T(ldr) r7, [r1], #4) @ May fault | 497 | USER( TUSER( ldr) r7, [r1], #4) @ May fault |
498 | orr r3, r3, r7, push #8 | 498 | orr r3, r3, r7, push #8 |
499 | str r3, [r0], #4 | 499 | str r3, [r0], #4 |
500 | mov ip, r1, lsl #32 - PAGE_SHIFT | 500 | mov ip, r1, lsl #32 - PAGE_SHIFT |
@@ -529,7 +529,7 @@ USER( T(ldr) r7, [r1], #4) @ May fault | |||
529 | stmneia r0!, {r3 - r4} | 529 | stmneia r0!, {r3 - r4} |
530 | tst ip, #4 | 530 | tst ip, #4 |
531 | movne r3, r7, pull #24 | 531 | movne r3, r7, pull #24 |
532 | USER( T(ldrne) r7, [r1], #4) @ May fault | 532 | USER( TUSER( ldrne) r7, [r1], #4) @ May fault |
533 | orrne r3, r3, r7, push #8 | 533 | orrne r3, r3, r7, push #8 |
534 | strne r3, [r0], #4 | 534 | strne r3, [r0], #4 |
535 | ands ip, ip, #3 | 535 | ands ip, ip, #3 |
@@ -539,9 +539,9 @@ USER( T(ldrne) r7, [r1], #4) @ May fault | |||
539 | beq .Lcfu_finished | 539 | beq .Lcfu_finished |
540 | cmp ip, #2 | 540 | cmp ip, #2 |
541 | strb r3, [r0], #1 | 541 | strb r3, [r0], #1 |
542 | USER( T(ldrgeb) r3, [r1], #1) @ May fault | 542 | USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault |
543 | strgeb r3, [r0], #1 | 543 | strgeb r3, [r0], #1 |
544 | USER( T(ldrgtb) r3, [r1], #1) @ May fault | 544 | USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault |
545 | strgtb r3, [r0], #1 | 545 | strgtb r3, [r0], #1 |
546 | b .Lcfu_finished | 546 | b .Lcfu_finished |
547 | ENDPROC(__copy_from_user) | 547 | ENDPROC(__copy_from_user) |
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 4f991f295284..71feb00a1e99 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig | |||
@@ -18,6 +18,12 @@ config HAVE_AT91_USART4 | |||
18 | config HAVE_AT91_USART5 | 18 | config HAVE_AT91_USART5 |
19 | bool | 19 | bool |
20 | 20 | ||
21 | config AT91_SAM9_ALT_RESET | ||
22 | bool | ||
23 | |||
24 | config AT91_SAM9G45_RESET | ||
25 | bool | ||
26 | |||
21 | menu "Atmel AT91 System-on-Chip" | 27 | menu "Atmel AT91 System-on-Chip" |
22 | 28 | ||
23 | choice | 29 | choice |
@@ -39,6 +45,7 @@ config ARCH_AT91SAM9260 | |||
39 | select HAVE_AT91_USART4 | 45 | select HAVE_AT91_USART4 |
40 | select HAVE_AT91_USART5 | 46 | select HAVE_AT91_USART5 |
41 | select HAVE_NET_MACB | 47 | select HAVE_NET_MACB |
48 | select AT91_SAM9_ALT_RESET | ||
42 | 49 | ||
43 | config ARCH_AT91SAM9261 | 50 | config ARCH_AT91SAM9261 |
44 | bool "AT91SAM9261" | 51 | bool "AT91SAM9261" |
@@ -46,6 +53,7 @@ config ARCH_AT91SAM9261 | |||
46 | select GENERIC_CLOCKEVENTS | 53 | select GENERIC_CLOCKEVENTS |
47 | select HAVE_FB_ATMEL | 54 | select HAVE_FB_ATMEL |
48 | select HAVE_AT91_DBGU0 | 55 | select HAVE_AT91_DBGU0 |
56 | select AT91_SAM9_ALT_RESET | ||
49 | 57 | ||
50 | config ARCH_AT91SAM9G10 | 58 | config ARCH_AT91SAM9G10 |
51 | bool "AT91SAM9G10" | 59 | bool "AT91SAM9G10" |
@@ -53,6 +61,7 @@ config ARCH_AT91SAM9G10 | |||
53 | select GENERIC_CLOCKEVENTS | 61 | select GENERIC_CLOCKEVENTS |
54 | select HAVE_AT91_DBGU0 | 62 | select HAVE_AT91_DBGU0 |
55 | select HAVE_FB_ATMEL | 63 | select HAVE_FB_ATMEL |
64 | select AT91_SAM9_ALT_RESET | ||
56 | 65 | ||
57 | config ARCH_AT91SAM9263 | 66 | config ARCH_AT91SAM9263 |
58 | bool "AT91SAM9263" | 67 | bool "AT91SAM9263" |
@@ -61,6 +70,7 @@ config ARCH_AT91SAM9263 | |||
61 | select HAVE_FB_ATMEL | 70 | select HAVE_FB_ATMEL |
62 | select HAVE_NET_MACB | 71 | select HAVE_NET_MACB |
63 | select HAVE_AT91_DBGU1 | 72 | select HAVE_AT91_DBGU1 |
73 | select AT91_SAM9_ALT_RESET | ||
64 | 74 | ||
65 | config ARCH_AT91SAM9RL | 75 | config ARCH_AT91SAM9RL |
66 | bool "AT91SAM9RL" | 76 | bool "AT91SAM9RL" |
@@ -69,6 +79,7 @@ config ARCH_AT91SAM9RL | |||
69 | select HAVE_AT91_USART3 | 79 | select HAVE_AT91_USART3 |
70 | select HAVE_FB_ATMEL | 80 | select HAVE_FB_ATMEL |
71 | select HAVE_AT91_DBGU0 | 81 | select HAVE_AT91_DBGU0 |
82 | select AT91_SAM9_ALT_RESET | ||
72 | 83 | ||
73 | config ARCH_AT91SAM9G20 | 84 | config ARCH_AT91SAM9G20 |
74 | bool "AT91SAM9G20" | 85 | bool "AT91SAM9G20" |
@@ -79,6 +90,7 @@ config ARCH_AT91SAM9G20 | |||
79 | select HAVE_AT91_USART4 | 90 | select HAVE_AT91_USART4 |
80 | select HAVE_AT91_USART5 | 91 | select HAVE_AT91_USART5 |
81 | select HAVE_NET_MACB | 92 | select HAVE_NET_MACB |
93 | select AT91_SAM9_ALT_RESET | ||
82 | 94 | ||
83 | config ARCH_AT91SAM9G45 | 95 | config ARCH_AT91SAM9G45 |
84 | bool "AT91SAM9G45" | 96 | bool "AT91SAM9G45" |
@@ -88,6 +100,7 @@ config ARCH_AT91SAM9G45 | |||
88 | select HAVE_FB_ATMEL | 100 | select HAVE_FB_ATMEL |
89 | select HAVE_NET_MACB | 101 | select HAVE_NET_MACB |
90 | select HAVE_AT91_DBGU1 | 102 | select HAVE_AT91_DBGU1 |
103 | select AT91_SAM9G45_RESET | ||
91 | 104 | ||
92 | config ARCH_AT91CAP9 | 105 | config ARCH_AT91CAP9 |
93 | bool "AT91CAP9" | 106 | bool "AT91CAP9" |
@@ -96,6 +109,7 @@ config ARCH_AT91CAP9 | |||
96 | select HAVE_FB_ATMEL | 109 | select HAVE_FB_ATMEL |
97 | select HAVE_NET_MACB | 110 | select HAVE_NET_MACB |
98 | select HAVE_AT91_DBGU1 | 111 | select HAVE_AT91_DBGU1 |
112 | select AT91_SAM9G45_RESET | ||
99 | 113 | ||
100 | config ARCH_AT91X40 | 114 | config ARCH_AT91X40 |
101 | bool "AT91x40" | 115 | bool "AT91x40" |
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 242174f9f355..705e1fbded39 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile | |||
@@ -8,15 +8,17 @@ obj-n := | |||
8 | obj- := | 8 | obj- := |
9 | 9 | ||
10 | obj-$(CONFIG_AT91_PMC_UNIT) += clock.o | 10 | obj-$(CONFIG_AT91_PMC_UNIT) += clock.o |
11 | obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o | ||
12 | obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o | ||
11 | 13 | ||
12 | # CPU-specific support | 14 | # CPU-specific support |
13 | obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o | 15 | obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o |
14 | obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o | 16 | obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o |
15 | obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o | 17 | obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o |
16 | obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o | 18 | obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o |
17 | obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o at91sam9_alt_reset.o | 19 | obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o |
18 | obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o at91sam9_alt_reset.o | 20 | obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o |
19 | obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o | 21 | obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o |
20 | obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o | 22 | obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o |
21 | obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o | 23 | obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o |
22 | obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o | 24 | obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o |
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c index edb879ac04c8..a42edc25a87e 100644 --- a/arch/arm/mach-at91/at91cap9.c +++ b/arch/arm/mach-at91/at91cap9.c | |||
@@ -21,7 +21,6 @@ | |||
21 | #include <mach/cpu.h> | 21 | #include <mach/cpu.h> |
22 | #include <mach/at91cap9.h> | 22 | #include <mach/at91cap9.h> |
23 | #include <mach/at91_pmc.h> | 23 | #include <mach/at91_pmc.h> |
24 | #include <mach/at91_rstc.h> | ||
25 | 24 | ||
26 | #include "soc.h" | 25 | #include "soc.h" |
27 | #include "generic.h" | 26 | #include "generic.h" |
@@ -314,11 +313,6 @@ static struct at91_gpio_bank at91cap9_gpio[] __initdata = { | |||
314 | } | 313 | } |
315 | }; | 314 | }; |
316 | 315 | ||
317 | static void at91cap9_restart(char mode, const char *cmd) | ||
318 | { | ||
319 | at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); | ||
320 | } | ||
321 | |||
322 | /* -------------------------------------------------------------------- | 316 | /* -------------------------------------------------------------------- |
323 | * AT91CAP9 processor initialization | 317 | * AT91CAP9 processor initialization |
324 | * -------------------------------------------------------------------- */ | 318 | * -------------------------------------------------------------------- */ |
@@ -331,13 +325,14 @@ static void __init at91cap9_map_io(void) | |||
331 | static void __init at91cap9_ioremap_registers(void) | 325 | static void __init at91cap9_ioremap_registers(void) |
332 | { | 326 | { |
333 | at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC); | 327 | at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC); |
328 | at91_ioremap_rstc(AT91CAP9_BASE_RSTC); | ||
334 | at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT); | 329 | at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT); |
335 | at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC); | 330 | at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC); |
336 | } | 331 | } |
337 | 332 | ||
338 | static void __init at91cap9_initialize(void) | 333 | static void __init at91cap9_initialize(void) |
339 | { | 334 | { |
340 | arm_pm_restart = at91cap9_restart; | 335 | arm_pm_restart = at91sam9g45_restart; |
341 | at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1); | 336 | at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1); |
342 | 337 | ||
343 | /* Register GPIO subsystem */ | 338 | /* Register GPIO subsystem */ |
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c index 18bacec2b094..97676bdae998 100644 --- a/arch/arm/mach-at91/at91rm9200_devices.c +++ b/arch/arm/mach-at91/at91rm9200_devices.c | |||
@@ -83,7 +83,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {} | |||
83 | * USB Device (Gadget) | 83 | * USB Device (Gadget) |
84 | * -------------------------------------------------------------------- */ | 84 | * -------------------------------------------------------------------- */ |
85 | 85 | ||
86 | #ifdef CONFIG_USB_AT91 | 86 | #if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE) |
87 | static struct at91_udc_data udc_data; | 87 | static struct at91_udc_data udc_data; |
88 | 88 | ||
89 | static struct resource udc_resources[] = { | 89 | static struct resource udc_resources[] = { |
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index 5e46e4a96430..d4036ba43612 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c | |||
@@ -323,6 +323,7 @@ static void __init at91sam9260_map_io(void) | |||
323 | static void __init at91sam9260_ioremap_registers(void) | 323 | static void __init at91sam9260_ioremap_registers(void) |
324 | { | 324 | { |
325 | at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC); | 325 | at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC); |
326 | at91_ioremap_rstc(AT91SAM9260_BASE_RSTC); | ||
326 | at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT); | 327 | at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT); |
327 | at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC); | 328 | at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC); |
328 | } | 329 | } |
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c index 642ccb6d26b2..5a24f0b4554d 100644 --- a/arch/arm/mach-at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/at91sam9260_devices.c | |||
@@ -84,7 +84,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {} | |||
84 | * USB Device (Gadget) | 84 | * USB Device (Gadget) |
85 | * -------------------------------------------------------------------- */ | 85 | * -------------------------------------------------------------------- */ |
86 | 86 | ||
87 | #ifdef CONFIG_USB_AT91 | 87 | #if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE) |
88 | static struct at91_udc_data udc_data; | 88 | static struct at91_udc_data udc_data; |
89 | 89 | ||
90 | static struct resource udc_resources[] = { | 90 | static struct resource udc_resources[] = { |
@@ -1215,8 +1215,7 @@ void __init at91_add_device_serial(void) {} | |||
1215 | * CF/IDE | 1215 | * CF/IDE |
1216 | * -------------------------------------------------------------------- */ | 1216 | * -------------------------------------------------------------------- */ |
1217 | 1217 | ||
1218 | #if defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) || \ | 1218 | #if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \ |
1219 | defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \ | ||
1220 | defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) | 1219 | defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) |
1221 | 1220 | ||
1222 | static struct at91_cf_data cf0_data; | 1221 | static struct at91_cf_data cf0_data; |
@@ -1313,10 +1312,8 @@ void __init at91_add_device_cf(struct at91_cf_data *data) | |||
1313 | if (data->flags & AT91_CF_TRUE_IDE) | 1312 | if (data->flags & AT91_CF_TRUE_IDE) |
1314 | #if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) | 1313 | #if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) |
1315 | pdev->name = "pata_at91"; | 1314 | pdev->name = "pata_at91"; |
1316 | #elif defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) | ||
1317 | pdev->name = "at91_ide"; | ||
1318 | #else | 1315 | #else |
1319 | #warning "board requires AT91_CF_TRUE_IDE: enable either at91_ide or pata_at91" | 1316 | #warning "board requires AT91_CF_TRUE_IDE: enable pata_at91" |
1320 | #endif | 1317 | #endif |
1321 | else | 1318 | else |
1322 | pdev->name = "at91_cf"; | 1319 | pdev->name = "at91_cf"; |
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c index b85b9ea60170..023c2ff138df 100644 --- a/arch/arm/mach-at91/at91sam9261.c +++ b/arch/arm/mach-at91/at91sam9261.c | |||
@@ -281,6 +281,7 @@ static void __init at91sam9261_map_io(void) | |||
281 | static void __init at91sam9261_ioremap_registers(void) | 281 | static void __init at91sam9261_ioremap_registers(void) |
282 | { | 282 | { |
283 | at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC); | 283 | at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC); |
284 | at91_ioremap_rstc(AT91SAM9261_BASE_RSTC); | ||
284 | at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT); | 285 | at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT); |
285 | at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC); | 286 | at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC); |
286 | } | 287 | } |
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c index fc59cbdb0e3c..1e28bed8f425 100644 --- a/arch/arm/mach-at91/at91sam9261_devices.c +++ b/arch/arm/mach-at91/at91sam9261_devices.c | |||
@@ -87,7 +87,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {} | |||
87 | * USB Device (Gadget) | 87 | * USB Device (Gadget) |
88 | * -------------------------------------------------------------------- */ | 88 | * -------------------------------------------------------------------- */ |
89 | 89 | ||
90 | #ifdef CONFIG_USB_AT91 | 90 | #if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE) |
91 | static struct at91_udc_data udc_data; | 91 | static struct at91_udc_data udc_data; |
92 | 92 | ||
93 | static struct resource udc_resources[] = { | 93 | static struct resource udc_resources[] = { |
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index 79e3669b1117..75e876c258af 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c | |||
@@ -301,6 +301,7 @@ static void __init at91sam9263_map_io(void) | |||
301 | static void __init at91sam9263_ioremap_registers(void) | 301 | static void __init at91sam9263_ioremap_registers(void) |
302 | { | 302 | { |
303 | at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC); | 303 | at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC); |
304 | at91_ioremap_rstc(AT91SAM9263_BASE_RSTC); | ||
304 | at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT); | 305 | at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT); |
305 | at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0); | 306 | at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0); |
306 | at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1); | 307 | at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1); |
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index 7b46b2787022..366a7765635b 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c | |||
@@ -92,7 +92,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {} | |||
92 | * USB Device (Gadget) | 92 | * USB Device (Gadget) |
93 | * -------------------------------------------------------------------- */ | 93 | * -------------------------------------------------------------------- */ |
94 | 94 | ||
95 | #ifdef CONFIG_USB_AT91 | 95 | #if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE) |
96 | static struct at91_udc_data udc_data; | 96 | static struct at91_udc_data udc_data; |
97 | 97 | ||
98 | static struct resource udc_resources[] = { | 98 | static struct resource udc_resources[] = { |
@@ -355,8 +355,8 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {} | |||
355 | * Compact Flash (PCMCIA or IDE) | 355 | * Compact Flash (PCMCIA or IDE) |
356 | * -------------------------------------------------------------------- */ | 356 | * -------------------------------------------------------------------- */ |
357 | 357 | ||
358 | #if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) || \ | 358 | #if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \ |
359 | defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) | 359 | defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) |
360 | 360 | ||
361 | static struct at91_cf_data cf0_data; | 361 | static struct at91_cf_data cf0_data; |
362 | 362 | ||
@@ -450,7 +450,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data) | |||
450 | at91_set_A_periph(AT91_PIN_PD9, 0); /* CFCE2 */ | 450 | at91_set_A_periph(AT91_PIN_PD9, 0); /* CFCE2 */ |
451 | at91_set_A_periph(AT91_PIN_PD14, 0); /* CFNRW */ | 451 | at91_set_A_periph(AT91_PIN_PD14, 0); /* CFNRW */ |
452 | 452 | ||
453 | pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "at91_ide" : "at91_cf"; | 453 | pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "pata_at91" : "at91_cf"; |
454 | platform_device_register(pdev); | 454 | platform_device_register(pdev); |
455 | } | 455 | } |
456 | #else | 456 | #else |
diff --git a/arch/arm/mach-at91/at91sam9_alt_reset.S b/arch/arm/mach-at91/at91sam9_alt_reset.S index d3f931c5942e..518e42377171 100644 --- a/arch/arm/mach-at91/at91sam9_alt_reset.S +++ b/arch/arm/mach-at91/at91sam9_alt_reset.S | |||
@@ -23,7 +23,8 @@ | |||
23 | .globl at91sam9_alt_restart | 23 | .globl at91sam9_alt_restart |
24 | 24 | ||
25 | at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants | 25 | at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants |
26 | ldr r1, .at91_va_base_rstc_cr | 26 | ldr r1, =at91_rstc_base |
27 | ldr r1, [r1] | ||
27 | 28 | ||
28 | mov r2, #1 | 29 | mov r2, #1 |
29 | mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN | 30 | mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN |
@@ -33,11 +34,9 @@ at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants | |||
33 | 34 | ||
34 | str r2, [r0, #AT91_SDRAMC_TR] @ disable SDRAM access | 35 | str r2, [r0, #AT91_SDRAMC_TR] @ disable SDRAM access |
35 | str r3, [r0, #AT91_SDRAMC_LPR] @ power down SDRAM | 36 | str r3, [r0, #AT91_SDRAMC_LPR] @ power down SDRAM |
36 | str r4, [r1] @ reset processor | 37 | str r4, [r1, #AT91_RSTC_CR] @ reset processor |
37 | 38 | ||
38 | b . | 39 | b . |
39 | 40 | ||
40 | .at91_va_base_sdramc: | 41 | .at91_va_base_sdramc: |
41 | .word AT91_VA_BASE_SYS + AT91_SDRAMC0 | 42 | .word AT91_VA_BASE_SYS + AT91_SDRAMC0 |
42 | .at91_va_base_rstc_cr: | ||
43 | .word AT91_VA_BASE_SYS + AT91_RSTC_CR | ||
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index 7032dd32cdf0..1cb6a96b1c1e 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c | |||
@@ -18,7 +18,6 @@ | |||
18 | #include <asm/mach/map.h> | 18 | #include <asm/mach/map.h> |
19 | #include <mach/at91sam9g45.h> | 19 | #include <mach/at91sam9g45.h> |
20 | #include <mach/at91_pmc.h> | 20 | #include <mach/at91_pmc.h> |
21 | #include <mach/at91_rstc.h> | ||
22 | #include <mach/cpu.h> | 21 | #include <mach/cpu.h> |
23 | 22 | ||
24 | #include "soc.h" | 23 | #include "soc.h" |
@@ -318,11 +317,6 @@ static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = { | |||
318 | } | 317 | } |
319 | }; | 318 | }; |
320 | 319 | ||
321 | static void at91sam9g45_restart(char mode, const char *cmd) | ||
322 | { | ||
323 | at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); | ||
324 | } | ||
325 | |||
326 | /* -------------------------------------------------------------------- | 320 | /* -------------------------------------------------------------------- |
327 | * AT91SAM9G45 processor initialization | 321 | * AT91SAM9G45 processor initialization |
328 | * -------------------------------------------------------------------- */ | 322 | * -------------------------------------------------------------------- */ |
@@ -336,6 +330,7 @@ static void __init at91sam9g45_map_io(void) | |||
336 | static void __init at91sam9g45_ioremap_registers(void) | 330 | static void __init at91sam9g45_ioremap_registers(void) |
337 | { | 331 | { |
338 | at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC); | 332 | at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC); |
333 | at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC); | ||
339 | at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT); | 334 | at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT); |
340 | at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC); | 335 | at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC); |
341 | } | 336 | } |
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S new file mode 100644 index 000000000000..0468be10980b --- /dev/null +++ b/arch/arm/mach-at91/at91sam9g45_reset.S | |||
@@ -0,0 +1,40 @@ | |||
1 | /* | ||
2 | * reset AT91SAM9G45 as per errata | ||
3 | * | ||
4 | * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com> | ||
5 | * | ||
6 | * unless the SDRAM is cleanly shutdown before we hit the | ||
7 | * reset register it can be left driving the data bus and | ||
8 | * killing the chance of a subsequent boot from NAND | ||
9 | * | ||
10 | * GPLv2 Only | ||
11 | */ | ||
12 | |||
13 | #include <linux/linkage.h> | ||
14 | #include <mach/hardware.h> | ||
15 | #include <mach/at91sam9_ddrsdr.h> | ||
16 | #include <mach/at91_rstc.h> | ||
17 | |||
18 | .arm | ||
19 | |||
20 | .globl at91sam9g45_restart | ||
21 | |||
22 | at91sam9g45_restart: | ||
23 | ldr r0, .at91_va_base_sdramc0 @ preload constants | ||
24 | ldr r1, =at91_rstc_base | ||
25 | ldr r1, [r1] | ||
26 | |||
27 | mov r2, #1 | ||
28 | mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN | ||
29 | ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST | ||
30 | |||
31 | .balign 32 @ align to cache line | ||
32 | |||
33 | str r2, [r0, #AT91_DDRSDRC_RTR] @ disable DDR0 access | ||
34 | str r3, [r0, #AT91_DDRSDRC_LPR] @ power down DDR0 | ||
35 | str r4, [r1, #AT91_RSTC_CR] @ reset processor | ||
36 | |||
37 | b . | ||
38 | |||
39 | .at91_va_base_sdramc0: | ||
40 | .word AT91_VA_BASE_SYS + AT91_DDRSDRC0 | ||
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c index d6bcb1da11df..d2c91a841cb8 100644 --- a/arch/arm/mach-at91/at91sam9rl.c +++ b/arch/arm/mach-at91/at91sam9rl.c | |||
@@ -286,6 +286,7 @@ static void __init at91sam9rl_map_io(void) | |||
286 | static void __init at91sam9rl_ioremap_registers(void) | 286 | static void __init at91sam9rl_ioremap_registers(void) |
287 | { | 287 | { |
288 | at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC); | 288 | at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC); |
289 | at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC); | ||
289 | at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT); | 290 | at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT); |
290 | at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC); | 291 | at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC); |
291 | } | 292 | } |
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index 4866b8180d66..594133451c0c 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h | |||
@@ -58,7 +58,9 @@ extern void at91_irq_suspend(void); | |||
58 | extern void at91_irq_resume(void); | 58 | extern void at91_irq_resume(void); |
59 | 59 | ||
60 | /* reset */ | 60 | /* reset */ |
61 | extern void at91_ioremap_rstc(u32 base_addr); | ||
61 | extern void at91sam9_alt_restart(char, const char *); | 62 | extern void at91sam9_alt_restart(char, const char *); |
63 | extern void at91sam9g45_restart(char, const char *); | ||
62 | 64 | ||
63 | /* shutdown */ | 65 | /* shutdown */ |
64 | extern void at91_ioremap_shdwc(u32 base_addr); | 66 | extern void at91_ioremap_shdwc(u32 base_addr); |
diff --git a/arch/arm/mach-at91/include/mach/at91_rstc.h b/arch/arm/mach-at91/include/mach/at91_rstc.h index cbd2bf052c1f..875fa336800b 100644 --- a/arch/arm/mach-at91/include/mach/at91_rstc.h +++ b/arch/arm/mach-at91/include/mach/at91_rstc.h | |||
@@ -16,13 +16,25 @@ | |||
16 | #ifndef AT91_RSTC_H | 16 | #ifndef AT91_RSTC_H |
17 | #define AT91_RSTC_H | 17 | #define AT91_RSTC_H |
18 | 18 | ||
19 | #define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ | 19 | #ifndef __ASSEMBLY__ |
20 | extern void __iomem *at91_rstc_base; | ||
21 | |||
22 | #define at91_rstc_read(field) \ | ||
23 | __raw_readl(at91_rstc_base + field) | ||
24 | |||
25 | #define at91_rstc_write(field, value) \ | ||
26 | __raw_writel(value, at91_rstc_base + field); | ||
27 | #else | ||
28 | .extern at91_rstc_base | ||
29 | #endif | ||
30 | |||
31 | #define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */ | ||
20 | #define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ | 32 | #define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ |
21 | #define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ | 33 | #define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ |
22 | #define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ | 34 | #define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ |
23 | #define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */ | 35 | #define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */ |
24 | 36 | ||
25 | #define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ | 37 | #define AT91_RSTC_SR 0x04 /* Reset Controller Status Register */ |
26 | #define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ | 38 | #define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ |
27 | #define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ | 39 | #define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ |
28 | #define AT91_RSTC_RSTTYP_GENERAL (0 << 8) | 40 | #define AT91_RSTC_RSTTYP_GENERAL (0 << 8) |
@@ -33,7 +45,7 @@ | |||
33 | #define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ | 45 | #define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ |
34 | #define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ | 46 | #define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ |
35 | 47 | ||
36 | #define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */ | 48 | #define AT91_RSTC_MR 0x08 /* Reset Controller Mode Register */ |
37 | #define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ | 49 | #define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ |
38 | #define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ | 50 | #define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ |
39 | #define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ | 51 | #define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ |
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h index 4c0e2f6011d7..61d952902f2b 100644 --- a/arch/arm/mach-at91/include/mach/at91cap9.h +++ b/arch/arm/mach-at91/include/mach/at91cap9.h | |||
@@ -83,7 +83,6 @@ | |||
83 | #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) | 83 | #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) |
84 | #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) | 84 | #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) |
85 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | 85 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
86 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
87 | #define AT91_GPBR (cpu_is_at91cap9_revB() ? \ | 86 | #define AT91_GPBR (cpu_is_at91cap9_revB() ? \ |
88 | (0xfffffd50 - AT91_BASE_SYS) : \ | 87 | (0xfffffd50 - AT91_BASE_SYS) : \ |
89 | (0xfffffd60 - AT91_BASE_SYS)) | 88 | (0xfffffd60 - AT91_BASE_SYS)) |
@@ -96,6 +95,7 @@ | |||
96 | #define AT91CAP9_BASE_PIOB 0xfffff400 | 95 | #define AT91CAP9_BASE_PIOB 0xfffff400 |
97 | #define AT91CAP9_BASE_PIOC 0xfffff600 | 96 | #define AT91CAP9_BASE_PIOC 0xfffff600 |
98 | #define AT91CAP9_BASE_PIOD 0xfffff800 | 97 | #define AT91CAP9_BASE_PIOD 0xfffff800 |
98 | #define AT91CAP9_BASE_RSTC 0xfffffd00 | ||
99 | #define AT91CAP9_BASE_SHDWC 0xfffffd10 | 99 | #define AT91CAP9_BASE_SHDWC 0xfffffd10 |
100 | #define AT91CAP9_BASE_RTT 0xfffffd20 | 100 | #define AT91CAP9_BASE_RTT 0xfffffd20 |
101 | #define AT91CAP9_BASE_PIT 0xfffffd30 | 101 | #define AT91CAP9_BASE_PIT 0xfffffd30 |
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h deleted file mode 100644 index 976f4a6c3353..000000000000 --- a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h +++ /dev/null | |||
@@ -1,108 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h | ||
3 | * | ||
4 | * (C) 2008 Andrew Victor | ||
5 | * | ||
6 | * DDR/SDR Controller (DDRSDRC) - System peripherals registers. | ||
7 | * Based on AT91CAP9 datasheet revision B. | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License, or | ||
12 | * (at your option) any later version. | ||
13 | */ | ||
14 | |||
15 | #ifndef AT91CAP9_DDRSDR_H | ||
16 | #define AT91CAP9_DDRSDR_H | ||
17 | |||
18 | #define AT91_DDRSDRC_MR 0x00 /* Mode Register */ | ||
19 | #define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */ | ||
20 | #define AT91_DDRSDRC_MODE_NORMAL 0 | ||
21 | #define AT91_DDRSDRC_MODE_NOP 1 | ||
22 | #define AT91_DDRSDRC_MODE_PRECHARGE 2 | ||
23 | #define AT91_DDRSDRC_MODE_LMR 3 | ||
24 | #define AT91_DDRSDRC_MODE_REFRESH 4 | ||
25 | #define AT91_DDRSDRC_MODE_EXT_LMR 5 | ||
26 | #define AT91_DDRSDRC_MODE_DEEP 6 | ||
27 | |||
28 | #define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */ | ||
29 | #define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */ | ||
30 | |||
31 | #define AT91_DDRSDRC_CR 0x08 /* Configuration Register */ | ||
32 | #define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */ | ||
33 | #define AT91_DDRSDRC_NC_SDR8 (0 << 0) | ||
34 | #define AT91_DDRSDRC_NC_SDR9 (1 << 0) | ||
35 | #define AT91_DDRSDRC_NC_SDR10 (2 << 0) | ||
36 | #define AT91_DDRSDRC_NC_SDR11 (3 << 0) | ||
37 | #define AT91_DDRSDRC_NC_DDR9 (0 << 0) | ||
38 | #define AT91_DDRSDRC_NC_DDR10 (1 << 0) | ||
39 | #define AT91_DDRSDRC_NC_DDR11 (2 << 0) | ||
40 | #define AT91_DDRSDRC_NC_DDR12 (3 << 0) | ||
41 | #define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */ | ||
42 | #define AT91_DDRSDRC_NR_11 (0 << 2) | ||
43 | #define AT91_DDRSDRC_NR_12 (1 << 2) | ||
44 | #define AT91_DDRSDRC_NR_13 (2 << 2) | ||
45 | #define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */ | ||
46 | #define AT91_DDRSDRC_CAS_2 (2 << 4) | ||
47 | #define AT91_DDRSDRC_CAS_3 (3 << 4) | ||
48 | #define AT91_DDRSDRC_CAS_25 (6 << 4) | ||
49 | #define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */ | ||
50 | #define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */ | ||
51 | |||
52 | #define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */ | ||
53 | #define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ | ||
54 | #define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */ | ||
55 | #define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */ | ||
56 | #define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */ | ||
57 | #define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ | ||
58 | #define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ | ||
59 | #define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */ | ||
60 | #define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ | ||
61 | |||
62 | #define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */ | ||
63 | #define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */ | ||
64 | #define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */ | ||
65 | #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */ | ||
66 | #define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */ | ||
67 | |||
68 | #define AT91_DDRSDRC_LPR 0x18 /* Low Power Register */ | ||
69 | #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ | ||
70 | #define AT91_DDRSDRC_LPCB_DISABLE 0 | ||
71 | #define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 | ||
72 | #define AT91_DDRSDRC_LPCB_POWER_DOWN 2 | ||
73 | #define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3 | ||
74 | #define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */ | ||
75 | #define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */ | ||
76 | #define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ | ||
77 | #define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */ | ||
78 | #define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ | ||
79 | #define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12) | ||
80 | #define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12) | ||
81 | #define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12) | ||
82 | |||
83 | #define AT91_DDRSDRC_MDR 0x1C /* Memory Device Register */ | ||
84 | #define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ | ||
85 | #define AT91_DDRSDRC_MD_SDR 0 | ||
86 | #define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 | ||
87 | #define AT91_DDRSDRC_MD_DDR 2 | ||
88 | #define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 | ||
89 | |||
90 | #define AT91_DDRSDRC_DLLR 0x20 /* DLL Information Register */ | ||
91 | #define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ | ||
92 | #define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ | ||
93 | #define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ | ||
94 | #define AT91_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */ | ||
95 | #define AT91_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */ | ||
96 | #define AT91_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */ | ||
97 | #define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ | ||
98 | #define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */ | ||
99 | #define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */ | ||
100 | |||
101 | /* Register access macros */ | ||
102 | #define at91_ramc_read(num, reg) \ | ||
103 | at91_sys_read(AT91_DDRSDRC##num + reg) | ||
104 | #define at91_ramc_write(num, reg, value) \ | ||
105 | at91_sys_write(AT91_DDRSDRC##num + reg, value) | ||
106 | |||
107 | |||
108 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h index f937c476bb67..fa5ca278adeb 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9260.h +++ b/arch/arm/mach-at91/include/mach/at91sam9260.h | |||
@@ -83,7 +83,6 @@ | |||
83 | #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) | 83 | #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) |
84 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) | 84 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) |
85 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | 85 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
86 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
87 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) | 86 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) |
88 | 87 | ||
89 | #define AT91SAM9260_BASE_ECC 0xffffe800 | 88 | #define AT91SAM9260_BASE_ECC 0xffffe800 |
@@ -92,6 +91,7 @@ | |||
92 | #define AT91SAM9260_BASE_PIOA 0xfffff400 | 91 | #define AT91SAM9260_BASE_PIOA 0xfffff400 |
93 | #define AT91SAM9260_BASE_PIOB 0xfffff600 | 92 | #define AT91SAM9260_BASE_PIOB 0xfffff600 |
94 | #define AT91SAM9260_BASE_PIOC 0xfffff800 | 93 | #define AT91SAM9260_BASE_PIOC 0xfffff800 |
94 | #define AT91SAM9260_BASE_RSTC 0xfffffd00 | ||
95 | #define AT91SAM9260_BASE_SHDWC 0xfffffd10 | 95 | #define AT91SAM9260_BASE_SHDWC 0xfffffd10 |
96 | #define AT91SAM9260_BASE_RTT 0xfffffd20 | 96 | #define AT91SAM9260_BASE_RTT 0xfffffd20 |
97 | #define AT91SAM9260_BASE_PIT 0xfffffd30 | 97 | #define AT91SAM9260_BASE_PIT 0xfffffd30 |
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h index 175604e261be..7cde2d36570e 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9261.h +++ b/arch/arm/mach-at91/include/mach/at91sam9261.h | |||
@@ -68,7 +68,6 @@ | |||
68 | #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) | 68 | #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) |
69 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) | 69 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) |
70 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | 70 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
71 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
72 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) | 71 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) |
73 | 72 | ||
74 | #define AT91SAM9261_BASE_SMC 0xffffec00 | 73 | #define AT91SAM9261_BASE_SMC 0xffffec00 |
@@ -76,6 +75,7 @@ | |||
76 | #define AT91SAM9261_BASE_PIOA 0xfffff400 | 75 | #define AT91SAM9261_BASE_PIOA 0xfffff400 |
77 | #define AT91SAM9261_BASE_PIOB 0xfffff600 | 76 | #define AT91SAM9261_BASE_PIOB 0xfffff600 |
78 | #define AT91SAM9261_BASE_PIOC 0xfffff800 | 77 | #define AT91SAM9261_BASE_PIOC 0xfffff800 |
78 | #define AT91SAM9261_BASE_RSTC 0xfffffd00 | ||
79 | #define AT91SAM9261_BASE_SHDWC 0xfffffd10 | 79 | #define AT91SAM9261_BASE_SHDWC 0xfffffd10 |
80 | #define AT91SAM9261_BASE_RTT 0xfffffd20 | 80 | #define AT91SAM9261_BASE_RTT 0xfffffd20 |
81 | #define AT91SAM9261_BASE_PIT 0xfffffd30 | 81 | #define AT91SAM9261_BASE_PIT 0xfffffd30 |
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h index 80c915002d83..5949abda962b 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9263.h +++ b/arch/arm/mach-at91/include/mach/at91sam9263.h | |||
@@ -78,7 +78,6 @@ | |||
78 | #define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) | 78 | #define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) |
79 | #define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) | 79 | #define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) |
80 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | 80 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
81 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
82 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) | 81 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) |
83 | 82 | ||
84 | #define AT91SAM9263_BASE_ECC0 0xffffe000 | 83 | #define AT91SAM9263_BASE_ECC0 0xffffe000 |
@@ -91,6 +90,7 @@ | |||
91 | #define AT91SAM9263_BASE_PIOC 0xfffff600 | 90 | #define AT91SAM9263_BASE_PIOC 0xfffff600 |
92 | #define AT91SAM9263_BASE_PIOD 0xfffff800 | 91 | #define AT91SAM9263_BASE_PIOD 0xfffff800 |
93 | #define AT91SAM9263_BASE_PIOE 0xfffffa00 | 92 | #define AT91SAM9263_BASE_PIOE 0xfffffa00 |
93 | #define AT91SAM9263_BASE_RSTC 0xfffffd00 | ||
94 | #define AT91SAM9263_BASE_SHDWC 0xfffffd10 | 94 | #define AT91SAM9263_BASE_SHDWC 0xfffffd10 |
95 | #define AT91SAM9263_BASE_RTT0 0xfffffd20 | 95 | #define AT91SAM9263_BASE_RTT0 0xfffffd20 |
96 | #define AT91SAM9263_BASE_PIT 0xfffffd30 | 96 | #define AT91SAM9263_BASE_PIT 0xfffffd30 |
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h index d27b15ba8ebf..e2f8da8ce5bc 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h +++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h | |||
@@ -46,10 +46,10 @@ | |||
46 | #define AT91_DDRSDRC_CAS_25 (6 << 4) | 46 | #define AT91_DDRSDRC_CAS_25 (6 << 4) |
47 | #define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */ | 47 | #define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */ |
48 | #define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */ | 48 | #define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */ |
49 | #define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL */ | 49 | #define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL [SAM9 Only] */ |
50 | #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver */ | 50 | #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */ |
51 | #define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared */ | 51 | #define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared [SAM9 Only] */ |
52 | #define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y */ | 52 | #define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */ |
53 | 53 | ||
54 | #define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */ | 54 | #define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */ |
55 | #define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ | 55 | #define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ |
@@ -59,7 +59,8 @@ | |||
59 | #define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ | 59 | #define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ |
60 | #define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ | 60 | #define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ |
61 | #define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */ | 61 | #define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */ |
62 | #define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay */ | 62 | #define AT91CAP9_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */ |
63 | #define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */ | ||
63 | #define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ | 64 | #define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ |
64 | 65 | ||
65 | #define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */ | 66 | #define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */ |
@@ -68,13 +69,14 @@ | |||
68 | #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */ | 69 | #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */ |
69 | #define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */ | 70 | #define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */ |
70 | 71 | ||
71 | #define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register */ | 72 | #define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register [SAM9 Only] */ |
72 | #define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */ | 73 | #define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */ |
73 | #define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */ | 74 | #define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */ |
74 | #define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */ | 75 | #define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */ |
75 | #define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */ | 76 | #define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */ |
76 | 77 | ||
77 | #define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */ | 78 | #define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */ |
79 | #define AT91CAP9_DDRSDRC_LPR 0x18 /* Low Power Register */ | ||
78 | #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ | 80 | #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ |
79 | #define AT91_DDRSDRC_LPCB_DISABLE 0 | 81 | #define AT91_DDRSDRC_LPCB_DISABLE 0 |
80 | #define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 | 82 | #define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 |
@@ -92,32 +94,40 @@ | |||
92 | #define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */ | 94 | #define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */ |
93 | 95 | ||
94 | #define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */ | 96 | #define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */ |
97 | #define AT91CAP9_DDRSDRC_MDR 0x1C /* Memory Device Register */ | ||
95 | #define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ | 98 | #define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ |
96 | #define AT91_DDRSDRC_MD_SDR 0 | 99 | #define AT91_DDRSDRC_MD_SDR 0 |
97 | #define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 | 100 | #define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 |
101 | #define AT91CAP9_DDRSDRC_MD_DDR 2 | ||
98 | #define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 | 102 | #define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 |
99 | #define AT91_DDRSDRC_MD_DDR2 6 | 103 | #define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */ |
100 | #define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */ | 104 | #define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */ |
101 | #define AT91_DDRSDRC_DBW_32BITS (0 << 4) | 105 | #define AT91_DDRSDRC_DBW_32BITS (0 << 4) |
102 | #define AT91_DDRSDRC_DBW_16BITS (1 << 4) | 106 | #define AT91_DDRSDRC_DBW_16BITS (1 << 4) |
103 | 107 | ||
104 | #define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */ | 108 | #define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */ |
109 | #define AT91CAP9_DDRSDRC_DLL 0x20 /* DLL Information Register */ | ||
105 | #define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ | 110 | #define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ |
106 | #define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ | 111 | #define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ |
107 | #define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ | 112 | #define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ |
113 | #define AT91CAP9_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */ | ||
114 | #define AT91CAP9_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */ | ||
115 | #define AT91CAP9_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */ | ||
108 | #define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ | 116 | #define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ |
117 | #define AT91CAP9_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */ | ||
118 | #define AT91CAP9_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */ | ||
109 | 119 | ||
110 | #define AT91_DDRSDRC_HS 0x2C /* High Speed Register */ | 120 | #define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */ |
111 | #define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */ | 121 | #define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */ |
112 | 122 | ||
113 | #define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */ | 123 | #define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */ |
114 | 124 | ||
115 | #define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register */ | 125 | #define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */ |
116 | #define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */ | 126 | #define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */ |
117 | #define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */ | 127 | #define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */ |
118 | #define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */ | 128 | #define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */ |
119 | 129 | ||
120 | #define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register */ | 130 | #define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register [SAM9 Only] */ |
121 | #define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */ | 131 | #define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */ |
122 | #define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */ | 132 | #define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */ |
123 | 133 | ||
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h index eb18a70fa647..175e1fdd9fe8 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h +++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h | |||
@@ -18,6 +18,35 @@ | |||
18 | 18 | ||
19 | #include <mach/cpu.h> | 19 | #include <mach/cpu.h> |
20 | 20 | ||
21 | #ifndef __ASSEMBLY__ | ||
22 | struct sam9_smc_config { | ||
23 | /* Setup register */ | ||
24 | u8 ncs_read_setup; | ||
25 | u8 nrd_setup; | ||
26 | u8 ncs_write_setup; | ||
27 | u8 nwe_setup; | ||
28 | |||
29 | /* Pulse register */ | ||
30 | u8 ncs_read_pulse; | ||
31 | u8 nrd_pulse; | ||
32 | u8 ncs_write_pulse; | ||
33 | u8 nwe_pulse; | ||
34 | |||
35 | /* Cycle register */ | ||
36 | u16 read_cycle; | ||
37 | u16 write_cycle; | ||
38 | |||
39 | /* Mode register */ | ||
40 | u32 mode; | ||
41 | u8 tdf_cycles:4; | ||
42 | }; | ||
43 | |||
44 | extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config); | ||
45 | extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config); | ||
46 | extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config); | ||
47 | extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config); | ||
48 | #endif | ||
49 | |||
21 | #define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */ | 50 | #define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */ |
22 | #define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ | 51 | #define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ |
23 | #define AT91_SMC_NWESETUP_(x) ((x) << 0) | 52 | #define AT91_SMC_NWESETUP_(x) ((x) << 0) |
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h index f0c23c960dec..dd9c95ea0862 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9g45.h +++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h | |||
@@ -90,7 +90,6 @@ | |||
90 | #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) | 90 | #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) |
91 | #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) | 91 | #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) |
92 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | 92 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
93 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
94 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) | 93 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) |
95 | 94 | ||
96 | #define AT91SAM9G45_BASE_ECC 0xffffe200 | 95 | #define AT91SAM9G45_BASE_ECC 0xffffe200 |
@@ -102,6 +101,7 @@ | |||
102 | #define AT91SAM9G45_BASE_PIOC 0xfffff600 | 101 | #define AT91SAM9G45_BASE_PIOC 0xfffff600 |
103 | #define AT91SAM9G45_BASE_PIOD 0xfffff800 | 102 | #define AT91SAM9G45_BASE_PIOD 0xfffff800 |
104 | #define AT91SAM9G45_BASE_PIOE 0xfffffa00 | 103 | #define AT91SAM9G45_BASE_PIOE 0xfffffa00 |
104 | #define AT91SAM9G45_BASE_RSTC 0xfffffd00 | ||
105 | #define AT91SAM9G45_BASE_SHDWC 0xfffffd10 | 105 | #define AT91SAM9G45_BASE_SHDWC 0xfffffd10 |
106 | #define AT91SAM9G45_BASE_RTT 0xfffffd20 | 106 | #define AT91SAM9G45_BASE_RTT 0xfffffd20 |
107 | #define AT91SAM9G45_BASE_PIT 0xfffffd30 | 107 | #define AT91SAM9G45_BASE_PIT 0xfffffd30 |
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h index 2bb359e60b97..d7bead7118da 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9rl.h +++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h | |||
@@ -72,7 +72,6 @@ | |||
72 | #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) | 72 | #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) |
73 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) | 73 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) |
74 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | 74 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
75 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
76 | #define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) | 75 | #define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) |
77 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) | 76 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) |
78 | 77 | ||
@@ -84,6 +83,7 @@ | |||
84 | #define AT91SAM9RL_BASE_PIOB 0xfffff600 | 83 | #define AT91SAM9RL_BASE_PIOB 0xfffff600 |
85 | #define AT91SAM9RL_BASE_PIOC 0xfffff800 | 84 | #define AT91SAM9RL_BASE_PIOC 0xfffff800 |
86 | #define AT91SAM9RL_BASE_PIOD 0xfffffa00 | 85 | #define AT91SAM9RL_BASE_PIOD 0xfffffa00 |
86 | #define AT91SAM9RL_BASE_RSTC 0xfffffd00 | ||
87 | #define AT91SAM9RL_BASE_SHDWC 0xfffffd10 | 87 | #define AT91SAM9RL_BASE_SHDWC 0xfffffd10 |
88 | #define AT91SAM9RL_BASE_RTT 0xfffffd20 | 88 | #define AT91SAM9RL_BASE_RTT 0xfffffd20 |
89 | #define AT91SAM9RL_BASE_PIT 0xfffffd30 | 89 | #define AT91SAM9RL_BASE_PIT 0xfffffd30 |
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h index d0b377b21bd7..3b33f07b1e11 100644 --- a/arch/arm/mach-at91/include/mach/board.h +++ b/arch/arm/mach-at91/include/mach/board.h | |||
@@ -88,7 +88,7 @@ extern void __init at91_add_device_eth(struct macb_platform_data *data); | |||
88 | struct at91_usbh_data { | 88 | struct at91_usbh_data { |
89 | u8 ports; /* number of ports on root hub */ | 89 | u8 ports; /* number of ports on root hub */ |
90 | int vbus_pin[2]; /* port power-control pin */ | 90 | int vbus_pin[2]; /* port power-control pin */ |
91 | u8 vbus_pin_inverted; | 91 | u8 vbus_pin_active_low[2]; |
92 | u8 overcurrent_supported; | 92 | u8 overcurrent_supported; |
93 | int overcurrent_pin[2]; | 93 | int overcurrent_pin[2]; |
94 | u8 overcurrent_status[2]; | 94 | u8 overcurrent_status[2]; |
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 62ad95556c36..1606379ac284 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c | |||
@@ -34,7 +34,6 @@ | |||
34 | /* | 34 | /* |
35 | * Show the reason for the previous system reset. | 35 | * Show the reason for the previous system reset. |
36 | */ | 36 | */ |
37 | #if defined(AT91_RSTC) | ||
38 | 37 | ||
39 | #include <mach/at91_rstc.h> | 38 | #include <mach/at91_rstc.h> |
40 | #include <mach/at91_shdwc.h> | 39 | #include <mach/at91_shdwc.h> |
@@ -58,10 +57,10 @@ static void __init show_reset_status(void) | |||
58 | char *reason, *r2 = reset; | 57 | char *reason, *r2 = reset; |
59 | u32 reset_type, wake_type; | 58 | u32 reset_type, wake_type; |
60 | 59 | ||
61 | if (!at91_shdwc_base) | 60 | if (!at91_shdwc_base || !at91_rstc_base) |
62 | return; | 61 | return; |
63 | 62 | ||
64 | reset_type = at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP; | 63 | reset_type = at91_rstc_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP; |
65 | wake_type = at91_shdwc_read(AT91_SHDW_SR); | 64 | wake_type = at91_shdwc_read(AT91_SHDW_SR); |
66 | 65 | ||
67 | switch (reset_type) { | 66 | switch (reset_type) { |
@@ -102,10 +101,6 @@ static void __init show_reset_status(void) | |||
102 | } | 101 | } |
103 | pr_info("AT91: Starting after %s %s\n", reason, r2); | 102 | pr_info("AT91: Starting after %s %s\n", reason, r2); |
104 | } | 103 | } |
105 | #else | ||
106 | static void __init show_reset_status(void) {} | ||
107 | #endif | ||
108 | |||
109 | 104 | ||
110 | static int at91_pm_valid_state(suspend_state_t state) | 105 | static int at91_pm_valid_state(suspend_state_t state) |
111 | { | 106 | { |
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index ce9a20699111..7eb40d24242f 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h | |||
@@ -25,21 +25,21 @@ static inline u32 sdram_selfrefresh_enable(void) | |||
25 | : : "r" (0)) | 25 | : : "r" (0)) |
26 | 26 | ||
27 | #elif defined(CONFIG_ARCH_AT91CAP9) | 27 | #elif defined(CONFIG_ARCH_AT91CAP9) |
28 | #include <mach/at91cap9_ddrsdr.h> | 28 | #include <mach/at91sam9_ddrsdr.h> |
29 | 29 | ||
30 | 30 | ||
31 | static inline u32 sdram_selfrefresh_enable(void) | 31 | static inline u32 sdram_selfrefresh_enable(void) |
32 | { | 32 | { |
33 | u32 saved_lpr, lpr; | 33 | u32 saved_lpr, lpr; |
34 | 34 | ||
35 | saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR); | 35 | saved_lpr = at91_ramc_read(0, AT91CAP9_DDRSDRC_LPR); |
36 | 36 | ||
37 | lpr = saved_lpr & ~AT91_DDRSDRC_LPCB; | 37 | lpr = saved_lpr & ~AT91_DDRSDRC_LPCB; |
38 | at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH); | 38 | at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH); |
39 | return saved_lpr; | 39 | return saved_lpr; |
40 | } | 40 | } |
41 | 41 | ||
42 | #define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr) | 42 | #define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, saved_lpr) |
43 | #define wait_for_interrupt_enable() cpu_do_idle() | 43 | #define wait_for_interrupt_enable() cpu_do_idle() |
44 | 44 | ||
45 | #elif defined(CONFIG_ARCH_AT91SAM9G45) | 45 | #elif defined(CONFIG_ARCH_AT91SAM9G45) |
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S index f7922a436172..92dfb8461392 100644 --- a/arch/arm/mach-at91/pm_slowclock.S +++ b/arch/arm/mach-at91/pm_slowclock.S | |||
@@ -18,9 +18,8 @@ | |||
18 | 18 | ||
19 | #if defined(CONFIG_ARCH_AT91RM9200) | 19 | #if defined(CONFIG_ARCH_AT91RM9200) |
20 | #include <mach/at91rm9200_mc.h> | 20 | #include <mach/at91rm9200_mc.h> |
21 | #elif defined(CONFIG_ARCH_AT91CAP9) | 21 | #elif defined(CONFIG_ARCH_AT91CAP9) \ |
22 | #include <mach/at91cap9_ddrsdr.h> | 22 | || defined(CONFIG_ARCH_AT91SAM9G45) |
23 | #elif defined(CONFIG_ARCH_AT91SAM9G45) | ||
24 | #include <mach/at91sam9_ddrsdr.h> | 23 | #include <mach/at91sam9_ddrsdr.h> |
25 | #else | 24 | #else |
26 | #include <mach/at91sam9_sdramc.h> | 25 | #include <mach/at91sam9_sdramc.h> |
diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c index 8294783b679d..99a0a1d2b7dc 100644 --- a/arch/arm/mach-at91/sam9_smc.c +++ b/arch/arm/mach-at91/sam9_smc.c | |||
@@ -2,6 +2,7 @@ | |||
2 | * linux/arch/arm/mach-at91/sam9_smc.c | 2 | * linux/arch/arm/mach-at91/sam9_smc.c |
3 | * | 3 | * |
4 | * Copyright (C) 2008 Andrew Victor | 4 | * Copyright (C) 2008 Andrew Victor |
5 | * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | ||
5 | * | 6 | * |
6 | * This program is free software; you can redistribute it and/or modify | 7 | * This program is free software; you can redistribute it and/or modify |
7 | * it under the terms of the GNU General Public License version 2 as | 8 | * it under the terms of the GNU General Public License version 2 as |
@@ -22,7 +23,22 @@ | |||
22 | 23 | ||
23 | static void __iomem *smc_base_addr[2]; | 24 | static void __iomem *smc_base_addr[2]; |
24 | 25 | ||
25 | static void __init sam9_smc_cs_configure(void __iomem *base, struct sam9_smc_config* config) | 26 | static void sam9_smc_cs_write_mode(void __iomem *base, |
27 | struct sam9_smc_config *config) | ||
28 | { | ||
29 | __raw_writel(config->mode | ||
30 | | AT91_SMC_TDF_(config->tdf_cycles), | ||
31 | base + AT91_SMC_MODE); | ||
32 | } | ||
33 | |||
34 | void sam9_smc_write_mode(int id, int cs, | ||
35 | struct sam9_smc_config *config) | ||
36 | { | ||
37 | sam9_smc_cs_write_mode(AT91_SMC_CS(id, cs), config); | ||
38 | } | ||
39 | |||
40 | static void sam9_smc_cs_configure(void __iomem *base, | ||
41 | struct sam9_smc_config *config) | ||
26 | { | 42 | { |
27 | 43 | ||
28 | /* Setup register */ | 44 | /* Setup register */ |
@@ -45,16 +61,66 @@ static void __init sam9_smc_cs_configure(void __iomem *base, struct sam9_smc_con | |||
45 | base + AT91_SMC_CYCLE); | 61 | base + AT91_SMC_CYCLE); |
46 | 62 | ||
47 | /* Mode register */ | 63 | /* Mode register */ |
48 | __raw_writel(config->mode | 64 | sam9_smc_cs_write_mode(base, config); |
49 | | AT91_SMC_TDF_(config->tdf_cycles), | ||
50 | base + AT91_SMC_MODE); | ||
51 | } | 65 | } |
52 | 66 | ||
53 | void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config) | 67 | void sam9_smc_configure(int id, int cs, |
68 | struct sam9_smc_config *config) | ||
54 | { | 69 | { |
55 | sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config); | 70 | sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config); |
56 | } | 71 | } |
57 | 72 | ||
73 | static void sam9_smc_cs_read_mode(void __iomem *base, | ||
74 | struct sam9_smc_config *config) | ||
75 | { | ||
76 | u32 val = __raw_readl(base + AT91_SMC_MODE); | ||
77 | |||
78 | config->mode = (val & ~AT91_SMC_NWECYCLE); | ||
79 | config->tdf_cycles = (val & AT91_SMC_NWECYCLE) >> 16 ; | ||
80 | } | ||
81 | |||
82 | void sam9_smc_read_mode(int id, int cs, | ||
83 | struct sam9_smc_config *config) | ||
84 | { | ||
85 | sam9_smc_cs_read_mode(AT91_SMC_CS(id, cs), config); | ||
86 | } | ||
87 | |||
88 | static void sam9_smc_cs_read(void __iomem *base, | ||
89 | struct sam9_smc_config *config) | ||
90 | { | ||
91 | u32 val; | ||
92 | |||
93 | /* Setup register */ | ||
94 | val = __raw_readl(base + AT91_SMC_SETUP); | ||
95 | |||
96 | config->nwe_setup = val & AT91_SMC_NWESETUP; | ||
97 | config->ncs_write_setup = (val & AT91_SMC_NCS_WRSETUP) >> 8; | ||
98 | config->nrd_setup = (val & AT91_SMC_NRDSETUP) >> 16; | ||
99 | config->ncs_read_setup = (val & AT91_SMC_NCS_RDSETUP) >> 24; | ||
100 | |||
101 | /* Pulse register */ | ||
102 | val = __raw_readl(base + AT91_SMC_PULSE); | ||
103 | |||
104 | config->nwe_setup = val & AT91_SMC_NWEPULSE; | ||
105 | config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8; | ||
106 | config->nrd_pulse = (val & AT91_SMC_NRDPULSE) >> 16; | ||
107 | config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24; | ||
108 | |||
109 | /* Cycle register */ | ||
110 | val = __raw_readl(base + AT91_SMC_CYCLE); | ||
111 | |||
112 | config->write_cycle = val & AT91_SMC_NWECYCLE; | ||
113 | config->read_cycle = (val & AT91_SMC_NRDCYCLE) >> 16; | ||
114 | |||
115 | /* Mode register */ | ||
116 | sam9_smc_cs_read_mode(base, config); | ||
117 | } | ||
118 | |||
119 | void sam9_smc_read(int id, int cs, struct sam9_smc_config *config) | ||
120 | { | ||
121 | sam9_smc_cs_read(AT91_SMC_CS(id, cs), config); | ||
122 | } | ||
123 | |||
58 | void __init at91sam9_ioremap_smc(int id, u32 addr) | 124 | void __init at91sam9_ioremap_smc(int id, u32 addr) |
59 | { | 125 | { |
60 | if (id > 1) { | 126 | if (id > 1) { |
diff --git a/arch/arm/mach-at91/sam9_smc.h b/arch/arm/mach-at91/sam9_smc.h index 039c5ce17aec..3e52dcd4a59f 100644 --- a/arch/arm/mach-at91/sam9_smc.h +++ b/arch/arm/mach-at91/sam9_smc.h | |||
@@ -8,27 +8,4 @@ | |||
8 | * published by the Free Software Foundation. | 8 | * published by the Free Software Foundation. |
9 | */ | 9 | */ |
10 | 10 | ||
11 | struct sam9_smc_config { | ||
12 | /* Setup register */ | ||
13 | u8 ncs_read_setup; | ||
14 | u8 nrd_setup; | ||
15 | u8 ncs_write_setup; | ||
16 | u8 nwe_setup; | ||
17 | |||
18 | /* Pulse register */ | ||
19 | u8 ncs_read_pulse; | ||
20 | u8 nrd_pulse; | ||
21 | u8 ncs_write_pulse; | ||
22 | u8 nwe_pulse; | ||
23 | |||
24 | /* Cycle register */ | ||
25 | u16 read_cycle; | ||
26 | u16 write_cycle; | ||
27 | |||
28 | /* Mode register */ | ||
29 | u32 mode; | ||
30 | u8 tdf_cycles:4; | ||
31 | }; | ||
32 | |||
33 | extern void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config); | ||
34 | extern void __init at91sam9_ioremap_smc(int id, u32 addr); | 11 | extern void __init at91sam9_ioremap_smc(int id, u32 addr); |
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c index 8bdcc3cb6012..69d3fc4c46f3 100644 --- a/arch/arm/mach-at91/setup.c +++ b/arch/arm/mach-at91/setup.c | |||
@@ -29,9 +29,12 @@ EXPORT_SYMBOL(at91_soc_initdata); | |||
29 | void __init at91rm9200_set_type(int type) | 29 | void __init at91rm9200_set_type(int type) |
30 | { | 30 | { |
31 | if (type == ARCH_REVISON_9200_PQFP) | 31 | if (type == ARCH_REVISON_9200_PQFP) |
32 | at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA; | ||
33 | else | ||
34 | at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP; | 32 | at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP; |
33 | else | ||
34 | at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA; | ||
35 | |||
36 | pr_info("AT91: filled in soc subtype: %s\n", | ||
37 | at91_get_soc_subtype(&at91_soc_initdata)); | ||
35 | } | 38 | } |
36 | 39 | ||
37 | void __init at91_init_irq_default(void) | 40 | void __init at91_init_irq_default(void) |
@@ -281,6 +284,15 @@ void __init at91_ioremap_shdwc(u32 base_addr) | |||
281 | pm_power_off = at91sam9_poweroff; | 284 | pm_power_off = at91sam9_poweroff; |
282 | } | 285 | } |
283 | 286 | ||
287 | void __iomem *at91_rstc_base; | ||
288 | |||
289 | void __init at91_ioremap_rstc(u32 base_addr) | ||
290 | { | ||
291 | at91_rstc_base = ioremap(base_addr, 16); | ||
292 | if (!at91_rstc_base) | ||
293 | panic("Impossible to ioremap at91_rstc_base\n"); | ||
294 | } | ||
295 | |||
284 | void __init at91_initialize(unsigned long main_clock) | 296 | void __init at91_initialize(unsigned long main_clock) |
285 | { | 297 | { |
286 | at91_boot_soc.ioremap_registers(); | 298 | at91_boot_soc.ioremap_registers(); |
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c index 9e5e7552498c..45c97b1ee9b1 100644 --- a/arch/arm/mach-bcmring/arch.c +++ b/arch/arm/mach-bcmring/arch.c | |||
@@ -194,6 +194,6 @@ MACHINE_START(BCMRING, "BCMRING") | |||
194 | .init_early = bcmring_init_early, | 194 | .init_early = bcmring_init_early, |
195 | .init_irq = bcmring_init_irq, | 195 | .init_irq = bcmring_init_irq, |
196 | .timer = &bcmring_timer, | 196 | .timer = &bcmring_timer, |
197 | .init_machine = bcmring_init_machine | 197 | .init_machine = bcmring_init_machine, |
198 | .restart = bcmring_restart, | 198 | .restart = bcmring_restart, |
199 | MACHINE_END | 199 | MACHINE_END |
diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c index 1a1a27dd5654..1024396797e1 100644 --- a/arch/arm/mach-bcmring/dma.c +++ b/arch/arm/mach-bcmring/dma.c | |||
@@ -33,17 +33,11 @@ | |||
33 | 33 | ||
34 | #include <mach/timer.h> | 34 | #include <mach/timer.h> |
35 | 35 | ||
36 | #include <linux/mm.h> | ||
37 | #include <linux/pfn.h> | 36 | #include <linux/pfn.h> |
38 | #include <linux/atomic.h> | 37 | #include <linux/atomic.h> |
39 | #include <linux/sched.h> | 38 | #include <linux/sched.h> |
40 | #include <mach/dma.h> | 39 | #include <mach/dma.h> |
41 | 40 | ||
42 | /* I don't quite understand why dc4 fails when this is set to 1 and DMA is enabled */ | ||
43 | /* especially since dc4 doesn't use kmalloc'd memory. */ | ||
44 | |||
45 | #define ALLOW_MAP_OF_KMALLOC_MEMORY 0 | ||
46 | |||
47 | /* ---- Public Variables ------------------------------------------------- */ | 41 | /* ---- Public Variables ------------------------------------------------- */ |
48 | 42 | ||
49 | /* ---- Private Constants and Types -------------------------------------- */ | 43 | /* ---- Private Constants and Types -------------------------------------- */ |
@@ -53,24 +47,12 @@ | |||
53 | #define CONTROLLER_FROM_HANDLE(handle) (((handle) >> 4) & 0x0f) | 47 | #define CONTROLLER_FROM_HANDLE(handle) (((handle) >> 4) & 0x0f) |
54 | #define CHANNEL_FROM_HANDLE(handle) ((handle) & 0x0f) | 48 | #define CHANNEL_FROM_HANDLE(handle) ((handle) & 0x0f) |
55 | 49 | ||
56 | #define DMA_MAP_DEBUG 0 | ||
57 | |||
58 | #if DMA_MAP_DEBUG | ||
59 | # define DMA_MAP_PRINT(fmt, args...) printk("%s: " fmt, __func__, ## args) | ||
60 | #else | ||
61 | # define DMA_MAP_PRINT(fmt, args...) | ||
62 | #endif | ||
63 | 50 | ||
64 | /* ---- Private Variables ------------------------------------------------ */ | 51 | /* ---- Private Variables ------------------------------------------------ */ |
65 | 52 | ||
66 | static DMA_Global_t gDMA; | 53 | static DMA_Global_t gDMA; |
67 | static struct proc_dir_entry *gDmaDir; | 54 | static struct proc_dir_entry *gDmaDir; |
68 | 55 | ||
69 | static atomic_t gDmaStatMemTypeKmalloc = ATOMIC_INIT(0); | ||
70 | static atomic_t gDmaStatMemTypeVmalloc = ATOMIC_INIT(0); | ||
71 | static atomic_t gDmaStatMemTypeUser = ATOMIC_INIT(0); | ||
72 | static atomic_t gDmaStatMemTypeCoherent = ATOMIC_INIT(0); | ||
73 | |||
74 | #include "dma_device.c" | 56 | #include "dma_device.c" |
75 | 57 | ||
76 | /* ---- Private Function Prototypes -------------------------------------- */ | 58 | /* ---- Private Function Prototypes -------------------------------------- */ |
@@ -79,34 +61,6 @@ static atomic_t gDmaStatMemTypeCoherent = ATOMIC_INIT(0); | |||
79 | 61 | ||
80 | /****************************************************************************/ | 62 | /****************************************************************************/ |
81 | /** | 63 | /** |
82 | * Displays information for /proc/dma/mem-type | ||
83 | */ | ||
84 | /****************************************************************************/ | ||
85 | |||
86 | static int dma_proc_read_mem_type(char *buf, char **start, off_t offset, | ||
87 | int count, int *eof, void *data) | ||
88 | { | ||
89 | int len = 0; | ||
90 | |||
91 | len += sprintf(buf + len, "dma_map_mem statistics\n"); | ||
92 | len += | ||
93 | sprintf(buf + len, "coherent: %d\n", | ||
94 | atomic_read(&gDmaStatMemTypeCoherent)); | ||
95 | len += | ||
96 | sprintf(buf + len, "kmalloc: %d\n", | ||
97 | atomic_read(&gDmaStatMemTypeKmalloc)); | ||
98 | len += | ||
99 | sprintf(buf + len, "vmalloc: %d\n", | ||
100 | atomic_read(&gDmaStatMemTypeVmalloc)); | ||
101 | len += | ||
102 | sprintf(buf + len, "user: %d\n", | ||
103 | atomic_read(&gDmaStatMemTypeUser)); | ||
104 | |||
105 | return len; | ||
106 | } | ||
107 | |||
108 | /****************************************************************************/ | ||
109 | /** | ||
110 | * Displays information for /proc/dma/channels | 64 | * Displays information for /proc/dma/channels |
111 | */ | 65 | */ |
112 | /****************************************************************************/ | 66 | /****************************************************************************/ |
@@ -846,8 +800,6 @@ int dma_init(void) | |||
846 | dma_proc_read_channels, NULL); | 800 | dma_proc_read_channels, NULL); |
847 | create_proc_read_entry("devices", 0, gDmaDir, | 801 | create_proc_read_entry("devices", 0, gDmaDir, |
848 | dma_proc_read_devices, NULL); | 802 | dma_proc_read_devices, NULL); |
849 | create_proc_read_entry("mem-type", 0, gDmaDir, | ||
850 | dma_proc_read_mem_type, NULL); | ||
851 | } | 803 | } |
852 | 804 | ||
853 | out: | 805 | out: |
@@ -1565,767 +1517,3 @@ int dma_set_device_handler(DMA_Device_t dev, /* Device to set the callback for. | |||
1565 | } | 1517 | } |
1566 | 1518 | ||
1567 | EXPORT_SYMBOL(dma_set_device_handler); | 1519 | EXPORT_SYMBOL(dma_set_device_handler); |
1568 | |||
1569 | /****************************************************************************/ | ||
1570 | /** | ||
1571 | * Initializes a memory mapping structure | ||
1572 | */ | ||
1573 | /****************************************************************************/ | ||
1574 | |||
1575 | int dma_init_mem_map(DMA_MemMap_t *memMap) | ||
1576 | { | ||
1577 | memset(memMap, 0, sizeof(*memMap)); | ||
1578 | |||
1579 | sema_init(&memMap->lock, 1); | ||
1580 | |||
1581 | return 0; | ||
1582 | } | ||
1583 | |||
1584 | EXPORT_SYMBOL(dma_init_mem_map); | ||
1585 | |||
1586 | /****************************************************************************/ | ||
1587 | /** | ||
1588 | * Releases any memory currently being held by a memory mapping structure. | ||
1589 | */ | ||
1590 | /****************************************************************************/ | ||
1591 | |||
1592 | int dma_term_mem_map(DMA_MemMap_t *memMap) | ||
1593 | { | ||
1594 | down(&memMap->lock); /* Just being paranoid */ | ||
1595 | |||
1596 | /* Free up any allocated memory */ | ||
1597 | |||
1598 | up(&memMap->lock); | ||
1599 | memset(memMap, 0, sizeof(*memMap)); | ||
1600 | |||
1601 | return 0; | ||
1602 | } | ||
1603 | |||
1604 | EXPORT_SYMBOL(dma_term_mem_map); | ||
1605 | |||
1606 | /****************************************************************************/ | ||
1607 | /** | ||
1608 | * Looks at a memory address and categorizes it. | ||
1609 | * | ||
1610 | * @return One of the values from the DMA_MemType_t enumeration. | ||
1611 | */ | ||
1612 | /****************************************************************************/ | ||
1613 | |||
1614 | DMA_MemType_t dma_mem_type(void *addr) | ||
1615 | { | ||
1616 | unsigned long addrVal = (unsigned long)addr; | ||
1617 | |||
1618 | if (addrVal >= CONSISTENT_BASE) { | ||
1619 | /* NOTE: DMA virtual memory space starts at 0xFFxxxxxx */ | ||
1620 | |||
1621 | /* dma_alloc_xxx pages are physically and virtually contiguous */ | ||
1622 | |||
1623 | return DMA_MEM_TYPE_DMA; | ||
1624 | } | ||
1625 | |||
1626 | /* Technically, we could add one more classification. Addresses between VMALLOC_END */ | ||
1627 | /* and the beginning of the DMA virtual address could be considered to be I/O space. */ | ||
1628 | /* Right now, nobody cares about this particular classification, so we ignore it. */ | ||
1629 | |||
1630 | if (is_vmalloc_addr(addr)) { | ||
1631 | /* Address comes from the vmalloc'd region. Pages are virtually */ | ||
1632 | /* contiguous but NOT physically contiguous */ | ||
1633 | |||
1634 | return DMA_MEM_TYPE_VMALLOC; | ||
1635 | } | ||
1636 | |||
1637 | if (addrVal >= PAGE_OFFSET) { | ||
1638 | /* PAGE_OFFSET is typically 0xC0000000 */ | ||
1639 | |||
1640 | /* kmalloc'd pages are physically contiguous */ | ||
1641 | |||
1642 | return DMA_MEM_TYPE_KMALLOC; | ||
1643 | } | ||
1644 | |||
1645 | return DMA_MEM_TYPE_USER; | ||
1646 | } | ||
1647 | |||
1648 | EXPORT_SYMBOL(dma_mem_type); | ||
1649 | |||
1650 | /****************************************************************************/ | ||
1651 | /** | ||
1652 | * Looks at a memory address and determines if we support DMA'ing to/from | ||
1653 | * that type of memory. | ||
1654 | * | ||
1655 | * @return boolean - | ||
1656 | * return value != 0 means dma supported | ||
1657 | * return value == 0 means dma not supported | ||
1658 | */ | ||
1659 | /****************************************************************************/ | ||
1660 | |||
1661 | int dma_mem_supports_dma(void *addr) | ||
1662 | { | ||
1663 | DMA_MemType_t memType = dma_mem_type(addr); | ||
1664 | |||
1665 | return (memType == DMA_MEM_TYPE_DMA) | ||
1666 | #if ALLOW_MAP_OF_KMALLOC_MEMORY | ||
1667 | || (memType == DMA_MEM_TYPE_KMALLOC) | ||
1668 | #endif | ||
1669 | || (memType == DMA_MEM_TYPE_USER); | ||
1670 | } | ||
1671 | |||
1672 | EXPORT_SYMBOL(dma_mem_supports_dma); | ||
1673 | |||
1674 | /****************************************************************************/ | ||
1675 | /** | ||
1676 | * Maps in a memory region such that it can be used for performing a DMA. | ||
1677 | * | ||
1678 | * @return | ||
1679 | */ | ||
1680 | /****************************************************************************/ | ||
1681 | |||
1682 | int dma_map_start(DMA_MemMap_t *memMap, /* Stores state information about the map */ | ||
1683 | enum dma_data_direction dir /* Direction that the mapping will be going */ | ||
1684 | ) { | ||
1685 | int rc; | ||
1686 | |||
1687 | down(&memMap->lock); | ||
1688 | |||
1689 | DMA_MAP_PRINT("memMap: %p\n", memMap); | ||
1690 | |||
1691 | if (memMap->inUse) { | ||
1692 | printk(KERN_ERR "%s: memory map %p is already being used\n", | ||
1693 | __func__, memMap); | ||
1694 | rc = -EBUSY; | ||
1695 | goto out; | ||
1696 | } | ||
1697 | |||
1698 | memMap->inUse = 1; | ||
1699 | memMap->dir = dir; | ||
1700 | memMap->numRegionsUsed = 0; | ||
1701 | |||
1702 | rc = 0; | ||
1703 | |||
1704 | out: | ||
1705 | |||
1706 | DMA_MAP_PRINT("returning %d", rc); | ||
1707 | |||
1708 | up(&memMap->lock); | ||
1709 | |||
1710 | return rc; | ||
1711 | } | ||
1712 | |||
1713 | EXPORT_SYMBOL(dma_map_start); | ||
1714 | |||
1715 | /****************************************************************************/ | ||
1716 | /** | ||
1717 | * Adds a segment of memory to a memory map. Each segment is both | ||
1718 | * physically and virtually contiguous. | ||
1719 | * | ||
1720 | * @return 0 on success, error code otherwise. | ||
1721 | */ | ||
1722 | /****************************************************************************/ | ||
1723 | |||
1724 | static int dma_map_add_segment(DMA_MemMap_t *memMap, /* Stores state information about the map */ | ||
1725 | DMA_Region_t *region, /* Region that the segment belongs to */ | ||
1726 | void *virtAddr, /* Virtual address of the segment being added */ | ||
1727 | dma_addr_t physAddr, /* Physical address of the segment being added */ | ||
1728 | size_t numBytes /* Number of bytes of the segment being added */ | ||
1729 | ) { | ||
1730 | DMA_Segment_t *segment; | ||
1731 | |||
1732 | DMA_MAP_PRINT("memMap:%p va:%p pa:0x%x #:%d\n", memMap, virtAddr, | ||
1733 | physAddr, numBytes); | ||
1734 | |||
1735 | /* Sanity check */ | ||
1736 | |||
1737 | if (((unsigned long)virtAddr < (unsigned long)region->virtAddr) | ||
1738 | || (((unsigned long)virtAddr + numBytes)) > | ||
1739 | ((unsigned long)region->virtAddr + region->numBytes)) { | ||
1740 | printk(KERN_ERR | ||
1741 | "%s: virtAddr %p is outside region @ %p len: %d\n", | ||
1742 | __func__, virtAddr, region->virtAddr, region->numBytes); | ||
1743 | return -EINVAL; | ||
1744 | } | ||
1745 | |||
1746 | if (region->numSegmentsUsed > 0) { | ||
1747 | /* Check to see if this segment is physically contiguous with the previous one */ | ||
1748 | |||
1749 | segment = ®ion->segment[region->numSegmentsUsed - 1]; | ||
1750 | |||
1751 | if ((segment->physAddr + segment->numBytes) == physAddr) { | ||
1752 | /* It is - just add on to the end */ | ||
1753 | |||
1754 | DMA_MAP_PRINT("appending %d bytes to last segment\n", | ||
1755 | numBytes); | ||
1756 | |||
1757 | segment->numBytes += numBytes; | ||
1758 | |||
1759 | return 0; | ||
1760 | } | ||
1761 | } | ||
1762 | |||
1763 | /* Reallocate to hold more segments, if required. */ | ||
1764 | |||
1765 | if (region->numSegmentsUsed >= region->numSegmentsAllocated) { | ||
1766 | DMA_Segment_t *newSegment; | ||
1767 | size_t oldSize = | ||
1768 | region->numSegmentsAllocated * sizeof(*newSegment); | ||
1769 | int newAlloc = region->numSegmentsAllocated + 4; | ||
1770 | size_t newSize = newAlloc * sizeof(*newSegment); | ||
1771 | |||
1772 | newSegment = kmalloc(newSize, GFP_KERNEL); | ||
1773 | if (newSegment == NULL) { | ||
1774 | return -ENOMEM; | ||
1775 | } | ||
1776 | memcpy(newSegment, region->segment, oldSize); | ||
1777 | memset(&((uint8_t *) newSegment)[oldSize], 0, | ||
1778 | newSize - oldSize); | ||
1779 | kfree(region->segment); | ||
1780 | |||
1781 | region->numSegmentsAllocated = newAlloc; | ||
1782 | region->segment = newSegment; | ||
1783 | } | ||
1784 | |||
1785 | segment = ®ion->segment[region->numSegmentsUsed]; | ||
1786 | region->numSegmentsUsed++; | ||
1787 | |||
1788 | segment->virtAddr = virtAddr; | ||
1789 | segment->physAddr = physAddr; | ||
1790 | segment->numBytes = numBytes; | ||
1791 | |||
1792 | DMA_MAP_PRINT("returning success\n"); | ||
1793 | |||
1794 | return 0; | ||
1795 | } | ||
1796 | |||
1797 | /****************************************************************************/ | ||
1798 | /** | ||
1799 | * Adds a region of memory to a memory map. Each region is virtually | ||
1800 | * contiguous, but not necessarily physically contiguous. | ||
1801 | * | ||
1802 | * @return 0 on success, error code otherwise. | ||
1803 | */ | ||
1804 | /****************************************************************************/ | ||
1805 | |||
1806 | int dma_map_add_region(DMA_MemMap_t *memMap, /* Stores state information about the map */ | ||
1807 | void *mem, /* Virtual address that we want to get a map of */ | ||
1808 | size_t numBytes /* Number of bytes being mapped */ | ||
1809 | ) { | ||
1810 | unsigned long addr = (unsigned long)mem; | ||
1811 | unsigned int offset; | ||
1812 | int rc = 0; | ||
1813 | DMA_Region_t *region; | ||
1814 | dma_addr_t physAddr; | ||
1815 | |||
1816 | down(&memMap->lock); | ||
1817 | |||
1818 | DMA_MAP_PRINT("memMap:%p va:%p #:%d\n", memMap, mem, numBytes); | ||
1819 | |||
1820 | if (!memMap->inUse) { | ||
1821 | printk(KERN_ERR "%s: Make sure you call dma_map_start first\n", | ||
1822 | __func__); | ||
1823 | rc = -EINVAL; | ||
1824 | goto out; | ||
1825 | } | ||
1826 | |||
1827 | /* Reallocate to hold more regions. */ | ||
1828 | |||
1829 | if (memMap->numRegionsUsed >= memMap->numRegionsAllocated) { | ||
1830 | DMA_Region_t *newRegion; | ||
1831 | size_t oldSize = | ||
1832 | memMap->numRegionsAllocated * sizeof(*newRegion); | ||
1833 | int newAlloc = memMap->numRegionsAllocated + 4; | ||
1834 | size_t newSize = newAlloc * sizeof(*newRegion); | ||
1835 | |||
1836 | newRegion = kmalloc(newSize, GFP_KERNEL); | ||
1837 | if (newRegion == NULL) { | ||
1838 | rc = -ENOMEM; | ||
1839 | goto out; | ||
1840 | } | ||
1841 | memcpy(newRegion, memMap->region, oldSize); | ||
1842 | memset(&((uint8_t *) newRegion)[oldSize], 0, newSize - oldSize); | ||
1843 | |||
1844 | kfree(memMap->region); | ||
1845 | |||
1846 | memMap->numRegionsAllocated = newAlloc; | ||
1847 | memMap->region = newRegion; | ||
1848 | } | ||
1849 | |||
1850 | region = &memMap->region[memMap->numRegionsUsed]; | ||
1851 | memMap->numRegionsUsed++; | ||
1852 | |||
1853 | offset = addr & ~PAGE_MASK; | ||
1854 | |||
1855 | region->memType = dma_mem_type(mem); | ||
1856 | region->virtAddr = mem; | ||
1857 | region->numBytes = numBytes; | ||
1858 | region->numSegmentsUsed = 0; | ||
1859 | region->numLockedPages = 0; | ||
1860 | region->lockedPages = NULL; | ||
1861 | |||
1862 | switch (region->memType) { | ||
1863 | case DMA_MEM_TYPE_VMALLOC: | ||
1864 | { | ||
1865 | atomic_inc(&gDmaStatMemTypeVmalloc); | ||
1866 | |||
1867 | /* printk(KERN_ERR "%s: vmalloc'd pages are not supported\n", __func__); */ | ||
1868 | |||
1869 | /* vmalloc'd pages are not physically contiguous */ | ||
1870 | |||
1871 | rc = -EINVAL; | ||
1872 | break; | ||
1873 | } | ||
1874 | |||
1875 | case DMA_MEM_TYPE_KMALLOC: | ||
1876 | { | ||
1877 | atomic_inc(&gDmaStatMemTypeKmalloc); | ||
1878 | |||
1879 | /* kmalloc'd pages are physically contiguous, so they'll have exactly */ | ||
1880 | /* one segment */ | ||
1881 | |||
1882 | #if ALLOW_MAP_OF_KMALLOC_MEMORY | ||
1883 | physAddr = | ||
1884 | dma_map_single(NULL, mem, numBytes, memMap->dir); | ||
1885 | rc = dma_map_add_segment(memMap, region, mem, physAddr, | ||
1886 | numBytes); | ||
1887 | #else | ||
1888 | rc = -EINVAL; | ||
1889 | #endif | ||
1890 | break; | ||
1891 | } | ||
1892 | |||
1893 | case DMA_MEM_TYPE_DMA: | ||
1894 | { | ||
1895 | /* dma_alloc_xxx pages are physically contiguous */ | ||
1896 | |||
1897 | atomic_inc(&gDmaStatMemTypeCoherent); | ||
1898 | |||
1899 | physAddr = (vmalloc_to_pfn(mem) << PAGE_SHIFT) + offset; | ||
1900 | |||
1901 | dma_sync_single_for_cpu(NULL, physAddr, numBytes, | ||
1902 | memMap->dir); | ||
1903 | rc = dma_map_add_segment(memMap, region, mem, physAddr, | ||
1904 | numBytes); | ||
1905 | break; | ||
1906 | } | ||
1907 | |||
1908 | case DMA_MEM_TYPE_USER: | ||
1909 | { | ||
1910 | size_t firstPageOffset; | ||
1911 | size_t firstPageSize; | ||
1912 | struct page **pages; | ||
1913 | struct task_struct *userTask; | ||
1914 | |||
1915 | atomic_inc(&gDmaStatMemTypeUser); | ||
1916 | |||
1917 | #if 1 | ||
1918 | /* If the pages are user pages, then the dma_mem_map_set_user_task function */ | ||
1919 | /* must have been previously called. */ | ||
1920 | |||
1921 | if (memMap->userTask == NULL) { | ||
1922 | printk(KERN_ERR | ||
1923 | "%s: must call dma_mem_map_set_user_task when using user-mode memory\n", | ||
1924 | __func__); | ||
1925 | return -EINVAL; | ||
1926 | } | ||
1927 | |||
1928 | /* User pages need to be locked. */ | ||
1929 | |||
1930 | firstPageOffset = | ||
1931 | (unsigned long)region->virtAddr & (PAGE_SIZE - 1); | ||
1932 | firstPageSize = PAGE_SIZE - firstPageOffset; | ||
1933 | |||
1934 | region->numLockedPages = (firstPageOffset | ||
1935 | + region->numBytes + | ||
1936 | PAGE_SIZE - 1) / PAGE_SIZE; | ||
1937 | pages = | ||
1938 | kmalloc(region->numLockedPages * | ||
1939 | sizeof(struct page *), GFP_KERNEL); | ||
1940 | |||
1941 | if (pages == NULL) { | ||
1942 | region->numLockedPages = 0; | ||
1943 | return -ENOMEM; | ||
1944 | } | ||
1945 | |||
1946 | userTask = memMap->userTask; | ||
1947 | |||
1948 | down_read(&userTask->mm->mmap_sem); | ||
1949 | rc = get_user_pages(userTask, /* task */ | ||
1950 | userTask->mm, /* mm */ | ||
1951 | (unsigned long)region->virtAddr, /* start */ | ||
1952 | region->numLockedPages, /* len */ | ||
1953 | memMap->dir == DMA_FROM_DEVICE, /* write */ | ||
1954 | 0, /* force */ | ||
1955 | pages, /* pages (array of pointers to page) */ | ||
1956 | NULL); /* vmas */ | ||
1957 | up_read(&userTask->mm->mmap_sem); | ||
1958 | |||
1959 | if (rc != region->numLockedPages) { | ||
1960 | kfree(pages); | ||
1961 | region->numLockedPages = 0; | ||
1962 | |||
1963 | if (rc >= 0) { | ||
1964 | rc = -EINVAL; | ||
1965 | } | ||
1966 | } else { | ||
1967 | uint8_t *virtAddr = region->virtAddr; | ||
1968 | size_t bytesRemaining; | ||
1969 | int pageIdx; | ||
1970 | |||
1971 | rc = 0; /* Since get_user_pages returns +ve number */ | ||
1972 | |||
1973 | region->lockedPages = pages; | ||
1974 | |||
1975 | /* We've locked the user pages. Now we need to walk them and figure */ | ||
1976 | /* out the physical addresses. */ | ||
1977 | |||
1978 | /* The first page may be partial */ | ||
1979 | |||
1980 | dma_map_add_segment(memMap, | ||
1981 | region, | ||
1982 | virtAddr, | ||
1983 | PFN_PHYS(page_to_pfn | ||
1984 | (pages[0])) + | ||
1985 | firstPageOffset, | ||
1986 | firstPageSize); | ||
1987 | |||
1988 | virtAddr += firstPageSize; | ||
1989 | bytesRemaining = | ||
1990 | region->numBytes - firstPageSize; | ||
1991 | |||
1992 | for (pageIdx = 1; | ||
1993 | pageIdx < region->numLockedPages; | ||
1994 | pageIdx++) { | ||
1995 | size_t bytesThisPage = | ||
1996 | (bytesRemaining > | ||
1997 | PAGE_SIZE ? PAGE_SIZE : | ||
1998 | bytesRemaining); | ||
1999 | |||
2000 | DMA_MAP_PRINT | ||
2001 | ("pageIdx:%d pages[pageIdx]=%p pfn=%u phys=%u\n", | ||
2002 | pageIdx, pages[pageIdx], | ||
2003 | page_to_pfn(pages[pageIdx]), | ||
2004 | PFN_PHYS(page_to_pfn | ||
2005 | (pages[pageIdx]))); | ||
2006 | |||
2007 | dma_map_add_segment(memMap, | ||
2008 | region, | ||
2009 | virtAddr, | ||
2010 | PFN_PHYS(page_to_pfn | ||
2011 | (pages | ||
2012 | [pageIdx])), | ||
2013 | bytesThisPage); | ||
2014 | |||
2015 | virtAddr += bytesThisPage; | ||
2016 | bytesRemaining -= bytesThisPage; | ||
2017 | } | ||
2018 | } | ||
2019 | #else | ||
2020 | printk(KERN_ERR | ||
2021 | "%s: User mode pages are not yet supported\n", | ||
2022 | __func__); | ||
2023 | |||
2024 | /* user pages are not physically contiguous */ | ||
2025 | |||
2026 | rc = -EINVAL; | ||
2027 | #endif | ||
2028 | break; | ||
2029 | } | ||
2030 | |||
2031 | default: | ||
2032 | { | ||
2033 | printk(KERN_ERR "%s: Unsupported memory type: %d\n", | ||
2034 | __func__, region->memType); | ||
2035 | |||
2036 | rc = -EINVAL; | ||
2037 | break; | ||
2038 | } | ||
2039 | } | ||
2040 | |||
2041 | if (rc != 0) { | ||
2042 | memMap->numRegionsUsed--; | ||
2043 | } | ||
2044 | |||
2045 | out: | ||
2046 | |||
2047 | DMA_MAP_PRINT("returning %d\n", rc); | ||
2048 | |||
2049 | up(&memMap->lock); | ||
2050 | |||
2051 | return rc; | ||
2052 | } | ||
2053 | |||
2054 | EXPORT_SYMBOL(dma_map_add_segment); | ||
2055 | |||
2056 | /****************************************************************************/ | ||
2057 | /** | ||
2058 | * Maps in a memory region such that it can be used for performing a DMA. | ||
2059 | * | ||
2060 | * @return 0 on success, error code otherwise. | ||
2061 | */ | ||
2062 | /****************************************************************************/ | ||
2063 | |||
2064 | int dma_map_mem(DMA_MemMap_t *memMap, /* Stores state information about the map */ | ||
2065 | void *mem, /* Virtual address that we want to get a map of */ | ||
2066 | size_t numBytes, /* Number of bytes being mapped */ | ||
2067 | enum dma_data_direction dir /* Direction that the mapping will be going */ | ||
2068 | ) { | ||
2069 | int rc; | ||
2070 | |||
2071 | rc = dma_map_start(memMap, dir); | ||
2072 | if (rc == 0) { | ||
2073 | rc = dma_map_add_region(memMap, mem, numBytes); | ||
2074 | if (rc < 0) { | ||
2075 | /* Since the add fails, this function will fail, and the caller won't */ | ||
2076 | /* call unmap, so we need to do it here. */ | ||
2077 | |||
2078 | dma_unmap(memMap, 0); | ||
2079 | } | ||
2080 | } | ||
2081 | |||
2082 | return rc; | ||
2083 | } | ||
2084 | |||
2085 | EXPORT_SYMBOL(dma_map_mem); | ||
2086 | |||
2087 | /****************************************************************************/ | ||
2088 | /** | ||
2089 | * Setup a descriptor ring for a given memory map. | ||
2090 | * | ||
2091 | * It is assumed that the descriptor ring has already been initialized, and | ||
2092 | * this routine will only reallocate a new descriptor ring if the existing | ||
2093 | * one is too small. | ||
2094 | * | ||
2095 | * @return 0 on success, error code otherwise. | ||
2096 | */ | ||
2097 | /****************************************************************************/ | ||
2098 | |||
2099 | int dma_map_create_descriptor_ring(DMA_Device_t dev, /* DMA device (where the ring is stored) */ | ||
2100 | DMA_MemMap_t *memMap, /* Memory map that will be used */ | ||
2101 | dma_addr_t devPhysAddr /* Physical address of device */ | ||
2102 | ) { | ||
2103 | int rc; | ||
2104 | int numDescriptors; | ||
2105 | DMA_DeviceAttribute_t *devAttr; | ||
2106 | DMA_Region_t *region; | ||
2107 | DMA_Segment_t *segment; | ||
2108 | dma_addr_t srcPhysAddr; | ||
2109 | dma_addr_t dstPhysAddr; | ||
2110 | int regionIdx; | ||
2111 | int segmentIdx; | ||
2112 | |||
2113 | devAttr = &DMA_gDeviceAttribute[dev]; | ||
2114 | |||
2115 | down(&memMap->lock); | ||
2116 | |||
2117 | /* Figure out how many descriptors we need */ | ||
2118 | |||
2119 | numDescriptors = 0; | ||
2120 | for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) { | ||
2121 | region = &memMap->region[regionIdx]; | ||
2122 | |||
2123 | for (segmentIdx = 0; segmentIdx < region->numSegmentsUsed; | ||
2124 | segmentIdx++) { | ||
2125 | segment = ®ion->segment[segmentIdx]; | ||
2126 | |||
2127 | if (memMap->dir == DMA_TO_DEVICE) { | ||
2128 | srcPhysAddr = segment->physAddr; | ||
2129 | dstPhysAddr = devPhysAddr; | ||
2130 | } else { | ||
2131 | srcPhysAddr = devPhysAddr; | ||
2132 | dstPhysAddr = segment->physAddr; | ||
2133 | } | ||
2134 | |||
2135 | rc = | ||
2136 | dma_calculate_descriptor_count(dev, srcPhysAddr, | ||
2137 | dstPhysAddr, | ||
2138 | segment-> | ||
2139 | numBytes); | ||
2140 | if (rc < 0) { | ||
2141 | printk(KERN_ERR | ||
2142 | "%s: dma_calculate_descriptor_count failed: %d\n", | ||
2143 | __func__, rc); | ||
2144 | goto out; | ||
2145 | } | ||
2146 | numDescriptors += rc; | ||
2147 | } | ||
2148 | } | ||
2149 | |||
2150 | /* Adjust the size of the ring, if it isn't big enough */ | ||
2151 | |||
2152 | if (numDescriptors > devAttr->ring.descriptorsAllocated) { | ||
2153 | dma_free_descriptor_ring(&devAttr->ring); | ||
2154 | rc = | ||
2155 | dma_alloc_descriptor_ring(&devAttr->ring, | ||
2156 | numDescriptors); | ||
2157 | if (rc < 0) { | ||
2158 | printk(KERN_ERR | ||
2159 | "%s: dma_alloc_descriptor_ring failed: %d\n", | ||
2160 | __func__, rc); | ||
2161 | goto out; | ||
2162 | } | ||
2163 | } else { | ||
2164 | rc = | ||
2165 | dma_init_descriptor_ring(&devAttr->ring, | ||
2166 | numDescriptors); | ||
2167 | if (rc < 0) { | ||
2168 | printk(KERN_ERR | ||
2169 | "%s: dma_init_descriptor_ring failed: %d\n", | ||
2170 | __func__, rc); | ||
2171 | goto out; | ||
2172 | } | ||
2173 | } | ||
2174 | |||
2175 | /* Populate the descriptors */ | ||
2176 | |||
2177 | for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) { | ||
2178 | region = &memMap->region[regionIdx]; | ||
2179 | |||
2180 | for (segmentIdx = 0; segmentIdx < region->numSegmentsUsed; | ||
2181 | segmentIdx++) { | ||
2182 | segment = ®ion->segment[segmentIdx]; | ||
2183 | |||
2184 | if (memMap->dir == DMA_TO_DEVICE) { | ||
2185 | srcPhysAddr = segment->physAddr; | ||
2186 | dstPhysAddr = devPhysAddr; | ||
2187 | } else { | ||
2188 | srcPhysAddr = devPhysAddr; | ||
2189 | dstPhysAddr = segment->physAddr; | ||
2190 | } | ||
2191 | |||
2192 | rc = | ||
2193 | dma_add_descriptors(&devAttr->ring, dev, | ||
2194 | srcPhysAddr, dstPhysAddr, | ||
2195 | segment->numBytes); | ||
2196 | if (rc < 0) { | ||
2197 | printk(KERN_ERR | ||
2198 | "%s: dma_add_descriptors failed: %d\n", | ||
2199 | __func__, rc); | ||
2200 | goto out; | ||
2201 | } | ||
2202 | } | ||
2203 | } | ||
2204 | |||
2205 | rc = 0; | ||
2206 | |||
2207 | out: | ||
2208 | |||
2209 | up(&memMap->lock); | ||
2210 | return rc; | ||
2211 | } | ||
2212 | |||
2213 | EXPORT_SYMBOL(dma_map_create_descriptor_ring); | ||
2214 | |||
2215 | /****************************************************************************/ | ||
2216 | /** | ||
2217 | * Maps in a memory region such that it can be used for performing a DMA. | ||
2218 | * | ||
2219 | * @return | ||
2220 | */ | ||
2221 | /****************************************************************************/ | ||
2222 | |||
2223 | int dma_unmap(DMA_MemMap_t *memMap, /* Stores state information about the map */ | ||
2224 | int dirtied /* non-zero if any of the pages were modified */ | ||
2225 | ) { | ||
2226 | |||
2227 | int rc = 0; | ||
2228 | int regionIdx; | ||
2229 | int segmentIdx; | ||
2230 | DMA_Region_t *region; | ||
2231 | DMA_Segment_t *segment; | ||
2232 | |||
2233 | down(&memMap->lock); | ||
2234 | |||
2235 | for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) { | ||
2236 | region = &memMap->region[regionIdx]; | ||
2237 | |||
2238 | for (segmentIdx = 0; segmentIdx < region->numSegmentsUsed; | ||
2239 | segmentIdx++) { | ||
2240 | segment = ®ion->segment[segmentIdx]; | ||
2241 | |||
2242 | switch (region->memType) { | ||
2243 | case DMA_MEM_TYPE_VMALLOC: | ||
2244 | { | ||
2245 | printk(KERN_ERR | ||
2246 | "%s: vmalloc'd pages are not yet supported\n", | ||
2247 | __func__); | ||
2248 | rc = -EINVAL; | ||
2249 | goto out; | ||
2250 | } | ||
2251 | |||
2252 | case DMA_MEM_TYPE_KMALLOC: | ||
2253 | { | ||
2254 | #if ALLOW_MAP_OF_KMALLOC_MEMORY | ||
2255 | dma_unmap_single(NULL, | ||
2256 | segment->physAddr, | ||
2257 | segment->numBytes, | ||
2258 | memMap->dir); | ||
2259 | #endif | ||
2260 | break; | ||
2261 | } | ||
2262 | |||
2263 | case DMA_MEM_TYPE_DMA: | ||
2264 | { | ||
2265 | dma_sync_single_for_cpu(NULL, | ||
2266 | segment-> | ||
2267 | physAddr, | ||
2268 | segment-> | ||
2269 | numBytes, | ||
2270 | memMap->dir); | ||
2271 | break; | ||
2272 | } | ||
2273 | |||
2274 | case DMA_MEM_TYPE_USER: | ||
2275 | { | ||
2276 | /* Nothing to do here. */ | ||
2277 | |||
2278 | break; | ||
2279 | } | ||
2280 | |||
2281 | default: | ||
2282 | { | ||
2283 | printk(KERN_ERR | ||
2284 | "%s: Unsupported memory type: %d\n", | ||
2285 | __func__, region->memType); | ||
2286 | rc = -EINVAL; | ||
2287 | goto out; | ||
2288 | } | ||
2289 | } | ||
2290 | |||
2291 | segment->virtAddr = NULL; | ||
2292 | segment->physAddr = 0; | ||
2293 | segment->numBytes = 0; | ||
2294 | } | ||
2295 | |||
2296 | if (region->numLockedPages > 0) { | ||
2297 | int pageIdx; | ||
2298 | |||
2299 | /* Some user pages were locked. We need to go and unlock them now. */ | ||
2300 | |||
2301 | for (pageIdx = 0; pageIdx < region->numLockedPages; | ||
2302 | pageIdx++) { | ||
2303 | struct page *page = | ||
2304 | region->lockedPages[pageIdx]; | ||
2305 | |||
2306 | if (memMap->dir == DMA_FROM_DEVICE) { | ||
2307 | SetPageDirty(page); | ||
2308 | } | ||
2309 | page_cache_release(page); | ||
2310 | } | ||
2311 | kfree(region->lockedPages); | ||
2312 | region->numLockedPages = 0; | ||
2313 | region->lockedPages = NULL; | ||
2314 | } | ||
2315 | |||
2316 | region->memType = DMA_MEM_TYPE_NONE; | ||
2317 | region->virtAddr = NULL; | ||
2318 | region->numBytes = 0; | ||
2319 | region->numSegmentsUsed = 0; | ||
2320 | } | ||
2321 | memMap->userTask = NULL; | ||
2322 | memMap->numRegionsUsed = 0; | ||
2323 | memMap->inUse = 0; | ||
2324 | |||
2325 | out: | ||
2326 | up(&memMap->lock); | ||
2327 | |||
2328 | return rc; | ||
2329 | } | ||
2330 | |||
2331 | EXPORT_SYMBOL(dma_unmap); | ||
diff --git a/arch/arm/mach-bcmring/include/mach/dma.h b/arch/arm/mach-bcmring/include/mach/dma.h index 1f2c5319c056..72543781207b 100644 --- a/arch/arm/mach-bcmring/include/mach/dma.h +++ b/arch/arm/mach-bcmring/include/mach/dma.h | |||
@@ -26,15 +26,9 @@ | |||
26 | /* ---- Include Files ---------------------------------------------------- */ | 26 | /* ---- Include Files ---------------------------------------------------- */ |
27 | 27 | ||
28 | #include <linux/kernel.h> | 28 | #include <linux/kernel.h> |
29 | #include <linux/wait.h> | ||
30 | #include <linux/semaphore.h> | 29 | #include <linux/semaphore.h> |
31 | #include <csp/dmacHw.h> | 30 | #include <csp/dmacHw.h> |
32 | #include <mach/timer.h> | 31 | #include <mach/timer.h> |
33 | #include <linux/scatterlist.h> | ||
34 | #include <linux/dma-mapping.h> | ||
35 | #include <linux/mm.h> | ||
36 | #include <linux/vmalloc.h> | ||
37 | #include <linux/pagemap.h> | ||
38 | 32 | ||
39 | /* ---- Constants and Types ---------------------------------------------- */ | 33 | /* ---- Constants and Types ---------------------------------------------- */ |
40 | 34 | ||
@@ -113,78 +107,6 @@ typedef struct { | |||
113 | 107 | ||
114 | /**************************************************************************** | 108 | /**************************************************************************** |
115 | * | 109 | * |
116 | * The DMA_MemType_t and DMA_MemMap_t are helper structures used to setup | ||
117 | * DMA chains from a variety of memory sources. | ||
118 | * | ||
119 | *****************************************************************************/ | ||
120 | |||
121 | #define DMA_MEM_MAP_MIN_SIZE 4096 /* Pages less than this size are better */ | ||
122 | /* off not being DMA'd. */ | ||
123 | |||
124 | typedef enum { | ||
125 | DMA_MEM_TYPE_NONE, /* Not a valid setting */ | ||
126 | DMA_MEM_TYPE_VMALLOC, /* Memory came from vmalloc call */ | ||
127 | DMA_MEM_TYPE_KMALLOC, /* Memory came from kmalloc call */ | ||
128 | DMA_MEM_TYPE_DMA, /* Memory came from dma_alloc_xxx call */ | ||
129 | DMA_MEM_TYPE_USER, /* Memory came from user space. */ | ||
130 | |||
131 | } DMA_MemType_t; | ||
132 | |||
133 | /* A segment represents a physically and virtually contiguous chunk of memory. */ | ||
134 | /* i.e. each segment can be DMA'd */ | ||
135 | /* A user of the DMA code will add memory regions. Each region may need to be */ | ||
136 | /* represented by one or more segments. */ | ||
137 | |||
138 | typedef struct { | ||
139 | void *virtAddr; /* Virtual address used for this segment */ | ||
140 | dma_addr_t physAddr; /* Physical address this segment maps to */ | ||
141 | size_t numBytes; /* Size of the segment, in bytes */ | ||
142 | |||
143 | } DMA_Segment_t; | ||
144 | |||
145 | /* A region represents a virtually contiguous chunk of memory, which may be */ | ||
146 | /* made up of multiple segments. */ | ||
147 | |||
148 | typedef struct { | ||
149 | DMA_MemType_t memType; | ||
150 | void *virtAddr; | ||
151 | size_t numBytes; | ||
152 | |||
153 | /* Each region (virtually contiguous) consists of one or more segments. Each */ | ||
154 | /* segment is virtually and physically contiguous. */ | ||
155 | |||
156 | int numSegmentsUsed; | ||
157 | int numSegmentsAllocated; | ||
158 | DMA_Segment_t *segment; | ||
159 | |||
160 | /* When a region corresponds to user memory, we need to lock all of the pages */ | ||
161 | /* down before we can figure out the physical addresses. The lockedPage array contains */ | ||
162 | /* the pages that were locked, and which subsequently need to be unlocked once the */ | ||
163 | /* memory is unmapped. */ | ||
164 | |||
165 | unsigned numLockedPages; | ||
166 | struct page **lockedPages; | ||
167 | |||
168 | } DMA_Region_t; | ||
169 | |||
170 | typedef struct { | ||
171 | int inUse; /* Is this mapping currently being used? */ | ||
172 | struct semaphore lock; /* Acquired when using this structure */ | ||
173 | enum dma_data_direction dir; /* Direction this transfer is intended for */ | ||
174 | |||
175 | /* In the event that we're mapping user memory, we need to know which task */ | ||
176 | /* the memory is for, so that we can obtain the correct mm locks. */ | ||
177 | |||
178 | struct task_struct *userTask; | ||
179 | |||
180 | int numRegionsUsed; | ||
181 | int numRegionsAllocated; | ||
182 | DMA_Region_t *region; | ||
183 | |||
184 | } DMA_MemMap_t; | ||
185 | |||
186 | /**************************************************************************** | ||
187 | * | ||
188 | * The DMA_DeviceAttribute_t contains information which describes a | 110 | * The DMA_DeviceAttribute_t contains information which describes a |
189 | * particular DMA device (or peripheral). | 111 | * particular DMA device (or peripheral). |
190 | * | 112 | * |
@@ -570,124 +492,6 @@ int dma_alloc_double_dst_descriptors(DMA_Handle_t handle, /* DMA Handle */ | |||
570 | 492 | ||
571 | /****************************************************************************/ | 493 | /****************************************************************************/ |
572 | /** | 494 | /** |
573 | * Initializes a DMA_MemMap_t data structure | ||
574 | */ | ||
575 | /****************************************************************************/ | ||
576 | |||
577 | int dma_init_mem_map(DMA_MemMap_t *memMap /* Stores state information about the map */ | ||
578 | ); | ||
579 | |||
580 | /****************************************************************************/ | ||
581 | /** | ||
582 | * Releases any memory currently being held by a memory mapping structure. | ||
583 | */ | ||
584 | /****************************************************************************/ | ||
585 | |||
586 | int dma_term_mem_map(DMA_MemMap_t *memMap /* Stores state information about the map */ | ||
587 | ); | ||
588 | |||
589 | /****************************************************************************/ | ||
590 | /** | ||
591 | * Looks at a memory address and categorizes it. | ||
592 | * | ||
593 | * @return One of the values from the DMA_MemType_t enumeration. | ||
594 | */ | ||
595 | /****************************************************************************/ | ||
596 | |||
597 | DMA_MemType_t dma_mem_type(void *addr); | ||
598 | |||
599 | /****************************************************************************/ | ||
600 | /** | ||
601 | * Sets the process (aka userTask) associated with a mem map. This is | ||
602 | * required if user-mode segments will be added to the mapping. | ||
603 | */ | ||
604 | /****************************************************************************/ | ||
605 | |||
606 | static inline void dma_mem_map_set_user_task(DMA_MemMap_t *memMap, | ||
607 | struct task_struct *task) | ||
608 | { | ||
609 | memMap->userTask = task; | ||
610 | } | ||
611 | |||
612 | /****************************************************************************/ | ||
613 | /** | ||
614 | * Looks at a memory address and determines if we support DMA'ing to/from | ||
615 | * that type of memory. | ||
616 | * | ||
617 | * @return boolean - | ||
618 | * return value != 0 means dma supported | ||
619 | * return value == 0 means dma not supported | ||
620 | */ | ||
621 | /****************************************************************************/ | ||
622 | |||
623 | int dma_mem_supports_dma(void *addr); | ||
624 | |||
625 | /****************************************************************************/ | ||
626 | /** | ||
627 | * Initializes a memory map for use. Since this function acquires a | ||
628 | * sempaphore within the memory map, it is VERY important that dma_unmap | ||
629 | * be called when you're finished using the map. | ||
630 | */ | ||
631 | /****************************************************************************/ | ||
632 | |||
633 | int dma_map_start(DMA_MemMap_t *memMap, /* Stores state information about the map */ | ||
634 | enum dma_data_direction dir /* Direction that the mapping will be going */ | ||
635 | ); | ||
636 | |||
637 | /****************************************************************************/ | ||
638 | /** | ||
639 | * Adds a segment of memory to a memory map. | ||
640 | * | ||
641 | * @return 0 on success, error code otherwise. | ||
642 | */ | ||
643 | /****************************************************************************/ | ||
644 | |||
645 | int dma_map_add_region(DMA_MemMap_t *memMap, /* Stores state information about the map */ | ||
646 | void *mem, /* Virtual address that we want to get a map of */ | ||
647 | size_t numBytes /* Number of bytes being mapped */ | ||
648 | ); | ||
649 | |||
650 | /****************************************************************************/ | ||
651 | /** | ||
652 | * Creates a descriptor ring from a memory mapping. | ||
653 | * | ||
654 | * @return 0 on success, error code otherwise. | ||
655 | */ | ||
656 | /****************************************************************************/ | ||
657 | |||
658 | int dma_map_create_descriptor_ring(DMA_Device_t dev, /* DMA device (where the ring is stored) */ | ||
659 | DMA_MemMap_t *memMap, /* Memory map that will be used */ | ||
660 | dma_addr_t devPhysAddr /* Physical address of device */ | ||
661 | ); | ||
662 | |||
663 | /****************************************************************************/ | ||
664 | /** | ||
665 | * Maps in a memory region such that it can be used for performing a DMA. | ||
666 | * | ||
667 | * @return | ||
668 | */ | ||
669 | /****************************************************************************/ | ||
670 | |||
671 | int dma_map_mem(DMA_MemMap_t *memMap, /* Stores state information about the map */ | ||
672 | void *addr, /* Virtual address that we want to get a map of */ | ||
673 | size_t count, /* Number of bytes being mapped */ | ||
674 | enum dma_data_direction dir /* Direction that the mapping will be going */ | ||
675 | ); | ||
676 | |||
677 | /****************************************************************************/ | ||
678 | /** | ||
679 | * Maps in a memory region such that it can be used for performing a DMA. | ||
680 | * | ||
681 | * @return | ||
682 | */ | ||
683 | /****************************************************************************/ | ||
684 | |||
685 | int dma_unmap(DMA_MemMap_t *memMap, /* Stores state information about the map */ | ||
686 | int dirtied /* non-zero if any of the pages were modified */ | ||
687 | ); | ||
688 | |||
689 | /****************************************************************************/ | ||
690 | /** | ||
691 | * Initiates a transfer when the descriptors have already been setup. | 495 | * Initiates a transfer when the descriptors have already been setup. |
692 | * | 496 | * |
693 | * This is a special case, and normally, the dma_transfer_xxx functions should | 497 | * This is a special case, and normally, the dma_transfer_xxx functions should |
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 6b22b543a83f..d5088900af6c 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c | |||
@@ -44,7 +44,7 @@ | |||
44 | #include <mach/aemif.h> | 44 | #include <mach/aemif.h> |
45 | #include <mach/spi.h> | 45 | #include <mach/spi.h> |
46 | 46 | ||
47 | #define DA850_EVM_PHY_ID "0:00" | 47 | #define DA850_EVM_PHY_ID "davinci_mdio-0:00" |
48 | #define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8) | 48 | #define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8) |
49 | #define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15) | 49 | #define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15) |
50 | 50 | ||
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c index 346e1de2f5a8..849311d3cb7c 100644 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ b/arch/arm/mach-davinci/board-dm365-evm.c | |||
@@ -54,7 +54,7 @@ static inline int have_tvp7002(void) | |||
54 | return 0; | 54 | return 0; |
55 | } | 55 | } |
56 | 56 | ||
57 | #define DM365_EVM_PHY_ID "0:01" | 57 | #define DM365_EVM_PHY_ID "davinci_mdio-0:01" |
58 | /* | 58 | /* |
59 | * A MAX-II CPLD is used for various board control functions. | 59 | * A MAX-II CPLD is used for various board control functions. |
60 | */ | 60 | */ |
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c index a64b49cfedca..1247ecdcf752 100644 --- a/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c | |||
@@ -40,7 +40,7 @@ | |||
40 | #include <mach/usb.h> | 40 | #include <mach/usb.h> |
41 | #include <mach/aemif.h> | 41 | #include <mach/aemif.h> |
42 | 42 | ||
43 | #define DM644X_EVM_PHY_ID "0:01" | 43 | #define DM644X_EVM_PHY_ID "davinci_mdio-0:01" |
44 | #define LXT971_PHY_ID (0x001378e2) | 44 | #define LXT971_PHY_ID (0x001378e2) |
45 | #define LXT971_PHY_MASK (0xfffffff0) | 45 | #define LXT971_PHY_MASK (0xfffffff0) |
46 | 46 | ||
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index 64017558860b..872ac69fa049 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c | |||
@@ -736,7 +736,7 @@ static struct davinci_uart_config uart_config __initdata = { | |||
736 | .enabled_uarts = (1 << 0), | 736 | .enabled_uarts = (1 << 0), |
737 | }; | 737 | }; |
738 | 738 | ||
739 | #define DM646X_EVM_PHY_ID "0:01" | 739 | #define DM646X_EVM_PHY_ID "davinci_mdio-0:01" |
740 | /* | 740 | /* |
741 | * The following EDMA channels/slots are not being used by drivers (for | 741 | * The following EDMA channels/slots are not being used by drivers (for |
742 | * example: Timer, GPIO, UART events etc) on dm646x, hence they are being | 742 | * example: Timer, GPIO, UART events etc) on dm646x, hence they are being |
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c index 6c4a16415d47..8d34f513d415 100644 --- a/arch/arm/mach-davinci/board-neuros-osd2.c +++ b/arch/arm/mach-davinci/board-neuros-osd2.c | |||
@@ -39,7 +39,7 @@ | |||
39 | #include <mach/mmc.h> | 39 | #include <mach/mmc.h> |
40 | #include <mach/usb.h> | 40 | #include <mach/usb.h> |
41 | 41 | ||
42 | #define NEUROS_OSD2_PHY_ID "0:01" | 42 | #define NEUROS_OSD2_PHY_ID "davinci_mdio-0:01" |
43 | #define LXT971_PHY_ID 0x001378e2 | 43 | #define LXT971_PHY_ID 0x001378e2 |
44 | #define LXT971_PHY_MASK 0xfffffff0 | 44 | #define LXT971_PHY_MASK 0xfffffff0 |
45 | 45 | ||
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c index e7c0c7c53493..45e815760a27 100644 --- a/arch/arm/mach-davinci/board-omapl138-hawk.c +++ b/arch/arm/mach-davinci/board-omapl138-hawk.c | |||
@@ -21,7 +21,7 @@ | |||
21 | #include <mach/da8xx.h> | 21 | #include <mach/da8xx.h> |
22 | #include <mach/mux.h> | 22 | #include <mach/mux.h> |
23 | 23 | ||
24 | #define HAWKBOARD_PHY_ID "0:07" | 24 | #define HAWKBOARD_PHY_ID "davinci_mdio-0:07" |
25 | #define DA850_HAWK_MMCSD_CD_PIN GPIO_TO_PIN(3, 12) | 25 | #define DA850_HAWK_MMCSD_CD_PIN GPIO_TO_PIN(3, 12) |
26 | #define DA850_HAWK_MMCSD_WP_PIN GPIO_TO_PIN(3, 13) | 26 | #define DA850_HAWK_MMCSD_WP_PIN GPIO_TO_PIN(3, 13) |
27 | 27 | ||
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c index 0b136a831c59..31da3c5b2ba3 100644 --- a/arch/arm/mach-davinci/board-sffsdr.c +++ b/arch/arm/mach-davinci/board-sffsdr.c | |||
@@ -42,7 +42,7 @@ | |||
42 | #include <mach/mux.h> | 42 | #include <mach/mux.h> |
43 | #include <mach/usb.h> | 43 | #include <mach/usb.h> |
44 | 44 | ||
45 | #define SFFSDR_PHY_ID "0:01" | 45 | #define SFFSDR_PHY_ID "davinci_mdio-0:01" |
46 | static struct mtd_partition davinci_sffsdr_nandflash_partition[] = { | 46 | static struct mtd_partition davinci_sffsdr_nandflash_partition[] = { |
47 | /* U-Boot Environment: Block 0 | 47 | /* U-Boot Environment: Block 0 |
48 | * UBL: Block 1 | 48 | * UBL: Block 1 |
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 0ed7fdb64efb..992c4c410185 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c | |||
@@ -153,34 +153,6 @@ static struct clk pll1_sysclk3 = { | |||
153 | .div_reg = PLLDIV3, | 153 | .div_reg = PLLDIV3, |
154 | }; | 154 | }; |
155 | 155 | ||
156 | static struct clk pll1_sysclk4 = { | ||
157 | .name = "pll1_sysclk4", | ||
158 | .parent = &pll1_clk, | ||
159 | .flags = CLK_PLL, | ||
160 | .div_reg = PLLDIV4, | ||
161 | }; | ||
162 | |||
163 | static struct clk pll1_sysclk5 = { | ||
164 | .name = "pll1_sysclk5", | ||
165 | .parent = &pll1_clk, | ||
166 | .flags = CLK_PLL, | ||
167 | .div_reg = PLLDIV5, | ||
168 | }; | ||
169 | |||
170 | static struct clk pll1_sysclk6 = { | ||
171 | .name = "pll0_sysclk6", | ||
172 | .parent = &pll0_clk, | ||
173 | .flags = CLK_PLL, | ||
174 | .div_reg = PLLDIV6, | ||
175 | }; | ||
176 | |||
177 | static struct clk pll1_sysclk7 = { | ||
178 | .name = "pll1_sysclk7", | ||
179 | .parent = &pll1_clk, | ||
180 | .flags = CLK_PLL, | ||
181 | .div_reg = PLLDIV7, | ||
182 | }; | ||
183 | |||
184 | static struct clk i2c0_clk = { | 156 | static struct clk i2c0_clk = { |
185 | .name = "i2c0", | 157 | .name = "i2c0", |
186 | .parent = &pll0_aux_clk, | 158 | .parent = &pll0_aux_clk, |
@@ -397,10 +369,6 @@ static struct clk_lookup da850_clks[] = { | |||
397 | CLK(NULL, "pll1_aux", &pll1_aux_clk), | 369 | CLK(NULL, "pll1_aux", &pll1_aux_clk), |
398 | CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), | 370 | CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), |
399 | CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), | 371 | CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), |
400 | CLK(NULL, "pll1_sysclk4", &pll1_sysclk4), | ||
401 | CLK(NULL, "pll1_sysclk5", &pll1_sysclk5), | ||
402 | CLK(NULL, "pll1_sysclk6", &pll1_sysclk6), | ||
403 | CLK(NULL, "pll1_sysclk7", &pll1_sysclk7), | ||
404 | CLK("i2c_davinci.1", NULL, &i2c0_clk), | 372 | CLK("i2c_davinci.1", NULL, &i2c0_clk), |
405 | CLK(NULL, "timer0", &timerp64_0_clk), | 373 | CLK(NULL, "timer0", &timerp64_0_clk), |
406 | CLK("watchdog", NULL, &timerp64_1_clk), | 374 | CLK("watchdog", NULL, &timerp64_1_clk), |
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index dd1429ae6405..bda7aca04ca0 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include <asm/mach/arch.h> | 28 | #include <asm/mach/arch.h> |
29 | #include <linux/irq.h> | 29 | #include <linux/irq.h> |
30 | #include <plat/time.h> | 30 | #include <plat/time.h> |
31 | #include <plat/ehci-orion.h> | ||
31 | #include <plat/common.h> | 32 | #include <plat/common.h> |
32 | #include <plat/addr-map.h> | 33 | #include <plat/addr-map.h> |
33 | #include "common.h" | 34 | #include "common.h" |
@@ -71,7 +72,7 @@ void __init dove_map_io(void) | |||
71 | ****************************************************************************/ | 72 | ****************************************************************************/ |
72 | void __init dove_ehci0_init(void) | 73 | void __init dove_ehci0_init(void) |
73 | { | 74 | { |
74 | orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0); | 75 | orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA); |
75 | } | 76 | } |
76 | 77 | ||
77 | /***************************************************************************** | 78 | /***************************************************************************** |
diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c index 03dd4012043e..d5fb44f16d31 100644 --- a/arch/arm/mach-ep93xx/vision_ep9307.c +++ b/arch/arm/mach-ep93xx/vision_ep9307.c | |||
@@ -32,6 +32,7 @@ | |||
32 | #include <mach/hardware.h> | 32 | #include <mach/hardware.h> |
33 | #include <mach/fb.h> | 33 | #include <mach/fb.h> |
34 | #include <mach/ep93xx_spi.h> | 34 | #include <mach/ep93xx_spi.h> |
35 | #include <mach/gpio-ep93xx.h> | ||
35 | 36 | ||
36 | #include <asm/mach-types.h> | 37 | #include <asm/mach-types.h> |
37 | #include <asm/mach/map.h> | 38 | #include <asm/mach/map.h> |
@@ -153,7 +154,6 @@ static struct i2c_board_info vision_i2c_info[] __initdata = { | |||
153 | }, { | 154 | }, { |
154 | I2C_BOARD_INFO("pca9539", 0x74), | 155 | I2C_BOARD_INFO("pca9539", 0x74), |
155 | .platform_data = &pca953x_74_gpio_data, | 156 | .platform_data = &pca953x_74_gpio_data, |
156 | .irq = gpio_to_irq(EP93XX_GPIO_LINE_F(7)), | ||
157 | }, { | 157 | }, { |
158 | I2C_BOARD_INFO("pca9539", 0x75), | 158 | I2C_BOARD_INFO("pca9539", 0x75), |
159 | .platform_data = &pca953x_75_gpio_data, | 159 | .platform_data = &pca953x_75_gpio_data, |
@@ -348,6 +348,8 @@ static void __init vision_init_machine(void) | |||
348 | "pca9539:74")) | 348 | "pca9539:74")) |
349 | pr_warn("cannot request interrupt gpio for pca9539:74\n"); | 349 | pr_warn("cannot request interrupt gpio for pca9539:74\n"); |
350 | 350 | ||
351 | vision_i2c_info[1].irq = gpio_to_irq(EP93XX_GPIO_LINE_F(7)); | ||
352 | |||
351 | ep93xx_register_i2c(&vision_i2c_gpio_data, vision_i2c_info, | 353 | ep93xx_register_i2c(&vision_i2c_gpio_data, vision_i2c_info, |
352 | ARRAY_SIZE(vision_i2c_info)); | 354 | ARRAY_SIZE(vision_i2c_info)); |
353 | ep93xx_register_spi(&vision_spi_master, vision_spi_board_info, | 355 | ep93xx_register_spi(&vision_spi_master, vision_spi_board_info, |
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c index a5823a7f249e..13312ccb2d93 100644 --- a/arch/arm/mach-exynos/clock-exynos4210.c +++ b/arch/arm/mach-exynos/clock-exynos4210.c | |||
@@ -32,6 +32,7 @@ | |||
32 | 32 | ||
33 | #include "common.h" | 33 | #include "common.h" |
34 | 34 | ||
35 | #ifdef CONFIG_PM_SLEEP | ||
35 | static struct sleep_save exynos4210_clock_save[] = { | 36 | static struct sleep_save exynos4210_clock_save[] = { |
36 | SAVE_ITEM(S5P_CLKSRC_IMAGE), | 37 | SAVE_ITEM(S5P_CLKSRC_IMAGE), |
37 | SAVE_ITEM(S5P_CLKSRC_LCD1), | 38 | SAVE_ITEM(S5P_CLKSRC_LCD1), |
@@ -42,6 +43,7 @@ static struct sleep_save exynos4210_clock_save[] = { | |||
42 | SAVE_ITEM(S5P_CLKGATE_IP_LCD1), | 43 | SAVE_ITEM(S5P_CLKGATE_IP_LCD1), |
43 | SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210), | 44 | SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210), |
44 | }; | 45 | }; |
46 | #endif | ||
45 | 47 | ||
46 | static struct clksrc_clk *sysclks[] = { | 48 | static struct clksrc_clk *sysclks[] = { |
47 | /* nothing here yet */ | 49 | /* nothing here yet */ |
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c index 26a668b0d101..48af28566fa1 100644 --- a/arch/arm/mach-exynos/clock-exynos4212.c +++ b/arch/arm/mach-exynos/clock-exynos4212.c | |||
@@ -32,12 +32,14 @@ | |||
32 | 32 | ||
33 | #include "common.h" | 33 | #include "common.h" |
34 | 34 | ||
35 | #ifdef CONFIG_PM_SLEEP | ||
35 | static struct sleep_save exynos4212_clock_save[] = { | 36 | static struct sleep_save exynos4212_clock_save[] = { |
36 | SAVE_ITEM(S5P_CLKSRC_IMAGE), | 37 | SAVE_ITEM(S5P_CLKSRC_IMAGE), |
37 | SAVE_ITEM(S5P_CLKDIV_IMAGE), | 38 | SAVE_ITEM(S5P_CLKDIV_IMAGE), |
38 | SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212), | 39 | SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212), |
39 | SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212), | 40 | SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212), |
40 | }; | 41 | }; |
42 | #endif | ||
41 | 43 | ||
42 | static struct clk *clk_src_mpll_user_list[] = { | 44 | static struct clk *clk_src_mpll_user_list[] = { |
43 | [0] = &clk_fin_mpll, | 45 | [0] = &clk_fin_mpll, |
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c index 5a8c42e90005..187287aa57ab 100644 --- a/arch/arm/mach-exynos/clock.c +++ b/arch/arm/mach-exynos/clock.c | |||
@@ -30,6 +30,7 @@ | |||
30 | 30 | ||
31 | #include "common.h" | 31 | #include "common.h" |
32 | 32 | ||
33 | #ifdef CONFIG_PM_SLEEP | ||
33 | static struct sleep_save exynos4_clock_save[] = { | 34 | static struct sleep_save exynos4_clock_save[] = { |
34 | SAVE_ITEM(S5P_CLKDIV_LEFTBUS), | 35 | SAVE_ITEM(S5P_CLKDIV_LEFTBUS), |
35 | SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS), | 36 | SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS), |
@@ -93,6 +94,7 @@ static struct sleep_save exynos4_clock_save[] = { | |||
93 | SAVE_ITEM(S5P_CLKGATE_SCLKCPU), | 94 | SAVE_ITEM(S5P_CLKGATE_SCLKCPU), |
94 | SAVE_ITEM(S5P_CLKGATE_IP_CPU), | 95 | SAVE_ITEM(S5P_CLKGATE_IP_CPU), |
95 | }; | 96 | }; |
97 | #endif | ||
96 | 98 | ||
97 | struct clk clk_sclk_hdmi27m = { | 99 | struct clk clk_sclk_hdmi27m = { |
98 | .name = "sclk_hdmi27m", | 100 | .name = "sclk_hdmi27m", |
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c index da70e7e39937..dd1ad55524c9 100644 --- a/arch/arm/mach-exynos/hotplug.c +++ b/arch/arm/mach-exynos/hotplug.c | |||
@@ -16,6 +16,7 @@ | |||
16 | #include <linux/io.h> | 16 | #include <linux/io.h> |
17 | 17 | ||
18 | #include <asm/cacheflush.h> | 18 | #include <asm/cacheflush.h> |
19 | #include <asm/smp_plat.h> | ||
19 | 20 | ||
20 | #include <mach/regs-pmu.h> | 21 | #include <mach/regs-pmu.h> |
21 | 22 | ||
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c index 85fa02767d67..e6b02fdf1b09 100644 --- a/arch/arm/mach-exynos/mach-exynos4-dt.c +++ b/arch/arm/mach-exynos/mach-exynos4-dt.c | |||
@@ -15,11 +15,13 @@ | |||
15 | #include <linux/serial_core.h> | 15 | #include <linux/serial_core.h> |
16 | 16 | ||
17 | #include <asm/mach/arch.h> | 17 | #include <asm/mach/arch.h> |
18 | #include <asm/hardware/gic.h> | ||
18 | #include <mach/map.h> | 19 | #include <mach/map.h> |
19 | 20 | ||
20 | #include <plat/cpu.h> | 21 | #include <plat/cpu.h> |
21 | #include <plat/regs-serial.h> | 22 | #include <plat/regs-serial.h> |
22 | #include <plat/exynos4.h> | 23 | |
24 | #include "common.h" | ||
23 | 25 | ||
24 | /* | 26 | /* |
25 | * The following lookup table is used to override device names when devices | 27 | * The following lookup table is used to override device names when devices |
@@ -60,7 +62,7 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = { | |||
60 | 62 | ||
61 | static void __init exynos4210_dt_map_io(void) | 63 | static void __init exynos4210_dt_map_io(void) |
62 | { | 64 | { |
63 | s5p_init_io(NULL, 0, S5P_VA_CHIPID); | 65 | exynos_init_io(NULL, 0); |
64 | s3c24xx_init_clocks(24000000); | 66 | s3c24xx_init_clocks(24000000); |
65 | } | 67 | } |
66 | 68 | ||
@@ -79,7 +81,9 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)") | |||
79 | /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */ | 81 | /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */ |
80 | .init_irq = exynos4_init_irq, | 82 | .init_irq = exynos4_init_irq, |
81 | .map_io = exynos4210_dt_map_io, | 83 | .map_io = exynos4210_dt_map_io, |
84 | .handle_irq = gic_handle_irq, | ||
82 | .init_machine = exynos4210_dt_machine_init, | 85 | .init_machine = exynos4210_dt_machine_init, |
83 | .timer = &exynos4_timer, | 86 | .timer = &exynos4_timer, |
84 | .dt_compat = exynos4210_dt_compat, | 87 | .dt_compat = exynos4210_dt_compat, |
88 | .restart = exynos4_restart, | ||
85 | MACHINE_END | 89 | MACHINE_END |
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c index b895ec031105..435261f83f46 100644 --- a/arch/arm/mach-exynos/mach-nuri.c +++ b/arch/arm/mach-exynos/mach-nuri.c | |||
@@ -220,14 +220,14 @@ static struct s3c_fb_pd_win nuri_fb_win0 = { | |||
220 | .lower_margin = 1, | 220 | .lower_margin = 1, |
221 | .hsync_len = 48, | 221 | .hsync_len = 48, |
222 | .vsync_len = 3, | 222 | .vsync_len = 3, |
223 | .xres = 1280, | 223 | .xres = 1024, |
224 | .yres = 800, | 224 | .yres = 600, |
225 | .refresh = 60, | 225 | .refresh = 60, |
226 | }, | 226 | }, |
227 | .max_bpp = 24, | 227 | .max_bpp = 24, |
228 | .default_bpp = 16, | 228 | .default_bpp = 16, |
229 | .virtual_x = 1280, | 229 | .virtual_x = 1024, |
230 | .virtual_y = 800, | 230 | .virtual_y = 2 * 600, |
231 | }; | 231 | }; |
232 | 232 | ||
233 | static struct s3c_fb_platdata nuri_fb_pdata __initdata = { | 233 | static struct s3c_fb_platdata nuri_fb_pdata __initdata = { |
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c index 37ac93e8d6d9..0fc65ffde8ff 100644 --- a/arch/arm/mach-exynos/mach-universal_c210.c +++ b/arch/arm/mach-exynos/mach-universal_c210.c | |||
@@ -910,7 +910,7 @@ static struct s5p_fimc_isp_info universal_camera_sensors[] = { | |||
910 | .bus_type = FIMC_MIPI_CSI2, | 910 | .bus_type = FIMC_MIPI_CSI2, |
911 | .board_info = &m5mols_board_info, | 911 | .board_info = &m5mols_board_info, |
912 | .i2c_bus_num = 0, | 912 | .i2c_bus_num = 0, |
913 | .clk_frequency = 21600000UL, | 913 | .clk_frequency = 24000000UL, |
914 | .csi_data_align = 32, | 914 | .csi_data_align = 32, |
915 | }, | 915 | }, |
916 | }; | 916 | }; |
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 683aec786b78..0f2035a1eb6e 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c | |||
@@ -23,6 +23,7 @@ | |||
23 | 23 | ||
24 | #include <asm/cacheflush.h> | 24 | #include <asm/cacheflush.h> |
25 | #include <asm/hardware/gic.h> | 25 | #include <asm/hardware/gic.h> |
26 | #include <asm/smp_plat.h> | ||
26 | #include <asm/smp_scu.h> | 27 | #include <asm/smp_scu.h> |
27 | 28 | ||
28 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index a4f61a43c7ba..e19013051772 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c | |||
@@ -206,7 +206,7 @@ static void exynos4_pm_prepare(void) | |||
206 | 206 | ||
207 | } | 207 | } |
208 | 208 | ||
209 | static int exynos4_pm_add(struct device *dev) | 209 | static int exynos4_pm_add(struct device *dev, struct subsys_interface *sif) |
210 | { | 210 | { |
211 | pm_cpu_prep = exynos4_pm_prepare; | 211 | pm_cpu_prep = exynos4_pm_prepare; |
212 | pm_cpu_sleep = exynos4_cpu_suspend; | 212 | pm_cpu_sleep = exynos4_cpu_suspend; |
@@ -384,7 +384,9 @@ static void exynos4_pm_resume(void) | |||
384 | 384 | ||
385 | exynos4_restore_pll(); | 385 | exynos4_restore_pll(); |
386 | 386 | ||
387 | #ifdef CONFIG_SMP | ||
387 | scu_enable(S5P_VA_SCU); | 388 | scu_enable(S5P_VA_SCU); |
389 | #endif | ||
388 | 390 | ||
389 | #ifdef CONFIG_CACHE_L2X0 | 391 | #ifdef CONFIG_CACHE_L2X0 |
390 | s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); | 392 | s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); |
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c index 7afbe1e55beb..8394d512a402 100644 --- a/arch/arm/mach-highbank/highbank.c +++ b/arch/arm/mach-highbank/highbank.c | |||
@@ -25,6 +25,7 @@ | |||
25 | #include <linux/smp.h> | 25 | #include <linux/smp.h> |
26 | 26 | ||
27 | #include <asm/cacheflush.h> | 27 | #include <asm/cacheflush.h> |
28 | #include <asm/smp_plat.h> | ||
28 | #include <asm/smp_scu.h> | 29 | #include <asm/smp_scu.h> |
29 | #include <asm/hardware/arm_timer.h> | 30 | #include <asm/hardware/arm_timer.h> |
30 | #include <asm/hardware/timer-sp.h> | 31 | #include <asm/hardware/timer-sp.h> |
@@ -72,9 +73,7 @@ static void __init highbank_map_io(void) | |||
72 | 73 | ||
73 | void highbank_set_cpu_jump(int cpu, void *jump_addr) | 74 | void highbank_set_cpu_jump(int cpu, void *jump_addr) |
74 | { | 75 | { |
75 | #ifdef CONFIG_SMP | ||
76 | cpu = cpu_logical_map(cpu); | 76 | cpu = cpu_logical_map(cpu); |
77 | #endif | ||
78 | writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu)); | 77 | writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu)); |
79 | __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16); | 78 | __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16); |
80 | outer_clean_range(HB_JUMP_TABLE_PHYS(cpu), | 79 | outer_clean_range(HB_JUMP_TABLE_PHYS(cpu), |
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 0e6de366c648..4defb97bbfc8 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig | |||
@@ -22,6 +22,18 @@ config ARCH_MX25 | |||
22 | config MACH_MX27 | 22 | config MACH_MX27 |
23 | bool | 23 | bool |
24 | 24 | ||
25 | config ARCH_MX5 | ||
26 | bool | ||
27 | |||
28 | config ARCH_MX50 | ||
29 | bool | ||
30 | |||
31 | config ARCH_MX51 | ||
32 | bool | ||
33 | |||
34 | config ARCH_MX53 | ||
35 | bool | ||
36 | |||
25 | config SOC_IMX1 | 37 | config SOC_IMX1 |
26 | bool | 38 | bool |
27 | select ARCH_MX1 | 39 | select ARCH_MX1 |
@@ -73,6 +85,31 @@ config SOC_IMX35 | |||
73 | select MXC_AVIC | 85 | select MXC_AVIC |
74 | select SMP_ON_UP if SMP | 86 | select SMP_ON_UP if SMP |
75 | 87 | ||
88 | config SOC_IMX5 | ||
89 | select CPU_V7 | ||
90 | select MXC_TZIC | ||
91 | select ARCH_MXC_IOMUX_V3 | ||
92 | select ARCH_MXC_AUDMUX_V2 | ||
93 | select ARCH_HAS_CPUFREQ | ||
94 | select ARCH_MX5 | ||
95 | bool | ||
96 | |||
97 | config SOC_IMX50 | ||
98 | bool | ||
99 | select SOC_IMX5 | ||
100 | select ARCH_MX50 | ||
101 | |||
102 | config SOC_IMX51 | ||
103 | bool | ||
104 | select SOC_IMX5 | ||
105 | select ARCH_MX5 | ||
106 | select ARCH_MX51 | ||
107 | |||
108 | config SOC_IMX53 | ||
109 | bool | ||
110 | select SOC_IMX5 | ||
111 | select ARCH_MX5 | ||
112 | select ARCH_MX53 | ||
76 | 113 | ||
77 | if ARCH_IMX_V4_V5 | 114 | if ARCH_IMX_V4_V5 |
78 | 115 | ||
@@ -592,6 +629,207 @@ config MACH_VPR200 | |||
592 | Include support for VPR200 platform. This includes specific | 629 | Include support for VPR200 platform. This includes specific |
593 | configurations for the board and its peripherals. | 630 | configurations for the board and its peripherals. |
594 | 631 | ||
632 | comment "i.MX5 platforms:" | ||
633 | |||
634 | config MACH_MX50_RDP | ||
635 | bool "Support MX50 reference design platform" | ||
636 | depends on BROKEN | ||
637 | select SOC_IMX50 | ||
638 | select IMX_HAVE_PLATFORM_IMX_I2C | ||
639 | select IMX_HAVE_PLATFORM_IMX_UART | ||
640 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
641 | select IMX_HAVE_PLATFORM_SPI_IMX | ||
642 | help | ||
643 | Include support for MX50 reference design platform (RDP) board. This | ||
644 | includes specific configurations for the board and its peripherals. | ||
645 | |||
646 | comment "i.MX51 machines:" | ||
647 | |||
648 | config MACH_IMX51_DT | ||
649 | bool "Support i.MX51 platforms from device tree" | ||
650 | select SOC_IMX51 | ||
651 | select USE_OF | ||
652 | select MACH_MX51_BABBAGE | ||
653 | help | ||
654 | Include support for Freescale i.MX51 based platforms | ||
655 | using the device tree for discovery | ||
656 | |||
657 | config MACH_MX51_BABBAGE | ||
658 | bool "Support MX51 BABBAGE platforms" | ||
659 | select SOC_IMX51 | ||
660 | select IMX_HAVE_PLATFORM_FSL_USB2_UDC | ||
661 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
662 | select IMX_HAVE_PLATFORM_IMX_I2C | ||
663 | select IMX_HAVE_PLATFORM_IMX_UART | ||
664 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
665 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
666 | select IMX_HAVE_PLATFORM_SPI_IMX | ||
667 | help | ||
668 | Include support for MX51 Babbage platform, also known as MX51EVK in | ||
669 | u-boot. This includes specific configurations for the board and its | ||
670 | peripherals. | ||
671 | |||
672 | config MACH_MX51_3DS | ||
673 | bool "Support MX51PDK (3DS)" | ||
674 | select SOC_IMX51 | ||
675 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
676 | select IMX_HAVE_PLATFORM_IMX_KEYPAD | ||
677 | select IMX_HAVE_PLATFORM_IMX_UART | ||
678 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
679 | select IMX_HAVE_PLATFORM_SPI_IMX | ||
680 | select MXC_DEBUG_BOARD | ||
681 | help | ||
682 | Include support for MX51PDK (3DS) platform. This includes specific | ||
683 | configurations for the board and its peripherals. | ||
684 | |||
685 | config MACH_EUKREA_CPUIMX51 | ||
686 | bool "Support Eukrea CPUIMX51 module" | ||
687 | select SOC_IMX51 | ||
688 | select IMX_HAVE_PLATFORM_FSL_USB2_UDC | ||
689 | select IMX_HAVE_PLATFORM_IMX_I2C | ||
690 | select IMX_HAVE_PLATFORM_IMX_UART | ||
691 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
692 | select IMX_HAVE_PLATFORM_MXC_NAND | ||
693 | select IMX_HAVE_PLATFORM_SPI_IMX | ||
694 | help | ||
695 | Include support for Eukrea CPUIMX51 platform. This includes | ||
696 | specific configurations for the module and its peripherals. | ||
697 | |||
698 | choice | ||
699 | prompt "Baseboard" | ||
700 | depends on MACH_EUKREA_CPUIMX51 | ||
701 | default MACH_EUKREA_MBIMX51_BASEBOARD | ||
702 | |||
703 | config MACH_EUKREA_MBIMX51_BASEBOARD | ||
704 | prompt "Eukrea MBIMX51 development board" | ||
705 | bool | ||
706 | select IMX_HAVE_PLATFORM_IMX_KEYPAD | ||
707 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
708 | select LEDS_GPIO_REGISTER | ||
709 | help | ||
710 | This adds board specific devices that can be found on Eukrea's | ||
711 | MBIMX51 evaluation board. | ||
712 | |||
713 | endchoice | ||
714 | |||
715 | config MACH_EUKREA_CPUIMX51SD | ||
716 | bool "Support Eukrea CPUIMX51SD module" | ||
717 | select SOC_IMX51 | ||
718 | select IMX_HAVE_PLATFORM_FSL_USB2_UDC | ||
719 | select IMX_HAVE_PLATFORM_IMX_I2C | ||
720 | select IMX_HAVE_PLATFORM_IMX_UART | ||
721 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
722 | select IMX_HAVE_PLATFORM_MXC_NAND | ||
723 | select IMX_HAVE_PLATFORM_SPI_IMX | ||
724 | help | ||
725 | Include support for Eukrea CPUIMX51SD platform. This includes | ||
726 | specific configurations for the module and its peripherals. | ||
727 | |||
728 | choice | ||
729 | prompt "Baseboard" | ||
730 | depends on MACH_EUKREA_CPUIMX51SD | ||
731 | default MACH_EUKREA_MBIMXSD51_BASEBOARD | ||
732 | |||
733 | config MACH_EUKREA_MBIMXSD51_BASEBOARD | ||
734 | prompt "Eukrea MBIMXSD development board" | ||
735 | bool | ||
736 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
737 | select LEDS_GPIO_REGISTER | ||
738 | help | ||
739 | This adds board specific devices that can be found on Eukrea's | ||
740 | MBIMXSD evaluation board. | ||
741 | |||
742 | endchoice | ||
743 | |||
744 | config MX51_EFIKA_COMMON | ||
745 | bool | ||
746 | select SOC_IMX51 | ||
747 | select IMX_HAVE_PLATFORM_IMX_UART | ||
748 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
749 | select IMX_HAVE_PLATFORM_PATA_IMX | ||
750 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
751 | select IMX_HAVE_PLATFORM_SPI_IMX | ||
752 | select MXC_ULPI if USB_ULPI | ||
753 | |||
754 | config MACH_MX51_EFIKAMX | ||
755 | bool "Support MX51 Genesi Efika MX nettop" | ||
756 | select LEDS_GPIO_REGISTER | ||
757 | select MX51_EFIKA_COMMON | ||
758 | help | ||
759 | Include support for Genesi Efika MX nettop. This includes specific | ||
760 | configurations for the board and its peripherals. | ||
761 | |||
762 | config MACH_MX51_EFIKASB | ||
763 | bool "Support MX51 Genesi Efika Smartbook" | ||
764 | select LEDS_GPIO_REGISTER | ||
765 | select MX51_EFIKA_COMMON | ||
766 | help | ||
767 | Include support for Genesi Efika Smartbook. This includes specific | ||
768 | configurations for the board and its peripherals. | ||
769 | |||
770 | comment "i.MX53 machines:" | ||
771 | |||
772 | config MACH_IMX53_DT | ||
773 | bool "Support i.MX53 platforms from device tree" | ||
774 | select SOC_IMX53 | ||
775 | select USE_OF | ||
776 | select MACH_MX53_ARD | ||
777 | select MACH_MX53_EVK | ||
778 | select MACH_MX53_LOCO | ||
779 | select MACH_MX53_SMD | ||
780 | help | ||
781 | Include support for Freescale i.MX53 based platforms | ||
782 | using the device tree for discovery | ||
783 | |||
784 | config MACH_MX53_EVK | ||
785 | bool "Support MX53 EVK platforms" | ||
786 | select SOC_IMX53 | ||
787 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
788 | select IMX_HAVE_PLATFORM_IMX_UART | ||
789 | select IMX_HAVE_PLATFORM_IMX_I2C | ||
790 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
791 | select IMX_HAVE_PLATFORM_SPI_IMX | ||
792 | select LEDS_GPIO_REGISTER | ||
793 | help | ||
794 | Include support for MX53 EVK platform. This includes specific | ||
795 | configurations for the board and its peripherals. | ||
796 | |||
797 | config MACH_MX53_SMD | ||
798 | bool "Support MX53 SMD platforms" | ||
799 | select SOC_IMX53 | ||
800 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
801 | select IMX_HAVE_PLATFORM_IMX_I2C | ||
802 | select IMX_HAVE_PLATFORM_IMX_UART | ||
803 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
804 | help | ||
805 | Include support for MX53 SMD platform. This includes specific | ||
806 | configurations for the board and its peripherals. | ||
807 | |||
808 | config MACH_MX53_LOCO | ||
809 | bool "Support MX53 LOCO platforms" | ||
810 | select SOC_IMX53 | ||
811 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
812 | select IMX_HAVE_PLATFORM_IMX_I2C | ||
813 | select IMX_HAVE_PLATFORM_IMX_UART | ||
814 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
815 | select IMX_HAVE_PLATFORM_GPIO_KEYS | ||
816 | select LEDS_GPIO_REGISTER | ||
817 | help | ||
818 | Include support for MX53 LOCO platform. This includes specific | ||
819 | configurations for the board and its peripherals. | ||
820 | |||
821 | config MACH_MX53_ARD | ||
822 | bool "Support MX53 ARD platforms" | ||
823 | select SOC_IMX53 | ||
824 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
825 | select IMX_HAVE_PLATFORM_IMX_I2C | ||
826 | select IMX_HAVE_PLATFORM_IMX_UART | ||
827 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
828 | select IMX_HAVE_PLATFORM_GPIO_KEYS | ||
829 | help | ||
830 | Include support for MX53 ARD platform. This includes specific | ||
831 | configurations for the board and its peripherals. | ||
832 | |||
595 | comment "i.MX6 family:" | 833 | comment "i.MX6 family:" |
596 | 834 | ||
597 | config SOC_IMX6Q | 835 | config SOC_IMX6Q |
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index f5920c24f7d7..55db9c488f2b 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile | |||
@@ -11,6 +11,8 @@ obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o | |||
11 | obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o | 11 | obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o |
12 | obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o | 12 | obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o |
13 | 13 | ||
14 | obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clock-mx51-mx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o | ||
15 | |||
14 | # Support for CMOS sensor interface | 16 | # Support for CMOS sensor interface |
15 | obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o | 17 | obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o |
16 | 18 | ||
@@ -75,3 +77,22 @@ obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o | |||
75 | ifeq ($(CONFIG_PM),y) | 77 | ifeq ($(CONFIG_PM),y) |
76 | obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o | 78 | obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o |
77 | endif | 79 | endif |
80 | |||
81 | # i.MX5 based machines | ||
82 | obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o | ||
83 | obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o | ||
84 | obj-$(CONFIG_MACH_MX53_EVK) += mach-mx53_evk.o | ||
85 | obj-$(CONFIG_MACH_MX53_SMD) += mach-mx53_smd.o | ||
86 | obj-$(CONFIG_MACH_MX53_LOCO) += mach-mx53_loco.o | ||
87 | obj-$(CONFIG_MACH_MX53_ARD) += mach-mx53_ard.o | ||
88 | obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += mach-cpuimx51.o | ||
89 | obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o | ||
90 | obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o | ||
91 | obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o | ||
92 | obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o | ||
93 | obj-$(CONFIG_MACH_MX51_EFIKAMX) += mach-mx51_efikamx.o | ||
94 | obj-$(CONFIG_MACH_MX51_EFIKASB) += mach-mx51_efikasb.o | ||
95 | obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o | ||
96 | |||
97 | obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o | ||
98 | obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o | ||
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot index 5f4d06af4912..6dfdbcc83afd 100644 --- a/arch/arm/mach-imx/Makefile.boot +++ b/arch/arm/mach-imx/Makefile.boot | |||
@@ -22,6 +22,18 @@ zreladdr-$(CONFIG_SOC_IMX35) += 0x80008000 | |||
22 | params_phys-$(CONFIG_SOC_IMX35) := 0x80000100 | 22 | params_phys-$(CONFIG_SOC_IMX35) := 0x80000100 |
23 | initrd_phys-$(CONFIG_SOC_IMX35) := 0x80800000 | 23 | initrd_phys-$(CONFIG_SOC_IMX35) := 0x80800000 |
24 | 24 | ||
25 | zreladdr-$(CONFIG_SOC_IMX50) += 0x70008000 | ||
26 | params_phys-$(CONFIG_SOC_IMX50) := 0x70000100 | ||
27 | initrd_phys-$(CONFIG_SOC_IMX50) := 0x70800000 | ||
28 | |||
29 | zreladdr-$(CONFIG_SOC_IMX51) += 0x90008000 | ||
30 | params_phys-$(CONFIG_SOC_IMX51) := 0x90000100 | ||
31 | initrd_phys-$(CONFIG_SOC_IMX51) := 0x90800000 | ||
32 | |||
33 | zreladdr-$(CONFIG_SOC_IMX53) += 0x70008000 | ||
34 | params_phys-$(CONFIG_SOC_IMX53) := 0x70000100 | ||
35 | initrd_phys-$(CONFIG_SOC_IMX53) := 0x70800000 | ||
36 | |||
25 | zreladdr-$(CONFIG_SOC_IMX6Q) += 0x10008000 | 37 | zreladdr-$(CONFIG_SOC_IMX6Q) += 0x10008000 |
26 | params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100 | 38 | params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100 |
27 | initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000 | 39 | initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000 |
diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c index 9273c2a24b54..2d88f8b9a454 100644 --- a/arch/arm/mach-imx/clock-imx6q.c +++ b/arch/arm/mach-imx/clock-imx6q.c | |||
@@ -814,6 +814,16 @@ DEF_PFD(pll3_pfd_540m, PFD_480, PFD1, &pll3_usb_otg); | |||
814 | DEF_PFD(pll3_pfd_508m, PFD_480, PFD2, &pll3_usb_otg); | 814 | DEF_PFD(pll3_pfd_508m, PFD_480, PFD2, &pll3_usb_otg); |
815 | DEF_PFD(pll3_pfd_454m, PFD_480, PFD3, &pll3_usb_otg); | 815 | DEF_PFD(pll3_pfd_454m, PFD_480, PFD3, &pll3_usb_otg); |
816 | 816 | ||
817 | static unsigned long twd_clk_get_rate(struct clk *clk) | ||
818 | { | ||
819 | return clk_get_rate(clk->parent) / 2; | ||
820 | } | ||
821 | |||
822 | static struct clk twd_clk = { | ||
823 | .parent = &arm_clk, | ||
824 | .get_rate = twd_clk_get_rate, | ||
825 | }; | ||
826 | |||
817 | static unsigned long pll2_200m_get_rate(struct clk *clk) | 827 | static unsigned long pll2_200m_get_rate(struct clk *clk) |
818 | { | 828 | { |
819 | return clk_get_rate(clk->parent) / 2; | 829 | return clk_get_rate(clk->parent) / 2; |
@@ -1894,6 +1904,7 @@ static struct clk_lookup lookups[] = { | |||
1894 | _REGISTER_CLOCK("20ec000.sdma", NULL, sdma_clk), | 1904 | _REGISTER_CLOCK("20ec000.sdma", NULL, sdma_clk), |
1895 | _REGISTER_CLOCK("20bc000.wdog", NULL, dummy_clk), | 1905 | _REGISTER_CLOCK("20bc000.wdog", NULL, dummy_clk), |
1896 | _REGISTER_CLOCK("20c0000.wdog", NULL, dummy_clk), | 1906 | _REGISTER_CLOCK("20c0000.wdog", NULL, dummy_clk), |
1907 | _REGISTER_CLOCK("smp_twd", NULL, twd_clk), | ||
1897 | _REGISTER_CLOCK(NULL, "ckih", ckih_clk), | 1908 | _REGISTER_CLOCK(NULL, "ckih", ckih_clk), |
1898 | _REGISTER_CLOCK(NULL, "ckil_clk", ckil_clk), | 1909 | _REGISTER_CLOCK(NULL, "ckil_clk", ckil_clk), |
1899 | _REGISTER_CLOCK(NULL, "aips_tz1_clk", aips_tz1_clk), | 1910 | _REGISTER_CLOCK(NULL, "aips_tz1_clk", aips_tz1_clk), |
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-imx/clock-mx51-mx53.c index 4cb276977190..08470504a088 100644 --- a/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/arch/arm/mach-imx/clock-mx51-mx53.c | |||
@@ -23,7 +23,7 @@ | |||
23 | #include <mach/common.h> | 23 | #include <mach/common.h> |
24 | #include <mach/clock.h> | 24 | #include <mach/clock.h> |
25 | 25 | ||
26 | #include "crm_regs.h" | 26 | #include "crm-regs-imx5.h" |
27 | 27 | ||
28 | /* External clock values passed-in by the board code */ | 28 | /* External clock values passed-in by the board code */ |
29 | static unsigned long external_high_reference, external_low_reference; | 29 | static unsigned long external_high_reference, external_low_reference; |
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-imx/cpu-imx5.c index 5e2e7a843860..5e2e7a843860 100644 --- a/arch/arm/mach-mx5/cpu.c +++ b/arch/arm/mach-imx/cpu-imx5.c | |||
diff --git a/arch/arm/mach-mx5/cpu_op-mx51.c b/arch/arm/mach-imx/cpu_op-mx51.c index 9d34c3d4c024..9d34c3d4c024 100644 --- a/arch/arm/mach-mx5/cpu_op-mx51.c +++ b/arch/arm/mach-imx/cpu_op-mx51.c | |||
diff --git a/arch/arm/mach-mx5/cpu_op-mx51.h b/arch/arm/mach-imx/cpu_op-mx51.h index 97477fecb469..97477fecb469 100644 --- a/arch/arm/mach-mx5/cpu_op-mx51.h +++ b/arch/arm/mach-imx/cpu_op-mx51.h | |||
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-imx/crm-regs-imx5.h index 5e11ba7daee2..5e11ba7daee2 100644 --- a/arch/arm/mach-mx5/crm_regs.h +++ b/arch/arm/mach-imx/crm-regs-imx5.h | |||
diff --git a/arch/arm/mach-mx5/devices-imx50.h b/arch/arm/mach-imx/devices-imx50.h index 7216667eaafc..7216667eaafc 100644 --- a/arch/arm/mach-mx5/devices-imx50.h +++ b/arch/arm/mach-imx/devices-imx50.h | |||
diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-imx/devices-imx51.h index af488bc0e225..af488bc0e225 100644 --- a/arch/arm/mach-mx5/devices-imx51.h +++ b/arch/arm/mach-imx/devices-imx51.h | |||
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-imx/devices-imx53.h index 6e1e5d1f8c3a..6e1e5d1f8c3a 100644 --- a/arch/arm/mach-mx5/devices-imx53.h +++ b/arch/arm/mach-imx/devices-imx53.h | |||
diff --git a/arch/arm/mach-mx5/efika.h b/arch/arm/mach-imx/efika.h index 014aa985faae..014aa985faae 100644 --- a/arch/arm/mach-mx5/efika.h +++ b/arch/arm/mach-imx/efika.h | |||
diff --git a/arch/arm/mach-mx5/ehci.c b/arch/arm/mach-imx/ehci-imx5.c index c17fa131728b..c17fa131728b 100644 --- a/arch/arm/mach-mx5/ehci.c +++ b/arch/arm/mach-imx/ehci-imx5.c | |||
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx51-baseboard.c index a6a3ab8f1b1c..a6a3ab8f1b1c 100644 --- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimx51-baseboard.c | |||
diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c index d817fc80b986..d817fc80b986 100644 --- a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c | |||
diff --git a/arch/arm/mach-mx5/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c index e6bad17b908c..e6bad17b908c 100644 --- a/arch/arm/mach-mx5/imx51-dt.c +++ b/arch/arm/mach-imx/imx51-dt.c | |||
diff --git a/arch/arm/mach-mx5/imx53-dt.c b/arch/arm/mach-imx/imx53-dt.c index 05ebb3e68679..05ebb3e68679 100644 --- a/arch/arm/mach-mx5/imx53-dt.c +++ b/arch/arm/mach-imx/imx53-dt.c | |||
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-imx/mach-cpuimx51.c index 944025da8333..944025da8333 100644 --- a/arch/arm/mach-mx5/board-cpuimx51.c +++ b/arch/arm/mach-imx/mach-cpuimx51.c | |||
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-imx/mach-cpuimx51sd.c index 9fbe923c8b08..9fbe923c8b08 100644 --- a/arch/arm/mach-mx5/board-cpuimx51sd.c +++ b/arch/arm/mach-imx/mach-cpuimx51sd.c | |||
diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-imx/mach-mx50_rdp.c index 42b66e8d9615..42b66e8d9615 100644 --- a/arch/arm/mach-mx5/board-mx50_rdp.c +++ b/arch/arm/mach-imx/mach-mx50_rdp.c | |||
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-imx/mach-mx51_3ds.c index 83eab4176ca4..83eab4176ca4 100644 --- a/arch/arm/mach-mx5/board-mx51_3ds.c +++ b/arch/arm/mach-imx/mach-mx51_3ds.c | |||
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c index e4b822e9f719..e4b822e9f719 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-imx/mach-mx51_babbage.c | |||
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-imx/mach-mx51_efikamx.c index 3a5ed2dd885a..3a5ed2dd885a 100644 --- a/arch/arm/mach-mx5/board-mx51_efikamx.c +++ b/arch/arm/mach-imx/mach-mx51_efikamx.c | |||
diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-imx/mach-mx51_efikasb.c index ea5f65b0381a..ea5f65b0381a 100644 --- a/arch/arm/mach-mx5/board-mx51_efikasb.c +++ b/arch/arm/mach-imx/mach-mx51_efikasb.c | |||
diff --git a/arch/arm/mach-mx5/board-mx53_ard.c b/arch/arm/mach-imx/mach-mx53_ard.c index 5f224f1c3eb6..753f4fc9ec04 100644 --- a/arch/arm/mach-mx5/board-mx53_ard.c +++ b/arch/arm/mach-imx/mach-mx53_ard.c | |||
@@ -32,7 +32,6 @@ | |||
32 | #include <asm/mach/arch.h> | 32 | #include <asm/mach/arch.h> |
33 | #include <asm/mach/time.h> | 33 | #include <asm/mach/time.h> |
34 | 34 | ||
35 | #include "crm_regs.h" | ||
36 | #include "devices-imx53.h" | 35 | #include "devices-imx53.h" |
37 | 36 | ||
38 | #define ARD_ETHERNET_INT_B IMX_GPIO_NR(2, 31) | 37 | #define ARD_ETHERNET_INT_B IMX_GPIO_NR(2, 31) |
@@ -189,8 +188,10 @@ static int weim_cs_config(void) | |||
189 | return -ENOMEM; | 188 | return -ENOMEM; |
190 | 189 | ||
191 | iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K); | 190 | iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K); |
192 | if (!iomuxc_base) | 191 | if (!iomuxc_base) { |
192 | iounmap(weim_base); | ||
193 | return -ENOMEM; | 193 | return -ENOMEM; |
194 | } | ||
194 | 195 | ||
195 | /* CS1 timings for LAN9220 */ | 196 | /* CS1 timings for LAN9220 */ |
196 | writel(0x20001, (weim_base + 0x18)); | 197 | writel(0x20001, (weim_base + 0x18)); |
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-imx/mach-mx53_evk.c index d6ce137896d6..5a72188b9cdb 100644 --- a/arch/arm/mach-mx5/board-mx53_evk.c +++ b/arch/arm/mach-imx/mach-mx53_evk.c | |||
@@ -37,7 +37,6 @@ | |||
37 | #define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19) | 37 | #define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19) |
38 | #define MX53EVK_LED IMX_GPIO_NR(7, 7) | 38 | #define MX53EVK_LED IMX_GPIO_NR(7, 7) |
39 | 39 | ||
40 | #include "crm_regs.h" | ||
41 | #include "devices-imx53.h" | 40 | #include "devices-imx53.h" |
42 | 41 | ||
43 | static iomux_v3_cfg_t mx53_evk_pads[] = { | 42 | static iomux_v3_cfg_t mx53_evk_pads[] = { |
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-imx/mach-mx53_loco.c index fd8b524e1c58..37f67cac15a4 100644 --- a/arch/arm/mach-mx5/board-mx53_loco.c +++ b/arch/arm/mach-imx/mach-mx53_loco.c | |||
@@ -32,7 +32,6 @@ | |||
32 | #include <asm/mach/arch.h> | 32 | #include <asm/mach/arch.h> |
33 | #include <asm/mach/time.h> | 33 | #include <asm/mach/time.h> |
34 | 34 | ||
35 | #include "crm_regs.h" | ||
36 | #include "devices-imx53.h" | 35 | #include "devices-imx53.h" |
37 | 36 | ||
38 | #define MX53_LOCO_POWER IMX_GPIO_NR(1, 8) | 37 | #define MX53_LOCO_POWER IMX_GPIO_NR(1, 8) |
diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-imx/mach-mx53_smd.c index 22c53c9b18aa..8e972c5c3e13 100644 --- a/arch/arm/mach-mx5/board-mx53_smd.c +++ b/arch/arm/mach-imx/mach-mx53_smd.c | |||
@@ -31,7 +31,6 @@ | |||
31 | #include <asm/mach/arch.h> | 31 | #include <asm/mach/arch.h> |
32 | #include <asm/mach/time.h> | 32 | #include <asm/mach/time.h> |
33 | 33 | ||
34 | #include "crm_regs.h" | ||
35 | #include "devices-imx53.h" | 34 | #include "devices-imx53.h" |
36 | 35 | ||
37 | #define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6) | 36 | #define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6) |
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-imx/mm-imx5.c index bc17dfea3817..bc17dfea3817 100644 --- a/arch/arm/mach-mx5/mm.c +++ b/arch/arm/mach-imx/mm-imx5.c | |||
diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-imx/mx51_efika.c index ec6ca91b299b..ec6ca91b299b 100644 --- a/arch/arm/mach-mx5/mx51_efika.c +++ b/arch/arm/mach-imx/mx51_efika.c | |||
diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-imx/pm-imx5.c index 5eebfaad1226..6dc093448057 100644 --- a/arch/arm/mach-mx5/system.c +++ b/arch/arm/mach-imx/pm-imx5.c | |||
@@ -1,8 +1,6 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. | 2 | * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. |
3 | */ | 3 | * |
4 | |||
5 | /* | ||
6 | * The code contained herein is licensed under the GNU General Public | 4 | * The code contained herein is licensed under the GNU General Public |
7 | * License. You may obtain a copy of the GNU General Public License | 5 | * License. You may obtain a copy of the GNU General Public License |
8 | * Version 2 or later at the following locations: | 6 | * Version 2 or later at the following locations: |
@@ -10,14 +8,22 @@ | |||
10 | * http://www.opensource.org/licenses/gpl-license.html | 8 | * http://www.opensource.org/licenses/gpl-license.html |
11 | * http://www.gnu.org/copyleft/gpl.html | 9 | * http://www.gnu.org/copyleft/gpl.html |
12 | */ | 10 | */ |
13 | #include <linux/platform_device.h> | 11 | #include <linux/suspend.h> |
12 | #include <linux/clk.h> | ||
14 | #include <linux/io.h> | 13 | #include <linux/io.h> |
15 | #include <mach/hardware.h> | 14 | #include <linux/err.h> |
15 | #include <asm/cacheflush.h> | ||
16 | #include <asm/tlbflush.h> | ||
16 | #include <mach/common.h> | 17 | #include <mach/common.h> |
17 | #include "crm_regs.h" | 18 | #include <mach/hardware.h> |
19 | #include "crm-regs-imx5.h" | ||
20 | |||
21 | static struct clk *gpc_dvfs_clk; | ||
18 | 22 | ||
19 | /* set cpu low power mode before WFI instruction. This function is called | 23 | /* |
20 | * mx5 because it can be used for mx50, mx51, and mx53.*/ | 24 | * set cpu low power mode before WFI instruction. This function is called |
25 | * mx5 because it can be used for mx50, mx51, and mx53. | ||
26 | */ | ||
21 | void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) | 27 | void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) |
22 | { | 28 | { |
23 | u32 plat_lpc, arm_srpgcr, ccm_clpcr; | 29 | u32 plat_lpc, arm_srpgcr, ccm_clpcr; |
@@ -80,3 +86,68 @@ void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) | |||
80 | __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR); | 86 | __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR); |
81 | } | 87 | } |
82 | } | 88 | } |
89 | |||
90 | static int mx5_suspend_prepare(void) | ||
91 | { | ||
92 | return clk_enable(gpc_dvfs_clk); | ||
93 | } | ||
94 | |||
95 | static int mx5_suspend_enter(suspend_state_t state) | ||
96 | { | ||
97 | switch (state) { | ||
98 | case PM_SUSPEND_MEM: | ||
99 | mx5_cpu_lp_set(STOP_POWER_OFF); | ||
100 | break; | ||
101 | case PM_SUSPEND_STANDBY: | ||
102 | mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); | ||
103 | break; | ||
104 | default: | ||
105 | return -EINVAL; | ||
106 | } | ||
107 | |||
108 | if (state == PM_SUSPEND_MEM) { | ||
109 | local_flush_tlb_all(); | ||
110 | flush_cache_all(); | ||
111 | |||
112 | /*clear the EMPGC0/1 bits */ | ||
113 | __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR); | ||
114 | __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); | ||
115 | } | ||
116 | cpu_do_idle(); | ||
117 | return 0; | ||
118 | } | ||
119 | |||
120 | static void mx5_suspend_finish(void) | ||
121 | { | ||
122 | clk_disable(gpc_dvfs_clk); | ||
123 | } | ||
124 | |||
125 | static int mx5_pm_valid(suspend_state_t state) | ||
126 | { | ||
127 | return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX); | ||
128 | } | ||
129 | |||
130 | static const struct platform_suspend_ops mx5_suspend_ops = { | ||
131 | .valid = mx5_pm_valid, | ||
132 | .prepare = mx5_suspend_prepare, | ||
133 | .enter = mx5_suspend_enter, | ||
134 | .finish = mx5_suspend_finish, | ||
135 | }; | ||
136 | |||
137 | static int __init mx5_pm_init(void) | ||
138 | { | ||
139 | if (!cpu_is_mx51() && !cpu_is_mx53()) | ||
140 | return 0; | ||
141 | |||
142 | if (gpc_dvfs_clk == NULL) | ||
143 | gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs"); | ||
144 | |||
145 | if (!IS_ERR(gpc_dvfs_clk)) { | ||
146 | if (cpu_is_mx51()) | ||
147 | suspend_set_ops(&mx5_suspend_ops); | ||
148 | } else | ||
149 | return -EPERM; | ||
150 | |||
151 | return 0; | ||
152 | } | ||
153 | device_initcall(mx5_pm_init); | ||
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c index 29bd1243781e..e15f1555c59b 100644 --- a/arch/arm/mach-imx/src.c +++ b/arch/arm/mach-imx/src.c | |||
@@ -15,6 +15,7 @@ | |||
15 | #include <linux/of.h> | 15 | #include <linux/of.h> |
16 | #include <linux/of_address.h> | 16 | #include <linux/of_address.h> |
17 | #include <linux/smp.h> | 17 | #include <linux/smp.h> |
18 | #include <asm/smp_plat.h> | ||
18 | 19 | ||
19 | #define SRC_SCR 0x000 | 20 | #define SRC_SCR 0x000 |
20 | #define SRC_GPR1 0x020 | 21 | #define SRC_GPR1 0x020 |
@@ -24,10 +25,6 @@ | |||
24 | 25 | ||
25 | static void __iomem *src_base; | 26 | static void __iomem *src_base; |
26 | 27 | ||
27 | #ifndef CONFIG_SMP | ||
28 | #define cpu_logical_map(cpu) 0 | ||
29 | #endif | ||
30 | |||
31 | void imx_enable_cpu(int cpu, bool enable) | 28 | void imx_enable_cpu(int cpu, bool enable) |
32 | { | 29 | { |
33 | u32 mask, val; | 30 | u32 mask, val; |
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index cc15426787b1..77d4852e19f2 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c | |||
@@ -27,6 +27,7 @@ | |||
27 | #include <plat/cache-feroceon-l2.h> | 27 | #include <plat/cache-feroceon-l2.h> |
28 | #include <plat/mvsdio.h> | 28 | #include <plat/mvsdio.h> |
29 | #include <plat/orion_nand.h> | 29 | #include <plat/orion_nand.h> |
30 | #include <plat/ehci-orion.h> | ||
30 | #include <plat/common.h> | 31 | #include <plat/common.h> |
31 | #include <plat/time.h> | 32 | #include <plat/time.h> |
32 | #include <plat/addr-map.h> | 33 | #include <plat/addr-map.h> |
@@ -73,7 +74,7 @@ unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED; | |||
73 | void __init kirkwood_ehci_init(void) | 74 | void __init kirkwood_ehci_init(void) |
74 | { | 75 | { |
75 | kirkwood_clk_ctrl |= CGC_USB0; | 76 | kirkwood_clk_ctrl |= CGC_USB0; |
76 | orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB); | 77 | orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA); |
77 | } | 78 | } |
78 | 79 | ||
79 | 80 | ||
diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h index e8fda45c0736..d5a0d1da2e0e 100644 --- a/arch/arm/mach-kirkwood/mpp.h +++ b/arch/arm/mach-kirkwood/mpp.h | |||
@@ -31,314 +31,314 @@ | |||
31 | #define MPP_F6282_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 0, 1 ) | 31 | #define MPP_F6282_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 0, 1 ) |
32 | 32 | ||
33 | #define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1, 1 ) | 33 | #define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1, 1 ) |
34 | #define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | 34 | #define MPP0_NF_IO2 MPP( 0, 0x1, 0, 0, 1, 1, 1, 1, 1 ) |
35 | #define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1, 1 ) | 35 | #define MPP0_SPI_SCn MPP( 0, 0x2, 0, 0, 1, 1, 1, 1, 1 ) |
36 | 36 | ||
37 | #define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1, 1 ) | 37 | #define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1, 1 ) |
38 | #define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | 38 | #define MPP1_NF_IO3 MPP( 1, 0x1, 0, 0, 1, 1, 1, 1, 1 ) |
39 | #define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1, 1 ) | 39 | #define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 0, 1, 1, 1, 1, 1 ) |
40 | 40 | ||
41 | #define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1, 1 ) | 41 | #define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1, 1 ) |
42 | #define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | 42 | #define MPP2_NF_IO4 MPP( 2, 0x1, 0, 0, 1, 1, 1, 1, 1 ) |
43 | #define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1, 1 ) | 43 | #define MPP2_SPI_SCK MPP( 2, 0x2, 0, 0, 1, 1, 1, 1, 1 ) |
44 | 44 | ||
45 | #define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1, 1 ) | 45 | #define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1, 1 ) |
46 | #define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | 46 | #define MPP3_NF_IO5 MPP( 3, 0x1, 0, 0, 1, 1, 1, 1, 1 ) |
47 | #define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1, 1 ) | 47 | #define MPP3_SPI_MISO MPP( 3, 0x2, 0, 0, 1, 1, 1, 1, 1 ) |
48 | 48 | ||
49 | #define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1, 1 ) | 49 | #define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1, 1 ) |
50 | #define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | 50 | #define MPP4_NF_IO6 MPP( 4, 0x1, 0, 0, 1, 1, 1, 1, 1 ) |
51 | #define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1, 1 ) | 51 | #define MPP4_UART0_RXD MPP( 4, 0x2, 0, 0, 1, 1, 1, 1, 1 ) |
52 | #define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1, 1 ) | 52 | #define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 0, 0, 0, 1, 1, 1 ) |
53 | #define MPP4_LCD_VGA_HSYNC MPP( 4, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 53 | #define MPP4_LCD_VGA_HSYNC MPP( 4, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
54 | #define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1, 0 ) | 54 | #define MPP4_PTP_CLK MPP( 4, 0xd, 0, 0, 1, 1, 1, 1, 0 ) |
55 | 55 | ||
56 | #define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1, 1 ) | 56 | #define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1, 1 ) |
57 | #define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | 57 | #define MPP5_NF_IO7 MPP( 5, 0x1, 0, 0, 1, 1, 1, 1, 1 ) |
58 | #define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1, 1 ) | 58 | #define MPP5_UART0_TXD MPP( 5, 0x2, 0, 0, 1, 1, 1, 1, 1 ) |
59 | #define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1, 0 ) | 59 | #define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 0, 1, 1, 1, 1, 0 ) |
60 | #define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1, 1 ) | 60 | #define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 0, 0, 1, 1, 1, 1 ) |
61 | #define MPP5_LCD_VGA_VSYNC MPP( 5, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 61 | #define MPP5_LCD_VGA_VSYNC MPP( 5, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
62 | 62 | ||
63 | #define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1, 1 ) | 63 | #define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 0, 1, 1, 1, 1, 1 ) |
64 | #define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1, 1 ) | 64 | #define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 0, 1, 1, 1, 1, 1 ) |
65 | #define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1, 0 ) | 65 | #define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 0, 1, 1, 1, 1, 0 ) |
66 | 66 | ||
67 | #define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1, 1 ) | 67 | #define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1, 1 ) |
68 | #define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1, 0 ) | 68 | #define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 0, 1, 1, 1, 1, 0 ) |
69 | #define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1, 1 ) | 69 | #define MPP7_SPI_SCn MPP( 7, 0x2, 0, 0, 1, 1, 1, 1, 1 ) |
70 | #define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1, 0 ) | 70 | #define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 0, 1, 1, 1, 1, 0 ) |
71 | #define MPP7_LCD_PWM MPP( 7, 0xb, 0, 1, 0, 0, 0, 0, 1 ) | 71 | #define MPP7_LCD_PWM MPP( 7, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
72 | 72 | ||
73 | #define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1, 1 ) | 73 | #define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1, 1 ) |
74 | #define MPP8_TW0_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | 74 | #define MPP8_TW0_SDA MPP( 8, 0x1, 0, 0, 1, 1, 1, 1, 1 ) |
75 | #define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1, 1 ) | 75 | #define MPP8_UART0_RTS MPP( 8, 0x2, 0, 0, 1, 1, 1, 1, 1 ) |
76 | #define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1, 1 ) | 76 | #define MPP8_UART1_RTS MPP( 8, 0x3, 0, 0, 1, 1, 1, 1, 1 ) |
77 | #define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1, 1 ) | 77 | #define MPP8_MII0_RXERR MPP( 8, 0x4, 0, 0, 0, 1, 1, 1, 1 ) |
78 | #define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1, 1 ) | 78 | #define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 0, 0, 0, 1, 1, 1 ) |
79 | #define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1, 0 ) | 79 | #define MPP8_PTP_CLK MPP( 8, 0xc, 0, 0, 1, 1, 1, 1, 0 ) |
80 | #define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1, 1 ) | 80 | #define MPP8_MII0_COL MPP( 8, 0xd, 0, 0, 1, 1, 1, 1, 1 ) |
81 | 81 | ||
82 | #define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1, 1 ) | 82 | #define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1, 1 ) |
83 | #define MPP9_TW0_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | 83 | #define MPP9_TW0_SCK MPP( 9, 0x1, 0, 0, 1, 1, 1, 1, 1 ) |
84 | #define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1, 1 ) | 84 | #define MPP9_UART0_CTS MPP( 9, 0x2, 0, 0, 1, 1, 1, 1, 1 ) |
85 | #define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1, 1 ) | 85 | #define MPP9_UART1_CTS MPP( 9, 0x3, 0, 0, 1, 1, 1, 1, 1 ) |
86 | #define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1, 1 ) | 86 | #define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 0, 0, 1, 1, 1, 1 ) |
87 | #define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1, 0 ) | 87 | #define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 0, 0, 1, 1, 1, 1, 0 ) |
88 | #define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1, 1 ) | 88 | #define MPP9_MII0_CRS MPP( 9, 0xd, 0, 0, 1, 1, 1, 1, 1 ) |
89 | 89 | ||
90 | #define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1, 1 ) | 90 | #define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1, 1 ) |
91 | #define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1, 1 ) | 91 | #define MPP10_SPI_SCK MPP( 10, 0x2, 0, 0, 1, 1, 1, 1, 1 ) |
92 | #define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1, 1 ) | 92 | #define MPP10_UART0_TXD MPP( 10, 0X3, 0, 0, 1, 1, 1, 1, 1 ) |
93 | #define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1, 1 ) | 93 | #define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 0, 0, 0, 1, 1, 1 ) |
94 | #define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1, 0 ) | 94 | #define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 0, 1, 1, 1, 1, 0 ) |
95 | 95 | ||
96 | #define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1, 1 ) | 96 | #define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1, 1 ) |
97 | #define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1, 1 ) | 97 | #define MPP11_SPI_MISO MPP( 11, 0x2, 0, 0, 1, 1, 1, 1, 1 ) |
98 | #define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1, 1 ) | 98 | #define MPP11_UART0_RXD MPP( 11, 0x3, 0, 0, 1, 1, 1, 1, 1 ) |
99 | #define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1, 0 ) | 99 | #define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 0, 0, 1, 1, 1, 1, 0 ) |
100 | #define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1, 0 ) | 100 | #define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 0, 1, 1, 1, 1, 0 ) |
101 | #define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1, 0 ) | 101 | #define MPP11_PTP_CLK MPP( 11, 0xd, 0, 0, 1, 1, 1, 1, 0 ) |
102 | #define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1, 1 ) | 102 | #define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 0, 0, 1, 1, 1, 1 ) |
103 | 103 | ||
104 | #define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 ) | 104 | #define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 ) |
105 | #define MPP12_GPIO MPP( 12, 0x0, 1, 1, 0, 0, 0, 1, 0 ) | 105 | #define MPP12_GPIO MPP( 12, 0x0, 1, 1, 0, 0, 0, 1, 0 ) |
106 | #define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1, 1 ) | 106 | #define MPP12_SD_CLK MPP( 12, 0x1, 0, 0, 1, 1, 1, 1, 1 ) |
107 | #define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 1, 0, 0, 0, 0, 1 ) | 107 | #define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 0, 0, 0, 0, 0, 1 ) |
108 | #define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 1, 0, 0, 0, 0, 1 ) | 108 | #define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
109 | #define MPP12_TW1_SDA MPP( 12, 0xd, 1, 0, 0, 0, 0, 0, 1 ) | 109 | #define MPP12_TW1_SDA MPP( 12, 0xd, 0, 0, 0, 0, 0, 0, 1 ) |
110 | 110 | ||
111 | #define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1, 1 ) | 111 | #define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1, 1 ) |
112 | #define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | 112 | #define MPP13_SD_CMD MPP( 13, 0x1, 0, 0, 1, 1, 1, 1, 1 ) |
113 | #define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1, 1 ) | 113 | #define MPP13_UART1_TXD MPP( 13, 0x3, 0, 0, 1, 1, 1, 1, 1 ) |
114 | #define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 1, 0, 0, 0, 0, 1 ) | 114 | #define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 0, 0, 0, 0, 0, 1 ) |
115 | #define MPP13_LCDPWM MPP( 13, 0xb, 0, 1, 0, 0, 0, 0, 1 ) | 115 | #define MPP13_LCDPWM MPP( 13, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
116 | 116 | ||
117 | #define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1, 1 ) | 117 | #define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1, 1 ) |
118 | #define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | 118 | #define MPP14_SD_D0 MPP( 14, 0x1, 0, 0, 1, 1, 1, 1, 1 ) |
119 | #define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1, 1 ) | 119 | #define MPP14_UART1_RXD MPP( 14, 0x3, 0, 0, 1, 1, 1, 1, 1 ) |
120 | #define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1, 1 ) | 120 | #define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 0, 0, 0, 1, 1, 1 ) |
121 | #define MPP14_AU_SPDIFI MPP( 14, 0xa, 1, 0, 0, 0, 0, 0, 1 ) | 121 | #define MPP14_AU_SPDIFI MPP( 14, 0xa, 0, 0, 0, 0, 0, 0, 1 ) |
122 | #define MPP14_AU_I2SDI MPP( 14, 0xb, 1, 0, 0, 0, 0, 0, 1 ) | 122 | #define MPP14_AU_I2SDI MPP( 14, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
123 | #define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1, 1 ) | 123 | #define MPP14_MII0_COL MPP( 14, 0xd, 0, 0, 1, 1, 1, 1, 1 ) |
124 | 124 | ||
125 | #define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1, 1 ) | 125 | #define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1, 1 ) |
126 | #define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | 126 | #define MPP15_SD_D1 MPP( 15, 0x1, 0, 0, 1, 1, 1, 1, 1 ) |
127 | #define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1, 1 ) | 127 | #define MPP15_UART0_RTS MPP( 15, 0x2, 0, 0, 1, 1, 1, 1, 1 ) |
128 | #define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1, 1 ) | 128 | #define MPP15_UART1_TXD MPP( 15, 0x3, 0, 0, 1, 1, 1, 1, 1 ) |
129 | #define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1, 1 ) | 129 | #define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 0, 0, 1, 1, 1, 1 ) |
130 | #define MPP15_SPI_CSn MPP( 15, 0xb, 0, 1, 0, 0, 0, 0, 1 ) | 130 | #define MPP15_SPI_CSn MPP( 15, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
131 | 131 | ||
132 | #define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1, 1 ) | 132 | #define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1, 1 ) |
133 | #define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | 133 | #define MPP16_SD_D2 MPP( 16, 0x1, 0, 0, 1, 1, 1, 1, 1 ) |
134 | #define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1, 1 ) | 134 | #define MPP16_UART0_CTS MPP( 16, 0x2, 0, 0, 1, 1, 1, 1, 1 ) |
135 | #define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1, 1 ) | 135 | #define MPP16_UART1_RXD MPP( 16, 0x3, 0, 0, 1, 1, 1, 1, 1 ) |
136 | #define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1, 1 ) | 136 | #define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 0, 0, 0, 1, 1, 1 ) |
137 | #define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 1, 0, 0, 0, 0, 0, 1 ) | 137 | #define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
138 | #define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1, 1 ) | 138 | #define MPP16_MII0_CRS MPP( 16, 0xd, 0, 0, 1, 1, 1, 1, 1 ) |
139 | 139 | ||
140 | #define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1, 1 ) | 140 | #define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1, 1 ) |
141 | #define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | 141 | #define MPP17_SD_D3 MPP( 17, 0x1, 0, 0, 1, 1, 1, 1, 1 ) |
142 | #define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1, 1 ) | 142 | #define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 0, 0, 1, 1, 1, 1 ) |
143 | #define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 1, 0, 0, 0, 0, 1 ) | 143 | #define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 0, 0, 0, 0, 0, 1 ) |
144 | #define MPP17_TW1_SCK MPP( 17, 0xd, 1, 1, 0, 0, 0, 0, 1 ) | 144 | #define MPP17_TW1_SCK MPP( 17, 0xd, 0, 0, 0, 0, 0, 0, 1 ) |
145 | 145 | ||
146 | #define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1, 1 ) | 146 | #define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1, 1 ) |
147 | #define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | 147 | #define MPP18_NF_IO0 MPP( 18, 0x1, 0, 0, 1, 1, 1, 1, 1 ) |
148 | #define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 1, 0, 0, 0, 0, 1 ) | 148 | #define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 0, 0, 0, 0, 0, 1 ) |
149 | 149 | ||
150 | #define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1, 1 ) | 150 | #define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1, 1 ) |
151 | #define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | 151 | #define MPP19_NF_IO1 MPP( 19, 0x1, 0, 0, 1, 1, 1, 1, 1 ) |
152 | 152 | ||
153 | #define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1, 1 ) | 153 | #define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
154 | #define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1, 1 ) | 154 | #define MPP20_TSMP0 MPP( 20, 0x1, 0, 0, 0, 0, 1, 1, 1 ) |
155 | #define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1, 1 ) | 155 | #define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 0, 0, 0, 1, 1, 1 ) |
156 | #define MPP20_GE1_TXD0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1, 1 ) | 156 | #define MPP20_GE1_TXD0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
157 | #define MPP20_AU_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1, 1 ) | 157 | #define MPP20_AU_SPDIFI MPP( 20, 0x4, 0, 0, 0, 0, 1, 1, 1 ) |
158 | #define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1, 1 ) | 158 | #define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 0, 0, 0, 1, 1, 1 ) |
159 | #define MPP20_LCD_D0 MPP( 20, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 159 | #define MPP20_LCD_D0 MPP( 20, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
160 | 160 | ||
161 | #define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1, 1 ) | 161 | #define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
162 | #define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1, 1 ) | 162 | #define MPP21_TSMP1 MPP( 21, 0x1, 0, 0, 0, 0, 1, 1, 1 ) |
163 | #define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1, 1 ) | 163 | #define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 0, 0, 0, 1, 1, 1 ) |
164 | #define MPP21_GE1_TXD1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1, 1 ) | 164 | #define MPP21_GE1_TXD1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
165 | #define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1, 1 ) | 165 | #define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 0, 0, 0, 1, 1, 1 ) |
166 | #define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1, 1 ) | 166 | #define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 0, 0, 1, 1, 1, 1 ) |
167 | #define MPP21_LCD_D1 MPP( 21, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 167 | #define MPP21_LCD_D1 MPP( 21, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
168 | 168 | ||
169 | #define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1, 1 ) | 169 | #define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
170 | #define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1, 1 ) | 170 | #define MPP22_TSMP2 MPP( 22, 0x1, 0, 0, 0, 0, 1, 1, 1 ) |
171 | #define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1, 1 ) | 171 | #define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 0, 0, 0, 1, 1, 1 ) |
172 | #define MPP22_GE1_TXD2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1, 1 ) | 172 | #define MPP22_GE1_TXD2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
173 | #define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1, 1 ) | 173 | #define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 0, 0, 0, 1, 1, 1 ) |
174 | #define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1, 1 ) | 174 | #define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 0, 0, 0, 1, 1, 1 ) |
175 | #define MPP22_LCD_D2 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 175 | #define MPP22_LCD_D2 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
176 | 176 | ||
177 | #define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1, 1 ) | 177 | #define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
178 | #define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1, 1 ) | 178 | #define MPP23_TSMP3 MPP( 23, 0x1, 0, 0, 0, 0, 1, 1, 1 ) |
179 | #define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1, 1 ) | 179 | #define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 0, 0, 0, 0, 1, 1, 1 ) |
180 | #define MPP23_GE1_TXD3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1, 1 ) | 180 | #define MPP23_GE1_TXD3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
181 | #define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1, 1 ) | 181 | #define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 0, 0, 0, 1, 1, 1 ) |
182 | #define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1, 1 ) | 182 | #define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 0, 0, 1, 1, 1, 1 ) |
183 | #define MPP23_LCD_D3 MPP( 23, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 183 | #define MPP23_LCD_D3 MPP( 23, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
184 | 184 | ||
185 | #define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1, 1 ) | 185 | #define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
186 | #define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1, 1 ) | 186 | #define MPP24_TSMP4 MPP( 24, 0x1, 0, 0, 0, 0, 1, 1, 1 ) |
187 | #define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 1, 0, 0, 1, 1, 1 ) | 187 | #define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 0, 0, 0, 1, 1, 1 ) |
188 | #define MPP24_GE1_RXD0 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1, 1 ) | 188 | #define MPP24_GE1_RXD0 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
189 | #define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1, 1 ) | 189 | #define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 0, 0, 0, 1, 1, 1 ) |
190 | #define MPP24_LCD_D4 MPP( 24, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 190 | #define MPP24_LCD_D4 MPP( 24, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
191 | 191 | ||
192 | #define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1, 1 ) | 192 | #define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
193 | #define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1, 1 ) | 193 | #define MPP25_TSMP5 MPP( 25, 0x1, 0, 0, 0, 0, 1, 1, 1 ) |
194 | #define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1, 1 ) | 194 | #define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 0, 0, 0, 1, 1, 1 ) |
195 | #define MPP25_GE1_RXD1 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1, 1 ) | 195 | #define MPP25_GE1_RXD1 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
196 | #define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1, 1 ) | 196 | #define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 0, 0, 0, 1, 1, 1 ) |
197 | #define MPP25_LCD_D5 MPP( 25, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 197 | #define MPP25_LCD_D5 MPP( 25, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
198 | 198 | ||
199 | #define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1, 1 ) | 199 | #define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
200 | #define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1, 1 ) | 200 | #define MPP26_TSMP6 MPP( 26, 0x1, 0, 0, 0, 0, 1, 1, 1 ) |
201 | #define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1, 1 ) | 201 | #define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 0, 0, 0, 0, 1, 1, 1 ) |
202 | #define MPP26_GE1_RXD2 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1, 1 ) | 202 | #define MPP26_GE1_RXD2 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
203 | #define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1, 1 ) | 203 | #define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 0, 0, 0, 1, 1, 1 ) |
204 | #define MPP26_LCD_D6 MPP( 26, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 204 | #define MPP26_LCD_D6 MPP( 26, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
205 | 205 | ||
206 | #define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1, 1 ) | 206 | #define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
207 | #define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1, 1 ) | 207 | #define MPP27_TSMP7 MPP( 27, 0x1, 0, 0, 0, 0, 1, 1, 1 ) |
208 | #define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1, 1 ) | 208 | #define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 0, 0, 0, 1, 1, 1 ) |
209 | #define MPP27_GE1_RXD3 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1, 1 ) | 209 | #define MPP27_GE1_RXD3 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
210 | #define MPP27_AU_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1, 1 ) | 210 | #define MPP27_AU_I2SDI MPP( 27, 0x4, 0, 0, 0, 0, 1, 1, 1 ) |
211 | #define MPP27_LCD_D7 MPP( 27, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 211 | #define MPP27_LCD_D7 MPP( 27, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
212 | 212 | ||
213 | #define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1, 1 ) | 213 | #define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
214 | #define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1, 1 ) | 214 | #define MPP28_TSMP8 MPP( 28, 0x1, 0, 0, 0, 0, 1, 1, 1 ) |
215 | #define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1, 1 ) | 215 | #define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1, 1 ) |
216 | #define MPP28_GE1_COL MPP( 28, 0x3, 0, 0, 0, 1, 1, 1, 1 ) | 216 | #define MPP28_GE1_COL MPP( 28, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
217 | #define MPP28_AU_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1, 1 ) | 217 | #define MPP28_AU_EXTCLK MPP( 28, 0x4, 0, 0, 0, 0, 1, 1, 1 ) |
218 | #define MPP28_LCD_D8 MPP( 28, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 218 | #define MPP28_LCD_D8 MPP( 28, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
219 | 219 | ||
220 | #define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1, 1 ) | 220 | #define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
221 | #define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1, 1 ) | 221 | #define MPP29_TSMP9 MPP( 29, 0x1, 0, 0, 0, 0, 1, 1, 1 ) |
222 | #define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1, 1 ) | 222 | #define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1, 1 ) |
223 | #define MPP29_GE1_TCLK MPP( 29, 0x3, 0, 0, 0, 1, 1, 1, 1 ) | 223 | #define MPP29_GE1_TCLK MPP( 29, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
224 | #define MPP29_LCD_D9 MPP( 29, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 224 | #define MPP29_LCD_D9 MPP( 29, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
225 | 225 | ||
226 | #define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1, 1 ) | 226 | #define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
227 | #define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1, 1 ) | 227 | #define MPP30_TSMP10 MPP( 30, 0x1, 0, 0, 0, 0, 1, 1, 1 ) |
228 | #define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1, 1 ) | 228 | #define MPP30_TDM_PCLK MPP( 30, 0x2, 0, 0, 0, 0, 1, 1, 1 ) |
229 | #define MPP30_GE1_RXCTL MPP( 30, 0x3, 0, 0, 0, 1, 1, 1, 1 ) | 229 | #define MPP30_GE1_RXCTL MPP( 30, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
230 | #define MPP30_LCD_D10 MPP( 30, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 230 | #define MPP30_LCD_D10 MPP( 30, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
231 | 231 | ||
232 | #define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1, 1 ) | 232 | #define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
233 | #define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1, 1 ) | 233 | #define MPP31_TSMP11 MPP( 31, 0x1, 0, 0, 0, 0, 1, 1, 1 ) |
234 | #define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1, 1 ) | 234 | #define MPP31_TDM_FS MPP( 31, 0x2, 0, 0, 0, 0, 1, 1, 1 ) |
235 | #define MPP31_GE1_RXCLK MPP( 31, 0x3, 0, 0, 0, 1, 1, 1, 1 ) | 235 | #define MPP31_GE1_RXCLK MPP( 31, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
236 | #define MPP31_LCD_D11 MPP( 31, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 236 | #define MPP31_LCD_D11 MPP( 31, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
237 | 237 | ||
238 | #define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1, 1 ) | 238 | #define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
239 | #define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1, 1 ) | 239 | #define MPP32_TSMP12 MPP( 32, 0x1, 0, 0, 0, 0, 1, 1, 1 ) |
240 | #define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1, 1 ) | 240 | #define MPP32_TDM_DRX MPP( 32, 0x2, 0, 0, 0, 0, 1, 1, 1 ) |
241 | #define MPP32_GE1_TCLKOUT MPP( 32, 0x3, 0, 0, 0, 1, 1, 1, 1 ) | 241 | #define MPP32_GE1_TCLKOUT MPP( 32, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
242 | #define MPP32_LCD_D12 MPP( 32, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 242 | #define MPP32_LCD_D12 MPP( 32, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
243 | 243 | ||
244 | #define MPP33_GPO MPP( 33, 0x0, 0, 1, 0, 1, 1, 1, 1 ) | 244 | #define MPP33_GPO MPP( 33, 0x0, 0, 1, 0, 1, 1, 1, 1 ) |
245 | #define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1, 1 ) | 245 | #define MPP33_TDM_DTX MPP( 33, 0x2, 0, 0, 0, 0, 1, 1, 1 ) |
246 | #define MPP33_GE1_TXCTL MPP( 33, 0x3, 0, 0, 0, 1, 1, 1, 1 ) | 246 | #define MPP33_GE1_TXCTL MPP( 33, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
247 | #define MPP33_LCD_D13 MPP( 33, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 247 | #define MPP33_LCD_D13 MPP( 33, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
248 | 248 | ||
249 | #define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1, 1 ) | 249 | #define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
250 | #define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1, 1 ) | 250 | #define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 0, 0, 0, 1, 1, 1 ) |
251 | #define MPP34_GE1_TXEN MPP( 34, 0x3, 0, 0, 0, 1, 1, 1, 1 ) | 251 | #define MPP34_GE1_TXEN MPP( 34, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
252 | #define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 1, 0, 0, 0, 1, 1 ) | 252 | #define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 0, 0, 0, 0, 1, 1 ) |
253 | #define MPP34_LCD_D14 MPP( 34, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 253 | #define MPP34_LCD_D14 MPP( 34, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
254 | 254 | ||
255 | #define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1, 1 ) | 255 | #define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1, 1 ) |
256 | #define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1, 1 ) | 256 | #define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 0, 0, 0, 1, 1, 1 ) |
257 | #define MPP35_GE1_RXERR MPP( 35, 0x3, 0, 0, 0, 1, 1, 1, 1 ) | 257 | #define MPP35_GE1_RXERR MPP( 35, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
258 | #define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1, 1 ) | 258 | #define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 0, 0, 1, 1, 1, 1 ) |
259 | #define MPP35_LCD_D15 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 259 | #define MPP35_LCD_D15 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
260 | #define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1, 1 ) | 260 | #define MPP35_MII0_RXERR MPP( 35, 0xc, 0, 0, 1, 1, 1, 1, 1 ) |
261 | 261 | ||
262 | #define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1, 1 ) | 262 | #define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1, 1 ) |
263 | #define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1, 1 ) | 263 | #define MPP36_TSMP0 MPP( 36, 0x1, 0, 0, 0, 0, 0, 1, 1 ) |
264 | #define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1, 1 ) | 264 | #define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 0, 0, 0, 0, 1, 1 ) |
265 | #define MPP36_AU_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1, 1 ) | 265 | #define MPP36_AU_SPDIFI MPP( 36, 0x4, 0, 0, 1, 0, 0, 1, 1 ) |
266 | #define MPP36_TW1_SDA MPP( 36, 0xb, 1, 1, 0, 0, 0, 0, 1 ) | 266 | #define MPP36_TW1_SDA MPP( 36, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
267 | 267 | ||
268 | #define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1, 1 ) | 268 | #define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1, 1 ) |
269 | #define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1, 1 ) | 269 | #define MPP37_TSMP1 MPP( 37, 0x1, 0, 0, 0, 0, 0, 1, 1 ) |
270 | #define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1, 1 ) | 270 | #define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 0, 0, 0, 0, 1, 1 ) |
271 | #define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1, 1 ) | 271 | #define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 0, 1, 0, 0, 1, 1 ) |
272 | #define MPP37_TW1_SCK MPP( 37, 0xb, 1, 1, 0, 0, 0, 0, 1 ) | 272 | #define MPP37_TW1_SCK MPP( 37, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
273 | 273 | ||
274 | #define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1, 1 ) | 274 | #define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1, 1 ) |
275 | #define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1, 1 ) | 275 | #define MPP38_TSMP2 MPP( 38, 0x1, 0, 0, 0, 0, 0, 1, 1 ) |
276 | #define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1, 1 ) | 276 | #define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 0, 0, 0, 0, 1, 1 ) |
277 | #define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1, 1 ) | 277 | #define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 0, 1, 0, 0, 1, 1 ) |
278 | #define MPP38_LCD_D18 MPP( 38, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 278 | #define MPP38_LCD_D18 MPP( 38, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
279 | 279 | ||
280 | #define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1, 1 ) | 280 | #define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1, 1 ) |
281 | #define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1, 1 ) | 281 | #define MPP39_TSMP3 MPP( 39, 0x1, 0, 0, 0, 0, 0, 1, 1 ) |
282 | #define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1, 1 ) | 282 | #define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 0, 0, 0, 0, 1, 1 ) |
283 | #define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1, 1 ) | 283 | #define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 0, 1, 0, 0, 1, 1 ) |
284 | #define MPP39_LCD_D19 MPP( 39, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 284 | #define MPP39_LCD_D19 MPP( 39, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
285 | 285 | ||
286 | #define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1, 1 ) | 286 | #define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1, 1 ) |
287 | #define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1, 1 ) | 287 | #define MPP40_TSMP4 MPP( 40, 0x1, 0, 0, 0, 0, 0, 1, 1 ) |
288 | #define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1, 1 ) | 288 | #define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 0, 0, 0, 0, 1, 1 ) |
289 | #define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1, 1 ) | 289 | #define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 0, 1, 0, 0, 1, 1 ) |
290 | #define MPP40_LCD_D20 MPP( 40, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 290 | #define MPP40_LCD_D20 MPP( 40, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
291 | 291 | ||
292 | #define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1, 1 ) | 292 | #define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1, 1 ) |
293 | #define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1, 1 ) | 293 | #define MPP41_TSMP5 MPP( 41, 0x1, 0, 0, 0, 0, 0, 1, 1 ) |
294 | #define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1, 1 ) | 294 | #define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 0, 0, 0, 0, 0, 1, 1 ) |
295 | #define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 1, 1, 0, 0, 1, 1 ) | 295 | #define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 0, 1, 0, 0, 1, 1 ) |
296 | #define MPP41_LCD_D21 MPP( 41, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 296 | #define MPP41_LCD_D21 MPP( 41, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
297 | 297 | ||
298 | #define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1, 1 ) | 298 | #define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1, 1 ) |
299 | #define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1, 1 ) | 299 | #define MPP42_TSMP6 MPP( 42, 0x1, 0, 0, 0, 0, 0, 1, 1 ) |
300 | #define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1, 1 ) | 300 | #define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 0, 0, 0, 0, 1, 1 ) |
301 | #define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1, 1 ) | 301 | #define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 0, 1, 0, 0, 1, 1 ) |
302 | #define MPP42_LCD_D22 MPP( 42, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 302 | #define MPP42_LCD_D22 MPP( 42, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
303 | 303 | ||
304 | #define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1, 1 ) | 304 | #define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1, 1 ) |
305 | #define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1, 1 ) | 305 | #define MPP43_TSMP7 MPP( 43, 0x1, 0, 0, 0, 0, 0, 1, 1 ) |
306 | #define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1, 1 ) | 306 | #define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1, 1 ) |
307 | #define MPP43_AU_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1, 1 ) | 307 | #define MPP43_AU_I2SDI MPP( 43, 0x4, 0, 0, 1, 0, 0, 1, 1 ) |
308 | #define MPP43_LCD_D23 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 308 | #define MPP43_LCD_D23 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
309 | 309 | ||
310 | #define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1, 1 ) | 310 | #define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1, 1 ) |
311 | #define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1, 1 ) | 311 | #define MPP44_TSMP8 MPP( 44, 0x1, 0, 0, 0, 0, 0, 1, 1 ) |
312 | #define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1, 1 ) | 312 | #define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1, 1 ) |
313 | #define MPP44_AU_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1, 1 ) | 313 | #define MPP44_AU_EXTCLK MPP( 44, 0x4, 0, 0, 1, 0, 0, 1, 1 ) |
314 | #define MPP44_LCD_CLK MPP( 44, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 314 | #define MPP44_LCD_CLK MPP( 44, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
315 | 315 | ||
316 | #define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1, 1 ) | 316 | #define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1, 1 ) |
317 | #define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1, 1 ) | 317 | #define MPP45_TSMP9 MPP( 45, 0x1, 0, 0, 0, 0, 0, 1, 1 ) |
318 | #define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1, 1 ) | 318 | #define MPP45_TDM_PCLK MPP( 45, 0x2, 0, 0, 0, 0, 0, 1, 1 ) |
319 | #define MPP245_LCD_E MPP( 45, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 319 | #define MPP245_LCD_E MPP( 45, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
320 | 320 | ||
321 | #define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1, 1 ) | 321 | #define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1, 1 ) |
322 | #define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1, 1 ) | 322 | #define MPP46_TSMP10 MPP( 46, 0x1, 0, 0, 0, 0, 0, 1, 1 ) |
323 | #define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1, 1 ) | 323 | #define MPP46_TDM_FS MPP( 46, 0x2, 0, 0, 0, 0, 0, 1, 1 ) |
324 | #define MPP46_LCD_HSYNC MPP( 46, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 324 | #define MPP46_LCD_HSYNC MPP( 46, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
325 | 325 | ||
326 | #define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1, 1 ) | 326 | #define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1, 1 ) |
327 | #define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1, 1 ) | 327 | #define MPP47_TSMP11 MPP( 47, 0x1, 0, 0, 0, 0, 0, 1, 1 ) |
328 | #define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1, 1 ) | 328 | #define MPP47_TDM_DRX MPP( 47, 0x2, 0, 0, 0, 0, 0, 1, 1 ) |
329 | #define MPP47_LCD_VSYNC MPP( 47, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 329 | #define MPP47_LCD_VSYNC MPP( 47, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
330 | 330 | ||
331 | #define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1, 1 ) | 331 | #define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1, 1 ) |
332 | #define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1, 1 ) | 332 | #define MPP48_TSMP12 MPP( 48, 0x1, 0, 0, 0, 0, 0, 1, 1 ) |
333 | #define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1, 1 ) | 333 | #define MPP48_TDM_DTX MPP( 48, 0x2, 0, 0, 0, 0, 0, 1, 1 ) |
334 | #define MPP48_LCD_D16 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 334 | #define MPP48_LCD_D16 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
335 | 335 | ||
336 | #define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1, 0 ) | 336 | #define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1, 0 ) |
337 | #define MPP49_GPO MPP( 49, 0x0, 0, 1, 0, 0, 0, 0, 1 ) | 337 | #define MPP49_GPO MPP( 49, 0x0, 0, 1, 0, 0, 0, 0, 1 ) |
338 | #define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1, 0 ) | 338 | #define MPP49_TSMP9 MPP( 49, 0x1, 0, 0, 0, 0, 0, 1, 0 ) |
339 | #define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1, 1 ) | 339 | #define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 0, 0, 0, 0, 1, 1 ) |
340 | #define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1, 0 ) | 340 | #define MPP49_PTP_CLK MPP( 49, 0x5, 0, 0, 0, 0, 0, 1, 0 ) |
341 | #define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 1, 0, 0, 0, 0, 1 ) | 341 | #define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 0, 0, 0, 0, 0, 1 ) |
342 | #define MPP49_LCD_D17 MPP( 49, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | 342 | #define MPP49_LCD_D17 MPP( 49, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
343 | 343 | ||
344 | #define MPP_MAX 49 | 344 | #define MPP_MAX 49 |
diff --git a/arch/arm/mach-msm/hotplug.c b/arch/arm/mach-msm/hotplug.c index 41c252de0215..a446fc14221f 100644 --- a/arch/arm/mach-msm/hotplug.c +++ b/arch/arm/mach-msm/hotplug.c | |||
@@ -11,6 +11,7 @@ | |||
11 | #include <linux/smp.h> | 11 | #include <linux/smp.h> |
12 | 12 | ||
13 | #include <asm/cacheflush.h> | 13 | #include <asm/cacheflush.h> |
14 | #include <asm/smp_plat.h> | ||
14 | 15 | ||
15 | extern volatile int pen_release; | 16 | extern volatile int pen_release; |
16 | 17 | ||
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c index 0b3e357c4c8c..db0117ec55f4 100644 --- a/arch/arm/mach-msm/platsmp.c +++ b/arch/arm/mach-msm/platsmp.c | |||
@@ -20,6 +20,7 @@ | |||
20 | #include <asm/cacheflush.h> | 20 | #include <asm/cacheflush.h> |
21 | #include <asm/cputype.h> | 21 | #include <asm/cputype.h> |
22 | #include <asm/mach-types.h> | 22 | #include <asm/mach-types.h> |
23 | #include <asm/smp_plat.h> | ||
23 | 24 | ||
24 | #include <mach/msm_iomap.h> | 25 | #include <mach/msm_iomap.h> |
25 | 26 | ||
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index 0cdd41004ad0..a5dcf766a3f9 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c | |||
@@ -19,6 +19,7 @@ | |||
19 | #include <mach/mv78xx0.h> | 19 | #include <mach/mv78xx0.h> |
20 | #include <mach/bridge-regs.h> | 20 | #include <mach/bridge-regs.h> |
21 | #include <plat/cache-feroceon-l2.h> | 21 | #include <plat/cache-feroceon-l2.h> |
22 | #include <plat/ehci-orion.h> | ||
22 | #include <plat/orion_nand.h> | 23 | #include <plat/orion_nand.h> |
23 | #include <plat/time.h> | 24 | #include <plat/time.h> |
24 | #include <plat/common.h> | 25 | #include <plat/common.h> |
@@ -169,7 +170,7 @@ void __init mv78xx0_map_io(void) | |||
169 | ****************************************************************************/ | 170 | ****************************************************************************/ |
170 | void __init mv78xx0_ehci0_init(void) | 171 | void __init mv78xx0_ehci0_init(void) |
171 | { | 172 | { |
172 | orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0); | 173 | orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA); |
173 | } | 174 | } |
174 | 175 | ||
175 | 176 | ||
diff --git a/arch/arm/mach-mv78xx0/mpp.h b/arch/arm/mach-mv78xx0/mpp.h index b61b50927123..3752302ae2ee 100644 --- a/arch/arm/mach-mv78xx0/mpp.h +++ b/arch/arm/mach-mv78xx0/mpp.h | |||
@@ -24,296 +24,296 @@ | |||
24 | #define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1) | 24 | #define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1) |
25 | 25 | ||
26 | #define MPP0_GPIO MPP(0, 0x0, 1, 1, 1) | 26 | #define MPP0_GPIO MPP(0, 0x0, 1, 1, 1) |
27 | #define MPP0_GE0_COL MPP(0, 0x1, 1, 0, 1) | 27 | #define MPP0_GE0_COL MPP(0, 0x1, 0, 0, 1) |
28 | #define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 1, 1) | 28 | #define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 0, 1) |
29 | #define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1) | 29 | #define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1) |
30 | 30 | ||
31 | #define MPP1_GPIO MPP(1, 0x0, 1, 1, 1) | 31 | #define MPP1_GPIO MPP(1, 0x0, 1, 1, 1) |
32 | #define MPP1_GE0_RXERR MPP(1, 0x1, 1, 0, 1) | 32 | #define MPP1_GE0_RXERR MPP(1, 0x1, 0, 0, 1) |
33 | #define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 1, 1) | 33 | #define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 0, 1) |
34 | #define MPP1_UNUSED MPP(1, 0x3, 0, 0, 1) | 34 | #define MPP1_UNUSED MPP(1, 0x3, 0, 0, 1) |
35 | 35 | ||
36 | #define MPP2_GPIO MPP(2, 0x0, 1, 1, 1) | 36 | #define MPP2_GPIO MPP(2, 0x0, 1, 1, 1) |
37 | #define MPP2_GE0_CRS MPP(2, 0x1, 1, 0, 1) | 37 | #define MPP2_GE0_CRS MPP(2, 0x1, 0, 0, 1) |
38 | #define MPP2_GE1_RXCTL MPP(2, 0x2, 1, 0, 1) | 38 | #define MPP2_GE1_RXCTL MPP(2, 0x2, 0, 0, 1) |
39 | #define MPP2_UNUSED MPP(2, 0x3, 0, 0, 1) | 39 | #define MPP2_UNUSED MPP(2, 0x3, 0, 0, 1) |
40 | 40 | ||
41 | #define MPP3_GPIO MPP(3, 0x0, 1, 1, 1) | 41 | #define MPP3_GPIO MPP(3, 0x0, 1, 1, 1) |
42 | #define MPP3_GE0_TXERR MPP(3, 0x1, 0, 1, 1) | 42 | #define MPP3_GE0_TXERR MPP(3, 0x1, 0, 0, 1) |
43 | #define MPP3_GE1_RXCLK MPP(3, 0x2, 1, 0, 1) | 43 | #define MPP3_GE1_RXCLK MPP(3, 0x2, 0, 0, 1) |
44 | #define MPP3_UNUSED MPP(3, 0x3, 0, 0, 1) | 44 | #define MPP3_UNUSED MPP(3, 0x3, 0, 0, 1) |
45 | 45 | ||
46 | #define MPP4_GPIO MPP(4, 0x0, 1, 1, 1) | 46 | #define MPP4_GPIO MPP(4, 0x0, 1, 1, 1) |
47 | #define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 1, 1) | 47 | #define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 0, 1) |
48 | #define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 1, 1) | 48 | #define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 0, 1) |
49 | #define MPP4_UNUSED MPP(4, 0x3, 0, 0, 1) | 49 | #define MPP4_UNUSED MPP(4, 0x3, 0, 0, 1) |
50 | 50 | ||
51 | #define MPP5_GPIO MPP(5, 0x0, 1, 1, 1) | 51 | #define MPP5_GPIO MPP(5, 0x0, 1, 1, 1) |
52 | #define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 1, 1) | 52 | #define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 0, 1) |
53 | #define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 1, 1) | 53 | #define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 0, 1) |
54 | #define MPP5_UNUSED MPP(5, 0x3, 0, 0, 1) | 54 | #define MPP5_UNUSED MPP(5, 0x3, 0, 0, 1) |
55 | 55 | ||
56 | #define MPP6_GPIO MPP(6, 0x0, 1, 1, 1) | 56 | #define MPP6_GPIO MPP(6, 0x0, 1, 1, 1) |
57 | #define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 1, 1) | 57 | #define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 0, 1) |
58 | #define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 1, 1) | 58 | #define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 0, 1) |
59 | #define MPP6_UNUSED MPP(6, 0x3, 0, 0, 1) | 59 | #define MPP6_UNUSED MPP(6, 0x3, 0, 0, 1) |
60 | 60 | ||
61 | #define MPP7_GPIO MPP(7, 0x0, 1, 1, 1) | 61 | #define MPP7_GPIO MPP(7, 0x0, 1, 1, 1) |
62 | #define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 1, 1) | 62 | #define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 0, 1) |
63 | #define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 1, 1) | 63 | #define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 0, 1) |
64 | #define MPP7_UNUSED MPP(7, 0x3, 0, 0, 1) | 64 | #define MPP7_UNUSED MPP(7, 0x3, 0, 0, 1) |
65 | 65 | ||
66 | #define MPP8_GPIO MPP(8, 0x0, 1, 1, 1) | 66 | #define MPP8_GPIO MPP(8, 0x0, 1, 1, 1) |
67 | #define MPP8_GE0_RXD4 MPP(8, 0x1, 1, 0, 1) | 67 | #define MPP8_GE0_RXD4 MPP(8, 0x1, 0, 0, 1) |
68 | #define MPP8_GE1_RXD0 MPP(8, 0x2, 1, 0, 1) | 68 | #define MPP8_GE1_RXD0 MPP(8, 0x2, 0, 0, 1) |
69 | #define MPP8_UNUSED MPP(8, 0x3, 0, 0, 1) | 69 | #define MPP8_UNUSED MPP(8, 0x3, 0, 0, 1) |
70 | 70 | ||
71 | #define MPP9_GPIO MPP(9, 0x0, 1, 1, 1) | 71 | #define MPP9_GPIO MPP(9, 0x0, 1, 1, 1) |
72 | #define MPP9_GE0_RXD5 MPP(9, 0x1, 1, 0, 1) | 72 | #define MPP9_GE0_RXD5 MPP(9, 0x1, 0, 0, 1) |
73 | #define MPP9_GE1_RXD1 MPP(9, 0x2, 1, 0, 1) | 73 | #define MPP9_GE1_RXD1 MPP(9, 0x2, 0, 0, 1) |
74 | #define MPP9_UNUSED MPP(9, 0x3, 0, 0, 1) | 74 | #define MPP9_UNUSED MPP(9, 0x3, 0, 0, 1) |
75 | 75 | ||
76 | #define MPP10_GPIO MPP(10, 0x0, 1, 1, 1) | 76 | #define MPP10_GPIO MPP(10, 0x0, 1, 1, 1) |
77 | #define MPP10_GE0_RXD6 MPP(10, 0x1, 1, 0, 1) | 77 | #define MPP10_GE0_RXD6 MPP(10, 0x1, 0, 0, 1) |
78 | #define MPP10_GE1_RXD2 MPP(10, 0x2, 1, 0, 1) | 78 | #define MPP10_GE1_RXD2 MPP(10, 0x2, 0, 0, 1) |
79 | #define MPP10_UNUSED MPP(10, 0x3, 0, 0, 1) | 79 | #define MPP10_UNUSED MPP(10, 0x3, 0, 0, 1) |
80 | 80 | ||
81 | #define MPP11_GPIO MPP(11, 0x0, 1, 1, 1) | 81 | #define MPP11_GPIO MPP(11, 0x0, 1, 1, 1) |
82 | #define MPP11_GE0_RXD7 MPP(11, 0x1, 1, 0, 1) | 82 | #define MPP11_GE0_RXD7 MPP(11, 0x1, 0, 0, 1) |
83 | #define MPP11_GE1_RXD3 MPP(11, 0x2, 1, 0, 1) | 83 | #define MPP11_GE1_RXD3 MPP(11, 0x2, 0, 0, 1) |
84 | #define MPP11_UNUSED MPP(11, 0x3, 0, 0, 1) | 84 | #define MPP11_UNUSED MPP(11, 0x3, 0, 0, 1) |
85 | 85 | ||
86 | #define MPP12_GPIO MPP(12, 0x0, 1, 1, 1) | 86 | #define MPP12_GPIO MPP(12, 0x0, 1, 1, 1) |
87 | #define MPP12_M_BB MPP(12, 0x3, 1, 0, 1) | 87 | #define MPP12_M_BB MPP(12, 0x3, 0, 0, 1) |
88 | #define MPP12_UA0_CTSn MPP(12, 0x4, 1, 0, 1) | 88 | #define MPP12_UA0_CTSn MPP(12, 0x4, 0, 0, 1) |
89 | #define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 1, 1) | 89 | #define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 0, 1) |
90 | #define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 1, 1) | 90 | #define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 0, 1) |
91 | #define MPP12_UNUSED MPP(12, 0x1, 0, 0, 1) | 91 | #define MPP12_UNUSED MPP(12, 0x1, 0, 0, 1) |
92 | 92 | ||
93 | #define MPP13_GPIO MPP(13, 0x0, 1, 1, 1) | 93 | #define MPP13_GPIO MPP(13, 0x0, 1, 1, 1) |
94 | #define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 1, 1) | 94 | #define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 0, 1) |
95 | #define MPP13_UA0_RTSn MPP(13, 0x4, 0, 1, 1) | 95 | #define MPP13_UA0_RTSn MPP(13, 0x4, 0, 0, 1) |
96 | #define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 1, 1) | 96 | #define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 0, 1) |
97 | #define MPP13_TDM_SCLK MPP(13, 0x6, 0, 1, 1) | 97 | #define MPP13_TDM_SCLK MPP(13, 0x6, 0, 0, 1) |
98 | #define MPP13_UNUSED MPP(13, 0x1, 0, 0, 1) | 98 | #define MPP13_UNUSED MPP(13, 0x1, 0, 0, 1) |
99 | 99 | ||
100 | #define MPP14_GPIO MPP(14, 0x0, 1, 1, 1) | 100 | #define MPP14_GPIO MPP(14, 0x0, 1, 1, 1) |
101 | #define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 1, 1) | 101 | #define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 0, 1) |
102 | #define MPP14_UA1_CTSn MPP(14, 0x4, 1, 0, 1) | 102 | #define MPP14_UA1_CTSn MPP(14, 0x4, 0, 0, 1) |
103 | #define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 1, 1) | 103 | #define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 0, 1) |
104 | #define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 1, 1) | 104 | #define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 0, 1) |
105 | #define MPP14_UNUSED MPP(14, 0x1, 0, 0, 1) | 105 | #define MPP14_UNUSED MPP(14, 0x1, 0, 0, 1) |
106 | 106 | ||
107 | #define MPP15_GPIO MPP(15, 0x0, 1, 1, 1) | 107 | #define MPP15_GPIO MPP(15, 0x0, 1, 1, 1) |
108 | #define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 1, 1) | 108 | #define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 0, 1) |
109 | #define MPP15_UA1_RTSn MPP(15, 0x4, 0, 1, 1) | 109 | #define MPP15_UA1_RTSn MPP(15, 0x4, 0, 0, 1) |
110 | #define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 1, 1) | 110 | #define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 0, 1) |
111 | #define MPP15_TDM_SMISO MPP(15, 0x6, 1, 0, 1) | 111 | #define MPP15_TDM_SMISO MPP(15, 0x6, 0, 0, 1) |
112 | #define MPP15_UNUSED MPP(15, 0x1, 0, 0, 1) | 112 | #define MPP15_UNUSED MPP(15, 0x1, 0, 0, 1) |
113 | 113 | ||
114 | #define MPP16_GPIO MPP(16, 0x0, 1, 1, 1) | 114 | #define MPP16_GPIO MPP(16, 0x0, 1, 1, 1) |
115 | #define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 1, 1) | 115 | #define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 0, 1) |
116 | #define MPP16_UA2_TXD MPP(16, 0x4, 0, 1, 1) | 116 | #define MPP16_UA2_TXD MPP(16, 0x4, 0, 0, 1) |
117 | #define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 1, 1) | 117 | #define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 0, 1) |
118 | #define MPP16_TDM_INTn MPP(16, 0x6, 1, 0, 1) | 118 | #define MPP16_TDM_INTn MPP(16, 0x6, 0, 0, 1) |
119 | #define MPP16_UNUSED MPP(16, 0x1, 0, 0, 1) | 119 | #define MPP16_UNUSED MPP(16, 0x1, 0, 0, 1) |
120 | 120 | ||
121 | 121 | ||
122 | #define MPP17_GPIO MPP(17, 0x0, 1, 1, 1) | 122 | #define MPP17_GPIO MPP(17, 0x0, 1, 1, 1) |
123 | #define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 1, 1) | 123 | #define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 0, 1) |
124 | #define MPP17_UA2_RXD MPP(17, 0x4, 1, 0, 1) | 124 | #define MPP17_UA2_RXD MPP(17, 0x4, 0, 0, 1) |
125 | #define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 1, 1) | 125 | #define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 0, 1) |
126 | #define MPP17_TDM_RSTn MPP(17, 0x6, 0, 1, 1) | 126 | #define MPP17_TDM_RSTn MPP(17, 0x6, 0, 0, 1) |
127 | #define MPP17_UNUSED MPP(17, 0x1, 0, 0, 1) | 127 | #define MPP17_UNUSED MPP(17, 0x1, 0, 0, 1) |
128 | 128 | ||
129 | 129 | ||
130 | #define MPP18_GPIO MPP(18, 0x0, 1, 1, 1) | 130 | #define MPP18_GPIO MPP(18, 0x0, 1, 1, 1) |
131 | #define MPP18_UA0_CTSn MPP(18, 0x4, 1, 0, 1) | 131 | #define MPP18_UA0_CTSn MPP(18, 0x4, 0, 0, 1) |
132 | #define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 1, 1) | 132 | #define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 0, 1) |
133 | #define MPP18_UNUSED MPP(18, 0x1, 0, 0, 1) | 133 | #define MPP18_UNUSED MPP(18, 0x1, 0, 0, 1) |
134 | 134 | ||
135 | 135 | ||
136 | 136 | ||
137 | #define MPP19_GPIO MPP(19, 0x0, 1, 1, 1) | 137 | #define MPP19_GPIO MPP(19, 0x0, 1, 1, 1) |
138 | #define MPP19_UA0_CTSn MPP(19, 0x4, 0, 1, 1) | 138 | #define MPP19_UA0_CTSn MPP(19, 0x4, 0, 0, 1) |
139 | #define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 1, 1) | 139 | #define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 0, 1) |
140 | #define MPP19_UNUSED MPP(19, 0x1, 0, 0, 1) | 140 | #define MPP19_UNUSED MPP(19, 0x1, 0, 0, 1) |
141 | 141 | ||
142 | 142 | ||
143 | #define MPP20_GPIO MPP(20, 0x0, 1, 1, 1) | 143 | #define MPP20_GPIO MPP(20, 0x0, 1, 1, 1) |
144 | #define MPP20_UA1_CTSs MPP(20, 0x4, 1, 0, 1) | 144 | #define MPP20_UA1_CTSs MPP(20, 0x4, 0, 0, 1) |
145 | #define MPP20_TDM_PCLK MPP(20, 0x6, 1, 1, 0) | 145 | #define MPP20_TDM_PCLK MPP(20, 0x6, 0, 0, 0) |
146 | #define MPP20_UNUSED MPP(20, 0x1, 0, 0, 1) | 146 | #define MPP20_UNUSED MPP(20, 0x1, 0, 0, 1) |
147 | 147 | ||
148 | 148 | ||
149 | 149 | ||
150 | #define MPP21_GPIO MPP(21, 0x0, 1, 1, 1) | 150 | #define MPP21_GPIO MPP(21, 0x0, 1, 1, 1) |
151 | #define MPP21_UA1_CTSs MPP(21, 0x4, 0, 1, 1) | 151 | #define MPP21_UA1_CTSs MPP(21, 0x4, 0, 0, 1) |
152 | #define MPP21_TDM_FSYNC MPP(21, 0x6, 1, 1, 0) | 152 | #define MPP21_TDM_FSYNC MPP(21, 0x6, 0, 0, 0) |
153 | #define MPP21_UNUSED MPP(21, 0x1, 0, 0, 1) | 153 | #define MPP21_UNUSED MPP(21, 0x1, 0, 0, 1) |
154 | 154 | ||
155 | 155 | ||
156 | 156 | ||
157 | #define MPP22_GPIO MPP(22, 0x0, 1, 1, 1) | 157 | #define MPP22_GPIO MPP(22, 0x0, 1, 1, 1) |
158 | #define MPP22_UA3_TDX MPP(22, 0x4, 0, 1, 1) | 158 | #define MPP22_UA3_TDX MPP(22, 0x4, 0, 0, 1) |
159 | #define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 1, 1) | 159 | #define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 0, 1) |
160 | #define MPP22_TDM_DRX MPP(22, 0x6, 1, 0, 1) | 160 | #define MPP22_TDM_DRX MPP(22, 0x6, 0, 0, 1) |
161 | #define MPP22_UNUSED MPP(22, 0x1, 0, 0, 1) | 161 | #define MPP22_UNUSED MPP(22, 0x1, 0, 0, 1) |
162 | 162 | ||
163 | 163 | ||
164 | 164 | ||
165 | #define MPP23_GPIO MPP(23, 0x0, 1, 1, 1) | 165 | #define MPP23_GPIO MPP(23, 0x0, 1, 1, 1) |
166 | #define MPP23_UA3_RDX MPP(23, 0x4, 1, 0, 1) | 166 | #define MPP23_UA3_RDX MPP(23, 0x4, 0, 0, 1) |
167 | #define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 1, 1) | 167 | #define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 0, 1) |
168 | #define MPP23_TDM_DTX MPP(23, 0x6, 0, 1, 1) | 168 | #define MPP23_TDM_DTX MPP(23, 0x6, 0, 0, 1) |
169 | #define MPP23_UNUSED MPP(23, 0x1, 0, 0, 1) | 169 | #define MPP23_UNUSED MPP(23, 0x1, 0, 0, 1) |
170 | 170 | ||
171 | 171 | ||
172 | #define MPP24_GPIO MPP(24, 0x0, 1, 1, 1) | 172 | #define MPP24_GPIO MPP(24, 0x0, 1, 1, 1) |
173 | #define MPP24_UA2_TXD MPP(24, 0x4, 0, 1, 1) | 173 | #define MPP24_UA2_TXD MPP(24, 0x4, 0, 0, 1) |
174 | #define MPP24_TDM_INTn MPP(24, 0x6, 1, 0, 1) | 174 | #define MPP24_TDM_INTn MPP(24, 0x6, 0, 0, 1) |
175 | #define MPP24_UNUSED MPP(24, 0x1, 0, 0, 1) | 175 | #define MPP24_UNUSED MPP(24, 0x1, 0, 0, 1) |
176 | 176 | ||
177 | 177 | ||
178 | #define MPP25_GPIO MPP(25, 0x0, 1, 1, 1) | 178 | #define MPP25_GPIO MPP(25, 0x0, 1, 1, 1) |
179 | #define MPP25_UA2_RXD MPP(25, 0x4, 1, 0, 1) | 179 | #define MPP25_UA2_RXD MPP(25, 0x4, 0, 0, 1) |
180 | #define MPP25_TDM_RSTn MPP(25, 0x6, 0, 1, 1) | 180 | #define MPP25_TDM_RSTn MPP(25, 0x6, 0, 0, 1) |
181 | #define MPP25_UNUSED MPP(25, 0x1, 0, 0, 1) | 181 | #define MPP25_UNUSED MPP(25, 0x1, 0, 0, 1) |
182 | 182 | ||
183 | 183 | ||
184 | #define MPP26_GPIO MPP(26, 0x0, 1, 1, 1) | 184 | #define MPP26_GPIO MPP(26, 0x0, 1, 1, 1) |
185 | #define MPP26_UA2_CTSn MPP(26, 0x4, 1, 0, 1) | 185 | #define MPP26_UA2_CTSn MPP(26, 0x4, 0, 0, 1) |
186 | #define MPP26_TDM_PCLK MPP(26, 0x6, 1, 1, 1) | 186 | #define MPP26_TDM_PCLK MPP(26, 0x6, 0, 0, 1) |
187 | #define MPP26_UNUSED MPP(26, 0x1, 0, 0, 1) | 187 | #define MPP26_UNUSED MPP(26, 0x1, 0, 0, 1) |
188 | 188 | ||
189 | 189 | ||
190 | #define MPP27_GPIO MPP(27, 0x0, 1, 1, 1) | 190 | #define MPP27_GPIO MPP(27, 0x0, 1, 1, 1) |
191 | #define MPP27_UA2_RTSn MPP(27, 0x4, 0, 1, 1) | 191 | #define MPP27_UA2_RTSn MPP(27, 0x4, 0, 0, 1) |
192 | #define MPP27_TDM_FSYNC MPP(27, 0x6, 1, 1, 1) | 192 | #define MPP27_TDM_FSYNC MPP(27, 0x6, 0, 0, 1) |
193 | #define MPP27_UNUSED MPP(27, 0x1, 0, 0, 1) | 193 | #define MPP27_UNUSED MPP(27, 0x1, 0, 0, 1) |
194 | 194 | ||
195 | 195 | ||
196 | #define MPP28_GPIO MPP(28, 0x0, 1, 1, 1) | 196 | #define MPP28_GPIO MPP(28, 0x0, 1, 1, 1) |
197 | #define MPP28_UA3_TXD MPP(28, 0x4, 0, 1, 1) | 197 | #define MPP28_UA3_TXD MPP(28, 0x4, 0, 0, 1) |
198 | #define MPP28_TDM_DRX MPP(28, 0x6, 1, 0, 1) | 198 | #define MPP28_TDM_DRX MPP(28, 0x6, 0, 0, 1) |
199 | #define MPP28_UNUSED MPP(28, 0x1, 0, 0, 1) | 199 | #define MPP28_UNUSED MPP(28, 0x1, 0, 0, 1) |
200 | 200 | ||
201 | #define MPP29_GPIO MPP(29, 0x0, 1, 1, 1) | 201 | #define MPP29_GPIO MPP(29, 0x0, 1, 1, 1) |
202 | #define MPP29_UA3_RXD MPP(29, 0x4, 1, 0, 1) | 202 | #define MPP29_UA3_RXD MPP(29, 0x4, 0, 0, 1) |
203 | #define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 1, 1) | 203 | #define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 0, 1) |
204 | #define MPP29_TDM_DTX MPP(29, 0x6, 0, 1, 1) | 204 | #define MPP29_TDM_DTX MPP(29, 0x6, 0, 0, 1) |
205 | #define MPP29_UNUSED MPP(29, 0x1, 0, 0, 1) | 205 | #define MPP29_UNUSED MPP(29, 0x1, 0, 0, 1) |
206 | 206 | ||
207 | #define MPP30_GPIO MPP(30, 0x0, 1, 1, 1) | 207 | #define MPP30_GPIO MPP(30, 0x0, 1, 1, 1) |
208 | #define MPP30_UA3_CTSn MPP(30, 0x4, 1, 0, 1) | 208 | #define MPP30_UA3_CTSn MPP(30, 0x4, 0, 0, 1) |
209 | #define MPP30_UNUSED MPP(30, 0x1, 0, 0, 1) | 209 | #define MPP30_UNUSED MPP(30, 0x1, 0, 0, 1) |
210 | 210 | ||
211 | #define MPP31_GPIO MPP(31, 0x0, 1, 1, 1) | 211 | #define MPP31_GPIO MPP(31, 0x0, 1, 1, 1) |
212 | #define MPP31_UA3_RTSn MPP(31, 0x4, 0, 1, 1) | 212 | #define MPP31_UA3_RTSn MPP(31, 0x4, 0, 0, 1) |
213 | #define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 1, 1) | 213 | #define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 0, 1) |
214 | #define MPP31_UNUSED MPP(31, 0x1, 0, 0, 1) | 214 | #define MPP31_UNUSED MPP(31, 0x1, 0, 0, 1) |
215 | 215 | ||
216 | 216 | ||
217 | #define MPP32_GPIO MPP(32, 0x1, 1, 1, 1) | 217 | #define MPP32_GPIO MPP(32, 0x1, 1, 1, 1) |
218 | #define MPP32_UA3_TDX MPP(32, 0x4, 0, 1, 1) | 218 | #define MPP32_UA3_TDX MPP(32, 0x4, 0, 0, 1) |
219 | #define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 1, 1) | 219 | #define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 0, 1) |
220 | #define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 1, 1) | 220 | #define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 0, 1) |
221 | #define MPP32_UNUSED MPP(32, 0x3, 0, 0, 1) | 221 | #define MPP32_UNUSED MPP(32, 0x3, 0, 0, 1) |
222 | 222 | ||
223 | 223 | ||
224 | #define MPP33_GPIO MPP(33, 0x1, 1, 1, 1) | 224 | #define MPP33_GPIO MPP(33, 0x1, 1, 1, 1) |
225 | #define MPP33_UA3_RDX MPP(33, 0x4, 1, 0, 1) | 225 | #define MPP33_UA3_RDX MPP(33, 0x4, 0, 0, 1) |
226 | #define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 1, 1) | 226 | #define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 0, 1) |
227 | #define MPP33_UNUSED MPP(33, 0x3, 0, 0, 1) | 227 | #define MPP33_UNUSED MPP(33, 0x3, 0, 0, 1) |
228 | 228 | ||
229 | 229 | ||
230 | 230 | ||
231 | #define MPP34_GPIO MPP(34, 0x1, 1, 1, 1) | 231 | #define MPP34_GPIO MPP(34, 0x1, 1, 1, 1) |
232 | #define MPP34_UA2_TDX MPP(34, 0x4, 0, 1, 1) | 232 | #define MPP34_UA2_TDX MPP(34, 0x4, 0, 0, 1) |
233 | #define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 1, 1) | 233 | #define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 0, 1) |
234 | #define MPP34_UNUSED MPP(34, 0x3, 0, 0, 1) | 234 | #define MPP34_UNUSED MPP(34, 0x3, 0, 0, 1) |
235 | 235 | ||
236 | 236 | ||
237 | 237 | ||
238 | #define MPP35_GPIO MPP(35, 0x1, 1, 1, 1) | 238 | #define MPP35_GPIO MPP(35, 0x1, 1, 1, 1) |
239 | #define MPP35_UA2_RDX MPP(35, 0x4, 1, 0, 1) | 239 | #define MPP35_UA2_RDX MPP(35, 0x4, 0, 0, 1) |
240 | #define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 1, 1) | 240 | #define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 0, 1) |
241 | #define MPP35_UNUSED MPP(35, 0x3, 0, 0, 1) | 241 | #define MPP35_UNUSED MPP(35, 0x3, 0, 0, 1) |
242 | 242 | ||
243 | #define MPP36_GPIO MPP(36, 0x1, 1, 1, 1) | 243 | #define MPP36_GPIO MPP(36, 0x1, 1, 1, 1) |
244 | #define MPP36_UA0_CTSn MPP(36, 0x2, 1, 0, 1) | 244 | #define MPP36_UA0_CTSn MPP(36, 0x2, 0, 0, 1) |
245 | #define MPP36_UA2_TDX MPP(36, 0x4, 0, 1, 1) | 245 | #define MPP36_UA2_TDX MPP(36, 0x4, 0, 0, 1) |
246 | #define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 1, 1) | 246 | #define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 0, 1) |
247 | #define MPP36_UNUSED MPP(36, 0x3, 0, 0, 1) | 247 | #define MPP36_UNUSED MPP(36, 0x3, 0, 0, 1) |
248 | 248 | ||
249 | 249 | ||
250 | #define MPP37_GPIO MPP(37, 0x1, 1, 1, 1) | 250 | #define MPP37_GPIO MPP(37, 0x1, 1, 1, 1) |
251 | #define MPP37_UA0_RTSn MPP(37, 0x2, 0, 1, 1) | 251 | #define MPP37_UA0_RTSn MPP(37, 0x2, 0, 0, 1) |
252 | #define MPP37_UA2_RXD MPP(37, 0x4, 1, 0, 1) | 252 | #define MPP37_UA2_RXD MPP(37, 0x4, 0, 0, 1) |
253 | #define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 1, 1) | 253 | #define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 0, 1) |
254 | #define MPP37_TDM_SCLK MPP(37, 0x6, 0, 1, 1) | 254 | #define MPP37_TDM_SCLK MPP(37, 0x6, 0, 0, 1) |
255 | #define MPP37_UNUSED MPP(37, 0x3, 0, 0, 1) | 255 | #define MPP37_UNUSED MPP(37, 0x3, 0, 0, 1) |
256 | 256 | ||
257 | 257 | ||
258 | 258 | ||
259 | 259 | ||
260 | #define MPP38_GPIO MPP(38, 0x1, 1, 1, 1) | 260 | #define MPP38_GPIO MPP(38, 0x1, 1, 1, 1) |
261 | #define MPP38_UA1_CTSn MPP(38, 0x2, 1, 0, 1) | 261 | #define MPP38_UA1_CTSn MPP(38, 0x2, 0, 0, 1) |
262 | #define MPP38_UA3_TXD MPP(38, 0x4, 0, 1, 1) | 262 | #define MPP38_UA3_TXD MPP(38, 0x4, 0, 0, 1) |
263 | #define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 1, 1) | 263 | #define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 0, 1) |
264 | #define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 1, 1) | 264 | #define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 0, 1) |
265 | #define MPP38_UNUSED MPP(38, 0x3, 0, 0, 1) | 265 | #define MPP38_UNUSED MPP(38, 0x3, 0, 0, 1) |
266 | 266 | ||
267 | 267 | ||
268 | 268 | ||
269 | 269 | ||
270 | #define MPP39_GPIO MPP(39, 0x1, 1, 1, 1) | 270 | #define MPP39_GPIO MPP(39, 0x1, 1, 1, 1) |
271 | #define MPP39_UA1_RTSn MPP(39, 0x2, 0, 1, 1) | 271 | #define MPP39_UA1_RTSn MPP(39, 0x2, 0, 0, 1) |
272 | #define MPP39_UA3_RXD MPP(39, 0x4, 1, 0, 1) | 272 | #define MPP39_UA3_RXD MPP(39, 0x4, 0, 0, 1) |
273 | #define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 1, 1) | 273 | #define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 0, 1) |
274 | #define MPP39_TDM_SMISO MPP(39, 0x6, 1, 0, 1) | 274 | #define MPP39_TDM_SMISO MPP(39, 0x6, 0, 0, 1) |
275 | #define MPP39_UNUSED MPP(39, 0x3, 0, 0, 1) | 275 | #define MPP39_UNUSED MPP(39, 0x3, 0, 0, 1) |
276 | 276 | ||
277 | 277 | ||
278 | 278 | ||
279 | #define MPP40_GPIO MPP(40, 0x1, 1, 1, 1) | 279 | #define MPP40_GPIO MPP(40, 0x1, 1, 1, 1) |
280 | #define MPP40_TDM_INTn MPP(40, 0x6, 1, 0, 1) | 280 | #define MPP40_TDM_INTn MPP(40, 0x6, 0, 0, 1) |
281 | #define MPP40_UNUSED MPP(40, 0x0, 0, 0, 1) | 281 | #define MPP40_UNUSED MPP(40, 0x0, 0, 0, 1) |
282 | 282 | ||
283 | 283 | ||
284 | 284 | ||
285 | #define MPP41_GPIO MPP(41, 0x1, 1, 1, 1) | 285 | #define MPP41_GPIO MPP(41, 0x1, 1, 1, 1) |
286 | #define MPP41_TDM_RSTn MPP(41, 0x6, 0, 1, 1) | 286 | #define MPP41_TDM_RSTn MPP(41, 0x6, 0, 0, 1) |
287 | #define MPP41_UNUSED MPP(41, 0x0, 0, 0, 1) | 287 | #define MPP41_UNUSED MPP(41, 0x0, 0, 0, 1) |
288 | 288 | ||
289 | 289 | ||
290 | 290 | ||
291 | #define MPP42_GPIO MPP(42, 0x1, 1, 1, 1) | 291 | #define MPP42_GPIO MPP(42, 0x1, 1, 1, 1) |
292 | #define MPP42_TDM_PCLK MPP(42, 0x6, 1, 1, 1) | 292 | #define MPP42_TDM_PCLK MPP(42, 0x6, 0, 0, 1) |
293 | #define MPP42_UNUSED MPP(42, 0x0, 0, 0, 1) | 293 | #define MPP42_UNUSED MPP(42, 0x0, 0, 0, 1) |
294 | 294 | ||
295 | 295 | ||
296 | 296 | ||
297 | #define MPP43_GPIO MPP(43, 0x1, 1, 1, 1) | 297 | #define MPP43_GPIO MPP(43, 0x1, 1, 1, 1) |
298 | #define MPP43_TDM_FSYNC MPP(43, 0x6, 1, 1, 1) | 298 | #define MPP43_TDM_FSYNC MPP(43, 0x6, 0, 0, 1) |
299 | #define MPP43_UNUSED MPP(43, 0x0, 0, 0, 1) | 299 | #define MPP43_UNUSED MPP(43, 0x0, 0, 0, 1) |
300 | 300 | ||
301 | 301 | ||
302 | 302 | ||
303 | #define MPP44_GPIO MPP(44, 0x1, 1, 1, 1) | 303 | #define MPP44_GPIO MPP(44, 0x1, 1, 1, 1) |
304 | #define MPP44_TDM_DRX MPP(44, 0x6, 1, 0, 1) | 304 | #define MPP44_TDM_DRX MPP(44, 0x6, 0, 0, 1) |
305 | #define MPP44_UNUSED MPP(44, 0x0, 0, 0, 1) | 305 | #define MPP44_UNUSED MPP(44, 0x0, 0, 0, 1) |
306 | 306 | ||
307 | 307 | ||
308 | 308 | ||
309 | #define MPP45_GPIO MPP(45, 0x1, 1, 1, 1) | 309 | #define MPP45_GPIO MPP(45, 0x1, 1, 1, 1) |
310 | #define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 1, 1) | 310 | #define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 0, 1) |
311 | #define MPP45_TDM_DRX MPP(45, 0x6, 0, 1, 1) | 311 | #define MPP45_TDM_DRX MPP(45, 0x6, 0, 0, 1) |
312 | #define MPP45_UNUSED MPP(45, 0x0, 0, 0, 1) | 312 | #define MPP45_UNUSED MPP(45, 0x0, 0, 0, 1) |
313 | 313 | ||
314 | 314 | ||
315 | #define MPP46_GPIO MPP(46, 0x1, 1, 1, 1) | 315 | #define MPP46_GPIO MPP(46, 0x1, 1, 1, 1) |
316 | #define MPP46_TDM_SCSn MPP(46, 0x6, 0, 1, 1) | 316 | #define MPP46_TDM_SCSn MPP(46, 0x6, 0, 0, 1) |
317 | #define MPP46_UNUSED MPP(46, 0x0, 0, 0, 1) | 317 | #define MPP46_UNUSED MPP(46, 0x0, 0, 0, 1) |
318 | 318 | ||
319 | 319 | ||
@@ -323,14 +323,14 @@ | |||
323 | 323 | ||
324 | 324 | ||
325 | #define MPP48_GPIO MPP(48, 0x1, 1, 1, 1) | 325 | #define MPP48_GPIO MPP(48, 0x1, 1, 1, 1) |
326 | #define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 1, 1) | 326 | #define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 0, 1) |
327 | #define MPP48_UNUSED MPP(48, 0x2, 0, 0, 1) | 327 | #define MPP48_UNUSED MPP(48, 0x2, 0, 0, 1) |
328 | 328 | ||
329 | 329 | ||
330 | 330 | ||
331 | #define MPP49_GPIO MPP(49, 0x1, 1, 1, 1) | 331 | #define MPP49_GPIO MPP(49, 0x1, 1, 1, 1) |
332 | #define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 1, 1) | 332 | #define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 0, 1) |
333 | #define MPP49_M_BB MPP(49, 0x4, 1, 0, 1) | 333 | #define MPP49_M_BB MPP(49, 0x4, 0, 0, 1) |
334 | #define MPP49_UNUSED MPP(49, 0x2, 0, 0, 1) | 334 | #define MPP49_UNUSED MPP(49, 0x2, 0, 0, 1) |
335 | 335 | ||
336 | 336 | ||
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig deleted file mode 100644 index af0c212e3c7b..000000000000 --- a/arch/arm/mach-mx5/Kconfig +++ /dev/null | |||
@@ -1,244 +0,0 @@ | |||
1 | if ARCH_MX5 | ||
2 | |||
3 | # ARCH_MX5/50/53 are left to mark places where prevent multi-soc in single | ||
4 | # image. So for most time, SOC_IMX50/51/53 should be used. | ||
5 | |||
6 | config ARCH_MX51 | ||
7 | bool | ||
8 | |||
9 | config ARCH_MX50 | ||
10 | bool | ||
11 | |||
12 | config ARCH_MX53 | ||
13 | bool | ||
14 | |||
15 | config SOC_IMX50 | ||
16 | bool | ||
17 | select CPU_V7 | ||
18 | select ARM_L1_CACHE_SHIFT_6 | ||
19 | select MXC_TZIC | ||
20 | select ARCH_MXC_IOMUX_V3 | ||
21 | select ARCH_MXC_AUDMUX_V2 | ||
22 | select ARCH_HAS_CPUFREQ | ||
23 | select ARCH_MX50 | ||
24 | |||
25 | config SOC_IMX51 | ||
26 | bool | ||
27 | select CPU_V7 | ||
28 | select ARM_L1_CACHE_SHIFT_6 | ||
29 | select MXC_TZIC | ||
30 | select ARCH_MXC_IOMUX_V3 | ||
31 | select ARCH_MXC_AUDMUX_V2 | ||
32 | select ARCH_HAS_CPUFREQ | ||
33 | select ARCH_MX51 | ||
34 | |||
35 | config SOC_IMX53 | ||
36 | bool | ||
37 | select CPU_V7 | ||
38 | select ARM_L1_CACHE_SHIFT_6 | ||
39 | select MXC_TZIC | ||
40 | select ARCH_MXC_IOMUX_V3 | ||
41 | select ARCH_MX53 | ||
42 | |||
43 | #comment "i.MX50 machines:" | ||
44 | |||
45 | config MACH_MX50_RDP | ||
46 | bool "Support MX50 reference design platform" | ||
47 | depends on BROKEN | ||
48 | select SOC_IMX50 | ||
49 | select IMX_HAVE_PLATFORM_IMX_I2C | ||
50 | select IMX_HAVE_PLATFORM_IMX_UART | ||
51 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
52 | select IMX_HAVE_PLATFORM_SPI_IMX | ||
53 | help | ||
54 | Include support for MX50 reference design platform (RDP) board. This | ||
55 | includes specific configurations for the board and its peripherals. | ||
56 | |||
57 | comment "i.MX51 machines:" | ||
58 | |||
59 | config MACH_IMX51_DT | ||
60 | bool "Support i.MX51 platforms from device tree" | ||
61 | select SOC_IMX51 | ||
62 | select USE_OF | ||
63 | select MACH_MX51_BABBAGE | ||
64 | help | ||
65 | Include support for Freescale i.MX51 based platforms | ||
66 | using the device tree for discovery | ||
67 | |||
68 | config MACH_MX51_BABBAGE | ||
69 | bool "Support MX51 BABBAGE platforms" | ||
70 | select SOC_IMX51 | ||
71 | select IMX_HAVE_PLATFORM_FSL_USB2_UDC | ||
72 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
73 | select IMX_HAVE_PLATFORM_IMX_I2C | ||
74 | select IMX_HAVE_PLATFORM_IMX_UART | ||
75 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
76 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
77 | select IMX_HAVE_PLATFORM_SPI_IMX | ||
78 | help | ||
79 | Include support for MX51 Babbage platform, also known as MX51EVK in | ||
80 | u-boot. This includes specific configurations for the board and its | ||
81 | peripherals. | ||
82 | |||
83 | config MACH_MX51_3DS | ||
84 | bool "Support MX51PDK (3DS)" | ||
85 | select SOC_IMX51 | ||
86 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
87 | select IMX_HAVE_PLATFORM_IMX_KEYPAD | ||
88 | select IMX_HAVE_PLATFORM_IMX_UART | ||
89 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
90 | select IMX_HAVE_PLATFORM_SPI_IMX | ||
91 | select MXC_DEBUG_BOARD | ||
92 | help | ||
93 | Include support for MX51PDK (3DS) platform. This includes specific | ||
94 | configurations for the board and its peripherals. | ||
95 | |||
96 | config MACH_EUKREA_CPUIMX51 | ||
97 | bool "Support Eukrea CPUIMX51 module" | ||
98 | select SOC_IMX51 | ||
99 | select IMX_HAVE_PLATFORM_FSL_USB2_UDC | ||
100 | select IMX_HAVE_PLATFORM_IMX_I2C | ||
101 | select IMX_HAVE_PLATFORM_IMX_UART | ||
102 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
103 | select IMX_HAVE_PLATFORM_MXC_NAND | ||
104 | select IMX_HAVE_PLATFORM_SPI_IMX | ||
105 | help | ||
106 | Include support for Eukrea CPUIMX51 platform. This includes | ||
107 | specific configurations for the module and its peripherals. | ||
108 | |||
109 | choice | ||
110 | prompt "Baseboard" | ||
111 | depends on MACH_EUKREA_CPUIMX51 | ||
112 | default MACH_EUKREA_MBIMX51_BASEBOARD | ||
113 | |||
114 | config MACH_EUKREA_MBIMX51_BASEBOARD | ||
115 | prompt "Eukrea MBIMX51 development board" | ||
116 | bool | ||
117 | select IMX_HAVE_PLATFORM_IMX_KEYPAD | ||
118 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
119 | select LEDS_GPIO_REGISTER | ||
120 | help | ||
121 | This adds board specific devices that can be found on Eukrea's | ||
122 | MBIMX51 evaluation board. | ||
123 | |||
124 | endchoice | ||
125 | |||
126 | config MACH_EUKREA_CPUIMX51SD | ||
127 | bool "Support Eukrea CPUIMX51SD module" | ||
128 | select SOC_IMX51 | ||
129 | select IMX_HAVE_PLATFORM_FSL_USB2_UDC | ||
130 | select IMX_HAVE_PLATFORM_IMX_I2C | ||
131 | select IMX_HAVE_PLATFORM_IMX_UART | ||
132 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
133 | select IMX_HAVE_PLATFORM_MXC_NAND | ||
134 | select IMX_HAVE_PLATFORM_SPI_IMX | ||
135 | help | ||
136 | Include support for Eukrea CPUIMX51SD platform. This includes | ||
137 | specific configurations for the module and its peripherals. | ||
138 | |||
139 | choice | ||
140 | prompt "Baseboard" | ||
141 | depends on MACH_EUKREA_CPUIMX51SD | ||
142 | default MACH_EUKREA_MBIMXSD51_BASEBOARD | ||
143 | |||
144 | config MACH_EUKREA_MBIMXSD51_BASEBOARD | ||
145 | prompt "Eukrea MBIMXSD development board" | ||
146 | bool | ||
147 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
148 | select LEDS_GPIO_REGISTER | ||
149 | help | ||
150 | This adds board specific devices that can be found on Eukrea's | ||
151 | MBIMXSD evaluation board. | ||
152 | |||
153 | endchoice | ||
154 | |||
155 | config MX51_EFIKA_COMMON | ||
156 | bool | ||
157 | select SOC_IMX51 | ||
158 | select IMX_HAVE_PLATFORM_IMX_UART | ||
159 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
160 | select IMX_HAVE_PLATFORM_PATA_IMX | ||
161 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
162 | select IMX_HAVE_PLATFORM_SPI_IMX | ||
163 | select MXC_ULPI if USB_ULPI | ||
164 | |||
165 | config MACH_MX51_EFIKAMX | ||
166 | bool "Support MX51 Genesi Efika MX nettop" | ||
167 | select LEDS_GPIO_REGISTER | ||
168 | select MX51_EFIKA_COMMON | ||
169 | help | ||
170 | Include support for Genesi Efika MX nettop. This includes specific | ||
171 | configurations for the board and its peripherals. | ||
172 | |||
173 | config MACH_MX51_EFIKASB | ||
174 | bool "Support MX51 Genesi Efika Smartbook" | ||
175 | select LEDS_GPIO_REGISTER | ||
176 | select MX51_EFIKA_COMMON | ||
177 | help | ||
178 | Include support for Genesi Efika Smartbook. This includes specific | ||
179 | configurations for the board and its peripherals. | ||
180 | |||
181 | comment "i.MX53 machines:" | ||
182 | |||
183 | config MACH_IMX53_DT | ||
184 | bool "Support i.MX53 platforms from device tree" | ||
185 | select SOC_IMX53 | ||
186 | select USE_OF | ||
187 | select MACH_MX53_ARD | ||
188 | select MACH_MX53_EVK | ||
189 | select MACH_MX53_LOCO | ||
190 | select MACH_MX53_SMD | ||
191 | help | ||
192 | Include support for Freescale i.MX53 based platforms | ||
193 | using the device tree for discovery | ||
194 | |||
195 | config MACH_MX53_EVK | ||
196 | bool "Support MX53 EVK platforms" | ||
197 | select SOC_IMX53 | ||
198 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
199 | select IMX_HAVE_PLATFORM_IMX_UART | ||
200 | select IMX_HAVE_PLATFORM_IMX_I2C | ||
201 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
202 | select IMX_HAVE_PLATFORM_SPI_IMX | ||
203 | select LEDS_GPIO_REGISTER | ||
204 | help | ||
205 | Include support for MX53 EVK platform. This includes specific | ||
206 | configurations for the board and its peripherals. | ||
207 | |||
208 | config MACH_MX53_SMD | ||
209 | bool "Support MX53 SMD platforms" | ||
210 | select SOC_IMX53 | ||
211 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
212 | select IMX_HAVE_PLATFORM_IMX_I2C | ||
213 | select IMX_HAVE_PLATFORM_IMX_UART | ||
214 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
215 | help | ||
216 | Include support for MX53 SMD platform. This includes specific | ||
217 | configurations for the board and its peripherals. | ||
218 | |||
219 | config MACH_MX53_LOCO | ||
220 | bool "Support MX53 LOCO platforms" | ||
221 | select SOC_IMX53 | ||
222 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
223 | select IMX_HAVE_PLATFORM_IMX_I2C | ||
224 | select IMX_HAVE_PLATFORM_IMX_UART | ||
225 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
226 | select IMX_HAVE_PLATFORM_GPIO_KEYS | ||
227 | select LEDS_GPIO_REGISTER | ||
228 | help | ||
229 | Include support for MX53 LOCO platform. This includes specific | ||
230 | configurations for the board and its peripherals. | ||
231 | |||
232 | config MACH_MX53_ARD | ||
233 | bool "Support MX53 ARD platforms" | ||
234 | select SOC_IMX53 | ||
235 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
236 | select IMX_HAVE_PLATFORM_IMX_I2C | ||
237 | select IMX_HAVE_PLATFORM_IMX_UART | ||
238 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
239 | select IMX_HAVE_PLATFORM_GPIO_KEYS | ||
240 | help | ||
241 | Include support for MX53 ARD platform. This includes specific | ||
242 | configurations for the board and its peripherals. | ||
243 | |||
244 | endif | ||
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile deleted file mode 100644 index 0fc60807fa2b..000000000000 --- a/arch/arm/mach-mx5/Makefile +++ /dev/null | |||
@@ -1,26 +0,0 @@ | |||
1 | # | ||
2 | # Makefile for the linux kernel. | ||
3 | # | ||
4 | |||
5 | # Object file lists. | ||
6 | obj-y := cpu.o mm.o clock-mx51-mx53.o ehci.o system.o | ||
7 | |||
8 | obj-$(CONFIG_PM) += pm-imx5.o | ||
9 | obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o | ||
10 | obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o | ||
11 | obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o | ||
12 | obj-$(CONFIG_MACH_MX53_EVK) += board-mx53_evk.o | ||
13 | obj-$(CONFIG_MACH_MX53_SMD) += board-mx53_smd.o | ||
14 | obj-$(CONFIG_MACH_MX53_LOCO) += board-mx53_loco.o | ||
15 | obj-$(CONFIG_MACH_MX53_ARD) += board-mx53_ard.o | ||
16 | obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o | ||
17 | obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o | ||
18 | obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o | ||
19 | obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o | ||
20 | obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o | ||
21 | obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o | ||
22 | obj-$(CONFIG_MACH_MX51_EFIKASB) += board-mx51_efikasb.o | ||
23 | obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o | ||
24 | |||
25 | obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o | ||
26 | obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o | ||
diff --git a/arch/arm/mach-mx5/Makefile.boot b/arch/arm/mach-mx5/Makefile.boot deleted file mode 100644 index ca207ca305ec..000000000000 --- a/arch/arm/mach-mx5/Makefile.boot +++ /dev/null | |||
@@ -1,9 +0,0 @@ | |||
1 | zreladdr-$(CONFIG_ARCH_MX50) += 0x70008000 | ||
2 | params_phys-$(CONFIG_ARCH_MX50) := 0x70000100 | ||
3 | initrd_phys-$(CONFIG_ARCH_MX50) := 0x70800000 | ||
4 | zreladdr-$(CONFIG_ARCH_MX51) += 0x90008000 | ||
5 | params_phys-$(CONFIG_ARCH_MX51) := 0x90000100 | ||
6 | initrd_phys-$(CONFIG_ARCH_MX51) := 0x90800000 | ||
7 | zreladdr-$(CONFIG_ARCH_MX53) += 0x70008000 | ||
8 | params_phys-$(CONFIG_ARCH_MX53) := 0x70000100 | ||
9 | initrd_phys-$(CONFIG_ARCH_MX53) := 0x70800000 | ||
diff --git a/arch/arm/mach-mx5/pm-imx5.c b/arch/arm/mach-mx5/pm-imx5.c deleted file mode 100644 index 98052fc852c7..000000000000 --- a/arch/arm/mach-mx5/pm-imx5.c +++ /dev/null | |||
@@ -1,83 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
3 | * | ||
4 | * The code contained herein is licensed under the GNU General Public | ||
5 | * License. You may obtain a copy of the GNU General Public License | ||
6 | * Version 2 or later at the following locations: | ||
7 | * | ||
8 | * http://www.opensource.org/licenses/gpl-license.html | ||
9 | * http://www.gnu.org/copyleft/gpl.html | ||
10 | */ | ||
11 | #include <linux/suspend.h> | ||
12 | #include <linux/clk.h> | ||
13 | #include <linux/io.h> | ||
14 | #include <linux/err.h> | ||
15 | #include <asm/cacheflush.h> | ||
16 | #include <asm/tlbflush.h> | ||
17 | #include <mach/common.h> | ||
18 | #include <mach/hardware.h> | ||
19 | #include "crm_regs.h" | ||
20 | |||
21 | static struct clk *gpc_dvfs_clk; | ||
22 | |||
23 | static int mx5_suspend_prepare(void) | ||
24 | { | ||
25 | return clk_enable(gpc_dvfs_clk); | ||
26 | } | ||
27 | |||
28 | static int mx5_suspend_enter(suspend_state_t state) | ||
29 | { | ||
30 | switch (state) { | ||
31 | case PM_SUSPEND_MEM: | ||
32 | mx5_cpu_lp_set(STOP_POWER_OFF); | ||
33 | break; | ||
34 | case PM_SUSPEND_STANDBY: | ||
35 | mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); | ||
36 | break; | ||
37 | default: | ||
38 | return -EINVAL; | ||
39 | } | ||
40 | |||
41 | if (state == PM_SUSPEND_MEM) { | ||
42 | local_flush_tlb_all(); | ||
43 | flush_cache_all(); | ||
44 | |||
45 | /*clear the EMPGC0/1 bits */ | ||
46 | __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR); | ||
47 | __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); | ||
48 | } | ||
49 | cpu_do_idle(); | ||
50 | return 0; | ||
51 | } | ||
52 | |||
53 | static void mx5_suspend_finish(void) | ||
54 | { | ||
55 | clk_disable(gpc_dvfs_clk); | ||
56 | } | ||
57 | |||
58 | static int mx5_pm_valid(suspend_state_t state) | ||
59 | { | ||
60 | return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX); | ||
61 | } | ||
62 | |||
63 | static const struct platform_suspend_ops mx5_suspend_ops = { | ||
64 | .valid = mx5_pm_valid, | ||
65 | .prepare = mx5_suspend_prepare, | ||
66 | .enter = mx5_suspend_enter, | ||
67 | .finish = mx5_suspend_finish, | ||
68 | }; | ||
69 | |||
70 | static int __init mx5_pm_init(void) | ||
71 | { | ||
72 | if (gpc_dvfs_clk == NULL) | ||
73 | gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs"); | ||
74 | |||
75 | if (!IS_ERR(gpc_dvfs_clk)) { | ||
76 | if (cpu_is_mx51()) | ||
77 | suspend_set_ops(&mx5_suspend_ops); | ||
78 | } else | ||
79 | return -EPERM; | ||
80 | |||
81 | return 0; | ||
82 | } | ||
83 | device_initcall(mx5_pm_init); | ||
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index a8ba7b96dcd1..d965da45160e 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig | |||
@@ -33,7 +33,6 @@ config ARCH_OMAP3 | |||
33 | default y | 33 | default y |
34 | select CPU_V7 | 34 | select CPU_V7 |
35 | select USB_ARCH_HAS_EHCI | 35 | select USB_ARCH_HAS_EHCI |
36 | select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4 | ||
37 | select ARCH_HAS_OPP | 36 | select ARCH_HAS_OPP |
38 | select PM_OPP if PM | 37 | select PM_OPP if PM |
39 | select ARM_CPU_SUSPEND if PM | 38 | select ARM_CPU_SUSPEND if PM |
@@ -214,13 +213,12 @@ config MACH_OMAP3_PANDORA | |||
214 | depends on ARCH_OMAP3 | 213 | depends on ARCH_OMAP3 |
215 | default y | 214 | default y |
216 | select OMAP_PACKAGE_CBB | 215 | select OMAP_PACKAGE_CBB |
217 | select REGULATOR_FIXED_VOLTAGE | 216 | select REGULATOR_FIXED_VOLTAGE if REGULATOR |
218 | 217 | ||
219 | config MACH_OMAP3_TOUCHBOOK | 218 | config MACH_OMAP3_TOUCHBOOK |
220 | bool "OMAP3 Touch Book" | 219 | bool "OMAP3 Touch Book" |
221 | depends on ARCH_OMAP3 | 220 | depends on ARCH_OMAP3 |
222 | default y | 221 | default y |
223 | select BACKLIGHT_CLASS_DEVICE | ||
224 | 222 | ||
225 | config MACH_OMAP_3430SDP | 223 | config MACH_OMAP_3430SDP |
226 | bool "OMAP 3430 SDP board" | 224 | bool "OMAP 3430 SDP board" |
@@ -266,7 +264,7 @@ config MACH_OMAP_ZOOM2 | |||
266 | select SERIAL_8250 | 264 | select SERIAL_8250 |
267 | select SERIAL_CORE_CONSOLE | 265 | select SERIAL_CORE_CONSOLE |
268 | select SERIAL_8250_CONSOLE | 266 | select SERIAL_8250_CONSOLE |
269 | select REGULATOR_FIXED_VOLTAGE | 267 | select REGULATOR_FIXED_VOLTAGE if REGULATOR |
270 | 268 | ||
271 | config MACH_OMAP_ZOOM3 | 269 | config MACH_OMAP_ZOOM3 |
272 | bool "OMAP3630 Zoom3 board" | 270 | bool "OMAP3630 Zoom3 board" |
@@ -276,7 +274,7 @@ config MACH_OMAP_ZOOM3 | |||
276 | select SERIAL_8250 | 274 | select SERIAL_8250 |
277 | select SERIAL_CORE_CONSOLE | 275 | select SERIAL_CORE_CONSOLE |
278 | select SERIAL_8250_CONSOLE | 276 | select SERIAL_8250_CONSOLE |
279 | select REGULATOR_FIXED_VOLTAGE | 277 | select REGULATOR_FIXED_VOLTAGE if REGULATOR |
280 | 278 | ||
281 | config MACH_CM_T35 | 279 | config MACH_CM_T35 |
282 | bool "CompuLab CM-T35/CM-T3730 modules" | 280 | bool "CompuLab CM-T35/CM-T3730 modules" |
@@ -335,7 +333,7 @@ config MACH_OMAP_4430SDP | |||
335 | depends on ARCH_OMAP4 | 333 | depends on ARCH_OMAP4 |
336 | select OMAP_PACKAGE_CBL | 334 | select OMAP_PACKAGE_CBL |
337 | select OMAP_PACKAGE_CBS | 335 | select OMAP_PACKAGE_CBS |
338 | select REGULATOR_FIXED_VOLTAGE | 336 | select REGULATOR_FIXED_VOLTAGE if REGULATOR |
339 | 337 | ||
340 | config MACH_OMAP4_PANDA | 338 | config MACH_OMAP4_PANDA |
341 | bool "OMAP4 Panda Board" | 339 | bool "OMAP4 Panda Board" |
@@ -343,7 +341,7 @@ config MACH_OMAP4_PANDA | |||
343 | depends on ARCH_OMAP4 | 341 | depends on ARCH_OMAP4 |
344 | select OMAP_PACKAGE_CBL | 342 | select OMAP_PACKAGE_CBL |
345 | select OMAP_PACKAGE_CBS | 343 | select OMAP_PACKAGE_CBS |
346 | select REGULATOR_FIXED_VOLTAGE | 344 | select REGULATOR_FIXED_VOLTAGE if REGULATOR |
347 | 345 | ||
348 | config OMAP3_EMU | 346 | config OMAP3_EMU |
349 | bool "OMAP3 debugging peripherals" | 347 | bool "OMAP3 debugging peripherals" |
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index fc9b238cbc19..bd76394ccaf8 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile | |||
@@ -11,9 +11,9 @@ hwmod-common = omap_hwmod.o \ | |||
11 | omap_hwmod_common_data.o | 11 | omap_hwmod_common_data.o |
12 | clock-common = clock.o clock_common_data.o \ | 12 | clock-common = clock.o clock_common_data.o \ |
13 | clkt_dpll.o clkt_clksel.o | 13 | clkt_dpll.o clkt_clksel.o |
14 | secure-common = omap-smc.o omap-secure.o | 14 | secure-common = omap-smc.o omap-secure.o |
15 | 15 | ||
16 | obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) $(secure-common) | 16 | obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) |
17 | obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) | 17 | obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) |
18 | obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) | 18 | obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) |
19 | 19 | ||
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 39fba9df17fb..4e9071589bfb 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c | |||
@@ -52,8 +52,9 @@ | |||
52 | #define ETH_KS8851_QUART 138 | 52 | #define ETH_KS8851_QUART 138 |
53 | #define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184 | 53 | #define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184 |
54 | #define OMAP4_SFH7741_ENABLE_GPIO 188 | 54 | #define OMAP4_SFH7741_ENABLE_GPIO 188 |
55 | #define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */ | 55 | #define HDMI_GPIO_CT_CP_HPD 60 /* HPD mode enable/disable */ |
56 | #define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */ | 56 | #define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */ |
57 | #define HDMI_GPIO_HPD 63 /* Hotplug detect */ | ||
57 | #define DISPLAY_SEL_GPIO 59 /* LCD2/PicoDLP switch */ | 58 | #define DISPLAY_SEL_GPIO 59 /* LCD2/PicoDLP switch */ |
58 | #define DLP_POWER_ON_GPIO 40 | 59 | #define DLP_POWER_ON_GPIO 40 |
59 | 60 | ||
@@ -603,8 +604,9 @@ static void __init omap_sfh7741prox_init(void) | |||
603 | } | 604 | } |
604 | 605 | ||
605 | static struct gpio sdp4430_hdmi_gpios[] = { | 606 | static struct gpio sdp4430_hdmi_gpios[] = { |
606 | { HDMI_GPIO_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_hpd" }, | 607 | { HDMI_GPIO_CT_CP_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ct_cp_hpd" }, |
607 | { HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" }, | 608 | { HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" }, |
609 | { HDMI_GPIO_HPD, GPIOF_DIR_IN, "hdmi_gpio_hpd" }, | ||
608 | }; | 610 | }; |
609 | 611 | ||
610 | static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev) | 612 | static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev) |
@@ -621,8 +623,7 @@ static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev) | |||
621 | 623 | ||
622 | static void sdp4430_panel_disable_hdmi(struct omap_dss_device *dssdev) | 624 | static void sdp4430_panel_disable_hdmi(struct omap_dss_device *dssdev) |
623 | { | 625 | { |
624 | gpio_free(HDMI_GPIO_LS_OE); | 626 | gpio_free_array(sdp4430_hdmi_gpios, ARRAY_SIZE(sdp4430_hdmi_gpios)); |
625 | gpio_free(HDMI_GPIO_HPD); | ||
626 | } | 627 | } |
627 | 628 | ||
628 | static struct nokia_dsi_panel_data dsi1_panel = { | 629 | static struct nokia_dsi_panel_data dsi1_panel = { |
@@ -738,6 +739,10 @@ static void sdp4430_lcd_init(void) | |||
738 | pr_err("%s: Could not get lcd2_reset_gpio\n", __func__); | 739 | pr_err("%s: Could not get lcd2_reset_gpio\n", __func__); |
739 | } | 740 | } |
740 | 741 | ||
742 | static struct omap_dss_hdmi_data sdp4430_hdmi_data = { | ||
743 | .hpd_gpio = HDMI_GPIO_HPD, | ||
744 | }; | ||
745 | |||
741 | static struct omap_dss_device sdp4430_hdmi_device = { | 746 | static struct omap_dss_device sdp4430_hdmi_device = { |
742 | .name = "hdmi", | 747 | .name = "hdmi", |
743 | .driver_name = "hdmi_panel", | 748 | .driver_name = "hdmi_panel", |
@@ -745,6 +750,7 @@ static struct omap_dss_device sdp4430_hdmi_device = { | |||
745 | .platform_enable = sdp4430_panel_enable_hdmi, | 750 | .platform_enable = sdp4430_panel_enable_hdmi, |
746 | .platform_disable = sdp4430_panel_disable_hdmi, | 751 | .platform_disable = sdp4430_panel_disable_hdmi, |
747 | .channel = OMAP_DSS_CHANNEL_DIGIT, | 752 | .channel = OMAP_DSS_CHANNEL_DIGIT, |
753 | .data = &sdp4430_hdmi_data, | ||
748 | }; | 754 | }; |
749 | 755 | ||
750 | static struct picodlp_panel_data sdp4430_picodlp_pdata = { | 756 | static struct picodlp_panel_data sdp4430_picodlp_pdata = { |
@@ -808,7 +814,7 @@ static struct omap_dss_board_info sdp4430_dss_data = { | |||
808 | .default_device = &sdp4430_lcd_device, | 814 | .default_device = &sdp4430_lcd_device, |
809 | }; | 815 | }; |
810 | 816 | ||
811 | static void omap_4430sdp_display_init(void) | 817 | static void __init omap_4430sdp_display_init(void) |
812 | { | 818 | { |
813 | int r; | 819 | int r; |
814 | 820 | ||
@@ -829,6 +835,10 @@ static void omap_4430sdp_display_init(void) | |||
829 | omap_hdmi_init(OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP); | 835 | omap_hdmi_init(OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP); |
830 | else | 836 | else |
831 | omap_hdmi_init(0); | 837 | omap_hdmi_init(0); |
838 | |||
839 | omap_mux_init_gpio(HDMI_GPIO_LS_OE, OMAP_PIN_OUTPUT); | ||
840 | omap_mux_init_gpio(HDMI_GPIO_CT_CP_HPD, OMAP_PIN_OUTPUT); | ||
841 | omap_mux_init_gpio(HDMI_GPIO_HPD, OMAP_PIN_INPUT_PULLDOWN); | ||
832 | } | 842 | } |
833 | 843 | ||
834 | #ifdef CONFIG_OMAP_MUX | 844 | #ifdef CONFIG_OMAP_MUX |
@@ -841,7 +851,7 @@ static struct omap_board_mux board_mux[] __initdata = { | |||
841 | #define board_mux NULL | 851 | #define board_mux NULL |
842 | #endif | 852 | #endif |
843 | 853 | ||
844 | static void omap4_sdp4430_wifi_mux_init(void) | 854 | static void __init omap4_sdp4430_wifi_mux_init(void) |
845 | { | 855 | { |
846 | omap_mux_init_gpio(GPIO_WIFI_IRQ, OMAP_PIN_INPUT | | 856 | omap_mux_init_gpio(GPIO_WIFI_IRQ, OMAP_PIN_INPUT | |
847 | OMAP_PIN_OFF_WAKEUPENABLE); | 857 | OMAP_PIN_OFF_WAKEUPENABLE); |
@@ -868,12 +878,17 @@ static struct wl12xx_platform_data omap4_sdp4430_wlan_data __initdata = { | |||
868 | .board_tcxo_clock = WL12XX_TCXOCLOCK_26, | 878 | .board_tcxo_clock = WL12XX_TCXOCLOCK_26, |
869 | }; | 879 | }; |
870 | 880 | ||
871 | static void omap4_sdp4430_wifi_init(void) | 881 | static void __init omap4_sdp4430_wifi_init(void) |
872 | { | 882 | { |
883 | int ret; | ||
884 | |||
873 | omap4_sdp4430_wifi_mux_init(); | 885 | omap4_sdp4430_wifi_mux_init(); |
874 | if (wl12xx_set_platform_data(&omap4_sdp4430_wlan_data)) | 886 | ret = wl12xx_set_platform_data(&omap4_sdp4430_wlan_data); |
875 | pr_err("Error setting wl12xx data\n"); | 887 | if (ret) |
876 | platform_device_register(&omap_vwlan_device); | 888 | pr_err("Error setting wl12xx data: %d\n", ret); |
889 | ret = platform_device_register(&omap_vwlan_device); | ||
890 | if (ret) | ||
891 | pr_err("Error registering wl12xx device: %d\n", ret); | ||
877 | } | 892 | } |
878 | 893 | ||
879 | static void __init omap_4430sdp_init(void) | 894 | static void __init omap_4430sdp_init(void) |
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index e921e3be24a4..d73316ed4207 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c | |||
@@ -437,7 +437,7 @@ static struct usbhs_omap_board_data usbhs_bdata __initdata = { | |||
437 | .reset_gpio_port[2] = -EINVAL | 437 | .reset_gpio_port[2] = -EINVAL |
438 | }; | 438 | }; |
439 | 439 | ||
440 | static void cm_t35_init_usbh(void) | 440 | static void __init cm_t35_init_usbh(void) |
441 | { | 441 | { |
442 | int err; | 442 | int err; |
443 | 443 | ||
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index d58756060483..ad497620539b 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c | |||
@@ -17,6 +17,7 @@ | |||
17 | #include <linux/i2c/twl.h> | 17 | #include <linux/i2c/twl.h> |
18 | 18 | ||
19 | #include <mach/hardware.h> | 19 | #include <mach/hardware.h> |
20 | #include <asm/hardware/gic.h> | ||
20 | #include <asm/mach/arch.h> | 21 | #include <asm/mach/arch.h> |
21 | 22 | ||
22 | #include <plat/board.h> | 23 | #include <plat/board.h> |
@@ -102,6 +103,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)") | |||
102 | .map_io = omap242x_map_io, | 103 | .map_io = omap242x_map_io, |
103 | .init_early = omap2420_init_early, | 104 | .init_early = omap2420_init_early, |
104 | .init_irq = omap2_init_irq, | 105 | .init_irq = omap2_init_irq, |
106 | .handle_irq = omap2_intc_handle_irq, | ||
105 | .init_machine = omap_generic_init, | 107 | .init_machine = omap_generic_init, |
106 | .timer = &omap2_timer, | 108 | .timer = &omap2_timer, |
107 | .dt_compat = omap242x_boards_compat, | 109 | .dt_compat = omap242x_boards_compat, |
@@ -141,6 +143,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)") | |||
141 | .map_io = omap3_map_io, | 143 | .map_io = omap3_map_io, |
142 | .init_early = omap3430_init_early, | 144 | .init_early = omap3430_init_early, |
143 | .init_irq = omap3_init_irq, | 145 | .init_irq = omap3_init_irq, |
146 | .handle_irq = omap3_intc_handle_irq, | ||
144 | .init_machine = omap3_init, | 147 | .init_machine = omap3_init, |
145 | .timer = &omap3_timer, | 148 | .timer = &omap3_timer, |
146 | .dt_compat = omap3_boards_compat, | 149 | .dt_compat = omap3_boards_compat, |
@@ -160,6 +163,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)") | |||
160 | .map_io = omap4_map_io, | 163 | .map_io = omap4_map_io, |
161 | .init_early = omap4430_init_early, | 164 | .init_early = omap4430_init_early, |
162 | .init_irq = gic_init_irq, | 165 | .init_irq = gic_init_irq, |
166 | .handle_irq = gic_handle_irq, | ||
163 | .init_machine = omap4_init, | 167 | .init_machine = omap4_init, |
164 | .timer = &omap4_timer, | 168 | .timer = &omap4_timer, |
165 | .dt_compat = omap4_boards_compat, | 169 | .dt_compat = omap4_boards_compat, |
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 003fe34c9343..c775bead1497 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c | |||
@@ -617,6 +617,21 @@ static struct gpio omap3_evm_ehci_gpios[] __initdata = { | |||
617 | { OMAP3_EVM_EHCI_SELECT, GPIOF_OUT_INIT_LOW, "select EHCI port" }, | 617 | { OMAP3_EVM_EHCI_SELECT, GPIOF_OUT_INIT_LOW, "select EHCI port" }, |
618 | }; | 618 | }; |
619 | 619 | ||
620 | static void __init omap3_evm_wl12xx_init(void) | ||
621 | { | ||
622 | #ifdef CONFIG_WL12XX_PLATFORM_DATA | ||
623 | int ret; | ||
624 | |||
625 | /* WL12xx WLAN Init */ | ||
626 | ret = wl12xx_set_platform_data(&omap3evm_wlan_data); | ||
627 | if (ret) | ||
628 | pr_err("error setting wl12xx data: %d\n", ret); | ||
629 | ret = platform_device_register(&omap3evm_wlan_regulator); | ||
630 | if (ret) | ||
631 | pr_err("error registering wl12xx device: %d\n", ret); | ||
632 | #endif | ||
633 | } | ||
634 | |||
620 | static void __init omap3_evm_init(void) | 635 | static void __init omap3_evm_init(void) |
621 | { | 636 | { |
622 | omap3_evm_get_revision(); | 637 | omap3_evm_get_revision(); |
@@ -665,13 +680,7 @@ static void __init omap3_evm_init(void) | |||
665 | omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL); | 680 | omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL); |
666 | omap3evm_init_smsc911x(); | 681 | omap3evm_init_smsc911x(); |
667 | omap3_evm_display_init(); | 682 | omap3_evm_display_init(); |
668 | 683 | omap3_evm_wl12xx_init(); | |
669 | #ifdef CONFIG_WL12XX_PLATFORM_DATA | ||
670 | /* WL12xx WLAN Init */ | ||
671 | if (wl12xx_set_platform_data(&omap3evm_wlan_data)) | ||
672 | pr_err("error setting wl12xx data\n"); | ||
673 | platform_device_register(&omap3evm_wlan_regulator); | ||
674 | #endif | ||
675 | } | 684 | } |
676 | 685 | ||
677 | MACHINE_START(OMAP3EVM, "OMAP3 EVM") | 686 | MACHINE_START(OMAP3EVM, "OMAP3 EVM") |
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index 30ad40db2cf3..28fc271f7031 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c | |||
@@ -51,8 +51,9 @@ | |||
51 | #define GPIO_HUB_NRESET 62 | 51 | #define GPIO_HUB_NRESET 62 |
52 | #define GPIO_WIFI_PMENA 43 | 52 | #define GPIO_WIFI_PMENA 43 |
53 | #define GPIO_WIFI_IRQ 53 | 53 | #define GPIO_WIFI_IRQ 53 |
54 | #define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */ | 54 | #define HDMI_GPIO_CT_CP_HPD 60 /* HPD mode enable/disable */ |
55 | #define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */ | 55 | #define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */ |
56 | #define HDMI_GPIO_HPD 63 /* Hotplug detect */ | ||
56 | 57 | ||
57 | /* wl127x BT, FM, GPS connectivity chip */ | 58 | /* wl127x BT, FM, GPS connectivity chip */ |
58 | static int wl1271_gpios[] = {46, -1, -1}; | 59 | static int wl1271_gpios[] = {46, -1, -1}; |
@@ -413,8 +414,9 @@ int __init omap4_panda_dvi_init(void) | |||
413 | } | 414 | } |
414 | 415 | ||
415 | static struct gpio panda_hdmi_gpios[] = { | 416 | static struct gpio panda_hdmi_gpios[] = { |
416 | { HDMI_GPIO_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_hpd" }, | 417 | { HDMI_GPIO_CT_CP_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ct_cp_hpd" }, |
417 | { HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" }, | 418 | { HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" }, |
419 | { HDMI_GPIO_HPD, GPIOF_DIR_IN, "hdmi_gpio_hpd" }, | ||
418 | }; | 420 | }; |
419 | 421 | ||
420 | static int omap4_panda_panel_enable_hdmi(struct omap_dss_device *dssdev) | 422 | static int omap4_panda_panel_enable_hdmi(struct omap_dss_device *dssdev) |
@@ -431,10 +433,13 @@ static int omap4_panda_panel_enable_hdmi(struct omap_dss_device *dssdev) | |||
431 | 433 | ||
432 | static void omap4_panda_panel_disable_hdmi(struct omap_dss_device *dssdev) | 434 | static void omap4_panda_panel_disable_hdmi(struct omap_dss_device *dssdev) |
433 | { | 435 | { |
434 | gpio_free(HDMI_GPIO_LS_OE); | 436 | gpio_free_array(panda_hdmi_gpios, ARRAY_SIZE(panda_hdmi_gpios)); |
435 | gpio_free(HDMI_GPIO_HPD); | ||
436 | } | 437 | } |
437 | 438 | ||
439 | static struct omap_dss_hdmi_data omap4_panda_hdmi_data = { | ||
440 | .hpd_gpio = HDMI_GPIO_HPD, | ||
441 | }; | ||
442 | |||
438 | static struct omap_dss_device omap4_panda_hdmi_device = { | 443 | static struct omap_dss_device omap4_panda_hdmi_device = { |
439 | .name = "hdmi", | 444 | .name = "hdmi", |
440 | .driver_name = "hdmi_panel", | 445 | .driver_name = "hdmi_panel", |
@@ -442,6 +447,7 @@ static struct omap_dss_device omap4_panda_hdmi_device = { | |||
442 | .platform_enable = omap4_panda_panel_enable_hdmi, | 447 | .platform_enable = omap4_panda_panel_enable_hdmi, |
443 | .platform_disable = omap4_panda_panel_disable_hdmi, | 448 | .platform_disable = omap4_panda_panel_disable_hdmi, |
444 | .channel = OMAP_DSS_CHANNEL_DIGIT, | 449 | .channel = OMAP_DSS_CHANNEL_DIGIT, |
450 | .data = &omap4_panda_hdmi_data, | ||
445 | }; | 451 | }; |
446 | 452 | ||
447 | static struct omap_dss_device *omap4_panda_dss_devices[] = { | 453 | static struct omap_dss_device *omap4_panda_dss_devices[] = { |
@@ -473,18 +479,24 @@ void omap4_panda_display_init(void) | |||
473 | omap_hdmi_init(OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP); | 479 | omap_hdmi_init(OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP); |
474 | else | 480 | else |
475 | omap_hdmi_init(0); | 481 | omap_hdmi_init(0); |
482 | |||
483 | omap_mux_init_gpio(HDMI_GPIO_LS_OE, OMAP_PIN_OUTPUT); | ||
484 | omap_mux_init_gpio(HDMI_GPIO_CT_CP_HPD, OMAP_PIN_OUTPUT); | ||
485 | omap_mux_init_gpio(HDMI_GPIO_HPD, OMAP_PIN_INPUT_PULLDOWN); | ||
476 | } | 486 | } |
477 | 487 | ||
478 | static void __init omap4_panda_init(void) | 488 | static void __init omap4_panda_init(void) |
479 | { | 489 | { |
480 | int package = OMAP_PACKAGE_CBS; | 490 | int package = OMAP_PACKAGE_CBS; |
491 | int ret; | ||
481 | 492 | ||
482 | if (omap_rev() == OMAP4430_REV_ES1_0) | 493 | if (omap_rev() == OMAP4430_REV_ES1_0) |
483 | package = OMAP_PACKAGE_CBL; | 494 | package = OMAP_PACKAGE_CBL; |
484 | omap4_mux_init(board_mux, NULL, package); | 495 | omap4_mux_init(board_mux, NULL, package); |
485 | 496 | ||
486 | if (wl12xx_set_platform_data(&omap_panda_wlan_data)) | 497 | ret = wl12xx_set_platform_data(&omap_panda_wlan_data); |
487 | pr_err("error setting wl12xx data\n"); | 498 | if (ret) |
499 | pr_err("error setting wl12xx data: %d\n", ret); | ||
488 | 500 | ||
489 | omap4_panda_i2c_init(); | 501 | omap4_panda_i2c_init(); |
490 | platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices)); | 502 | platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices)); |
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index 8d7ce11cfeaf..c126461836ac 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c | |||
@@ -296,8 +296,10 @@ static void enable_board_wakeup_source(void) | |||
296 | 296 | ||
297 | void __init zoom_peripherals_init(void) | 297 | void __init zoom_peripherals_init(void) |
298 | { | 298 | { |
299 | if (wl12xx_set_platform_data(&omap_zoom_wlan_data)) | 299 | int ret = wl12xx_set_platform_data(&omap_zoom_wlan_data); |
300 | pr_err("error setting wl12xx data\n"); | 300 | |
301 | if (ret) | ||
302 | pr_err("error setting wl12xx data: %d\n", ret); | ||
301 | 303 | ||
302 | omap_i2c_init(); | 304 | omap_i2c_init(); |
303 | platform_device_register(&omap_vwlan_device); | 305 | platform_device_register(&omap_vwlan_device); |
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 0b510ad01a00..283d11eae693 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c | |||
@@ -405,6 +405,7 @@ static int omap_mcspi_init(struct omap_hwmod *oh, void *unused) | |||
405 | break; | 405 | break; |
406 | default: | 406 | default: |
407 | pr_err("Invalid McSPI Revision value\n"); | 407 | pr_err("Invalid McSPI Revision value\n"); |
408 | kfree(pdata); | ||
408 | return -EINVAL; | 409 | return -EINVAL; |
409 | } | 410 | } |
410 | 411 | ||
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index 3c446d1a1781..3677b1f58b85 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c | |||
@@ -103,12 +103,8 @@ static void omap4_hdmi_mux_pads(enum omap_hdmi_flags flags) | |||
103 | u32 reg; | 103 | u32 reg; |
104 | u16 control_i2c_1; | 104 | u16 control_i2c_1; |
105 | 105 | ||
106 | /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */ | ||
107 | omap_mux_init_signal("hdmi_hpd", | ||
108 | OMAP_PIN_INPUT_PULLUP); | ||
109 | omap_mux_init_signal("hdmi_cec", | 106 | omap_mux_init_signal("hdmi_cec", |
110 | OMAP_PIN_INPUT_PULLUP); | 107 | OMAP_PIN_INPUT_PULLUP); |
111 | /* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */ | ||
112 | omap_mux_init_signal("hdmi_ddc_scl", | 108 | omap_mux_init_signal("hdmi_ddc_scl", |
113 | OMAP_PIN_INPUT_PULLUP); | 109 | OMAP_PIN_INPUT_PULLUP); |
114 | omap_mux_init_signal("hdmi_ddc_sda", | 110 | omap_mux_init_signal("hdmi_ddc_sda", |
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 130034bf01d5..dfffbbf4c009 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c | |||
@@ -528,7 +528,13 @@ int gpmc_cs_configure(int cs, int cmd, int wval) | |||
528 | 528 | ||
529 | case GPMC_CONFIG_DEV_SIZE: | 529 | case GPMC_CONFIG_DEV_SIZE: |
530 | regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | 530 | regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); |
531 | |||
532 | /* clear 2 target bits */ | ||
533 | regval &= ~GPMC_CONFIG1_DEVICESIZE(3); | ||
534 | |||
535 | /* set the proper value */ | ||
531 | regval |= GPMC_CONFIG1_DEVICESIZE(wval); | 536 | regval |= GPMC_CONFIG1_DEVICESIZE(wval); |
537 | |||
532 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); | 538 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); |
533 | break; | 539 | break; |
534 | 540 | ||
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index bd844af13af5..b40c28895298 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c | |||
@@ -175,14 +175,15 @@ static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc) | |||
175 | { | 175 | { |
176 | u32 reg; | 176 | u32 reg; |
177 | 177 | ||
178 | if (mmc->slots[0].internal_clock) { | 178 | reg = omap_ctrl_readl(control_devconf1_offset); |
179 | reg = omap_ctrl_readl(control_devconf1_offset); | 179 | if (mmc->slots[0].internal_clock) |
180 | reg |= OMAP2_MMCSDIO2ADPCLKISEL; | 180 | reg |= OMAP2_MMCSDIO2ADPCLKISEL; |
181 | omap_ctrl_writel(reg, control_devconf1_offset); | 181 | else |
182 | } | 182 | reg &= ~OMAP2_MMCSDIO2ADPCLKISEL; |
183 | omap_ctrl_writel(reg, control_devconf1_offset); | ||
183 | } | 184 | } |
184 | 185 | ||
185 | static void hsmmc23_before_set_reg(struct device *dev, int slot, | 186 | static void hsmmc2_before_set_reg(struct device *dev, int slot, |
186 | int power_on, int vdd) | 187 | int power_on, int vdd) |
187 | { | 188 | { |
188 | struct omap_mmc_platform_data *mmc = dev->platform_data; | 189 | struct omap_mmc_platform_data *mmc = dev->platform_data; |
@@ -292,8 +293,8 @@ static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller, | |||
292 | } | 293 | } |
293 | } | 294 | } |
294 | 295 | ||
295 | static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, | 296 | static int omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, |
296 | struct omap_mmc_platform_data *mmc) | 297 | struct omap_mmc_platform_data *mmc) |
297 | { | 298 | { |
298 | char *hc_name; | 299 | char *hc_name; |
299 | 300 | ||
@@ -407,14 +408,13 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, | |||
407 | c->caps &= ~MMC_CAP_8_BIT_DATA; | 408 | c->caps &= ~MMC_CAP_8_BIT_DATA; |
408 | c->caps |= MMC_CAP_4_BIT_DATA; | 409 | c->caps |= MMC_CAP_4_BIT_DATA; |
409 | } | 410 | } |
410 | /* FALLTHROUGH */ | ||
411 | case 3: | ||
412 | if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { | 411 | if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { |
413 | /* off-chip level shifting, or none */ | 412 | /* off-chip level shifting, or none */ |
414 | mmc->slots[0].before_set_reg = hsmmc23_before_set_reg; | 413 | mmc->slots[0].before_set_reg = hsmmc2_before_set_reg; |
415 | mmc->slots[0].after_set_reg = NULL; | 414 | mmc->slots[0].after_set_reg = NULL; |
416 | } | 415 | } |
417 | break; | 416 | break; |
417 | case 3: | ||
418 | case 4: | 418 | case 4: |
419 | case 5: | 419 | case 5: |
420 | mmc->slots[0].before_set_reg = NULL; | 420 | mmc->slots[0].before_set_reg = NULL; |
@@ -430,7 +430,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, | |||
430 | 430 | ||
431 | #define MAX_OMAP_MMC_HWMOD_NAME_LEN 16 | 431 | #define MAX_OMAP_MMC_HWMOD_NAME_LEN 16 |
432 | 432 | ||
433 | void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr) | 433 | void omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr) |
434 | { | 434 | { |
435 | struct omap_hwmod *oh; | 435 | struct omap_hwmod *oh; |
436 | struct platform_device *pdev; | 436 | struct platform_device *pdev; |
@@ -487,7 +487,7 @@ done: | |||
487 | kfree(mmc_data); | 487 | kfree(mmc_data); |
488 | } | 488 | } |
489 | 489 | ||
490 | void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) | 490 | void omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) |
491 | { | 491 | { |
492 | u32 reg; | 492 | u32 reg; |
493 | 493 | ||
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 3f174d51f67f..eb50c29fb644 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c | |||
@@ -388,7 +388,7 @@ static void __init omap_hwmod_init_postsetup(void) | |||
388 | omap_pm_if_early_init(); | 388 | omap_pm_if_early_init(); |
389 | } | 389 | } |
390 | 390 | ||
391 | #ifdef CONFIG_ARCH_OMAP2 | 391 | #ifdef CONFIG_SOC_OMAP2420 |
392 | void __init omap2420_init_early(void) | 392 | void __init omap2420_init_early(void) |
393 | { | 393 | { |
394 | omap2_set_globals_242x(); | 394 | omap2_set_globals_242x(); |
@@ -400,7 +400,9 @@ void __init omap2420_init_early(void) | |||
400 | omap_hwmod_init_postsetup(); | 400 | omap_hwmod_init_postsetup(); |
401 | omap2420_clk_init(); | 401 | omap2420_clk_init(); |
402 | } | 402 | } |
403 | #endif | ||
403 | 404 | ||
405 | #ifdef CONFIG_SOC_OMAP2430 | ||
404 | void __init omap2430_init_early(void) | 406 | void __init omap2430_init_early(void) |
405 | { | 407 | { |
406 | omap2_set_globals_243x(); | 408 | omap2_set_globals_243x(); |
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index e1cc75d1a57a..fb8bc9fa43b1 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c | |||
@@ -100,8 +100,8 @@ void omap_mux_write_array(struct omap_mux_partition *partition, | |||
100 | 100 | ||
101 | static char *omap_mux_options; | 101 | static char *omap_mux_options; |
102 | 102 | ||
103 | static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition, | 103 | static int _omap_mux_init_gpio(struct omap_mux_partition *partition, |
104 | int gpio, int val) | 104 | int gpio, int val) |
105 | { | 105 | { |
106 | struct omap_mux_entry *e; | 106 | struct omap_mux_entry *e; |
107 | struct omap_mux *gpio_mux = NULL; | 107 | struct omap_mux *gpio_mux = NULL; |
@@ -145,7 +145,7 @@ static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition, | |||
145 | return 0; | 145 | return 0; |
146 | } | 146 | } |
147 | 147 | ||
148 | int __init omap_mux_init_gpio(int gpio, int val) | 148 | int omap_mux_init_gpio(int gpio, int val) |
149 | { | 149 | { |
150 | struct omap_mux_partition *partition; | 150 | struct omap_mux_partition *partition; |
151 | int ret; | 151 | int ret; |
@@ -159,9 +159,9 @@ int __init omap_mux_init_gpio(int gpio, int val) | |||
159 | return -ENODEV; | 159 | return -ENODEV; |
160 | } | 160 | } |
161 | 161 | ||
162 | static int __init _omap_mux_get_by_name(struct omap_mux_partition *partition, | 162 | static int _omap_mux_get_by_name(struct omap_mux_partition *partition, |
163 | const char *muxname, | 163 | const char *muxname, |
164 | struct omap_mux **found_mux) | 164 | struct omap_mux **found_mux) |
165 | { | 165 | { |
166 | struct omap_mux *mux = NULL; | 166 | struct omap_mux *mux = NULL; |
167 | struct omap_mux_entry *e; | 167 | struct omap_mux_entry *e; |
@@ -240,7 +240,7 @@ omap_mux_get_by_name(const char *muxname, | |||
240 | return -ENODEV; | 240 | return -ENODEV; |
241 | } | 241 | } |
242 | 242 | ||
243 | int __init omap_mux_init_signal(const char *muxname, int val) | 243 | int omap_mux_init_signal(const char *muxname, int val) |
244 | { | 244 | { |
245 | struct omap_mux_partition *partition = NULL; | 245 | struct omap_mux_partition *partition = NULL; |
246 | struct omap_mux *mux = NULL; | 246 | struct omap_mux *mux = NULL; |
@@ -1094,8 +1094,8 @@ static void omap_mux_init_package(struct omap_mux *superset, | |||
1094 | omap_mux_package_init_balls(package_balls, superset); | 1094 | omap_mux_package_init_balls(package_balls, superset); |
1095 | } | 1095 | } |
1096 | 1096 | ||
1097 | static void omap_mux_init_signals(struct omap_mux_partition *partition, | 1097 | static void __init omap_mux_init_signals(struct omap_mux_partition *partition, |
1098 | struct omap_board_mux *board_mux) | 1098 | struct omap_board_mux *board_mux) |
1099 | { | 1099 | { |
1100 | omap_mux_set_cmdline_signals(); | 1100 | omap_mux_set_cmdline_signals(); |
1101 | omap_mux_write_array(partition, board_mux); | 1101 | omap_mux_write_array(partition, board_mux); |
@@ -1109,8 +1109,8 @@ static void omap_mux_init_package(struct omap_mux *superset, | |||
1109 | { | 1109 | { |
1110 | } | 1110 | } |
1111 | 1111 | ||
1112 | static void omap_mux_init_signals(struct omap_mux_partition *partition, | 1112 | static void __init omap_mux_init_signals(struct omap_mux_partition *partition, |
1113 | struct omap_board_mux *board_mux) | 1113 | struct omap_board_mux *board_mux) |
1114 | { | 1114 | { |
1115 | } | 1115 | } |
1116 | 1116 | ||
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S index b13ef7ef5ef4..503ac777a2ba 100644 --- a/arch/arm/mach-omap2/omap-headsmp.S +++ b/arch/arm/mach-omap2/omap-headsmp.S | |||
@@ -18,6 +18,7 @@ | |||
18 | #include <linux/linkage.h> | 18 | #include <linux/linkage.h> |
19 | #include <linux/init.h> | 19 | #include <linux/init.h> |
20 | 20 | ||
21 | __CPUINIT | ||
21 | /* | 22 | /* |
22 | * OMAP4 specific entry point for secondary CPU to jump from ROM | 23 | * OMAP4 specific entry point for secondary CPU to jump from ROM |
23 | * code. This routine also provides a holding flag into which | 24 | * code. This routine also provides a holding flag into which |
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 5192cabb40ed..eba6cd3816f5 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c | |||
@@ -1517,8 +1517,8 @@ static int _enable(struct omap_hwmod *oh) | |||
1517 | if (oh->_state != _HWMOD_STATE_INITIALIZED && | 1517 | if (oh->_state != _HWMOD_STATE_INITIALIZED && |
1518 | oh->_state != _HWMOD_STATE_IDLE && | 1518 | oh->_state != _HWMOD_STATE_IDLE && |
1519 | oh->_state != _HWMOD_STATE_DISABLED) { | 1519 | oh->_state != _HWMOD_STATE_DISABLED) { |
1520 | WARN(1, "omap_hwmod: %s: enabled state can only be entered " | 1520 | WARN(1, "omap_hwmod: %s: enabled state can only be entered from initialized, idle, or disabled state\n", |
1521 | "from initialized, idle, or disabled state\n", oh->name); | 1521 | oh->name); |
1522 | return -EINVAL; | 1522 | return -EINVAL; |
1523 | } | 1523 | } |
1524 | 1524 | ||
@@ -1600,8 +1600,8 @@ static int _idle(struct omap_hwmod *oh) | |||
1600 | pr_debug("omap_hwmod: %s: idling\n", oh->name); | 1600 | pr_debug("omap_hwmod: %s: idling\n", oh->name); |
1601 | 1601 | ||
1602 | if (oh->_state != _HWMOD_STATE_ENABLED) { | 1602 | if (oh->_state != _HWMOD_STATE_ENABLED) { |
1603 | WARN(1, "omap_hwmod: %s: idle state can only be entered from " | 1603 | WARN(1, "omap_hwmod: %s: idle state can only be entered from enabled state\n", |
1604 | "enabled state\n", oh->name); | 1604 | oh->name); |
1605 | return -EINVAL; | 1605 | return -EINVAL; |
1606 | } | 1606 | } |
1607 | 1607 | ||
@@ -1682,8 +1682,8 @@ static int _shutdown(struct omap_hwmod *oh) | |||
1682 | 1682 | ||
1683 | if (oh->_state != _HWMOD_STATE_IDLE && | 1683 | if (oh->_state != _HWMOD_STATE_IDLE && |
1684 | oh->_state != _HWMOD_STATE_ENABLED) { | 1684 | oh->_state != _HWMOD_STATE_ENABLED) { |
1685 | WARN(1, "omap_hwmod: %s: disabled state can only be entered " | 1685 | WARN(1, "omap_hwmod: %s: disabled state can only be entered from idle, or enabled state\n", |
1686 | "from idle, or enabled state\n", oh->name); | 1686 | oh->name); |
1687 | return -EINVAL; | 1687 | return -EINVAL; |
1688 | } | 1688 | } |
1689 | 1689 | ||
@@ -2240,8 +2240,8 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) | |||
2240 | BUG_ON(!oh); | 2240 | BUG_ON(!oh); |
2241 | 2241 | ||
2242 | if (!oh->class->sysc || !oh->class->sysc->sysc_flags) { | 2242 | if (!oh->class->sysc || !oh->class->sysc->sysc_flags) { |
2243 | WARN(1, "omap_device: %s: OCP barrier impossible due to " | 2243 | WARN(1, "omap_device: %s: OCP barrier impossible due to device configuration\n", |
2244 | "device configuration\n", oh->name); | 2244 | oh->name); |
2245 | return; | 2245 | return; |
2246 | } | 2246 | } |
2247 | 2247 | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c index c11273da5dcc..f08e442af397 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c | |||
@@ -56,27 +56,6 @@ struct omap_hwmod_class omap2_dss_hwmod_class = { | |||
56 | }; | 56 | }; |
57 | 57 | ||
58 | /* | 58 | /* |
59 | * 'dispc' class | ||
60 | * display controller | ||
61 | */ | ||
62 | |||
63 | static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = { | ||
64 | .rev_offs = 0x0000, | ||
65 | .sysc_offs = 0x0010, | ||
66 | .syss_offs = 0x0014, | ||
67 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | | ||
68 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | ||
69 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
70 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | ||
71 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
72 | }; | ||
73 | |||
74 | struct omap_hwmod_class omap2_dispc_hwmod_class = { | ||
75 | .name = "dispc", | ||
76 | .sysc = &omap2_dispc_sysc, | ||
77 | }; | ||
78 | |||
79 | /* | ||
80 | * 'rfbi' class | 59 | * 'rfbi' class |
81 | * remote frame buffer interface | 60 | * remote frame buffer interface |
82 | */ | 61 | */ |
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index 177dee20faef..2a6729741b06 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | |||
@@ -28,6 +28,28 @@ struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = { | |||
28 | { .name = "dispc", .dma_req = 5 }, | 28 | { .name = "dispc", .dma_req = 5 }, |
29 | { .dma_req = -1 } | 29 | { .dma_req = -1 } |
30 | }; | 30 | }; |
31 | |||
32 | /* | ||
33 | * 'dispc' class | ||
34 | * display controller | ||
35 | */ | ||
36 | |||
37 | static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = { | ||
38 | .rev_offs = 0x0000, | ||
39 | .sysc_offs = 0x0010, | ||
40 | .syss_offs = 0x0014, | ||
41 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | | ||
42 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | ||
43 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
44 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | ||
45 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
46 | }; | ||
47 | |||
48 | struct omap_hwmod_class omap2_dispc_hwmod_class = { | ||
49 | .name = "dispc", | ||
50 | .sysc = &omap2_dispc_sysc, | ||
51 | }; | ||
52 | |||
31 | /* OMAP2xxx Timer Common */ | 53 | /* OMAP2xxx Timer Common */ |
32 | static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = { | 54 | static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = { |
33 | .rev_offs = 0x0000, | 55 | .rev_offs = 0x0000, |
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 5324e8d93bc0..3c8dd928628e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | |||
@@ -1480,6 +1480,28 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = { | |||
1480 | .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), | 1480 | .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), |
1481 | }; | 1481 | }; |
1482 | 1482 | ||
1483 | /* | ||
1484 | * 'dispc' class | ||
1485 | * display controller | ||
1486 | */ | ||
1487 | |||
1488 | static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = { | ||
1489 | .rev_offs = 0x0000, | ||
1490 | .sysc_offs = 0x0010, | ||
1491 | .syss_offs = 0x0014, | ||
1492 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | | ||
1493 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | ||
1494 | SYSC_HAS_ENAWAKEUP), | ||
1495 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
1496 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | ||
1497 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
1498 | }; | ||
1499 | |||
1500 | static struct omap_hwmod_class omap3_dispc_hwmod_class = { | ||
1501 | .name = "dispc", | ||
1502 | .sysc = &omap3_dispc_sysc, | ||
1503 | }; | ||
1504 | |||
1483 | /* l4_core -> dss_dispc */ | 1505 | /* l4_core -> dss_dispc */ |
1484 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { | 1506 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { |
1485 | .master = &omap3xxx_l4_core_hwmod, | 1507 | .master = &omap3xxx_l4_core_hwmod, |
@@ -1503,7 +1525,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = { | |||
1503 | 1525 | ||
1504 | static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { | 1526 | static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { |
1505 | .name = "dss_dispc", | 1527 | .name = "dss_dispc", |
1506 | .class = &omap2_dispc_hwmod_class, | 1528 | .class = &omap3_dispc_hwmod_class, |
1507 | .mpu_irqs = omap2_dispc_irqs, | 1529 | .mpu_irqs = omap2_dispc_irqs, |
1508 | .main_clk = "dss1_alwon_fck", | 1530 | .main_clk = "dss1_alwon_fck", |
1509 | .prcm = { | 1531 | .prcm = { |
@@ -3523,12 +3545,6 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { | |||
3523 | &omap3xxx_uart2_hwmod, | 3545 | &omap3xxx_uart2_hwmod, |
3524 | &omap3xxx_uart3_hwmod, | 3546 | &omap3xxx_uart3_hwmod, |
3525 | 3547 | ||
3526 | /* dss class */ | ||
3527 | &omap3xxx_dss_dispc_hwmod, | ||
3528 | &omap3xxx_dss_dsi1_hwmod, | ||
3529 | &omap3xxx_dss_rfbi_hwmod, | ||
3530 | &omap3xxx_dss_venc_hwmod, | ||
3531 | |||
3532 | /* i2c class */ | 3548 | /* i2c class */ |
3533 | &omap3xxx_i2c1_hwmod, | 3549 | &omap3xxx_i2c1_hwmod, |
3534 | &omap3xxx_i2c2_hwmod, | 3550 | &omap3xxx_i2c2_hwmod, |
@@ -3635,6 +3651,15 @@ static __initdata struct omap_hwmod *am35xx_hwmods[] = { | |||
3635 | NULL | 3651 | NULL |
3636 | }; | 3652 | }; |
3637 | 3653 | ||
3654 | static __initdata struct omap_hwmod *omap3xxx_dss_hwmods[] = { | ||
3655 | /* dss class */ | ||
3656 | &omap3xxx_dss_dispc_hwmod, | ||
3657 | &omap3xxx_dss_dsi1_hwmod, | ||
3658 | &omap3xxx_dss_rfbi_hwmod, | ||
3659 | &omap3xxx_dss_venc_hwmod, | ||
3660 | NULL | ||
3661 | }; | ||
3662 | |||
3638 | int __init omap3xxx_hwmod_init(void) | 3663 | int __init omap3xxx_hwmod_init(void) |
3639 | { | 3664 | { |
3640 | int r; | 3665 | int r; |
@@ -3708,6 +3733,21 @@ int __init omap3xxx_hwmod_init(void) | |||
3708 | 3733 | ||
3709 | if (h) | 3734 | if (h) |
3710 | r = omap_hwmod_register(h); | 3735 | r = omap_hwmod_register(h); |
3736 | if (r < 0) | ||
3737 | return r; | ||
3738 | |||
3739 | /* | ||
3740 | * DSS code presumes that dss_core hwmod is handled first, | ||
3741 | * _before_ any other DSS related hwmods so register common | ||
3742 | * DSS hwmods last to ensure that dss_core is already registered. | ||
3743 | * Otherwise some change things may happen, for ex. if dispc | ||
3744 | * is handled before dss_core and DSS is enabled in bootloader | ||
3745 | * DIPSC will be reset with outputs enabled which sometimes leads | ||
3746 | * to unrecoverable L3 error. | ||
3747 | * XXX The long-term fix to this is to ensure modules are set up | ||
3748 | * in dependency order in the hwmod core code. | ||
3749 | */ | ||
3750 | r = omap_hwmod_register(omap3xxx_dss_hwmods); | ||
3711 | 3751 | ||
3712 | return r; | 3752 | return r; |
3713 | } | 3753 | } |
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index f9f151081760..ef0524c10a84 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c | |||
@@ -1031,6 +1031,7 @@ static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { | |||
1031 | 1031 | ||
1032 | static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { | 1032 | static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { |
1033 | { | 1033 | { |
1034 | .name = "mpu", | ||
1034 | .pa_start = 0x4012e000, | 1035 | .pa_start = 0x4012e000, |
1035 | .pa_end = 0x4012e07f, | 1036 | .pa_end = 0x4012e07f, |
1036 | .flags = ADDR_TYPE_RT | 1037 | .flags = ADDR_TYPE_RT |
@@ -1049,6 +1050,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { | |||
1049 | 1050 | ||
1050 | static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { | 1051 | static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { |
1051 | { | 1052 | { |
1053 | .name = "dma", | ||
1052 | .pa_start = 0x4902e000, | 1054 | .pa_start = 0x4902e000, |
1053 | .pa_end = 0x4902e07f, | 1055 | .pa_end = 0x4902e07f, |
1054 | .flags = ADDR_TYPE_RT | 1056 | .flags = ADDR_TYPE_RT |
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index b8822f8b2891..23de98d03841 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c | |||
@@ -82,13 +82,7 @@ static int omap2_fclks_active(void) | |||
82 | f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); | 82 | f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); |
83 | f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); | 83 | f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); |
84 | 84 | ||
85 | /* Ignore UART clocks. These are handled by UART core (serial.c) */ | 85 | return (f1 | f2) ? 1 : 0; |
86 | f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK); | ||
87 | f2 &= ~OMAP24XX_EN_UART3_MASK; | ||
88 | |||
89 | if (f1 | f2) | ||
90 | return 1; | ||
91 | return 0; | ||
92 | } | 86 | } |
93 | 87 | ||
94 | static void omap2_enter_full_retention(void) | 88 | static void omap2_enter_full_retention(void) |
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c index c1c4d86a79a8..9ce765407ad5 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c | |||
@@ -19,6 +19,7 @@ | |||
19 | #include "common.h" | 19 | #include "common.h" |
20 | #include <plat/cpu.h> | 20 | #include <plat/cpu.h> |
21 | #include <plat/prcm.h> | 21 | #include <plat/prcm.h> |
22 | #include <plat/irqs.h> | ||
22 | 23 | ||
23 | #include "vp.h" | 24 | #include "vp.h" |
24 | 25 | ||
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index 33dd655e6aab..a1d6154dc120 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c | |||
@@ -19,6 +19,7 @@ | |||
19 | 19 | ||
20 | #include "common.h" | 20 | #include "common.h" |
21 | #include <plat/cpu.h> | 21 | #include <plat/cpu.h> |
22 | #include <plat/irqs.h> | ||
22 | #include <plat/prcm.h> | 23 | #include <plat/prcm.h> |
23 | 24 | ||
24 | #include "vp.h" | 25 | #include "vp.h" |
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 247d89478f24..f590afc1f673 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c | |||
@@ -107,18 +107,18 @@ static void omap_uart_set_noidle(struct platform_device *pdev) | |||
107 | omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO); | 107 | omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO); |
108 | } | 108 | } |
109 | 109 | ||
110 | static void omap_uart_set_forceidle(struct platform_device *pdev) | 110 | static void omap_uart_set_smartidle(struct platform_device *pdev) |
111 | { | 111 | { |
112 | struct omap_device *od = to_omap_device(pdev); | 112 | struct omap_device *od = to_omap_device(pdev); |
113 | 113 | ||
114 | omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_FORCE); | 114 | omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_SMART); |
115 | } | 115 | } |
116 | 116 | ||
117 | #else | 117 | #else |
118 | static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable) | 118 | static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable) |
119 | {} | 119 | {} |
120 | static void omap_uart_set_noidle(struct platform_device *pdev) {} | 120 | static void omap_uart_set_noidle(struct platform_device *pdev) {} |
121 | static void omap_uart_set_forceidle(struct platform_device *pdev) {} | 121 | static void omap_uart_set_smartidle(struct platform_device *pdev) {} |
122 | #endif /* CONFIG_PM */ | 122 | #endif /* CONFIG_PM */ |
123 | 123 | ||
124 | #ifdef CONFIG_OMAP_MUX | 124 | #ifdef CONFIG_OMAP_MUX |
@@ -349,7 +349,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata, | |||
349 | omap_up.uartclk = OMAP24XX_BASE_BAUD * 16; | 349 | omap_up.uartclk = OMAP24XX_BASE_BAUD * 16; |
350 | omap_up.flags = UPF_BOOT_AUTOCONF; | 350 | omap_up.flags = UPF_BOOT_AUTOCONF; |
351 | omap_up.get_context_loss_count = omap_pm_get_dev_context_loss_count; | 351 | omap_up.get_context_loss_count = omap_pm_get_dev_context_loss_count; |
352 | omap_up.set_forceidle = omap_uart_set_forceidle; | 352 | omap_up.set_forceidle = omap_uart_set_smartidle; |
353 | omap_up.set_noidle = omap_uart_set_noidle; | 353 | omap_up.set_noidle = omap_uart_set_noidle; |
354 | omap_up.enable_wakeup = omap_uart_enable_wakeup; | 354 | omap_up.enable_wakeup = omap_uart_enable_wakeup; |
355 | omap_up.dma_rx_buf_size = info->dma_rx_buf_size; | 355 | omap_up.dma_rx_buf_size = info->dma_rx_buf_size; |
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c index 9dd93453e563..7e755bb0ffc4 100644 --- a/arch/arm/mach-omap2/smartreflex.c +++ b/arch/arm/mach-omap2/smartreflex.c | |||
@@ -897,7 +897,7 @@ static int __init omap_sr_probe(struct platform_device *pdev) | |||
897 | ret = sr_late_init(sr_info); | 897 | ret = sr_late_init(sr_info); |
898 | if (ret) { | 898 | if (ret) { |
899 | pr_warning("%s: Error in SR late init\n", __func__); | 899 | pr_warning("%s: Error in SR late init\n", __func__); |
900 | return ret; | 900 | goto err_iounmap; |
901 | } | 901 | } |
902 | } | 902 | } |
903 | 903 | ||
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 6eeff0e0ae01..5c9acea95761 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c | |||
@@ -270,7 +270,7 @@ static struct clocksource clocksource_gpt = { | |||
270 | static u32 notrace dmtimer_read_sched_clock(void) | 270 | static u32 notrace dmtimer_read_sched_clock(void) |
271 | { | 271 | { |
272 | if (clksrc.reserved) | 272 | if (clksrc.reserved) |
273 | return __omap_dm_timer_read_counter(clksrc.io_base, 1); | 273 | return __omap_dm_timer_read_counter(&clksrc, 1); |
274 | 274 | ||
275 | return 0; | 275 | return 0; |
276 | } | 276 | } |
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c index 031d116fbf10..175b7d86d86a 100644 --- a/arch/arm/mach-omap2/vc.c +++ b/arch/arm/mach-omap2/vc.c | |||
@@ -247,7 +247,7 @@ static void __init omap4_vc_init_channel(struct voltagedomain *voltdm) | |||
247 | * omap_vc_i2c_init - initialize I2C interface to PMIC | 247 | * omap_vc_i2c_init - initialize I2C interface to PMIC |
248 | * @voltdm: voltage domain containing VC data | 248 | * @voltdm: voltage domain containing VC data |
249 | * | 249 | * |
250 | * Use PMIC supplied seetings for I2C high-speed mode and | 250 | * Use PMIC supplied settings for I2C high-speed mode and |
251 | * master code (if set) and program the VC I2C configuration | 251 | * master code (if set) and program the VC I2C configuration |
252 | * register. | 252 | * register. |
253 | * | 253 | * |
@@ -265,8 +265,8 @@ static void __init omap_vc_i2c_init(struct voltagedomain *voltdm) | |||
265 | 265 | ||
266 | if (initialized) { | 266 | if (initialized) { |
267 | if (voltdm->pmic->i2c_high_speed != i2c_high_speed) | 267 | if (voltdm->pmic->i2c_high_speed != i2c_high_speed) |
268 | pr_warn("%s: I2C config for all channels must match.", | 268 | pr_warn("%s: I2C config for vdd_%s does not match other channels (%u).", |
269 | __func__); | 269 | __func__, voltdm->name, i2c_high_speed); |
270 | return; | 270 | return; |
271 | } | 271 | } |
272 | 272 | ||
@@ -292,9 +292,7 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm) | |||
292 | u32 val; | 292 | u32 val; |
293 | 293 | ||
294 | if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) { | 294 | if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) { |
295 | pr_err("%s: PMIC info requried to configure vc for" | 295 | pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name); |
296 | "vdd_%s not populated.Hence cannot initialize vc\n", | ||
297 | __func__, voltdm->name); | ||
298 | return; | 296 | return; |
299 | } | 297 | } |
300 | 298 | ||
diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c index c005e2f5e383..57db2038b23c 100644 --- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c +++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c | |||
@@ -108,6 +108,7 @@ void __init omap3xxx_voltagedomains_init(void) | |||
108 | * XXX Will depend on the process, validation, and binning | 108 | * XXX Will depend on the process, validation, and binning |
109 | * for the currently-running IC | 109 | * for the currently-running IC |
110 | */ | 110 | */ |
111 | #ifdef CONFIG_PM_OPP | ||
111 | if (cpu_is_omap3630()) { | 112 | if (cpu_is_omap3630()) { |
112 | omap3_voltdm_mpu.volt_data = omap36xx_vddmpu_volt_data; | 113 | omap3_voltdm_mpu.volt_data = omap36xx_vddmpu_volt_data; |
113 | omap3_voltdm_core.volt_data = omap36xx_vddcore_volt_data; | 114 | omap3_voltdm_core.volt_data = omap36xx_vddcore_volt_data; |
@@ -115,6 +116,7 @@ void __init omap3xxx_voltagedomains_init(void) | |||
115 | omap3_voltdm_mpu.volt_data = omap34xx_vddmpu_volt_data; | 116 | omap3_voltdm_mpu.volt_data = omap34xx_vddmpu_volt_data; |
116 | omap3_voltdm_core.volt_data = omap34xx_vddcore_volt_data; | 117 | omap3_voltdm_core.volt_data = omap34xx_vddcore_volt_data; |
117 | } | 118 | } |
119 | #endif | ||
118 | 120 | ||
119 | if (cpu_is_omap3517() || cpu_is_omap3505()) | 121 | if (cpu_is_omap3517() || cpu_is_omap3505()) |
120 | voltdms = voltagedomains_am35xx; | 122 | voltdms = voltagedomains_am35xx; |
diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c index 4e11d022595d..c3115f6853d4 100644 --- a/arch/arm/mach-omap2/voltagedomains44xx_data.c +++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c | |||
@@ -100,9 +100,11 @@ void __init omap44xx_voltagedomains_init(void) | |||
100 | * XXX Will depend on the process, validation, and binning | 100 | * XXX Will depend on the process, validation, and binning |
101 | * for the currently-running IC | 101 | * for the currently-running IC |
102 | */ | 102 | */ |
103 | #ifdef CONFIG_PM_OPP | ||
103 | omap4_voltdm_mpu.volt_data = omap44xx_vdd_mpu_volt_data; | 104 | omap4_voltdm_mpu.volt_data = omap44xx_vdd_mpu_volt_data; |
104 | omap4_voltdm_iva.volt_data = omap44xx_vdd_iva_volt_data; | 105 | omap4_voltdm_iva.volt_data = omap44xx_vdd_iva_volt_data; |
105 | omap4_voltdm_core.volt_data = omap44xx_vdd_core_volt_data; | 106 | omap4_voltdm_core.volt_data = omap44xx_vdd_core_volt_data; |
107 | #endif | ||
106 | 108 | ||
107 | for (i = 0; voltdm = voltagedomains_omap4[i], voltdm; i++) | 109 | for (i = 0; voltdm = voltagedomains_omap4[i], voltdm; i++) |
108 | voltdm->sys_clk.name = sys_clk_name; | 110 | voltdm->sys_clk.name = sys_clk_name; |
diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c index 807391d84a9d..0df88820978d 100644 --- a/arch/arm/mach-omap2/vp.c +++ b/arch/arm/mach-omap2/vp.c | |||
@@ -41,6 +41,11 @@ void __init omap_vp_init(struct voltagedomain *voltdm) | |||
41 | u32 val, sys_clk_rate, timeout, waittime; | 41 | u32 val, sys_clk_rate, timeout, waittime; |
42 | u32 vddmin, vddmax, vstepmin, vstepmax; | 42 | u32 vddmin, vddmax, vstepmin, vstepmax; |
43 | 43 | ||
44 | if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) { | ||
45 | pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name); | ||
46 | return; | ||
47 | } | ||
48 | |||
44 | if (!voltdm->read || !voltdm->write) { | 49 | if (!voltdm->read || !voltdm->write) { |
45 | pr_err("%s: No read/write API for accessing vdd_%s regs\n", | 50 | pr_err("%s: No read/write API for accessing vdd_%s regs\n", |
46 | __func__, voltdm->name); | 51 | __func__, voltdm->name); |
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 0e28bae20bd4..5dad38ec00ea 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c | |||
@@ -29,6 +29,7 @@ | |||
29 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
30 | #include <mach/orion5x.h> | 30 | #include <mach/orion5x.h> |
31 | #include <plat/orion_nand.h> | 31 | #include <plat/orion_nand.h> |
32 | #include <plat/ehci-orion.h> | ||
32 | #include <plat/time.h> | 33 | #include <plat/time.h> |
33 | #include <plat/common.h> | 34 | #include <plat/common.h> |
34 | #include <plat/addr-map.h> | 35 | #include <plat/addr-map.h> |
@@ -72,7 +73,8 @@ void __init orion5x_map_io(void) | |||
72 | ****************************************************************************/ | 73 | ****************************************************************************/ |
73 | void __init orion5x_ehci0_init(void) | 74 | void __init orion5x_ehci0_init(void) |
74 | { | 75 | { |
75 | orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL); | 76 | orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL, |
77 | EHCI_PHY_ORION); | ||
76 | } | 78 | } |
77 | 79 | ||
78 | 80 | ||
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index 18fd177073f4..5bc13121eac5 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c | |||
@@ -415,29 +415,9 @@ static struct resource pxa_rtc_resources[] = { | |||
415 | }, | 415 | }, |
416 | }; | 416 | }; |
417 | 417 | ||
418 | static struct resource sa1100_rtc_resources[] = { | ||
419 | [0] = { | ||
420 | .start = 0x40900000, | ||
421 | .end = 0x409000ff, | ||
422 | .flags = IORESOURCE_MEM, | ||
423 | }, | ||
424 | [1] = { | ||
425 | .start = IRQ_RTC1Hz, | ||
426 | .end = IRQ_RTC1Hz, | ||
427 | .flags = IORESOURCE_IRQ, | ||
428 | }, | ||
429 | [2] = { | ||
430 | .start = IRQ_RTCAlrm, | ||
431 | .end = IRQ_RTCAlrm, | ||
432 | .flags = IORESOURCE_IRQ, | ||
433 | }, | ||
434 | }; | ||
435 | |||
436 | struct platform_device sa1100_device_rtc = { | 418 | struct platform_device sa1100_device_rtc = { |
437 | .name = "sa1100-rtc", | 419 | .name = "sa1100-rtc", |
438 | .id = -1, | 420 | .id = -1, |
439 | .num_resources = ARRAY_SIZE(sa1100_rtc_resources), | ||
440 | .resource = sa1100_rtc_resources, | ||
441 | }; | 421 | }; |
442 | 422 | ||
443 | struct platform_device pxa_device_rtc = { | 423 | struct platform_device pxa_device_rtc = { |
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index adf058fa97ee..91e4f6c03766 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c | |||
@@ -209,8 +209,6 @@ static struct clk_lookup pxa25x_clkregs[] = { | |||
209 | INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"), | 209 | INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"), |
210 | INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"), | 210 | INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"), |
211 | INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL), | 211 | INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL), |
212 | INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL), | ||
213 | INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), | ||
214 | }; | 212 | }; |
215 | 213 | ||
216 | static struct clk_lookup pxa25x_hwuart_clkreg = | 214 | static struct clk_lookup pxa25x_hwuart_clkreg = |
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 180bd8675d4b..aed6cbcf3866 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c | |||
@@ -230,8 +230,6 @@ static struct clk_lookup pxa27x_clkregs[] = { | |||
230 | INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"), | 230 | INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"), |
231 | INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"), | 231 | INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"), |
232 | INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL), | 232 | INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL), |
233 | INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL), | ||
234 | INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), | ||
235 | }; | 233 | }; |
236 | 234 | ||
237 | #ifdef CONFIG_PM | 235 | #ifdef CONFIG_PM |
diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c index 0388eda7878a..40bb16501d86 100644 --- a/arch/arm/mach-pxa/pxa300.c +++ b/arch/arm/mach-pxa/pxa300.c | |||
@@ -89,7 +89,6 @@ static DEFINE_PXA3_CKEN(gcu, PXA300_GCU, 0, 0); | |||
89 | static struct clk_lookup common_clkregs[] = { | 89 | static struct clk_lookup common_clkregs[] = { |
90 | INIT_CLKREG(&clk_common_nand, "pxa3xx-nand", NULL), | 90 | INIT_CLKREG(&clk_common_nand, "pxa3xx-nand", NULL), |
91 | INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL), | 91 | INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL), |
92 | INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), | ||
93 | }; | 92 | }; |
94 | 93 | ||
95 | static DEFINE_PXA3_CKEN(pxa310_mmc3, MMC3, 19500000, 0); | 94 | static DEFINE_PXA3_CKEN(pxa310_mmc3, MMC3, 19500000, 0); |
diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c index d487e1ff4c9a..8d614ecd8e99 100644 --- a/arch/arm/mach-pxa/pxa320.c +++ b/arch/arm/mach-pxa/pxa320.c | |||
@@ -83,7 +83,6 @@ static DEFINE_PXA3_CKEN(gcu, PXA320_GCU, 0, 0); | |||
83 | static struct clk_lookup pxa320_clkregs[] = { | 83 | static struct clk_lookup pxa320_clkregs[] = { |
84 | INIT_CLKREG(&clk_pxa320_nand, "pxa3xx-nand", NULL), | 84 | INIT_CLKREG(&clk_pxa320_nand, "pxa3xx-nand", NULL), |
85 | INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL), | 85 | INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL), |
86 | INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), | ||
87 | }; | 86 | }; |
88 | 87 | ||
89 | static int __init pxa320_init(void) | 88 | static int __init pxa320_init(void) |
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index f107c71c7589..4f402afa6609 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c | |||
@@ -67,7 +67,6 @@ static struct clk_lookup pxa3xx_clkregs[] = { | |||
67 | INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), | 67 | INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), |
68 | /* Power I2C clock is always on */ | 68 | /* Power I2C clock is always on */ |
69 | INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL), | 69 | INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL), |
70 | INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), | ||
71 | INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL), | 70 | INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL), |
72 | INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"), | 71 | INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"), |
73 | INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"), | 72 | INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"), |
diff --git a/arch/arm/mach-pxa/pxa95x.c b/arch/arm/mach-pxa/pxa95x.c index fccc644702e6..d082a583df78 100644 --- a/arch/arm/mach-pxa/pxa95x.c +++ b/arch/arm/mach-pxa/pxa95x.c | |||
@@ -217,7 +217,6 @@ static struct clk_lookup pxa95x_clkregs[] = { | |||
217 | INIT_CLKREG(&clk_pxa95x_pout, NULL, "CLK_POUT"), | 217 | INIT_CLKREG(&clk_pxa95x_pout, NULL, "CLK_POUT"), |
218 | /* Power I2C clock is always on */ | 218 | /* Power I2C clock is always on */ |
219 | INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL), | 219 | INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL), |
220 | INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), | ||
221 | INIT_CLKREG(&clk_pxa95x_lcd, "pxa2xx-fb", NULL), | 220 | INIT_CLKREG(&clk_pxa95x_lcd, "pxa2xx-fb", NULL), |
222 | INIT_CLKREG(&clk_pxa95x_ffuart, "pxa2xx-uart.0", NULL), | 221 | INIT_CLKREG(&clk_pxa95x_ffuart, "pxa2xx-uart.0", NULL), |
223 | INIT_CLKREG(&clk_pxa95x_btuart, "pxa2xx-uart.1", NULL), | 222 | INIT_CLKREG(&clk_pxa95x_btuart, "pxa2xx-uart.1", NULL), |
diff --git a/arch/arm/mach-realview/hotplug.c b/arch/arm/mach-realview/hotplug.c index ac1aed2a8da4..eb55f05bef3a 100644 --- a/arch/arm/mach-realview/hotplug.c +++ b/arch/arm/mach-realview/hotplug.c | |||
@@ -13,6 +13,7 @@ | |||
13 | #include <linux/smp.h> | 13 | #include <linux/smp.h> |
14 | 14 | ||
15 | #include <asm/cacheflush.h> | 15 | #include <asm/cacheflush.h> |
16 | #include <asm/smp_plat.h> | ||
16 | 17 | ||
17 | extern volatile int pen_release; | 18 | extern volatile int pen_release; |
18 | 19 | ||
diff --git a/arch/arm/mach-realview/include/mach/board-eb.h b/arch/arm/mach-realview/include/mach/board-eb.h index 794a8d91a6a6..124bce6b4d7b 100644 --- a/arch/arm/mach-realview/include/mach/board-eb.h +++ b/arch/arm/mach-realview/include/mach/board-eb.h | |||
@@ -47,21 +47,23 @@ | |||
47 | #define REALVIEW_EB_USB_BASE 0x4F000000 /* USB */ | 47 | #define REALVIEW_EB_USB_BASE 0x4F000000 /* USB */ |
48 | 48 | ||
49 | #ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB | 49 | #ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB |
50 | #define REALVIEW_EB11MP_SCU_BASE 0x10100000 /* SCU registers */ | 50 | #define REALVIEW_EB11MP_PRIV_MEM_BASE 0x1F000000 |
51 | #define REALVIEW_EB11MP_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */ | ||
52 | #define REALVIEW_EB11MP_TWD_BASE 0x10100600 | ||
53 | #define REALVIEW_EB11MP_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */ | ||
54 | #define REALVIEW_EB11MP_L220_BASE 0x10102000 /* L220 registers */ | 51 | #define REALVIEW_EB11MP_L220_BASE 0x10102000 /* L220 registers */ |
55 | #define REALVIEW_EB11MP_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */ | 52 | #define REALVIEW_EB11MP_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */ |
56 | #else | 53 | #else |
57 | #define REALVIEW_EB11MP_SCU_BASE 0x1F000000 /* SCU registers */ | 54 | #define REALVIEW_EB11MP_PRIV_MEM_BASE 0x1F000000 |
58 | #define REALVIEW_EB11MP_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */ | ||
59 | #define REALVIEW_EB11MP_TWD_BASE 0x1F000600 | ||
60 | #define REALVIEW_EB11MP_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */ | ||
61 | #define REALVIEW_EB11MP_L220_BASE 0x1F002000 /* L220 registers */ | 55 | #define REALVIEW_EB11MP_L220_BASE 0x1F002000 /* L220 registers */ |
62 | #define REALVIEW_EB11MP_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */ | 56 | #define REALVIEW_EB11MP_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */ |
63 | #endif | 57 | #endif |
64 | 58 | ||
59 | #define REALVIEW_EB11MP_PRIV_MEM_SIZE SZ_8K | ||
60 | #define REALVIEW_EB11MP_PRIV_MEM_OFF(x) (REALVIEW_EB11MP_PRIV_MEM_BASE + (x)) | ||
61 | |||
62 | #define REALVIEW_EB11MP_SCU_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0) /* SCU registers */ | ||
63 | #define REALVIEW_EB11MP_GIC_CPU_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x0100) /* Generic interrupt controller CPU interface */ | ||
64 | #define REALVIEW_EB11MP_TWD_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x0600) | ||
65 | #define REALVIEW_EB11MP_GIC_DIST_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x1000) /* Generic interrupt controller distributor */ | ||
66 | |||
65 | /* | 67 | /* |
66 | * Core tile identification (REALVIEW_SYS_PROCID) | 68 | * Core tile identification (REALVIEW_SYS_PROCID) |
67 | */ | 69 | */ |
diff --git a/arch/arm/mach-realview/include/mach/board-pb11mp.h b/arch/arm/mach-realview/include/mach/board-pb11mp.h index 7abf918b77e9..aa2d4e02ea2c 100644 --- a/arch/arm/mach-realview/include/mach/board-pb11mp.h +++ b/arch/arm/mach-realview/include/mach/board-pb11mp.h | |||
@@ -75,6 +75,8 @@ | |||
75 | /* | 75 | /* |
76 | * Testchip peripheral and fpga gic regions | 76 | * Testchip peripheral and fpga gic regions |
77 | */ | 77 | */ |
78 | #define REALVIEW_TC11MP_PRIV_MEM_BASE 0x1F000000 | ||
79 | #define REALVIEW_TC11MP_PRIV_MEM_SIZE SZ_8K | ||
78 | #define REALVIEW_TC11MP_SCU_BASE 0x1F000000 /* IRQ, Test chip */ | 80 | #define REALVIEW_TC11MP_SCU_BASE 0x1F000000 /* IRQ, Test chip */ |
79 | #define REALVIEW_TC11MP_GIC_CPU_BASE 0x1F000100 /* Test chip interrupt controller CPU interface */ | 81 | #define REALVIEW_TC11MP_GIC_CPU_BASE 0x1F000100 /* Test chip interrupt controller CPU interface */ |
80 | #define REALVIEW_TC11MP_TWD_BASE 0x1F000600 | 82 | #define REALVIEW_TC11MP_TWD_BASE 0x1F000600 |
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index e62962117763..9578145f2df0 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c | |||
@@ -91,14 +91,9 @@ static struct map_desc realview_eb_io_desc[] __initdata = { | |||
91 | 91 | ||
92 | static struct map_desc realview_eb11mp_io_desc[] __initdata = { | 92 | static struct map_desc realview_eb11mp_io_desc[] __initdata = { |
93 | { | 93 | { |
94 | .virtual = IO_ADDRESS(REALVIEW_EB11MP_SCU_BASE), | 94 | .virtual = IO_ADDRESS(REALVIEW_EB11MP_PRIV_MEM_BASE), |
95 | .pfn = __phys_to_pfn(REALVIEW_EB11MP_SCU_BASE), | 95 | .pfn = __phys_to_pfn(REALVIEW_EB11MP_PRIV_MEM_BASE), |
96 | .length = SZ_4K, | 96 | .length = REALVIEW_EB11MP_PRIV_MEM_SIZE, |
97 | .type = MT_DEVICE, | ||
98 | }, { | ||
99 | .virtual = IO_ADDRESS(REALVIEW_EB11MP_GIC_DIST_BASE), | ||
100 | .pfn = __phys_to_pfn(REALVIEW_EB11MP_GIC_DIST_BASE), | ||
101 | .length = SZ_4K, | ||
102 | .type = MT_DEVICE, | 97 | .type = MT_DEVICE, |
103 | }, { | 98 | }, { |
104 | .virtual = IO_ADDRESS(REALVIEW_EB11MP_L220_BASE), | 99 | .virtual = IO_ADDRESS(REALVIEW_EB11MP_L220_BASE), |
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c index 127a3fd42ab1..2147335f66f5 100644 --- a/arch/arm/mach-realview/realview_pb11mp.c +++ b/arch/arm/mach-realview/realview_pb11mp.c | |||
@@ -64,15 +64,10 @@ static struct map_desc realview_pb11mp_io_desc[] __initdata = { | |||
64 | .pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_DIST_BASE), | 64 | .pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_DIST_BASE), |
65 | .length = SZ_4K, | 65 | .length = SZ_4K, |
66 | .type = MT_DEVICE, | 66 | .type = MT_DEVICE, |
67 | }, { | 67 | }, { /* Maps the SCU, GIC CPU interface, TWD, GIC DIST */ |
68 | .virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_CPU_BASE), | 68 | .virtual = IO_ADDRESS(REALVIEW_TC11MP_PRIV_MEM_BASE), |
69 | .pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_CPU_BASE), | 69 | .pfn = __phys_to_pfn(REALVIEW_TC11MP_PRIV_MEM_BASE), |
70 | .length = SZ_4K, | 70 | .length = REALVIEW_TC11MP_PRIV_MEM_SIZE, |
71 | .type = MT_DEVICE, | ||
72 | }, { | ||
73 | .virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_DIST_BASE), | ||
74 | .pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_DIST_BASE), | ||
75 | .length = SZ_4K, | ||
76 | .type = MT_DEVICE, | 71 | .type = MT_DEVICE, |
77 | }, { | 72 | }, { |
78 | .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE), | 73 | .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE), |
diff --git a/arch/arm/mach-s3c2410/cpu-freq.c b/arch/arm/mach-s3c2410/cpu-freq.c index 7dc6c46b5e2b..5404535da1a5 100644 --- a/arch/arm/mach-s3c2410/cpu-freq.c +++ b/arch/arm/mach-s3c2410/cpu-freq.c | |||
@@ -115,7 +115,8 @@ static struct s3c_cpufreq_info s3c2410_cpufreq_info = { | |||
115 | .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), | 115 | .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), |
116 | }; | 116 | }; |
117 | 117 | ||
118 | static int s3c2410_cpufreq_add(struct device *dev) | 118 | static int s3c2410_cpufreq_add(struct device *dev, |
119 | struct subsys_interface *sif) | ||
119 | { | 120 | { |
120 | return s3c_cpufreq_register(&s3c2410_cpufreq_info); | 121 | return s3c_cpufreq_register(&s3c2410_cpufreq_info); |
121 | } | 122 | } |
@@ -133,7 +134,8 @@ static int __init s3c2410_cpufreq_init(void) | |||
133 | 134 | ||
134 | arch_initcall(s3c2410_cpufreq_init); | 135 | arch_initcall(s3c2410_cpufreq_init); |
135 | 136 | ||
136 | static int s3c2410a_cpufreq_add(struct device *dev) | 137 | static int s3c2410a_cpufreq_add(struct device *dev, |
138 | struct subsys_interface *sif) | ||
137 | { | 139 | { |
138 | /* alter the maximum freq settings for S3C2410A. If a board knows | 140 | /* alter the maximum freq settings for S3C2410A. If a board knows |
139 | * it only has a maximum of 200, then it should register its own | 141 | * it only has a maximum of 200, then it should register its own |
@@ -144,7 +146,7 @@ static int s3c2410a_cpufreq_add(struct device *dev) | |||
144 | s3c2410_cpufreq_info.max.pclk = 66500000; | 146 | s3c2410_cpufreq_info.max.pclk = 66500000; |
145 | s3c2410_cpufreq_info.name = "s3c2410a"; | 147 | s3c2410_cpufreq_info.name = "s3c2410a"; |
146 | 148 | ||
147 | return s3c2410_cpufreq_add(dev); | 149 | return s3c2410_cpufreq_add(dev, sif); |
148 | } | 150 | } |
149 | 151 | ||
150 | static struct subsys_interface s3c2410a_cpufreq_interface = { | 152 | static struct subsys_interface s3c2410a_cpufreq_interface = { |
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c index 2afd00014a77..4803338cf56e 100644 --- a/arch/arm/mach-s3c2410/dma.c +++ b/arch/arm/mach-s3c2410/dma.c | |||
@@ -132,7 +132,8 @@ static struct s3c24xx_dma_order __initdata s3c2410_dma_order = { | |||
132 | }, | 132 | }, |
133 | }; | 133 | }; |
134 | 134 | ||
135 | static int __init s3c2410_dma_add(struct device *dev) | 135 | static int __init s3c2410_dma_add(struct device *dev, |
136 | struct subsys_interface *sif) | ||
136 | { | 137 | { |
137 | s3c2410_dma_init(); | 138 | s3c2410_dma_init(); |
138 | s3c24xx_dma_order_set(&s3c2410_dma_order); | 139 | s3c24xx_dma_order_set(&s3c2410_dma_order); |
@@ -148,7 +149,7 @@ static struct subsys_interface s3c2410_dma_interface = { | |||
148 | 149 | ||
149 | static int __init s3c2410_dma_drvinit(void) | 150 | static int __init s3c2410_dma_drvinit(void) |
150 | { | 151 | { |
151 | return subsys_interface_register(&s3c2410_interface); | 152 | return subsys_interface_register(&s3c2410_dma_interface); |
152 | } | 153 | } |
153 | 154 | ||
154 | arch_initcall(s3c2410_dma_drvinit); | 155 | arch_initcall(s3c2410_dma_drvinit); |
diff --git a/arch/arm/mach-s3c2410/pll.c b/arch/arm/mach-s3c2410/pll.c index c07438bfc99f..e0b3b347da82 100644 --- a/arch/arm/mach-s3c2410/pll.c +++ b/arch/arm/mach-s3c2410/pll.c | |||
@@ -66,7 +66,7 @@ static struct cpufreq_frequency_table pll_vals_12MHz[] = { | |||
66 | { .frequency = 270000000, .index = PLLVAL(127, 1, 1), }, | 66 | { .frequency = 270000000, .index = PLLVAL(127, 1, 1), }, |
67 | }; | 67 | }; |
68 | 68 | ||
69 | static int s3c2410_plls_add(struct device *dev) | 69 | static int s3c2410_plls_add(struct device *dev, struct subsys_interface *sif) |
70 | { | 70 | { |
71 | return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz)); | 71 | return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz)); |
72 | } | 72 | } |
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c index fda5385deff6..03f706dd6009 100644 --- a/arch/arm/mach-s3c2410/pm.c +++ b/arch/arm/mach-s3c2410/pm.c | |||
@@ -111,7 +111,7 @@ struct syscore_ops s3c2410_pm_syscore_ops = { | |||
111 | .resume = s3c2410_pm_resume, | 111 | .resume = s3c2410_pm_resume, |
112 | }; | 112 | }; |
113 | 113 | ||
114 | static int s3c2410_pm_add(struct device *dev) | 114 | static int s3c2410_pm_add(struct device *dev, struct subsys_interface *sif) |
115 | { | 115 | { |
116 | pm_cpu_prep = s3c2410_pm_prepare; | 116 | pm_cpu_prep = s3c2410_pm_prepare; |
117 | pm_cpu_sleep = s3c2410_cpu_suspend; | 117 | pm_cpu_sleep = s3c2410_cpu_suspend; |
diff --git a/arch/arm/mach-s3c2412/cpu-freq.c b/arch/arm/mach-s3c2412/cpu-freq.c index d8664b7652ce..125be7d5fa60 100644 --- a/arch/arm/mach-s3c2412/cpu-freq.c +++ b/arch/arm/mach-s3c2412/cpu-freq.c | |||
@@ -194,7 +194,8 @@ static struct s3c_cpufreq_info s3c2412_cpufreq_info = { | |||
194 | .debug_io_show = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs), | 194 | .debug_io_show = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs), |
195 | }; | 195 | }; |
196 | 196 | ||
197 | static int s3c2412_cpufreq_add(struct device *dev) | 197 | static int s3c2412_cpufreq_add(struct device *dev, |
198 | struct subsys_interface *sif) | ||
198 | { | 199 | { |
199 | unsigned long fclk_rate; | 200 | unsigned long fclk_rate; |
200 | 201 | ||
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c index 142acd3b5e15..38472ac920ff 100644 --- a/arch/arm/mach-s3c2412/dma.c +++ b/arch/arm/mach-s3c2412/dma.c | |||
@@ -159,7 +159,8 @@ static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = { | |||
159 | .map_size = ARRAY_SIZE(s3c2412_dma_mappings), | 159 | .map_size = ARRAY_SIZE(s3c2412_dma_mappings), |
160 | }; | 160 | }; |
161 | 161 | ||
162 | static int __init s3c2412_dma_add(struct device *dev) | 162 | static int __init s3c2412_dma_add(struct device *dev, |
163 | struct subsys_interface *sif) | ||
163 | { | 164 | { |
164 | s3c2410_dma_init(); | 165 | s3c2410_dma_init(); |
165 | return s3c24xx_dma_init_map(&s3c2412_dma_sel); | 166 | return s3c24xx_dma_init_map(&s3c2412_dma_sel); |
diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c index a8a46c1644f4..e65619ddbccc 100644 --- a/arch/arm/mach-s3c2412/irq.c +++ b/arch/arm/mach-s3c2412/irq.c | |||
@@ -170,7 +170,7 @@ static int s3c2412_irq_rtc_wake(struct irq_data *data, unsigned int state) | |||
170 | 170 | ||
171 | static struct irq_chip s3c2412_irq_rtc_chip; | 171 | static struct irq_chip s3c2412_irq_rtc_chip; |
172 | 172 | ||
173 | static int s3c2412_irq_add(struct device *dev) | 173 | static int s3c2412_irq_add(struct device *dev, struct subsys_interface *sif) |
174 | { | 174 | { |
175 | unsigned int irqno; | 175 | unsigned int irqno; |
176 | 176 | ||
diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c2412/pm.c index d1adfa65f66d..d04588506ec4 100644 --- a/arch/arm/mach-s3c2412/pm.c +++ b/arch/arm/mach-s3c2412/pm.c | |||
@@ -56,7 +56,7 @@ static void s3c2412_pm_prepare(void) | |||
56 | { | 56 | { |
57 | } | 57 | } |
58 | 58 | ||
59 | static int s3c2412_pm_add(struct device *dev) | 59 | static int s3c2412_pm_add(struct device *dev, struct subsys_interface *sif) |
60 | { | 60 | { |
61 | pm_cpu_prep = s3c2412_pm_prepare; | 61 | pm_cpu_prep = s3c2412_pm_prepare; |
62 | pm_cpu_sleep = s3c2412_cpu_suspend; | 62 | pm_cpu_sleep = s3c2412_cpu_suspend; |
diff --git a/arch/arm/mach-s3c2416/irq.c b/arch/arm/mach-s3c2416/irq.c index 36df761061de..fd49f35e448e 100644 --- a/arch/arm/mach-s3c2416/irq.c +++ b/arch/arm/mach-s3c2416/irq.c | |||
@@ -213,7 +213,8 @@ static int __init s3c2416_add_sub(unsigned int base, | |||
213 | return 0; | 213 | return 0; |
214 | } | 214 | } |
215 | 215 | ||
216 | static int __init s3c2416_irq_add(struct device *dev) | 216 | static int __init s3c2416_irq_add(struct device *dev, |
217 | struct subsys_interface *sif) | ||
217 | { | 218 | { |
218 | printk(KERN_INFO "S3C2416: IRQ Support\n"); | 219 | printk(KERN_INFO "S3C2416: IRQ Support\n"); |
219 | 220 | ||
diff --git a/arch/arm/mach-s3c2416/pm.c b/arch/arm/mach-s3c2416/pm.c index 3bdb15a0d419..1bd4817b8eb8 100644 --- a/arch/arm/mach-s3c2416/pm.c +++ b/arch/arm/mach-s3c2416/pm.c | |||
@@ -48,7 +48,7 @@ static void s3c2416_pm_prepare(void) | |||
48 | __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1); | 48 | __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1); |
49 | } | 49 | } |
50 | 50 | ||
51 | static int s3c2416_pm_add(struct device *dev) | 51 | static int s3c2416_pm_add(struct device *dev, struct subsys_interface *sif) |
52 | { | 52 | { |
53 | pm_cpu_prep = s3c2416_pm_prepare; | 53 | pm_cpu_prep = s3c2416_pm_prepare; |
54 | pm_cpu_sleep = s3c2416_cpu_suspend; | 54 | pm_cpu_sleep = s3c2416_cpu_suspend; |
diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c index bedbc87a3426..414364eb426c 100644 --- a/arch/arm/mach-s3c2440/clock.c +++ b/arch/arm/mach-s3c2440/clock.c | |||
@@ -149,7 +149,7 @@ static struct clk_lookup s3c2440_clk_lookup[] = { | |||
149 | CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n), | 149 | CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n), |
150 | }; | 150 | }; |
151 | 151 | ||
152 | static int s3c2440_clk_add(struct device *dev) | 152 | static int s3c2440_clk_add(struct device *dev, struct subsys_interface *sif) |
153 | { | 153 | { |
154 | struct clk *clock_upll; | 154 | struct clk *clock_upll; |
155 | struct clk *clock_h; | 155 | struct clk *clock_h; |
diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c index 15b1ddf8f626..5f0a0c8ef84f 100644 --- a/arch/arm/mach-s3c2440/dma.c +++ b/arch/arm/mach-s3c2440/dma.c | |||
@@ -174,7 +174,8 @@ static struct s3c24xx_dma_order __initdata s3c2440_dma_order = { | |||
174 | }, | 174 | }, |
175 | }; | 175 | }; |
176 | 176 | ||
177 | static int __init s3c2440_dma_add(struct device *dev) | 177 | static int __init s3c2440_dma_add(struct device *dev, |
178 | struct subsys_interface *sif) | ||
178 | { | 179 | { |
179 | s3c2410_dma_init(); | 180 | s3c2410_dma_init(); |
180 | s3c24xx_dma_order_set(&s3c2440_dma_order); | 181 | s3c24xx_dma_order_set(&s3c2440_dma_order); |
diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c index 4fee9bc6bcb5..4a18cde439cc 100644 --- a/arch/arm/mach-s3c2440/irq.c +++ b/arch/arm/mach-s3c2440/irq.c | |||
@@ -92,7 +92,7 @@ static struct irq_chip s3c_irq_wdtac97 = { | |||
92 | .irq_ack = s3c_irq_wdtac97_ack, | 92 | .irq_ack = s3c_irq_wdtac97_ack, |
93 | }; | 93 | }; |
94 | 94 | ||
95 | static int s3c2440_irq_add(struct device *dev) | 95 | static int s3c2440_irq_add(struct device *dev, struct subsys_interface *sif) |
96 | { | 96 | { |
97 | unsigned int irqno; | 97 | unsigned int irqno; |
98 | 98 | ||
diff --git a/arch/arm/mach-s3c2440/s3c2440-cpufreq.c b/arch/arm/mach-s3c2440/s3c2440-cpufreq.c index cf7596694efe..61776764d9f4 100644 --- a/arch/arm/mach-s3c2440/s3c2440-cpufreq.c +++ b/arch/arm/mach-s3c2440/s3c2440-cpufreq.c | |||
@@ -270,7 +270,8 @@ struct s3c_cpufreq_info s3c2440_cpufreq_info = { | |||
270 | .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), | 270 | .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), |
271 | }; | 271 | }; |
272 | 272 | ||
273 | static int s3c2440_cpufreq_add(struct device *dev) | 273 | static int s3c2440_cpufreq_add(struct device *dev, |
274 | struct subsys_interface *sif) | ||
274 | { | 275 | { |
275 | xtal = s3c_cpufreq_clk_get(NULL, "xtal"); | 276 | xtal = s3c_cpufreq_clk_get(NULL, "xtal"); |
276 | hclk = s3c_cpufreq_clk_get(NULL, "hclk"); | 277 | hclk = s3c_cpufreq_clk_get(NULL, "hclk"); |
diff --git a/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c b/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c index b5368ae8d7fe..551fb433be87 100644 --- a/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c +++ b/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c | |||
@@ -51,7 +51,7 @@ static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = { | |||
51 | { .frequency = 400000000, .index = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */ | 51 | { .frequency = 400000000, .index = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */ |
52 | }; | 52 | }; |
53 | 53 | ||
54 | static int s3c2440_plls12_add(struct device *dev) | 54 | static int s3c2440_plls12_add(struct device *dev, struct subsys_interface *sif) |
55 | { | 55 | { |
56 | struct clk *xtal_clk; | 56 | struct clk *xtal_clk; |
57 | unsigned long xtal; | 57 | unsigned long xtal; |
diff --git a/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c b/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c index 42f2b5cd2399..3f15bcf64290 100644 --- a/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c +++ b/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c | |||
@@ -79,7 +79,8 @@ static struct cpufreq_frequency_table s3c2440_plls_169344[] __initdata = { | |||
79 | { .frequency = 402192000, .index = PLLVAL(87, 2, 1), }, /* FVco 804.384000 */ | 79 | { .frequency = 402192000, .index = PLLVAL(87, 2, 1), }, /* FVco 804.384000 */ |
80 | }; | 80 | }; |
81 | 81 | ||
82 | static int s3c2440_plls169344_add(struct device *dev) | 82 | static int s3c2440_plls169344_add(struct device *dev, |
83 | struct subsys_interface *sif) | ||
83 | { | 84 | { |
84 | struct clk *xtal_clk; | 85 | struct clk *xtal_clk; |
85 | unsigned long xtal; | 86 | unsigned long xtal; |
diff --git a/arch/arm/mach-s3c2440/s3c2442.c b/arch/arm/mach-s3c2440/s3c2442.c index 8004e0497bf4..22cb7c94a8c8 100644 --- a/arch/arm/mach-s3c2440/s3c2442.c +++ b/arch/arm/mach-s3c2440/s3c2442.c | |||
@@ -122,7 +122,7 @@ static struct clk s3c2442_clk_cam_upll = { | |||
122 | }, | 122 | }, |
123 | }; | 123 | }; |
124 | 124 | ||
125 | static int s3c2442_clk_add(struct device *dev) | 125 | static int s3c2442_clk_add(struct device *dev, struct subsys_interface *sif) |
126 | { | 126 | { |
127 | struct clk *clock_upll; | 127 | struct clk *clock_upll; |
128 | struct clk *clock_h; | 128 | struct clk *clock_h; |
diff --git a/arch/arm/mach-s3c2440/s3c244x-clock.c b/arch/arm/mach-s3c2440/s3c244x-clock.c index b3fdbdda3d5f..6d9b688c442b 100644 --- a/arch/arm/mach-s3c2440/s3c244x-clock.c +++ b/arch/arm/mach-s3c2440/s3c244x-clock.c | |||
@@ -72,7 +72,7 @@ static struct clk clk_arm = { | |||
72 | }, | 72 | }, |
73 | }; | 73 | }; |
74 | 74 | ||
75 | static int s3c244x_clk_add(struct device *dev) | 75 | static int s3c244x_clk_add(struct device *dev, struct subsys_interface *sif) |
76 | { | 76 | { |
77 | unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); | 77 | unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); |
78 | unsigned long clkdivn; | 78 | unsigned long clkdivn; |
diff --git a/arch/arm/mach-s3c2440/s3c244x-irq.c b/arch/arm/mach-s3c2440/s3c244x-irq.c index 74d3dcf46a48..5fe8e58d3afd 100644 --- a/arch/arm/mach-s3c2440/s3c244x-irq.c +++ b/arch/arm/mach-s3c2440/s3c244x-irq.c | |||
@@ -91,7 +91,7 @@ static struct irq_chip s3c_irq_cam = { | |||
91 | .irq_ack = s3c_irq_cam_ack, | 91 | .irq_ack = s3c_irq_cam_ack, |
92 | }; | 92 | }; |
93 | 93 | ||
94 | static int s3c244x_irq_add(struct device *dev) | 94 | static int s3c244x_irq_add(struct device *dev, struct subsys_interface *sif) |
95 | { | 95 | { |
96 | unsigned int irqno; | 96 | unsigned int irqno; |
97 | 97 | ||
diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c index de6b4a23c9ed..14224517e621 100644 --- a/arch/arm/mach-s3c2443/dma.c +++ b/arch/arm/mach-s3c2443/dma.c | |||
@@ -135,7 +135,8 @@ static struct s3c24xx_dma_selection __initdata s3c2443_dma_sel = { | |||
135 | .map_size = ARRAY_SIZE(s3c2443_dma_mappings), | 135 | .map_size = ARRAY_SIZE(s3c2443_dma_mappings), |
136 | }; | 136 | }; |
137 | 137 | ||
138 | static int __init s3c2443_dma_add(struct device *dev) | 138 | static int __init s3c2443_dma_add(struct device *dev, |
139 | struct subsys_interface *sif) | ||
139 | { | 140 | { |
140 | s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100); | 141 | s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100); |
141 | return s3c24xx_dma_init_map(&s3c2443_dma_sel); | 142 | return s3c24xx_dma_init_map(&s3c2443_dma_sel); |
diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c2443/irq.c index 35e4ff24fb43..ac2829f56d12 100644 --- a/arch/arm/mach-s3c2443/irq.c +++ b/arch/arm/mach-s3c2443/irq.c | |||
@@ -241,7 +241,8 @@ static int __init s3c2443_add_sub(unsigned int base, | |||
241 | return 0; | 241 | return 0; |
242 | } | 242 | } |
243 | 243 | ||
244 | static int __init s3c2443_irq_add(struct device *dev) | 244 | static int __init s3c2443_irq_add(struct device *dev, |
245 | struct subsys_interface *sif) | ||
245 | { | 246 | { |
246 | printk("S3C2443: IRQ Support\n"); | 247 | printk("S3C2443: IRQ Support\n"); |
247 | 248 | ||
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c index 31bb27dc4aeb..aebbcc291b4e 100644 --- a/arch/arm/mach-s3c64xx/clock.c +++ b/arch/arm/mach-s3c64xx/clock.c | |||
@@ -138,6 +138,11 @@ static struct clk init_clocks_off[] = { | |||
138 | .ctrlbit = S3C_CLKCON_PCLK_TSADC, | 138 | .ctrlbit = S3C_CLKCON_PCLK_TSADC, |
139 | }, { | 139 | }, { |
140 | .name = "i2c", | 140 | .name = "i2c", |
141 | #ifdef CONFIG_S3C_DEV_I2C1 | ||
142 | .devname = "s3c2440-i2c.0", | ||
143 | #else | ||
144 | .devname = "s3c2440-i2c", | ||
145 | #endif | ||
141 | .parent = &clk_p, | 146 | .parent = &clk_p, |
142 | .enable = s3c64xx_pclk_ctrl, | 147 | .enable = s3c64xx_pclk_ctrl, |
143 | .ctrlbit = S3C_CLKCON_PCLK_IIC, | 148 | .ctrlbit = S3C_CLKCON_PCLK_IIC, |
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c index 4a7394d4bd9e..bee7dcd4df7c 100644 --- a/arch/arm/mach-s3c64xx/common.c +++ b/arch/arm/mach-s3c64xx/common.c | |||
@@ -49,7 +49,7 @@ | |||
49 | 49 | ||
50 | /* uart registration process */ | 50 | /* uart registration process */ |
51 | 51 | ||
52 | void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) | 52 | static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) |
53 | { | 53 | { |
54 | s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no); | 54 | s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no); |
55 | } | 55 | } |
diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c index 23f9b22439c9..9cba18bfe47b 100644 --- a/arch/arm/mach-s5p64x0/pm.c +++ b/arch/arm/mach-s5p64x0/pm.c | |||
@@ -160,7 +160,7 @@ static void s5p64x0_pm_prepare(void) | |||
160 | 160 | ||
161 | } | 161 | } |
162 | 162 | ||
163 | static int s5p64x0_pm_add(struct device *dev) | 163 | static int s5p64x0_pm_add(struct device *dev, struct subsys_interface *sif) |
164 | { | 164 | { |
165 | pm_cpu_prep = s5p64x0_pm_prepare; | 165 | pm_cpu_prep = s5p64x0_pm_prepare; |
166 | pm_cpu_sleep = s5p64x0_cpu_suspend; | 166 | pm_cpu_sleep = s5p64x0_cpu_suspend; |
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index c78dfddd77fd..b9ec0c35379f 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c | |||
@@ -175,7 +175,7 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable) | |||
175 | return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable); | 175 | return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable); |
176 | } | 176 | } |
177 | 177 | ||
178 | static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable) | 178 | static int s5pv210_clk_hdmiphy_ctrl(struct clk *clk, int enable) |
179 | { | 179 | { |
180 | return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable); | 180 | return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable); |
181 | } | 181 | } |
@@ -372,7 +372,7 @@ static struct clk init_clocks_off[] = { | |||
372 | }, { | 372 | }, { |
373 | .name = "hdmiphy", | 373 | .name = "hdmiphy", |
374 | .devname = "s5pv210-hdmi", | 374 | .devname = "s5pv210-hdmi", |
375 | .enable = exynos4_clk_hdmiphy_ctrl, | 375 | .enable = s5pv210_clk_hdmiphy_ctrl, |
376 | .ctrlbit = (1 << 0), | 376 | .ctrlbit = (1 << 0), |
377 | }, { | 377 | }, { |
378 | .name = "dacphy", | 378 | .name = "dacphy", |
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c index 677c71c41e50..736bfb103cbc 100644 --- a/arch/arm/mach-s5pv210/pm.c +++ b/arch/arm/mach-s5pv210/pm.c | |||
@@ -133,7 +133,7 @@ static void s5pv210_pm_prepare(void) | |||
133 | s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save)); | 133 | s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save)); |
134 | } | 134 | } |
135 | 135 | ||
136 | static int s5pv210_pm_add(struct device *dev) | 136 | static int s5pv210_pm_add(struct device *dev, struct subsys_interface *sif) |
137 | { | 137 | { |
138 | pm_cpu_prep = s5pv210_pm_prepare; | 138 | pm_cpu_prep = s5pv210_pm_prepare; |
139 | pm_cpu_sleep = s5pv210_cpu_suspend; | 139 | pm_cpu_sleep = s5pv210_cpu_suspend; |
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c index ebafe8aa8956..0c4b76ab4d8e 100644 --- a/arch/arm/mach-sa1100/assabet.c +++ b/arch/arm/mach-sa1100/assabet.c | |||
@@ -202,7 +202,6 @@ static struct irda_platform_data assabet_irda_data = { | |||
202 | static struct mcp_plat_data assabet_mcp_data = { | 202 | static struct mcp_plat_data assabet_mcp_data = { |
203 | .mccr0 = MCCR0_ADM, | 203 | .mccr0 = MCCR0_ADM, |
204 | .sclk_rate = 11981000, | 204 | .sclk_rate = 11981000, |
205 | .codec = "ucb1x00", | ||
206 | }; | 205 | }; |
207 | 206 | ||
208 | static void __init assabet_init(void) | 207 | static void __init assabet_init(void) |
@@ -253,17 +252,6 @@ static void __init assabet_init(void) | |||
253 | sa11x0_register_mtd(&assabet_flash_data, assabet_flash_resources, | 252 | sa11x0_register_mtd(&assabet_flash_data, assabet_flash_resources, |
254 | ARRAY_SIZE(assabet_flash_resources)); | 253 | ARRAY_SIZE(assabet_flash_resources)); |
255 | sa11x0_register_irda(&assabet_irda_data); | 254 | sa11x0_register_irda(&assabet_irda_data); |
256 | |||
257 | /* | ||
258 | * Setup the PPC unit correctly. | ||
259 | */ | ||
260 | PPDR &= ~PPC_RXD4; | ||
261 | PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM; | ||
262 | PSDR |= PPC_RXD4; | ||
263 | PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); | ||
264 | PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); | ||
265 | |||
266 | ASSABET_BCR_set(ASSABET_BCR_CODEC_RST); | ||
267 | sa11x0_register_mcp(&assabet_mcp_data); | 255 | sa11x0_register_mcp(&assabet_mcp_data); |
268 | } | 256 | } |
269 | 257 | ||
diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c index d12d0f48b1dc..11bb6d0b9be3 100644 --- a/arch/arm/mach-sa1100/cerf.c +++ b/arch/arm/mach-sa1100/cerf.c | |||
@@ -124,23 +124,12 @@ static void __init cerf_map_io(void) | |||
124 | static struct mcp_plat_data cerf_mcp_data = { | 124 | static struct mcp_plat_data cerf_mcp_data = { |
125 | .mccr0 = MCCR0_ADM, | 125 | .mccr0 = MCCR0_ADM, |
126 | .sclk_rate = 11981000, | 126 | .sclk_rate = 11981000, |
127 | .codec = "ucb1x00", | ||
128 | }; | 127 | }; |
129 | 128 | ||
130 | static void __init cerf_init(void) | 129 | static void __init cerf_init(void) |
131 | { | 130 | { |
132 | platform_add_devices(cerf_devices, ARRAY_SIZE(cerf_devices)); | 131 | platform_add_devices(cerf_devices, ARRAY_SIZE(cerf_devices)); |
133 | sa11x0_register_mtd(&cerf_flash_data, &cerf_flash_resource, 1); | 132 | sa11x0_register_mtd(&cerf_flash_data, &cerf_flash_resource, 1); |
134 | |||
135 | /* | ||
136 | * Setup the PPC unit correctly. | ||
137 | */ | ||
138 | PPDR &= ~PPC_RXD4; | ||
139 | PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM; | ||
140 | PSDR |= PPC_RXD4; | ||
141 | PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); | ||
142 | PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); | ||
143 | |||
144 | sa11x0_register_mcp(&cerf_mcp_data); | 133 | sa11x0_register_mcp(&cerf_mcp_data); |
145 | } | 134 | } |
146 | 135 | ||
diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c index d6df9f6c9f7e..dab3c6347a8f 100644 --- a/arch/arm/mach-sa1100/clock.c +++ b/arch/arm/mach-sa1100/clock.c | |||
@@ -11,39 +11,17 @@ | |||
11 | #include <linux/clk.h> | 11 | #include <linux/clk.h> |
12 | #include <linux/spinlock.h> | 12 | #include <linux/spinlock.h> |
13 | #include <linux/mutex.h> | 13 | #include <linux/mutex.h> |
14 | #include <linux/io.h> | ||
15 | #include <linux/clkdev.h> | ||
16 | 14 | ||
17 | #include <mach/hardware.h> | 15 | #include <mach/hardware.h> |
18 | 16 | ||
19 | struct clkops { | 17 | /* |
20 | void (*enable)(struct clk *); | 18 | * Very simple clock implementation - we only have one clock to deal with. |
21 | void (*disable)(struct clk *); | 19 | */ |
22 | unsigned long (*getrate)(struct clk *); | ||
23 | }; | ||
24 | |||
25 | struct clk { | 20 | struct clk { |
26 | const struct clkops *ops; | ||
27 | unsigned long rate; | ||
28 | unsigned int enabled; | 21 | unsigned int enabled; |
29 | }; | 22 | }; |
30 | 23 | ||
31 | #define INIT_CLKREG(_clk, _devname, _conname) \ | 24 | static void clk_gpio27_enable(void) |
32 | { \ | ||
33 | .clk = _clk, \ | ||
34 | .dev_id = _devname, \ | ||
35 | .con_id = _conname, \ | ||
36 | } | ||
37 | |||
38 | #define DEFINE_CLK(_name, _ops, _rate) \ | ||
39 | struct clk clk_##_name = { \ | ||
40 | .ops = _ops, \ | ||
41 | .rate = _rate, \ | ||
42 | } | ||
43 | |||
44 | static DEFINE_SPINLOCK(clocks_lock); | ||
45 | |||
46 | static void clk_gpio27_enable(struct clk *clk) | ||
47 | { | 25 | { |
48 | /* | 26 | /* |
49 | * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111: | 27 | * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111: |
@@ -54,22 +32,38 @@ static void clk_gpio27_enable(struct clk *clk) | |||
54 | TUCR = TUCR_3_6864MHz; | 32 | TUCR = TUCR_3_6864MHz; |
55 | } | 33 | } |
56 | 34 | ||
57 | static void clk_gpio27_disable(struct clk *clk) | 35 | static void clk_gpio27_disable(void) |
58 | { | 36 | { |
59 | TUCR = 0; | 37 | TUCR = 0; |
60 | GPDR &= ~GPIO_32_768kHz; | 38 | GPDR &= ~GPIO_32_768kHz; |
61 | GAFR &= ~GPIO_32_768kHz; | 39 | GAFR &= ~GPIO_32_768kHz; |
62 | } | 40 | } |
63 | 41 | ||
42 | static struct clk clk_gpio27; | ||
43 | |||
44 | static DEFINE_SPINLOCK(clocks_lock); | ||
45 | |||
46 | struct clk *clk_get(struct device *dev, const char *id) | ||
47 | { | ||
48 | const char *devname = dev_name(dev); | ||
49 | |||
50 | return strcmp(devname, "sa1111.0") ? ERR_PTR(-ENOENT) : &clk_gpio27; | ||
51 | } | ||
52 | EXPORT_SYMBOL(clk_get); | ||
53 | |||
54 | void clk_put(struct clk *clk) | ||
55 | { | ||
56 | } | ||
57 | EXPORT_SYMBOL(clk_put); | ||
58 | |||
64 | int clk_enable(struct clk *clk) | 59 | int clk_enable(struct clk *clk) |
65 | { | 60 | { |
66 | unsigned long flags; | 61 | unsigned long flags; |
67 | 62 | ||
68 | spin_lock_irqsave(&clocks_lock, flags); | 63 | spin_lock_irqsave(&clocks_lock, flags); |
69 | if (clk->enabled++ == 0) | 64 | if (clk->enabled++ == 0) |
70 | clk->ops->enable(clk); | 65 | clk_gpio27_enable(); |
71 | spin_unlock_irqrestore(&clocks_lock, flags); | 66 | spin_unlock_irqrestore(&clocks_lock, flags); |
72 | |||
73 | return 0; | 67 | return 0; |
74 | } | 68 | } |
75 | EXPORT_SYMBOL(clk_enable); | 69 | EXPORT_SYMBOL(clk_enable); |
@@ -82,48 +76,13 @@ void clk_disable(struct clk *clk) | |||
82 | 76 | ||
83 | spin_lock_irqsave(&clocks_lock, flags); | 77 | spin_lock_irqsave(&clocks_lock, flags); |
84 | if (--clk->enabled == 0) | 78 | if (--clk->enabled == 0) |
85 | clk->ops->disable(clk); | 79 | clk_gpio27_disable(); |
86 | spin_unlock_irqrestore(&clocks_lock, flags); | 80 | spin_unlock_irqrestore(&clocks_lock, flags); |
87 | } | 81 | } |
88 | EXPORT_SYMBOL(clk_disable); | 82 | EXPORT_SYMBOL(clk_disable); |
89 | 83 | ||
90 | unsigned long clk_get_rate(struct clk *clk) | 84 | unsigned long clk_get_rate(struct clk *clk) |
91 | { | 85 | { |
92 | unsigned long rate; | 86 | return 3686400; |
93 | |||
94 | rate = clk->rate; | ||
95 | if (clk->ops->getrate) | ||
96 | rate = clk->ops->getrate(clk); | ||
97 | |||
98 | return rate; | ||
99 | } | 87 | } |
100 | EXPORT_SYMBOL(clk_get_rate); | 88 | EXPORT_SYMBOL(clk_get_rate); |
101 | |||
102 | const struct clkops clk_gpio27_ops = { | ||
103 | .enable = clk_gpio27_enable, | ||
104 | .disable = clk_gpio27_disable, | ||
105 | }; | ||
106 | |||
107 | static void clk_dummy_enable(struct clk *clk) { } | ||
108 | static void clk_dummy_disable(struct clk *clk) { } | ||
109 | |||
110 | const struct clkops clk_dummy_ops = { | ||
111 | .enable = clk_dummy_enable, | ||
112 | .disable = clk_dummy_disable, | ||
113 | }; | ||
114 | |||
115 | static DEFINE_CLK(gpio27, &clk_gpio27_ops, 3686400); | ||
116 | static DEFINE_CLK(dummy, &clk_dummy_ops, 0); | ||
117 | |||
118 | static struct clk_lookup sa11xx_clkregs[] = { | ||
119 | INIT_CLKREG(&clk_gpio27, "sa1111.0", NULL), | ||
120 | INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), | ||
121 | }; | ||
122 | |||
123 | static int __init sa11xx_clk_init(void) | ||
124 | { | ||
125 | clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs)); | ||
126 | return 0; | ||
127 | } | ||
128 | |||
129 | postcore_initcall(sa11xx_clk_init); | ||
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c index c483912d08af..fd5652118ed1 100644 --- a/arch/arm/mach-sa1100/collie.c +++ b/arch/arm/mach-sa1100/collie.c | |||
@@ -27,7 +27,6 @@ | |||
27 | #include <linux/timer.h> | 27 | #include <linux/timer.h> |
28 | #include <linux/gpio.h> | 28 | #include <linux/gpio.h> |
29 | #include <linux/pda_power.h> | 29 | #include <linux/pda_power.h> |
30 | #include <linux/mfd/ucb1x00.h> | ||
31 | 30 | ||
32 | #include <mach/hardware.h> | 31 | #include <mach/hardware.h> |
33 | #include <asm/mach-types.h> | 32 | #include <asm/mach-types.h> |
@@ -86,15 +85,10 @@ static struct scoop_pcmcia_config collie_pcmcia_config = { | |||
86 | .num_devs = 1, | 85 | .num_devs = 1, |
87 | }; | 86 | }; |
88 | 87 | ||
89 | static struct ucb1x00_plat_data collie_ucb1x00_data = { | ||
90 | .gpio_base = COLLIE_TC35143_GPIO_BASE, | ||
91 | }; | ||
92 | |||
93 | static struct mcp_plat_data collie_mcp_data = { | 88 | static struct mcp_plat_data collie_mcp_data = { |
94 | .mccr0 = MCCR0_ADM | MCCR0_ExtClk, | 89 | .mccr0 = MCCR0_ADM | MCCR0_ExtClk, |
95 | .sclk_rate = 9216000, | 90 | .sclk_rate = 9216000, |
96 | .codec = "ucb1x00", | 91 | .gpio_base = COLLIE_TC35143_GPIO_BASE, |
97 | .codec_pdata = &collie_ucb1x00_data, | ||
98 | }; | 92 | }; |
99 | 93 | ||
100 | /* | 94 | /* |
@@ -144,8 +138,6 @@ static struct pda_power_pdata collie_power_data = { | |||
144 | static struct resource collie_power_resource[] = { | 138 | static struct resource collie_power_resource[] = { |
145 | { | 139 | { |
146 | .name = "ac", | 140 | .name = "ac", |
147 | .start = gpio_to_irq(COLLIE_GPIO_AC_IN), | ||
148 | .end = gpio_to_irq(COLLIE_GPIO_AC_IN), | ||
149 | .flags = IORESOURCE_IRQ | | 141 | .flags = IORESOURCE_IRQ | |
150 | IORESOURCE_IRQ_HIGHEDGE | | 142 | IORESOURCE_IRQ_HIGHEDGE | |
151 | IORESOURCE_IRQ_LOWEDGE, | 143 | IORESOURCE_IRQ_LOWEDGE, |
@@ -347,7 +339,8 @@ static void __init collie_init(void) | |||
347 | 339 | ||
348 | GPSR |= _COLLIE_GPIO_UCB1x00_RESET; | 340 | GPSR |= _COLLIE_GPIO_UCB1x00_RESET; |
349 | 341 | ||
350 | 342 | collie_power_resource[0].start = gpio_to_irq(COLLIE_GPIO_AC_IN); | |
343 | collie_power_resource[0].end = gpio_to_irq(COLLIE_GPIO_AC_IN); | ||
351 | platform_scoop_config = &collie_pcmcia_config; | 344 | platform_scoop_config = &collie_pcmcia_config; |
352 | 345 | ||
353 | ret = platform_add_devices(devices, ARRAY_SIZE(devices)); | 346 | ret = platform_add_devices(devices, ARRAY_SIZE(devices)); |
@@ -357,16 +350,6 @@ static void __init collie_init(void) | |||
357 | 350 | ||
358 | sa11x0_register_mtd(&collie_flash_data, collie_flash_resources, | 351 | sa11x0_register_mtd(&collie_flash_data, collie_flash_resources, |
359 | ARRAY_SIZE(collie_flash_resources)); | 352 | ARRAY_SIZE(collie_flash_resources)); |
360 | |||
361 | /* | ||
362 | * Setup the PPC unit correctly. | ||
363 | */ | ||
364 | PPDR &= ~PPC_RXD4; | ||
365 | PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM; | ||
366 | PSDR |= PPC_RXD4; | ||
367 | PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); | ||
368 | PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); | ||
369 | |||
370 | sa11x0_register_mcp(&collie_mcp_data); | 353 | sa11x0_register_mcp(&collie_mcp_data); |
371 | 354 | ||
372 | sharpsl_save_param(); | 355 | sharpsl_save_param(); |
diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c index aaa8acf76b7b..19b2053f5af4 100644 --- a/arch/arm/mach-sa1100/cpu-sa1100.c +++ b/arch/arm/mach-sa1100/cpu-sa1100.c | |||
@@ -228,7 +228,7 @@ static int __init sa1100_cpu_init(struct cpufreq_policy *policy) | |||
228 | return 0; | 228 | return 0; |
229 | } | 229 | } |
230 | 230 | ||
231 | static struct cpufreq_driver sa1100_driver = { | 231 | static struct cpufreq_driver sa1100_driver __refdata = { |
232 | .flags = CPUFREQ_STICKY, | 232 | .flags = CPUFREQ_STICKY, |
233 | .verify = sa11x0_verify_speed, | 233 | .verify = sa11x0_verify_speed, |
234 | .target = sa1100_target, | 234 | .target = sa1100_target, |
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c index e3a28ca2a7b7..bb10ee2cb89f 100644 --- a/arch/arm/mach-sa1100/generic.c +++ b/arch/arm/mach-sa1100/generic.c | |||
@@ -217,15 +217,10 @@ static struct platform_device sa11x0uart3_device = { | |||
217 | static struct resource sa11x0mcp_resources[] = { | 217 | static struct resource sa11x0mcp_resources[] = { |
218 | [0] = { | 218 | [0] = { |
219 | .start = __PREG(Ser4MCCR0), | 219 | .start = __PREG(Ser4MCCR0), |
220 | .end = __PREG(Ser4MCCR0) + 0x1C - 1, | 220 | .end = __PREG(Ser4MCCR0) + 0xffff, |
221 | .flags = IORESOURCE_MEM, | 221 | .flags = IORESOURCE_MEM, |
222 | }, | 222 | }, |
223 | [1] = { | 223 | [1] = { |
224 | .start = __PREG(Ser4MCCR1), | ||
225 | .end = __PREG(Ser4MCCR1) + 0x4 - 1, | ||
226 | .flags = IORESOURCE_MEM, | ||
227 | }, | ||
228 | [2] = { | ||
229 | .start = IRQ_Ser4MCP, | 224 | .start = IRQ_Ser4MCP, |
230 | .end = IRQ_Ser4MCP, | 225 | .end = IRQ_Ser4MCP, |
231 | .flags = IORESOURCE_IRQ, | 226 | .flags = IORESOURCE_IRQ, |
@@ -350,29 +345,9 @@ void sa11x0_register_irda(struct irda_platform_data *irda) | |||
350 | sa11x0_register_device(&sa11x0ir_device, irda); | 345 | sa11x0_register_device(&sa11x0ir_device, irda); |
351 | } | 346 | } |
352 | 347 | ||
353 | static struct resource sa11x0rtc_resources[] = { | ||
354 | [0] = { | ||
355 | .start = 0x90010000, | ||
356 | .end = 0x900100ff, | ||
357 | .flags = IORESOURCE_MEM, | ||
358 | }, | ||
359 | [1] = { | ||
360 | .start = IRQ_RTC1Hz, | ||
361 | .end = IRQ_RTC1Hz, | ||
362 | .flags = IORESOURCE_IRQ, | ||
363 | }, | ||
364 | [2] = { | ||
365 | .start = IRQ_RTCAlrm, | ||
366 | .end = IRQ_RTCAlrm, | ||
367 | .flags = IORESOURCE_IRQ, | ||
368 | }, | ||
369 | }; | ||
370 | |||
371 | static struct platform_device sa11x0rtc_device = { | 348 | static struct platform_device sa11x0rtc_device = { |
372 | .name = "sa1100-rtc", | 349 | .name = "sa1100-rtc", |
373 | .id = -1, | 350 | .id = -1, |
374 | .resource = sa11x0rtc_resources, | ||
375 | .num_resources = ARRAY_SIZE(sa11x0rtc_resources), | ||
376 | }; | 351 | }; |
377 | 352 | ||
378 | static struct platform_device *sa11x0_devices[] __initdata = { | 353 | static struct platform_device *sa11x0_devices[] __initdata = { |
diff --git a/arch/arm/mach-sa1100/include/mach/mcp.h b/arch/arm/mach-sa1100/include/mach/mcp.h index 586cec898b35..ed1a331508a7 100644 --- a/arch/arm/mach-sa1100/include/mach/mcp.h +++ b/arch/arm/mach-sa1100/include/mach/mcp.h | |||
@@ -17,8 +17,6 @@ struct mcp_plat_data { | |||
17 | u32 mccr1; | 17 | u32 mccr1; |
18 | unsigned int sclk_rate; | 18 | unsigned int sclk_rate; |
19 | int gpio_base; | 19 | int gpio_base; |
20 | const char *codec; | ||
21 | void *codec_pdata; | ||
22 | }; | 20 | }; |
23 | 21 | ||
24 | #endif | 22 | #endif |
diff --git a/arch/arm/mach-sa1100/jornada720_ssp.c b/arch/arm/mach-sa1100/jornada720_ssp.c index f50b00bd18a0..b412fc09c80c 100644 --- a/arch/arm/mach-sa1100/jornada720_ssp.c +++ b/arch/arm/mach-sa1100/jornada720_ssp.c | |||
@@ -198,3 +198,5 @@ static int __init jornada_ssp_init(void) | |||
198 | { | 198 | { |
199 | return platform_driver_register(&jornadassp_driver); | 199 | return platform_driver_register(&jornadassp_driver); |
200 | } | 200 | } |
201 | |||
202 | module_init(jornada_ssp_init); | ||
diff --git a/arch/arm/mach-sa1100/lart.c b/arch/arm/mach-sa1100/lart.c index d117ceab6215..af4e2761f3db 100644 --- a/arch/arm/mach-sa1100/lart.c +++ b/arch/arm/mach-sa1100/lart.c | |||
@@ -24,20 +24,10 @@ | |||
24 | static struct mcp_plat_data lart_mcp_data = { | 24 | static struct mcp_plat_data lart_mcp_data = { |
25 | .mccr0 = MCCR0_ADM, | 25 | .mccr0 = MCCR0_ADM, |
26 | .sclk_rate = 11981000, | 26 | .sclk_rate = 11981000, |
27 | .codec = "ucb1x00", | ||
28 | }; | 27 | }; |
29 | 28 | ||
30 | static void __init lart_init(void) | 29 | static void __init lart_init(void) |
31 | { | 30 | { |
32 | /* | ||
33 | * Setup the PPC unit correctly. | ||
34 | */ | ||
35 | PPDR &= ~PPC_RXD4; | ||
36 | PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM; | ||
37 | PSDR |= PPC_RXD4; | ||
38 | PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); | ||
39 | PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); | ||
40 | |||
41 | sa11x0_register_mcp(&lart_mcp_data); | 31 | sa11x0_register_mcp(&lart_mcp_data); |
42 | } | 32 | } |
43 | 33 | ||
diff --git a/arch/arm/mach-sa1100/shannon.c b/arch/arm/mach-sa1100/shannon.c index 748d34435b3f..318b2b766a0b 100644 --- a/arch/arm/mach-sa1100/shannon.c +++ b/arch/arm/mach-sa1100/shannon.c | |||
@@ -55,22 +55,11 @@ static struct resource shannon_flash_resource = { | |||
55 | static struct mcp_plat_data shannon_mcp_data = { | 55 | static struct mcp_plat_data shannon_mcp_data = { |
56 | .mccr0 = MCCR0_ADM, | 56 | .mccr0 = MCCR0_ADM, |
57 | .sclk_rate = 11981000, | 57 | .sclk_rate = 11981000, |
58 | .codec = "ucb1x00", | ||
59 | }; | 58 | }; |
60 | 59 | ||
61 | static void __init shannon_init(void) | 60 | static void __init shannon_init(void) |
62 | { | 61 | { |
63 | sa11x0_register_mtd(&shannon_flash_data, &shannon_flash_resource, 1); | 62 | sa11x0_register_mtd(&shannon_flash_data, &shannon_flash_resource, 1); |
64 | |||
65 | /* | ||
66 | * Setup the PPC unit correctly. | ||
67 | */ | ||
68 | PPDR &= ~PPC_RXD4; | ||
69 | PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM; | ||
70 | PSDR |= PPC_RXD4; | ||
71 | PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); | ||
72 | PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); | ||
73 | |||
74 | sa11x0_register_mcp(&shannon_mcp_data); | 63 | sa11x0_register_mcp(&shannon_mcp_data); |
75 | } | 64 | } |
76 | 65 | ||
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c index 458ececefa58..e17c04d6e324 100644 --- a/arch/arm/mach-sa1100/simpad.c +++ b/arch/arm/mach-sa1100/simpad.c | |||
@@ -14,7 +14,6 @@ | |||
14 | #include <linux/mtd/partitions.h> | 14 | #include <linux/mtd/partitions.h> |
15 | #include <linux/io.h> | 15 | #include <linux/io.h> |
16 | #include <linux/gpio.h> | 16 | #include <linux/gpio.h> |
17 | #include <linux/mfd/ucb1x00.h> | ||
18 | 17 | ||
19 | #include <asm/irq.h> | 18 | #include <asm/irq.h> |
20 | #include <mach/hardware.h> | 19 | #include <mach/hardware.h> |
@@ -188,15 +187,10 @@ static struct resource simpad_flash_resources [] = { | |||
188 | } | 187 | } |
189 | }; | 188 | }; |
190 | 189 | ||
191 | static struct ucb1x00_plat_data simpad_ucb1x00_data = { | ||
192 | .gpio_base = SIMPAD_UCB1X00_GPIO_BASE, | ||
193 | }; | ||
194 | |||
195 | static struct mcp_plat_data simpad_mcp_data = { | 190 | static struct mcp_plat_data simpad_mcp_data = { |
196 | .mccr0 = MCCR0_ADM, | 191 | .mccr0 = MCCR0_ADM, |
197 | .sclk_rate = 11981000, | 192 | .sclk_rate = 11981000, |
198 | .codec = "ucb1300", | 193 | .gpio_base = SIMPAD_UCB1X00_GPIO_BASE, |
199 | .codec_pdata = &simpad_ucb1x00_data, | ||
200 | }; | 194 | }; |
201 | 195 | ||
202 | 196 | ||
@@ -384,16 +378,6 @@ static int __init simpad_init(void) | |||
384 | 378 | ||
385 | sa11x0_register_mtd(&simpad_flash_data, simpad_flash_resources, | 379 | sa11x0_register_mtd(&simpad_flash_data, simpad_flash_resources, |
386 | ARRAY_SIZE(simpad_flash_resources)); | 380 | ARRAY_SIZE(simpad_flash_resources)); |
387 | |||
388 | /* | ||
389 | * Setup the PPC unit correctly. | ||
390 | */ | ||
391 | PPDR &= ~PPC_RXD4; | ||
392 | PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM; | ||
393 | PSDR |= PPC_RXD4; | ||
394 | PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); | ||
395 | PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); | ||
396 | |||
397 | sa11x0_register_mcp(&simpad_mcp_data); | 381 | sa11x0_register_mcp(&simpad_mcp_data); |
398 | 382 | ||
399 | ret = platform_add_devices(devices, ARRAY_SIZE(devices)); | 383 | ret = platform_add_devices(devices, ARRAY_SIZE(devices)); |
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c index eff8a96c75ee..068b754bc348 100644 --- a/arch/arm/mach-shmobile/board-ag5evm.c +++ b/arch/arm/mach-shmobile/board-ag5evm.c | |||
@@ -30,6 +30,7 @@ | |||
30 | #include <linux/serial_sci.h> | 30 | #include <linux/serial_sci.h> |
31 | #include <linux/smsc911x.h> | 31 | #include <linux/smsc911x.h> |
32 | #include <linux/gpio.h> | 32 | #include <linux/gpio.h> |
33 | #include <linux/videodev2.h> | ||
33 | #include <linux/input.h> | 34 | #include <linux/input.h> |
34 | #include <linux/input/sh_keysc.h> | 35 | #include <linux/input/sh_keysc.h> |
35 | #include <linux/mmc/host.h> | 36 | #include <linux/mmc/host.h> |
@@ -37,7 +38,6 @@ | |||
37 | #include <linux/mmc/sh_mobile_sdhi.h> | 38 | #include <linux/mmc/sh_mobile_sdhi.h> |
38 | #include <linux/mfd/tmio.h> | 39 | #include <linux/mfd/tmio.h> |
39 | #include <linux/sh_clk.h> | 40 | #include <linux/sh_clk.h> |
40 | #include <linux/dma-mapping.h> | ||
41 | #include <video/sh_mobile_lcdc.h> | 41 | #include <video/sh_mobile_lcdc.h> |
42 | #include <video/sh_mipi_dsi.h> | 42 | #include <video/sh_mipi_dsi.h> |
43 | #include <sound/sh_fsi.h> | 43 | #include <sound/sh_fsi.h> |
@@ -159,19 +159,12 @@ static struct resource sh_mmcif_resources[] = { | |||
159 | }, | 159 | }, |
160 | }; | 160 | }; |
161 | 161 | ||
162 | static struct sh_mmcif_dma sh_mmcif_dma = { | ||
163 | .chan_priv_rx = { | ||
164 | .slave_id = SHDMA_SLAVE_MMCIF_RX, | ||
165 | }, | ||
166 | .chan_priv_tx = { | ||
167 | .slave_id = SHDMA_SLAVE_MMCIF_TX, | ||
168 | }, | ||
169 | }; | ||
170 | static struct sh_mmcif_plat_data sh_mmcif_platdata = { | 162 | static struct sh_mmcif_plat_data sh_mmcif_platdata = { |
171 | .sup_pclk = 0, | 163 | .sup_pclk = 0, |
172 | .ocr = MMC_VDD_165_195, | 164 | .ocr = MMC_VDD_165_195, |
173 | .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, | 165 | .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, |
174 | .dma = &sh_mmcif_dma, | 166 | .slave_id_tx = SHDMA_SLAVE_MMCIF_TX, |
167 | .slave_id_rx = SHDMA_SLAVE_MMCIF_RX, | ||
175 | }; | 168 | }; |
176 | 169 | ||
177 | static struct platform_device mmc_device = { | 170 | static struct platform_device mmc_device = { |
@@ -321,12 +314,11 @@ static struct resource mipidsi0_resources[] = { | |||
321 | }, | 314 | }, |
322 | }; | 315 | }; |
323 | 316 | ||
324 | #define DSI0PHYCR 0xe615006c | ||
325 | static int sh_mipi_set_dot_clock(struct platform_device *pdev, | 317 | static int sh_mipi_set_dot_clock(struct platform_device *pdev, |
326 | void __iomem *base, | 318 | void __iomem *base, |
327 | int enable) | 319 | int enable) |
328 | { | 320 | { |
329 | struct clk *pck; | 321 | struct clk *pck, *phy; |
330 | int ret; | 322 | int ret; |
331 | 323 | ||
332 | pck = clk_get(&pdev->dev, "dsip_clk"); | 324 | pck = clk_get(&pdev->dev, "dsip_clk"); |
@@ -335,18 +327,27 @@ static int sh_mipi_set_dot_clock(struct platform_device *pdev, | |||
335 | goto sh_mipi_set_dot_clock_pck_err; | 327 | goto sh_mipi_set_dot_clock_pck_err; |
336 | } | 328 | } |
337 | 329 | ||
330 | phy = clk_get(&pdev->dev, "dsiphy_clk"); | ||
331 | if (IS_ERR(phy)) { | ||
332 | ret = PTR_ERR(phy); | ||
333 | goto sh_mipi_set_dot_clock_phy_err; | ||
334 | } | ||
335 | |||
338 | if (enable) { | 336 | if (enable) { |
339 | clk_set_rate(pck, clk_round_rate(pck, 24000000)); | 337 | clk_set_rate(pck, clk_round_rate(pck, 24000000)); |
340 | __raw_writel(0x2a809010, DSI0PHYCR); | 338 | clk_set_rate(phy, clk_round_rate(pck, 510000000)); |
341 | clk_enable(pck); | 339 | clk_enable(pck); |
340 | clk_enable(phy); | ||
342 | } else { | 341 | } else { |
343 | clk_disable(pck); | 342 | clk_disable(pck); |
343 | clk_disable(phy); | ||
344 | } | 344 | } |
345 | 345 | ||
346 | ret = 0; | 346 | ret = 0; |
347 | 347 | ||
348 | clk_put(phy); | ||
349 | sh_mipi_set_dot_clock_phy_err: | ||
348 | clk_put(pck); | 350 | clk_put(pck); |
349 | |||
350 | sh_mipi_set_dot_clock_pck_err: | 351 | sh_mipi_set_dot_clock_pck_err: |
351 | return ret; | 352 | return ret; |
352 | } | 353 | } |
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index aab0a349f759..eeb4d9664584 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c | |||
@@ -295,15 +295,6 @@ static struct resource sh_mmcif_resources[] = { | |||
295 | }, | 295 | }, |
296 | }; | 296 | }; |
297 | 297 | ||
298 | static struct sh_mmcif_dma sh_mmcif_dma = { | ||
299 | .chan_priv_rx = { | ||
300 | .slave_id = SHDMA_SLAVE_MMCIF_RX, | ||
301 | }, | ||
302 | .chan_priv_tx = { | ||
303 | .slave_id = SHDMA_SLAVE_MMCIF_TX, | ||
304 | }, | ||
305 | }; | ||
306 | |||
307 | static struct sh_mmcif_plat_data sh_mmcif_plat = { | 298 | static struct sh_mmcif_plat_data sh_mmcif_plat = { |
308 | .sup_pclk = 0, | 299 | .sup_pclk = 0, |
309 | .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, | 300 | .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, |
@@ -311,7 +302,8 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = { | |||
311 | MMC_CAP_8_BIT_DATA | | 302 | MMC_CAP_8_BIT_DATA | |
312 | MMC_CAP_NEEDS_POLL, | 303 | MMC_CAP_NEEDS_POLL, |
313 | .get_cd = slot_cn7_get_cd, | 304 | .get_cd = slot_cn7_get_cd, |
314 | .dma = &sh_mmcif_dma, | 305 | .slave_id_tx = SHDMA_SLAVE_MMCIF_TX, |
306 | .slave_id_rx = SHDMA_SLAVE_MMCIF_RX, | ||
315 | }; | 307 | }; |
316 | 308 | ||
317 | static struct platform_device sh_mmcif_device = { | 309 | static struct platform_device sh_mmcif_device = { |
diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c index 857ceeec1bb0..c8e7ca23fc06 100644 --- a/arch/arm/mach-shmobile/board-kota2.c +++ b/arch/arm/mach-shmobile/board-kota2.c | |||
@@ -143,11 +143,10 @@ static struct gpio_keys_button gpio_buttons[] = { | |||
143 | static struct gpio_keys_platform_data gpio_key_info = { | 143 | static struct gpio_keys_platform_data gpio_key_info = { |
144 | .buttons = gpio_buttons, | 144 | .buttons = gpio_buttons, |
145 | .nbuttons = ARRAY_SIZE(gpio_buttons), | 145 | .nbuttons = ARRAY_SIZE(gpio_buttons), |
146 | .poll_interval = 250, /* polled for now */ | ||
147 | }; | 146 | }; |
148 | 147 | ||
149 | static struct platform_device gpio_keys_device = { | 148 | static struct platform_device gpio_keys_device = { |
150 | .name = "gpio-keys-polled", /* polled for now */ | 149 | .name = "gpio-keys", |
151 | .id = -1, | 150 | .id = -1, |
152 | .dev = { | 151 | .dev = { |
153 | .platform_data = &gpio_key_info, | 152 | .platform_data = &gpio_key_info, |
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index 9b42fbd10f8e..a2813247b455 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c | |||
@@ -43,7 +43,6 @@ | |||
43 | #include <linux/smsc911x.h> | 43 | #include <linux/smsc911x.h> |
44 | #include <linux/sh_intc.h> | 44 | #include <linux/sh_intc.h> |
45 | #include <linux/tca6416_keypad.h> | 45 | #include <linux/tca6416_keypad.h> |
46 | #include <linux/usb/r8a66597.h> | ||
47 | #include <linux/usb/renesas_usbhs.h> | 46 | #include <linux/usb/renesas_usbhs.h> |
48 | #include <linux/dma-mapping.h> | 47 | #include <linux/dma-mapping.h> |
49 | 48 | ||
@@ -145,11 +144,6 @@ | |||
145 | * 1-2 short | VBUS 5V | Host | 144 | * 1-2 short | VBUS 5V | Host |
146 | * open | external VBUS | Function | 145 | * open | external VBUS | Function |
147 | * | 146 | * |
148 | * *1 | ||
149 | * CN31 is used as | ||
150 | * CONFIG_USB_R8A66597_HCD Host | ||
151 | * CONFIG_USB_RENESAS_USBHS Function | ||
152 | * | ||
153 | * CAUTION | 147 | * CAUTION |
154 | * | 148 | * |
155 | * renesas_usbhs driver can use external interrupt mode | 149 | * renesas_usbhs driver can use external interrupt mode |
@@ -161,15 +155,6 @@ | |||
161 | * mackerel can not use external interrupt (IRQ7-PORT167) mode on "USB0", | 155 | * mackerel can not use external interrupt (IRQ7-PORT167) mode on "USB0", |
162 | * because Touchscreen is using IRQ7-PORT40. | 156 | * because Touchscreen is using IRQ7-PORT40. |
163 | * It is impossible to use IRQ7 demux on this board. | 157 | * It is impossible to use IRQ7 demux on this board. |
164 | * | ||
165 | * We can use external interrupt mode USB-Function on "USB1". | ||
166 | * USB1 can become Host by r8a66597, and become Function by renesas_usbhs. | ||
167 | * But don't select both drivers in same time. | ||
168 | * These uses same IRQ number for request_irq(), and aren't supporting | ||
169 | * IRQF_SHARED / IORESOURCE_IRQ_SHAREABLE. | ||
170 | * | ||
171 | * Actually these are old/new version of USB driver. | ||
172 | * This mean its register will be broken if it supports shared IRQ, | ||
173 | */ | 158 | */ |
174 | 159 | ||
175 | /* | 160 | /* |
@@ -208,6 +193,16 @@ | |||
208 | */ | 193 | */ |
209 | 194 | ||
210 | /* | 195 | /* |
196 | * FSI - AK4642 | ||
197 | * | ||
198 | * it needs amixer settings for playing | ||
199 | * | ||
200 | * amixer set "Headphone" on | ||
201 | * amixer set "HPOUTL Mixer DACH" on | ||
202 | * amixer set "HPOUTR Mixer DACH" on | ||
203 | */ | ||
204 | |||
205 | /* | ||
211 | * FIXME !! | 206 | * FIXME !! |
212 | * | 207 | * |
213 | * gpio_no_direction | 208 | * gpio_no_direction |
@@ -676,51 +671,16 @@ static struct platform_device usbhs0_device = { | |||
676 | * Use J30 to select between Host and Function. This setting | 671 | * Use J30 to select between Host and Function. This setting |
677 | * can however not be detected by software. Hotplug of USBHS1 | 672 | * can however not be detected by software. Hotplug of USBHS1 |
678 | * is provided via IRQ8. | 673 | * is provided via IRQ8. |
674 | * | ||
675 | * Current USB1 works as "USB Host". | ||
676 | * - set J30 "short" | ||
677 | * | ||
678 | * If you want to use it as "USB gadget", | ||
679 | * - J30 "open" | ||
680 | * - modify usbhs1_get_id() USBHS_HOST -> USBHS_GADGET | ||
681 | * - add .get_vbus = usbhs_get_vbus in usbhs1_private | ||
679 | */ | 682 | */ |
680 | #define IRQ8 evt2irq(0x0300) | 683 | #define IRQ8 evt2irq(0x0300) |
681 | |||
682 | /* USBHS1 USB Host support via r8a66597_hcd */ | ||
683 | static void usb1_host_port_power(int port, int power) | ||
684 | { | ||
685 | if (!power) /* only power-on is supported for now */ | ||
686 | return; | ||
687 | |||
688 | /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */ | ||
689 | __raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008); | ||
690 | } | ||
691 | |||
692 | static struct r8a66597_platdata usb1_host_data = { | ||
693 | .on_chip = 1, | ||
694 | .port_power = usb1_host_port_power, | ||
695 | }; | ||
696 | |||
697 | static struct resource usb1_host_resources[] = { | ||
698 | [0] = { | ||
699 | .name = "USBHS1", | ||
700 | .start = 0xe68b0000, | ||
701 | .end = 0xe68b00e6 - 1, | ||
702 | .flags = IORESOURCE_MEM, | ||
703 | }, | ||
704 | [1] = { | ||
705 | .start = evt2irq(0x1ce0) /* USB1_USB1I0 */, | ||
706 | .flags = IORESOURCE_IRQ, | ||
707 | }, | ||
708 | }; | ||
709 | |||
710 | static struct platform_device usb1_host_device = { | ||
711 | .name = "r8a66597_hcd", | ||
712 | .id = 1, | ||
713 | .dev = { | ||
714 | .dma_mask = NULL, /* not use dma */ | ||
715 | .coherent_dma_mask = 0xffffffff, | ||
716 | .platform_data = &usb1_host_data, | ||
717 | }, | ||
718 | .num_resources = ARRAY_SIZE(usb1_host_resources), | ||
719 | .resource = usb1_host_resources, | ||
720 | }; | ||
721 | |||
722 | /* USBHS1 USB Function support via renesas_usbhs */ | ||
723 | |||
724 | #define USB_PHY_MODE (1 << 4) | 684 | #define USB_PHY_MODE (1 << 4) |
725 | #define USB_PHY_INT_EN ((1 << 3) | (1 << 2)) | 685 | #define USB_PHY_INT_EN ((1 << 3) | (1 << 2)) |
726 | #define USB_PHY_ON (1 << 1) | 686 | #define USB_PHY_ON (1 << 1) |
@@ -776,7 +736,7 @@ static void usbhs1_hardware_exit(struct platform_device *pdev) | |||
776 | 736 | ||
777 | static int usbhs1_get_id(struct platform_device *pdev) | 737 | static int usbhs1_get_id(struct platform_device *pdev) |
778 | { | 738 | { |
779 | return USBHS_GADGET; | 739 | return USBHS_HOST; |
780 | } | 740 | } |
781 | 741 | ||
782 | static u32 usbhs1_pipe_cfg[] = { | 742 | static u32 usbhs1_pipe_cfg[] = { |
@@ -807,7 +767,6 @@ static struct usbhs_private usbhs1_private = { | |||
807 | .hardware_exit = usbhs1_hardware_exit, | 767 | .hardware_exit = usbhs1_hardware_exit, |
808 | .get_id = usbhs1_get_id, | 768 | .get_id = usbhs1_get_id, |
809 | .phy_reset = usbhs_phy_reset, | 769 | .phy_reset = usbhs_phy_reset, |
810 | .get_vbus = usbhs_get_vbus, | ||
811 | }, | 770 | }, |
812 | .driver_param = { | 771 | .driver_param = { |
813 | .buswait_bwait = 4, | 772 | .buswait_bwait = 4, |
@@ -1184,15 +1143,6 @@ static struct resource sh_mmcif_resources[] = { | |||
1184 | }, | 1143 | }, |
1185 | }; | 1144 | }; |
1186 | 1145 | ||
1187 | static struct sh_mmcif_dma sh_mmcif_dma = { | ||
1188 | .chan_priv_rx = { | ||
1189 | .slave_id = SHDMA_SLAVE_MMCIF_RX, | ||
1190 | }, | ||
1191 | .chan_priv_tx = { | ||
1192 | .slave_id = SHDMA_SLAVE_MMCIF_TX, | ||
1193 | }, | ||
1194 | }; | ||
1195 | |||
1196 | static struct sh_mmcif_plat_data sh_mmcif_plat = { | 1146 | static struct sh_mmcif_plat_data sh_mmcif_plat = { |
1197 | .sup_pclk = 0, | 1147 | .sup_pclk = 0, |
1198 | .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, | 1148 | .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, |
@@ -1200,7 +1150,8 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = { | |||
1200 | MMC_CAP_8_BIT_DATA | | 1150 | MMC_CAP_8_BIT_DATA | |
1201 | MMC_CAP_NEEDS_POLL, | 1151 | MMC_CAP_NEEDS_POLL, |
1202 | .get_cd = slot_cn7_get_cd, | 1152 | .get_cd = slot_cn7_get_cd, |
1203 | .dma = &sh_mmcif_dma, | 1153 | .slave_id_tx = SHDMA_SLAVE_MMCIF_TX, |
1154 | .slave_id_rx = SHDMA_SLAVE_MMCIF_RX, | ||
1204 | }; | 1155 | }; |
1205 | 1156 | ||
1206 | static struct platform_device sh_mmcif_device = { | 1157 | static struct platform_device sh_mmcif_device = { |
@@ -1311,7 +1262,6 @@ static struct platform_device *mackerel_devices[] __initdata = { | |||
1311 | &nor_flash_device, | 1262 | &nor_flash_device, |
1312 | &smc911x_device, | 1263 | &smc911x_device, |
1313 | &lcdc_device, | 1264 | &lcdc_device, |
1314 | &usb1_host_device, | ||
1315 | &usbhs1_device, | 1265 | &usbhs1_device, |
1316 | &usbhs0_device, | 1266 | &usbhs0_device, |
1317 | &leds_device, | 1267 | &leds_device, |
@@ -1473,9 +1423,6 @@ static void __init mackerel_init(void) | |||
1473 | gpio_pull_down(GPIO_PORT167CR); /* VBUS0_1 pull down */ | 1423 | gpio_pull_down(GPIO_PORT167CR); /* VBUS0_1 pull down */ |
1474 | gpio_request(GPIO_FN_IDIN_1_113, NULL); | 1424 | gpio_request(GPIO_FN_IDIN_1_113, NULL); |
1475 | 1425 | ||
1476 | /* USB phy tweak to make the r8a66597_hcd host driver work */ | ||
1477 | __raw_writew(0x8a0a, 0xe6058130); /* USBCR4 */ | ||
1478 | |||
1479 | /* enable FSI2 port A (ak4643) */ | 1426 | /* enable FSI2 port A (ak4643) */ |
1480 | gpio_request(GPIO_FN_FSIAIBT, NULL); | 1427 | gpio_request(GPIO_FN_FSIAIBT, NULL); |
1481 | gpio_request(GPIO_FN_FSIAILR, NULL); | 1428 | gpio_request(GPIO_FN_FSIAILR, NULL); |
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index afbead6a6e17..7727cca6136c 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c | |||
@@ -365,6 +365,114 @@ static struct clk div6_clks[DIV6_NR] = { | |||
365 | dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3), | 365 | dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3), |
366 | }; | 366 | }; |
367 | 367 | ||
368 | /* DSI DIV */ | ||
369 | static unsigned long dsiphy_recalc(struct clk *clk) | ||
370 | { | ||
371 | u32 value; | ||
372 | |||
373 | value = __raw_readl(clk->mapping->base); | ||
374 | |||
375 | /* FIXME */ | ||
376 | if (!(value & 0x000B8000)) | ||
377 | return clk->parent->rate; | ||
378 | |||
379 | value &= 0x3f; | ||
380 | value += 1; | ||
381 | |||
382 | if ((value < 12) || | ||
383 | (value > 33)) { | ||
384 | pr_err("DSIPHY has wrong value (%d)", value); | ||
385 | return 0; | ||
386 | } | ||
387 | |||
388 | return clk->parent->rate / value; | ||
389 | } | ||
390 | |||
391 | static long dsiphy_round_rate(struct clk *clk, unsigned long rate) | ||
392 | { | ||
393 | return clk_rate_mult_range_round(clk, 12, 33, rate); | ||
394 | } | ||
395 | |||
396 | static void dsiphy_disable(struct clk *clk) | ||
397 | { | ||
398 | u32 value; | ||
399 | |||
400 | value = __raw_readl(clk->mapping->base); | ||
401 | value &= ~0x000B8000; | ||
402 | |||
403 | __raw_writel(value , clk->mapping->base); | ||
404 | } | ||
405 | |||
406 | static int dsiphy_enable(struct clk *clk) | ||
407 | { | ||
408 | u32 value; | ||
409 | int multi; | ||
410 | |||
411 | value = __raw_readl(clk->mapping->base); | ||
412 | multi = (value & 0x3f) + 1; | ||
413 | |||
414 | if ((multi < 12) || (multi > 33)) | ||
415 | return -EIO; | ||
416 | |||
417 | __raw_writel(value | 0x000B8000, clk->mapping->base); | ||
418 | |||
419 | return 0; | ||
420 | } | ||
421 | |||
422 | static int dsiphy_set_rate(struct clk *clk, unsigned long rate) | ||
423 | { | ||
424 | u32 value; | ||
425 | int idx; | ||
426 | |||
427 | idx = rate / clk->parent->rate; | ||
428 | if ((idx < 12) || (idx > 33)) | ||
429 | return -EINVAL; | ||
430 | |||
431 | idx += -1; | ||
432 | |||
433 | value = __raw_readl(clk->mapping->base); | ||
434 | value = (value & ~0x3f) + idx; | ||
435 | |||
436 | __raw_writel(value, clk->mapping->base); | ||
437 | |||
438 | return 0; | ||
439 | } | ||
440 | |||
441 | static struct clk_ops dsiphy_clk_ops = { | ||
442 | .recalc = dsiphy_recalc, | ||
443 | .round_rate = dsiphy_round_rate, | ||
444 | .set_rate = dsiphy_set_rate, | ||
445 | .enable = dsiphy_enable, | ||
446 | .disable = dsiphy_disable, | ||
447 | }; | ||
448 | |||
449 | static struct clk_mapping dsi0phy_clk_mapping = { | ||
450 | .phys = DSI0PHYCR, | ||
451 | .len = 4, | ||
452 | }; | ||
453 | |||
454 | static struct clk_mapping dsi1phy_clk_mapping = { | ||
455 | .phys = DSI1PHYCR, | ||
456 | .len = 4, | ||
457 | }; | ||
458 | |||
459 | static struct clk dsi0phy_clk = { | ||
460 | .ops = &dsiphy_clk_ops, | ||
461 | .parent = &div6_clks[DIV6_DSI0P], /* late install */ | ||
462 | .mapping = &dsi0phy_clk_mapping, | ||
463 | }; | ||
464 | |||
465 | static struct clk dsi1phy_clk = { | ||
466 | .ops = &dsiphy_clk_ops, | ||
467 | .parent = &div6_clks[DIV6_DSI1P], /* late install */ | ||
468 | .mapping = &dsi1phy_clk_mapping, | ||
469 | }; | ||
470 | |||
471 | static struct clk *late_main_clks[] = { | ||
472 | &dsi0phy_clk, | ||
473 | &dsi1phy_clk, | ||
474 | }; | ||
475 | |||
368 | enum { MSTP001, | 476 | enum { MSTP001, |
369 | MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100, | 477 | MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100, |
370 | MSTP219, | 478 | MSTP219, |
@@ -429,6 +537,8 @@ static struct clk_lookup lookups[] = { | |||
429 | CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]), | 537 | CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]), |
430 | CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]), | 538 | CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]), |
431 | CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]), | 539 | CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]), |
540 | CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.0", &dsi0phy_clk), | ||
541 | CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.1", &dsi1phy_clk), | ||
432 | 542 | ||
433 | /* MSTP32 clocks */ | 543 | /* MSTP32 clocks */ |
434 | CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */ | 544 | CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */ |
@@ -504,6 +614,9 @@ void __init sh73a0_clock_init(void) | |||
504 | if (!ret) | 614 | if (!ret) |
505 | ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); | 615 | ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); |
506 | 616 | ||
617 | for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++) | ||
618 | ret = clk_register(late_main_clks[k]); | ||
619 | |||
507 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | 620 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); |
508 | 621 | ||
509 | if (!ret) | 622 | if (!ret) |
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h index 881d515a9686..cad57578ceed 100644 --- a/arch/arm/mach-shmobile/include/mach/sh73a0.h +++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h | |||
@@ -515,8 +515,8 @@ enum { | |||
515 | SHDMA_SLAVE_MMCIF_RX, | 515 | SHDMA_SLAVE_MMCIF_RX, |
516 | }; | 516 | }; |
517 | 517 | ||
518 | /* PINT interrupts are located at Linux IRQ 768 and up */ | 518 | /* PINT interrupts are located at Linux IRQ 800 and up */ |
519 | #define SH73A0_PINT0_IRQ(irq) ((irq) + 768) | 519 | #define SH73A0_PINT0_IRQ(irq) ((irq) + 800) |
520 | #define SH73A0_PINT1_IRQ(irq) ((irq) + 800) | 520 | #define SH73A0_PINT1_IRQ(irq) ((irq) + 832) |
521 | 521 | ||
522 | #endif /* __ASM_SH73A0_H__ */ | 522 | #endif /* __ASM_SH73A0_H__ */ |
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c index 1eda6b0b69e3..9857595eaa79 100644 --- a/arch/arm/mach-shmobile/intc-sh73a0.c +++ b/arch/arm/mach-shmobile/intc-sh73a0.c | |||
@@ -19,6 +19,7 @@ | |||
19 | #include <linux/kernel.h> | 19 | #include <linux/kernel.h> |
20 | #include <linux/init.h> | 20 | #include <linux/init.h> |
21 | #include <linux/interrupt.h> | 21 | #include <linux/interrupt.h> |
22 | #include <linux/module.h> | ||
22 | #include <linux/irq.h> | 23 | #include <linux/irq.h> |
23 | #include <linux/io.h> | 24 | #include <linux/io.h> |
24 | #include <linux/sh_intc.h> | 25 | #include <linux/sh_intc.h> |
@@ -445,6 +446,7 @@ void __init sh73a0_init_irq(void) | |||
445 | setup_irq(gic_spi(1 + k), &sh73a0_irq_pin_cascade[k]); | 446 | setup_irq(gic_spi(1 + k), &sh73a0_irq_pin_cascade[k]); |
446 | 447 | ||
447 | n = intcs_evt2irq(to_intc_vect(gic_spi(1 + k))); | 448 | n = intcs_evt2irq(to_intc_vect(gic_spi(1 + k))); |
449 | WARN_ON(irq_alloc_desc_at(n, numa_node_id()) != n); | ||
448 | irq_set_chip_and_handler_name(n, &intca_gic_irq_chip, | 450 | irq_set_chip_and_handler_name(n, &intca_gic_irq_chip, |
449 | handle_level_irq, "level"); | 451 | handle_level_irq, "level"); |
450 | set_irq_flags(n, IRQF_VALID); /* yuck */ | 452 | set_irq_flags(n, IRQF_VALID); /* yuck */ |
diff --git a/arch/arm/mach-shmobile/pfc-r8a7779.c b/arch/arm/mach-shmobile/pfc-r8a7779.c index 963532f2b2c4..d14c9b048077 100644 --- a/arch/arm/mach-shmobile/pfc-r8a7779.c +++ b/arch/arm/mach-shmobile/pfc-r8a7779.c | |||
@@ -2120,7 +2120,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { | |||
2120 | FN_AUDATA3, 0, 0, 0 } | 2120 | FN_AUDATA3, 0, 0, 0 } |
2121 | }, | 2121 | }, |
2122 | { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32, | 2122 | { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32, |
2123 | 3, 1, 1, 1, 1, 1, 1, 3, 3, 1, | 2123 | 3, 1, 1, 1, 1, 1, 1, 3, 3, |
2124 | 1, 1, 1, 1, 1, 1, 3, 3, 3, 2) { | 2124 | 1, 1, 1, 1, 1, 1, 3, 3, 3, 2) { |
2125 | /* IP4_31_29 [3] */ | 2125 | /* IP4_31_29 [3] */ |
2126 | FN_DU1_DB0, FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0, | 2126 | FN_DU1_DB0, FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0, |
diff --git a/arch/arm/mach-shmobile/pfc-sh7372.c b/arch/arm/mach-shmobile/pfc-sh7372.c index 1bd6585a6acf..336093f9210a 100644 --- a/arch/arm/mach-shmobile/pfc-sh7372.c +++ b/arch/arm/mach-shmobile/pfc-sh7372.c | |||
@@ -23,6 +23,7 @@ | |||
23 | #include <linux/init.h> | 23 | #include <linux/init.h> |
24 | #include <linux/kernel.h> | 24 | #include <linux/kernel.h> |
25 | #include <linux/gpio.h> | 25 | #include <linux/gpio.h> |
26 | #include <mach/irqs.h> | ||
26 | #include <mach/sh7372.h> | 27 | #include <mach/sh7372.h> |
27 | 28 | ||
28 | #define CPU_ALL_PORT(fn, pfx, sfx) \ | 29 | #define CPU_ALL_PORT(fn, pfx, sfx) \ |
@@ -1594,6 +1595,43 @@ static struct pinmux_data_reg pinmux_data_regs[] = { | |||
1594 | { }, | 1595 | { }, |
1595 | }; | 1596 | }; |
1596 | 1597 | ||
1598 | #define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5)) | ||
1599 | #define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5)) | ||
1600 | static struct pinmux_irq pinmux_irqs[] = { | ||
1601 | PINMUX_IRQ(EXT_IRQ16L(0), PORT6_FN0, PORT162_FN0), | ||
1602 | PINMUX_IRQ(EXT_IRQ16L(1), PORT12_FN0), | ||
1603 | PINMUX_IRQ(EXT_IRQ16L(2), PORT4_FN0, PORT5_FN0), | ||
1604 | PINMUX_IRQ(EXT_IRQ16L(3), PORT8_FN0, PORT16_FN0), | ||
1605 | PINMUX_IRQ(EXT_IRQ16L(4), PORT17_FN0, PORT163_FN0), | ||
1606 | PINMUX_IRQ(EXT_IRQ16L(5), PORT18_FN0), | ||
1607 | PINMUX_IRQ(EXT_IRQ16L(6), PORT39_FN0, PORT164_FN0), | ||
1608 | PINMUX_IRQ(EXT_IRQ16L(7), PORT40_FN0, PORT167_FN0), | ||
1609 | PINMUX_IRQ(EXT_IRQ16L(8), PORT41_FN0, PORT168_FN0), | ||
1610 | PINMUX_IRQ(EXT_IRQ16L(9), PORT42_FN0, PORT169_FN0), | ||
1611 | PINMUX_IRQ(EXT_IRQ16L(10), PORT65_FN0), | ||
1612 | PINMUX_IRQ(EXT_IRQ16L(11), PORT67_FN0), | ||
1613 | PINMUX_IRQ(EXT_IRQ16L(12), PORT80_FN0, PORT137_FN0), | ||
1614 | PINMUX_IRQ(EXT_IRQ16L(13), PORT81_FN0, PORT145_FN0), | ||
1615 | PINMUX_IRQ(EXT_IRQ16L(14), PORT82_FN0, PORT146_FN0), | ||
1616 | PINMUX_IRQ(EXT_IRQ16L(15), PORT83_FN0, PORT147_FN0), | ||
1617 | PINMUX_IRQ(EXT_IRQ16H(16), PORT84_FN0, PORT170_FN0), | ||
1618 | PINMUX_IRQ(EXT_IRQ16H(17), PORT85_FN0), | ||
1619 | PINMUX_IRQ(EXT_IRQ16H(18), PORT86_FN0), | ||
1620 | PINMUX_IRQ(EXT_IRQ16H(19), PORT87_FN0), | ||
1621 | PINMUX_IRQ(EXT_IRQ16H(20), PORT92_FN0), | ||
1622 | PINMUX_IRQ(EXT_IRQ16H(21), PORT93_FN0), | ||
1623 | PINMUX_IRQ(EXT_IRQ16H(22), PORT94_FN0), | ||
1624 | PINMUX_IRQ(EXT_IRQ16H(23), PORT95_FN0), | ||
1625 | PINMUX_IRQ(EXT_IRQ16H(24), PORT112_FN0), | ||
1626 | PINMUX_IRQ(EXT_IRQ16H(25), PORT119_FN0), | ||
1627 | PINMUX_IRQ(EXT_IRQ16H(26), PORT121_FN0, PORT172_FN0), | ||
1628 | PINMUX_IRQ(EXT_IRQ16H(27), PORT122_FN0, PORT180_FN0), | ||
1629 | PINMUX_IRQ(EXT_IRQ16H(28), PORT123_FN0, PORT181_FN0), | ||
1630 | PINMUX_IRQ(EXT_IRQ16H(29), PORT129_FN0, PORT182_FN0), | ||
1631 | PINMUX_IRQ(EXT_IRQ16H(30), PORT130_FN0, PORT183_FN0), | ||
1632 | PINMUX_IRQ(EXT_IRQ16H(31), PORT138_FN0, PORT184_FN0), | ||
1633 | }; | ||
1634 | |||
1597 | static struct pinmux_info sh7372_pinmux_info = { | 1635 | static struct pinmux_info sh7372_pinmux_info = { |
1598 | .name = "sh7372_pfc", | 1636 | .name = "sh7372_pfc", |
1599 | .reserved_id = PINMUX_RESERVED, | 1637 | .reserved_id = PINMUX_RESERVED, |
@@ -1614,6 +1652,9 @@ static struct pinmux_info sh7372_pinmux_info = { | |||
1614 | 1652 | ||
1615 | .gpio_data = pinmux_data, | 1653 | .gpio_data = pinmux_data, |
1616 | .gpio_data_size = ARRAY_SIZE(pinmux_data), | 1654 | .gpio_data_size = ARRAY_SIZE(pinmux_data), |
1655 | |||
1656 | .gpio_irq = pinmux_irqs, | ||
1657 | .gpio_irq_size = ARRAY_SIZE(pinmux_irqs), | ||
1617 | }; | 1658 | }; |
1618 | 1659 | ||
1619 | void sh7372_pinmux_init(void) | 1660 | void sh7372_pinmux_init(void) |
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c index 6fcf304d3cdf..a83cf51fc099 100644 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c | |||
@@ -662,6 +662,7 @@ static struct sh_dmae_pdata usb_dma0_platform_data = { | |||
662 | .dmaor_is_32bit = 1, | 662 | .dmaor_is_32bit = 1, |
663 | .needs_tend_set = 1, | 663 | .needs_tend_set = 1, |
664 | .no_dmars = 1, | 664 | .no_dmars = 1, |
665 | .slave_only = 1, | ||
665 | }; | 666 | }; |
666 | 667 | ||
667 | static struct resource sh7372_usb_dmae0_resources[] = { | 668 | static struct resource sh7372_usb_dmae0_resources[] = { |
@@ -723,6 +724,7 @@ static struct sh_dmae_pdata usb_dma1_platform_data = { | |||
723 | .dmaor_is_32bit = 1, | 724 | .dmaor_is_32bit = 1, |
724 | .needs_tend_set = 1, | 725 | .needs_tend_set = 1, |
725 | .no_dmars = 1, | 726 | .no_dmars = 1, |
727 | .slave_only = 1, | ||
726 | }; | 728 | }; |
727 | 729 | ||
728 | static struct resource sh7372_usb_dmae1_resources[] = { | 730 | static struct resource sh7372_usb_dmae1_resources[] = { |
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index cc97ef892d1b..4fe2e9eaf501 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c | |||
@@ -25,6 +25,7 @@ | |||
25 | #include <linux/delay.h> | 25 | #include <linux/delay.h> |
26 | #include <mach/common.h> | 26 | #include <mach/common.h> |
27 | #include <mach/r8a7779.h> | 27 | #include <mach/r8a7779.h> |
28 | #include <asm/smp_plat.h> | ||
28 | #include <asm/smp_scu.h> | 29 | #include <asm/smp_scu.h> |
29 | #include <asm/smp_twd.h> | 30 | #include <asm/smp_twd.h> |
30 | #include <asm/hardware/gic.h> | 31 | #include <asm/hardware/gic.h> |
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index be1ade76ccc8..2d0d4212be41 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c | |||
@@ -23,6 +23,7 @@ | |||
23 | #include <linux/spinlock.h> | 23 | #include <linux/spinlock.h> |
24 | #include <linux/io.h> | 24 | #include <linux/io.h> |
25 | #include <mach/common.h> | 25 | #include <mach/common.h> |
26 | #include <asm/smp_plat.h> | ||
26 | #include <asm/smp_scu.h> | 27 | #include <asm/smp_scu.h> |
27 | #include <asm/smp_twd.h> | 28 | #include <asm/smp_twd.h> |
28 | #include <asm/hardware/gic.h> | 29 | #include <asm/hardware/gic.h> |
@@ -79,7 +80,7 @@ int __cpuinit sh73a0_boot_secondary(unsigned int cpu) | |||
79 | /* enable cache coherency */ | 80 | /* enable cache coherency */ |
80 | modify_scu_cpu_psr(0, 3 << (cpu * 8)); | 81 | modify_scu_cpu_psr(0, 3 << (cpu * 8)); |
81 | 82 | ||
82 | if (((__raw_readw(__io(PSTR)) >> (4 * cpu)) & 3) == 3) | 83 | if (((__raw_readl(__io(PSTR)) >> (4 * cpu)) & 3) == 3) |
83 | __raw_writel(1 << cpu, __io(WUPCR)); /* wake up */ | 84 | __raw_writel(1 << cpu, __io(WUPCR)); /* wake up */ |
84 | else | 85 | else |
85 | __raw_writel(1 << cpu, __io(SRESCR)); /* reset */ | 86 | __raw_writel(1 << cpu, __io(SRESCR)); /* reset */ |
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c index fcf4f377b1dc..330afdfa2475 100644 --- a/arch/arm/mach-tegra/board-paz00.c +++ b/arch/arm/mach-tegra/board-paz00.c | |||
@@ -60,9 +60,9 @@ static struct plat_serial8250_port debug_uart_platform_data[] = { | |||
60 | .uartclk = 216000000, | 60 | .uartclk = 216000000, |
61 | }, { | 61 | }, { |
62 | /* serial port on mini-pcie */ | 62 | /* serial port on mini-pcie */ |
63 | .membase = IO_ADDRESS(TEGRA_UARTD_BASE), | 63 | .membase = IO_ADDRESS(TEGRA_UARTC_BASE), |
64 | .mapbase = TEGRA_UARTD_BASE, | 64 | .mapbase = TEGRA_UARTC_BASE, |
65 | .irq = INT_UARTD, | 65 | .irq = INT_UARTC, |
66 | .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, | 66 | .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, |
67 | .type = PORT_TEGRA, | 67 | .type = PORT_TEGRA, |
68 | .iotype = UPIO_MEM, | 68 | .iotype = UPIO_MEM, |
@@ -174,7 +174,7 @@ static void __init tegra_paz00_fixup(struct tag *tags, char **cmdline, | |||
174 | static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = { | 174 | static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = { |
175 | /* name parent rate enabled */ | 175 | /* name parent rate enabled */ |
176 | { "uarta", "pll_p", 216000000, true }, | 176 | { "uarta", "pll_p", 216000000, true }, |
177 | { "uartd", "pll_p", 216000000, true }, | 177 | { "uartc", "pll_p", 216000000, true }, |
178 | 178 | ||
179 | { "pll_p_out4", "pll_p", 24000000, true }, | 179 | { "pll_p_out4", "pll_p", 24000000, true }, |
180 | { "usbd", "clk_m", 12000000, false }, | 180 | { "usbd", "clk_m", 12000000, false }, |
diff --git a/arch/arm/mach-tegra/board-paz00.h b/arch/arm/mach-tegra/board-paz00.h index ffa83f580db6..3c9f8da37ea3 100644 --- a/arch/arm/mach-tegra/board-paz00.h +++ b/arch/arm/mach-tegra/board-paz00.h | |||
@@ -22,7 +22,7 @@ | |||
22 | /* SDCARD */ | 22 | /* SDCARD */ |
23 | #define TEGRA_GPIO_SD1_CD TEGRA_GPIO_PV5 | 23 | #define TEGRA_GPIO_SD1_CD TEGRA_GPIO_PV5 |
24 | #define TEGRA_GPIO_SD1_WP TEGRA_GPIO_PH1 | 24 | #define TEGRA_GPIO_SD1_WP TEGRA_GPIO_PH1 |
25 | #define TEGRA_GPIO_SD1_POWER TEGRA_GPIO_PT3 | 25 | #define TEGRA_GPIO_SD1_POWER TEGRA_GPIO_PV1 |
26 | 26 | ||
27 | /* ULPI */ | 27 | /* ULPI */ |
28 | #define TEGRA_ULPI_RST TEGRA_GPIO_PV0 | 28 | #define TEGRA_ULPI_RST TEGRA_GPIO_PV0 |
diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h index d0132e8031a1..3c9339058bec 100644 --- a/arch/arm/mach-tegra/include/mach/dma.h +++ b/arch/arm/mach-tegra/include/mach/dma.h | |||
@@ -23,11 +23,6 @@ | |||
23 | 23 | ||
24 | #include <linux/list.h> | 24 | #include <linux/list.h> |
25 | 25 | ||
26 | #if defined(CONFIG_TEGRA_SYSTEM_DMA) | ||
27 | |||
28 | struct tegra_dma_req; | ||
29 | struct tegra_dma_channel; | ||
30 | |||
31 | #define TEGRA_DMA_REQ_SEL_CNTR 0 | 26 | #define TEGRA_DMA_REQ_SEL_CNTR 0 |
32 | #define TEGRA_DMA_REQ_SEL_I2S_2 1 | 27 | #define TEGRA_DMA_REQ_SEL_I2S_2 1 |
33 | #define TEGRA_DMA_REQ_SEL_I2S_1 2 | 28 | #define TEGRA_DMA_REQ_SEL_I2S_1 2 |
@@ -56,6 +51,11 @@ struct tegra_dma_channel; | |||
56 | #define TEGRA_DMA_REQ_SEL_OWR 25 | 51 | #define TEGRA_DMA_REQ_SEL_OWR 25 |
57 | #define TEGRA_DMA_REQ_SEL_INVALID 31 | 52 | #define TEGRA_DMA_REQ_SEL_INVALID 31 |
58 | 53 | ||
54 | #if defined(CONFIG_TEGRA_SYSTEM_DMA) | ||
55 | |||
56 | struct tegra_dma_req; | ||
57 | struct tegra_dma_channel; | ||
58 | |||
59 | enum tegra_dma_mode { | 59 | enum tegra_dma_mode { |
60 | TEGRA_DMA_SHARED = 1, | 60 | TEGRA_DMA_SHARED = 1, |
61 | TEGRA_DMA_MODE_CONTINOUS = 2, | 61 | TEGRA_DMA_MODE_CONTINOUS = 2, |
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index a3e0c8692f0d..52af00446a63 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig | |||
@@ -7,6 +7,7 @@ config UX500_SOC_COMMON | |||
7 | select HAS_MTU | 7 | select HAS_MTU |
8 | select ARM_ERRATA_753970 | 8 | select ARM_ERRATA_753970 |
9 | select ARM_ERRATA_754322 | 9 | select ARM_ERRATA_754322 |
10 | select ARM_ERRATA_764369 | ||
10 | 11 | ||
11 | menu "Ux500 SoC" | 12 | menu "Ux500 SoC" |
12 | 13 | ||
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c index 23be34b3bb6e..5dde4d4ebe88 100644 --- a/arch/arm/mach-ux500/board-mop500-sdi.c +++ b/arch/arm/mach-ux500/board-mop500-sdi.c | |||
@@ -261,6 +261,8 @@ void __init mop500_sdi_init(void) | |||
261 | 261 | ||
262 | void __init snowball_sdi_init(void) | 262 | void __init snowball_sdi_init(void) |
263 | { | 263 | { |
264 | /* On Snowball MMC_CAP_SD_HIGHSPEED isn't supported (Hardware issue?) */ | ||
265 | mop500_sdi0_data.capabilities &= ~MMC_CAP_SD_HIGHSPEED; | ||
264 | /* On-board eMMC */ | 266 | /* On-board eMMC */ |
265 | db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID); | 267 | db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID); |
266 | /* External Micro SD slot */ | 268 | /* External Micro SD slot */ |
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c index 122ddde00ba7..da5569d83d58 100644 --- a/arch/arm/mach-ux500/cache-l2x0.c +++ b/arch/arm/mach-ux500/cache-l2x0.c | |||
@@ -12,44 +12,6 @@ | |||
12 | 12 | ||
13 | static void __iomem *l2x0_base; | 13 | static void __iomem *l2x0_base; |
14 | 14 | ||
15 | static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask) | ||
16 | { | ||
17 | /* wait for the operation to complete */ | ||
18 | while (readl_relaxed(reg) & mask) | ||
19 | cpu_relax(); | ||
20 | } | ||
21 | |||
22 | static inline void ux500_cache_sync(void) | ||
23 | { | ||
24 | writel_relaxed(0, l2x0_base + L2X0_CACHE_SYNC); | ||
25 | ux500_cache_wait(l2x0_base + L2X0_CACHE_SYNC, 1); | ||
26 | } | ||
27 | |||
28 | /* | ||
29 | * The L2 cache cannot be turned off in the non-secure world. | ||
30 | * Dummy until a secure service is in place. | ||
31 | */ | ||
32 | static void ux500_l2x0_disable(void) | ||
33 | { | ||
34 | } | ||
35 | |||
36 | /* | ||
37 | * This is only called when doing a kexec, just after turning off the L2 | ||
38 | * and L1 cache, and it is surrounded by a spinlock in the generic version. | ||
39 | * However, we're not really turning off the L2 cache right now and the | ||
40 | * PL310 does not support exclusive accesses (used to implement the spinlock). | ||
41 | * So, the invalidation needs to be done without the spinlock. | ||
42 | */ | ||
43 | static void ux500_l2x0_inv_all(void) | ||
44 | { | ||
45 | uint32_t l2x0_way_mask = (1<<16) - 1; /* Bitmask of active ways */ | ||
46 | |||
47 | /* invalidate all ways */ | ||
48 | writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY); | ||
49 | ux500_cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask); | ||
50 | ux500_cache_sync(); | ||
51 | } | ||
52 | |||
53 | static int __init ux500_l2x0_unlock(void) | 15 | static int __init ux500_l2x0_unlock(void) |
54 | { | 16 | { |
55 | int i; | 17 | int i; |
@@ -85,9 +47,13 @@ static int __init ux500_l2x0_init(void) | |||
85 | /* 64KB way size, 8 way associativity, force WA */ | 47 | /* 64KB way size, 8 way associativity, force WA */ |
86 | l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff); | 48 | l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff); |
87 | 49 | ||
88 | /* Override invalidate function */ | 50 | /* |
89 | outer_cache.disable = ux500_l2x0_disable; | 51 | * We can't disable l2 as we are in non secure mode, currently |
90 | outer_cache.inv_all = ux500_l2x0_inv_all; | 52 | * this seems be called only during kexec path. So let's |
53 | * override outer.disable with nasty assignment until we have | ||
54 | * some SMI service available. | ||
55 | */ | ||
56 | outer_cache.disable = NULL; | ||
91 | 57 | ||
92 | return 0; | 58 | return 0; |
93 | } | 59 | } |
diff --git a/arch/arm/mach-ux500/hotplug.c b/arch/arm/mach-ux500/hotplug.c index 572015e57cd9..c76f0f456f04 100644 --- a/arch/arm/mach-ux500/hotplug.c +++ b/arch/arm/mach-ux500/hotplug.c | |||
@@ -13,6 +13,7 @@ | |||
13 | #include <linux/smp.h> | 13 | #include <linux/smp.h> |
14 | 14 | ||
15 | #include <asm/cacheflush.h> | 15 | #include <asm/cacheflush.h> |
16 | #include <asm/smp_plat.h> | ||
16 | 17 | ||
17 | extern volatile int pen_release; | 18 | extern volatile int pen_release; |
18 | 19 | ||
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c index a19e398dade3..d2058ef8345f 100644 --- a/arch/arm/mach-ux500/platsmp.c +++ b/arch/arm/mach-ux500/platsmp.c | |||
@@ -19,6 +19,7 @@ | |||
19 | 19 | ||
20 | #include <asm/cacheflush.h> | 20 | #include <asm/cacheflush.h> |
21 | #include <asm/hardware/gic.h> | 21 | #include <asm/hardware/gic.h> |
22 | #include <asm/smp_plat.h> | ||
22 | #include <asm/smp_scu.h> | 23 | #include <asm/smp_scu.h> |
23 | #include <mach/hardware.h> | 24 | #include <mach/hardware.h> |
24 | #include <mach/setup.h> | 25 | #include <mach/setup.h> |
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c index 0a01cbdfe063..9f9e1c203061 100644 --- a/arch/arm/mach-ux500/usb.c +++ b/arch/arm/mach-ux500/usb.c | |||
@@ -95,13 +95,7 @@ static struct musb_hdrc_config musb_hdrc_config = { | |||
95 | }; | 95 | }; |
96 | 96 | ||
97 | static struct musb_hdrc_platform_data musb_platform_data = { | 97 | static struct musb_hdrc_platform_data musb_platform_data = { |
98 | #if defined(CONFIG_USB_MUSB_OTG) | ||
99 | .mode = MUSB_OTG, | 98 | .mode = MUSB_OTG, |
100 | #elif defined(CONFIG_USB_MUSB_PERIPHERAL) | ||
101 | .mode = MUSB_PERIPHERAL, | ||
102 | #else /* defined(CONFIG_USB_MUSB_HOST) */ | ||
103 | .mode = MUSB_HOST, | ||
104 | #endif | ||
105 | .config = &musb_hdrc_config, | 99 | .config = &musb_hdrc_config, |
106 | .board_data = &musb_board_data, | 100 | .board_data = &musb_board_data, |
107 | }; | 101 | }; |
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c index 2b1e836a76ed..b1e87c184e54 100644 --- a/arch/arm/mach-vexpress/ct-ca9x4.c +++ b/arch/arm/mach-vexpress/ct-ca9x4.c | |||
@@ -217,7 +217,7 @@ static void __init ct_ca9x4_init(void) | |||
217 | } | 217 | } |
218 | 218 | ||
219 | #ifdef CONFIG_SMP | 219 | #ifdef CONFIG_SMP |
220 | static void ct_ca9x4_init_cpu_map(void) | 220 | static void __init ct_ca9x4_init_cpu_map(void) |
221 | { | 221 | { |
222 | int i, ncores = scu_get_core_count(MMIO_P2V(A9_MPCORE_SCU)); | 222 | int i, ncores = scu_get_core_count(MMIO_P2V(A9_MPCORE_SCU)); |
223 | 223 | ||
@@ -233,7 +233,7 @@ static void ct_ca9x4_init_cpu_map(void) | |||
233 | set_smp_cross_call(gic_raise_softirq); | 233 | set_smp_cross_call(gic_raise_softirq); |
234 | } | 234 | } |
235 | 235 | ||
236 | static void ct_ca9x4_smp_enable(unsigned int max_cpus) | 236 | static void __init ct_ca9x4_smp_enable(unsigned int max_cpus) |
237 | { | 237 | { |
238 | scu_enable(MMIO_P2V(A9_MPCORE_SCU)); | 238 | scu_enable(MMIO_P2V(A9_MPCORE_SCU)); |
239 | } | 239 | } |
diff --git a/arch/arm/mach-vexpress/hotplug.c b/arch/arm/mach-vexpress/hotplug.c index 813ee08f96e6..3034a4dab4a1 100644 --- a/arch/arm/mach-vexpress/hotplug.c +++ b/arch/arm/mach-vexpress/hotplug.c | |||
@@ -13,6 +13,7 @@ | |||
13 | #include <linux/smp.h> | 13 | #include <linux/smp.h> |
14 | 14 | ||
15 | #include <asm/cacheflush.h> | 15 | #include <asm/cacheflush.h> |
16 | #include <asm/smp_plat.h> | ||
16 | #include <asm/system.h> | 17 | #include <asm/system.h> |
17 | 18 | ||
18 | extern volatile int pen_release; | 19 | extern volatile int pen_release; |
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 4cefb57d9ed2..7edef9121632 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig | |||
@@ -631,7 +631,8 @@ comment "Processor Features" | |||
631 | 631 | ||
632 | config ARM_LPAE | 632 | config ARM_LPAE |
633 | bool "Support for the Large Physical Address Extension" | 633 | bool "Support for the Large Physical Address Extension" |
634 | depends on MMU && CPU_V7 | 634 | depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \ |
635 | !CPU_32v4 && !CPU_32v3 | ||
635 | help | 636 | help |
636 | Say Y if you have an ARMv7 processor supporting the LPAE page | 637 | Say Y if you have an ARMv7 processor supporting the LPAE page |
637 | table format and you would like to access memory beyond the | 638 | table format and you would like to access memory beyond the |
@@ -882,6 +883,7 @@ config CACHE_XSC3L2 | |||
882 | 883 | ||
883 | config ARM_L1_CACHE_SHIFT_6 | 884 | config ARM_L1_CACHE_SHIFT_6 |
884 | bool | 885 | bool |
886 | default y if CPU_V7 | ||
885 | help | 887 | help |
886 | Setting ARM L1 cache line size to 64 Bytes. | 888 | Setting ARM L1 cache line size to 64 Bytes. |
887 | 889 | ||
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 07c4bc8ea0a4..a655d3da386d 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S | |||
@@ -54,9 +54,15 @@ loop1: | |||
54 | and r1, r1, #7 @ mask of the bits for current cache only | 54 | and r1, r1, #7 @ mask of the bits for current cache only |
55 | cmp r1, #2 @ see what cache we have at this level | 55 | cmp r1, #2 @ see what cache we have at this level |
56 | blt skip @ skip if no cache, or just i-cache | 56 | blt skip @ skip if no cache, or just i-cache |
57 | #ifdef CONFIG_PREEMPT | ||
58 | save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic | ||
59 | #endif | ||
57 | mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr | 60 | mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr |
58 | isb @ isb to sych the new cssr&csidr | 61 | isb @ isb to sych the new cssr&csidr |
59 | mrc p15, 1, r1, c0, c0, 0 @ read the new csidr | 62 | mrc p15, 1, r1, c0, c0, 0 @ read the new csidr |
63 | #ifdef CONFIG_PREEMPT | ||
64 | restore_irqs_notrace r9 | ||
65 | #endif | ||
60 | and r2, r1, #7 @ extract the length of the cache lines | 66 | and r2, r1, #7 @ extract the length of the cache lines |
61 | add r2, r2, #4 @ add 4 (line length offset) | 67 | add r2, r2, #4 @ add 4 (line length offset) |
62 | ldr r4, =0x3ff | 68 | ldr r4, =0x3ff |
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 6ec1226fc62d..5dc7d127a40f 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c | |||
@@ -310,7 +310,7 @@ static void arm_memory_present(void) | |||
310 | 310 | ||
311 | static bool arm_memblock_steal_permitted = true; | 311 | static bool arm_memblock_steal_permitted = true; |
312 | 312 | ||
313 | phys_addr_t arm_memblock_steal(phys_addr_t size, phys_addr_t align) | 313 | phys_addr_t __init arm_memblock_steal(phys_addr_t size, phys_addr_t align) |
314 | { | 314 | { |
315 | phys_addr_t phys; | 315 | phys_addr_t phys; |
316 | 316 | ||
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 7e9b5bf910c1..0404ccbb8aa3 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S | |||
@@ -148,10 +148,6 @@ ENDPROC(cpu_v7_do_resume) | |||
148 | * Initialise TLB, Caches, and MMU state ready to switch the MMU | 148 | * Initialise TLB, Caches, and MMU state ready to switch the MMU |
149 | * on. Return in r0 the new CP15 C1 control register setting. | 149 | * on. Return in r0 the new CP15 C1 control register setting. |
150 | * | 150 | * |
151 | * We automatically detect if we have a Harvard cache, and use the | ||
152 | * Harvard cache control instructions insead of the unified cache | ||
153 | * control instructions. | ||
154 | * | ||
155 | * This should be able to cover all ARMv7 cores. | 151 | * This should be able to cover all ARMv7 cores. |
156 | * | 152 | * |
157 | * It is assumed that: | 153 | * It is assumed that: |
@@ -251,9 +247,7 @@ __v7_setup: | |||
251 | #endif | 247 | #endif |
252 | 248 | ||
253 | 3: mov r10, #0 | 249 | 3: mov r10, #0 |
254 | #ifdef HARVARD_CACHE | ||
255 | mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate | 250 | mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate |
256 | #endif | ||
257 | dsb | 251 | dsb |
258 | #ifdef CONFIG_MMU | 252 | #ifdef CONFIG_MMU |
259 | mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs | 253 | mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs |
@@ -330,16 +324,6 @@ __v7_ca5mp_proc_info: | |||
330 | .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info | 324 | .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info |
331 | 325 | ||
332 | /* | 326 | /* |
333 | * ARM Ltd. Cortex A7 processor. | ||
334 | */ | ||
335 | .type __v7_ca7mp_proc_info, #object | ||
336 | __v7_ca7mp_proc_info: | ||
337 | .long 0x410fc070 | ||
338 | .long 0xff0ffff0 | ||
339 | __v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV | ||
340 | .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info | ||
341 | |||
342 | /* | ||
343 | * ARM Ltd. Cortex A9 processor. | 327 | * ARM Ltd. Cortex A9 processor. |
344 | */ | 328 | */ |
345 | .type __v7_ca9mp_proc_info, #object | 329 | .type __v7_ca9mp_proc_info, #object |
@@ -351,6 +335,16 @@ __v7_ca9mp_proc_info: | |||
351 | #endif /* CONFIG_ARM_LPAE */ | 335 | #endif /* CONFIG_ARM_LPAE */ |
352 | 336 | ||
353 | /* | 337 | /* |
338 | * ARM Ltd. Cortex A7 processor. | ||
339 | */ | ||
340 | .type __v7_ca7mp_proc_info, #object | ||
341 | __v7_ca7mp_proc_info: | ||
342 | .long 0x410fc070 | ||
343 | .long 0xff0ffff0 | ||
344 | __v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV | ||
345 | .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info | ||
346 | |||
347 | /* | ||
354 | * ARM Ltd. Cortex A15 processor. | 348 | * ARM Ltd. Cortex A15 processor. |
355 | */ | 349 | */ |
356 | .type __v7_ca15mp_proc_info, #object | 350 | .type __v7_ca15mp_proc_info, #object |
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index b30708e28c1d..dcebb1230f7f 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig | |||
@@ -17,26 +17,17 @@ config ARCH_IMX_V4_V5 | |||
17 | and ARMv5 SoCs | 17 | and ARMv5 SoCs |
18 | 18 | ||
19 | config ARCH_IMX_V6_V7 | 19 | config ARCH_IMX_V6_V7 |
20 | bool "i.MX3, i.MX6" | 20 | bool "i.MX3, i.MX5, i.MX6" |
21 | select AUTO_ZRELADDR if !ZBOOT_ROM | 21 | select AUTO_ZRELADDR if !ZBOOT_ROM |
22 | select ARM_PATCH_PHYS_VIRT | 22 | select ARM_PATCH_PHYS_VIRT |
23 | select MIGHT_HAVE_CACHE_L2X0 | 23 | select MIGHT_HAVE_CACHE_L2X0 |
24 | help | 24 | help |
25 | This enables support for systems based on the Freescale i.MX3 and i.MX6 | 25 | This enables support for systems based on the Freescale i.MX3, i.MX5 |
26 | family. | 26 | and i.MX6 family. |
27 | |||
28 | config ARCH_MX5 | ||
29 | bool "i.MX50, i.MX51, i.MX53" | ||
30 | select AUTO_ZRELADDR if !ZBOOT_ROM | ||
31 | select ARM_PATCH_PHYS_VIRT | ||
32 | help | ||
33 | This enables support for machines using Freescale's i.MX50 and i.MX53 | ||
34 | processors. | ||
35 | 27 | ||
36 | endchoice | 28 | endchoice |
37 | 29 | ||
38 | source "arch/arm/mach-imx/Kconfig" | 30 | source "arch/arm/mach-imx/Kconfig" |
39 | source "arch/arm/mach-mx5/Kconfig" | ||
40 | 31 | ||
41 | endmenu | 32 | endmenu |
42 | 33 | ||
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v1.h b/arch/arm/plat-mxc/include/mach/iomux-v1.h index 6fa8a707b9a0..f7d18046c04f 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v1.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v1.h | |||
@@ -96,6 +96,6 @@ extern int mxc_gpio_mode(int gpio_mode); | |||
96 | extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, | 96 | extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, |
97 | const char *label); | 97 | const char *label); |
98 | 98 | ||
99 | extern int __init imx_iomuxv1_init(void __iomem *base, int numports); | 99 | extern int imx_iomuxv1_init(void __iomem *base, int numports); |
100 | 100 | ||
101 | #endif /* __MACH_IOMUX_V1_H__ */ | 101 | #endif /* __MACH_IOMUX_V1_H__ */ |
diff --git a/arch/arm/plat-omap/include/plat/omap-secure.h b/arch/arm/plat-omap/include/plat/omap-secure.h index 64f9d1c7f1bb..3047ff923a63 100644 --- a/arch/arm/plat-omap/include/plat/omap-secure.h +++ b/arch/arm/plat-omap/include/plat/omap-secure.h | |||
@@ -3,7 +3,7 @@ | |||
3 | 3 | ||
4 | #include <linux/types.h> | 4 | #include <linux/types.h> |
5 | 5 | ||
6 | #ifdef CONFIG_ARCH_OMAP2PLUS | 6 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
7 | extern int omap_secure_ram_reserve_memblock(void); | 7 | extern int omap_secure_ram_reserve_memblock(void); |
8 | #else | 8 | #else |
9 | static inline void omap_secure_ram_reserve_memblock(void) | 9 | static inline void omap_secure_ram_reserve_memblock(void) |
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index e5a2fde29b19..089899a7db72 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c | |||
@@ -789,10 +789,7 @@ void __init orion_xor1_init(unsigned long mapbase_low, | |||
789 | /***************************************************************************** | 789 | /***************************************************************************** |
790 | * EHCI | 790 | * EHCI |
791 | ****************************************************************************/ | 791 | ****************************************************************************/ |
792 | static struct orion_ehci_data orion_ehci_data = { | 792 | static struct orion_ehci_data orion_ehci_data; |
793 | .phy_version = EHCI_PHY_NA, | ||
794 | }; | ||
795 | |||
796 | static u64 ehci_dmamask = DMA_BIT_MASK(32); | 793 | static u64 ehci_dmamask = DMA_BIT_MASK(32); |
797 | 794 | ||
798 | 795 | ||
@@ -812,8 +809,10 @@ static struct platform_device orion_ehci = { | |||
812 | }; | 809 | }; |
813 | 810 | ||
814 | void __init orion_ehci_init(unsigned long mapbase, | 811 | void __init orion_ehci_init(unsigned long mapbase, |
815 | unsigned long irq) | 812 | unsigned long irq, |
813 | enum orion_ehci_phy_ver phy_version) | ||
816 | { | 814 | { |
815 | orion_ehci_data.phy_version = phy_version; | ||
817 | fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1, | 816 | fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1, |
818 | irq); | 817 | irq); |
819 | 818 | ||
diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index 0fe08d77e835..a7fa005a5a0e 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h | |||
@@ -89,7 +89,8 @@ void __init orion_xor1_init(unsigned long mapbase_low, | |||
89 | unsigned long irq_1); | 89 | unsigned long irq_1); |
90 | 90 | ||
91 | void __init orion_ehci_init(unsigned long mapbase, | 91 | void __init orion_ehci_init(unsigned long mapbase, |
92 | unsigned long irq); | 92 | unsigned long irq, |
93 | enum orion_ehci_phy_ver phy_version); | ||
93 | 94 | ||
94 | void __init orion_ehci_1_init(unsigned long mapbase, | 95 | void __init orion_ehci_1_init(unsigned long mapbase, |
95 | unsigned long irq); | 96 | unsigned long irq); |
diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c index 91553432711d..3b1e17bd3d17 100644 --- a/arch/arm/plat-orion/mpp.c +++ b/arch/arm/plat-orion/mpp.c | |||
@@ -64,8 +64,7 @@ void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask, | |||
64 | gpio_mode |= GPIO_INPUT_OK; | 64 | gpio_mode |= GPIO_INPUT_OK; |
65 | if (*mpp_list & MPP_OUTPUT_MASK) | 65 | if (*mpp_list & MPP_OUTPUT_MASK) |
66 | gpio_mode |= GPIO_OUTPUT_OK; | 66 | gpio_mode |= GPIO_OUTPUT_OK; |
67 | if (sel != 0) | 67 | |
68 | gpio_mode = 0; | ||
69 | orion_gpio_set_valid(num, gpio_mode); | 68 | orion_gpio_set_valid(num, gpio_mode); |
70 | } | 69 | } |
71 | 70 | ||
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index 32a6e394db24..f10768e988d4 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c | |||
@@ -468,8 +468,10 @@ void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd) | |||
468 | { | 468 | { |
469 | struct s3c2410_platform_i2c *npd; | 469 | struct s3c2410_platform_i2c *npd; |
470 | 470 | ||
471 | if (!pd) | 471 | if (!pd) { |
472 | pd = &default_i2c_data; | 472 | pd = &default_i2c_data; |
473 | pd->bus_num = 0; | ||
474 | } | ||
473 | 475 | ||
474 | npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), | 476 | npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), |
475 | &s3c_device_i2c0); | 477 | &s3c_device_i2c0); |
diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c index 92f18d372b69..49c7db48c7f1 100644 --- a/arch/arm/plat-versatile/platsmp.c +++ b/arch/arm/plat-versatile/platsmp.c | |||
@@ -16,6 +16,7 @@ | |||
16 | #include <linux/smp.h> | 16 | #include <linux/smp.h> |
17 | 17 | ||
18 | #include <asm/cacheflush.h> | 18 | #include <asm/cacheflush.h> |
19 | #include <asm/smp_plat.h> | ||
19 | #include <asm/hardware/gic.h> | 20 | #include <asm/hardware/gic.h> |
20 | 21 | ||
21 | /* | 22 | /* |