diff options
| author | Timothy Baldwin <T.E.Baldwin99@members.leeds.ac.uk> | 2005-09-04 05:13:48 -0400 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2005-09-04 05:13:48 -0400 |
| commit | ca6ca91d8c7498d45e0d35800503699164366f10 (patch) | |
| tree | 3e340cd984e08f4f1edd7c8f33c4e45cf6ace743 /arch/arm | |
| parent | 9bed07d0fed01f7c39d128e59e5d35d7d67ff439 (diff) | |
[ARM] 2875/1: Data Abort fixes
Patch from Timothy Baldwin
All data aborts are treated as read accesses. The existing code updates the wrong bit of r1, also the comments are wrong in that the sense of the L bit is inverted.
Signed-off-by: Timothy E. Baldwin <T.E.Baldwin99@members.leeds.ac.uk>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mm/proc-arm6_7.S | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S index 0ee214b824ff..189ef6a71ba1 100644 --- a/arch/arm/mm/proc-arm6_7.S +++ b/arch/arm/mm/proc-arm6_7.S | |||
| @@ -38,8 +38,8 @@ ENTRY(cpu_arm7_data_abort) | |||
| 38 | mrc p15, 0, r1, c5, c0, 0 @ get FSR | 38 | mrc p15, 0, r1, c5, c0, 0 @ get FSR |
| 39 | mrc p15, 0, r0, c6, c0, 0 @ get FAR | 39 | mrc p15, 0, r0, c6, c0, 0 @ get FAR |
| 40 | ldr r8, [r0] @ read arm instruction | 40 | ldr r8, [r0] @ read arm instruction |
| 41 | tst r8, #1 << 20 @ L = 1 -> write? | 41 | tst r8, #1 << 20 @ L = 0 -> write? |
| 42 | orreq r1, r1, #1 << 8 @ yes. | 42 | orreq r1, r1, #1 << 11 @ yes. |
| 43 | and r7, r8, #15 << 24 | 43 | and r7, r8, #15 << 24 |
| 44 | add pc, pc, r7, lsr #22 @ Now branch to the relevant processing routine | 44 | add pc, pc, r7, lsr #22 @ Now branch to the relevant processing routine |
| 45 | nop | 45 | nop |
| @@ -71,8 +71,8 @@ ENTRY(cpu_arm6_data_abort) | |||
| 71 | mrc p15, 0, r1, c5, c0, 0 @ get FSR | 71 | mrc p15, 0, r1, c5, c0, 0 @ get FSR |
| 72 | mrc p15, 0, r0, c6, c0, 0 @ get FAR | 72 | mrc p15, 0, r0, c6, c0, 0 @ get FAR |
| 73 | ldr r8, [r2] @ read arm instruction | 73 | ldr r8, [r2] @ read arm instruction |
| 74 | tst r8, #1 << 20 @ L = 1 -> write? | 74 | tst r8, #1 << 20 @ L = 0 -> write? |
| 75 | orreq r1, r1, #1 << 8 @ yes. | 75 | orreq r1, r1, #1 << 11 @ yes. |
| 76 | and r7, r8, #14 << 24 | 76 | and r7, r8, #14 << 24 |
| 77 | teq r7, #8 << 24 @ was it ldm/stm | 77 | teq r7, #8 << 24 @ was it ldm/stm |
| 78 | movne pc, lr | 78 | movne pc, lr |