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authorArnd Bergmann <arnd@arndb.de>2013-01-25 17:44:17 -0500
committerNicolas Ferre <nicolas.ferre@atmel.com>2013-04-18 10:31:02 -0400
commitf5fa4098c3fcc0e504fbc0682dccd331dbbcf197 (patch)
treef409c2b7fea4d220a6e0682f09c1133f208fe97b /arch/arm
parent13ab6aeb49663b0ca0f0eed3560fbaecacf4858f (diff)
ARM: at91: suspend both memory controllers on at91sam9263
For the past three years, we have had a #warning in mach-at91 about the sdram_selfrefresh_enable or at91sam9_standby functions possibly not working on at91sam9263. In the meantime a function was added to do the right thing on at91sam9g45, which looks like it should also work on '9263. Signed-off-by: Arnd Bergmann <arnd@arndb.de> [nicolas.ferre@atmel.com: remove paragraph in commit message] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-at91/cpuidle.c2
-rw-r--r--arch/arm/mach-at91/pm.c2
-rw-r--r--arch/arm/mach-at91/pm.h30
3 files changed, 28 insertions, 6 deletions
diff --git a/arch/arm/mach-at91/cpuidle.c b/arch/arm/mach-at91/cpuidle.c
index 0c6381516a5a..4c6794603780 100644
--- a/arch/arm/mach-at91/cpuidle.c
+++ b/arch/arm/mach-at91/cpuidle.c
@@ -38,6 +38,8 @@ static int at91_enter_idle(struct cpuidle_device *dev,
38 at91rm9200_standby(); 38 at91rm9200_standby();
39 else if (cpu_is_at91sam9g45()) 39 else if (cpu_is_at91sam9g45())
40 at91sam9g45_standby(); 40 at91sam9g45_standby();
41 else if (cpu_is_at91sam9263())
42 at91sam9263_standby();
41 else 43 else
42 at91sam9_standby(); 44 at91sam9_standby();
43 45
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index adb6db888a1f..b8017c1a864d 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -267,6 +267,8 @@ static int at91_pm_enter(suspend_state_t state)
267 at91rm9200_standby(); 267 at91rm9200_standby();
268 else if (cpu_is_at91sam9g45()) 268 else if (cpu_is_at91sam9g45())
269 at91sam9g45_standby(); 269 at91sam9g45_standby();
270 else if (cpu_is_at91sam9263())
271 at91sam9263_standby();
270 else 272 else
271 at91sam9_standby(); 273 at91sam9_standby();
272 break; 274 break;
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 38f467c6b710..2f5908f0b8c5 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -70,13 +70,31 @@ static inline void at91sam9g45_standby(void)
70 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); 70 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
71} 71}
72 72
73#ifdef CONFIG_SOC_AT91SAM9263 73/* We manage both DDRAM/SDRAM controllers, we need more than one value to
74/* 74 * remember.
75 * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
76 * handle those cases both here and in the Suspend-To-RAM support.
77 */ 75 */
78#warning Assuming EB1 SDRAM controller is *NOT* used 76static inline void at91sam9263_standby(void)
79#endif 77{
78 u32 lpr0, lpr1;
79 u32 saved_lpr0, saved_lpr1;
80
81 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
82 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
83 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
84
85 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
86 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
87 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
88
89 /* self-refresh mode now */
90 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
91 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
92
93 cpu_do_idle();
94
95 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
96 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
97}
80 98
81static inline void at91sam9_standby(void) 99static inline void at91sam9_standby(void)
82{ 100{