aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm
diff options
context:
space:
mode:
authorArnd Bergmann <arnd@arndb.de>2012-09-28 15:51:22 -0400
committerArnd Bergmann <arnd@arndb.de>2012-09-28 15:51:38 -0400
commitdf69a4627eb5de58ec71fdf6a7b5d0ce9410d57e (patch)
tree8f7587ab9a24a3c04afe842c3a7d51cb2c31a1cc /arch/arm
parente3a66aa33a8f06924f67770e15c22a5c52df314e (diff)
parent25e4b485fb8eeda8aa7a2e1e45fbb31538565117 (diff)
Merge branch 'bcmring/removal' into next/multiplatform
The removal of bcmring has non-obvious commits with the way the multiplatform configuration works, so merge it in here. Conflicts: arch/arm/Kconfig arch/arm/Makefile arch/arm/mach-bcmring/arch.c Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig14
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/configs/bcmring_defconfig79
-rw-r--r--arch/arm/mach-bcmring/Kconfig19
-rw-r--r--arch/arm/mach-bcmring/Makefile8
-rw-r--r--arch/arm/mach-bcmring/Makefile.boot6
-rw-r--r--arch/arm/mach-bcmring/arch.c198
-rw-r--r--arch/arm/mach-bcmring/clock.c223
-rw-r--r--arch/arm/mach-bcmring/clock.h33
-rw-r--r--arch/arm/mach-bcmring/core.c227
-rw-r--r--arch/arm/mach-bcmring/core.h31
-rw-r--r--arch/arm/mach-bcmring/csp/Makefile3
-rw-r--r--arch/arm/mach-bcmring/csp/chipc/Makefile1
-rw-r--r--arch/arm/mach-bcmring/csp/chipc/chipcHw.c779
-rw-r--r--arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c283
-rw-r--r--arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c125
-rw-r--r--arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c64
-rw-r--r--arch/arm/mach-bcmring/csp/dmac/Makefile1
-rw-r--r--arch/arm/mach-bcmring/csp/dmac/dmacHw.c916
-rw-r--r--arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c1017
-rw-r--r--arch/arm/mach-bcmring/csp/tmr/Makefile1
-rw-r--r--arch/arm/mach-bcmring/csp/tmr/tmrHw.c576
-rw-r--r--arch/arm/mach-bcmring/dma.c1518
-rw-r--r--arch/arm/mach-bcmring/dma_device.c593
-rw-r--r--arch/arm/mach-bcmring/include/mach/cfg_global.h51
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/cap.h63
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/cap_inline.h409
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h1123
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h1682
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h530
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h872
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/dmacHw.h596
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h145
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h406
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h73
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h246
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/mm_addr.h101
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/mm_io.h147
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/reg.h115
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/secHw_def.h100
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h79
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/tmrHw.h263
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h82
-rw-r--r--arch/arm/mach-bcmring/include/mach/dma.h630
-rw-r--r--arch/arm/mach-bcmring/include/mach/entry-macro.S76
-rw-r--r--arch/arm/mach-bcmring/include/mach/hardware.h57
-rw-r--r--arch/arm/mach-bcmring/include/mach/irqs.h132
-rw-r--r--arch/arm/mach-bcmring/include/mach/memory_settings.h67
-rw-r--r--arch/arm/mach-bcmring/include/mach/reg_nand.h66
-rw-r--r--arch/arm/mach-bcmring/include/mach/reg_umi.h237
-rw-r--r--arch/arm/mach-bcmring/include/mach/timer.h77
-rw-r--r--arch/arm/mach-bcmring/include/mach/timex.h25
-rw-r--r--arch/arm/mach-bcmring/include/mach/uncompress.h43
-rw-r--r--arch/arm/mach-bcmring/irq.c126
-rw-r--r--arch/arm/mach-bcmring/mm.c60
-rw-r--r--arch/arm/mach-bcmring/timer.c61
56 files changed, 0 insertions, 15456 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f416422ddb0e..f7673b4e56bc 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -345,18 +345,6 @@ config ARCH_BCM2835
345 This enables support for the Broadcom BCM2835 SoC. This SoC is 345 This enables support for the Broadcom BCM2835 SoC. This SoC is
346 use in the Raspberry Pi, and Roku 2 devices. 346 use in the Raspberry Pi, and Roku 2 devices.
347 347
348config ARCH_BCMRING
349 bool "Broadcom BCMRING"
350 depends on MMU
351 select CPU_V6
352 select ARM_AMBA
353 select ARM_TIMER_SP804
354 select CLKDEV_LOOKUP
355 select GENERIC_CLOCKEVENTS
356 select ARCH_WANT_OPTIONAL_GPIOLIB
357 help
358 Support for Broadcom's BCMRing platform.
359
360config ARCH_CLPS711X 348config ARCH_CLPS711X
361 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" 349 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
362 select CPU_ARM720T 350 select CPU_ARM720T
@@ -1020,8 +1008,6 @@ source "arch/arm/mach-mvebu/Kconfig"
1020 1008
1021source "arch/arm/mach-at91/Kconfig" 1009source "arch/arm/mach-at91/Kconfig"
1022 1010
1023source "arch/arm/mach-bcmring/Kconfig"
1024
1025source "arch/arm/mach-clps711x/Kconfig" 1011source "arch/arm/mach-clps711x/Kconfig"
1026 1012
1027source "arch/arm/mach-cns3xxx/Kconfig" 1013source "arch/arm/mach-cns3xxx/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 1c974cf9db1b..770da51242c4 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -137,7 +137,6 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
137# by CONFIG_* macro name. 137# by CONFIG_* macro name.
138machine-$(CONFIG_ARCH_AT91) += at91 138machine-$(CONFIG_ARCH_AT91) += at91
139machine-$(CONFIG_ARCH_BCM2835) += bcm2835 139machine-$(CONFIG_ARCH_BCM2835) += bcm2835
140machine-$(CONFIG_ARCH_BCMRING) += bcmring
141machine-$(CONFIG_ARCH_CLPS711X) += clps711x 140machine-$(CONFIG_ARCH_CLPS711X) += clps711x
142machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx 141machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx
143machine-$(CONFIG_ARCH_DAVINCI) += davinci 142machine-$(CONFIG_ARCH_DAVINCI) += davinci
diff --git a/arch/arm/configs/bcmring_defconfig b/arch/arm/configs/bcmring_defconfig
deleted file mode 100644
index 9e6a8fe13164..000000000000
--- a/arch/arm/configs/bcmring_defconfig
+++ /dev/null
@@ -1,79 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2# CONFIG_LOCALVERSION_AUTO is not set
3# CONFIG_SWAP is not set
4CONFIG_SYSVIPC=y
5CONFIG_EXPERT=y
6CONFIG_KALLSYMS_EXTRA_PASS=y
7# CONFIG_HOTPLUG is not set
8# CONFIG_ELF_CORE is not set
9# CONFIG_EPOLL is not set
10# CONFIG_SIGNALFD is not set
11# CONFIG_TIMERFD is not set
12# CONFIG_EVENTFD is not set
13# CONFIG_AIO is not set
14CONFIG_PERF_EVENTS=y
15# CONFIG_VM_EVENT_COUNTERS is not set
16# CONFIG_SLUB_DEBUG is not set
17# CONFIG_COMPAT_BRK is not set
18CONFIG_MODULES=y
19CONFIG_MODULE_UNLOAD=y
20# CONFIG_BLK_DEV_BSG is not set
21# CONFIG_IOSCHED_DEADLINE is not set
22# CONFIG_IOSCHED_CFQ is not set
23CONFIG_ARCH_BCMRING=y
24CONFIG_BCM_ZRELADDR=0x8000
25CONFIG_CPU_32v6K=y
26CONFIG_NO_HZ=y
27CONFIG_PREEMPT=y
28CONFIG_AEABI=y
29# CONFIG_OABI_COMPAT is not set
30CONFIG_UACCESS_WITH_MEMCPY=y
31CONFIG_ZBOOT_ROM_TEXT=0x0e000000
32CONFIG_ZBOOT_ROM_BSS=0x0ea00000
33CONFIG_ZBOOT_ROM=y
34CONFIG_NET=y
35# CONFIG_WIRELESS is not set
36CONFIG_MTD=y
37CONFIG_MTD_CONCAT=y
38CONFIG_MTD_PARTITIONS=y
39CONFIG_MTD_CMDLINE_PARTS=y
40CONFIG_MTD_CHAR=y
41CONFIG_MTD_BLOCK=y
42CONFIG_MTD_CFI=y
43CONFIG_MTD_CFI_ADV_OPTIONS=y
44CONFIG_MTD_CFI_GEOMETRY=y
45# CONFIG_MTD_CFI_I2 is not set
46CONFIG_MTD_NAND=y
47CONFIG_MTD_NAND_VERIFY_WRITE=y
48CONFIG_MTD_NAND_BCM_UMI=y
49CONFIG_MTD_NAND_BCM_UMI_HWCS=y
50# CONFIG_MISC_DEVICES is not set
51# CONFIG_INPUT_MOUSEDEV is not set
52# CONFIG_INPUT_KEYBOARD is not set
53# CONFIG_INPUT_MOUSE is not set
54# CONFIG_SERIO is not set
55# CONFIG_CONSOLE_TRANSLATIONS is not set
56# CONFIG_DEVKMEM is not set
57CONFIG_SERIAL_AMBA_PL011=y
58CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
59CONFIG_LEGACY_PTY_COUNT=64
60# CONFIG_HW_RANDOM is not set
61# CONFIG_HWMON is not set
62# CONFIG_VGA_CONSOLE is not set
63# CONFIG_HID_SUPPORT is not set
64# CONFIG_USB_SUPPORT is not set
65# CONFIG_FILE_LOCKING is not set
66# CONFIG_DNOTIFY is not set
67# CONFIG_INOTIFY_USER is not set
68# CONFIG_PROC_PAGE_MONITOR is not set
69CONFIG_TMPFS=y
70CONFIG_JFFS2_FS=y
71CONFIG_JFFS2_SUMMARY=y
72CONFIG_JFFS2_FS_XATTR=y
73# CONFIG_JFFS2_FS_SECURITY is not set
74# CONFIG_NETWORK_FILESYSTEMS is not set
75# CONFIG_ENABLE_WARN_DEPRECATED is not set
76CONFIG_MAGIC_SYSRQ=y
77CONFIG_HEADERS_CHECK=y
78# CONFIG_RCU_CPU_STALL_DETECTOR is not set
79# CONFIG_ARM_UNWIND is not set
diff --git a/arch/arm/mach-bcmring/Kconfig b/arch/arm/mach-bcmring/Kconfig
deleted file mode 100644
index 9170d16dca50..000000000000
--- a/arch/arm/mach-bcmring/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
1choice
2 prompt "Processor selection in BCMRING family of devices"
3 depends on ARCH_BCMRING
4 default ARCH_BCM11107
5
6config ARCH_FPGA11107
7 bool "FPGA11107"
8
9config ARCH_BCM11107
10 bool "BCM11107"
11endchoice
12
13menu "BCMRING Options"
14 depends on ARCH_BCMRING
15
16config BCM_ZRELADDR
17 hex "Compressed ZREL ADDR"
18
19endmenu
diff --git a/arch/arm/mach-bcmring/Makefile b/arch/arm/mach-bcmring/Makefile
deleted file mode 100644
index f8d9fcedf917..000000000000
--- a/arch/arm/mach-bcmring/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Object file lists.
6
7obj-y := arch.o mm.o irq.o clock.o core.o timer.o dma.o
8obj-y += csp/
diff --git a/arch/arm/mach-bcmring/Makefile.boot b/arch/arm/mach-bcmring/Makefile.boot
deleted file mode 100644
index aef2467757fa..000000000000
--- a/arch/arm/mach-bcmring/Makefile.boot
+++ /dev/null
@@ -1,6 +0,0 @@
1# Address where decompressor will be written and eventually executed.
2#
3# default to SDRAM
4zreladdr-y += $(CONFIG_BCM_ZRELADDR)
5params_phys-y := 0x00000800
6
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
deleted file mode 100644
index c18a5048b6c5..000000000000
--- a/arch/arm/mach-bcmring/arch.c
+++ /dev/null
@@ -1,198 +0,0 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#include <linux/kernel.h>
16#include <linux/platform_device.h>
17#include <linux/types.h>
18#include <linux/sched.h>
19#include <linux/interrupt.h>
20#include <linux/init.h>
21#include <linux/errno.h>
22#include <linux/spinlock.h>
23#include <linux/module.h>
24
25#include <linux/proc_fs.h>
26#include <linux/sysctl.h>
27
28#include <asm/irq.h>
29#include <asm/setup.h>
30#include <asm/mach-types.h>
31#include <asm/mach/time.h>
32
33#include <asm/mach/arch.h>
34#include <mach/dma.h>
35#include <mach/hardware.h>
36#include <mach/csp/mm_io.h>
37#include <mach/csp/chipcHw_def.h>
38#include <mach/csp/chipcHw_inline.h>
39
40#include <mach/cfg_global.h>
41
42#include "core.h"
43
44HW_DECLARE_SPINLOCK(arch)
45HW_DECLARE_SPINLOCK(gpio)
46#if defined(CONFIG_DEBUG_SPINLOCK)
47 EXPORT_SYMBOL(bcmring_gpio_reg_lock);
48#endif
49
50/* sysctl */
51static int bcmring_arch_warm_reboot; /* do a warm reboot on hard reset */
52
53static void bcmring_restart(char mode, const char *cmd)
54{
55 printk("arch_reset:%c %x\n", mode, bcmring_arch_warm_reboot);
56
57 if (mode == 'h') {
58 /* Reboot configured in proc entry */
59 if (bcmring_arch_warm_reboot) {
60 printk("warm reset\n");
61 /* Issue Warm reset (do not reset ethernet switch, keep alive) */
62 chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_WARM);
63 } else {
64 /* Force reset of everything */
65 printk("force reset\n");
66 chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
67 }
68 } else {
69 /* Force reset of everything */
70 printk("force reset\n");
71 chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
72 }
73}
74
75static struct ctl_table_header *bcmring_sysctl_header;
76
77static struct ctl_table bcmring_sysctl_warm_reboot[] = {
78 {
79 .procname = "warm",
80 .data = &bcmring_arch_warm_reboot,
81 .maxlen = sizeof(int),
82 .mode = 0644,
83 .proc_handler = proc_dointvec},
84 {}
85};
86
87static struct ctl_table bcmring_sysctl_reboot[] = {
88 {
89 .procname = "reboot",
90 .mode = 0555,
91 .child = bcmring_sysctl_warm_reboot},
92 {}
93};
94
95static struct resource nand_resource[] = {
96 [0] = {
97 .start = MM_ADDR_IO_NAND,
98 .end = MM_ADDR_IO_NAND + 0x1000 - 1,
99 .flags = IORESOURCE_MEM,
100 },
101};
102
103static struct platform_device nand_device = {
104 .name = "bcm-nand",
105 .id = -1,
106 .resource = nand_resource,
107 .num_resources = ARRAY_SIZE(nand_resource),
108};
109
110static struct resource pmu_resource = {
111 .start = IRQ_PMUIRQ,
112 .end = IRQ_PMUIRQ,
113 .flags = IORESOURCE_IRQ,
114};
115
116static struct platform_device pmu_device = {
117 .name = "arm-pmu",
118 .id = -1,
119 .resource = &pmu_resource,
120 .num_resources = 1,
121};
122
123
124static struct platform_device *devices[] __initdata = {
125 &nand_device,
126 &pmu_device,
127};
128
129/****************************************************************************
130*
131* Called from the customize_machine function in arch/arm/kernel/setup.c
132*
133* The customize_machine function is tagged as an arch_initcall
134* (see include/linux/init.h for the order that the various init sections
135* are called in.
136*
137*****************************************************************************/
138static void __init bcmring_init_machine(void)
139{
140
141 bcmring_sysctl_header = register_sysctl_table(bcmring_sysctl_reboot);
142
143 /* Enable spread spectrum */
144 chipcHw_enableSpreadSpectrum();
145
146 platform_add_devices(devices, ARRAY_SIZE(devices));
147
148 bcmring_amba_init();
149
150 dma_init();
151}
152
153/****************************************************************************
154*
155* Called from setup_arch (in arch/arm/kernel/setup.c) to fixup any tags
156* passed in by the boot loader.
157*
158*****************************************************************************/
159
160static void __init bcmring_fixup(struct tag *t, char **cmdline,
161 struct meminfo *mi) {
162#ifdef CONFIG_BLK_DEV_INITRD
163 printk(KERN_NOTICE "bcmring_fixup\n");
164 t->hdr.tag = ATAG_CORE;
165 t->hdr.size = tag_size(tag_core);
166 t->u.core.flags = 0;
167 t->u.core.pagesize = PAGE_SIZE;
168 t->u.core.rootdev = 31 << 8 | 0;
169 t = tag_next(t);
170
171 t->hdr.tag = ATAG_MEM;
172 t->hdr.size = tag_size(tag_mem32);
173 t->u.mem.start = CFG_GLOBAL_RAM_BASE;
174 t->u.mem.size = CFG_GLOBAL_RAM_SIZE;
175
176 t = tag_next(t);
177
178 t->hdr.tag = ATAG_NONE;
179 t->hdr.size = 0;
180#endif
181}
182
183/****************************************************************************
184*
185* Machine Description
186*
187*****************************************************************************/
188
189MACHINE_START(BCMRING, "BCMRING")
190 /* Maintainer: Broadcom Corporation */
191 .fixup = bcmring_fixup,
192 .map_io = bcmring_map_io,
193 .init_early = bcmring_init_early,
194 .init_irq = bcmring_init_irq,
195 .timer = &bcmring_timer,
196 .init_machine = bcmring_init_machine,
197 .restart = bcmring_restart,
198MACHINE_END
diff --git a/arch/arm/mach-bcmring/clock.c b/arch/arm/mach-bcmring/clock.c
deleted file mode 100644
index ad237a42d265..000000000000
--- a/arch/arm/mach-bcmring/clock.c
+++ /dev/null
@@ -1,223 +0,0 @@
1/*****************************************************************************
2* Copyright 2001 - 2009 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/device.h>
18#include <linux/list.h>
19#include <linux/errno.h>
20#include <linux/err.h>
21#include <linux/string.h>
22#include <linux/clk.h>
23#include <linux/spinlock.h>
24#include <linux/clkdev.h>
25#include <mach/csp/hw_cfg.h>
26#include <mach/csp/chipcHw_def.h>
27#include <mach/csp/chipcHw_reg.h>
28#include <mach/csp/chipcHw_inline.h>
29
30#include "clock.h"
31
32#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
33#define clk_is_pll1(x) ((x)->type & CLK_TYPE_PLL1)
34#define clk_is_pll2(x) ((x)->type & CLK_TYPE_PLL2)
35#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
36#define clk_is_bypassable(x) ((x)->type & CLK_TYPE_BYPASSABLE)
37
38#define clk_is_using_xtal(x) ((x)->mode & CLK_MODE_XTAL)
39
40static DEFINE_SPINLOCK(clk_lock);
41
42static void __clk_enable(struct clk *clk)
43{
44 if (!clk)
45 return;
46
47 /* enable parent clock first */
48 if (clk->parent)
49 __clk_enable(clk->parent);
50
51 if (clk->use_cnt++ == 0) {
52 if (clk_is_pll1(clk)) { /* PLL1 */
53 chipcHw_pll1Enable(clk->rate_hz, 0);
54 } else if (clk_is_pll2(clk)) { /* PLL2 */
55 chipcHw_pll2Enable(clk->rate_hz);
56 } else if (clk_is_using_xtal(clk)) { /* source is crystal */
57 if (!clk_is_primary(clk))
58 chipcHw_bypassClockEnable(clk->csp_id);
59 } else { /* source is PLL */
60 chipcHw_setClockEnable(clk->csp_id);
61 }
62 }
63}
64
65int clk_enable(struct clk *clk)
66{
67 unsigned long flags;
68
69 if (!clk)
70 return -EINVAL;
71
72 spin_lock_irqsave(&clk_lock, flags);
73 __clk_enable(clk);
74 spin_unlock_irqrestore(&clk_lock, flags);
75
76 return 0;
77}
78EXPORT_SYMBOL(clk_enable);
79
80static void __clk_disable(struct clk *clk)
81{
82 if (!clk)
83 return;
84
85 BUG_ON(clk->use_cnt == 0);
86
87 if (--clk->use_cnt == 0) {
88 if (clk_is_pll1(clk)) { /* PLL1 */
89 chipcHw_pll1Disable();
90 } else if (clk_is_pll2(clk)) { /* PLL2 */
91 chipcHw_pll2Disable();
92 } else if (clk_is_using_xtal(clk)) { /* source is crystal */
93 if (!clk_is_primary(clk))
94 chipcHw_bypassClockDisable(clk->csp_id);
95 } else { /* source is PLL */
96 chipcHw_setClockDisable(clk->csp_id);
97 }
98 }
99
100 if (clk->parent)
101 __clk_disable(clk->parent);
102}
103
104void clk_disable(struct clk *clk)
105{
106 unsigned long flags;
107
108 if (!clk)
109 return;
110
111 spin_lock_irqsave(&clk_lock, flags);
112 __clk_disable(clk);
113 spin_unlock_irqrestore(&clk_lock, flags);
114}
115EXPORT_SYMBOL(clk_disable);
116
117unsigned long clk_get_rate(struct clk *clk)
118{
119 if (!clk)
120 return 0;
121
122 return clk->rate_hz;
123}
124EXPORT_SYMBOL(clk_get_rate);
125
126long clk_round_rate(struct clk *clk, unsigned long rate)
127{
128 unsigned long flags;
129 unsigned long actual;
130 unsigned long rate_hz;
131
132 if (!clk)
133 return -EINVAL;
134
135 if (!clk_is_programmable(clk))
136 return -EINVAL;
137
138 if (clk->use_cnt)
139 return -EBUSY;
140
141 spin_lock_irqsave(&clk_lock, flags);
142 actual = clk->parent->rate_hz;
143 rate_hz = min(actual, rate);
144 spin_unlock_irqrestore(&clk_lock, flags);
145
146 return rate_hz;
147}
148EXPORT_SYMBOL(clk_round_rate);
149
150int clk_set_rate(struct clk *clk, unsigned long rate)
151{
152 unsigned long flags;
153 unsigned long actual;
154 unsigned long rate_hz;
155
156 if (!clk)
157 return -EINVAL;
158
159 if (!clk_is_programmable(clk))
160 return -EINVAL;
161
162 if (clk->use_cnt)
163 return -EBUSY;
164
165 spin_lock_irqsave(&clk_lock, flags);
166 actual = clk->parent->rate_hz;
167 rate_hz = min(actual, rate);
168 rate_hz = chipcHw_setClockFrequency(clk->csp_id, rate_hz);
169 clk->rate_hz = rate_hz;
170 spin_unlock_irqrestore(&clk_lock, flags);
171
172 return 0;
173}
174EXPORT_SYMBOL(clk_set_rate);
175
176struct clk *clk_get_parent(struct clk *clk)
177{
178 if (!clk)
179 return NULL;
180
181 return clk->parent;
182}
183EXPORT_SYMBOL(clk_get_parent);
184
185int clk_set_parent(struct clk *clk, struct clk *parent)
186{
187 unsigned long flags;
188 struct clk *old_parent;
189
190 if (!clk || !parent)
191 return -EINVAL;
192
193 if (!clk_is_primary(parent) || !clk_is_bypassable(clk))
194 return -EINVAL;
195
196 /* if more than one user, parent is not allowed */
197 if (clk->use_cnt > 1)
198 return -EBUSY;
199
200 if (clk->parent == parent)
201 return 0;
202
203 spin_lock_irqsave(&clk_lock, flags);
204 old_parent = clk->parent;
205 clk->parent = parent;
206 if (clk_is_using_xtal(parent))
207 clk->mode |= CLK_MODE_XTAL;
208 else
209 clk->mode &= (~CLK_MODE_XTAL);
210
211 /* if clock is active */
212 if (clk->use_cnt != 0) {
213 clk->use_cnt--;
214 /* enable clock with the new parent */
215 __clk_enable(clk);
216 /* disable the old parent */
217 __clk_disable(old_parent);
218 }
219 spin_unlock_irqrestore(&clk_lock, flags);
220
221 return 0;
222}
223EXPORT_SYMBOL(clk_set_parent);
diff --git a/arch/arm/mach-bcmring/clock.h b/arch/arm/mach-bcmring/clock.h
deleted file mode 100644
index 5e0b98138973..000000000000
--- a/arch/arm/mach-bcmring/clock.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*****************************************************************************
2* Copyright 2001 - 2009 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14#include <mach/csp/chipcHw_def.h>
15
16#define CLK_TYPE_PRIMARY 1 /* primary clock must NOT have a parent */
17#define CLK_TYPE_PLL1 2 /* PPL1 */
18#define CLK_TYPE_PLL2 4 /* PPL2 */
19#define CLK_TYPE_PROGRAMMABLE 8 /* programmable clock rate */
20#define CLK_TYPE_BYPASSABLE 16 /* parent can be changed */
21
22#define CLK_MODE_XTAL 1 /* clock source is from crystal */
23
24struct clk {
25 const char *name; /* clock name */
26 unsigned int type; /* clock type */
27 unsigned int mode; /* current mode */
28 volatile int use_bypass; /* indicate if it's in bypass mode */
29 chipcHw_CLOCK_e csp_id; /* clock ID for CSP CHIPC */
30 unsigned long rate_hz; /* clock rate in Hz */
31 unsigned int use_cnt; /* usage count */
32 struct clk *parent; /* parent clock */
33};
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
deleted file mode 100644
index 4b50228a6771..000000000000
--- a/arch/arm/mach-bcmring/core.c
+++ /dev/null
@@ -1,227 +0,0 @@
1/*
2 * derived from linux/arch/arm/mach-versatile/core.c
3 * linux/arch/arm/mach-bcmring/core.c
4 *
5 * Copyright (C) 1999 - 2003 ARM Limited
6 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22/* Portions copyright Broadcom 2008 */
23
24#include <linux/init.h>
25#include <linux/device.h>
26#include <linux/dma-mapping.h>
27#include <linux/platform_device.h>
28#include <linux/interrupt.h>
29#include <linux/amba/bus.h>
30#include <linux/clkdev.h>
31
32#include <mach/csp/mm_addr.h>
33#include <mach/hardware.h>
34#include <linux/io.h>
35#include <asm/irq.h>
36#include <asm/hardware/arm_timer.h>
37#include <asm/hardware/timer-sp.h>
38#include <asm/mach-types.h>
39
40#include <asm/mach/arch.h>
41#include <asm/mach/flash.h>
42#include <asm/mach/irq.h>
43#include <asm/mach/time.h>
44#include <asm/mach/map.h>
45
46#include <mach/cfg_global.h>
47
48#include "clock.h"
49
50#include <mach/csp/secHw_def.h>
51#include <mach/csp/chipcHw_inline.h>
52#include <mach/csp/tmrHw_reg.h>
53
54static AMBA_APB_DEVICE(uartA, "uartA", 0, MM_ADDR_IO_UARTA, {IRQ_UARTA}, NULL);
55static AMBA_APB_DEVICE(uartB, "uartB", 0, MM_ADDR_IO_UARTB, {IRQ_UARTB}, NULL);
56
57static struct clk pll1_clk = {
58 .name = "PLL1",
59 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL1,
60 .rate_hz = 2000000000,
61 .use_cnt = 7,
62};
63
64static struct clk uart_clk = {
65 .name = "UART",
66 .type = CLK_TYPE_PROGRAMMABLE,
67 .csp_id = chipcHw_CLOCK_UART,
68 .rate_hz = HW_CFG_UART_CLK_HZ,
69 .parent = &pll1_clk,
70};
71
72static struct clk dummy_apb_pclk = {
73 .name = "BUSCLK",
74 .type = CLK_TYPE_PRIMARY,
75 .mode = CLK_MODE_XTAL,
76};
77
78/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically 150-166 MHz */
79#if defined(CONFIG_ARCH_FPGA11107)
80/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
81/* slow down Linux's sense of time */
82#define TIMER0_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
83#define TIMER1_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
84#define TIMER3_FREQUENCY_MHZ (tmrHw_HIGH_FREQUENCY_MHZ * 30)
85#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
86#else
87#define TIMER0_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
88#define TIMER1_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
89#define TIMER3_FREQUENCY_MHZ tmrHw_HIGH_FREQUENCY_MHZ
90#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000)
91#endif
92
93static struct clk sp804_timer012_clk = {
94 .name = "sp804-timer-0,1,2",
95 .type = CLK_TYPE_PRIMARY,
96 .mode = CLK_MODE_XTAL,
97 .rate_hz = TIMER1_FREQUENCY_MHZ * 1000000,
98};
99
100static struct clk sp804_timer3_clk = {
101 .name = "sp804-timer-3",
102 .type = CLK_TYPE_PRIMARY,
103 .mode = CLK_MODE_XTAL,
104 .rate_hz = TIMER3_FREQUENCY_KHZ * 1000,
105};
106
107static struct clk_lookup lookups[] = {
108 { /* Bus clock */
109 .con_id = "apb_pclk",
110 .clk = &dummy_apb_pclk,
111 }, { /* UART0 */
112 .dev_id = "uarta",
113 .clk = &uart_clk,
114 }, { /* UART1 */
115 .dev_id = "uartb",
116 .clk = &uart_clk,
117 }, { /* SP804 timer 0 */
118 .dev_id = "sp804",
119 .con_id = "timer0",
120 .clk = &sp804_timer012_clk,
121 }, { /* SP804 timer 1 */
122 .dev_id = "sp804",
123 .con_id = "timer1",
124 .clk = &sp804_timer012_clk,
125 }, { /* SP804 timer 3 */
126 .dev_id = "sp804",
127 .con_id = "timer3",
128 .clk = &sp804_timer3_clk,
129 }
130};
131
132static struct amba_device *amba_devs[] __initdata = {
133 &uartA_device,
134 &uartB_device,
135};
136
137void __init bcmring_amba_init(void)
138{
139 int i;
140 u32 bus_clock;
141
142/* Linux is run initially in non-secure mode. Secure peripherals */
143/* generate FIQ, and must be handled in secure mode. Until we have */
144/* a linux security monitor implementation, keep everything in */
145/* non-secure mode. */
146 chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU);
147 secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL |
148 secHw_BLK_MASK_KEY_SCAN |
149 secHw_BLK_MASK_TOUCH_SCREEN |
150 secHw_BLK_MASK_UART0 |
151 secHw_BLK_MASK_UART1 |
152 secHw_BLK_MASK_WATCHDOG |
153 secHw_BLK_MASK_SPUM |
154 secHw_BLK_MASK_DDR2 |
155 secHw_BLK_MASK_SPU |
156 secHw_BLK_MASK_PKA |
157 secHw_BLK_MASK_RNG |
158 secHw_BLK_MASK_RTC |
159 secHw_BLK_MASK_OTP |
160 secHw_BLK_MASK_BOOT |
161 secHw_BLK_MASK_MPU |
162 secHw_BLK_MASK_TZCTRL | secHw_BLK_MASK_INTR);
163
164 /* Only the devices attached to the AMBA bus are enabled just before the bus is */
165 /* scanned and the drivers are loaded. The clocks need to be on for the AMBA bus */
166 /* driver to access these blocks. The bus is probed, and the drivers are loaded. */
167 /* FIXME Need to remove enable of PIF once CLCD clock enable used properly in FPGA. */
168 bus_clock = chipcHw_REG_BUS_CLOCK_GE
169 | chipcHw_REG_BUS_CLOCK_SDIO0 | chipcHw_REG_BUS_CLOCK_SDIO1;
170
171 chipcHw_busInterfaceClockEnable(bus_clock);
172
173 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
174 struct amba_device *d = amba_devs[i];
175 amba_device_register(d, &iomem_resource);
176 }
177}
178
179/*
180 * Where is the timer (VA)?
181 */
182#define TIMER0_VA_BASE ((void __iomem *)MM_IO_BASE_TMR)
183#define TIMER1_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x20))
184#define TIMER2_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x40))
185#define TIMER3_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x60))
186
187static int __init bcmring_clocksource_init(void)
188{
189 /* setup timer1 as free-running clocksource */
190 sp804_clocksource_init(TIMER1_VA_BASE, "timer1");
191
192 /* setup timer3 as free-running clocksource */
193 sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
194
195 return 0;
196}
197
198/*
199 * Set up timer interrupt, and return the current time in seconds.
200 */
201void __init bcmring_init_timer(void)
202{
203 printk(KERN_INFO "bcmring_init_timer\n");
204 /*
205 * Initialise to a known state (all timers off)
206 */
207 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
208 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
209 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
210 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
211
212 /*
213 * Make irqs happen for the system timer
214 */
215 bcmring_clocksource_init();
216
217 sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMER0, "timer0");
218}
219
220struct sys_timer bcmring_timer = {
221 .init = bcmring_init_timer,
222};
223
224void __init bcmring_init_early(void)
225{
226 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
227}
diff --git a/arch/arm/mach-bcmring/core.h b/arch/arm/mach-bcmring/core.h
deleted file mode 100644
index e0e02c48f9b1..000000000000
--- a/arch/arm/mach-bcmring/core.h
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * linux/arch/arm/mach-versatile/core.h
3 *
4 * Copyright (C) 2004 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21/* Portions copyright Broadcom 2008 */
22#ifndef __ASM_ARCH_BCMRING_H
23#define __ASM_ARCH_BCMRING_H
24
25void __init bcmring_amba_init(void);
26void __init bcmring_map_io(void);
27void __init bcmring_init_irq(void);
28void __init bcmring_init_early(void);
29
30extern struct sys_timer bcmring_timer;
31#endif
diff --git a/arch/arm/mach-bcmring/csp/Makefile b/arch/arm/mach-bcmring/csp/Makefile
deleted file mode 100644
index 648c0377530e..000000000000
--- a/arch/arm/mach-bcmring/csp/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
1obj-y += dmac/
2obj-y += tmr/
3obj-y += chipc/
diff --git a/arch/arm/mach-bcmring/csp/chipc/Makefile b/arch/arm/mach-bcmring/csp/chipc/Makefile
deleted file mode 100644
index 673952768ee5..000000000000
--- a/arch/arm/mach-bcmring/csp/chipc/Makefile
+++ /dev/null
@@ -1 +0,0 @@
1obj-y += chipcHw.o chipcHw_str.o chipcHw_reset.o chipcHw_init.o
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
deleted file mode 100644
index 5050833817b7..000000000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
+++ /dev/null
@@ -1,779 +0,0 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file chipcHw.c
18*
19* @brief Low level Various CHIP clock controlling routines
20*
21* @note
22*
23* These routines provide basic clock controlling functionality only.
24*/
25/****************************************************************************/
26
27/* ---- Include Files ---------------------------------------------------- */
28
29#include <linux/errno.h>
30#include <linux/types.h>
31#include <linux/export.h>
32
33#include <mach/csp/chipcHw_def.h>
34#include <mach/csp/chipcHw_inline.h>
35
36#include <mach/csp/reg.h>
37#include <linux/delay.h>
38
39/* ---- Private Constants and Types --------------------------------------- */
40
41/* VPM alignment algorithm uses this */
42#define MAX_PHASE_ADJUST_COUNT 0xFFFF /* Max number of times allowed to adjust the phase */
43#define MAX_PHASE_ALIGN_ATTEMPTS 10 /* Max number of attempt to align the phase */
44
45/* Local definition of clock type */
46#define PLL_CLOCK 1 /* PLL Clock */
47#define NON_PLL_CLOCK 2 /* Divider clock */
48
49static int chipcHw_divide(int num, int denom)
50 __attribute__ ((section(".aramtext")));
51
52/****************************************************************************/
53/**
54* @brief Set clock fequency for miscellaneous configurable clocks
55*
56* This function sets clock frequency
57*
58* @return Configured clock frequency in hertz
59*
60*/
61/****************************************************************************/
62chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */
63 ) {
64 uint32_t __iomem *pPLLReg = NULL;
65 uint32_t __iomem *pClockCtrl = NULL;
66 uint32_t __iomem *pDependentClock = NULL;
67 uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */
68 uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */
69 uint32_t dependentClockType = 0;
70 uint32_t vcoHz = 0;
71
72 /* Get VCO frequencies */
73 if ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
74 uint64_t adjustFreq = 0;
75
76 vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
77 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
78 ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
79 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
80
81 /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
82 adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz *
83 (uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS *
84 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, (chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC));
85 vcoFreqPll1Hz += (uint32_t) adjustFreq;
86 } else {
87 vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
88 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
89 ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
90 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
91 }
92 vcoFreqPll2Hz =
93 chipcHw_XTAL_FREQ_Hz *
94 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
95 ((readl(&pChipcHw->PLLPreDivider2) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
96 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
97
98 switch (clock) {
99 case chipcHw_CLOCK_DDR:
100 pPLLReg = &pChipcHw->DDRClock;
101 vcoHz = vcoFreqPll1Hz;
102 break;
103 case chipcHw_CLOCK_ARM:
104 pPLLReg = &pChipcHw->ARMClock;
105 vcoHz = vcoFreqPll1Hz;
106 break;
107 case chipcHw_CLOCK_ESW:
108 pPLLReg = &pChipcHw->ESWClock;
109 vcoHz = vcoFreqPll1Hz;
110 break;
111 case chipcHw_CLOCK_VPM:
112 pPLLReg = &pChipcHw->VPMClock;
113 vcoHz = vcoFreqPll1Hz;
114 break;
115 case chipcHw_CLOCK_ESW125:
116 pPLLReg = &pChipcHw->ESW125Clock;
117 vcoHz = vcoFreqPll1Hz;
118 break;
119 case chipcHw_CLOCK_UART:
120 pPLLReg = &pChipcHw->UARTClock;
121 vcoHz = vcoFreqPll1Hz;
122 break;
123 case chipcHw_CLOCK_SDIO0:
124 pPLLReg = &pChipcHw->SDIO0Clock;
125 vcoHz = vcoFreqPll1Hz;
126 break;
127 case chipcHw_CLOCK_SDIO1:
128 pPLLReg = &pChipcHw->SDIO1Clock;
129 vcoHz = vcoFreqPll1Hz;
130 break;
131 case chipcHw_CLOCK_SPI:
132 pPLLReg = &pChipcHw->SPIClock;
133 vcoHz = vcoFreqPll1Hz;
134 break;
135 case chipcHw_CLOCK_ETM:
136 pPLLReg = &pChipcHw->ETMClock;
137 vcoHz = vcoFreqPll1Hz;
138 break;
139 case chipcHw_CLOCK_USB:
140 pPLLReg = &pChipcHw->USBClock;
141 vcoHz = vcoFreqPll2Hz;
142 break;
143 case chipcHw_CLOCK_LCD:
144 pPLLReg = &pChipcHw->LCDClock;
145 vcoHz = vcoFreqPll2Hz;
146 break;
147 case chipcHw_CLOCK_APM:
148 pPLLReg = &pChipcHw->APMClock;
149 vcoHz = vcoFreqPll2Hz;
150 break;
151 case chipcHw_CLOCK_BUS:
152 pClockCtrl = &pChipcHw->ACLKClock;
153 pDependentClock = &pChipcHw->ARMClock;
154 vcoHz = vcoFreqPll1Hz;
155 dependentClockType = PLL_CLOCK;
156 break;
157 case chipcHw_CLOCK_OTP:
158 pClockCtrl = &pChipcHw->OTPClock;
159 break;
160 case chipcHw_CLOCK_I2C:
161 pClockCtrl = &pChipcHw->I2CClock;
162 break;
163 case chipcHw_CLOCK_I2S0:
164 pClockCtrl = &pChipcHw->I2S0Clock;
165 break;
166 case chipcHw_CLOCK_RTBUS:
167 pClockCtrl = &pChipcHw->RTBUSClock;
168 pDependentClock = &pChipcHw->ACLKClock;
169 dependentClockType = NON_PLL_CLOCK;
170 break;
171 case chipcHw_CLOCK_APM100:
172 pClockCtrl = &pChipcHw->APM100Clock;
173 pDependentClock = &pChipcHw->APMClock;
174 vcoHz = vcoFreqPll2Hz;
175 dependentClockType = PLL_CLOCK;
176 break;
177 case chipcHw_CLOCK_TSC:
178 pClockCtrl = &pChipcHw->TSCClock;
179 break;
180 case chipcHw_CLOCK_LED:
181 pClockCtrl = &pChipcHw->LEDClock;
182 break;
183 case chipcHw_CLOCK_I2S1:
184 pClockCtrl = &pChipcHw->I2S1Clock;
185 break;
186 }
187
188 if (pPLLReg) {
189 /* Obtain PLL clock frequency */
190 if (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
191 /* Return crystal clock frequency when bypassed */
192 return chipcHw_XTAL_FREQ_Hz;
193 } else if (clock == chipcHw_CLOCK_DDR) {
194 /* DDR frequency is configured in PLLDivider register */
195 return chipcHw_divide (vcoHz, (((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) ? ((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) : 256));
196 } else {
197 /* From chip revision number B0, LCD clock is internally divided by 2 */
198 if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
199 vcoHz >>= 1;
200 }
201 /* Obtain PLL clock frequency using VCO dividers */
202 return chipcHw_divide(vcoHz, ((readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
203 }
204 } else if (pClockCtrl) {
205 /* Obtain divider clock frequency */
206 uint32_t div;
207 uint32_t freq = 0;
208
209 if (readl(pClockCtrl) & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
210 /* Return crystal clock frequency when bypassed */
211 return chipcHw_XTAL_FREQ_Hz;
212 } else if (pDependentClock) {
213 /* Identify the dependent clock frequency */
214 switch (dependentClockType) {
215 case PLL_CLOCK:
216 if (readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
217 /* Use crystal clock frequency when dependent PLL clock is bypassed */
218 freq = chipcHw_XTAL_FREQ_Hz;
219 } else {
220 /* Obtain PLL clock frequency using VCO dividers */
221 div = readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_MDIV_MASK;
222 freq = div ? chipcHw_divide(vcoHz, div) : 0;
223 }
224 break;
225 case NON_PLL_CLOCK:
226 if (pDependentClock == &pChipcHw->ACLKClock) {
227 freq = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
228 } else {
229 if (readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
230 /* Use crystal clock frequency when dependent divider clock is bypassed */
231 freq = chipcHw_XTAL_FREQ_Hz;
232 } else {
233 /* Obtain divider clock frequency using XTAL dividers */
234 div = readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_DIV_MASK;
235 freq = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, (div ? div : 256));
236 }
237 }
238 break;
239 }
240 } else {
241 /* Dependent on crystal clock */
242 freq = chipcHw_XTAL_FREQ_Hz;
243 }
244
245 div = readl(pClockCtrl) & chipcHw_REG_DIV_CLOCK_DIV_MASK;
246 return chipcHw_divide(freq, (div ? div : 256));
247 }
248 return 0;
249}
250
251/****************************************************************************/
252/**
253* @brief Set clock fequency for miscellaneous configurable clocks
254*
255* This function sets clock frequency
256*
257* @return Configured clock frequency in Hz
258*
259*/
260/****************************************************************************/
261chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configurable clock */
262 uint32_t freq /* [ IN ] Clock frequency in Hz */
263 ) {
264 uint32_t __iomem *pPLLReg = NULL;
265 uint32_t __iomem *pClockCtrl = NULL;
266 uint32_t __iomem *pDependentClock = NULL;
267 uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */
268 uint32_t desVcoFreqPll1Hz = 0; /* Desired VCO frequency for PLL1 in Hz */
269 uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */
270 uint32_t dependentClockType = 0;
271 uint32_t vcoHz = 0;
272 uint32_t desVcoHz = 0;
273
274 /* Get VCO frequencies */
275 if ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
276 uint64_t adjustFreq = 0;
277
278 vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
279 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
280 ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
281 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
282
283 /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
284 adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz *
285 (uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS *
286 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, (chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC));
287 vcoFreqPll1Hz += (uint32_t) adjustFreq;
288
289 /* Desired VCO frequency */
290 desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
291 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
292 (((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
293 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) + 1);
294 } else {
295 vcoFreqPll1Hz = desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
296 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
297 ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
298 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
299 }
300 vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
301 ((readl(&pChipcHw->PLLPreDivider2) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
302 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
303
304 switch (clock) {
305 case chipcHw_CLOCK_DDR:
306 /* Configure the DDR_ctrl:BUS ratio settings */
307 {
308 REG_LOCAL_IRQ_SAVE;
309 /* Dvide DDR_phy by two to obtain DDR_ctrl clock */
310 writel((readl(&pChipcHw->DDRClock) & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT), &pChipcHw->DDRClock);
311 REG_LOCAL_IRQ_RESTORE;
312 }
313 pPLLReg = &pChipcHw->DDRClock;
314 vcoHz = vcoFreqPll1Hz;
315 desVcoHz = desVcoFreqPll1Hz;
316 break;
317 case chipcHw_CLOCK_ARM:
318 pPLLReg = &pChipcHw->ARMClock;
319 vcoHz = vcoFreqPll1Hz;
320 desVcoHz = desVcoFreqPll1Hz;
321 break;
322 case chipcHw_CLOCK_ESW:
323 pPLLReg = &pChipcHw->ESWClock;
324 vcoHz = vcoFreqPll1Hz;
325 desVcoHz = desVcoFreqPll1Hz;
326 break;
327 case chipcHw_CLOCK_VPM:
328 /* Configure the VPM:BUS ratio settings */
329 {
330 REG_LOCAL_IRQ_SAVE;
331 writel((readl(&pChipcHw->VPMClock) & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT), &pChipcHw->VPMClock);
332 REG_LOCAL_IRQ_RESTORE;
333 }
334 pPLLReg = &pChipcHw->VPMClock;
335 vcoHz = vcoFreqPll1Hz;
336 desVcoHz = desVcoFreqPll1Hz;
337 break;
338 case chipcHw_CLOCK_ESW125:
339 pPLLReg = &pChipcHw->ESW125Clock;
340 vcoHz = vcoFreqPll1Hz;
341 desVcoHz = desVcoFreqPll1Hz;
342 break;
343 case chipcHw_CLOCK_UART:
344 pPLLReg = &pChipcHw->UARTClock;
345 vcoHz = vcoFreqPll1Hz;
346 desVcoHz = desVcoFreqPll1Hz;
347 break;
348 case chipcHw_CLOCK_SDIO0:
349 pPLLReg = &pChipcHw->SDIO0Clock;
350 vcoHz = vcoFreqPll1Hz;
351 desVcoHz = desVcoFreqPll1Hz;
352 break;
353 case chipcHw_CLOCK_SDIO1:
354 pPLLReg = &pChipcHw->SDIO1Clock;
355 vcoHz = vcoFreqPll1Hz;
356 desVcoHz = desVcoFreqPll1Hz;
357 break;
358 case chipcHw_CLOCK_SPI:
359 pPLLReg = &pChipcHw->SPIClock;
360 vcoHz = vcoFreqPll1Hz;
361 desVcoHz = desVcoFreqPll1Hz;
362 break;
363 case chipcHw_CLOCK_ETM:
364 pPLLReg = &pChipcHw->ETMClock;
365 vcoHz = vcoFreqPll1Hz;
366 desVcoHz = desVcoFreqPll1Hz;
367 break;
368 case chipcHw_CLOCK_USB:
369 pPLLReg = &pChipcHw->USBClock;
370 vcoHz = vcoFreqPll2Hz;
371 desVcoHz = vcoFreqPll2Hz;
372 break;
373 case chipcHw_CLOCK_LCD:
374 pPLLReg = &pChipcHw->LCDClock;
375 vcoHz = vcoFreqPll2Hz;
376 desVcoHz = vcoFreqPll2Hz;
377 break;
378 case chipcHw_CLOCK_APM:
379 pPLLReg = &pChipcHw->APMClock;
380 vcoHz = vcoFreqPll2Hz;
381 desVcoHz = vcoFreqPll2Hz;
382 break;
383 case chipcHw_CLOCK_BUS:
384 pClockCtrl = &pChipcHw->ACLKClock;
385 pDependentClock = &pChipcHw->ARMClock;
386 vcoHz = vcoFreqPll1Hz;
387 desVcoHz = desVcoFreqPll1Hz;
388 dependentClockType = PLL_CLOCK;
389 break;
390 case chipcHw_CLOCK_OTP:
391 pClockCtrl = &pChipcHw->OTPClock;
392 break;
393 case chipcHw_CLOCK_I2C:
394 pClockCtrl = &pChipcHw->I2CClock;
395 break;
396 case chipcHw_CLOCK_I2S0:
397 pClockCtrl = &pChipcHw->I2S0Clock;
398 break;
399 case chipcHw_CLOCK_RTBUS:
400 pClockCtrl = &pChipcHw->RTBUSClock;
401 pDependentClock = &pChipcHw->ACLKClock;
402 dependentClockType = NON_PLL_CLOCK;
403 break;
404 case chipcHw_CLOCK_APM100:
405 pClockCtrl = &pChipcHw->APM100Clock;
406 pDependentClock = &pChipcHw->APMClock;
407 vcoHz = vcoFreqPll2Hz;
408 desVcoHz = vcoFreqPll2Hz;
409 dependentClockType = PLL_CLOCK;
410 break;
411 case chipcHw_CLOCK_TSC:
412 pClockCtrl = &pChipcHw->TSCClock;
413 break;
414 case chipcHw_CLOCK_LED:
415 pClockCtrl = &pChipcHw->LEDClock;
416 break;
417 case chipcHw_CLOCK_I2S1:
418 pClockCtrl = &pChipcHw->I2S1Clock;
419 break;
420 }
421
422 if (pPLLReg) {
423 /* Select XTAL as bypass source */
424 reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_SOURCE_GPIO);
425 reg32_modify_or(pPLLReg, chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
426 /* For DDR settings use only the PLL divider clock */
427 if (pPLLReg == &pChipcHw->DDRClock) {
428 /* Set M1DIV for PLL1, which controls the DDR clock */
429 reg32_write(&pChipcHw->PLLDivider, (readl(&pChipcHw->PLLDivider) & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24));
430 /* Calculate expected frequency */
431 freq = chipcHw_divide(vcoHz, (((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) ? ((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) : 256));
432 } else {
433 /* From chip revision number B0, LCD clock is internally divided by 2 */
434 if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
435 desVcoHz >>= 1;
436 vcoHz >>= 1;
437 }
438 /* Set MDIV to change the frequency */
439 reg32_modify_and(pPLLReg, ~(chipcHw_REG_PLL_CLOCK_MDIV_MASK));
440 reg32_modify_or(pPLLReg, chipcHw_REG_PLL_DIVIDER_MDIV(desVcoHz, freq));
441 /* Calculate expected frequency */
442 freq = chipcHw_divide(vcoHz, ((readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
443 }
444 /* Wait for for atleast 200ns as per the protocol to change frequency */
445 udelay(1);
446 /* Do not bypass */
447 reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
448 /* Return the configured frequency */
449 return freq;
450 } else if (pClockCtrl) {
451 uint32_t divider = 0;
452
453 /* Divider clock should not be bypassed */
454 reg32_modify_and(pClockCtrl,
455 ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
456
457 /* Identify the clock source */
458 if (pDependentClock) {
459 switch (dependentClockType) {
460 case PLL_CLOCK:
461 divider = chipcHw_divide(chipcHw_divide (desVcoHz, (readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq);
462 break;
463 case NON_PLL_CLOCK:
464 {
465 uint32_t sourceClock = 0;
466
467 if (pDependentClock == &pChipcHw->ACLKClock) {
468 sourceClock = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
469 } else {
470 uint32_t div = readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_DIV_MASK;
471 sourceClock = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, ((div) ? div : 256));
472 }
473 divider = chipcHw_divide(sourceClock, freq);
474 }
475 break;
476 }
477 } else {
478 divider = chipcHw_divide(chipcHw_XTAL_FREQ_Hz, freq);
479 }
480
481 if (divider) {
482 REG_LOCAL_IRQ_SAVE;
483 /* Set the divider to obtain the required frequency */
484 writel((readl(pClockCtrl) & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK), pClockCtrl);
485 REG_LOCAL_IRQ_RESTORE;
486 return freq;
487 }
488 }
489
490 return 0;
491}
492
493EXPORT_SYMBOL(chipcHw_setClockFrequency);
494
495/****************************************************************************/
496/**
497* @brief Set VPM clock in sync with BUS clock for Chip Rev #A0
498*
499* This function does the phase adjustment between VPM and BUS clock
500*
501* @return >= 0 : On success (# of adjustment required)
502* -1 : On failure
503*
504*/
505/****************************************************************************/
506static int vpmPhaseAlignA0(void)
507{
508 uint32_t phaseControl;
509 uint32_t phaseValue;
510 uint32_t prevPhaseComp;
511 int iter = 0;
512 int adjustCount = 0;
513 int count = 0;
514
515 for (iter = 0; (iter < MAX_PHASE_ALIGN_ATTEMPTS) && (adjustCount < MAX_PHASE_ADJUST_COUNT); iter++) {
516 phaseControl = (readl(&pChipcHw->VPMClock) & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT;
517 phaseValue = 0;
518 prevPhaseComp = 0;
519
520 /* Step 1: Look for falling PH_COMP transition */
521
522 /* Read the contents of VPM Clock resgister */
523 phaseValue = readl(&pChipcHw->VPMClock);
524 do {
525 /* Store previous value of phase comparator */
526 prevPhaseComp = phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP;
527 /* Change the value of PH_CTRL. */
528 reg32_write(&pChipcHw->VPMClock,
529 (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
530 /* Wait atleast 20 ns */
531 udelay(1);
532 /* Toggle the LOAD_CH after phase control is written. */
533 writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
534 /* Read the contents of VPM Clock resgister. */
535 phaseValue = readl(&pChipcHw->VPMClock);
536
537 if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
538 phaseControl = (0x3F & (phaseControl - 1));
539 } else {
540 /* Increment to the Phase count value for next write, if Phase is not stable. */
541 phaseControl = (0x3F & (phaseControl + 1));
542 }
543 /* Count number of adjustment made */
544 adjustCount++;
545 } while (((prevPhaseComp == (phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP)) || /* Look for a transition */
546 ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) != 0x0)) && /* Look for a falling edge */
547 (adjustCount < MAX_PHASE_ADJUST_COUNT) /* Do not exceed the limit while trying */
548 );
549
550 if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
551 /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
552 return -1;
553 }
554
555 /* Step 2: Keep moving forward to make sure falling PH_COMP transition was valid */
556
557 for (count = 0; (count < 5) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
558 phaseControl = (0x3F & (phaseControl + 1));
559 reg32_write(&pChipcHw->VPMClock,
560 (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
561 /* Wait atleast 20 ns */
562 udelay(1);
563 /* Toggle the LOAD_CH after phase control is written. */
564 writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
565 phaseValue = readl(&pChipcHw->VPMClock);
566 /* Count number of adjustment made */
567 adjustCount++;
568 }
569
570 if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
571 /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
572 return -1;
573 }
574
575 if (count != 5) {
576 /* Detected false transition */
577 continue;
578 }
579
580 /* Step 3: Keep moving backward to make sure falling PH_COMP transition was stable */
581
582 for (count = 0; (count < 3) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
583 phaseControl = (0x3F & (phaseControl - 1));
584 reg32_write(&pChipcHw->VPMClock,
585 (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
586 /* Wait atleast 20 ns */
587 udelay(1);
588 /* Toggle the LOAD_CH after phase control is written. */
589 writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
590 phaseValue = readl(&pChipcHw->VPMClock);
591 /* Count number of adjustment made */
592 adjustCount++;
593 }
594
595 if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
596 /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
597 return -1;
598 }
599
600 if (count != 3) {
601 /* Detected noisy transition */
602 continue;
603 }
604
605 /* Step 4: Keep moving backward before the original transition took place. */
606
607 for (count = 0; (count < 5); count++) {
608 phaseControl = (0x3F & (phaseControl - 1));
609 reg32_write(&pChipcHw->VPMClock,
610 (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
611 /* Wait atleast 20 ns */
612 udelay(1);
613 /* Toggle the LOAD_CH after phase control is written. */
614 writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
615 phaseValue = readl(&pChipcHw->VPMClock);
616 /* Count number of adjustment made */
617 adjustCount++;
618 }
619
620 if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
621 /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
622 return -1;
623 }
624
625 if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0) {
626 /* Detected false transition */
627 continue;
628 }
629
630 /* Step 5: Re discover the valid transition */
631
632 do {
633 /* Store previous value of phase comparator */
634 prevPhaseComp = phaseValue;
635 /* Change the value of PH_CTRL. */
636 reg32_write(&pChipcHw->VPMClock,
637 (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
638 /* Wait atleast 20 ns */
639 udelay(1);
640 /* Toggle the LOAD_CH after phase control is written. */
641 writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
642 /* Read the contents of VPM Clock resgister. */
643 phaseValue = readl(&pChipcHw->VPMClock);
644
645 if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
646 phaseControl = (0x3F & (phaseControl - 1));
647 } else {
648 /* Increment to the Phase count value for next write, if Phase is not stable. */
649 phaseControl = (0x3F & (phaseControl + 1));
650 }
651
652 /* Count number of adjustment made */
653 adjustCount++;
654 } while (((prevPhaseComp == (phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP)) || ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) != 0x0)) && (adjustCount < MAX_PHASE_ADJUST_COUNT));
655
656 if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
657 /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
658 return -1;
659 } else {
660 /* Valid phase must have detected */
661 break;
662 }
663 }
664
665 /* For VPM Phase should be perfectly aligned. */
666 phaseControl = (((readl(&pChipcHw->VPMClock) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F);
667 {
668 REG_LOCAL_IRQ_SAVE;
669
670 writel((readl(&pChipcHw->VPMClock) & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT), &pChipcHw->VPMClock);
671 /* Load new phase value */
672 writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
673
674 REG_LOCAL_IRQ_RESTORE;
675 }
676 /* Return the status */
677 return (int)adjustCount;
678}
679
680/****************************************************************************/
681/**
682* @brief Set VPM clock in sync with BUS clock
683*
684* This function does the phase adjustment between VPM and BUS clock
685*
686* @return >= 0 : On success (# of adjustment required)
687* -1 : On failure
688*
689*/
690/****************************************************************************/
691int chipcHw_vpmPhaseAlign(void)
692{
693
694 if (chipcHw_getChipRevisionNumber() == chipcHw_REV_NUMBER_A0) {
695 return vpmPhaseAlignA0();
696 } else {
697 uint32_t phaseControl = chipcHw_getVpmPhaseControl();
698 uint32_t phaseValue = 0;
699 int adjustCount = 0;
700
701 /* Disable VPM access */
702 writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1);
703 /* Disable HW VPM phase alignment */
704 chipcHw_vpmHwPhaseAlignDisable();
705 /* Enable SW VPM phase alignment */
706 chipcHw_vpmSwPhaseAlignEnable();
707 /* Adjust VPM phase */
708 while (adjustCount < MAX_PHASE_ADJUST_COUNT) {
709 phaseValue = chipcHw_getVpmHwPhaseAlignStatus();
710
711 /* Adjust phase control value */
712 if (phaseValue > 0xF) {
713 /* Increment phase control value */
714 phaseControl++;
715 } else if (phaseValue < 0xF) {
716 /* Decrement phase control value */
717 phaseControl--;
718 } else {
719 /* Enable VPM access */
720 writel(readl(&pChipcHw->Spare1) | chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1);
721 /* Return adjust count */
722 return adjustCount;
723 }
724 /* Change the value of PH_CTRL. */
725 reg32_write(&pChipcHw->VPMClock,
726 (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
727 /* Wait atleast 20 ns */
728 udelay(1);
729 /* Toggle the LOAD_CH after phase control is written. */
730 writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
731 /* Count adjustment */
732 adjustCount++;
733 }
734 }
735
736 /* Disable VPM access */
737 writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1);
738 return -1;
739}
740
741/****************************************************************************/
742/**
743* @brief Local Divide function
744*
745* This function does the divide
746*
747* @return divide value
748*
749*/
750/****************************************************************************/
751static int chipcHw_divide(int num, int denom)
752{
753 int r;
754 int t = 1;
755
756 /* Shift denom and t up to the largest value to optimize algorithm */
757 /* t contains the units of each divide */
758 while ((denom & 0x40000000) == 0) { /* fails if denom=0 */
759 denom = denom << 1;
760 t = t << 1;
761 }
762
763 /* Initialize the result */
764 r = 0;
765
766 do {
767 /* Determine if there exists a positive remainder */
768 if ((num - denom) >= 0) {
769 /* Accumlate t to the result and calculate a new remainder */
770 num = num - denom;
771 r = r + t;
772 }
773 /* Continue to shift denom and shift t down to 0 */
774 denom = denom >> 1;
775 t = t >> 1;
776 } while (t != 0);
777
778 return r;
779}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
deleted file mode 100644
index 8377d8054168..000000000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
+++ /dev/null
@@ -1,283 +0,0 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file chipcHw_init.c
18*
19* @brief Low level CHIPC PLL configuration functions
20*
21* @note
22*
23* These routines provide basic PLL controlling functionality only.
24*/
25/****************************************************************************/
26
27/* ---- Include Files ---------------------------------------------------- */
28
29#include <linux/errno.h>
30#include <linux/types.h>
31#include <linux/export.h>
32
33#include <mach/csp/chipcHw_def.h>
34#include <mach/csp/chipcHw_inline.h>
35
36#include <mach/csp/reg.h>
37#include <linux/delay.h>
38/* ---- Private Constants and Types --------------------------------------- */
39
40/*
41 Calculation for NDIV_i to obtain VCO frequency
42 -----------------------------------------------
43
44 Freq_vco = Freq_ref * (P2 / P1) * (PLL_NDIV_i + PLL_NDIV_f)
45 for Freq_vco = VCO_FREQ_MHz
46 Freq_ref = chipcHw_XTAL_FREQ_Hz
47 PLL_P1 = PLL_P2 = 1
48 and
49 PLL_NDIV_f = 0
50
51 We get:
52 PLL_NDIV_i = Freq_vco / Freq_ref = VCO_FREQ_MHz / chipcHw_XTAL_FREQ_Hz
53
54 Calculation for PLL MDIV to obtain frequency Freq_x for channel x
55 -----------------------------------------------------------------
56 Freq_x = chipcHw_XTAL_FREQ_Hz * PLL_NDIV_i / PLL_MDIV_x = VCO_FREQ_MHz / PLL_MDIV_x
57
58 PLL_MDIV_x = VCO_FREQ_MHz / Freq_x
59*/
60
61/* ---- Private Variables ------------------------------------------------- */
62/****************************************************************************/
63/**
64* @brief Initializes the PLL2
65*
66* This function initializes the PLL2
67*
68*/
69/****************************************************************************/
70void chipcHw_pll2Enable(uint32_t vcoFreqHz)
71{
72 uint32_t pllPreDivider2 = 0;
73
74 {
75 REG_LOCAL_IRQ_SAVE;
76 writel(chipcHw_REG_PLL_CONFIG_D_RESET |
77 chipcHw_REG_PLL_CONFIG_A_RESET,
78 &pChipcHw->PLLConfig2);
79
80 pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
81 chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
82 (chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
83 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
84 (chipcHw_REG_PLL_PREDIVIDER_P1 <<
85 chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
86 (chipcHw_REG_PLL_PREDIVIDER_P2 <<
87 chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
88
89 /* Enable CHIPC registers to control the PLL */
90 writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus);
91
92 /* Set pre divider to get desired VCO frequency */
93 writel(pllPreDivider2, &pChipcHw->PLLPreDivider2);
94 /* Set NDIV Frac */
95 writel(chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider2);
96
97 /* This has to be removed once the default values are fixed for PLL2. */
98 writel(0x38000700, &pChipcHw->PLLControl12);
99 writel(0x00000015, &pChipcHw->PLLControl22);
100
101 /* Reset PLL2 */
102 if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
103 writel(chipcHw_REG_PLL_CONFIG_D_RESET |
104 chipcHw_REG_PLL_CONFIG_A_RESET |
105 chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
106 chipcHw_REG_PLL_CONFIG_POWER_DOWN,
107 &pChipcHw->PLLConfig2);
108 } else {
109 writel(chipcHw_REG_PLL_CONFIG_D_RESET |
110 chipcHw_REG_PLL_CONFIG_A_RESET |
111 chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
112 chipcHw_REG_PLL_CONFIG_POWER_DOWN,
113 &pChipcHw->PLLConfig2);
114 }
115 REG_LOCAL_IRQ_RESTORE;
116 }
117
118 /* Insert certain amount of delay before deasserting ARESET. */
119 udelay(1);
120
121 {
122 REG_LOCAL_IRQ_SAVE;
123 /* Remove analog reset and Power on the PLL */
124 writel(readl(&pChipcHw->PLLConfig2) &
125 ~(chipcHw_REG_PLL_CONFIG_A_RESET |
126 chipcHw_REG_PLL_CONFIG_POWER_DOWN),
127 &pChipcHw->PLLConfig2);
128
129 REG_LOCAL_IRQ_RESTORE;
130
131 }
132
133 /* Wait until PLL is locked */
134 while (!(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED))
135 ;
136
137 {
138 REG_LOCAL_IRQ_SAVE;
139 /* Remove digital reset */
140 writel(readl(&pChipcHw->PLLConfig2) &
141 ~chipcHw_REG_PLL_CONFIG_D_RESET,
142 &pChipcHw->PLLConfig2);
143
144 REG_LOCAL_IRQ_RESTORE;
145 }
146}
147
148EXPORT_SYMBOL(chipcHw_pll2Enable);
149
150/****************************************************************************/
151/**
152* @brief Initializes the PLL1
153*
154* This function initializes the PLL1
155*
156*/
157/****************************************************************************/
158void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
159{
160 uint32_t pllPreDivider = 0;
161
162 {
163 REG_LOCAL_IRQ_SAVE;
164
165 writel(chipcHw_REG_PLL_CONFIG_D_RESET |
166 chipcHw_REG_PLL_CONFIG_A_RESET,
167 &pChipcHw->PLLConfig);
168 /* Setting VCO frequency */
169 if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
170 pllPreDivider =
171 chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8 |
172 ((chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) -
173 1) << chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
174 (chipcHw_REG_PLL_PREDIVIDER_P1 <<
175 chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
176 (chipcHw_REG_PLL_PREDIVIDER_P2 <<
177 chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
178 } else {
179 pllPreDivider = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
180 chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
181 (chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
182 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
183 (chipcHw_REG_PLL_PREDIVIDER_P1 <<
184 chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
185 (chipcHw_REG_PLL_PREDIVIDER_P2 <<
186 chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
187 }
188
189 /* Enable CHIPC registers to control the PLL */
190 writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus);
191
192 /* Set pre divider to get desired VCO frequency */
193 writel(pllPreDivider, &pChipcHw->PLLPreDivider);
194 /* Set NDIV Frac */
195 if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
196 writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f_SS, &pChipcHw->PLLDivider);
197 } else {
198 writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider);
199 }
200
201 /* Reset PLL1 */
202 if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
203 writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig);
204 } else {
205 writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_800_1600 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig);
206 }
207
208 REG_LOCAL_IRQ_RESTORE;
209
210 /* Insert certain amount of delay before deasserting ARESET. */
211 udelay(1);
212
213 {
214 REG_LOCAL_IRQ_SAVE;
215 /* Remove analog reset and Power on the PLL */
216 writel(readl(&pChipcHw->PLLConfig) & ~(chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_POWER_DOWN), &pChipcHw->PLLConfig);
217 REG_LOCAL_IRQ_RESTORE;
218 }
219
220 /* Wait until PLL is locked */
221 while (!(readl(&pChipcHw->PLLStatus) & chipcHw_REG_PLL_STATUS_LOCKED)
222 || !(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED))
223 ;
224
225 /* Remove digital reset */
226 {
227 REG_LOCAL_IRQ_SAVE;
228 writel(readl(&pChipcHw->PLLConfig) & ~chipcHw_REG_PLL_CONFIG_D_RESET, &pChipcHw->PLLConfig);
229 REG_LOCAL_IRQ_RESTORE;
230 }
231 }
232}
233
234EXPORT_SYMBOL(chipcHw_pll1Enable);
235
236/****************************************************************************/
237/**
238* @brief Initializes the chipc module
239*
240* This function initializes the PLLs and core system clocks
241*
242*/
243/****************************************************************************/
244
245void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam /* [ IN ] Misc chip initialization parameter */
246 ) {
247#if !(defined(__KERNEL__) && !defined(STANDALONE))
248 delay_init();
249#endif
250
251 /* Do not program PLL, when warm reset */
252 if (!(chipcHw_getStickyBits() & chipcHw_REG_STICKY_CHIP_WARM_RESET)) {
253 chipcHw_pll1Enable(initParam->pllVcoFreqHz,
254 initParam->ssSupport);
255 chipcHw_pll2Enable(initParam->pll2VcoFreqHz);
256 } else {
257 /* Clear sticky bits */
258 chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_WARM_RESET);
259 }
260 /* Clear sticky bits */
261 chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET);
262
263 /* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */
264 writel((readl(&pChipcHw->ACLKClock) & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam-> armBusRatio & chipcHw_REG_ACLKClock_CLK_DIV_MASK), &pChipcHw->ACLKClock);
265
266 /* Set various core component frequencies. The order in which this is done is important for some. */
267 /* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */
268 /* frequency to find its ratio with the BUS. Hence we must set the ARM first, followed by the BUS, */
269 /* then VPM and RTBUS. */
270
271 chipcHw_setClockFrequency(chipcHw_CLOCK_ARM,
272 initParam->busClockFreqHz *
273 initParam->armBusRatio);
274 chipcHw_setClockFrequency(chipcHw_CLOCK_BUS, initParam->busClockFreqHz);
275 chipcHw_setClockFrequency(chipcHw_CLOCK_VPM,
276 initParam->busClockFreqHz *
277 initParam->vpmBusRatio);
278 chipcHw_setClockFrequency(chipcHw_CLOCK_DDR,
279 initParam->busClockFreqHz *
280 initParam->ddrBusRatio);
281 chipcHw_setClockFrequency(chipcHw_CLOCK_RTBUS,
282 initParam->busClockFreqHz / 2);
283}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
deleted file mode 100644
index f95ce913fa1e..000000000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
+++ /dev/null
@@ -1,125 +0,0 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/* ---- Include Files ---------------------------------------------------- */
16#include <linux/types.h>
17#include <mach/csp/chipcHw_def.h>
18#include <mach/csp/chipcHw_inline.h>
19#include <mach/csp/intcHw_reg.h>
20#include <asm/cacheflush.h>
21
22/* ---- Private Constants and Types --------------------------------------- */
23/* ---- Private Variables ------------------------------------------------- */
24void chipcHw_reset_run_from_aram(void);
25
26typedef void (*RUNFUNC) (void);
27
28/****************************************************************************/
29/**
30* @brief warmReset
31*
32* @note warmReset configures the clocks which are not reset back to the state
33* required to execute on reset. To do so we need to copy the code into internal
34* memory to change the ARM clock while we are not executing from DDR.
35*/
36/****************************************************************************/
37void chipcHw_reset(uint32_t mask)
38{
39 int i = 0;
40 RUNFUNC runFunc = (RUNFUNC) (unsigned long)MM_ADDR_IO_ARAM;
41
42 /* Disable all interrupts */
43 intcHw_irq_disable(INTCHW_INTC0, 0xffffffff);
44 intcHw_irq_disable(INTCHW_INTC1, 0xffffffff);
45 intcHw_irq_disable(INTCHW_SINTC, 0xffffffff);
46
47 {
48 REG_LOCAL_IRQ_SAVE;
49 if (mask & chipcHw_REG_SOFT_RESET_CHIP_SOFT) {
50 chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
51 }
52 /* Bypass the PLL clocks before reboot */
53 writel(readl(&pChipcHw->UARTClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT,
54 &pChipcHw->UARTClock);
55 writel(readl(&pChipcHw->SPIClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT,
56 &pChipcHw->SPIClock);
57
58 /* Copy the chipcHw_warmReset_run_from_aram function into ARAM */
59 do {
60 writel(((uint32_t *) &chipcHw_reset_run_from_aram)[i], ((uint32_t __iomem *) MM_IO_BASE_ARAM) + i);
61 i++;
62 } while (readl(((uint32_t __iomem*) MM_IO_BASE_ARAM) + i - 1) != 0xe1a0f00f); /* 0xe1a0f00f == asm ("mov r15, r15"); */
63
64 flush_cache_all();
65
66 /* run the function from ARAM */
67 runFunc();
68
69 /* Code will never get here, but include it to balance REG_LOCAL_IRQ_SAVE above */
70 REG_LOCAL_IRQ_RESTORE;
71 }
72}
73
74/* This function must run from internal memory */
75void chipcHw_reset_run_from_aram(void)
76{
77/* Make sure, pipeline is filled with instructions coming from ARAM */
78__asm (" nop \n\t"
79 " nop \n\t"
80#if defined(__KERNEL__) && !defined(STANDALONE)
81 " MRC p15,#0x0,r0,c1,c0,#0 \n\t"
82 " BIC r0,r0,#0xd \n\t"
83 " MCR p15,#0x0,r0,c1,c0,#0 \n\t"
84 " nop \n\t"
85 " nop \n\t"
86 " nop \n\t"
87 " nop \n\t"
88 " nop \n\t"
89 " nop \n\t"
90#endif
91 " nop \n\t"
92 " nop \n\t"
93/* Bypass the ARM clock and switch to XTAL clock */
94 " MOV r2,#0x80000000 \n\t"
95 " LDR r3,[r2,#8] \n\t"
96 " ORR r3,r3,#0x20000 \n\t"
97 " STR r3,[r2,#8] \n\t"
98
99 " nop \n\t"
100 " nop \n\t"
101 " nop \n\t"
102 " nop \n\t"
103 " nop \n\t"
104 " nop \n\t"
105 " nop \n\t"
106 " nop \n\t"
107 " nop \n\t"
108 " nop \n\t"
109 " nop \n\t"
110 " nop \n\t"
111 " nop \n\t"
112 " nop \n\t"
113 " nop \n\t"
114 " nop \n\t"
115 " nop \n\t"
116 " nop \n\t"
117 " nop \n\t"
118 " nop \n\t"
119/* Issue reset */
120 " MOV r3,#0x2 \n\t"
121 " STR r3,[r2,#0x80] \n\t"
122/* End here */
123 " MOV pc,pc \n\t");
124/* 0xe1a0f00f == asm ("mov r15, r15"); */
125}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
deleted file mode 100644
index 54ad964fe94c..000000000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
+++ /dev/null
@@ -1,64 +0,0 @@
1/*****************************************************************************
2* Copyright 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14/****************************************************************************/
15/**
16* @file chipcHw_str.c
17*
18* @brief Contains strings which are useful to linux and csp
19*
20* @note
21*/
22/****************************************************************************/
23
24/* ---- Include Files ---------------------------------------------------- */
25
26#include <mach/csp/chipcHw_inline.h>
27
28/* ---- Private Constants and Types --------------------------------------- */
29
30static const char *gMuxStr[] = {
31 "GPIO", /* 0 */
32 "KeyPad", /* 1 */
33 "I2C-Host", /* 2 */
34 "SPI", /* 3 */
35 "Uart", /* 4 */
36 "LED-Mtx-P", /* 5 */
37 "LED-Mtx-S", /* 6 */
38 "SDIO-0", /* 7 */
39 "SDIO-1", /* 8 */
40 "PCM", /* 9 */
41 "I2S", /* 10 */
42 "ETM", /* 11 */
43 "Debug", /* 12 */
44 "Misc", /* 13 */
45 "0xE", /* 14 */
46 "0xF", /* 15 */
47};
48
49/****************************************************************************/
50/**
51* @brief Retrieves a string representation of the mux setting for a pin.
52*
53* @return Pointer to a character string.
54*/
55/****************************************************************************/
56
57const char *chipcHw_getGpioPinFunctionStr(int pin)
58{
59 if ((pin < 0) || (pin >= chipcHw_GPIO_COUNT)) {
60 return "";
61 }
62
63 return gMuxStr[chipcHw_getGpioPinFunction(pin)];
64}
diff --git a/arch/arm/mach-bcmring/csp/dmac/Makefile b/arch/arm/mach-bcmring/csp/dmac/Makefile
deleted file mode 100644
index fb1104fe56b2..000000000000
--- a/arch/arm/mach-bcmring/csp/dmac/Makefile
+++ /dev/null
@@ -1 +0,0 @@
1obj-y += dmacHw.o dmacHw_extra.o \ No newline at end of file
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
deleted file mode 100644
index 547f746c7ff4..000000000000
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
+++ /dev/null
@@ -1,916 +0,0 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file dmacHw.c
18*
19* @brief Low level DMA controller driver routines
20*
21* @note
22*
23* These routines provide basic DMA functionality only.
24*/
25/****************************************************************************/
26
27/* ---- Include Files ---------------------------------------------------- */
28#include <linux/types.h>
29#include <linux/string.h>
30#include <linux/stddef.h>
31
32#include <mach/csp/dmacHw.h>
33#include <mach/csp/dmacHw_reg.h>
34#include <mach/csp/dmacHw_priv.h>
35#include <mach/csp/chipcHw_inline.h>
36
37/* ---- External Function Prototypes ------------------------------------- */
38
39/* Allocate DMA control blocks */
40dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT];
41
42uint32_t dmaChannelCount_0 = dmacHw_MAX_CHANNEL_COUNT / 2;
43uint32_t dmaChannelCount_1 = dmacHw_MAX_CHANNEL_COUNT / 2;
44
45/****************************************************************************/
46/**
47* @brief Get maximum FIFO for a DMA channel
48*
49* @return Maximum allowable FIFO size
50*
51*
52*/
53/****************************************************************************/
54static uint32_t GetFifoSize(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
55 ) {
56 uint32_t val = 0;
57 dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
58 dmacHw_MISC_t __iomem *pMiscReg = (void __iomem *)dmacHw_REG_MISC_BASE(pCblk->module);
59
60 switch (pCblk->channel) {
61 case 0:
62 val = (readl(&pMiscReg->CompParm2.lo) & 0x70000000) >> 28;
63 break;
64 case 1:
65 val = (readl(&pMiscReg->CompParm3.hi) & 0x70000000) >> 28;
66 break;
67 case 2:
68 val = (readl(&pMiscReg->CompParm3.lo) & 0x70000000) >> 28;
69 break;
70 case 3:
71 val = (readl(&pMiscReg->CompParm4.hi) & 0x70000000) >> 28;
72 break;
73 case 4:
74 val = (readl(&pMiscReg->CompParm4.lo) & 0x70000000) >> 28;
75 break;
76 case 5:
77 val = (readl(&pMiscReg->CompParm5.hi) & 0x70000000) >> 28;
78 break;
79 case 6:
80 val = (readl(&pMiscReg->CompParm5.lo) & 0x70000000) >> 28;
81 break;
82 case 7:
83 val = (readl(&pMiscReg->CompParm6.hi) & 0x70000000) >> 28;
84 break;
85 }
86
87 if (val <= 0x4) {
88 return 8 << val;
89 } else {
90 dmacHw_ASSERT(0);
91 }
92 return 0;
93}
94
95/****************************************************************************/
96/**
97* @brief Program channel register to initiate transfer
98*
99* @return void
100*
101*
102* @note
103* - Descriptor buffer MUST ALWAYS be flushed before calling this function
104* - This function should also be called from ISR to program the channel with
105* pending descriptors
106*/
107/****************************************************************************/
108void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
109 dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
110 void *pDescriptor /* [ IN ] Descriptor buffer */
111 ) {
112 dmacHw_DESC_RING_t *pRing;
113 dmacHw_DESC_t *pProg;
114 dmacHw_CBLK_t *pCblk;
115
116 pCblk = dmacHw_HANDLE_TO_CBLK(handle);
117 pRing = dmacHw_GET_DESC_RING(pDescriptor);
118
119 if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
120 /* Not safe yet to program the channel */
121 return;
122 }
123
124 if (pCblk->varDataStarted) {
125 if (pCblk->descUpdated) {
126 pCblk->descUpdated = 0;
127 pProg =
128 (dmacHw_DESC_t *) ((uint32_t)
129 dmacHw_REG_LLP(pCblk->module,
130 pCblk->channel) +
131 pRing->virt2PhyOffset);
132
133 /* Load descriptor if not loaded */
134 if (!(pProg->ctl.hi & dmacHw_REG_CTL_DONE)) {
135 dmacHw_SET_SAR(pCblk->module, pCblk->channel,
136 pProg->sar);
137 dmacHw_SET_DAR(pCblk->module, pCblk->channel,
138 pProg->dar);
139 dmacHw_REG_CTL_LO(pCblk->module,
140 pCblk->channel) =
141 pProg->ctl.lo;
142 dmacHw_REG_CTL_HI(pCblk->module,
143 pCblk->channel) =
144 pProg->ctl.hi;
145 } else if (pProg == (dmacHw_DESC_t *) pRing->pEnd->llp) {
146 /* Return as end descriptor is processed */
147 return;
148 } else {
149 dmacHw_ASSERT(0);
150 }
151 } else {
152 return;
153 }
154 } else {
155 if (pConfig->transferMode == dmacHw_TRANSFER_MODE_PERIODIC) {
156 /* Do not make a single chain, rather process one descriptor at a time */
157 pProg = pRing->pHead;
158 /* Point to the next descriptor for next iteration */
159 dmacHw_NEXT_DESC(pRing, pHead);
160 } else {
161 /* Return if no more pending descriptor */
162 if (pRing->pEnd == NULL) {
163 return;
164 }
165
166 pProg = pRing->pProg;
167 if (pConfig->transferMode ==
168 dmacHw_TRANSFER_MODE_CONTINUOUS) {
169 /* Make sure a complete ring can be formed */
170 dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pEnd->
171 llp == pRing->pProg);
172 /* Make sure pProg pointing to the pHead */
173 dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pProg ==
174 pRing->pHead);
175 /* Make a complete ring */
176 do {
177 pRing->pProg->ctl.lo |=
178 (dmacHw_REG_CTL_LLP_DST_EN |
179 dmacHw_REG_CTL_LLP_SRC_EN);
180 pRing->pProg =
181 (dmacHw_DESC_t *) pRing->pProg->llp;
182 } while (pRing->pProg != pRing->pHead);
183 } else {
184 /* Make a single long chain */
185 while (pRing->pProg != pRing->pEnd) {
186 pRing->pProg->ctl.lo |=
187 (dmacHw_REG_CTL_LLP_DST_EN |
188 dmacHw_REG_CTL_LLP_SRC_EN);
189 pRing->pProg =
190 (dmacHw_DESC_t *) pRing->pProg->llp;
191 }
192 }
193 }
194
195 /* Program the channel registers */
196 dmacHw_SET_SAR(pCblk->module, pCblk->channel, pProg->sar);
197 dmacHw_SET_DAR(pCblk->module, pCblk->channel, pProg->dar);
198 dmacHw_SET_LLP(pCblk->module, pCblk->channel,
199 (uint32_t) pProg - pRing->virt2PhyOffset);
200 dmacHw_REG_CTL_LO(pCblk->module, pCblk->channel) =
201 pProg->ctl.lo;
202 dmacHw_REG_CTL_HI(pCblk->module, pCblk->channel) =
203 pProg->ctl.hi;
204 if (pRing->pEnd) {
205 /* Remember the descriptor to use next */
206 pRing->pProg = (dmacHw_DESC_t *) pRing->pEnd->llp;
207 }
208 /* Indicate no more pending descriptor */
209 pRing->pEnd = (dmacHw_DESC_t *) NULL;
210 }
211 /* Start DMA operation */
212 dmacHw_DMA_START(pCblk->module, pCblk->channel);
213}
214
215/****************************************************************************/
216/**
217* @brief Initializes DMA
218*
219* This function initializes DMA CSP driver
220*
221* @note
222* Must be called before using any DMA channel
223*/
224/****************************************************************************/
225void dmacHw_initDma(void)
226{
227
228 uint32_t i = 0;
229
230 dmaChannelCount_0 = dmacHw_GET_NUM_CHANNEL(0);
231 dmaChannelCount_1 = dmacHw_GET_NUM_CHANNEL(1);
232
233 /* Enable access to the DMA block */
234 chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC0);
235 chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC1);
236
237 if ((dmaChannelCount_0 + dmaChannelCount_1) > dmacHw_MAX_CHANNEL_COUNT) {
238 dmacHw_ASSERT(0);
239 }
240
241 memset((void *)dmacHw_gCblk, 0,
242 sizeof(dmacHw_CBLK_t) * (dmaChannelCount_0 + dmaChannelCount_1));
243 for (i = 0; i < dmaChannelCount_0; i++) {
244 dmacHw_gCblk[i].module = 0;
245 dmacHw_gCblk[i].channel = i;
246 }
247 for (i = 0; i < dmaChannelCount_1; i++) {
248 dmacHw_gCblk[i + dmaChannelCount_0].module = 1;
249 dmacHw_gCblk[i + dmaChannelCount_0].channel = i;
250 }
251}
252
253/****************************************************************************/
254/**
255* @brief Exit function for DMA
256*
257* This function isolates DMA from the system
258*
259*/
260/****************************************************************************/
261void dmacHw_exitDma(void)
262{
263 /* Disable access to the DMA block */
264 chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC0);
265 chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC1);
266}
267
268/****************************************************************************/
269/**
270* @brief Gets a handle to a DMA channel
271*
272* This function returns a handle, representing a control block of a particular DMA channel
273*
274* @return -1 - On Failure
275* handle - On Success, representing a channel control block
276*
277* @note
278* None Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro
279*/
280/****************************************************************************/
281dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId /* [ IN ] DMA Channel Id */
282 ) {
283 int idx;
284
285 switch ((channelId >> 8)) {
286 case 0:
287 dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_0);
288 idx = (channelId & 0xff);
289 break;
290 case 1:
291 dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_1);
292 idx = dmaChannelCount_0 + (channelId & 0xff);
293 break;
294 default:
295 dmacHw_ASSERT(0);
296 return (dmacHw_HANDLE_t) -1;
297 }
298
299 return dmacHw_CBLK_TO_HANDLE(&dmacHw_gCblk[idx]);
300}
301
302/****************************************************************************/
303/**
304* @brief Initializes a DMA channel for use
305*
306* This function initializes and resets a DMA channel for use
307*
308* @return -1 - On Failure
309* 0 - On Success
310*
311* @note
312* None
313*/
314/****************************************************************************/
315int dmacHw_initChannel(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
316 ) {
317 dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
318 int module = pCblk->module;
319 int channel = pCblk->channel;
320
321 /* Reinitialize the control block */
322 memset((void *)pCblk, 0, sizeof(dmacHw_CBLK_t));
323 pCblk->module = module;
324 pCblk->channel = channel;
325
326 /* Enable DMA controller */
327 dmacHw_DMA_ENABLE(pCblk->module);
328 /* Reset DMA channel */
329 dmacHw_RESET_CONTROL_LO(pCblk->module, pCblk->channel);
330 dmacHw_RESET_CONTROL_HI(pCblk->module, pCblk->channel);
331 dmacHw_RESET_CONFIG_LO(pCblk->module, pCblk->channel);
332 dmacHw_RESET_CONFIG_HI(pCblk->module, pCblk->channel);
333
334 /* Clear all raw interrupt status */
335 dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
336 dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
337 dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
338
339 /* Mask event specific interrupts */
340 dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
341 dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
342 dmacHw_STRAN_INT_DISABLE(pCblk->module, pCblk->channel);
343 dmacHw_DTRAN_INT_DISABLE(pCblk->module, pCblk->channel);
344 dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
345
346 return 0;
347}
348
349/****************************************************************************/
350/**
351* @brief Finds amount of memory required to form a descriptor ring
352*
353*
354* @return Number of bytes required to form a descriptor ring
355*
356*
357*/
358/****************************************************************************/
359uint32_t dmacHw_descriptorLen(uint32_t descCnt /* [ IN ] Number of descriptor in the ring */
360 ) {
361 /* Need extra 4 byte to ensure 32 bit alignment */
362 return (descCnt * sizeof(dmacHw_DESC_t)) + sizeof(dmacHw_DESC_RING_t) +
363 sizeof(uint32_t);
364}
365
366/****************************************************************************/
367/**
368* @brief Initializes descriptor ring
369*
370* This function will initializes the descriptor ring of a DMA channel
371*
372*
373* @return -1 - On failure
374* 0 - On success
375* @note
376* - "len" parameter should be obtained from "dmacHw_descriptorLen"
377* - Descriptor buffer MUST be 32 bit aligned and uncached as it is
378* accessed by ARM and DMA
379*/
380/****************************************************************************/
381int dmacHw_initDescriptor(void *pDescriptorVirt, /* [ IN ] Virtual address of uncahced buffer allocated to form descriptor ring */
382 uint32_t descriptorPhyAddr, /* [ IN ] Physical address of pDescriptorVirt (descriptor buffer) */
383 uint32_t len, /* [ IN ] Size of the pBuf */
384 uint32_t num /* [ IN ] Number of descriptor in the ring */
385 ) {
386 uint32_t i;
387 dmacHw_DESC_RING_t *pRing;
388 dmacHw_DESC_t *pDesc;
389
390 /* Check the alignment of the descriptor */
391 if ((uint32_t) pDescriptorVirt & 0x00000003) {
392 dmacHw_ASSERT(0);
393 return -1;
394 }
395
396 /* Check if enough space has been allocated for descriptor ring */
397 if (len < dmacHw_descriptorLen(num)) {
398 return -1;
399 }
400
401 pRing = dmacHw_GET_DESC_RING(pDescriptorVirt);
402 pRing->pHead =
403 (dmacHw_DESC_t *) ((uint32_t) pRing + sizeof(dmacHw_DESC_RING_t));
404 pRing->pFree = pRing->pTail = pRing->pEnd = pRing->pHead;
405 pRing->pProg = dmacHw_DESC_INIT;
406 /* Initialize link item chain, starting from the head */
407 pDesc = pRing->pHead;
408 /* Find the offset between virtual to physical address */
409 pRing->virt2PhyOffset = (uint32_t) pDescriptorVirt - descriptorPhyAddr;
410
411 /* Form the descriptor ring */
412 for (i = 0; i < num - 1; i++) {
413 /* Clear link list item */
414 memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t));
415 /* Point to the next item in the physical address */
416 pDesc->llpPhy = (uint32_t) (pDesc + 1) - pRing->virt2PhyOffset;
417 /* Point to the next item in the virtual address */
418 pDesc->llp = (uint32_t) (pDesc + 1);
419 /* Mark descriptor is ready to use */
420 pDesc->ctl.hi = dmacHw_DESC_FREE;
421 /* Look into next link list item */
422 pDesc++;
423 }
424
425 /* Clear last link list item */
426 memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t));
427 /* Last item pointing to the first item in the
428 physical address to complete the ring */
429 pDesc->llpPhy = (uint32_t) pRing->pHead - pRing->virt2PhyOffset;
430 /* Last item pointing to the first item in the
431 virtual address to complete the ring
432 */
433 pDesc->llp = (uint32_t) pRing->pHead;
434 /* Mark descriptor is ready to use */
435 pDesc->ctl.hi = dmacHw_DESC_FREE;
436 /* Set the number of descriptors in the ring */
437 pRing->num = num;
438 return 0;
439}
440
441/****************************************************************************/
442/**
443* @brief Configure DMA channel
444*
445* @return 0 : On success
446* -1 : On failure
447*/
448/****************************************************************************/
449int dmacHw_configChannel(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
450 dmacHw_CONFIG_t *pConfig /* [ IN ] Configuration settings */
451 ) {
452 dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
453 uint32_t cfgHigh = 0;
454 int srcTrSize;
455 int dstTrSize;
456
457 pCblk->varDataStarted = 0;
458 pCblk->userData = NULL;
459
460 /* Configure
461 - Burst transaction when enough data in available in FIFO
462 - AHB Access protection 1
463 - Source and destination peripheral ports
464 */
465 cfgHigh =
466 dmacHw_REG_CFG_HI_FIFO_ENOUGH | dmacHw_REG_CFG_HI_AHB_HPROT_1 |
467 dmacHw_SRC_PERI_INTF(pConfig->
468 srcPeripheralPort) |
469 dmacHw_DST_PERI_INTF(pConfig->dstPeripheralPort);
470 /* Set priority */
471 dmacHw_SET_CHANNEL_PRIORITY(pCblk->module, pCblk->channel,
472 pConfig->channelPriority);
473
474 if (pConfig->dstStatusRegisterAddress != 0) {
475 /* Destination status update enable */
476 cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_DST_STAT;
477 /* Configure status registers */
478 dmacHw_SET_DSTATAR(pCblk->module, pCblk->channel,
479 pConfig->dstStatusRegisterAddress);
480 }
481
482 if (pConfig->srcStatusRegisterAddress != 0) {
483 /* Source status update enable */
484 cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_SRC_STAT;
485 /* Source status update enable */
486 dmacHw_SET_SSTATAR(pCblk->module, pCblk->channel,
487 pConfig->srcStatusRegisterAddress);
488 }
489 /* Configure the config high register */
490 dmacHw_GET_CONFIG_HI(pCblk->module, pCblk->channel) = cfgHigh;
491
492 /* Clear all raw interrupt status */
493 dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
494 dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
495 dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
496
497 /* Configure block interrupt */
498 if (pConfig->blockTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
499 dmacHw_BLOCK_INT_ENABLE(pCblk->module, pCblk->channel);
500 } else {
501 dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
502 }
503 /* Configure complete transfer interrupt */
504 if (pConfig->completeTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
505 dmacHw_TRAN_INT_ENABLE(pCblk->module, pCblk->channel);
506 } else {
507 dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
508 }
509 /* Configure error interrupt */
510 if (pConfig->errorInterrupt == dmacHw_INTERRUPT_ENABLE) {
511 dmacHw_ERROR_INT_ENABLE(pCblk->module, pCblk->channel);
512 } else {
513 dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
514 }
515 /* Configure gather register */
516 if (pConfig->srcGatherWidth) {
517 srcTrSize =
518 dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
519 if (!
520 ((pConfig->srcGatherWidth % srcTrSize)
521 && (pConfig->srcGatherJump % srcTrSize))) {
522 dmacHw_REG_SGR_LO(pCblk->module, pCblk->channel) =
523 ((pConfig->srcGatherWidth /
524 srcTrSize) << 20) | (pConfig->srcGatherJump /
525 srcTrSize);
526 } else {
527 return -1;
528 }
529 }
530 /* Configure scatter register */
531 if (pConfig->dstScatterWidth) {
532 dstTrSize =
533 dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
534 if (!
535 ((pConfig->dstScatterWidth % dstTrSize)
536 && (pConfig->dstScatterJump % dstTrSize))) {
537 dmacHw_REG_DSR_LO(pCblk->module, pCblk->channel) =
538 ((pConfig->dstScatterWidth /
539 dstTrSize) << 20) | (pConfig->dstScatterJump /
540 dstTrSize);
541 } else {
542 return -1;
543 }
544 }
545 return 0;
546}
547
548/****************************************************************************/
549/**
550* @brief Indicates whether DMA transfer is in progress or completed
551*
552* @return DMA transfer status
553* dmacHw_TRANSFER_STATUS_BUSY: DMA Transfer ongoing
554* dmacHw_TRANSFER_STATUS_DONE: DMA Transfer completed
555* dmacHw_TRANSFER_STATUS_ERROR: DMA Transfer error
556*
557*/
558/****************************************************************************/
559dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
560 ) {
561 dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
562
563 if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
564 return dmacHw_TRANSFER_STATUS_BUSY;
565 } else if (dmacHw_REG_INT_RAW_ERROR(pCblk->module) &
566 (0x00000001 << pCblk->channel)) {
567 return dmacHw_TRANSFER_STATUS_ERROR;
568 }
569
570 return dmacHw_TRANSFER_STATUS_DONE;
571}
572
573/****************************************************************************/
574/**
575* @brief Set descriptors for known data length
576*
577* When DMA has to work as a flow controller, this function prepares the
578* descriptor chain to transfer data
579*
580* from:
581* - Memory to memory
582* - Peripheral to memory
583* - Memory to Peripheral
584* - Peripheral to Peripheral
585*
586* @return -1 - On failure
587* 0 - On success
588*
589*/
590/****************************************************************************/
591int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
592 void *pDescriptor, /* [ IN ] Descriptor buffer */
593 void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */
594 void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */
595 size_t dataLen /* [ IN ] Data length in bytes */
596 ) {
597 dmacHw_TRANSACTION_WIDTH_e dstTrWidth;
598 dmacHw_TRANSACTION_WIDTH_e srcTrWidth;
599 dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
600 dmacHw_DESC_t *pStart;
601 dmacHw_DESC_t *pProg;
602 int srcTs = 0;
603 int blkTs = 0;
604 int oddSize = 0;
605 int descCount = 0;
606 int count = 0;
607 int dstTrSize = 0;
608 int srcTrSize = 0;
609 uint32_t maxBlockSize = dmacHw_MAX_BLOCKSIZE;
610
611 dstTrSize = dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
612 srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
613
614 /* Skip Tx if buffer is NULL or length is unknown */
615 if ((pSrcAddr == NULL) || (pDstAddr == NULL) || (dataLen == 0)) {
616 /* Do not initiate transfer */
617 return -1;
618 }
619
620 /* Ensure scatter and gather are transaction aligned */
621 if ((pConfig->srcGatherWidth % srcTrSize)
622 || (pConfig->dstScatterWidth % dstTrSize)) {
623 return -2;
624 }
625
626 /*
627 Background 1: DMAC can not perform DMA if source and destination addresses are
628 not properly aligned with the channel's transaction width. So, for successful
629 DMA transfer, transaction width must be set according to the alignment of the
630 source and destination address.
631 */
632
633 /* Adjust destination transaction width if destination address is not aligned properly */
634 dstTrWidth = pConfig->dstMaxTransactionWidth;
635 while (dmacHw_ADDRESS_MASK(dstTrSize) & (uint32_t) pDstAddr) {
636 dstTrWidth = dmacHw_GetNextTrWidth(dstTrWidth);
637 dstTrSize = dmacHw_GetTrWidthInBytes(dstTrWidth);
638 }
639
640 /* Adjust source transaction width if source address is not aligned properly */
641 srcTrWidth = pConfig->srcMaxTransactionWidth;
642 while (dmacHw_ADDRESS_MASK(srcTrSize) & (uint32_t) pSrcAddr) {
643 srcTrWidth = dmacHw_GetNextTrWidth(srcTrWidth);
644 srcTrSize = dmacHw_GetTrWidthInBytes(srcTrWidth);
645 }
646
647 /* Find the maximum transaction per descriptor */
648 if (pConfig->maxDataPerBlock
649 && ((pConfig->maxDataPerBlock / srcTrSize) <
650 dmacHw_MAX_BLOCKSIZE)) {
651 maxBlockSize = pConfig->maxDataPerBlock / srcTrSize;
652 }
653
654 /* Find number of source transactions needed to complete the DMA transfer */
655 srcTs = dataLen / srcTrSize;
656 /* Find the odd number of bytes that need to be transferred as single byte transaction width */
657 if (srcTs && (dstTrSize > srcTrSize)) {
658 oddSize = dataLen % dstTrSize;
659 /* Adjust source transaction count due to "oddSize" */
660 srcTs = srcTs - (oddSize / srcTrSize);
661 } else {
662 oddSize = dataLen % srcTrSize;
663 }
664 /* Adjust "descCount" due to "oddSize" */
665 if (oddSize) {
666 descCount++;
667 }
668 /* Find the number of descriptor needed for total "srcTs" */
669 if (srcTs) {
670 descCount += ((srcTs - 1) / maxBlockSize) + 1;
671 }
672
673 /* Check the availability of "descCount" discriptors in the ring */
674 pProg = pRing->pHead;
675 for (count = 0; (descCount <= pRing->num) && (count < descCount);
676 count++) {
677 if ((pProg->ctl.hi & dmacHw_DESC_FREE) == 0) {
678 /* Sufficient descriptors are not available */
679 return -3;
680 }
681 pProg = (dmacHw_DESC_t *) pProg->llp;
682 }
683
684 /* Remember the link list item to program the channel registers */
685 pStart = pProg = pRing->pHead;
686 /* Make a link list with "descCount(=count)" number of descriptors */
687 while (count) {
688 /* Reset channel control information */
689 pProg->ctl.lo = 0;
690 /* Enable source gather if configured */
691 if (pConfig->srcGatherWidth) {
692 pProg->ctl.lo |= dmacHw_REG_CTL_SG_ENABLE;
693 }
694 /* Enable destination scatter if configured */
695 if (pConfig->dstScatterWidth) {
696 pProg->ctl.lo |= dmacHw_REG_CTL_DS_ENABLE;
697 }
698 /* Set source and destination address */
699 pProg->sar = (uint32_t) pSrcAddr;
700 pProg->dar = (uint32_t) pDstAddr;
701 /* Use "devCtl" to mark that user memory need to be freed later if needed */
702 if (pProg == pRing->pHead) {
703 pProg->devCtl = dmacHw_FREE_USER_MEMORY;
704 } else {
705 pProg->devCtl = 0;
706 }
707
708 blkTs = srcTs;
709
710 /* Special treatmeant for last descriptor */
711 if (count == 1) {
712 /* Mark the last descriptor */
713 pProg->ctl.lo &=
714 ~(dmacHw_REG_CTL_LLP_DST_EN |
715 dmacHw_REG_CTL_LLP_SRC_EN);
716 /* Treatment for odd data bytes */
717 if (oddSize) {
718 /* Adjust for single byte transaction width */
719 switch (pConfig->transferType) {
720 case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
721 dstTrWidth =
722 dmacHw_DST_TRANSACTION_WIDTH_8;
723 blkTs =
724 (oddSize / srcTrSize) +
725 ((oddSize % srcTrSize) ? 1 : 0);
726 break;
727 case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
728 srcTrWidth =
729 dmacHw_SRC_TRANSACTION_WIDTH_8;
730 blkTs = oddSize;
731 break;
732 case dmacHw_TRANSFER_TYPE_MEM_TO_MEM:
733 srcTrWidth =
734 dmacHw_SRC_TRANSACTION_WIDTH_8;
735 dstTrWidth =
736 dmacHw_DST_TRANSACTION_WIDTH_8;
737 blkTs = oddSize;
738 break;
739 case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL:
740 /* Do not adjust the transaction width */
741 break;
742 }
743 } else {
744 srcTs -= blkTs;
745 }
746 } else {
747 if (srcTs / maxBlockSize) {
748 blkTs = maxBlockSize;
749 }
750 /* Remaining source transactions for next iteration */
751 srcTs -= blkTs;
752 }
753 /* Must have a valid source transactions */
754 dmacHw_ASSERT(blkTs > 0);
755 /* Set control information */
756 if (pConfig->flowControler == dmacHw_FLOW_CONTROL_DMA) {
757 pProg->ctl.lo |= pConfig->transferType |
758 pConfig->srcUpdate |
759 pConfig->dstUpdate |
760 srcTrWidth |
761 dstTrWidth |
762 pConfig->srcMaxBurstWidth |
763 pConfig->dstMaxBurstWidth |
764 pConfig->srcMasterInterface |
765 pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
766 } else {
767 uint32_t transferType = 0;
768 switch (pConfig->transferType) {
769 case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
770 transferType = dmacHw_REG_CTL_TTFC_PM_PERI;
771 break;
772 case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
773 transferType = dmacHw_REG_CTL_TTFC_MP_PERI;
774 break;
775 default:
776 dmacHw_ASSERT(0);
777 }
778 pProg->ctl.lo |= transferType |
779 pConfig->srcUpdate |
780 pConfig->dstUpdate |
781 srcTrWidth |
782 dstTrWidth |
783 pConfig->srcMaxBurstWidth |
784 pConfig->dstMaxBurstWidth |
785 pConfig->srcMasterInterface |
786 pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
787 }
788
789 /* Set block transaction size */
790 pProg->ctl.hi = blkTs & dmacHw_REG_CTL_BLOCK_TS_MASK;
791 /* Look for next descriptor */
792 if (count > 1) {
793 /* Point to the next descriptor */
794 pProg = (dmacHw_DESC_t *) pProg->llp;
795
796 /* Update source and destination address for next iteration */
797 switch (pConfig->transferType) {
798 case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
799 if (pConfig->dstScatterWidth) {
800 pDstAddr =
801 (char *)pDstAddr +
802 blkTs * srcTrSize +
803 (((blkTs * srcTrSize) /
804 pConfig->dstScatterWidth) *
805 pConfig->dstScatterJump);
806 } else {
807 pDstAddr =
808 (char *)pDstAddr +
809 blkTs * srcTrSize;
810 }
811 break;
812 case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
813 if (pConfig->srcGatherWidth) {
814 pSrcAddr =
815 (char *)pDstAddr +
816 blkTs * srcTrSize +
817 (((blkTs * srcTrSize) /
818 pConfig->srcGatherWidth) *
819 pConfig->srcGatherJump);
820 } else {
821 pSrcAddr =
822 (char *)pSrcAddr +
823 blkTs * srcTrSize;
824 }
825 break;
826 case dmacHw_TRANSFER_TYPE_MEM_TO_MEM:
827 if (pConfig->dstScatterWidth) {
828 pDstAddr =
829 (char *)pDstAddr +
830 blkTs * srcTrSize +
831 (((blkTs * srcTrSize) /
832 pConfig->dstScatterWidth) *
833 pConfig->dstScatterJump);
834 } else {
835 pDstAddr =
836 (char *)pDstAddr +
837 blkTs * srcTrSize;
838 }
839
840 if (pConfig->srcGatherWidth) {
841 pSrcAddr =
842 (char *)pDstAddr +
843 blkTs * srcTrSize +
844 (((blkTs * srcTrSize) /
845 pConfig->srcGatherWidth) *
846 pConfig->srcGatherJump);
847 } else {
848 pSrcAddr =
849 (char *)pSrcAddr +
850 blkTs * srcTrSize;
851 }
852 break;
853 case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL:
854 /* Do not adjust the address */
855 break;
856 default:
857 dmacHw_ASSERT(0);
858 }
859 } else {
860 /* At the end of transfer "srcTs" must be zero */
861 dmacHw_ASSERT(srcTs == 0);
862 }
863 count--;
864 }
865
866 /* Remember the descriptor to initialize the registers */
867 if (pRing->pProg == dmacHw_DESC_INIT) {
868 pRing->pProg = pStart;
869 }
870 /* Indicate that the descriptor is updated */
871 pRing->pEnd = pProg;
872 /* Head pointing to the next descriptor */
873 pRing->pHead = (dmacHw_DESC_t *) pProg->llp;
874 /* Update Tail pointer if destination is a peripheral,
875 because no one is going to read from the pTail
876 */
877 if (!dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
878 pRing->pTail = pRing->pHead;
879 }
880 return 0;
881}
882
883/****************************************************************************/
884/**
885* @brief Provides DMA controller attributes
886*
887*
888* @return DMA controller attributes
889*
890* @note
891* None
892*/
893/****************************************************************************/
894uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
895 dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controller attribute of type dmacHw_CONTROLLER_ATTRIB_e */
896 ) {
897 dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
898
899 switch (attr) {
900 case dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM:
901 return dmacHw_GET_NUM_CHANNEL(pCblk->module);
902 case dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE:
903 return (1 <<
904 (dmacHw_GET_MAX_BLOCK_SIZE
905 (pCblk->module, pCblk->module) + 2)) - 8;
906 case dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM:
907 return dmacHw_GET_NUM_INTERFACE(pCblk->module);
908 case dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH:
909 return 32 << dmacHw_GET_CHANNEL_DATA_WIDTH(pCblk->module,
910 pCblk->channel);
911 case dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE:
912 return GetFifoSize(handle);
913 }
914 dmacHw_ASSERT(0);
915 return 0;
916}
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
deleted file mode 100644
index fe438699d11e..000000000000
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
+++ /dev/null
@@ -1,1017 +0,0 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file dmacHw_extra.c
18*
19* @brief Extra Low level DMA controller driver routines
20*
21* @note
22*
23* These routines provide basic DMA functionality only.
24*/
25/****************************************************************************/
26
27/* ---- Include Files ---------------------------------------------------- */
28
29#include <linux/types.h>
30#include <linux/stddef.h>
31
32#include <mach/csp/dmacHw.h>
33#include <mach/csp/dmacHw_reg.h>
34#include <mach/csp/dmacHw_priv.h>
35
36extern dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT]; /* Declared in dmacHw.c */
37
38/* ---- External Function Prototypes ------------------------------------- */
39
40/* ---- Internal Use Function Prototypes --------------------------------- */
41/****************************************************************************/
42/**
43* @brief Overwrites data length in the descriptor
44*
45* This function overwrites data length in the descriptor
46*
47*
48* @return void
49*
50* @note
51* This is only used for PCM channel
52*/
53/****************************************************************************/
54void dmacHw_setDataLength(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
55 void *pDescriptor, /* [ IN ] Descriptor buffer */
56 size_t dataLen /* [ IN ] Data length in bytes */
57 );
58
59/****************************************************************************/
60/**
61* @brief Helper function to display DMA registers
62*
63* @return void
64*
65*
66* @note
67* None
68*/
69/****************************************************************************/
70static void DisplayRegisterContents(int module, /* [ IN ] DMA Controller unit (0-1) */
71 int channel, /* [ IN ] DMA Channel (0-7) / -1(all) */
72 int (*fpPrint) (const char *, ...) /* [ IN ] Callback to the print function */
73 ) {
74 int chan;
75
76 (*fpPrint) ("Displaying register content \n\n");
77 (*fpPrint) ("Module %d: Interrupt raw transfer 0x%X\n",
78 module, (uint32_t) (dmacHw_REG_INT_RAW_TRAN(module)));
79 (*fpPrint) ("Module %d: Interrupt raw block 0x%X\n",
80 module, (uint32_t) (dmacHw_REG_INT_RAW_BLOCK(module)));
81 (*fpPrint) ("Module %d: Interrupt raw src transfer 0x%X\n",
82 module, (uint32_t) (dmacHw_REG_INT_RAW_STRAN(module)));
83 (*fpPrint) ("Module %d: Interrupt raw dst transfer 0x%X\n",
84 module, (uint32_t) (dmacHw_REG_INT_RAW_DTRAN(module)));
85 (*fpPrint) ("Module %d: Interrupt raw error 0x%X\n",
86 module, (uint32_t) (dmacHw_REG_INT_RAW_ERROR(module)));
87 (*fpPrint) ("--------------------------------------------------\n");
88 (*fpPrint) ("Module %d: Interrupt stat transfer 0x%X\n",
89 module, (uint32_t) (dmacHw_REG_INT_STAT_TRAN(module)));
90 (*fpPrint) ("Module %d: Interrupt stat block 0x%X\n",
91 module, (uint32_t) (dmacHw_REG_INT_STAT_BLOCK(module)));
92 (*fpPrint) ("Module %d: Interrupt stat src transfer 0x%X\n",
93 module, (uint32_t) (dmacHw_REG_INT_STAT_STRAN(module)));
94 (*fpPrint) ("Module %d: Interrupt stat dst transfer 0x%X\n",
95 module, (uint32_t) (dmacHw_REG_INT_STAT_DTRAN(module)));
96 (*fpPrint) ("Module %d: Interrupt stat error 0x%X\n",
97 module, (uint32_t) (dmacHw_REG_INT_STAT_ERROR(module)));
98 (*fpPrint) ("--------------------------------------------------\n");
99 (*fpPrint) ("Module %d: Interrupt mask transfer 0x%X\n",
100 module, (uint32_t) (dmacHw_REG_INT_MASK_TRAN(module)));
101 (*fpPrint) ("Module %d: Interrupt mask block 0x%X\n",
102 module, (uint32_t) (dmacHw_REG_INT_MASK_BLOCK(module)));
103 (*fpPrint) ("Module %d: Interrupt mask src transfer 0x%X\n",
104 module, (uint32_t) (dmacHw_REG_INT_MASK_STRAN(module)));
105 (*fpPrint) ("Module %d: Interrupt mask dst transfer 0x%X\n",
106 module, (uint32_t) (dmacHw_REG_INT_MASK_DTRAN(module)));
107 (*fpPrint) ("Module %d: Interrupt mask error 0x%X\n",
108 module, (uint32_t) (dmacHw_REG_INT_MASK_ERROR(module)));
109 (*fpPrint) ("--------------------------------------------------\n");
110 (*fpPrint) ("Module %d: Interrupt clear transfer 0x%X\n",
111 module, (uint32_t) (dmacHw_REG_INT_CLEAR_TRAN(module)));
112 (*fpPrint) ("Module %d: Interrupt clear block 0x%X\n",
113 module, (uint32_t) (dmacHw_REG_INT_CLEAR_BLOCK(module)));
114 (*fpPrint) ("Module %d: Interrupt clear src transfer 0x%X\n",
115 module, (uint32_t) (dmacHw_REG_INT_CLEAR_STRAN(module)));
116 (*fpPrint) ("Module %d: Interrupt clear dst transfer 0x%X\n",
117 module, (uint32_t) (dmacHw_REG_INT_CLEAR_DTRAN(module)));
118 (*fpPrint) ("Module %d: Interrupt clear error 0x%X\n",
119 module, (uint32_t) (dmacHw_REG_INT_CLEAR_ERROR(module)));
120 (*fpPrint) ("--------------------------------------------------\n");
121 (*fpPrint) ("Module %d: SW source req 0x%X\n",
122 module, (uint32_t) (dmacHw_REG_SW_HS_SRC_REQ(module)));
123 (*fpPrint) ("Module %d: SW dest req 0x%X\n",
124 module, (uint32_t) (dmacHw_REG_SW_HS_DST_REQ(module)));
125 (*fpPrint) ("Module %d: SW source signal 0x%X\n",
126 module, (uint32_t) (dmacHw_REG_SW_HS_SRC_SGL_REQ(module)));
127 (*fpPrint) ("Module %d: SW dest signal 0x%X\n",
128 module, (uint32_t) (dmacHw_REG_SW_HS_DST_SGL_REQ(module)));
129 (*fpPrint) ("Module %d: SW source last 0x%X\n",
130 module, (uint32_t) (dmacHw_REG_SW_HS_SRC_LST_REQ(module)));
131 (*fpPrint) ("Module %d: SW dest last 0x%X\n",
132 module, (uint32_t) (dmacHw_REG_SW_HS_DST_LST_REQ(module)));
133 (*fpPrint) ("--------------------------------------------------\n");
134 (*fpPrint) ("Module %d: misc config 0x%X\n",
135 module, (uint32_t) (dmacHw_REG_MISC_CFG(module)));
136 (*fpPrint) ("Module %d: misc channel enable 0x%X\n",
137 module, (uint32_t) (dmacHw_REG_MISC_CH_ENABLE(module)));
138 (*fpPrint) ("Module %d: misc ID 0x%X\n",
139 module, (uint32_t) (dmacHw_REG_MISC_ID(module)));
140 (*fpPrint) ("Module %d: misc test 0x%X\n",
141 module, (uint32_t) (dmacHw_REG_MISC_TEST(module)));
142
143 if (channel == -1) {
144 for (chan = 0; chan < 8; chan++) {
145 (*fpPrint)
146 ("--------------------------------------------------\n");
147 (*fpPrint)
148 ("Module %d: Channel %d Source 0x%X\n",
149 module, chan,
150 (uint32_t) (dmacHw_REG_SAR(module, chan)));
151 (*fpPrint)
152 ("Module %d: Channel %d Destination 0x%X\n",
153 module, chan,
154 (uint32_t) (dmacHw_REG_DAR(module, chan)));
155 (*fpPrint)
156 ("Module %d: Channel %d LLP 0x%X\n",
157 module, chan,
158 (uint32_t) (dmacHw_REG_LLP(module, chan)));
159 (*fpPrint)
160 ("Module %d: Channel %d Control (LO) 0x%X\n",
161 module, chan,
162 (uint32_t) (dmacHw_REG_CTL_LO(module, chan)));
163 (*fpPrint)
164 ("Module %d: Channel %d Control (HI) 0x%X\n",
165 module, chan,
166 (uint32_t) (dmacHw_REG_CTL_HI(module, chan)));
167 (*fpPrint)
168 ("Module %d: Channel %d Source Stats 0x%X\n",
169 module, chan,
170 (uint32_t) (dmacHw_REG_SSTAT(module, chan)));
171 (*fpPrint)
172 ("Module %d: Channel %d Dest Stats 0x%X\n",
173 module, chan,
174 (uint32_t) (dmacHw_REG_DSTAT(module, chan)));
175 (*fpPrint)
176 ("Module %d: Channel %d Source Stats Addr 0x%X\n",
177 module, chan,
178 (uint32_t) (dmacHw_REG_SSTATAR(module, chan)));
179 (*fpPrint)
180 ("Module %d: Channel %d Dest Stats Addr 0x%X\n",
181 module, chan,
182 (uint32_t) (dmacHw_REG_DSTATAR(module, chan)));
183 (*fpPrint)
184 ("Module %d: Channel %d Config (LO) 0x%X\n",
185 module, chan,
186 (uint32_t) (dmacHw_REG_CFG_LO(module, chan)));
187 (*fpPrint)
188 ("Module %d: Channel %d Config (HI) 0x%X\n",
189 module, chan,
190 (uint32_t) (dmacHw_REG_CFG_HI(module, chan)));
191 }
192 } else {
193 chan = channel;
194 (*fpPrint)
195 ("--------------------------------------------------\n");
196 (*fpPrint)
197 ("Module %d: Channel %d Source 0x%X\n",
198 module, chan, (uint32_t) (dmacHw_REG_SAR(module, chan)));
199 (*fpPrint)
200 ("Module %d: Channel %d Destination 0x%X\n",
201 module, chan, (uint32_t) (dmacHw_REG_DAR(module, chan)));
202 (*fpPrint)
203 ("Module %d: Channel %d LLP 0x%X\n",
204 module, chan, (uint32_t) (dmacHw_REG_LLP(module, chan)));
205 (*fpPrint)
206 ("Module %d: Channel %d Control (LO) 0x%X\n",
207 module, chan,
208 (uint32_t) (dmacHw_REG_CTL_LO(module, chan)));
209 (*fpPrint)
210 ("Module %d: Channel %d Control (HI) 0x%X\n",
211 module, chan,
212 (uint32_t) (dmacHw_REG_CTL_HI(module, chan)));
213 (*fpPrint)
214 ("Module %d: Channel %d Source Stats 0x%X\n",
215 module, chan, (uint32_t) (dmacHw_REG_SSTAT(module, chan)));
216 (*fpPrint)
217 ("Module %d: Channel %d Dest Stats 0x%X\n",
218 module, chan, (uint32_t) (dmacHw_REG_DSTAT(module, chan)));
219 (*fpPrint)
220 ("Module %d: Channel %d Source Stats Addr 0x%X\n",
221 module, chan,
222 (uint32_t) (dmacHw_REG_SSTATAR(module, chan)));
223 (*fpPrint)
224 ("Module %d: Channel %d Dest Stats Addr 0x%X\n",
225 module, chan,
226 (uint32_t) (dmacHw_REG_DSTATAR(module, chan)));
227 (*fpPrint)
228 ("Module %d: Channel %d Config (LO) 0x%X\n",
229 module, chan,
230 (uint32_t) (dmacHw_REG_CFG_LO(module, chan)));
231 (*fpPrint)
232 ("Module %d: Channel %d Config (HI) 0x%X\n",
233 module, chan,
234 (uint32_t) (dmacHw_REG_CFG_HI(module, chan)));
235 }
236}
237
238/****************************************************************************/
239/**
240* @brief Helper function to display descriptor ring
241*
242* @return void
243*
244*
245* @note
246* None
247*/
248/****************************************************************************/
249static void DisplayDescRing(void *pDescriptor, /* [ IN ] Descriptor buffer */
250 int (*fpPrint) (const char *, ...) /* [ IN ] Callback to the print function */
251 ) {
252 dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
253 dmacHw_DESC_t *pStart;
254
255 if (pRing->pHead == NULL) {
256 return;
257 }
258
259 pStart = pRing->pHead;
260
261 while ((dmacHw_DESC_t *) pStart->llp != pRing->pHead) {
262 if (pStart == pRing->pHead) {
263 (*fpPrint) ("Head\n");
264 }
265 if (pStart == pRing->pTail) {
266 (*fpPrint) ("Tail\n");
267 }
268 if (pStart == pRing->pProg) {
269 (*fpPrint) ("Prog\n");
270 }
271 if (pStart == pRing->pEnd) {
272 (*fpPrint) ("End\n");
273 }
274 if (pStart == pRing->pFree) {
275 (*fpPrint) ("Free\n");
276 }
277 (*fpPrint) ("0x%X:\n", (uint32_t) pStart);
278 (*fpPrint) ("sar 0x%0X\n", pStart->sar);
279 (*fpPrint) ("dar 0x%0X\n", pStart->dar);
280 (*fpPrint) ("llp 0x%0X\n", pStart->llp);
281 (*fpPrint) ("ctl.lo 0x%0X\n", pStart->ctl.lo);
282 (*fpPrint) ("ctl.hi 0x%0X\n", pStart->ctl.hi);
283 (*fpPrint) ("sstat 0x%0X\n", pStart->sstat);
284 (*fpPrint) ("dstat 0x%0X\n", pStart->dstat);
285 (*fpPrint) ("devCtl 0x%0X\n", pStart->devCtl);
286
287 pStart = (dmacHw_DESC_t *) pStart->llp;
288 }
289 if (pStart == pRing->pHead) {
290 (*fpPrint) ("Head\n");
291 }
292 if (pStart == pRing->pTail) {
293 (*fpPrint) ("Tail\n");
294 }
295 if (pStart == pRing->pProg) {
296 (*fpPrint) ("Prog\n");
297 }
298 if (pStart == pRing->pEnd) {
299 (*fpPrint) ("End\n");
300 }
301 if (pStart == pRing->pFree) {
302 (*fpPrint) ("Free\n");
303 }
304 (*fpPrint) ("0x%X:\n", (uint32_t) pStart);
305 (*fpPrint) ("sar 0x%0X\n", pStart->sar);
306 (*fpPrint) ("dar 0x%0X\n", pStart->dar);
307 (*fpPrint) ("llp 0x%0X\n", pStart->llp);
308 (*fpPrint) ("ctl.lo 0x%0X\n", pStart->ctl.lo);
309 (*fpPrint) ("ctl.hi 0x%0X\n", pStart->ctl.hi);
310 (*fpPrint) ("sstat 0x%0X\n", pStart->sstat);
311 (*fpPrint) ("dstat 0x%0X\n", pStart->dstat);
312 (*fpPrint) ("devCtl 0x%0X\n", pStart->devCtl);
313}
314
315/****************************************************************************/
316/**
317* @brief Check if DMA channel is the flow controller
318*
319* @return 1 : If DMA is a flow controller
320* 0 : Peripheral is the flow controller
321*
322* @note
323* None
324*/
325/****************************************************************************/
326static inline int DmaIsFlowController(void *pDescriptor /* [ IN ] Descriptor buffer */
327 ) {
328 uint32_t ttfc =
329 (dmacHw_GET_DESC_RING(pDescriptor))->pTail->ctl.
330 lo & dmacHw_REG_CTL_TTFC_MASK;
331
332 switch (ttfc) {
333 case dmacHw_REG_CTL_TTFC_MM_DMAC:
334 case dmacHw_REG_CTL_TTFC_MP_DMAC:
335 case dmacHw_REG_CTL_TTFC_PM_DMAC:
336 case dmacHw_REG_CTL_TTFC_PP_DMAC:
337 return 1;
338 }
339
340 return 0;
341}
342
343/****************************************************************************/
344/**
345* @brief Overwrites data length in the descriptor
346*
347* This function overwrites data length in the descriptor
348*
349*
350* @return void
351*
352* @note
353* This is only used for PCM channel
354*/
355/****************************************************************************/
356void dmacHw_setDataLength(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
357 void *pDescriptor, /* [ IN ] Descriptor buffer */
358 size_t dataLen /* [ IN ] Data length in bytes */
359 ) {
360 dmacHw_DESC_t *pProg;
361 dmacHw_DESC_t *pHead;
362 int srcTs = 0;
363 int srcTrSize = 0;
364
365 pHead = (dmacHw_GET_DESC_RING(pDescriptor))->pHead;
366 pProg = pHead;
367
368 srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
369 srcTs = dataLen / srcTrSize;
370 do {
371 pProg->ctl.hi = srcTs & dmacHw_REG_CTL_BLOCK_TS_MASK;
372 pProg = (dmacHw_DESC_t *) pProg->llp;
373 } while (pProg != pHead);
374}
375
376/****************************************************************************/
377/**
378* @brief Clears the interrupt
379*
380* This function clears the DMA channel specific interrupt
381*
382*
383* @return void
384*
385* @note
386* Must be called under the context of ISR
387*/
388/****************************************************************************/
389void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
390 ) {
391 dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
392
393 dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
394 dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
395 dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
396}
397
398/****************************************************************************/
399/**
400* @brief Returns the cause of channel specific DMA interrupt
401*
402* This function returns the cause of interrupt
403*
404* @return Interrupt status, each bit representing a specific type of interrupt
405*
406* @note
407* Should be called under the context of ISR
408*/
409/****************************************************************************/
410dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
411 ) {
412 dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
413 dmacHw_INTERRUPT_STATUS_e status = dmacHw_INTERRUPT_STATUS_NONE;
414
415 if (dmacHw_REG_INT_STAT_TRAN(pCblk->module) &
416 ((0x00000001 << pCblk->channel))) {
417 status |= dmacHw_INTERRUPT_STATUS_TRANS;
418 }
419 if (dmacHw_REG_INT_STAT_BLOCK(pCblk->module) &
420 ((0x00000001 << pCblk->channel))) {
421 status |= dmacHw_INTERRUPT_STATUS_BLOCK;
422 }
423 if (dmacHw_REG_INT_STAT_ERROR(pCblk->module) &
424 ((0x00000001 << pCblk->channel))) {
425 status |= dmacHw_INTERRUPT_STATUS_ERROR;
426 }
427
428 return status;
429}
430
431/****************************************************************************/
432/**
433* @brief Indentifies a DMA channel causing interrupt
434*
435* This functions returns a channel causing interrupt of type dmacHw_INTERRUPT_STATUS_e
436*
437* @return NULL : No channel causing DMA interrupt
438* ! NULL : Handle to a channel causing DMA interrupt
439* @note
440* dmacHw_clearInterrupt() must be called with a valid handle after calling this function
441*/
442/****************************************************************************/
443dmacHw_HANDLE_t dmacHw_getInterruptSource(void)
444{
445 uint32_t i;
446
447 for (i = 0; i < dmaChannelCount_0 + dmaChannelCount_1; i++) {
448 if ((dmacHw_REG_INT_STAT_TRAN(dmacHw_gCblk[i].module) &
449 ((0x00000001 << dmacHw_gCblk[i].channel)))
450 || (dmacHw_REG_INT_STAT_BLOCK(dmacHw_gCblk[i].module) &
451 ((0x00000001 << dmacHw_gCblk[i].channel)))
452 || (dmacHw_REG_INT_STAT_ERROR(dmacHw_gCblk[i].module) &
453 ((0x00000001 << dmacHw_gCblk[i].channel)))
454 ) {
455 return dmacHw_CBLK_TO_HANDLE(&dmacHw_gCblk[i]);
456 }
457 }
458 return dmacHw_CBLK_TO_HANDLE(NULL);
459}
460
461/****************************************************************************/
462/**
463* @brief Estimates number of descriptor needed to perform certain DMA transfer
464*
465*
466* @return On failure : -1
467* On success : Number of descriptor count
468*
469*
470*/
471/****************************************************************************/
472int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
473 void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */
474 void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */
475 size_t dataLen /* [ IN ] Data length in bytes */
476 ) {
477 int srcTs = 0;
478 int oddSize = 0;
479 int descCount = 0;
480 int dstTrSize = 0;
481 int srcTrSize = 0;
482 uint32_t maxBlockSize = dmacHw_MAX_BLOCKSIZE;
483 dmacHw_TRANSACTION_WIDTH_e dstTrWidth;
484 dmacHw_TRANSACTION_WIDTH_e srcTrWidth;
485
486 dstTrSize = dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
487 srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
488
489 /* Skip Tx if buffer is NULL or length is unknown */
490 if ((pSrcAddr == NULL) || (pDstAddr == NULL) || (dataLen == 0)) {
491 /* Do not initiate transfer */
492 return -1;
493 }
494
495 /* Ensure scatter and gather are transaction aligned */
496 if (pConfig->srcGatherWidth % srcTrSize
497 || pConfig->dstScatterWidth % dstTrSize) {
498 return -1;
499 }
500
501 /*
502 Background 1: DMAC can not perform DMA if source and destination addresses are
503 not properly aligned with the channel's transaction width. So, for successful
504 DMA transfer, transaction width must be set according to the alignment of the
505 source and destination address.
506 */
507
508 /* Adjust destination transaction width if destination address is not aligned properly */
509 dstTrWidth = pConfig->dstMaxTransactionWidth;
510 while (dmacHw_ADDRESS_MASK(dstTrSize) & (uint32_t) pDstAddr) {
511 dstTrWidth = dmacHw_GetNextTrWidth(dstTrWidth);
512 dstTrSize = dmacHw_GetTrWidthInBytes(dstTrWidth);
513 }
514
515 /* Adjust source transaction width if source address is not aligned properly */
516 srcTrWidth = pConfig->srcMaxTransactionWidth;
517 while (dmacHw_ADDRESS_MASK(srcTrSize) & (uint32_t) pSrcAddr) {
518 srcTrWidth = dmacHw_GetNextTrWidth(srcTrWidth);
519 srcTrSize = dmacHw_GetTrWidthInBytes(srcTrWidth);
520 }
521
522 /* Find the maximum transaction per descriptor */
523 if (pConfig->maxDataPerBlock
524 && ((pConfig->maxDataPerBlock / srcTrSize) <
525 dmacHw_MAX_BLOCKSIZE)) {
526 maxBlockSize = pConfig->maxDataPerBlock / srcTrSize;
527 }
528
529 /* Find number of source transactions needed to complete the DMA transfer */
530 srcTs = dataLen / srcTrSize;
531 /* Find the odd number of bytes that need to be transferred as single byte transaction width */
532 if (srcTs && (dstTrSize > srcTrSize)) {
533 oddSize = dataLen % dstTrSize;
534 /* Adjust source transaction count due to "oddSize" */
535 srcTs = srcTs - (oddSize / srcTrSize);
536 } else {
537 oddSize = dataLen % srcTrSize;
538 }
539 /* Adjust "descCount" due to "oddSize" */
540 if (oddSize) {
541 descCount++;
542 }
543
544 /* Find the number of descriptor needed for total "srcTs" */
545 if (srcTs) {
546 descCount += ((srcTs - 1) / maxBlockSize) + 1;
547 }
548
549 return descCount;
550}
551
552/****************************************************************************/
553/**
554* @brief Check the existence of pending descriptor
555*
556* This function confirmes if there is any pending descriptor in the chain
557* to program the channel
558*
559* @return 1 : Channel need to be programmed with pending descriptor
560* 0 : No more pending descriptor to programe the channel
561*
562* @note
563* - This function should be called from ISR in case there are pending
564* descriptor to program the channel.
565*
566* Example:
567*
568* dmac_isr ()
569* {
570* ...
571* if (dmacHw_descriptorPending (handle))
572* {
573* dmacHw_initiateTransfer (handle);
574* }
575* }
576*
577*/
578/****************************************************************************/
579uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
580 void *pDescriptor /* [ IN ] Descriptor buffer */
581 ) {
582 dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
583 dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
584
585 /* Make sure channel is not busy */
586 if (!CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
587 /* Check if pEnd is not processed */
588 if (pRing->pEnd) {
589 /* Something left for processing */
590 return 1;
591 }
592 }
593 return 0;
594}
595
596/****************************************************************************/
597/**
598* @brief Program channel register to stop transfer
599*
600* Ensures the channel is not doing any transfer after calling this function
601*
602* @return void
603*
604*/
605/****************************************************************************/
606void dmacHw_stopTransfer(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
607 ) {
608 dmacHw_CBLK_t *pCblk;
609
610 pCblk = dmacHw_HANDLE_TO_CBLK(handle);
611
612 /* Stop the channel */
613 dmacHw_DMA_STOP(pCblk->module, pCblk->channel);
614}
615
616/****************************************************************************/
617/**
618* @brief Deallocates source or destination memory, allocated
619*
620* This function can be called to deallocate data memory that was DMAed successfully
621*
622* @return On failure : -1
623* On success : Number of buffer freed
624*
625* @note
626* This function will be called ONLY, when source OR destination address is pointing
627* to dynamic memory
628*/
629/****************************************************************************/
630int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
631 void *pDescriptor, /* [ IN ] Descriptor buffer */
632 void (*fpFree) (void *) /* [ IN ] Function pointer to free data memory */
633 ) {
634 dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
635 uint32_t count = 0;
636
637 if (fpFree == NULL) {
638 return -1;
639 }
640
641 while ((pRing->pFree != pRing->pTail)
642 && (pRing->pFree->ctl.lo & dmacHw_DESC_FREE)) {
643 if (pRing->pFree->devCtl == dmacHw_FREE_USER_MEMORY) {
644 /* Identify, which memory to free */
645 if (dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
646 (*fpFree) ((void *)pRing->pFree->dar);
647 } else {
648 /* Destination was a peripheral */
649 (*fpFree) ((void *)pRing->pFree->sar);
650 }
651 /* Unmark user memory to indicate it is freed */
652 pRing->pFree->devCtl = ~dmacHw_FREE_USER_MEMORY;
653 }
654 dmacHw_NEXT_DESC(pRing, pFree);
655
656 count++;
657 }
658
659 return count;
660}
661
662/****************************************************************************/
663/**
664* @brief Prepares descriptor ring, when source peripheral working as a flow controller
665*
666* This function will update the discriptor ring by allocating buffers, when source peripheral
667* has to work as a flow controller to transfer data from:
668* - Peripheral to memory.
669*
670* @return On failure : -1
671* On success : Number of descriptor updated
672*
673*
674* @note
675* Channel must be configured for peripheral to memory transfer
676*
677*/
678/****************************************************************************/
679int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
680 dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
681 void *pDescriptor, /* [ IN ] Descriptor buffer */
682 uint32_t srcAddr, /* [ IN ] Source peripheral address */
683 void *(*fpAlloc) (int len), /* [ IN ] Function pointer that provides destination memory */
684 int len, /* [ IN ] Number of bytes "fpAlloc" will allocate for destination */
685 int num /* [ IN ] Number of descriptor to set */
686 ) {
687 dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
688 dmacHw_DESC_t *pProg = NULL;
689 dmacHw_DESC_t *pLast = NULL;
690 dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
691 uint32_t dstAddr;
692 uint32_t controlParam;
693 int i;
694
695 dmacHw_ASSERT(pConfig->transferType ==
696 dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM);
697
698 if (num > pRing->num) {
699 return -1;
700 }
701
702 pLast = pRing->pEnd; /* Last descriptor updated */
703 pProg = pRing->pHead; /* First descriptor in the new list */
704
705 controlParam = pConfig->srcUpdate |
706 pConfig->dstUpdate |
707 pConfig->srcMaxTransactionWidth |
708 pConfig->dstMaxTransactionWidth |
709 pConfig->srcMasterInterface |
710 pConfig->dstMasterInterface |
711 pConfig->srcMaxBurstWidth |
712 pConfig->dstMaxBurstWidth |
713 dmacHw_REG_CTL_TTFC_PM_PERI |
714 dmacHw_REG_CTL_LLP_DST_EN |
715 dmacHw_REG_CTL_LLP_SRC_EN | dmacHw_REG_CTL_INT_EN;
716
717 for (i = 0; i < num; i++) {
718 /* Allocate Rx buffer only for idle descriptor */
719 if (((pRing->pHead->ctl.hi & dmacHw_DESC_FREE) == 0) ||
720 ((dmacHw_DESC_t *) pRing->pHead->llp == pRing->pTail)
721 ) {
722 /* Rx descriptor is not idle */
723 break;
724 }
725 /* Set source address */
726 pRing->pHead->sar = srcAddr;
727 if (fpAlloc) {
728 /* Allocate memory for buffer in descriptor */
729 dstAddr = (uint32_t) (*fpAlloc) (len);
730 /* Check the destination address */
731 if (dstAddr == 0) {
732 if (i == 0) {
733 /* Not a single descriptor is available */
734 return -1;
735 }
736 break;
737 }
738 /* Set destination address */
739 pRing->pHead->dar = dstAddr;
740 }
741 /* Set control information */
742 pRing->pHead->ctl.lo = controlParam;
743 /* Use "devCtl" to mark the memory that need to be freed later */
744 pRing->pHead->devCtl = dmacHw_FREE_USER_MEMORY;
745 /* Descriptor is now owned by the channel */
746 pRing->pHead->ctl.hi = 0;
747 /* Remember the descriptor last updated */
748 pRing->pEnd = pRing->pHead;
749 /* Update next descriptor */
750 dmacHw_NEXT_DESC(pRing, pHead);
751 }
752
753 /* Mark the end of the list */
754 pRing->pEnd->ctl.lo &=
755 ~(dmacHw_REG_CTL_LLP_DST_EN | dmacHw_REG_CTL_LLP_SRC_EN);
756 /* Connect the list */
757 if (pLast != pProg) {
758 pLast->ctl.lo |=
759 dmacHw_REG_CTL_LLP_DST_EN | dmacHw_REG_CTL_LLP_SRC_EN;
760 }
761 /* Mark the descriptors are updated */
762 pCblk->descUpdated = 1;
763 if (!pCblk->varDataStarted) {
764 /* LLP must be pointing to the first descriptor */
765 dmacHw_SET_LLP(pCblk->module, pCblk->channel,
766 (uint32_t) pProg - pRing->virt2PhyOffset);
767 /* Channel, handling variable data started */
768 pCblk->varDataStarted = 1;
769 }
770
771 return i;
772}
773
774/****************************************************************************/
775/**
776* @brief Read data DMAed to memory
777*
778* This function will read data that has been DMAed to memory while transferring from:
779* - Memory to memory
780* - Peripheral to memory
781*
782* @param handle -
783* @param ppBbuf -
784* @param pLen -
785*
786* @return 0 - No more data is available to read
787* 1 - More data might be available to read
788*
789*/
790/****************************************************************************/
791int dmacHw_readTransferredData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
792 dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
793 void *pDescriptor, /* [ IN ] Descriptor buffer */
794 void **ppBbuf, /* [ OUT ] Data received */
795 size_t *pLlen /* [ OUT ] Length of the data received */
796 ) {
797 dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
798
799 (void)handle;
800
801 if (pConfig->transferMode != dmacHw_TRANSFER_MODE_CONTINUOUS) {
802 if (((pRing->pTail->ctl.hi & dmacHw_DESC_FREE) == 0) ||
803 (pRing->pTail == pRing->pHead)
804 ) {
805 /* No receive data available */
806 *ppBbuf = (char *)NULL;
807 *pLlen = 0;
808
809 return 0;
810 }
811 }
812
813 /* Return read buffer and length */
814 *ppBbuf = (char *)pRing->pTail->dar;
815
816 /* Extract length of the received data */
817 if (DmaIsFlowController(pDescriptor)) {
818 uint32_t srcTrSize = 0;
819
820 switch (pRing->pTail->ctl.lo & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) {
821 case dmacHw_REG_CTL_SRC_TR_WIDTH_8:
822 srcTrSize = 1;
823 break;
824 case dmacHw_REG_CTL_SRC_TR_WIDTH_16:
825 srcTrSize = 2;
826 break;
827 case dmacHw_REG_CTL_SRC_TR_WIDTH_32:
828 srcTrSize = 4;
829 break;
830 case dmacHw_REG_CTL_SRC_TR_WIDTH_64:
831 srcTrSize = 8;
832 break;
833 default:
834 dmacHw_ASSERT(0);
835 }
836 /* Calculate length from the block size */
837 *pLlen =
838 (pRing->pTail->ctl.hi & dmacHw_REG_CTL_BLOCK_TS_MASK) *
839 srcTrSize;
840 } else {
841 /* Extract length from the source peripheral */
842 *pLlen = pRing->pTail->sstat;
843 }
844
845 /* Advance tail to next descriptor */
846 dmacHw_NEXT_DESC(pRing, pTail);
847
848 return 1;
849}
850
851/****************************************************************************/
852/**
853* @brief Set descriptor carrying control information
854*
855* This function will be used to send specific control information to the device
856* using the DMA channel
857*
858*
859* @return -1 - On failure
860* 0 - On success
861*
862* @note
863* None
864*/
865/****************************************************************************/
866int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
867 void *pDescriptor, /* [ IN ] Descriptor buffer */
868 uint32_t ctlAddress, /* [ IN ] Address of the device control register */
869 uint32_t control /* [ IN ] Device control information */
870 ) {
871 dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
872
873 if (ctlAddress == 0) {
874 return -1;
875 }
876
877 /* Check the availability of descriptors in the ring */
878 if ((pRing->pHead->ctl.hi & dmacHw_DESC_FREE) == 0) {
879 return -1;
880 }
881 /* Set control information */
882 pRing->pHead->devCtl = control;
883 /* Set source and destination address */
884 pRing->pHead->sar = (uint32_t) &pRing->pHead->devCtl;
885 pRing->pHead->dar = ctlAddress;
886 /* Set control parameters */
887 if (pConfig->flowControler == dmacHw_FLOW_CONTROL_DMA) {
888 pRing->pHead->ctl.lo = pConfig->transferType |
889 dmacHw_SRC_ADDRESS_UPDATE_MODE_INC |
890 dmacHw_DST_ADDRESS_UPDATE_MODE_INC |
891 dmacHw_SRC_TRANSACTION_WIDTH_32 |
892 pConfig->dstMaxTransactionWidth |
893 dmacHw_SRC_BURST_WIDTH_0 |
894 dmacHw_DST_BURST_WIDTH_0 |
895 pConfig->srcMasterInterface |
896 pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
897 } else {
898 uint32_t transferType = 0;
899 switch (pConfig->transferType) {
900 case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
901 transferType = dmacHw_REG_CTL_TTFC_PM_PERI;
902 break;
903 case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
904 transferType = dmacHw_REG_CTL_TTFC_MP_PERI;
905 break;
906 default:
907 dmacHw_ASSERT(0);
908 }
909 pRing->pHead->ctl.lo = transferType |
910 dmacHw_SRC_ADDRESS_UPDATE_MODE_INC |
911 dmacHw_DST_ADDRESS_UPDATE_MODE_INC |
912 dmacHw_SRC_TRANSACTION_WIDTH_32 |
913 pConfig->dstMaxTransactionWidth |
914 dmacHw_SRC_BURST_WIDTH_0 |
915 dmacHw_DST_BURST_WIDTH_0 |
916 pConfig->srcMasterInterface |
917 pConfig->dstMasterInterface |
918 pConfig->flowControler | dmacHw_REG_CTL_INT_EN;
919 }
920
921 /* Set block transaction size to one 32 bit transaction */
922 pRing->pHead->ctl.hi = dmacHw_REG_CTL_BLOCK_TS_MASK & 1;
923
924 /* Remember the descriptor to initialize the registers */
925 if (pRing->pProg == dmacHw_DESC_INIT) {
926 pRing->pProg = pRing->pHead;
927 }
928 pRing->pEnd = pRing->pHead;
929
930 /* Advance the descriptor */
931 dmacHw_NEXT_DESC(pRing, pHead);
932
933 /* Update Tail pointer if destination is a peripheral */
934 if (!dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
935 pRing->pTail = pRing->pHead;
936 }
937 return 0;
938}
939
940/****************************************************************************/
941/**
942* @brief Sets channel specific user data
943*
944* This function associates user data to a specific DMA channel
945*
946*/
947/****************************************************************************/
948void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
949 void *userData /* [ IN ] User data */
950 ) {
951 dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
952
953 pCblk->userData = userData;
954}
955
956/****************************************************************************/
957/**
958* @brief Gets channel specific user data
959*
960* This function returns user data specific to a DMA channel
961*
962* @return user data
963*/
964/****************************************************************************/
965void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
966 ) {
967 dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
968
969 return pCblk->userData;
970}
971
972/****************************************************************************/
973/**
974* @brief Resets descriptor control information
975*
976* @return void
977*/
978/****************************************************************************/
979void dmacHw_resetDescriptorControl(void *pDescriptor /* [ IN ] Descriptor buffer */
980 ) {
981 int i;
982 dmacHw_DESC_RING_t *pRing;
983 dmacHw_DESC_t *pDesc;
984
985 pRing = dmacHw_GET_DESC_RING(pDescriptor);
986 pDesc = pRing->pHead;
987
988 for (i = 0; i < pRing->num; i++) {
989 /* Mark descriptor is ready to use */
990 pDesc->ctl.hi = dmacHw_DESC_FREE;
991 /* Look into next link list item */
992 pDesc++;
993 }
994 pRing->pFree = pRing->pTail = pRing->pEnd = pRing->pHead;
995 pRing->pProg = dmacHw_DESC_INIT;
996}
997
998/****************************************************************************/
999/**
1000* @brief Displays channel specific registers and other control parameters
1001*
1002* @return void
1003*
1004*
1005* @note
1006* None
1007*/
1008/****************************************************************************/
1009void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
1010 void *pDescriptor, /* [ IN ] Descriptor buffer */
1011 int (*fpPrint) (const char *, ...) /* [ IN ] Print callback function */
1012 ) {
1013 dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
1014
1015 DisplayRegisterContents(pCblk->module, pCblk->channel, fpPrint);
1016 DisplayDescRing(pDescriptor, fpPrint);
1017}
diff --git a/arch/arm/mach-bcmring/csp/tmr/Makefile b/arch/arm/mach-bcmring/csp/tmr/Makefile
deleted file mode 100644
index 244a61ab7697..000000000000
--- a/arch/arm/mach-bcmring/csp/tmr/Makefile
+++ /dev/null
@@ -1 +0,0 @@
1obj-y += tmrHw.o
diff --git a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
deleted file mode 100644
index dc4137ff75ca..000000000000
--- a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
+++ /dev/null
@@ -1,576 +0,0 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file tmrHw.c
18*
19* @brief Low level Timer driver routines
20*
21* @note
22*
23* These routines provide basic timer functionality only.
24*/
25/****************************************************************************/
26
27/* ---- Include Files ---------------------------------------------------- */
28
29#include <linux/errno.h>
30#include <linux/types.h>
31
32#include <mach/csp/tmrHw.h>
33#include <mach/csp/tmrHw_reg.h>
34
35#define tmrHw_ASSERT(a) if (!(a)) *(char *)0 = 0
36#define tmrHw_MILLISEC_PER_SEC (1000)
37
38#define tmrHw_LOW_1_RESOLUTION_COUNT (tmrHw_LOW_RESOLUTION_CLOCK / tmrHw_MILLISEC_PER_SEC)
39#define tmrHw_LOW_1_MAX_MILLISEC (0xFFFFFFFF / tmrHw_LOW_1_RESOLUTION_COUNT)
40#define tmrHw_LOW_16_RESOLUTION_COUNT (tmrHw_LOW_1_RESOLUTION_COUNT / 16)
41#define tmrHw_LOW_16_MAX_MILLISEC (0xFFFFFFFF / tmrHw_LOW_16_RESOLUTION_COUNT)
42#define tmrHw_LOW_256_RESOLUTION_COUNT (tmrHw_LOW_1_RESOLUTION_COUNT / 256)
43#define tmrHw_LOW_256_MAX_MILLISEC (0xFFFFFFFF / tmrHw_LOW_256_RESOLUTION_COUNT)
44
45#define tmrHw_HIGH_1_RESOLUTION_COUNT (tmrHw_HIGH_RESOLUTION_CLOCK / tmrHw_MILLISEC_PER_SEC)
46#define tmrHw_HIGH_1_MAX_MILLISEC (0xFFFFFFFF / tmrHw_HIGH_1_RESOLUTION_COUNT)
47#define tmrHw_HIGH_16_RESOLUTION_COUNT (tmrHw_HIGH_1_RESOLUTION_COUNT / 16)
48#define tmrHw_HIGH_16_MAX_MILLISEC (0xFFFFFFFF / tmrHw_HIGH_16_RESOLUTION_COUNT)
49#define tmrHw_HIGH_256_RESOLUTION_COUNT (tmrHw_HIGH_1_RESOLUTION_COUNT / 256)
50#define tmrHw_HIGH_256_MAX_MILLISEC (0xFFFFFFFF / tmrHw_HIGH_256_RESOLUTION_COUNT)
51
52static void ResetTimer(tmrHw_ID_t timerId)
53 __attribute__ ((section(".aramtext")));
54static int tmrHw_divide(int num, int denom)
55 __attribute__ ((section(".aramtext")));
56
57/****************************************************************************/
58/**
59* @brief Get timer capability
60*
61* This function returns various capabilities/attributes of a timer
62*
63* @return Capability
64*
65*/
66/****************************************************************************/
67uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
68 tmrHw_CAPABILITY_e capability /* [ IN ] Timer capability */
69) {
70 switch (capability) {
71 case tmrHw_CAPABILITY_CLOCK:
72 return (timerId <=
73 1) ? tmrHw_LOW_RESOLUTION_CLOCK :
74 tmrHw_HIGH_RESOLUTION_CLOCK;
75 case tmrHw_CAPABILITY_RESOLUTION:
76 return 32;
77 default:
78 return 0;
79 }
80 return 0;
81}
82
83/****************************************************************************/
84/**
85* @brief Resets a timer
86*
87* This function initializes timer
88*
89* @return void
90*
91*/
92/****************************************************************************/
93static void ResetTimer(tmrHw_ID_t timerId /* [ IN ] Timer Id */
94) {
95 /* Reset timer */
96 pTmrHw[timerId].LoadValue = 0;
97 pTmrHw[timerId].CurrentValue = 0xFFFFFFFF;
98 pTmrHw[timerId].Control = 0;
99 pTmrHw[timerId].BackgroundLoad = 0;
100 /* Always configure as a 32 bit timer */
101 pTmrHw[timerId].Control |= tmrHw_CONTROL_32BIT;
102 /* Clear interrupt only if raw status interrupt is set */
103 if (pTmrHw[timerId].RawInterruptStatus) {
104 pTmrHw[timerId].InterruptClear = 0xFFFFFFFF;
105 }
106}
107
108/****************************************************************************/
109/**
110* @brief Sets counter value for an interval in ms
111*
112* @return On success: Effective counter value set
113* On failure: 0
114*
115*/
116/****************************************************************************/
117static tmrHw_INTERVAL_t SetTimerPeriod(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
118 tmrHw_INTERVAL_t msec /* [ IN ] Interval in milli-second */
119) {
120 uint32_t scale = 0;
121 uint32_t count = 0;
122
123 if (timerId == 0 || timerId == 1) {
124 if (msec <= tmrHw_LOW_1_MAX_MILLISEC) {
125 pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
126 scale = tmrHw_LOW_1_RESOLUTION_COUNT;
127 } else if (msec <= tmrHw_LOW_16_MAX_MILLISEC) {
128 pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
129 scale = tmrHw_LOW_16_RESOLUTION_COUNT;
130 } else if (msec <= tmrHw_LOW_256_MAX_MILLISEC) {
131 pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
132 scale = tmrHw_LOW_256_RESOLUTION_COUNT;
133 } else {
134 return 0;
135 }
136
137 count = msec * scale;
138 /* Set counter value */
139 pTmrHw[timerId].LoadValue = count;
140 pTmrHw[timerId].BackgroundLoad = count;
141
142 } else if (timerId == 2 || timerId == 3) {
143 if (msec <= tmrHw_HIGH_1_MAX_MILLISEC) {
144 pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
145 scale = tmrHw_HIGH_1_RESOLUTION_COUNT;
146 } else if (msec <= tmrHw_HIGH_16_MAX_MILLISEC) {
147 pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
148 scale = tmrHw_HIGH_16_RESOLUTION_COUNT;
149 } else if (msec <= tmrHw_HIGH_256_MAX_MILLISEC) {
150 pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
151 scale = tmrHw_HIGH_256_RESOLUTION_COUNT;
152 } else {
153 return 0;
154 }
155
156 count = msec * scale;
157 /* Set counter value */
158 pTmrHw[timerId].LoadValue = count;
159 pTmrHw[timerId].BackgroundLoad = count;
160 }
161 return count / scale;
162}
163
164/****************************************************************************/
165/**
166* @brief Configures a periodic timer in terms of timer interrupt rate
167*
168* This function initializes a periodic timer to generate specific number of
169* timer interrupt per second
170*
171* @return On success: Effective timer frequency
172* On failure: 0
173*
174*/
175/****************************************************************************/
176tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
177 tmrHw_RATE_t rate /* [ IN ] Number of timer interrupt per second */
178) {
179 uint32_t resolution = 0;
180 uint32_t count = 0;
181 ResetTimer(timerId);
182
183 /* Set timer mode periodic */
184 pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
185 pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
186 /* Set timer in highest resolution */
187 pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
188
189 if (rate && (timerId == 0 || timerId == 1)) {
190 if (rate > tmrHw_LOW_RESOLUTION_CLOCK) {
191 return 0;
192 }
193 resolution = tmrHw_LOW_RESOLUTION_CLOCK;
194 } else if (rate && (timerId == 2 || timerId == 3)) {
195 if (rate > tmrHw_HIGH_RESOLUTION_CLOCK) {
196 return 0;
197 } else {
198 resolution = tmrHw_HIGH_RESOLUTION_CLOCK;
199 }
200 } else {
201 return 0;
202 }
203 /* Find the counter value */
204 count = resolution / rate;
205 /* Set counter value */
206 pTmrHw[timerId].LoadValue = count;
207 pTmrHw[timerId].BackgroundLoad = count;
208
209 return resolution / count;
210}
211
212/****************************************************************************/
213/**
214* @brief Configures a periodic timer to generate timer interrupt after
215* certain time interval
216*
217* This function initializes a periodic timer to generate timer interrupt
218* after every time interval in millisecond
219*
220* @return On success: Effective interval set in milli-second
221* On failure: 0
222*
223*/
224/****************************************************************************/
225tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
226 tmrHw_INTERVAL_t msec /* [ IN ] Interval in milli-second */
227) {
228 ResetTimer(timerId);
229
230 /* Set timer mode periodic */
231 pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
232 pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
233
234 return SetTimerPeriod(timerId, msec);
235}
236
237/****************************************************************************/
238/**
239* @brief Configures a periodic timer to generate timer interrupt just once
240* after certain time interval
241*
242* This function initializes a periodic timer to generate a single ticks after
243* certain time interval in millisecond
244*
245* @return On success: Effective interval set in milli-second
246* On failure: 0
247*
248*/
249/****************************************************************************/
250tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
251 tmrHw_INTERVAL_t msec /* [ IN ] Interval in milli-second */
252) {
253 ResetTimer(timerId);
254
255 /* Set timer mode oneshot */
256 pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
257 pTmrHw[timerId].Control |= tmrHw_CONTROL_ONESHOT;
258
259 return SetTimerPeriod(timerId, msec);
260}
261
262/****************************************************************************/
263/**
264* @brief Configures a timer to run as a free running timer
265*
266* This function initializes a timer to run as a free running timer
267*
268* @return Timer resolution (count / sec)
269*
270*/
271/****************************************************************************/
272tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
273 uint32_t divider /* [ IN ] Dividing the clock frequency */
274) {
275 uint32_t scale = 0;
276
277 ResetTimer(timerId);
278 /* Set timer as free running mode */
279 pTmrHw[timerId].Control &= ~tmrHw_CONTROL_PERIODIC;
280 pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
281
282 if (divider >= 64) {
283 pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
284 scale = 256;
285 } else if (divider >= 8) {
286 pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
287 scale = 16;
288 } else {
289 pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
290 scale = 1;
291 }
292
293 if (timerId == 0 || timerId == 1) {
294 return tmrHw_divide(tmrHw_LOW_RESOLUTION_CLOCK, scale);
295 } else if (timerId == 2 || timerId == 3) {
296 return tmrHw_divide(tmrHw_HIGH_RESOLUTION_CLOCK, scale);
297 }
298
299 return 0;
300}
301
302/****************************************************************************/
303/**
304* @brief Starts a timer
305*
306* This function starts a preconfigured timer
307*
308* @return -1 - On Failure
309* 0 - On Success
310*
311*/
312/****************************************************************************/
313int tmrHw_startTimer(tmrHw_ID_t timerId /* [ IN ] Timer id */
314) {
315 pTmrHw[timerId].Control |= tmrHw_CONTROL_TIMER_ENABLE;
316 return 0;
317}
318
319/****************************************************************************/
320/**
321* @brief Stops a timer
322*
323* This function stops a running timer
324*
325* @return -1 - On Failure
326* 0 - On Success
327*
328*/
329/****************************************************************************/
330int tmrHw_stopTimer(tmrHw_ID_t timerId /* [ IN ] Timer id */
331) {
332 pTmrHw[timerId].Control &= ~tmrHw_CONTROL_TIMER_ENABLE;
333 return 0;
334}
335
336/****************************************************************************/
337/**
338* @brief Gets current timer count
339*
340* This function returns the current timer value
341*
342* @return Current downcounting timer value
343*
344*/
345/****************************************************************************/
346uint32_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId /* [ IN ] Timer id */
347) {
348 /* return 32 bit timer value */
349 switch (pTmrHw[timerId].Control & tmrHw_CONTROL_MODE_MASK) {
350 case tmrHw_CONTROL_FREE_RUNNING:
351 if (pTmrHw[timerId].CurrentValue) {
352 return tmrHw_MAX_COUNT - pTmrHw[timerId].CurrentValue;
353 }
354 break;
355 case tmrHw_CONTROL_PERIODIC:
356 case tmrHw_CONTROL_ONESHOT:
357 return pTmrHw[timerId].BackgroundLoad -
358 pTmrHw[timerId].CurrentValue;
359 }
360 return 0;
361}
362
363/****************************************************************************/
364/**
365* @brief Gets timer count rate
366*
367* This function returns the number of counts per second
368*
369* @return Count rate
370*
371*/
372/****************************************************************************/
373tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId /* [ IN ] Timer id */
374) {
375 uint32_t divider = 0;
376
377 switch (pTmrHw[timerId].Control & tmrHw_CONTROL_PRESCALE_MASK) {
378 case tmrHw_CONTROL_PRESCALE_1:
379 divider = 1;
380 break;
381 case tmrHw_CONTROL_PRESCALE_16:
382 divider = 16;
383 break;
384 case tmrHw_CONTROL_PRESCALE_256:
385 divider = 256;
386 break;
387 default:
388 tmrHw_ASSERT(0);
389 }
390
391 if (timerId == 0 || timerId == 1) {
392 return tmrHw_divide(tmrHw_LOW_RESOLUTION_CLOCK, divider);
393 } else {
394 return tmrHw_divide(tmrHw_HIGH_RESOLUTION_CLOCK, divider);
395 }
396 return 0;
397}
398
399/****************************************************************************/
400/**
401* @brief Enables timer interrupt
402*
403* This function enables the timer interrupt
404*
405* @return N/A
406*
407*/
408/****************************************************************************/
409void tmrHw_enableInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */
410) {
411 pTmrHw[timerId].Control |= tmrHw_CONTROL_INTERRUPT_ENABLE;
412}
413
414/****************************************************************************/
415/**
416* @brief Disables timer interrupt
417*
418* This function disable the timer interrupt
419*
420* @return N/A
421*
422*/
423/****************************************************************************/
424void tmrHw_disableInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */
425) {
426 pTmrHw[timerId].Control &= ~tmrHw_CONTROL_INTERRUPT_ENABLE;
427}
428
429/****************************************************************************/
430/**
431* @brief Clears the interrupt
432*
433* This function clears the timer interrupt
434*
435* @return N/A
436*
437* @note
438* Must be called under the context of ISR
439*/
440/****************************************************************************/
441void tmrHw_clearInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */
442) {
443 pTmrHw[timerId].InterruptClear = 0x1;
444}
445
446/****************************************************************************/
447/**
448* @brief Gets the interrupt status
449*
450* This function returns timer interrupt status
451*
452* @return Interrupt status
453*/
454/****************************************************************************/
455tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId /* [ IN ] Timer id */
456) {
457 if (pTmrHw[timerId].InterruptStatus) {
458 return tmrHw_INTERRUPT_STATUS_SET;
459 } else {
460 return tmrHw_INTERRUPT_STATUS_UNSET;
461 }
462}
463
464/****************************************************************************/
465/**
466* @brief Indentifies a timer causing interrupt
467*
468* This functions returns a timer causing interrupt
469*
470* @return 0xFFFFFFFF : No timer causing an interrupt
471* ! 0xFFFFFFFF : timer causing an interrupt
472* @note
473* tmrHw_clearIntrrupt() must be called with a valid timer id after calling this function
474*/
475/****************************************************************************/
476tmrHw_ID_t tmrHw_getInterruptSource(void /* void */
477) {
478 int i;
479
480 for (i = 0; i < tmrHw_TIMER_NUM_COUNT; i++) {
481 if (pTmrHw[i].InterruptStatus) {
482 return i;
483 }
484 }
485
486 return 0xFFFFFFFF;
487}
488
489/****************************************************************************/
490/**
491* @brief Displays specific timer registers
492*
493*
494* @return void
495*
496*/
497/****************************************************************************/
498void tmrHw_printDebugInfo(tmrHw_ID_t timerId, /* [ IN ] Timer id */
499 int (*fpPrint) (const char *, ...) /* [ IN ] Print callback function */
500) {
501 (*fpPrint) ("Displaying register contents \n\n");
502 (*fpPrint) ("Timer %d: Load value 0x%X\n", timerId,
503 pTmrHw[timerId].LoadValue);
504 (*fpPrint) ("Timer %d: Background load value 0x%X\n", timerId,
505 pTmrHw[timerId].BackgroundLoad);
506 (*fpPrint) ("Timer %d: Control 0x%X\n", timerId,
507 pTmrHw[timerId].Control);
508 (*fpPrint) ("Timer %d: Interrupt clear 0x%X\n", timerId,
509 pTmrHw[timerId].InterruptClear);
510 (*fpPrint) ("Timer %d: Interrupt raw interrupt 0x%X\n", timerId,
511 pTmrHw[timerId].RawInterruptStatus);
512 (*fpPrint) ("Timer %d: Interrupt status 0x%X\n", timerId,
513 pTmrHw[timerId].InterruptStatus);
514}
515
516/****************************************************************************/
517/**
518* @brief Use a timer to perform a busy wait delay for a number of usecs.
519*
520* @return N/A
521*/
522/****************************************************************************/
523void tmrHw_udelay(tmrHw_ID_t timerId, /* [ IN ] Timer id */
524 unsigned long usecs /* [ IN ] usec to delay */
525) {
526 tmrHw_RATE_t usec_tick_rate;
527 tmrHw_COUNT_t start_time;
528 tmrHw_COUNT_t delta_time;
529
530 start_time = tmrHw_GetCurrentCount(timerId);
531 usec_tick_rate = tmrHw_divide(tmrHw_getCountRate(timerId), 1000000);
532 delta_time = usecs * usec_tick_rate;
533
534 /* Busy wait */
535 while (delta_time > (tmrHw_GetCurrentCount(timerId) - start_time))
536 ;
537}
538
539/****************************************************************************/
540/**
541* @brief Local Divide function
542*
543* This function does the divide
544*
545* @return divide value
546*
547*/
548/****************************************************************************/
549static int tmrHw_divide(int num, int denom)
550{
551 int r;
552 int t = 1;
553
554 /* Shift denom and t up to the largest value to optimize algorithm */
555 /* t contains the units of each divide */
556 while ((denom & 0x40000000) == 0) { /* fails if denom=0 */
557 denom = denom << 1;
558 t = t << 1;
559 }
560
561 /* Initialize the result */
562 r = 0;
563
564 do {
565 /* Determine if there exists a positive remainder */
566 if ((num - denom) >= 0) {
567 /* Accumlate t to the result and calculate a new remainder */
568 num = num - denom;
569 r = r + t;
570 }
571 /* Continue to shift denom and shift t down to 0 */
572 denom = denom >> 1;
573 t = t >> 1;
574 } while (t != 0);
575 return r;
576}
diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c
deleted file mode 100644
index e5fd241fccdc..000000000000
--- a/arch/arm/mach-bcmring/dma.c
+++ /dev/null
@@ -1,1518 +0,0 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file dma.c
18*
19* @brief Implements the DMA interface.
20*/
21/****************************************************************************/
22
23/* ---- Include Files ---------------------------------------------------- */
24
25#include <linux/module.h>
26#include <linux/device.h>
27#include <linux/dma-mapping.h>
28#include <linux/interrupt.h>
29#include <linux/sched.h>
30#include <linux/irqreturn.h>
31#include <linux/proc_fs.h>
32#include <linux/slab.h>
33
34#include <mach/timer.h>
35
36#include <linux/pfn.h>
37#include <linux/atomic.h>
38#include <mach/dma.h>
39
40/* ---- Public Variables ------------------------------------------------- */
41
42/* ---- Private Constants and Types -------------------------------------- */
43
44#define MAKE_HANDLE(controllerIdx, channelIdx) (((controllerIdx) << 4) | (channelIdx))
45
46#define CONTROLLER_FROM_HANDLE(handle) (((handle) >> 4) & 0x0f)
47#define CHANNEL_FROM_HANDLE(handle) ((handle) & 0x0f)
48
49
50/* ---- Private Variables ------------------------------------------------ */
51
52static DMA_Global_t gDMA;
53static struct proc_dir_entry *gDmaDir;
54
55#include "dma_device.c"
56
57/* ---- Private Function Prototypes -------------------------------------- */
58
59/* ---- Functions ------------------------------------------------------- */
60
61/****************************************************************************/
62/**
63* Displays information for /proc/dma/channels
64*/
65/****************************************************************************/
66
67static int dma_proc_read_channels(char *buf, char **start, off_t offset,
68 int count, int *eof, void *data)
69{
70 int controllerIdx;
71 int channelIdx;
72 int limit = count - 200;
73 int len = 0;
74 DMA_Channel_t *channel;
75
76 if (down_interruptible(&gDMA.lock) < 0) {
77 return -ERESTARTSYS;
78 }
79
80 for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
81 controllerIdx++) {
82 for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
83 channelIdx++) {
84 if (len >= limit) {
85 break;
86 }
87
88 channel =
89 &gDMA.controller[controllerIdx].channel[channelIdx];
90
91 len +=
92 sprintf(buf + len, "%d:%d ", controllerIdx,
93 channelIdx);
94
95 if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) !=
96 0) {
97 len +=
98 sprintf(buf + len, "Dedicated for %s ",
99 DMA_gDeviceAttribute[channel->
100 devType].name);
101 } else {
102 len += sprintf(buf + len, "Shared ");
103 }
104
105 if ((channel->flags & DMA_CHANNEL_FLAG_NO_ISR) != 0) {
106 len += sprintf(buf + len, "No ISR ");
107 }
108
109 if ((channel->flags & DMA_CHANNEL_FLAG_LARGE_FIFO) != 0) {
110 len += sprintf(buf + len, "Fifo: 128 ");
111 } else {
112 len += sprintf(buf + len, "Fifo: 64 ");
113 }
114
115 if ((channel->flags & DMA_CHANNEL_FLAG_IN_USE) != 0) {
116 len +=
117 sprintf(buf + len, "InUse by %s",
118 DMA_gDeviceAttribute[channel->
119 devType].name);
120#if (DMA_DEBUG_TRACK_RESERVATION)
121 len +=
122 sprintf(buf + len, " (%s:%d)",
123 channel->fileName,
124 channel->lineNum);
125#endif
126 } else {
127 len += sprintf(buf + len, "Avail ");
128 }
129
130 if (channel->lastDevType != DMA_DEVICE_NONE) {
131 len +=
132 sprintf(buf + len, "Last use: %s ",
133 DMA_gDeviceAttribute[channel->
134 lastDevType].
135 name);
136 }
137
138 len += sprintf(buf + len, "\n");
139 }
140 }
141 up(&gDMA.lock);
142 *eof = 1;
143
144 return len;
145}
146
147/****************************************************************************/
148/**
149* Displays information for /proc/dma/devices
150*/
151/****************************************************************************/
152
153static int dma_proc_read_devices(char *buf, char **start, off_t offset,
154 int count, int *eof, void *data)
155{
156 int limit = count - 200;
157 int len = 0;
158 int devIdx;
159
160 if (down_interruptible(&gDMA.lock) < 0) {
161 return -ERESTARTSYS;
162 }
163
164 for (devIdx = 0; devIdx < DMA_NUM_DEVICE_ENTRIES; devIdx++) {
165 DMA_DeviceAttribute_t *devAttr = &DMA_gDeviceAttribute[devIdx];
166
167 if (devAttr->name == NULL) {
168 continue;
169 }
170
171 if (len >= limit) {
172 break;
173 }
174
175 len += sprintf(buf + len, "%-12s ", devAttr->name);
176
177 if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
178 len +=
179 sprintf(buf + len, "Dedicated %d:%d ",
180 devAttr->dedicatedController,
181 devAttr->dedicatedChannel);
182 } else {
183 len += sprintf(buf + len, "Shared DMA:");
184 if ((devAttr->flags & DMA_DEVICE_FLAG_ON_DMA0) != 0) {
185 len += sprintf(buf + len, "0");
186 }
187 if ((devAttr->flags & DMA_DEVICE_FLAG_ON_DMA1) != 0) {
188 len += sprintf(buf + len, "1");
189 }
190 len += sprintf(buf + len, " ");
191 }
192 if ((devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) != 0) {
193 len += sprintf(buf + len, "NoISR ");
194 }
195 if ((devAttr->flags & DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO) != 0) {
196 len += sprintf(buf + len, "Allow-128 ");
197 }
198
199 len +=
200 sprintf(buf + len,
201 "Xfer #: %Lu Ticks: %Lu Bytes: %Lu DescLen: %u\n",
202 devAttr->numTransfers, devAttr->transferTicks,
203 devAttr->transferBytes,
204 devAttr->ring.bytesAllocated);
205
206 }
207
208 up(&gDMA.lock);
209 *eof = 1;
210
211 return len;
212}
213
214/****************************************************************************/
215/**
216* Determines if a DMA_Device_t is "valid".
217*
218* @return
219* TRUE - dma device is valid
220* FALSE - dma device isn't valid
221*/
222/****************************************************************************/
223
224static inline int IsDeviceValid(DMA_Device_t device)
225{
226 return (device >= 0) && (device < DMA_NUM_DEVICE_ENTRIES);
227}
228
229/****************************************************************************/
230/**
231* Translates a DMA handle into a pointer to a channel.
232*
233* @return
234* non-NULL - pointer to DMA_Channel_t
235* NULL - DMA Handle was invalid
236*/
237/****************************************************************************/
238
239static inline DMA_Channel_t *HandleToChannel(DMA_Handle_t handle)
240{
241 int controllerIdx;
242 int channelIdx;
243
244 controllerIdx = CONTROLLER_FROM_HANDLE(handle);
245 channelIdx = CHANNEL_FROM_HANDLE(handle);
246
247 if ((controllerIdx > DMA_NUM_CONTROLLERS)
248 || (channelIdx > DMA_NUM_CHANNELS)) {
249 return NULL;
250 }
251 return &gDMA.controller[controllerIdx].channel[channelIdx];
252}
253
254/****************************************************************************/
255/**
256* Interrupt handler which is called to process DMA interrupts.
257*/
258/****************************************************************************/
259
260static irqreturn_t dma_interrupt_handler(int irq, void *dev_id)
261{
262 DMA_Channel_t *channel;
263 DMA_DeviceAttribute_t *devAttr;
264 int irqStatus;
265
266 channel = (DMA_Channel_t *) dev_id;
267
268 /* Figure out why we were called, and knock down the interrupt */
269
270 irqStatus = dmacHw_getInterruptStatus(channel->dmacHwHandle);
271 dmacHw_clearInterrupt(channel->dmacHwHandle);
272
273 if ((channel->devType < 0)
274 || (channel->devType > DMA_NUM_DEVICE_ENTRIES)) {
275 printk(KERN_ERR "dma_interrupt_handler: Invalid devType: %d\n",
276 channel->devType);
277 return IRQ_NONE;
278 }
279 devAttr = &DMA_gDeviceAttribute[channel->devType];
280
281 /* Update stats */
282
283 if ((irqStatus & dmacHw_INTERRUPT_STATUS_TRANS) != 0) {
284 devAttr->transferTicks +=
285 (timer_get_tick_count() - devAttr->transferStartTime);
286 }
287
288 if ((irqStatus & dmacHw_INTERRUPT_STATUS_ERROR) != 0) {
289 printk(KERN_ERR
290 "dma_interrupt_handler: devType :%d DMA error (%s)\n",
291 channel->devType, devAttr->name);
292 } else {
293 devAttr->numTransfers++;
294 devAttr->transferBytes += devAttr->numBytes;
295 }
296
297 /* Call any installed handler */
298
299 if (devAttr->devHandler != NULL) {
300 devAttr->devHandler(channel->devType, irqStatus,
301 devAttr->userData);
302 }
303
304 return IRQ_HANDLED;
305}
306
307/****************************************************************************/
308/**
309* Allocates memory to hold a descriptor ring. The descriptor ring then
310* needs to be populated by making one or more calls to
311* dna_add_descriptors.
312*
313* The returned descriptor ring will be automatically initialized.
314*
315* @return
316* 0 Descriptor ring was allocated successfully
317* -EINVAL Invalid parameters passed in
318* -ENOMEM Unable to allocate memory for the desired number of descriptors.
319*/
320/****************************************************************************/
321
322int dma_alloc_descriptor_ring(DMA_DescriptorRing_t *ring, /* Descriptor ring to populate */
323 int numDescriptors /* Number of descriptors that need to be allocated. */
324 ) {
325 size_t bytesToAlloc = dmacHw_descriptorLen(numDescriptors);
326
327 if ((ring == NULL) || (numDescriptors <= 0)) {
328 return -EINVAL;
329 }
330
331 ring->physAddr = 0;
332 ring->descriptorsAllocated = 0;
333 ring->bytesAllocated = 0;
334
335 ring->virtAddr = dma_alloc_writecombine(NULL,
336 bytesToAlloc,
337 &ring->physAddr,
338 GFP_KERNEL);
339 if (ring->virtAddr == NULL) {
340 return -ENOMEM;
341 }
342
343 ring->bytesAllocated = bytesToAlloc;
344 ring->descriptorsAllocated = numDescriptors;
345
346 return dma_init_descriptor_ring(ring, numDescriptors);
347}
348
349EXPORT_SYMBOL(dma_alloc_descriptor_ring);
350
351/****************************************************************************/
352/**
353* Releases the memory which was previously allocated for a descriptor ring.
354*/
355/****************************************************************************/
356
357void dma_free_descriptor_ring(DMA_DescriptorRing_t *ring /* Descriptor to release */
358 ) {
359 if (ring->virtAddr != NULL) {
360 dma_free_writecombine(NULL,
361 ring->bytesAllocated,
362 ring->virtAddr, ring->physAddr);
363 }
364
365 ring->bytesAllocated = 0;
366 ring->descriptorsAllocated = 0;
367 ring->virtAddr = NULL;
368 ring->physAddr = 0;
369}
370
371EXPORT_SYMBOL(dma_free_descriptor_ring);
372
373/****************************************************************************/
374/**
375* Initializes a descriptor ring, so that descriptors can be added to it.
376* Once a descriptor ring has been allocated, it may be reinitialized for
377* use with additional/different regions of memory.
378*
379* Note that if 7 descriptors are allocated, it's perfectly acceptable to
380* initialize the ring with a smaller number of descriptors. The amount
381* of memory allocated for the descriptor ring will not be reduced, and
382* the descriptor ring may be reinitialized later
383*
384* @return
385* 0 Descriptor ring was initialized successfully
386* -ENOMEM The descriptor which was passed in has insufficient space
387* to hold the desired number of descriptors.
388*/
389/****************************************************************************/
390
391int dma_init_descriptor_ring(DMA_DescriptorRing_t *ring, /* Descriptor ring to initialize */
392 int numDescriptors /* Number of descriptors to initialize. */
393 ) {
394 if (ring->virtAddr == NULL) {
395 return -EINVAL;
396 }
397 if (dmacHw_initDescriptor(ring->virtAddr,
398 ring->physAddr,
399 ring->bytesAllocated, numDescriptors) < 0) {
400 printk(KERN_ERR
401 "dma_init_descriptor_ring: dmacHw_initDescriptor failed\n");
402 return -ENOMEM;
403 }
404
405 return 0;
406}
407
408EXPORT_SYMBOL(dma_init_descriptor_ring);
409
410/****************************************************************************/
411/**
412* Determines the number of descriptors which would be required for a
413* transfer of the indicated memory region.
414*
415* This function also needs to know which DMA device this transfer will
416* be destined for, so that the appropriate DMA configuration can be retrieved.
417* DMA parameters such as transfer width, and whether this is a memory-to-memory
418* or memory-to-peripheral, etc can all affect the actual number of descriptors
419* required.
420*
421* @return
422* > 0 Returns the number of descriptors required for the indicated transfer
423* -ENODEV - Device handed in is invalid.
424* -EINVAL Invalid parameters
425* -ENOMEM Memory exhausted
426*/
427/****************************************************************************/
428
429int dma_calculate_descriptor_count(DMA_Device_t device, /* DMA Device that this will be associated with */
430 dma_addr_t srcData, /* Place to get data to write to device */
431 dma_addr_t dstData, /* Pointer to device data address */
432 size_t numBytes /* Number of bytes to transfer to the device */
433 ) {
434 int numDescriptors;
435 DMA_DeviceAttribute_t *devAttr;
436
437 if (!IsDeviceValid(device)) {
438 return -ENODEV;
439 }
440 devAttr = &DMA_gDeviceAttribute[device];
441
442 numDescriptors = dmacHw_calculateDescriptorCount(&devAttr->config,
443 (void *)srcData,
444 (void *)dstData,
445 numBytes);
446 if (numDescriptors < 0) {
447 printk(KERN_ERR
448 "dma_calculate_descriptor_count: dmacHw_calculateDescriptorCount failed\n");
449 return -EINVAL;
450 }
451
452 return numDescriptors;
453}
454
455EXPORT_SYMBOL(dma_calculate_descriptor_count);
456
457/****************************************************************************/
458/**
459* Adds a region of memory to the descriptor ring. Note that it may take
460* multiple descriptors for each region of memory. It is the callers
461* responsibility to allocate a sufficiently large descriptor ring.
462*
463* @return
464* 0 Descriptors were added successfully
465* -ENODEV Device handed in is invalid.
466* -EINVAL Invalid parameters
467* -ENOMEM Memory exhausted
468*/
469/****************************************************************************/
470
471int dma_add_descriptors(DMA_DescriptorRing_t *ring, /* Descriptor ring to add descriptors to */
472 DMA_Device_t device, /* DMA Device that descriptors are for */
473 dma_addr_t srcData, /* Place to get data (memory or device) */
474 dma_addr_t dstData, /* Place to put data (memory or device) */
475 size_t numBytes /* Number of bytes to transfer to the device */
476 ) {
477 int rc;
478 DMA_DeviceAttribute_t *devAttr;
479
480 if (!IsDeviceValid(device)) {
481 return -ENODEV;
482 }
483 devAttr = &DMA_gDeviceAttribute[device];
484
485 rc = dmacHw_setDataDescriptor(&devAttr->config,
486 ring->virtAddr,
487 (void *)srcData,
488 (void *)dstData, numBytes);
489 if (rc < 0) {
490 printk(KERN_ERR
491 "dma_add_descriptors: dmacHw_setDataDescriptor failed with code: %d\n",
492 rc);
493 return -ENOMEM;
494 }
495
496 return 0;
497}
498
499EXPORT_SYMBOL(dma_add_descriptors);
500
501/****************************************************************************/
502/**
503* Sets the descriptor ring associated with a device.
504*
505* Once set, the descriptor ring will be associated with the device, even
506* across channel request/free calls. Passing in a NULL descriptor ring
507* will release any descriptor ring currently associated with the device.
508*
509* Note: If you call dma_transfer, or one of the other dma_alloc_ functions
510* the descriptor ring may be released and reallocated.
511*
512* Note: This function will release the descriptor memory for any current
513* descriptor ring associated with this device.
514*
515* @return
516* 0 Descriptors were added successfully
517* -ENODEV Device handed in is invalid.
518*/
519/****************************************************************************/
520
521int dma_set_device_descriptor_ring(DMA_Device_t device, /* Device to update the descriptor ring for. */
522 DMA_DescriptorRing_t *ring /* Descriptor ring to add descriptors to */
523 ) {
524 DMA_DeviceAttribute_t *devAttr;
525
526 if (!IsDeviceValid(device)) {
527 return -ENODEV;
528 }
529 devAttr = &DMA_gDeviceAttribute[device];
530
531 /* Free the previously allocated descriptor ring */
532
533 dma_free_descriptor_ring(&devAttr->ring);
534
535 if (ring != NULL) {
536 /* Copy in the new one */
537
538 devAttr->ring = *ring;
539 }
540
541 /* Set things up so that if dma_transfer is called then this descriptor */
542 /* ring will get freed. */
543
544 devAttr->prevSrcData = 0;
545 devAttr->prevDstData = 0;
546 devAttr->prevNumBytes = 0;
547
548 return 0;
549}
550
551EXPORT_SYMBOL(dma_set_device_descriptor_ring);
552
553/****************************************************************************/
554/**
555* Retrieves the descriptor ring associated with a device.
556*
557* @return
558* 0 Descriptors were added successfully
559* -ENODEV Device handed in is invalid.
560*/
561/****************************************************************************/
562
563int dma_get_device_descriptor_ring(DMA_Device_t device, /* Device to retrieve the descriptor ring for. */
564 DMA_DescriptorRing_t *ring /* Place to store retrieved ring */
565 ) {
566 DMA_DeviceAttribute_t *devAttr;
567
568 memset(ring, 0, sizeof(*ring));
569
570 if (!IsDeviceValid(device)) {
571 return -ENODEV;
572 }
573 devAttr = &DMA_gDeviceAttribute[device];
574
575 *ring = devAttr->ring;
576
577 return 0;
578}
579
580EXPORT_SYMBOL(dma_get_device_descriptor_ring);
581
582/****************************************************************************/
583/**
584* Configures a DMA channel.
585*
586* @return
587* >= 0 - Initialization was successful.
588*
589* -EBUSY - Device is currently being used.
590* -ENODEV - Device handed in is invalid.
591*/
592/****************************************************************************/
593
594static int ConfigChannel(DMA_Handle_t handle)
595{
596 DMA_Channel_t *channel;
597 DMA_DeviceAttribute_t *devAttr;
598 int controllerIdx;
599
600 channel = HandleToChannel(handle);
601 if (channel == NULL) {
602 return -ENODEV;
603 }
604 devAttr = &DMA_gDeviceAttribute[channel->devType];
605 controllerIdx = CONTROLLER_FROM_HANDLE(handle);
606
607 if ((devAttr->flags & DMA_DEVICE_FLAG_PORT_PER_DMAC) != 0) {
608 if (devAttr->config.transferType ==
609 dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL) {
610 devAttr->config.dstPeripheralPort =
611 devAttr->dmacPort[controllerIdx];
612 } else if (devAttr->config.transferType ==
613 dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) {
614 devAttr->config.srcPeripheralPort =
615 devAttr->dmacPort[controllerIdx];
616 }
617 }
618
619 if (dmacHw_configChannel(channel->dmacHwHandle, &devAttr->config) != 0) {
620 printk(KERN_ERR "ConfigChannel: dmacHw_configChannel failed\n");
621 return -EIO;
622 }
623
624 return 0;
625}
626
627/****************************************************************************/
628/**
629* Initializes all of the data structures associated with the DMA.
630* @return
631* >= 0 - Initialization was successful.
632*
633* -EBUSY - Device is currently being used.
634* -ENODEV - Device handed in is invalid.
635*/
636/****************************************************************************/
637
638int dma_init(void)
639{
640 int rc = 0;
641 int controllerIdx;
642 int channelIdx;
643 DMA_Device_t devIdx;
644 DMA_Channel_t *channel;
645 DMA_Handle_t dedicatedHandle;
646
647 memset(&gDMA, 0, sizeof(gDMA));
648
649 sema_init(&gDMA.lock, 0);
650 init_waitqueue_head(&gDMA.freeChannelQ);
651
652 /* Initialize the Hardware */
653
654 dmacHw_initDma();
655
656 /* Start off by marking all of the DMA channels as shared. */
657
658 for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
659 controllerIdx++) {
660 for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
661 channelIdx++) {
662 channel =
663 &gDMA.controller[controllerIdx].channel[channelIdx];
664
665 channel->flags = 0;
666 channel->devType = DMA_DEVICE_NONE;
667 channel->lastDevType = DMA_DEVICE_NONE;
668
669#if (DMA_DEBUG_TRACK_RESERVATION)
670 channel->fileName = "";
671 channel->lineNum = 0;
672#endif
673
674 channel->dmacHwHandle =
675 dmacHw_getChannelHandle(dmacHw_MAKE_CHANNEL_ID
676 (controllerIdx,
677 channelIdx));
678 dmacHw_initChannel(channel->dmacHwHandle);
679 }
680 }
681
682 /* Record any special attributes that channels may have */
683
684 gDMA.controller[0].channel[0].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
685 gDMA.controller[0].channel[1].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
686 gDMA.controller[1].channel[0].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
687 gDMA.controller[1].channel[1].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
688
689 /* Now walk through and record the dedicated channels. */
690
691 for (devIdx = 0; devIdx < DMA_NUM_DEVICE_ENTRIES; devIdx++) {
692 DMA_DeviceAttribute_t *devAttr = &DMA_gDeviceAttribute[devIdx];
693
694 if (((devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) != 0)
695 && ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) == 0)) {
696 printk(KERN_ERR
697 "DMA Device: %s Can only request NO_ISR for dedicated devices\n",
698 devAttr->name);
699 rc = -EINVAL;
700 goto out;
701 }
702
703 if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
704 /* This is a dedicated device. Mark the channel as being reserved. */
705
706 if (devAttr->dedicatedController >= DMA_NUM_CONTROLLERS) {
707 printk(KERN_ERR
708 "DMA Device: %s DMA Controller %d is out of range\n",
709 devAttr->name,
710 devAttr->dedicatedController);
711 rc = -EINVAL;
712 goto out;
713 }
714
715 if (devAttr->dedicatedChannel >= DMA_NUM_CHANNELS) {
716 printk(KERN_ERR
717 "DMA Device: %s DMA Channel %d is out of range\n",
718 devAttr->name,
719 devAttr->dedicatedChannel);
720 rc = -EINVAL;
721 goto out;
722 }
723
724 dedicatedHandle =
725 MAKE_HANDLE(devAttr->dedicatedController,
726 devAttr->dedicatedChannel);
727 channel = HandleToChannel(dedicatedHandle);
728
729 if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) !=
730 0) {
731 printk
732 ("DMA Device: %s attempting to use same DMA Controller:Channel (%d:%d) as %s\n",
733 devAttr->name,
734 devAttr->dedicatedController,
735 devAttr->dedicatedChannel,
736 DMA_gDeviceAttribute[channel->devType].
737 name);
738 rc = -EBUSY;
739 goto out;
740 }
741
742 channel->flags |= DMA_CHANNEL_FLAG_IS_DEDICATED;
743 channel->devType = devIdx;
744
745 if (devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) {
746 channel->flags |= DMA_CHANNEL_FLAG_NO_ISR;
747 }
748
749 /* For dedicated channels, we can go ahead and configure the DMA channel now */
750 /* as well. */
751
752 ConfigChannel(dedicatedHandle);
753 }
754 }
755
756 /* Go through and register the interrupt handlers */
757
758 for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
759 controllerIdx++) {
760 for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
761 channelIdx++) {
762 channel =
763 &gDMA.controller[controllerIdx].channel[channelIdx];
764
765 if ((channel->flags & DMA_CHANNEL_FLAG_NO_ISR) == 0) {
766 snprintf(channel->name, sizeof(channel->name),
767 "dma %d:%d %s", controllerIdx,
768 channelIdx,
769 channel->devType ==
770 DMA_DEVICE_NONE ? "" :
771 DMA_gDeviceAttribute[channel->devType].
772 name);
773
774 rc =
775 request_irq(IRQ_DMA0C0 +
776 (controllerIdx *
777 DMA_NUM_CHANNELS) +
778 channelIdx,
779 dma_interrupt_handler,
780 IRQF_DISABLED, channel->name,
781 channel);
782 if (rc != 0) {
783 printk(KERN_ERR
784 "request_irq for IRQ_DMA%dC%d failed\n",
785 controllerIdx, channelIdx);
786 }
787 }
788 }
789 }
790
791 /* Create /proc/dma/channels and /proc/dma/devices */
792
793 gDmaDir = proc_mkdir("dma", NULL);
794
795 if (gDmaDir == NULL) {
796 printk(KERN_ERR "Unable to create /proc/dma\n");
797 } else {
798 create_proc_read_entry("channels", 0, gDmaDir,
799 dma_proc_read_channels, NULL);
800 create_proc_read_entry("devices", 0, gDmaDir,
801 dma_proc_read_devices, NULL);
802 }
803
804out:
805
806 up(&gDMA.lock);
807
808 return rc;
809}
810
811/****************************************************************************/
812/**
813* Reserves a channel for use with @a dev. If the device is setup to use
814* a shared channel, then this function will block until a free channel
815* becomes available.
816*
817* @return
818* >= 0 - A valid DMA Handle.
819* -EBUSY - Device is currently being used.
820* -ENODEV - Device handed in is invalid.
821*/
822/****************************************************************************/
823
824#if (DMA_DEBUG_TRACK_RESERVATION)
825DMA_Handle_t dma_request_channel_dbg
826 (DMA_Device_t dev, const char *fileName, int lineNum)
827#else
828DMA_Handle_t dma_request_channel(DMA_Device_t dev)
829#endif
830{
831 DMA_Handle_t handle;
832 DMA_DeviceAttribute_t *devAttr;
833 DMA_Channel_t *channel;
834 int controllerIdx;
835 int controllerIdx2;
836 int channelIdx;
837
838 if (down_interruptible(&gDMA.lock) < 0) {
839 return -ERESTARTSYS;
840 }
841
842 if ((dev < 0) || (dev >= DMA_NUM_DEVICE_ENTRIES)) {
843 handle = -ENODEV;
844 goto out;
845 }
846 devAttr = &DMA_gDeviceAttribute[dev];
847
848#if (DMA_DEBUG_TRACK_RESERVATION)
849 {
850 char *s;
851
852 s = strrchr(fileName, '/');
853 if (s != NULL) {
854 fileName = s + 1;
855 }
856 }
857#endif
858 if ((devAttr->flags & DMA_DEVICE_FLAG_IN_USE) != 0) {
859 /* This device has already been requested and not been freed */
860
861 printk(KERN_ERR "%s: device %s is already requested\n",
862 __func__, devAttr->name);
863 handle = -EBUSY;
864 goto out;
865 }
866
867 if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
868 /* This device has a dedicated channel. */
869
870 channel =
871 &gDMA.controller[devAttr->dedicatedController].
872 channel[devAttr->dedicatedChannel];
873 if ((channel->flags & DMA_CHANNEL_FLAG_IN_USE) != 0) {
874 handle = -EBUSY;
875 goto out;
876 }
877
878 channel->flags |= DMA_CHANNEL_FLAG_IN_USE;
879 devAttr->flags |= DMA_DEVICE_FLAG_IN_USE;
880
881#if (DMA_DEBUG_TRACK_RESERVATION)
882 channel->fileName = fileName;
883 channel->lineNum = lineNum;
884#endif
885 handle =
886 MAKE_HANDLE(devAttr->dedicatedController,
887 devAttr->dedicatedChannel);
888 goto out;
889 }
890
891 /* This device needs to use one of the shared channels. */
892
893 handle = DMA_INVALID_HANDLE;
894 while (handle == DMA_INVALID_HANDLE) {
895 /* Scan through the shared channels and see if one is available */
896
897 for (controllerIdx2 = 0; controllerIdx2 < DMA_NUM_CONTROLLERS;
898 controllerIdx2++) {
899 /* Check to see if we should try on controller 1 first. */
900
901 controllerIdx = controllerIdx2;
902 if ((devAttr->
903 flags & DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST) != 0) {
904 controllerIdx = 1 - controllerIdx;
905 }
906
907 /* See if the device is available on the controller being tested */
908
909 if ((devAttr->
910 flags & (DMA_DEVICE_FLAG_ON_DMA0 << controllerIdx))
911 != 0) {
912 for (channelIdx = 0;
913 channelIdx < DMA_NUM_CHANNELS;
914 channelIdx++) {
915 channel =
916 &gDMA.controller[controllerIdx].
917 channel[channelIdx];
918
919 if (((channel->
920 flags &
921 DMA_CHANNEL_FLAG_IS_DEDICATED) ==
922 0)
923 &&
924 ((channel->
925 flags & DMA_CHANNEL_FLAG_IN_USE)
926 == 0)) {
927 if (((channel->
928 flags &
929 DMA_CHANNEL_FLAG_LARGE_FIFO)
930 != 0)
931 &&
932 ((devAttr->
933 flags &
934 DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO)
935 == 0)) {
936 /* This channel is a large fifo - don't tie it up */
937 /* with devices that we don't want using it. */
938
939 continue;
940 }
941
942 channel->flags |=
943 DMA_CHANNEL_FLAG_IN_USE;
944 channel->devType = dev;
945 devAttr->flags |=
946 DMA_DEVICE_FLAG_IN_USE;
947
948#if (DMA_DEBUG_TRACK_RESERVATION)
949 channel->fileName = fileName;
950 channel->lineNum = lineNum;
951#endif
952 handle =
953 MAKE_HANDLE(controllerIdx,
954 channelIdx);
955
956 /* Now that we've reserved the channel - we can go ahead and configure it */
957
958 if (ConfigChannel(handle) != 0) {
959 handle = -EIO;
960 printk(KERN_ERR
961 "dma_request_channel: ConfigChannel failed\n");
962 }
963 goto out;
964 }
965 }
966 }
967 }
968
969 /* No channels are currently available. Let's wait for one to free up. */
970
971 {
972 DEFINE_WAIT(wait);
973
974 prepare_to_wait(&gDMA.freeChannelQ, &wait,
975 TASK_INTERRUPTIBLE);
976 up(&gDMA.lock);
977 schedule();
978 finish_wait(&gDMA.freeChannelQ, &wait);
979
980 if (signal_pending(current)) {
981 /* We don't currently hold gDMA.lock, so we return directly */
982
983 return -ERESTARTSYS;
984 }
985 }
986
987 if (down_interruptible(&gDMA.lock)) {
988 return -ERESTARTSYS;
989 }
990 }
991
992out:
993 up(&gDMA.lock);
994
995 return handle;
996}
997
998/* Create both _dbg and non _dbg functions for modules. */
999
1000#if (DMA_DEBUG_TRACK_RESERVATION)
1001#undef dma_request_channel
1002DMA_Handle_t dma_request_channel(DMA_Device_t dev)
1003{
1004 return dma_request_channel_dbg(dev, __FILE__, __LINE__);
1005}
1006
1007EXPORT_SYMBOL(dma_request_channel_dbg);
1008#endif
1009EXPORT_SYMBOL(dma_request_channel);
1010
1011/****************************************************************************/
1012/**
1013* Frees a previously allocated DMA Handle.
1014*/
1015/****************************************************************************/
1016
1017int dma_free_channel(DMA_Handle_t handle /* DMA handle. */
1018 ) {
1019 int rc = 0;
1020 DMA_Channel_t *channel;
1021 DMA_DeviceAttribute_t *devAttr;
1022
1023 if (down_interruptible(&gDMA.lock) < 0) {
1024 return -ERESTARTSYS;
1025 }
1026
1027 channel = HandleToChannel(handle);
1028 if (channel == NULL) {
1029 rc = -EINVAL;
1030 goto out;
1031 }
1032
1033 devAttr = &DMA_gDeviceAttribute[channel->devType];
1034
1035 if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) == 0) {
1036 channel->lastDevType = channel->devType;
1037 channel->devType = DMA_DEVICE_NONE;
1038 }
1039 channel->flags &= ~DMA_CHANNEL_FLAG_IN_USE;
1040 devAttr->flags &= ~DMA_DEVICE_FLAG_IN_USE;
1041
1042out:
1043 up(&gDMA.lock);
1044
1045 wake_up_interruptible(&gDMA.freeChannelQ);
1046
1047 return rc;
1048}
1049
1050EXPORT_SYMBOL(dma_free_channel);
1051
1052/****************************************************************************/
1053/**
1054* Determines if a given device has been configured as using a shared
1055* channel.
1056*
1057* @return
1058* 0 Device uses a dedicated channel
1059* > zero Device uses a shared channel
1060* < zero Error code
1061*/
1062/****************************************************************************/
1063
1064int dma_device_is_channel_shared(DMA_Device_t device /* Device to check. */
1065 ) {
1066 DMA_DeviceAttribute_t *devAttr;
1067
1068 if (!IsDeviceValid(device)) {
1069 return -ENODEV;
1070 }
1071 devAttr = &DMA_gDeviceAttribute[device];
1072
1073 return ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) == 0);
1074}
1075
1076EXPORT_SYMBOL(dma_device_is_channel_shared);
1077
1078/****************************************************************************/
1079/**
1080* Allocates buffers for the descriptors. This is normally done automatically
1081* but needs to be done explicitly when initiating a dma from interrupt
1082* context.
1083*
1084* @return
1085* 0 Descriptors were allocated successfully
1086* -EINVAL Invalid device type for this kind of transfer
1087* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
1088* -ENOMEM Memory exhausted
1089*/
1090/****************************************************************************/
1091
1092int dma_alloc_descriptors(DMA_Handle_t handle, /* DMA Handle */
1093 dmacHw_TRANSFER_TYPE_e transferType, /* Type of transfer being performed */
1094 dma_addr_t srcData, /* Place to get data to write to device */
1095 dma_addr_t dstData, /* Pointer to device data address */
1096 size_t numBytes /* Number of bytes to transfer to the device */
1097 ) {
1098 DMA_Channel_t *channel;
1099 DMA_DeviceAttribute_t *devAttr;
1100 int numDescriptors;
1101 size_t ringBytesRequired;
1102 int rc = 0;
1103
1104 channel = HandleToChannel(handle);
1105 if (channel == NULL) {
1106 return -ENODEV;
1107 }
1108
1109 devAttr = &DMA_gDeviceAttribute[channel->devType];
1110
1111 if (devAttr->config.transferType != transferType) {
1112 return -EINVAL;
1113 }
1114
1115 /* Figure out how many descriptors we need. */
1116
1117 /* printk("srcData: 0x%08x dstData: 0x%08x, numBytes: %d\n", */
1118 /* srcData, dstData, numBytes); */
1119
1120 numDescriptors = dmacHw_calculateDescriptorCount(&devAttr->config,
1121 (void *)srcData,
1122 (void *)dstData,
1123 numBytes);
1124 if (numDescriptors < 0) {
1125 printk(KERN_ERR "%s: dmacHw_calculateDescriptorCount failed\n",
1126 __func__);
1127 return -EINVAL;
1128 }
1129
1130 /* Check to see if we can reuse the existing descriptor ring, or if we need to allocate */
1131 /* a new one. */
1132
1133 ringBytesRequired = dmacHw_descriptorLen(numDescriptors);
1134
1135 /* printk("ringBytesRequired: %d\n", ringBytesRequired); */
1136
1137 if (ringBytesRequired > devAttr->ring.bytesAllocated) {
1138 /* Make sure that this code path is never taken from interrupt context. */
1139 /* It's OK for an interrupt to initiate a DMA transfer, but the descriptor */
1140 /* allocation needs to have already been done. */
1141
1142 might_sleep();
1143
1144 /* Free the old descriptor ring and allocate a new one. */
1145
1146 dma_free_descriptor_ring(&devAttr->ring);
1147
1148 /* And allocate a new one. */
1149
1150 rc =
1151 dma_alloc_descriptor_ring(&devAttr->ring,
1152 numDescriptors);
1153 if (rc < 0) {
1154 printk(KERN_ERR
1155 "%s: dma_alloc_descriptor_ring(%d) failed\n",
1156 __func__, numDescriptors);
1157 return rc;
1158 }
1159 /* Setup the descriptor for this transfer */
1160
1161 if (dmacHw_initDescriptor(devAttr->ring.virtAddr,
1162 devAttr->ring.physAddr,
1163 devAttr->ring.bytesAllocated,
1164 numDescriptors) < 0) {
1165 printk(KERN_ERR "%s: dmacHw_initDescriptor failed\n",
1166 __func__);
1167 return -EINVAL;
1168 }
1169 } else {
1170 /* We've already got enough ring buffer allocated. All we need to do is reset */
1171 /* any control information, just in case the previous DMA was stopped. */
1172
1173 dmacHw_resetDescriptorControl(devAttr->ring.virtAddr);
1174 }
1175
1176 /* dma_alloc/free both set the prevSrc/DstData to 0. If they happen to be the same */
1177 /* as last time, then we don't need to call setDataDescriptor again. */
1178
1179 if (dmacHw_setDataDescriptor(&devAttr->config,
1180 devAttr->ring.virtAddr,
1181 (void *)srcData,
1182 (void *)dstData, numBytes) < 0) {
1183 printk(KERN_ERR "%s: dmacHw_setDataDescriptor failed\n",
1184 __func__);
1185 return -EINVAL;
1186 }
1187
1188 /* Remember the critical information for this transfer so that we can eliminate */
1189 /* another call to dma_alloc_descriptors if the caller reuses the same buffers */
1190
1191 devAttr->prevSrcData = srcData;
1192 devAttr->prevDstData = dstData;
1193 devAttr->prevNumBytes = numBytes;
1194
1195 return 0;
1196}
1197
1198EXPORT_SYMBOL(dma_alloc_descriptors);
1199
1200/****************************************************************************/
1201/**
1202* Allocates and sets up descriptors for a double buffered circular buffer.
1203*
1204* This is primarily intended to be used for things like the ingress samples
1205* from a microphone.
1206*
1207* @return
1208* > 0 Number of descriptors actually allocated.
1209* -EINVAL Invalid device type for this kind of transfer
1210* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
1211* -ENOMEM Memory exhausted
1212*/
1213/****************************************************************************/
1214
1215int dma_alloc_double_dst_descriptors(DMA_Handle_t handle, /* DMA Handle */
1216 dma_addr_t srcData, /* Physical address of source data */
1217 dma_addr_t dstData1, /* Physical address of first destination buffer */
1218 dma_addr_t dstData2, /* Physical address of second destination buffer */
1219 size_t numBytes /* Number of bytes in each destination buffer */
1220 ) {
1221 DMA_Channel_t *channel;
1222 DMA_DeviceAttribute_t *devAttr;
1223 int numDst1Descriptors;
1224 int numDst2Descriptors;
1225 int numDescriptors;
1226 size_t ringBytesRequired;
1227 int rc = 0;
1228
1229 channel = HandleToChannel(handle);
1230 if (channel == NULL) {
1231 return -ENODEV;
1232 }
1233
1234 devAttr = &DMA_gDeviceAttribute[channel->devType];
1235
1236 /* Figure out how many descriptors we need. */
1237
1238 /* printk("srcData: 0x%08x dstData: 0x%08x, numBytes: %d\n", */
1239 /* srcData, dstData, numBytes); */
1240
1241 numDst1Descriptors =
1242 dmacHw_calculateDescriptorCount(&devAttr->config, (void *)srcData,
1243 (void *)dstData1, numBytes);
1244 if (numDst1Descriptors < 0) {
1245 return -EINVAL;
1246 }
1247 numDst2Descriptors =
1248 dmacHw_calculateDescriptorCount(&devAttr->config, (void *)srcData,
1249 (void *)dstData2, numBytes);
1250 if (numDst2Descriptors < 0) {
1251 return -EINVAL;
1252 }
1253 numDescriptors = numDst1Descriptors + numDst2Descriptors;
1254 /* printk("numDescriptors: %d\n", numDescriptors); */
1255
1256 /* Check to see if we can reuse the existing descriptor ring, or if we need to allocate */
1257 /* a new one. */
1258
1259 ringBytesRequired = dmacHw_descriptorLen(numDescriptors);
1260
1261 /* printk("ringBytesRequired: %d\n", ringBytesRequired); */
1262
1263 if (ringBytesRequired > devAttr->ring.bytesAllocated) {
1264 /* Make sure that this code path is never taken from interrupt context. */
1265 /* It's OK for an interrupt to initiate a DMA transfer, but the descriptor */
1266 /* allocation needs to have already been done. */
1267
1268 might_sleep();
1269
1270 /* Free the old descriptor ring and allocate a new one. */
1271
1272 dma_free_descriptor_ring(&devAttr->ring);
1273
1274 /* And allocate a new one. */
1275
1276 rc =
1277 dma_alloc_descriptor_ring(&devAttr->ring,
1278 numDescriptors);
1279 if (rc < 0) {
1280 printk(KERN_ERR
1281 "%s: dma_alloc_descriptor_ring(%d) failed\n",
1282 __func__, ringBytesRequired);
1283 return rc;
1284 }
1285 }
1286
1287 /* Setup the descriptor for this transfer. Since this function is used with */
1288 /* CONTINUOUS DMA operations, we need to reinitialize every time, otherwise */
1289 /* setDataDescriptor will keep trying to append onto the end. */
1290
1291 if (dmacHw_initDescriptor(devAttr->ring.virtAddr,
1292 devAttr->ring.physAddr,
1293 devAttr->ring.bytesAllocated,
1294 numDescriptors) < 0) {
1295 printk(KERN_ERR "%s: dmacHw_initDescriptor failed\n", __func__);
1296 return -EINVAL;
1297 }
1298
1299 /* dma_alloc/free both set the prevSrc/DstData to 0. If they happen to be the same */
1300 /* as last time, then we don't need to call setDataDescriptor again. */
1301
1302 if (dmacHw_setDataDescriptor(&devAttr->config,
1303 devAttr->ring.virtAddr,
1304 (void *)srcData,
1305 (void *)dstData1, numBytes) < 0) {
1306 printk(KERN_ERR "%s: dmacHw_setDataDescriptor 1 failed\n",
1307 __func__);
1308 return -EINVAL;
1309 }
1310 if (dmacHw_setDataDescriptor(&devAttr->config,
1311 devAttr->ring.virtAddr,
1312 (void *)srcData,
1313 (void *)dstData2, numBytes) < 0) {
1314 printk(KERN_ERR "%s: dmacHw_setDataDescriptor 2 failed\n",
1315 __func__);
1316 return -EINVAL;
1317 }
1318
1319 /* You should use dma_start_transfer rather than dma_transfer_xxx so we don't */
1320 /* try to make the 'prev' variables right. */
1321
1322 devAttr->prevSrcData = 0;
1323 devAttr->prevDstData = 0;
1324 devAttr->prevNumBytes = 0;
1325
1326 return numDescriptors;
1327}
1328
1329EXPORT_SYMBOL(dma_alloc_double_dst_descriptors);
1330
1331/****************************************************************************/
1332/**
1333* Initiates a transfer when the descriptors have already been setup.
1334*
1335* This is a special case, and normally, the dma_transfer_xxx functions should
1336* be used.
1337*
1338* @return
1339* 0 Transfer was started successfully
1340* -ENODEV Invalid handle
1341*/
1342/****************************************************************************/
1343
1344int dma_start_transfer(DMA_Handle_t handle)
1345{
1346 DMA_Channel_t *channel;
1347 DMA_DeviceAttribute_t *devAttr;
1348
1349 channel = HandleToChannel(handle);
1350 if (channel == NULL) {
1351 return -ENODEV;
1352 }
1353 devAttr = &DMA_gDeviceAttribute[channel->devType];
1354
1355 dmacHw_initiateTransfer(channel->dmacHwHandle, &devAttr->config,
1356 devAttr->ring.virtAddr);
1357
1358 /* Since we got this far, everything went successfully */
1359
1360 return 0;
1361}
1362
1363EXPORT_SYMBOL(dma_start_transfer);
1364
1365/****************************************************************************/
1366/**
1367* Stops a previously started DMA transfer.
1368*
1369* @return
1370* 0 Transfer was stopped successfully
1371* -ENODEV Invalid handle
1372*/
1373/****************************************************************************/
1374
1375int dma_stop_transfer(DMA_Handle_t handle)
1376{
1377 DMA_Channel_t *channel;
1378
1379 channel = HandleToChannel(handle);
1380 if (channel == NULL) {
1381 return -ENODEV;
1382 }
1383
1384 dmacHw_stopTransfer(channel->dmacHwHandle);
1385
1386 return 0;
1387}
1388
1389EXPORT_SYMBOL(dma_stop_transfer);
1390
1391/****************************************************************************/
1392/**
1393* Waits for a DMA to complete by polling. This function is only intended
1394* to be used for testing. Interrupts should be used for most DMA operations.
1395*/
1396/****************************************************************************/
1397
1398int dma_wait_transfer_done(DMA_Handle_t handle)
1399{
1400 DMA_Channel_t *channel;
1401 dmacHw_TRANSFER_STATUS_e status;
1402
1403 channel = HandleToChannel(handle);
1404 if (channel == NULL) {
1405 return -ENODEV;
1406 }
1407
1408 while ((status =
1409 dmacHw_transferCompleted(channel->dmacHwHandle)) ==
1410 dmacHw_TRANSFER_STATUS_BUSY) {
1411 ;
1412 }
1413
1414 if (status == dmacHw_TRANSFER_STATUS_ERROR) {
1415 printk(KERN_ERR "%s: DMA transfer failed\n", __func__);
1416 return -EIO;
1417 }
1418 return 0;
1419}
1420
1421EXPORT_SYMBOL(dma_wait_transfer_done);
1422
1423/****************************************************************************/
1424/**
1425* Initiates a DMA, allocating the descriptors as required.
1426*
1427* @return
1428* 0 Transfer was started successfully
1429* -EINVAL Invalid device type for this kind of transfer
1430* (i.e. the device is _DEV_TO_MEM and not _MEM_TO_DEV)
1431*/
1432/****************************************************************************/
1433
1434int dma_transfer(DMA_Handle_t handle, /* DMA Handle */
1435 dmacHw_TRANSFER_TYPE_e transferType, /* Type of transfer being performed */
1436 dma_addr_t srcData, /* Place to get data to write to device */
1437 dma_addr_t dstData, /* Pointer to device data address */
1438 size_t numBytes /* Number of bytes to transfer to the device */
1439 ) {
1440 DMA_Channel_t *channel;
1441 DMA_DeviceAttribute_t *devAttr;
1442 int rc = 0;
1443
1444 channel = HandleToChannel(handle);
1445 if (channel == NULL) {
1446 return -ENODEV;
1447 }
1448
1449 devAttr = &DMA_gDeviceAttribute[channel->devType];
1450
1451 if (devAttr->config.transferType != transferType) {
1452 return -EINVAL;
1453 }
1454
1455 /* We keep track of the information about the previous request for this */
1456 /* device, and if the attributes match, then we can use the descriptors we setup */
1457 /* the last time, and not have to reinitialize everything. */
1458
1459 {
1460 rc =
1461 dma_alloc_descriptors(handle, transferType, srcData,
1462 dstData, numBytes);
1463 if (rc != 0) {
1464 return rc;
1465 }
1466 }
1467
1468 /* And kick off the transfer */
1469
1470 devAttr->numBytes = numBytes;
1471 devAttr->transferStartTime = timer_get_tick_count();
1472
1473 dmacHw_initiateTransfer(channel->dmacHwHandle, &devAttr->config,
1474 devAttr->ring.virtAddr);
1475
1476 /* Since we got this far, everything went successfully */
1477
1478 return 0;
1479}
1480
1481EXPORT_SYMBOL(dma_transfer);
1482
1483/****************************************************************************/
1484/**
1485* Set the callback function which will be called when a transfer completes.
1486* If a NULL callback function is set, then no callback will occur.
1487*
1488* @note @a devHandler will be called from IRQ context.
1489*
1490* @return
1491* 0 - Success
1492* -ENODEV - Device handed in is invalid.
1493*/
1494/****************************************************************************/
1495
1496int dma_set_device_handler(DMA_Device_t dev, /* Device to set the callback for. */
1497 DMA_DeviceHandler_t devHandler, /* Function to call when the DMA completes */
1498 void *userData /* Pointer which will be passed to devHandler. */
1499 ) {
1500 DMA_DeviceAttribute_t *devAttr;
1501 unsigned long flags;
1502
1503 if (!IsDeviceValid(dev)) {
1504 return -ENODEV;
1505 }
1506 devAttr = &DMA_gDeviceAttribute[dev];
1507
1508 local_irq_save(flags);
1509
1510 devAttr->userData = userData;
1511 devAttr->devHandler = devHandler;
1512
1513 local_irq_restore(flags);
1514
1515 return 0;
1516}
1517
1518EXPORT_SYMBOL(dma_set_device_handler);
diff --git a/arch/arm/mach-bcmring/dma_device.c b/arch/arm/mach-bcmring/dma_device.c
deleted file mode 100644
index ca0ad736870b..000000000000
--- a/arch/arm/mach-bcmring/dma_device.c
+++ /dev/null
@@ -1,593 +0,0 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file dma_device.c
18*
19* @brief private array of DMA_DeviceAttribute_t
20*/
21/****************************************************************************/
22
23DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES] = {
24 [DMA_DEVICE_MEM_TO_MEM] = /* MEM 2 MEM */
25 {
26 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
27 .name = "mem-to-mem",
28 .config = {
29 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
30 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
31 .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
32 .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
33 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
34 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
35 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
36 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
37 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
38 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
39 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
40
41 },
42 },
43 [DMA_DEVICE_VPM_MEM_TO_MEM] = /* VPM */
44 {
45 .flags = DMA_DEVICE_FLAG_IS_DEDICATED | DMA_DEVICE_FLAG_NO_ISR,
46 .name = "vpm",
47 .dedicatedController = 0,
48 .dedicatedChannel = 0,
49 /* reserve DMA0:0 for VPM */
50 },
51 [DMA_DEVICE_NAND_MEM_TO_MEM] = /* NAND */
52 {
53 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
54 .name = "nand",
55 .config = {
56 .srcPeripheralPort = 0,
57 .dstPeripheralPort = 0,
58 .srcStatusRegisterAddress = 0x00000000,
59 .dstStatusRegisterAddress = 0x00000000,
60 .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
61 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
62 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
63 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
64 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
65 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
66 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
67 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
68 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
69 .channelPriority = dmacHw_CHANNEL_PRIORITY_6,
70 },
71 },
72 [DMA_DEVICE_PIF_MEM_TO_DEV] = /* PIF TX */
73 {
74 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1
75 | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO
76 | DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST | DMA_DEVICE_FLAG_PORT_PER_DMAC,
77 .name = "pif_tx",
78 .dmacPort = {14, 5},
79 .config = {
80 .srcPeripheralPort = 0, /* SRC: memory */
81 /* dstPeripheralPort = 5 or 14 */
82 .srcStatusRegisterAddress = 0x00000000,
83 .dstStatusRegisterAddress = 0x00000000,
84 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
85 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
86 .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
87 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
88 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
89 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
90 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
91 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
92 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
93 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
94 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
95 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
96 .maxDataPerBlock = 16256,
97 },
98 },
99 [DMA_DEVICE_PIF_DEV_TO_MEM] = /* PIF RX */
100 {
101 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1
102 | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO
103 /* DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST */
104 | DMA_DEVICE_FLAG_PORT_PER_DMAC,
105 .name = "pif_rx",
106 .dmacPort = {14, 5},
107 .config = {
108 /* srcPeripheralPort = 5 or 14 */
109 .dstPeripheralPort = 0, /* DST: memory */
110 .srcStatusRegisterAddress = 0x00000000,
111 .dstStatusRegisterAddress = 0x00000000,
112 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
113 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
114 .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
115 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
116 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
117 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
118 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
119 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
120 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
121 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
122 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
123 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
124 .maxDataPerBlock = 16256,
125 },
126 },
127 [DMA_DEVICE_I2S0_DEV_TO_MEM] = /* I2S RX */
128 {
129 .flags = DMA_DEVICE_FLAG_ON_DMA0,
130 .name = "i2s0_rx",
131 .config = {
132 .srcPeripheralPort = 0, /* SRC: I2S0 */
133 .dstPeripheralPort = 0, /* DST: memory */
134 .srcStatusRegisterAddress = 0,
135 .dstStatusRegisterAddress = 0,
136 .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
137 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
138 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
139 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16,
140 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
141 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
142 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
143 .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
144 .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
145 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
146 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
147 .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
148 },
149 },
150 [DMA_DEVICE_I2S0_MEM_TO_DEV] = /* I2S TX */
151 {
152 .flags = DMA_DEVICE_FLAG_ON_DMA0,
153 .name = "i2s0_tx",
154 .config = {
155 .srcPeripheralPort = 0, /* SRC: memory */
156 .dstPeripheralPort = 1, /* DST: I2S0 */
157 .srcStatusRegisterAddress = 0,
158 .dstStatusRegisterAddress = 0,
159 .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
160 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
161 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
162 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
163 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16,
164 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
165 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
166 .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
167 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
168 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
169 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
170 .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
171 },
172 },
173 [DMA_DEVICE_I2S1_DEV_TO_MEM] = /* I2S1 RX */
174 {
175 .flags = DMA_DEVICE_FLAG_ON_DMA1,
176 .name = "i2s1_rx",
177 .config = {
178 .srcPeripheralPort = 2, /* SRC: I2S1 */
179 .dstPeripheralPort = 0, /* DST: memory */
180 .srcStatusRegisterAddress = 0,
181 .dstStatusRegisterAddress = 0,
182 .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
183 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
184 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
185 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16,
186 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
187 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
188 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
189 .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
190 .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
191 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
192 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
193 .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
194 },
195 },
196 [DMA_DEVICE_I2S1_MEM_TO_DEV] = /* I2S1 TX */
197 {
198 .flags = DMA_DEVICE_FLAG_ON_DMA1,
199 .name = "i2s1_tx",
200 .config = {
201 .srcPeripheralPort = 0, /* SRC: memory */
202 .dstPeripheralPort = 3, /* DST: I2S1 */
203 .srcStatusRegisterAddress = 0,
204 .dstStatusRegisterAddress = 0,
205 .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
206 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
207 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
208 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
209 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16,
210 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
211 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
212 .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
213 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
214 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
215 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
216 .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
217 },
218 },
219 [DMA_DEVICE_ESW_MEM_TO_DEV] = /* ESW TX */
220 {
221 .name = "esw_tx",
222 .flags = DMA_DEVICE_FLAG_IS_DEDICATED,
223 .dedicatedController = 1,
224 .dedicatedChannel = 3,
225 .config = {
226 .srcPeripheralPort = 0, /* SRC: memory */
227 .dstPeripheralPort = 1, /* DST: ESW (MTP) */
228 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
229 .errorInterrupt = dmacHw_INTERRUPT_DISABLE,
230 /* DMAx_AHB_SSTATARy */
231 .srcStatusRegisterAddress = 0x00000000,
232 /* DMAx_AHB_DSTATARy */
233 .dstStatusRegisterAddress = 0x30490010,
234 /* DMAx_AHB_CFGy */
235 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
236 /* DMAx_AHB_CTLy */
237 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
238 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
239 .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
240 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
241 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
242 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
243 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
244 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
245 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
246 },
247 },
248 [DMA_DEVICE_ESW_DEV_TO_MEM] = /* ESW RX */
249 {
250 .name = "esw_rx",
251 .flags = DMA_DEVICE_FLAG_IS_DEDICATED,
252 .dedicatedController = 1,
253 .dedicatedChannel = 2,
254 .config = {
255 .srcPeripheralPort = 0, /* SRC: ESW (PTM) */
256 .dstPeripheralPort = 0, /* DST: memory */
257 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
258 .errorInterrupt = dmacHw_INTERRUPT_DISABLE,
259 /* DMAx_AHB_SSTATARy */
260 .srcStatusRegisterAddress = 0x30480010,
261 /* DMAx_AHB_DSTATARy */
262 .dstStatusRegisterAddress = 0x00000000,
263 /* DMAx_AHB_CFGy */
264 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
265 /* DMAx_AHB_CTLy */
266 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
267 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
268 .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
269 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
270 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
271 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
272 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
273 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
274 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
275 },
276 },
277 [DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM] = /* APM Codec A Ingress */
278 {
279 .flags = DMA_DEVICE_FLAG_ON_DMA0,
280 .name = "apm_a_rx",
281 .config = {
282 .srcPeripheralPort = 2, /* SRC: Codec A Ingress FIFO */
283 .dstPeripheralPort = 0, /* DST: memory */
284 .srcStatusRegisterAddress = 0x00000000,
285 .dstStatusRegisterAddress = 0x00000000,
286 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
287 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
288 .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
289 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
290 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
291 .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
292 .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
293 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
294 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
295 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
296 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
297 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
298 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
299 .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
300 },
301 },
302 [DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV] = /* APM Codec A Egress */
303 {
304 .flags = DMA_DEVICE_FLAG_ON_DMA0,
305 .name = "apm_a_tx",
306 .config = {
307 .srcPeripheralPort = 0, /* SRC: memory */
308 .dstPeripheralPort = 3, /* DST: Codec A Egress FIFO */
309 .srcStatusRegisterAddress = 0x00000000,
310 .dstStatusRegisterAddress = 0x00000000,
311 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
312 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
313 .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
314 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
315 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
316 .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
317 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
318 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
319 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
320 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
321 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
322 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
323 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
324 .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
325 },
326 },
327 [DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM] = /* APM Codec B Ingress */
328 {
329 .flags = DMA_DEVICE_FLAG_ON_DMA0,
330 .name = "apm_b_rx",
331 .config = {
332 .srcPeripheralPort = 4, /* SRC: Codec B Ingress FIFO */
333 .dstPeripheralPort = 0, /* DST: memory */
334 .srcStatusRegisterAddress = 0x00000000,
335 .dstStatusRegisterAddress = 0x00000000,
336 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
337 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
338 .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
339 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
340 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
341 .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
342 .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
343 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
344 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
345 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
346 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
347 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
348 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
349 .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
350 },
351 },
352 [DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV] = /* APM Codec B Egress */
353 {
354 .flags = DMA_DEVICE_FLAG_ON_DMA0,
355 .name = "apm_b_tx",
356 .config = {
357 .srcPeripheralPort = 0, /* SRC: memory */
358 .dstPeripheralPort = 5, /* DST: Codec B Egress FIFO */
359 .srcStatusRegisterAddress = 0x00000000,
360 .dstStatusRegisterAddress = 0x00000000,
361 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
362 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
363 .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
364 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
365 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
366 .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
367 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
368 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
369 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
370 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
371 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
372 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
373 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
374 .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
375 },
376 },
377 [DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM] = /* APM Codec C Ingress */
378 {
379 .flags = DMA_DEVICE_FLAG_ON_DMA1,
380 .name = "apm_c_rx",
381 .config = {
382 .srcPeripheralPort = 4, /* SRC: Codec C Ingress FIFO */
383 .dstPeripheralPort = 0, /* DST: memory */
384 .srcStatusRegisterAddress = 0x00000000,
385 .dstStatusRegisterAddress = 0x00000000,
386 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
387 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
388 .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
389 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
390 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
391 .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
392 .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
393 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
394 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
395 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
396 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
397 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
398 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
399 .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
400 },
401 },
402 [DMA_DEVICE_APM_PCM0_DEV_TO_MEM] = /* PCM0 RX */
403 {
404 .flags = DMA_DEVICE_FLAG_ON_DMA0,
405 .name = "pcm0_rx",
406 .config = {
407 .srcPeripheralPort = 12, /* SRC: PCM0 */
408 .dstPeripheralPort = 0, /* DST: memory */
409 .srcStatusRegisterAddress = 0,
410 .dstStatusRegisterAddress = 0,
411 .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
412 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
413 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
414 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
415 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
416 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
417 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
418 .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
419 .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
420 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
421 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
422 .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
423 },
424 },
425 [DMA_DEVICE_APM_PCM0_MEM_TO_DEV] = /* PCM0 TX */
426 {
427 .flags = DMA_DEVICE_FLAG_ON_DMA0,
428 .name = "pcm0_tx",
429 .config = {
430 .srcPeripheralPort = 0, /* SRC: memory */
431 .dstPeripheralPort = 13, /* DST: PCM0 */
432 .srcStatusRegisterAddress = 0,
433 .dstStatusRegisterAddress = 0,
434 .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
435 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
436 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
437 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
438 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
439 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
440 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
441 .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
442 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
443 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
444 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
445 .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
446 },
447 },
448 [DMA_DEVICE_APM_PCM1_DEV_TO_MEM] = /* PCM1 RX */
449 {
450 .flags = DMA_DEVICE_FLAG_ON_DMA1,
451 .name = "pcm1_rx",
452 .config = {
453 .srcPeripheralPort = 14, /* SRC: PCM1 */
454 .dstPeripheralPort = 0, /* DST: memory */
455 .srcStatusRegisterAddress = 0,
456 .dstStatusRegisterAddress = 0,
457 .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
458 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
459 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
460 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
461 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
462 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
463 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
464 .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
465 .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
466 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
467 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
468 .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
469 },
470 },
471 [DMA_DEVICE_APM_PCM1_MEM_TO_DEV] = /* PCM1 TX */
472 {
473 .flags = DMA_DEVICE_FLAG_ON_DMA1,
474 .name = "pcm1_tx",
475 .config = {
476 .srcPeripheralPort = 0, /* SRC: memory */
477 .dstPeripheralPort = 15, /* DST: PCM1 */
478 .srcStatusRegisterAddress = 0,
479 .dstStatusRegisterAddress = 0,
480 .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
481 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
482 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
483 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
484 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
485 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
486 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
487 .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
488 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
489 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
490 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
491 .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
492 },
493 },
494 [DMA_DEVICE_SPUM_DEV_TO_MEM] = /* SPUM RX */
495 {
496 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
497 .name = "spum_rx",
498 .config = {
499 .srcPeripheralPort = 6, /* SRC: Codec A Ingress FIFO */
500 .dstPeripheralPort = 0, /* DST: memory */
501 .srcStatusRegisterAddress = 0x00000000,
502 .dstStatusRegisterAddress = 0x00000000,
503 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
504 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
505 .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
506 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
507 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
508 .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
509 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
510 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
511 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
512 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
513 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
514 /* Busrt size **MUST** be 16 for SPUM to work */
515 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16,
516 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16,
517 .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
518 /* on the RX side, SPU needs to be the flow controller */
519 .flowControler = dmacHw_FLOW_CONTROL_PERIPHERAL,
520 },
521 },
522 [DMA_DEVICE_SPUM_MEM_TO_DEV] = /* SPUM TX */
523 {
524 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
525 .name = "spum_tx",
526 .config = {
527 .srcPeripheralPort = 0, /* SRC: memory */
528 .dstPeripheralPort = 7, /* DST: SPUM */
529 .srcStatusRegisterAddress = 0x00000000,
530 .dstStatusRegisterAddress = 0x00000000,
531 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
532 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
533 .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
534 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
535 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
536 .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
537 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
538 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
539 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
540 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
541 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
542 /* Busrt size **MUST** be 16 for SPUM to work */
543 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16,
544 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16,
545 .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
546 },
547 },
548 [DMA_DEVICE_MEM_TO_VRAM] = /* MEM 2 VRAM */
549 {
550 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
551 .name = "mem-to-vram",
552 .config = {
553 .srcPeripheralPort = 0, /* SRC: memory */
554 .srcStatusRegisterAddress = 0x00000000,
555 .dstStatusRegisterAddress = 0x00000000,
556 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
557 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
558 .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
559 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
560 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
561 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
562 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
563 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
564 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
565 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
566 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
567 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
568 },
569 },
570 [DMA_DEVICE_VRAM_TO_MEM] = /* VRAM 2 MEM */
571 {
572 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
573 .name = "vram-to-mem",
574 .config = {
575 .dstPeripheralPort = 0, /* DST: memory */
576 .srcStatusRegisterAddress = 0x00000000,
577 .dstStatusRegisterAddress = 0x00000000,
578 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
579 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
580 .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
581 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
582 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
583 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
584 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
585 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
586 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
587 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
588 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
589 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
590 },
591 },
592};
593EXPORT_SYMBOL(DMA_gDeviceAttribute); /* primarily for dma-test.c */
diff --git a/arch/arm/mach-bcmring/include/mach/cfg_global.h b/arch/arm/mach-bcmring/include/mach/cfg_global.h
deleted file mode 100644
index 449133eacdf5..000000000000
--- a/arch/arm/mach-bcmring/include/mach/cfg_global.h
+++ /dev/null
@@ -1,51 +0,0 @@
1/*****************************************************************************
2* Copyright 2006 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#ifndef CFG_GLOBAL_DEFINES_H
16#define CFG_GLOBAL_DEFINES_H
17
18/* CHIP */
19#define BCM1103 1
20
21#define BCM1191 4
22#define BCM2153 5
23#define BCM2820 6
24
25#define BCM2826 8
26#define FPGA11107 9
27#define BCM11107 10
28#define BCM11109 11
29#define BCM11170 12
30#define BCM11110 13
31#define BCM11211 14
32
33/* CFG_GLOBAL_CHIP_FAMILY types */
34#define CFG_GLOBAL_CHIP_FAMILY_NONE 0
35#define CFG_GLOBAL_CHIP_FAMILY_BCM116X 2
36#define CFG_GLOBAL_CHIP_FAMILY_BCMRING 4
37#define CFG_GLOBAL_CHIP_FAMILY_BCM1103 8
38
39#define IMAGE_HEADER_SIZE_CHECKSUM 4
40#endif
41#ifndef _CFG_GLOBAL_H_
42#define _CFG_GLOBAL_H_
43
44#define CFG_GLOBAL_CHIP BCM11107
45#define CFG_GLOBAL_CHIP_FAMILY CFG_GLOBAL_CHIP_FAMILY_BCMRING
46#define CFG_GLOBAL_CHIP_REV 0xB0
47#define CFG_GLOBAL_RAM_SIZE 0x10000000
48#define CFG_GLOBAL_RAM_BASE 0x00000000
49#define CFG_GLOBAL_RAM_RESERVED_SIZE 0x000000
50
51#endif /* _CFG_GLOBAL_H_ */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap.h b/arch/arm/mach-bcmring/include/mach/csp/cap.h
deleted file mode 100644
index 30fa2d540630..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/cap.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*****************************************************************************
2* Copyright 2009 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#ifndef CAP_H
16#define CAP_H
17
18/* ---- Include Files ---------------------------------------------------- */
19/* ---- Public Constants and Types --------------------------------------- */
20typedef enum {
21 CAP_NOT_PRESENT = 0,
22 CAP_PRESENT
23} CAP_RC_T;
24
25typedef enum {
26 CAP_VPM,
27 CAP_ETH_PHY,
28 CAP_ETH_GMII,
29 CAP_ETH_SGMII,
30 CAP_USB,
31 CAP_TSC,
32 CAP_EHSS,
33 CAP_SDIO,
34 CAP_UARTB,
35 CAP_KEYPAD,
36 CAP_CLCD,
37 CAP_GE,
38 CAP_LEDM,
39 CAP_BBL,
40 CAP_VDEC,
41 CAP_PIF,
42 CAP_APM,
43 CAP_SPU,
44 CAP_PKA,
45 CAP_RNG,
46} CAP_CAPABILITY_T;
47
48typedef enum {
49 CAP_LCD_WVGA = 0,
50 CAP_LCD_VGA = 0x1,
51 CAP_LCD_WQVGA = 0x2,
52 CAP_LCD_QVGA = 0x3
53} CAP_LCD_RES_T;
54
55/* ---- Public Variable Externs ------------------------------------------ */
56/* ---- Public Function Prototypes --------------------------------------- */
57
58static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int index);
59static inline uint32_t cap_getMaxArmSpeedHz(void);
60static inline uint32_t cap_getMaxVpmSpeedHz(void);
61static inline CAP_LCD_RES_T cap_getMaxLcdRes(void);
62
63#endif
diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
deleted file mode 100644
index 0a89e0c63419..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
+++ /dev/null
@@ -1,409 +0,0 @@
1/*****************************************************************************
2* Copyright 2009 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#ifndef CAP_INLINE_H
16#define CAP_INLINE_H
17
18/* ---- Include Files ---------------------------------------------------- */
19#include <mach/csp/cap.h>
20#include <mach/cfg_global.h>
21
22/* ---- Public Constants and Types --------------------------------------- */
23#define CAP_CONFIG0_VPM_DIS 0x00000001
24#define CAP_CONFIG0_ETH_PHY0_DIS 0x00000002
25#define CAP_CONFIG0_ETH_PHY1_DIS 0x00000004
26#define CAP_CONFIG0_ETH_GMII0_DIS 0x00000008
27#define CAP_CONFIG0_ETH_GMII1_DIS 0x00000010
28#define CAP_CONFIG0_ETH_SGMII0_DIS 0x00000020
29#define CAP_CONFIG0_ETH_SGMII1_DIS 0x00000040
30#define CAP_CONFIG0_USB0_DIS 0x00000080
31#define CAP_CONFIG0_USB1_DIS 0x00000100
32#define CAP_CONFIG0_TSC_DIS 0x00000200
33#define CAP_CONFIG0_EHSS0_DIS 0x00000400
34#define CAP_CONFIG0_EHSS1_DIS 0x00000800
35#define CAP_CONFIG0_SDIO0_DIS 0x00001000
36#define CAP_CONFIG0_SDIO1_DIS 0x00002000
37#define CAP_CONFIG0_UARTB_DIS 0x00004000
38#define CAP_CONFIG0_KEYPAD_DIS 0x00008000
39#define CAP_CONFIG0_CLCD_DIS 0x00010000
40#define CAP_CONFIG0_GE_DIS 0x00020000
41#define CAP_CONFIG0_LEDM_DIS 0x00040000
42#define CAP_CONFIG0_BBL_DIS 0x00080000
43#define CAP_CONFIG0_VDEC_DIS 0x00100000
44#define CAP_CONFIG0_PIF_DIS 0x00200000
45#define CAP_CONFIG0_RESERVED1_DIS 0x00400000
46#define CAP_CONFIG0_RESERVED2_DIS 0x00800000
47
48#define CAP_CONFIG1_APMA_DIS 0x00000001
49#define CAP_CONFIG1_APMB_DIS 0x00000002
50#define CAP_CONFIG1_APMC_DIS 0x00000004
51#define CAP_CONFIG1_CLCD_RES_MASK 0x00000600
52#define CAP_CONFIG1_CLCD_RES_SHIFT 9
53#define CAP_CONFIG1_CLCD_RES_WVGA (CAP_LCD_WVGA << CAP_CONFIG1_CLCD_RES_SHIFT)
54#define CAP_CONFIG1_CLCD_RES_VGA (CAP_LCD_VGA << CAP_CONFIG1_CLCD_RES_SHIFT)
55#define CAP_CONFIG1_CLCD_RES_WQVGA (CAP_LCD_WQVGA << CAP_CONFIG1_CLCD_RES_SHIFT)
56#define CAP_CONFIG1_CLCD_RES_QVGA (CAP_LCD_QVGA << CAP_CONFIG1_CLCD_RES_SHIFT)
57
58#define CAP_CONFIG2_SPU_DIS 0x00000010
59#define CAP_CONFIG2_PKA_DIS 0x00000020
60#define CAP_CONFIG2_RNG_DIS 0x00000080
61
62#if (CFG_GLOBAL_CHIP == BCM11107)
63#define capConfig0 0
64#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA
65#define capConfig2 0
66#define CAP_APM_MAX_NUM_CHANS 3
67#elif (CFG_GLOBAL_CHIP == FPGA11107)
68#define capConfig0 0
69#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA
70#define capConfig2 0
71#define CAP_APM_MAX_NUM_CHANS 3
72#elif (CFG_GLOBAL_CHIP == BCM11109)
73#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
74#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA)
75#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
76#define CAP_APM_MAX_NUM_CHANS 2
77#elif (CFG_GLOBAL_CHIP == BCM11170)
78#define capConfig0 (CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_USB0_DIS | CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_CLCD_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
79#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA)
80#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
81#define CAP_APM_MAX_NUM_CHANS 2
82#elif (CFG_GLOBAL_CHIP == BCM11110)
83#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
84#define capConfig1 CAP_CONFIG1_APMC_DIS
85#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
86#define CAP_APM_MAX_NUM_CHANS 2
87#elif (CFG_GLOBAL_CHIP == BCM11211)
88#define capConfig0 (CAP_CONFIG0_ETH_PHY0_DIS | CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_ETH_SGMII0_DIS | CAP_CONFIG0_ETH_SGMII1_DIS | CAP_CONFIG0_CLCD_DIS)
89#define capConfig1 CAP_CONFIG1_APMC_DIS
90#define capConfig2 0
91#define CAP_APM_MAX_NUM_CHANS 2
92#else
93#error CFG_GLOBAL_CHIP type capabilities not defined
94#endif
95
96#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107))
97#define CAP_HW_CFG_ARM_CLK_HZ 500000000
98#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
99#define CAP_HW_CFG_ARM_CLK_HZ 300000000
100#elif (CFG_GLOBAL_CHIP == BCM11211)
101#define CAP_HW_CFG_ARM_CLK_HZ 666666666
102#else
103#error CFG_GLOBAL_CHIP type capabilities not defined
104#endif
105
106#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || (CFG_GLOBAL_CHIP == FPGA11107))
107#define CAP_HW_CFG_VPM_CLK_HZ 333333333
108#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
109#define CAP_HW_CFG_VPM_CLK_HZ 200000000
110#else
111#error CFG_GLOBAL_CHIP type capabilities not defined
112#endif
113
114/* ---- Public Variable Externs ------------------------------------------ */
115/* ---- Public Function Prototypes --------------------------------------- */
116
117/****************************************************************************
118* cap_isPresent -
119*
120* PURPOSE:
121* Determines if the chip has a certain capability present
122*
123* PARAMETERS:
124* capability - type of capability to determine if present
125*
126* RETURNS:
127* CAP_PRESENT or CAP_NOT_PRESENT
128****************************************************************************/
129static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int index)
130{
131 CAP_RC_T returnVal = CAP_NOT_PRESENT;
132
133 switch (capability) {
134 case CAP_VPM:
135 {
136 if (!(capConfig0 & CAP_CONFIG0_VPM_DIS)) {
137 returnVal = CAP_PRESENT;
138 }
139 }
140 break;
141
142 case CAP_ETH_PHY:
143 {
144 if ((index == 0)
145 && (!(capConfig0 & CAP_CONFIG0_ETH_PHY0_DIS))) {
146 returnVal = CAP_PRESENT;
147 }
148 if ((index == 1)
149 && (!(capConfig0 & CAP_CONFIG0_ETH_PHY1_DIS))) {
150 returnVal = CAP_PRESENT;
151 }
152 }
153 break;
154
155 case CAP_ETH_GMII:
156 {
157 if ((index == 0)
158 && (!(capConfig0 & CAP_CONFIG0_ETH_GMII0_DIS))) {
159 returnVal = CAP_PRESENT;
160 }
161 if ((index == 1)
162 && (!(capConfig0 & CAP_CONFIG0_ETH_GMII1_DIS))) {
163 returnVal = CAP_PRESENT;
164 }
165 }
166 break;
167
168 case CAP_ETH_SGMII:
169 {
170 if ((index == 0)
171 && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII0_DIS))) {
172 returnVal = CAP_PRESENT;
173 }
174 if ((index == 1)
175 && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII1_DIS))) {
176 returnVal = CAP_PRESENT;
177 }
178 }
179 break;
180
181 case CAP_USB:
182 {
183 if ((index == 0)
184 && (!(capConfig0 & CAP_CONFIG0_USB0_DIS))) {
185 returnVal = CAP_PRESENT;
186 }
187 if ((index == 1)
188 && (!(capConfig0 & CAP_CONFIG0_USB1_DIS))) {
189 returnVal = CAP_PRESENT;
190 }
191 }
192 break;
193
194 case CAP_TSC:
195 {
196 if (!(capConfig0 & CAP_CONFIG0_TSC_DIS)) {
197 returnVal = CAP_PRESENT;
198 }
199 }
200 break;
201
202 case CAP_EHSS:
203 {
204 if ((index == 0)
205 && (!(capConfig0 & CAP_CONFIG0_EHSS0_DIS))) {
206 returnVal = CAP_PRESENT;
207 }
208 if ((index == 1)
209 && (!(capConfig0 & CAP_CONFIG0_EHSS1_DIS))) {
210 returnVal = CAP_PRESENT;
211 }
212 }
213 break;
214
215 case CAP_SDIO:
216 {
217 if ((index == 0)
218 && (!(capConfig0 & CAP_CONFIG0_SDIO0_DIS))) {
219 returnVal = CAP_PRESENT;
220 }
221 if ((index == 1)
222 && (!(capConfig0 & CAP_CONFIG0_SDIO1_DIS))) {
223 returnVal = CAP_PRESENT;
224 }
225 }
226 break;
227
228 case CAP_UARTB:
229 {
230 if (!(capConfig0 & CAP_CONFIG0_UARTB_DIS)) {
231 returnVal = CAP_PRESENT;
232 }
233 }
234 break;
235
236 case CAP_KEYPAD:
237 {
238 if (!(capConfig0 & CAP_CONFIG0_KEYPAD_DIS)) {
239 returnVal = CAP_PRESENT;
240 }
241 }
242 break;
243
244 case CAP_CLCD:
245 {
246 if (!(capConfig0 & CAP_CONFIG0_CLCD_DIS)) {
247 returnVal = CAP_PRESENT;
248 }
249 }
250 break;
251
252 case CAP_GE:
253 {
254 if (!(capConfig0 & CAP_CONFIG0_GE_DIS)) {
255 returnVal = CAP_PRESENT;
256 }
257 }
258 break;
259
260 case CAP_LEDM:
261 {
262 if (!(capConfig0 & CAP_CONFIG0_LEDM_DIS)) {
263 returnVal = CAP_PRESENT;
264 }
265 }
266 break;
267
268 case CAP_BBL:
269 {
270 if (!(capConfig0 & CAP_CONFIG0_BBL_DIS)) {
271 returnVal = CAP_PRESENT;
272 }
273 }
274 break;
275
276 case CAP_VDEC:
277 {
278 if (!(capConfig0 & CAP_CONFIG0_VDEC_DIS)) {
279 returnVal = CAP_PRESENT;
280 }
281 }
282 break;
283
284 case CAP_PIF:
285 {
286 if (!(capConfig0 & CAP_CONFIG0_PIF_DIS)) {
287 returnVal = CAP_PRESENT;
288 }
289 }
290 break;
291
292 case CAP_APM:
293 {
294 if ((index == 0)
295 && (!(capConfig1 & CAP_CONFIG1_APMA_DIS))) {
296 returnVal = CAP_PRESENT;
297 }
298 if ((index == 1)
299 && (!(capConfig1 & CAP_CONFIG1_APMB_DIS))) {
300 returnVal = CAP_PRESENT;
301 }
302 if ((index == 2)
303 && (!(capConfig1 & CAP_CONFIG1_APMC_DIS))) {
304 returnVal = CAP_PRESENT;
305 }
306 }
307 break;
308
309 case CAP_SPU:
310 {
311 if (!(capConfig2 & CAP_CONFIG2_SPU_DIS)) {
312 returnVal = CAP_PRESENT;
313 }
314 }
315 break;
316
317 case CAP_PKA:
318 {
319 if (!(capConfig2 & CAP_CONFIG2_PKA_DIS)) {
320 returnVal = CAP_PRESENT;
321 }
322 }
323 break;
324
325 case CAP_RNG:
326 {
327 if (!(capConfig2 & CAP_CONFIG2_RNG_DIS)) {
328 returnVal = CAP_PRESENT;
329 }
330 }
331 break;
332
333 default:
334 {
335 }
336 break;
337 }
338 return returnVal;
339}
340
341/****************************************************************************
342* cap_getMaxArmSpeedHz -
343*
344* PURPOSE:
345* Determines the maximum speed of the ARM CPU
346*
347* PARAMETERS:
348* none
349*
350* RETURNS:
351* clock speed in Hz that the ARM processor is able to run at
352****************************************************************************/
353static inline uint32_t cap_getMaxArmSpeedHz(void)
354{
355#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107))
356 return 500000000;
357#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
358 return 300000000;
359#elif (CFG_GLOBAL_CHIP == BCM11211)
360 return 666666666;
361#else
362#error CFG_GLOBAL_CHIP type capabilities not defined
363#endif
364}
365
366/****************************************************************************
367* cap_getMaxVpmSpeedHz -
368*
369* PURPOSE:
370* Determines the maximum speed of the VPM
371*
372* PARAMETERS:
373* none
374*
375* RETURNS:
376* clock speed in Hz that the VPM is able to run at
377****************************************************************************/
378static inline uint32_t cap_getMaxVpmSpeedHz(void)
379{
380#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || (CFG_GLOBAL_CHIP == FPGA11107))
381 return 333333333;
382#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
383 return 200000000;
384#else
385#error CFG_GLOBAL_CHIP type capabilities not defined
386#endif
387}
388
389/****************************************************************************
390* cap_getMaxLcdRes -
391*
392* PURPOSE:
393* Determines the maximum LCD resolution capabilities
394*
395* PARAMETERS:
396* none
397*
398* RETURNS:
399* CAP_LCD_WVGA, CAP_LCD_VGA, CAP_LCD_WQVGA or CAP_LCD_QVGA
400*
401****************************************************************************/
402static inline CAP_LCD_RES_T cap_getMaxLcdRes(void)
403{
404 return (CAP_LCD_RES_T)
405 ((capConfig1 & CAP_CONFIG1_CLCD_RES_MASK) >>
406 CAP_CONFIG1_CLCD_RES_SHIFT);
407}
408
409#endif
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
deleted file mode 100644
index 39f09cb89208..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
+++ /dev/null
@@ -1,1123 +0,0 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#ifndef CHIPC_DEF_H
16#define CHIPC_DEF_H
17
18/* ---- Include Files ----------------------------------------------------- */
19
20#include <linux/types.h>
21#include <linux/errno.h>
22#include <mach/csp/reg.h>
23#include <mach/csp/chipcHw_reg.h>
24
25/* ---- Public Constants and Types ---------------------------------------- */
26
27/* Set 1 to configure DDR/VPM phase alignment by HW */
28#define chipcHw_DDR_HW_PHASE_ALIGN 0
29#define chipcHw_VPM_HW_PHASE_ALIGN 0
30
31typedef uint32_t chipcHw_freq;
32
33/* Configurable miscellaneous clocks */
34typedef enum {
35 chipcHw_CLOCK_DDR, /* DDR PHY Clock */
36 chipcHw_CLOCK_ARM, /* ARM Clock */
37 chipcHw_CLOCK_ESW, /* Ethernet Switch Clock */
38 chipcHw_CLOCK_VPM, /* VPM Clock */
39 chipcHw_CLOCK_ESW125, /* Ethernet MII Clock */
40 chipcHw_CLOCK_UART, /* UART Clock */
41 chipcHw_CLOCK_SDIO0, /* SDIO 0 Clock */
42 chipcHw_CLOCK_SDIO1, /* SDIO 1 Clock */
43 chipcHw_CLOCK_SPI, /* SPI Clock */
44 chipcHw_CLOCK_ETM, /* ARM ETM Clock */
45
46 chipcHw_CLOCK_BUS, /* BUS Clock */
47 chipcHw_CLOCK_OTP, /* OTP Clock */
48 chipcHw_CLOCK_I2C, /* I2C Host Clock */
49 chipcHw_CLOCK_I2S0, /* I2S 0 Host Clock */
50 chipcHw_CLOCK_RTBUS, /* DDR PHY Configuration Clock */
51 chipcHw_CLOCK_APM100, /* APM100 Clock */
52 chipcHw_CLOCK_TSC, /* Touch screen Clock */
53 chipcHw_CLOCK_LED, /* LED Clock */
54
55 chipcHw_CLOCK_USB, /* USB Clock */
56 chipcHw_CLOCK_LCD, /* LCD CLock */
57 chipcHw_CLOCK_APM, /* APM Clock */
58
59 chipcHw_CLOCK_I2S1, /* I2S 1 Host Clock */
60} chipcHw_CLOCK_e;
61
62/* System booting strap options */
63typedef enum {
64 chipcHw_BOOT_DEVICE_UART = chipcHw_STRAPS_BOOT_DEVICE_UART,
65 chipcHw_BOOT_DEVICE_SERIAL_FLASH =
66 chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH,
67 chipcHw_BOOT_DEVICE_NOR_FLASH_16 =
68 chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16,
69 chipcHw_BOOT_DEVICE_NAND_FLASH_8 =
70 chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8,
71 chipcHw_BOOT_DEVICE_NAND_FLASH_16 =
72 chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16
73} chipcHw_BOOT_DEVICE_e;
74
75/* System booting modes */
76typedef enum {
77 chipcHw_BOOT_MODE_NORMAL = chipcHw_STRAPS_BOOT_MODE_NORMAL,
78 chipcHw_BOOT_MODE_DBG_SW = chipcHw_STRAPS_BOOT_MODE_DBG_SW,
79 chipcHw_BOOT_MODE_DBG_BOOT = chipcHw_STRAPS_BOOT_MODE_DBG_BOOT,
80 chipcHw_BOOT_MODE_NORMAL_QUIET = chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET
81} chipcHw_BOOT_MODE_e;
82
83/* NAND Flash page size strap options */
84typedef enum {
85 chipcHw_NAND_PAGESIZE_512 = chipcHw_STRAPS_NAND_PAGESIZE_512,
86 chipcHw_NAND_PAGESIZE_2048 = chipcHw_STRAPS_NAND_PAGESIZE_2048,
87 chipcHw_NAND_PAGESIZE_4096 = chipcHw_STRAPS_NAND_PAGESIZE_4096,
88 chipcHw_NAND_PAGESIZE_EXT = chipcHw_STRAPS_NAND_PAGESIZE_EXT
89} chipcHw_NAND_PAGESIZE_e;
90
91/* GPIO Pin function */
92typedef enum {
93 chipcHw_GPIO_FUNCTION_KEYPAD = chipcHw_REG_GPIO_MUX_KEYPAD,
94 chipcHw_GPIO_FUNCTION_I2CH = chipcHw_REG_GPIO_MUX_I2CH,
95 chipcHw_GPIO_FUNCTION_SPI = chipcHw_REG_GPIO_MUX_SPI,
96 chipcHw_GPIO_FUNCTION_UART = chipcHw_REG_GPIO_MUX_UART,
97 chipcHw_GPIO_FUNCTION_LEDMTXP = chipcHw_REG_GPIO_MUX_LEDMTXP,
98 chipcHw_GPIO_FUNCTION_LEDMTXS = chipcHw_REG_GPIO_MUX_LEDMTXS,
99 chipcHw_GPIO_FUNCTION_SDIO0 = chipcHw_REG_GPIO_MUX_SDIO0,
100 chipcHw_GPIO_FUNCTION_SDIO1 = chipcHw_REG_GPIO_MUX_SDIO1,
101 chipcHw_GPIO_FUNCTION_PCM = chipcHw_REG_GPIO_MUX_PCM,
102 chipcHw_GPIO_FUNCTION_I2S = chipcHw_REG_GPIO_MUX_I2S,
103 chipcHw_GPIO_FUNCTION_ETM = chipcHw_REG_GPIO_MUX_ETM,
104 chipcHw_GPIO_FUNCTION_DEBUG = chipcHw_REG_GPIO_MUX_DEBUG,
105 chipcHw_GPIO_FUNCTION_MISC = chipcHw_REG_GPIO_MUX_MISC,
106 chipcHw_GPIO_FUNCTION_GPIO = chipcHw_REG_GPIO_MUX_GPIO
107} chipcHw_GPIO_FUNCTION_e;
108
109/* PIN Output slew rate */
110typedef enum {
111 chipcHw_PIN_SLEW_RATE_HIGH = chipcHw_REG_SLEW_RATE_HIGH,
112 chipcHw_PIN_SLEW_RATE_NORMAL = chipcHw_REG_SLEW_RATE_NORMAL
113} chipcHw_PIN_SLEW_RATE_e;
114
115/* PIN Current drive strength */
116typedef enum {
117 chipcHw_PIN_CURRENT_STRENGTH_2mA = chipcHw_REG_CURRENT_STRENGTH_2mA,
118 chipcHw_PIN_CURRENT_STRENGTH_4mA = chipcHw_REG_CURRENT_STRENGTH_4mA,
119 chipcHw_PIN_CURRENT_STRENGTH_6mA = chipcHw_REG_CURRENT_STRENGTH_6mA,
120 chipcHw_PIN_CURRENT_STRENGTH_8mA = chipcHw_REG_CURRENT_STRENGTH_8mA,
121 chipcHw_PIN_CURRENT_STRENGTH_10mA = chipcHw_REG_CURRENT_STRENGTH_10mA,
122 chipcHw_PIN_CURRENT_STRENGTH_12mA = chipcHw_REG_CURRENT_STRENGTH_12mA
123} chipcHw_PIN_CURRENT_STRENGTH_e;
124
125/* PIN Pull up register settings */
126typedef enum {
127 chipcHw_PIN_PULL_NONE = chipcHw_REG_PULL_NONE,
128 chipcHw_PIN_PULL_UP = chipcHw_REG_PULL_UP,
129 chipcHw_PIN_PULL_DOWN = chipcHw_REG_PULL_DOWN
130} chipcHw_PIN_PULL_e;
131
132/* PIN input type settings */
133typedef enum {
134 chipcHw_PIN_INPUTTYPE_CMOS = chipcHw_REG_INPUTTYPE_CMOS,
135 chipcHw_PIN_INPUTTYPE_ST = chipcHw_REG_INPUTTYPE_ST
136} chipcHw_PIN_INPUTTYPE_e;
137
138/* Allow/Disalow the support of spread spectrum */
139typedef enum {
140 chipcHw_SPREAD_SPECTRUM_DISALLOW, /* Spread spectrum support is not allowed */
141 chipcHw_SPREAD_SPECTRUM_ALLOW /* Spread spectrum support is allowed */
142} chipcHw_SPREAD_SPECTRUM_e;
143
144typedef struct {
145 chipcHw_SPREAD_SPECTRUM_e ssSupport; /* Allow/Disalow to support spread spectrum.
146 If supported, call chipcHw_enableSpreadSpectrum ()
147 to activate the spread spectrum with desired spread. */
148 uint32_t pllVcoFreqHz; /* PLL VCO frequency in Hz */
149 uint32_t pll2VcoFreqHz; /* PLL2 VCO frequency in Hz */
150 uint32_t busClockFreqHz; /* Bus clock frequency in Hz */
151 uint32_t armBusRatio; /* ARM clock : Bus clock */
152 uint32_t vpmBusRatio; /* VPM clock : Bus clock */
153 uint32_t ddrBusRatio; /* DDR clock : Bus clock */
154} chipcHw_INIT_PARAM_t;
155
156/* CHIP revision number */
157typedef enum {
158 chipcHw_REV_NUMBER_A0 = chipcHw_REG_REV_A0,
159 chipcHw_REV_NUMBER_B0 = chipcHw_REG_REV_B0
160} chipcHw_REV_NUMBER_e;
161
162typedef enum {
163 chipcHw_VPM_HW_PHASE_INTR_DISABLE = chipcHw_REG_VPM_INTR_DISABLE,
164 chipcHw_VPM_HW_PHASE_INTR_FAST = chipcHw_REG_VPM_INTR_FAST,
165 chipcHw_VPM_HW_PHASE_INTR_MEDIUM = chipcHw_REG_VPM_INTR_MEDIUM,
166 chipcHw_VPM_HW_PHASE_INTR_SLOW = chipcHw_REG_VPM_INTR_SLOW
167} chipcHw_VPM_HW_PHASE_INTR_e;
168
169typedef enum {
170 chipcHw_DDR_HW_PHASE_MARGIN_STRICT, /* Strict margin for DDR phase align condition */
171 chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM, /* Medium margin for DDR phase align condition */
172 chipcHw_DDR_HW_PHASE_MARGIN_WIDE /* Wider margin for DDR phase align condition */
173} chipcHw_DDR_HW_PHASE_MARGIN_e;
174
175typedef enum {
176 chipcHw_VPM_HW_PHASE_MARGIN_STRICT, /* Strict margin for VPM phase align condition */
177 chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM, /* Medium margin for VPM phase align condition */
178 chipcHw_VPM_HW_PHASE_MARGIN_WIDE /* Wider margin for VPM phase align condition */
179} chipcHw_VPM_HW_PHASE_MARGIN_e;
180
181#define chipcHw_XTAL_FREQ_Hz 25000000 /* Reference clock frequency in Hz */
182
183/* Programmable pin defines */
184#define chipcHw_PIN_GPIO(n) ((((n) >= 0) && ((n) < (chipcHw_GPIO_COUNT))) ? (n) : 0xFFFFFFFF)
185 /* GPIO pin 0 - 60 */
186#define chipcHw_PIN_UARTTXD (chipcHw_GPIO_COUNT + 0) /* UART Transmit */
187#define chipcHw_PIN_NVI_A (chipcHw_GPIO_COUNT + 1) /* NVI Interface */
188#define chipcHw_PIN_NVI_D (chipcHw_GPIO_COUNT + 2) /* NVI Interface */
189#define chipcHw_PIN_NVI_OEB (chipcHw_GPIO_COUNT + 3) /* NVI Interface */
190#define chipcHw_PIN_NVI_WEB (chipcHw_GPIO_COUNT + 4) /* NVI Interface */
191#define chipcHw_PIN_NVI_CS (chipcHw_GPIO_COUNT + 5) /* NVI Interface */
192#define chipcHw_PIN_NVI_NAND_CSB (chipcHw_GPIO_COUNT + 6) /* NVI Interface */
193#define chipcHw_PIN_NVI_FLASHWP (chipcHw_GPIO_COUNT + 7) /* NVI Interface */
194#define chipcHw_PIN_NVI_NAND_RDYB (chipcHw_GPIO_COUNT + 8) /* NVI Interface */
195#define chipcHw_PIN_CL_DATA_0_17 (chipcHw_GPIO_COUNT + 9) /* LCD Data 0 - 17 */
196#define chipcHw_PIN_CL_DATA_18_20 (chipcHw_GPIO_COUNT + 10) /* LCD Data 18 - 20 */
197#define chipcHw_PIN_CL_DATA_21_23 (chipcHw_GPIO_COUNT + 11) /* LCD Data 21 - 23 */
198#define chipcHw_PIN_CL_POWER (chipcHw_GPIO_COUNT + 12) /* LCD Power */
199#define chipcHw_PIN_CL_ACK (chipcHw_GPIO_COUNT + 13) /* LCD Ack */
200#define chipcHw_PIN_CL_FP (chipcHw_GPIO_COUNT + 14) /* LCD FP */
201#define chipcHw_PIN_CL_LP (chipcHw_GPIO_COUNT + 15) /* LCD LP */
202#define chipcHw_PIN_UARTRXD (chipcHw_GPIO_COUNT + 16) /* UART Receive */
203
204/* ---- Public Variable Externs ------------------------------------------ */
205/* ---- Public Function Prototypes --------------------------------------- */
206
207/****************************************************************************/
208/**
209* @brief Initializes the clock module
210*
211*/
212/****************************************************************************/
213void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam /* [ IN ] Misc chip initialization parameter */
214 ) __attribute__ ((section(".aramtext")));
215
216/****************************************************************************/
217/**
218* @brief Enables the PLL1
219*
220* This function enables the PLL1
221*
222*/
223/****************************************************************************/
224void chipcHw_pll1Enable(uint32_t vcoFreqHz, /* [ IN ] VCO frequency in Hz */
225 chipcHw_SPREAD_SPECTRUM_e ssSupport /* [ IN ] SS status */
226 ) __attribute__ ((section(".aramtext")));
227
228/****************************************************************************/
229/**
230* @brief Enables the PLL2
231*
232* This function enables the PLL2
233*
234*/
235/****************************************************************************/
236void chipcHw_pll2Enable(uint32_t vcoFreqHz /* [ IN ] VCO frequency in Hz */
237 ) __attribute__ ((section(".aramtext")));
238
239/****************************************************************************/
240/**
241* @brief Disable the PLL1
242*
243*/
244/****************************************************************************/
245static inline void chipcHw_pll1Disable(void);
246
247/****************************************************************************/
248/**
249* @brief Disable the PLL2
250*
251*/
252/****************************************************************************/
253static inline void chipcHw_pll2Disable(void);
254
255/****************************************************************************/
256/**
257* @brief Set clock fequency for miscellaneous configurable clocks
258*
259* This function sets clock frequency
260*
261* @return Configured clock frequency in KHz
262*
263*/
264/****************************************************************************/
265chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */
266 ) __attribute__ ((section(".aramtext")));
267
268/****************************************************************************/
269/**
270* @brief Set clock fequency for miscellaneous configurable clocks
271*
272* This function sets clock frequency
273*
274* @return Configured clock frequency in Hz
275*
276*/
277/****************************************************************************/
278chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configurable clock */
279 uint32_t freq /* [ IN ] Clock frequency in Hz */
280 ) __attribute__ ((section(".aramtext")));
281
282/****************************************************************************/
283/**
284* @brief Set VPM clock in sync with BUS clock
285*
286* This function does the phase adjustment between VPM and BUS clock
287*
288* @return >= 0 : On success ( # of adjustment required )
289* -1 : On failure
290*/
291/****************************************************************************/
292int chipcHw_vpmPhaseAlign(void);
293
294/****************************************************************************/
295/**
296* @brief Enables core a clock of a certain device
297*
298* This function enables a core clock
299*
300* @return void
301*
302* @note Doesnot affect the bus interface clock
303*/
304/****************************************************************************/
305static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */
306 );
307
308/****************************************************************************/
309/**
310* @brief Disabled a core clock of a certain device
311*
312* This function disables a core clock
313*
314* @return void
315*
316* @note Doesnot affect the bus interface clock
317*/
318/****************************************************************************/
319static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */
320 );
321
322/****************************************************************************/
323/**
324* @brief Enables bypass clock of a certain device
325*
326* This function enables bypass clock
327*
328* @note Doesnot affect the bus interface clock
329*/
330/****************************************************************************/
331static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */
332 );
333
334/****************************************************************************/
335/**
336* @brief Disabled bypass clock of a certain device
337*
338* This function disables bypass clock
339*
340* @note Doesnot affect the bus interface clock
341*/
342/****************************************************************************/
343static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */
344 );
345
346/****************************************************************************/
347/**
348* @brief Get Numeric Chip ID
349*
350* This function returns Chip ID that includes the revison number
351*
352* @return Complete numeric Chip ID
353*
354*/
355/****************************************************************************/
356static inline uint32_t chipcHw_getChipId(void);
357
358/****************************************************************************/
359/**
360* @brief Get Chip Product ID
361*
362* This function returns Chip Product ID
363*
364* @return Chip Product ID
365*/
366/****************************************************************************/
367static inline uint32_t chipcHw_getChipProductId(void);
368
369/****************************************************************************/
370/**
371* @brief Get revision number
372*
373* This function returns revision number of the chip
374*
375* @return Revision number
376*/
377/****************************************************************************/
378static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void);
379
380/****************************************************************************/
381/**
382* @brief Enables bus interface clock
383*
384* Enables bus interface clock of various device
385*
386* @return void
387*
388* @note use chipcHw_REG_BUS_CLOCK_XXXX
389*/
390/****************************************************************************/
391static inline void chipcHw_busInterfaceClockEnable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_BUS_CLOCK_XXXXX */
392 );
393
394/****************************************************************************/
395/**
396* @brief Disables bus interface clock
397*
398* Disables bus interface clock of various device
399*
400* @return void
401*
402* @note use chipcHw_REG_BUS_CLOCK_XXXX
403*/
404/****************************************************************************/
405static inline void chipcHw_busInterfaceClockDisable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_BUS_CLOCK_XXXXX */
406 );
407
408/****************************************************************************/
409/**
410* @brief Enables various audio channels
411*
412* Enables audio channel
413*
414* @return void
415*
416* @note use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
417*/
418/****************************************************************************/
419static inline void chipcHw_audioChannelEnable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_AUDIO_CHANNEL_XXXXXX */
420 );
421
422/****************************************************************************/
423/**
424* @brief Disables various audio channels
425*
426* Disables audio channel
427*
428* @return void
429*
430* @note use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
431*/
432/****************************************************************************/
433static inline void chipcHw_audioChannelDisable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_AUDIO_CHANNEL_XXXXXX */
434 );
435
436/****************************************************************************/
437/**
438* @brief Soft resets devices
439*
440* Soft resets various devices
441*
442* @return void
443*
444* @note use chipcHw_REG_SOFT_RESET_XXXXXX defines
445*/
446/****************************************************************************/
447static inline void chipcHw_softReset(uint64_t mask /* [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
448 );
449
450static inline void chipcHw_softResetDisable(uint64_t mask /* [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
451 );
452
453static inline void chipcHw_softResetEnable(uint64_t mask /* [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
454 );
455
456/****************************************************************************/
457/**
458* @brief Configures misc CHIP functionality
459*
460* Configures CHIP functionality
461*
462* @return void
463*
464* @note use chipcHw_REG_MISC_CTRL_XXXXXX
465*/
466/****************************************************************************/
467static inline void chipcHw_miscControl(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
468 );
469
470static inline void chipcHw_miscControlDisable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
471 );
472
473static inline void chipcHw_miscControlEnable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
474 );
475
476/****************************************************************************/
477/**
478* @brief Set OTP options
479*
480* Set OTP options
481*
482* @return void
483*
484* @note use chipcHw_REG_OTP_XXXXXX
485*/
486/****************************************************************************/
487static inline void chipcHw_setOTPOption(uint64_t mask /* [ IN ] Bit map of type chipcHw_REG_OTP_XXXXXX */
488 );
489
490/****************************************************************************/
491/**
492* @brief Get sticky bits
493*
494* @return Sticky bit options of type chipcHw_REG_STICKY_XXXXXX
495*
496*/
497/****************************************************************************/
498static inline uint32_t chipcHw_getStickyBits(void);
499
500/****************************************************************************/
501/**
502* @brief Set sticky bits
503*
504* @return void
505*
506* @note use chipcHw_REG_STICKY_XXXXXX
507*/
508/****************************************************************************/
509static inline void chipcHw_setStickyBits(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_STICKY_XXXXXX */
510 );
511
512/****************************************************************************/
513/**
514* @brief Clear sticky bits
515*
516* @return void
517*
518* @note use chipcHw_REG_STICKY_XXXXXX
519*/
520/****************************************************************************/
521static inline void chipcHw_clearStickyBits(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_STICKY_XXXXXX */
522 );
523
524/****************************************************************************/
525/**
526* @brief Get software override strap options
527*
528* Retrieves software override strap options
529*
530* @return Software override strap value
531*
532*/
533/****************************************************************************/
534static inline uint32_t chipcHw_getSoftStraps(void);
535
536/****************************************************************************/
537/**
538* @brief Set software override strap options
539*
540* set software override strap options
541*
542* @return nothing
543*
544*/
545/****************************************************************************/
546static inline void chipcHw_setSoftStraps(uint32_t strapOptions);
547
548/****************************************************************************/
549/**
550* @brief Get pin strap options
551*
552* Retrieves pin strap options
553*
554* @return Pin strap value
555*
556*/
557/****************************************************************************/
558static inline uint32_t chipcHw_getPinStraps(void);
559
560/****************************************************************************/
561/**
562* @brief Get valid pin strap options
563*
564* Retrieves valid pin strap options
565*
566* @return valid Pin strap value
567*
568*/
569/****************************************************************************/
570static inline uint32_t chipcHw_getValidStraps(void);
571
572/****************************************************************************/
573/**
574* @brief Initialize valid pin strap options
575*
576* Retrieves valid pin strap options by copying HW strap options to soft register
577* (if chipcHw_STRAPS_SOFT_OVERRIDE not set)
578*
579* @return nothing
580*
581*/
582/****************************************************************************/
583static inline void chipcHw_initValidStraps(void);
584
585/****************************************************************************/
586/**
587* @brief Get status (enabled/disabled) of bus interface clock
588*
589* This function returns the status of devices' bus interface clock
590*
591* @return Bus interface clock
592*
593*/
594/****************************************************************************/
595static inline uint32_t chipcHw_getBusInterfaceClockStatus(void);
596
597/****************************************************************************/
598/**
599* @brief Get boot device
600*
601* This function returns the device type used in booting the system
602*
603* @return Boot device of type chipcHw_BOOT_DEVICE_e
604*
605*/
606/****************************************************************************/
607static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void);
608
609/****************************************************************************/
610/**
611* @brief Get boot mode
612*
613* This function returns the way the system was booted
614*
615* @return Boot mode of type chipcHw_BOOT_MODE_e
616*
617*/
618/****************************************************************************/
619static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void);
620
621/****************************************************************************/
622/**
623* @brief Get NAND flash page size
624*
625* This function returns the NAND device page size
626*
627* @return Boot NAND device page size
628*
629*/
630/****************************************************************************/
631static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void);
632
633/****************************************************************************/
634/**
635* @brief Get NAND flash address cycle configuration
636*
637* This function returns the NAND flash address cycle configuration
638*
639* @return 0 = Do not extra address cycle, 1 = Add extra cycle
640*
641*/
642/****************************************************************************/
643static inline int chipcHw_getNandExtraCycle(void);
644
645/****************************************************************************/
646/**
647* @brief Activates PIF interface
648*
649* This function activates PIF interface by taking control of LCD pins
650*
651* @note
652* When activated, LCD pins will be defined as follows for PIF operation
653*
654* CLD[17:0] = pif_data[17:0]
655* CLD[23:18] = pif_address[5:0]
656* CLPOWER = pif_wr_str
657* CLCP = pif_rd_str
658* CLAC = pif_hat1
659* CLFP = pif_hrdy1
660* CLLP = pif_hat2
661* GPIO[42] = pif_hrdy2
662*
663* In PIF mode, "pif_hrdy2" overrides other shared function for GPIO[42] pin
664*
665*/
666/****************************************************************************/
667static inline void chipcHw_activatePifInterface(void);
668
669/****************************************************************************/
670/**
671* @brief Activates LCD interface
672*
673* This function activates LCD interface
674*
675* @note
676* When activated, LCD pins will be defined as follows
677*
678* CLD[17:0] = LCD data
679* CLD[23:18] = LCD data
680* CLPOWER = LCD power
681* CLCP =
682* CLAC = LCD ack
683* CLFP =
684* CLLP =
685*/
686/****************************************************************************/
687static inline void chipcHw_activateLcdInterface(void);
688
689/****************************************************************************/
690/**
691* @brief Deactivates PIF/LCD interface
692*
693* This function deactivates PIF/LCD interface
694*
695* @note
696* When deactivated LCD pins will be in rti-stated
697*
698*/
699/****************************************************************************/
700static inline void chipcHw_deactivatePifLcdInterface(void);
701
702/****************************************************************************/
703/**
704* @brief Get to know the configuration of GPIO pin
705*
706*/
707/****************************************************************************/
708static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin /* GPIO Pin number */
709 );
710
711/****************************************************************************/
712/**
713* @brief Configure GPIO pin function
714*
715*/
716/****************************************************************************/
717static inline void chipcHw_setGpioPinFunction(int pin, /* GPIO Pin number */
718 chipcHw_GPIO_FUNCTION_e func /* Configuration function */
719 );
720
721/****************************************************************************/
722/**
723* @brief Set Pin slew rate
724*
725* This function sets the slew of individual pin
726*
727*/
728/****************************************************************************/
729static inline void chipcHw_setPinSlewRate(uint32_t pin, /* Pin of type chipcHw_PIN_XXXXX */
730 chipcHw_PIN_SLEW_RATE_e slewRate /* Pin slew rate */
731 );
732
733/****************************************************************************/
734/**
735* @brief Set Pin output drive current
736*
737* This function sets output drive current of individual pin
738*
739* Note: Avoid the use of the word 'current' since linux headers define this
740* to be the current task.
741*/
742/****************************************************************************/
743static inline void chipcHw_setPinOutputCurrent(uint32_t pin, /* Pin of type chipcHw_PIN_XXXXX */
744 chipcHw_PIN_CURRENT_STRENGTH_e curr /* Pin current rating */
745 );
746
747/****************************************************************************/
748/**
749* @brief Set Pin pullup register
750*
751* This function sets pullup register of individual pin
752*
753*/
754/****************************************************************************/
755static inline void chipcHw_setPinPullup(uint32_t pin, /* Pin of type chipcHw_PIN_XXXXX */
756 chipcHw_PIN_PULL_e pullup /* Pullup register settings */
757 );
758
759/****************************************************************************/
760/**
761* @brief Set Pin input type
762*
763* This function sets input type of individual Pin
764*
765*/
766/****************************************************************************/
767static inline void chipcHw_setPinInputType(uint32_t pin, /* Pin of type chipcHw_PIN_XXXXX */
768 chipcHw_PIN_INPUTTYPE_e inputType /* Pin input type */
769 );
770
771/****************************************************************************/
772/**
773* @brief Retrieves a string representation of the mux setting for a pin.
774*
775* @return Pointer to a character string.
776*/
777/****************************************************************************/
778
779const char *chipcHw_getGpioPinFunctionStr(int pin);
780
781/****************************************************************************/
782/** @brief issue warmReset
783 */
784/****************************************************************************/
785void chipcHw_reset(uint32_t mask);
786
787/****************************************************************************/
788/** @brief clock reconfigure
789 */
790/****************************************************************************/
791void chipcHw_clockReconfig(uint32_t busHz, uint32_t armRatio, uint32_t vpmRatio,
792 uint32_t ddrRatio);
793
794/****************************************************************************/
795/**
796* @brief Enable Spread Spectrum
797*
798* @note chipcHw_Init() must be called earlier
799*/
800/****************************************************************************/
801static inline void chipcHw_enableSpreadSpectrum(void);
802
803/****************************************************************************/
804/**
805* @brief Disable Spread Spectrum
806*
807*/
808/****************************************************************************/
809static inline void chipcHw_disableSpreadSpectrum(void);
810
811/****************************************************************************/
812/** @brief Checks if software strap is enabled
813 *
814 * @return 1 : When enable
815 * 0 : When disable
816 */
817/****************************************************************************/
818static inline int chipcHw_isSoftwareStrapsEnable(void);
819
820/****************************************************************************/
821/** @brief Enable software strap
822 */
823/****************************************************************************/
824static inline void chipcHw_softwareStrapsEnable(void);
825
826/****************************************************************************/
827/** @brief Disable software strap
828 */
829/****************************************************************************/
830static inline void chipcHw_softwareStrapsDisable(void);
831
832/****************************************************************************/
833/** @brief PLL test enable
834 */
835/****************************************************************************/
836static inline void chipcHw_pllTestEnable(void);
837
838/****************************************************************************/
839/** @brief PLL2 test enable
840 */
841/****************************************************************************/
842static inline void chipcHw_pll2TestEnable(void);
843
844/****************************************************************************/
845/** @brief PLL test disable
846 */
847/****************************************************************************/
848static inline void chipcHw_pllTestDisable(void);
849
850/****************************************************************************/
851/** @brief PLL2 test disable
852 */
853/****************************************************************************/
854static inline void chipcHw_pll2TestDisable(void);
855
856/****************************************************************************/
857/** @brief Get PLL test status
858 */
859/****************************************************************************/
860static inline int chipcHw_isPllTestEnable(void);
861
862/****************************************************************************/
863/** @brief Get PLL2 test status
864 */
865/****************************************************************************/
866static inline int chipcHw_isPll2TestEnable(void);
867
868/****************************************************************************/
869/** @brief PLL test select
870 */
871/****************************************************************************/
872static inline void chipcHw_pllTestSelect(uint32_t val);
873
874/****************************************************************************/
875/** @brief PLL2 test select
876 */
877/****************************************************************************/
878static inline void chipcHw_pll2TestSelect(uint32_t val);
879
880/****************************************************************************/
881/** @brief Get PLL test selected option
882 */
883/****************************************************************************/
884static inline uint8_t chipcHw_getPllTestSelected(void);
885
886/****************************************************************************/
887/** @brief Get PLL2 test selected option
888 */
889/****************************************************************************/
890static inline uint8_t chipcHw_getPll2TestSelected(void);
891
892/****************************************************************************/
893/**
894* @brief Enables DDR SW phase alignment interrupt
895*/
896/****************************************************************************/
897static inline void chipcHw_ddrPhaseAlignInterruptEnable(void);
898
899/****************************************************************************/
900/**
901* @brief Disables DDR SW phase alignment interrupt
902*/
903/****************************************************************************/
904static inline void chipcHw_ddrPhaseAlignInterruptDisable(void);
905
906/****************************************************************************/
907/**
908* @brief Set VPM SW phase alignment interrupt mode
909*
910* This function sets VPM phase alignment interrupt
911*
912*/
913/****************************************************************************/
914static inline void
915chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode);
916
917/****************************************************************************/
918/**
919* @brief Enable DDR phase alignment in software
920*
921*/
922/****************************************************************************/
923static inline void chipcHw_ddrSwPhaseAlignEnable(void);
924
925/****************************************************************************/
926/**
927* @brief Disable DDR phase alignment in software
928*
929*/
930/****************************************************************************/
931static inline void chipcHw_ddrSwPhaseAlignDisable(void);
932
933/****************************************************************************/
934/**
935* @brief Enable DDR phase alignment in hardware
936*
937*/
938/****************************************************************************/
939static inline void chipcHw_ddrHwPhaseAlignEnable(void);
940
941/****************************************************************************/
942/**
943* @brief Disable DDR phase alignment in hardware
944*
945*/
946/****************************************************************************/
947static inline void chipcHw_ddrHwPhaseAlignDisable(void);
948
949/****************************************************************************/
950/**
951* @brief Enable VPM phase alignment in software
952*
953*/
954/****************************************************************************/
955static inline void chipcHw_vpmSwPhaseAlignEnable(void);
956
957/****************************************************************************/
958/**
959* @brief Disable VPM phase alignment in software
960*
961*/
962/****************************************************************************/
963static inline void chipcHw_vpmSwPhaseAlignDisable(void);
964
965/****************************************************************************/
966/**
967* @brief Enable VPM phase alignment in hardware
968*
969*/
970/****************************************************************************/
971static inline void chipcHw_vpmHwPhaseAlignEnable(void);
972
973/****************************************************************************/
974/**
975* @brief Disable VPM phase alignment in hardware
976*
977*/
978/****************************************************************************/
979static inline void chipcHw_vpmHwPhaseAlignDisable(void);
980
981/****************************************************************************/
982/**
983* @brief Set DDR phase alignment margin in hardware
984*
985*/
986/****************************************************************************/
987static inline void chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin /* Margin alinging DDR phase */
988 );
989
990/****************************************************************************/
991/**
992* @brief Set VPM phase alignment margin in hardware
993*
994*/
995/****************************************************************************/
996static inline void chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin /* Margin alinging VPM phase */
997 );
998
999/****************************************************************************/
1000/**
1001* @brief Checks DDR phase aligned status done by HW
1002*
1003* @return 1: When aligned
1004* 0: When not aligned
1005*/
1006/****************************************************************************/
1007static inline uint32_t chipcHw_isDdrHwPhaseAligned(void);
1008
1009/****************************************************************************/
1010/**
1011* @brief Checks VPM phase aligned status done by HW
1012*
1013* @return 1: When aligned
1014* 0: When not aligned
1015*/
1016/****************************************************************************/
1017static inline uint32_t chipcHw_isVpmHwPhaseAligned(void);
1018
1019/****************************************************************************/
1020/**
1021* @brief Get DDR phase aligned status done by HW
1022*
1023*/
1024/****************************************************************************/
1025static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void);
1026
1027/****************************************************************************/
1028/**
1029* @brief Get VPM phase aligned status done by HW
1030*
1031*/
1032/****************************************************************************/
1033static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void);
1034
1035/****************************************************************************/
1036/**
1037* @brief Get DDR phase control value
1038*
1039*/
1040/****************************************************************************/
1041static inline uint32_t chipcHw_getDdrPhaseControl(void);
1042
1043/****************************************************************************/
1044/**
1045* @brief Get VPM phase control value
1046*
1047*/
1048/****************************************************************************/
1049static inline uint32_t chipcHw_getVpmPhaseControl(void);
1050
1051/****************************************************************************/
1052/**
1053* @brief DDR phase alignment timeout count
1054*
1055* @note If HW fails to perform the phase alignment, it will trigger
1056* a DDR phase alignment timeout interrupt.
1057*/
1058/****************************************************************************/
1059static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle /* Timeout in bus cycle */
1060 );
1061
1062/****************************************************************************/
1063/**
1064* @brief VPM phase alignment timeout count
1065*
1066* @note If HW fails to perform the phase alignment, it will trigger
1067* a VPM phase alignment timeout interrupt.
1068*/
1069/****************************************************************************/
1070static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle /* Timeout in bus cycle */
1071 );
1072
1073/****************************************************************************/
1074/**
1075* @brief DDR phase alignment timeout interrupt enable
1076*
1077*/
1078/****************************************************************************/
1079static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void);
1080
1081/****************************************************************************/
1082/**
1083* @brief VPM phase alignment timeout interrupt enable
1084*
1085*/
1086/****************************************************************************/
1087static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void);
1088
1089/****************************************************************************/
1090/**
1091* @brief DDR phase alignment timeout interrupt disable
1092*
1093*/
1094/****************************************************************************/
1095static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void);
1096
1097/****************************************************************************/
1098/**
1099* @brief VPM phase alignment timeout interrupt disable
1100*
1101*/
1102/****************************************************************************/
1103static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void);
1104
1105/****************************************************************************/
1106/**
1107* @brief Clear DDR phase alignment timeout interrupt
1108*
1109*/
1110/****************************************************************************/
1111static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void);
1112
1113/****************************************************************************/
1114/**
1115* @brief Clear VPM phase alignment timeout interrupt
1116*
1117*/
1118/****************************************************************************/
1119static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void);
1120
1121/* ---- Private Constants and Types -------------------------------------- */
1122
1123#endif /* CHIPC_DEF_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
deleted file mode 100644
index a66f3f7abb86..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
+++ /dev/null
@@ -1,1682 +0,0 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#ifndef CHIPC_INLINE_H
16#define CHIPC_INLINE_H
17
18/* ---- Include Files ----------------------------------------------------- */
19
20#include <linux/errno.h>
21#include <mach/csp/reg.h>
22#include <mach/csp/chipcHw_reg.h>
23#include <mach/csp/chipcHw_def.h>
24
25/* ---- Private Constants and Types --------------------------------------- */
26typedef enum {
27 chipcHw_OPTYPE_BYPASS, /* Bypass operation */
28 chipcHw_OPTYPE_OUTPUT /* Output operation */
29} chipcHw_OPTYPE_e;
30
31/* ---- Public Constants and Types ---------------------------------------- */
32/* ---- Public Variable Externs ------------------------------------------- */
33/* ---- Public Function Prototypes ---------------------------------------- */
34/* ---- Private Function Prototypes --------------------------------------- */
35static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
36 chipcHw_OPTYPE_e type, int mode);
37
38/****************************************************************************/
39/**
40* @brief Get Numeric Chip ID
41*
42* This function returns Chip ID that includes the revison number
43*
44* @return Complete numeric Chip ID
45*
46*/
47/****************************************************************************/
48static inline uint32_t chipcHw_getChipId(void)
49{
50 return readl(&pChipcHw->ChipId);
51}
52
53/****************************************************************************/
54/**
55* @brief Enable Spread Spectrum
56*
57* @note chipcHw_Init() must be called earlier
58*/
59/****************************************************************************/
60static inline void chipcHw_enableSpreadSpectrum(void)
61{
62 if ((readl(&pChipcHw->
63 PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) !=
64 chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
65 writel((0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) |
66 (ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK <<
67 ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT),
68 &ddrcReg_PHY_ADDR_CTL_REGP->ssCfg);
69 writel(readl(&ddrcReg_PHY_ADDR_CTL_REGP->ssCtl) |
70 ddrcReg_PHY_ADDR_SS_CTRL_ENABLE,
71 &ddrcReg_PHY_ADDR_CTL_REGP->ssCtl);
72 }
73}
74
75/****************************************************************************/
76/**
77* @brief Disable Spread Spectrum
78*
79*/
80/****************************************************************************/
81static inline void chipcHw_disableSpreadSpectrum(void)
82{
83 ddrcReg_PHY_ADDR_CTL_REGP->ssCtl &= ~ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
84}
85
86/****************************************************************************/
87/**
88* @brief Get Chip Product ID
89*
90* This function returns Chip Product ID
91*
92* @return Chip Product ID
93*/
94/****************************************************************************/
95static inline uint32_t chipcHw_getChipProductId(void)
96{
97 return (readl(&pChipcHw->
98 ChipId) & chipcHw_REG_CHIPID_BASE_MASK) >>
99 chipcHw_REG_CHIPID_BASE_SHIFT;
100}
101
102/****************************************************************************/
103/**
104* @brief Get revision number
105*
106* This function returns revision number of the chip
107*
108* @return Revision number
109*/
110/****************************************************************************/
111static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void)
112{
113 return readl(&pChipcHw->ChipId) & chipcHw_REG_CHIPID_REV_MASK;
114}
115
116/****************************************************************************/
117/**
118* @brief Enables bus interface clock
119*
120* Enables bus interface clock of various device
121*
122* @return void
123*
124* @note use chipcHw_REG_BUS_CLOCK_XXXX for mask
125*/
126/****************************************************************************/
127static inline void chipcHw_busInterfaceClockEnable(uint32_t mask)
128{
129 reg32_modify_or(&pChipcHw->BusIntfClock, mask);
130}
131
132/****************************************************************************/
133/**
134* @brief Disables bus interface clock
135*
136* Disables bus interface clock of various device
137*
138* @return void
139*
140* @note use chipcHw_REG_BUS_CLOCK_XXXX
141*/
142/****************************************************************************/
143static inline void chipcHw_busInterfaceClockDisable(uint32_t mask)
144{
145 reg32_modify_and(&pChipcHw->BusIntfClock, ~mask);
146}
147
148/****************************************************************************/
149/**
150* @brief Get status (enabled/disabled) of bus interface clock
151*
152* This function returns the status of devices' bus interface clock
153*
154* @return Bus interface clock
155*
156*/
157/****************************************************************************/
158static inline uint32_t chipcHw_getBusInterfaceClockStatus(void)
159{
160 return readl(&pChipcHw->BusIntfClock);
161}
162
163/****************************************************************************/
164/**
165* @brief Enables various audio channels
166*
167* Enables audio channel
168*
169* @return void
170*
171* @note use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
172*/
173/****************************************************************************/
174static inline void chipcHw_audioChannelEnable(uint32_t mask)
175{
176 reg32_modify_or(&pChipcHw->AudioEnable, mask);
177}
178
179/****************************************************************************/
180/**
181* @brief Disables various audio channels
182*
183* Disables audio channel
184*
185* @return void
186*
187* @note use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
188*/
189/****************************************************************************/
190static inline void chipcHw_audioChannelDisable(uint32_t mask)
191{
192 reg32_modify_and(&pChipcHw->AudioEnable, ~mask);
193}
194
195/****************************************************************************/
196/**
197* @brief Soft resets devices
198*
199* Soft resets various devices
200*
201* @return void
202*
203* @note use chipcHw_REG_SOFT_RESET_XXXXXX defines
204*/
205/****************************************************************************/
206static inline void chipcHw_softReset(uint64_t mask)
207{
208 chipcHw_softResetEnable(mask);
209 chipcHw_softResetDisable(mask);
210}
211
212static inline void chipcHw_softResetDisable(uint64_t mask)
213{
214 uint32_t ctrl1 = (uint32_t) mask;
215 uint32_t ctrl2 = (uint32_t) (mask >> 32);
216
217 /* Deassert module soft reset */
218 REG_LOCAL_IRQ_SAVE;
219 writel(readl(&pChipcHw->SoftReset1) ^ ctrl1, &pChipcHw->SoftReset1);
220 writel(readl(&pChipcHw->SoftReset2) ^ (ctrl2 &
221 (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2);
222 REG_LOCAL_IRQ_RESTORE;
223}
224
225static inline void chipcHw_softResetEnable(uint64_t mask)
226{
227 uint32_t ctrl1 = (uint32_t) mask;
228 uint32_t ctrl2 = (uint32_t) (mask >> 32);
229 uint32_t unhold = 0;
230
231 REG_LOCAL_IRQ_SAVE;
232 writel(readl(&pChipcHw->SoftReset1) | ctrl1, &pChipcHw->SoftReset1);
233 /* Mask out unhold request bits */
234 writel(readl(&pChipcHw->SoftReset2) | (ctrl2 &
235 (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2);
236
237 /* Process unhold requests */
238 if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD) {
239 unhold = chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD;
240 }
241
242 if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_UNHOLD) {
243 unhold |= chipcHw_REG_SOFT_RESET_VPM_HOLD;
244 }
245
246 if (ctrl2 & chipcHw_REG_SOFT_RESET_ARM_UNHOLD) {
247 unhold |= chipcHw_REG_SOFT_RESET_ARM_HOLD;
248 }
249
250 if (unhold) {
251 /* Make sure unhold request is effective */
252 writel(readl(&pChipcHw->SoftReset1) & ~unhold, &pChipcHw->SoftReset1);
253 }
254 REG_LOCAL_IRQ_RESTORE;
255}
256
257/****************************************************************************/
258/**
259* @brief Configures misc CHIP functionality
260*
261* Configures CHIP functionality
262*
263* @return void
264*
265* @note use chipcHw_REG_MISC_CTRL_XXXXXX
266*/
267/****************************************************************************/
268static inline void chipcHw_miscControl(uint32_t mask)
269{
270 reg32_write(&pChipcHw->MiscCtrl, mask);
271}
272
273static inline void chipcHw_miscControlDisable(uint32_t mask)
274{
275 reg32_modify_and(&pChipcHw->MiscCtrl, ~mask);
276}
277
278static inline void chipcHw_miscControlEnable(uint32_t mask)
279{
280 reg32_modify_or(&pChipcHw->MiscCtrl, mask);
281}
282
283/****************************************************************************/
284/**
285* @brief Set OTP options
286*
287* Set OTP options
288*
289* @return void
290*
291* @note use chipcHw_REG_OTP_XXXXXX
292*/
293/****************************************************************************/
294static inline void chipcHw_setOTPOption(uint64_t mask)
295{
296 uint32_t ctrl1 = (uint32_t) mask;
297 uint32_t ctrl2 = (uint32_t) (mask >> 32);
298
299 reg32_modify_or(&pChipcHw->SoftOTP1, ctrl1);
300 reg32_modify_or(&pChipcHw->SoftOTP2, ctrl2);
301}
302
303/****************************************************************************/
304/**
305* @brief Get sticky bits
306*
307* @return Sticky bit options of type chipcHw_REG_STICKY_XXXXXX
308*
309*/
310/****************************************************************************/
311static inline uint32_t chipcHw_getStickyBits(void)
312{
313 return readl(&pChipcHw->Sticky);
314}
315
316/****************************************************************************/
317/**
318* @brief Set sticky bits
319*
320* @return void
321*
322* @note use chipcHw_REG_STICKY_XXXXXX
323*/
324/****************************************************************************/
325static inline void chipcHw_setStickyBits(uint32_t mask)
326{
327 uint32_t bits = 0;
328
329 REG_LOCAL_IRQ_SAVE;
330 if (mask & chipcHw_REG_STICKY_POR_BROM) {
331 bits |= chipcHw_REG_STICKY_POR_BROM;
332 } else {
333 uint32_t sticky;
334 sticky = readl(pChipcHw->Sticky);
335
336 if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
337 && (sticky & chipcHw_REG_STICKY_BOOT_DONE) == 0) {
338 bits |= chipcHw_REG_STICKY_BOOT_DONE;
339 }
340 if ((mask & chipcHw_REG_STICKY_GENERAL_1)
341 && (sticky & chipcHw_REG_STICKY_GENERAL_1) == 0) {
342 bits |= chipcHw_REG_STICKY_GENERAL_1;
343 }
344 if ((mask & chipcHw_REG_STICKY_GENERAL_2)
345 && (sticky & chipcHw_REG_STICKY_GENERAL_2) == 0) {
346 bits |= chipcHw_REG_STICKY_GENERAL_2;
347 }
348 if ((mask & chipcHw_REG_STICKY_GENERAL_3)
349 && (sticky & chipcHw_REG_STICKY_GENERAL_3) == 0) {
350 bits |= chipcHw_REG_STICKY_GENERAL_3;
351 }
352 if ((mask & chipcHw_REG_STICKY_GENERAL_4)
353 && (sticky & chipcHw_REG_STICKY_GENERAL_4) == 0) {
354 bits |= chipcHw_REG_STICKY_GENERAL_4;
355 }
356 if ((mask & chipcHw_REG_STICKY_GENERAL_5)
357 && (sticky & chipcHw_REG_STICKY_GENERAL_5) == 0) {
358 bits |= chipcHw_REG_STICKY_GENERAL_5;
359 }
360 }
361 writel(bits, pChipcHw->Sticky);
362 REG_LOCAL_IRQ_RESTORE;
363}
364
365/****************************************************************************/
366/**
367* @brief Clear sticky bits
368*
369* @return void
370*
371* @note use chipcHw_REG_STICKY_XXXXXX
372*/
373/****************************************************************************/
374static inline void chipcHw_clearStickyBits(uint32_t mask)
375{
376 uint32_t bits = 0;
377
378 REG_LOCAL_IRQ_SAVE;
379 if (mask &
380 (chipcHw_REG_STICKY_BOOT_DONE | chipcHw_REG_STICKY_GENERAL_1 |
381 chipcHw_REG_STICKY_GENERAL_2 | chipcHw_REG_STICKY_GENERAL_3 |
382 chipcHw_REG_STICKY_GENERAL_4 | chipcHw_REG_STICKY_GENERAL_5)) {
383 uint32_t sticky = readl(&pChipcHw->Sticky);
384
385 if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
386 && (sticky & chipcHw_REG_STICKY_BOOT_DONE)) {
387 bits = chipcHw_REG_STICKY_BOOT_DONE;
388 mask &= ~chipcHw_REG_STICKY_BOOT_DONE;
389 }
390 if ((mask & chipcHw_REG_STICKY_GENERAL_1)
391 && (sticky & chipcHw_REG_STICKY_GENERAL_1)) {
392 bits |= chipcHw_REG_STICKY_GENERAL_1;
393 mask &= ~chipcHw_REG_STICKY_GENERAL_1;
394 }
395 if ((mask & chipcHw_REG_STICKY_GENERAL_2)
396 && (sticky & chipcHw_REG_STICKY_GENERAL_2)) {
397 bits |= chipcHw_REG_STICKY_GENERAL_2;
398 mask &= ~chipcHw_REG_STICKY_GENERAL_2;
399 }
400 if ((mask & chipcHw_REG_STICKY_GENERAL_3)
401 && (sticky & chipcHw_REG_STICKY_GENERAL_3)) {
402 bits |= chipcHw_REG_STICKY_GENERAL_3;
403 mask &= ~chipcHw_REG_STICKY_GENERAL_3;
404 }
405 if ((mask & chipcHw_REG_STICKY_GENERAL_4)
406 && (sticky & chipcHw_REG_STICKY_GENERAL_4)) {
407 bits |= chipcHw_REG_STICKY_GENERAL_4;
408 mask &= ~chipcHw_REG_STICKY_GENERAL_4;
409 }
410 if ((mask & chipcHw_REG_STICKY_GENERAL_5)
411 && (sticky & chipcHw_REG_STICKY_GENERAL_5)) {
412 bits |= chipcHw_REG_STICKY_GENERAL_5;
413 mask &= ~chipcHw_REG_STICKY_GENERAL_5;
414 }
415 }
416 writel(bits | mask, &pChipcHw->Sticky);
417 REG_LOCAL_IRQ_RESTORE;
418}
419
420/****************************************************************************/
421/**
422* @brief Get software strap value
423*
424* Retrieves software strap value
425*
426* @return Software strap value
427*
428*/
429/****************************************************************************/
430static inline uint32_t chipcHw_getSoftStraps(void)
431{
432 return readl(&pChipcHw->SoftStraps);
433}
434
435/****************************************************************************/
436/**
437* @brief Set software override strap options
438*
439* set software override strap options
440*
441* @return nothing
442*
443*/
444/****************************************************************************/
445static inline void chipcHw_setSoftStraps(uint32_t strapOptions)
446{
447 reg32_write(&pChipcHw->SoftStraps, strapOptions);
448}
449
450/****************************************************************************/
451/**
452* @brief Get Pin Strap Options
453*
454* This function returns the raw boot strap options
455*
456* @return strap options
457*
458*/
459/****************************************************************************/
460static inline uint32_t chipcHw_getPinStraps(void)
461{
462 return readl(&pChipcHw->PinStraps);
463}
464
465/****************************************************************************/
466/**
467* @brief Get Valid Strap Options
468*
469* This function returns the valid raw boot strap options
470*
471* @return strap options
472*
473*/
474/****************************************************************************/
475static inline uint32_t chipcHw_getValidStraps(void)
476{
477 uint32_t softStraps;
478
479 /*
480 ** Always return the SoftStraps - bootROM calls chipcHw_initValidStraps
481 ** which copies HW straps to soft straps if there is no override
482 */
483 softStraps = chipcHw_getSoftStraps();
484
485 return softStraps;
486}
487
488/****************************************************************************/
489/**
490* @brief Initialize valid pin strap options
491*
492* Retrieves valid pin strap options by copying HW strap options to soft register
493* (if chipcHw_STRAPS_SOFT_OVERRIDE not set)
494*
495* @return nothing
496*
497*/
498/****************************************************************************/
499static inline void chipcHw_initValidStraps(void)
500{
501 uint32_t softStraps;
502
503 REG_LOCAL_IRQ_SAVE;
504 softStraps = chipcHw_getSoftStraps();
505
506 if ((softStraps & chipcHw_STRAPS_SOFT_OVERRIDE) == 0) {
507 /* Copy HW straps to software straps */
508 chipcHw_setSoftStraps(chipcHw_getPinStraps());
509 }
510 REG_LOCAL_IRQ_RESTORE;
511}
512
513/****************************************************************************/
514/**
515* @brief Get boot device
516*
517* This function returns the device type used in booting the system
518*
519* @return Boot device of type chipcHw_BOOT_DEVICE
520*
521*/
522/****************************************************************************/
523static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void)
524{
525 return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_DEVICE_MASK;
526}
527
528/****************************************************************************/
529/**
530* @brief Get boot mode
531*
532* This function returns the way the system was booted
533*
534* @return Boot mode of type chipcHw_BOOT_MODE
535*
536*/
537/****************************************************************************/
538static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void)
539{
540 return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_MODE_MASK;
541}
542
543/****************************************************************************/
544/**
545* @brief Get NAND flash page size
546*
547* This function returns the NAND device page size
548*
549* @return Boot NAND device page size
550*
551*/
552/****************************************************************************/
553static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void)
554{
555 return chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_PAGESIZE_MASK;
556}
557
558/****************************************************************************/
559/**
560* @brief Get NAND flash address cycle configuration
561*
562* This function returns the NAND flash address cycle configuration
563*
564* @return 0 = Do not extra address cycle, 1 = Add extra cycle
565*
566*/
567/****************************************************************************/
568static inline int chipcHw_getNandExtraCycle(void)
569{
570 if (chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_EXTRA_CYCLE) {
571 return 1;
572 } else {
573 return 0;
574 }
575}
576
577/****************************************************************************/
578/**
579* @brief Activates PIF interface
580*
581* This function activates PIF interface by taking control of LCD pins
582*
583* @note
584* When activated, LCD pins will be defined as follows for PIF operation
585*
586* CLD[17:0] = pif_data[17:0]
587* CLD[23:18] = pif_address[5:0]
588* CLPOWER = pif_wr_str
589* CLCP = pif_rd_str
590* CLAC = pif_hat1
591* CLFP = pif_hrdy1
592* CLLP = pif_hat2
593* GPIO[42] = pif_hrdy2
594*
595* In PIF mode, "pif_hrdy2" overrides other shared function for GPIO[42] pin
596*
597*/
598/****************************************************************************/
599static inline void chipcHw_activatePifInterface(void)
600{
601 reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_PIF_PIN_ENABLE);
602}
603
604/****************************************************************************/
605/**
606* @brief Activates LCD interface
607*
608* This function activates LCD interface
609*
610* @note
611* When activated, LCD pins will be defined as follows
612*
613* CLD[17:0] = LCD data
614* CLD[23:18] = LCD data
615* CLPOWER = LCD power
616* CLCP =
617* CLAC = LCD ack
618* CLFP =
619* CLLP =
620*/
621/****************************************************************************/
622static inline void chipcHw_activateLcdInterface(void)
623{
624 reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_LCD_PIN_ENABLE);
625}
626
627/****************************************************************************/
628/**
629* @brief Deactivates PIF/LCD interface
630*
631* This function deactivates PIF/LCD interface
632*
633* @note
634* When deactivated LCD pins will be in rti-stated
635*
636*/
637/****************************************************************************/
638static inline void chipcHw_deactivatePifLcdInterface(void)
639{
640 reg32_write(&pChipcHw->LcdPifMode, 0);
641}
642
643/****************************************************************************/
644/**
645* @brief Select GE2
646*
647* This function select GE2 as the graphic engine
648*
649*/
650/****************************************************************************/
651static inline void chipcHw_selectGE2(void)
652{
653 reg32_modify_and(&pChipcHw->MiscCtrl, ~chipcHw_REG_MISC_CTRL_GE_SEL);
654}
655
656/****************************************************************************/
657/**
658* @brief Select GE3
659*
660* This function select GE3 as the graphic engine
661*
662*/
663/****************************************************************************/
664static inline void chipcHw_selectGE3(void)
665{
666 reg32_modify_or(&pChipcHw->MiscCtrl, chipcHw_REG_MISC_CTRL_GE_SEL);
667}
668
669/****************************************************************************/
670/**
671* @brief Get to know the configuration of GPIO pin
672*
673*/
674/****************************************************************************/
675static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin)
676{
677 return (readl(chipcHw_REG_GPIO_MUX(pin))) &
678 (chipcHw_REG_GPIO_MUX_MASK <<
679 chipcHw_REG_GPIO_MUX_POSITION(pin)) >>
680 chipcHw_REG_GPIO_MUX_POSITION(pin);
681}
682
683/****************************************************************************/
684/**
685* @brief Configure GPIO pin function
686*
687*/
688/****************************************************************************/
689static inline void chipcHw_setGpioPinFunction(int pin,
690 chipcHw_GPIO_FUNCTION_e func)
691{
692 REG_LOCAL_IRQ_SAVE;
693 *((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &=
694 ~(chipcHw_REG_GPIO_MUX_MASK << chipcHw_REG_GPIO_MUX_POSITION(pin));
695 *((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) |=
696 func << chipcHw_REG_GPIO_MUX_POSITION(pin);
697 REG_LOCAL_IRQ_RESTORE;
698}
699
700/****************************************************************************/
701/**
702* @brief Set Pin slew rate
703*
704* This function sets the slew of individual pin
705*
706*/
707/****************************************************************************/
708static inline void chipcHw_setPinSlewRate(uint32_t pin,
709 chipcHw_PIN_SLEW_RATE_e slewRate)
710{
711 REG_LOCAL_IRQ_SAVE;
712 *((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) &=
713 ~(chipcHw_REG_SLEW_RATE_MASK <<
714 chipcHw_REG_SLEW_RATE_POSITION(pin));
715 *((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) |=
716 (uint32_t) slewRate << chipcHw_REG_SLEW_RATE_POSITION(pin);
717 REG_LOCAL_IRQ_RESTORE;
718}
719
720/****************************************************************************/
721/**
722* @brief Set Pin output drive current
723*
724* This function sets output drive current of individual pin
725*
726* Note: Avoid the use of the word 'current' since linux headers define this
727* to be the current task.
728*/
729/****************************************************************************/
730static inline void chipcHw_setPinOutputCurrent(uint32_t pin,
731 chipcHw_PIN_CURRENT_STRENGTH_e
732 curr)
733{
734 REG_LOCAL_IRQ_SAVE;
735 *((uint32_t *) chipcHw_REG_CURRENT(pin)) &=
736 ~(chipcHw_REG_CURRENT_MASK << chipcHw_REG_CURRENT_POSITION(pin));
737 *((uint32_t *) chipcHw_REG_CURRENT(pin)) |=
738 (uint32_t) curr << chipcHw_REG_CURRENT_POSITION(pin);
739 REG_LOCAL_IRQ_RESTORE;
740}
741
742/****************************************************************************/
743/**
744* @brief Set Pin pullup register
745*
746* This function sets pullup register of individual pin
747*
748*/
749/****************************************************************************/
750static inline void chipcHw_setPinPullup(uint32_t pin, chipcHw_PIN_PULL_e pullup)
751{
752 REG_LOCAL_IRQ_SAVE;
753 *((uint32_t *) chipcHw_REG_PULLUP(pin)) &=
754 ~(chipcHw_REG_PULLUP_MASK << chipcHw_REG_PULLUP_POSITION(pin));
755 *((uint32_t *) chipcHw_REG_PULLUP(pin)) |=
756 (uint32_t) pullup << chipcHw_REG_PULLUP_POSITION(pin);
757 REG_LOCAL_IRQ_RESTORE;
758}
759
760/****************************************************************************/
761/**
762* @brief Set Pin input type
763*
764* This function sets input type of individual pin
765*
766*/
767/****************************************************************************/
768static inline void chipcHw_setPinInputType(uint32_t pin,
769 chipcHw_PIN_INPUTTYPE_e inputType)
770{
771 REG_LOCAL_IRQ_SAVE;
772 *((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) &=
773 ~(chipcHw_REG_INPUTTYPE_MASK <<
774 chipcHw_REG_INPUTTYPE_POSITION(pin));
775 *((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) |=
776 (uint32_t) inputType << chipcHw_REG_INPUTTYPE_POSITION(pin);
777 REG_LOCAL_IRQ_RESTORE;
778}
779
780/****************************************************************************/
781/**
782* @brief Power up the USB PHY
783*
784* This function powers up the USB PHY
785*
786*/
787/****************************************************************************/
788static inline void chipcHw_powerUpUsbPhy(void)
789{
790 reg32_modify_and(&pChipcHw->MiscCtrl,
791 chipcHw_REG_MISC_CTRL_USB_POWERON);
792}
793
794/****************************************************************************/
795/**
796* @brief Power down the USB PHY
797*
798* This function powers down the USB PHY
799*
800*/
801/****************************************************************************/
802static inline void chipcHw_powerDownUsbPhy(void)
803{
804 reg32_modify_or(&pChipcHw->MiscCtrl,
805 chipcHw_REG_MISC_CTRL_USB_POWEROFF);
806}
807
808/****************************************************************************/
809/**
810* @brief Set the 2nd USB as host
811*
812* This function sets the 2nd USB as host
813*
814*/
815/****************************************************************************/
816static inline void chipcHw_setUsbHost(void)
817{
818 reg32_modify_or(&pChipcHw->MiscCtrl,
819 chipcHw_REG_MISC_CTRL_USB_MODE_HOST);
820}
821
822/****************************************************************************/
823/**
824* @brief Set the 2nd USB as device
825*
826* This function sets the 2nd USB as device
827*
828*/
829/****************************************************************************/
830static inline void chipcHw_setUsbDevice(void)
831{
832 reg32_modify_and(&pChipcHw->MiscCtrl,
833 chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE);
834}
835
836/****************************************************************************/
837/**
838* @brief Lower layer function to enable/disable a clock of a certain device
839*
840* This function enables/disables a core clock
841*
842*/
843/****************************************************************************/
844static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
845 chipcHw_OPTYPE_e type, int mode)
846{
847 uint32_t __iomem *pPLLReg = NULL;
848 uint32_t __iomem *pClockCtrl = NULL;
849
850 switch (clock) {
851 case chipcHw_CLOCK_DDR:
852 pPLLReg = &pChipcHw->DDRClock;
853 break;
854 case chipcHw_CLOCK_ARM:
855 pPLLReg = &pChipcHw->ARMClock;
856 break;
857 case chipcHw_CLOCK_ESW:
858 pPLLReg = &pChipcHw->ESWClock;
859 break;
860 case chipcHw_CLOCK_VPM:
861 pPLLReg = &pChipcHw->VPMClock;
862 break;
863 case chipcHw_CLOCK_ESW125:
864 pPLLReg = &pChipcHw->ESW125Clock;
865 break;
866 case chipcHw_CLOCK_UART:
867 pPLLReg = &pChipcHw->UARTClock;
868 break;
869 case chipcHw_CLOCK_SDIO0:
870 pPLLReg = &pChipcHw->SDIO0Clock;
871 break;
872 case chipcHw_CLOCK_SDIO1:
873 pPLLReg = &pChipcHw->SDIO1Clock;
874 break;
875 case chipcHw_CLOCK_SPI:
876 pPLLReg = &pChipcHw->SPIClock;
877 break;
878 case chipcHw_CLOCK_ETM:
879 pPLLReg = &pChipcHw->ETMClock;
880 break;
881 case chipcHw_CLOCK_USB:
882 pPLLReg = &pChipcHw->USBClock;
883 if (type == chipcHw_OPTYPE_OUTPUT) {
884 if (mode) {
885 reg32_modify_and(pPLLReg,
886 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
887 } else {
888 reg32_modify_or(pPLLReg,
889 chipcHw_REG_PLL_CLOCK_POWER_DOWN);
890 }
891 }
892 break;
893 case chipcHw_CLOCK_LCD:
894 pPLLReg = &pChipcHw->LCDClock;
895 if (type == chipcHw_OPTYPE_OUTPUT) {
896 if (mode) {
897 reg32_modify_and(pPLLReg,
898 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
899 } else {
900 reg32_modify_or(pPLLReg,
901 chipcHw_REG_PLL_CLOCK_POWER_DOWN);
902 }
903 }
904 break;
905 case chipcHw_CLOCK_APM:
906 pPLLReg = &pChipcHw->APMClock;
907 if (type == chipcHw_OPTYPE_OUTPUT) {
908 if (mode) {
909 reg32_modify_and(pPLLReg,
910 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
911 } else {
912 reg32_modify_or(pPLLReg,
913 chipcHw_REG_PLL_CLOCK_POWER_DOWN);
914 }
915 }
916 break;
917 case chipcHw_CLOCK_BUS:
918 pClockCtrl = &pChipcHw->ACLKClock;
919 break;
920 case chipcHw_CLOCK_OTP:
921 pClockCtrl = &pChipcHw->OTPClock;
922 break;
923 case chipcHw_CLOCK_I2C:
924 pClockCtrl = &pChipcHw->I2CClock;
925 break;
926 case chipcHw_CLOCK_I2S0:
927 pClockCtrl = &pChipcHw->I2S0Clock;
928 break;
929 case chipcHw_CLOCK_RTBUS:
930 pClockCtrl = &pChipcHw->RTBUSClock;
931 break;
932 case chipcHw_CLOCK_APM100:
933 pClockCtrl = &pChipcHw->APM100Clock;
934 break;
935 case chipcHw_CLOCK_TSC:
936 pClockCtrl = &pChipcHw->TSCClock;
937 break;
938 case chipcHw_CLOCK_LED:
939 pClockCtrl = &pChipcHw->LEDClock;
940 break;
941 case chipcHw_CLOCK_I2S1:
942 pClockCtrl = &pChipcHw->I2S1Clock;
943 break;
944 }
945
946 if (pPLLReg) {
947 switch (type) {
948 case chipcHw_OPTYPE_OUTPUT:
949 /* PLL clock output enable/disable */
950 if (mode) {
951 if (clock == chipcHw_CLOCK_DDR) {
952 /* DDR clock enable is inverted */
953 reg32_modify_and(pPLLReg,
954 ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
955 } else {
956 reg32_modify_or(pPLLReg,
957 chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
958 }
959 } else {
960 if (clock == chipcHw_CLOCK_DDR) {
961 /* DDR clock disable is inverted */
962 reg32_modify_or(pPLLReg,
963 chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
964 } else {
965 reg32_modify_and(pPLLReg,
966 ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
967 }
968 }
969 break;
970 case chipcHw_OPTYPE_BYPASS:
971 /* PLL clock bypass enable/disable */
972 if (mode) {
973 reg32_modify_or(pPLLReg,
974 chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
975 } else {
976 reg32_modify_and(pPLLReg,
977 ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
978 }
979 break;
980 }
981 } else if (pClockCtrl) {
982 switch (type) {
983 case chipcHw_OPTYPE_OUTPUT:
984 if (mode) {
985 reg32_modify_or(pClockCtrl,
986 chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE);
987 } else {
988 reg32_modify_and(pClockCtrl,
989 ~chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE);
990 }
991 break;
992 case chipcHw_OPTYPE_BYPASS:
993 if (mode) {
994 reg32_modify_or(pClockCtrl,
995 chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
996 } else {
997 reg32_modify_and(pClockCtrl,
998 ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
999 }
1000 break;
1001 }
1002 }
1003}
1004
1005/****************************************************************************/
1006/**
1007* @brief Disables a core clock of a certain device
1008*
1009* This function disables a core clock
1010*
1011* @note no change in power consumption
1012*/
1013/****************************************************************************/
1014static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock)
1015{
1016
1017 /* Disable output of the clock */
1018 chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 0);
1019}
1020
1021/****************************************************************************/
1022/**
1023* @brief Enable a core clock of a certain device
1024*
1025* This function enables a core clock
1026*
1027* @note no change in power consumption
1028*/
1029/****************************************************************************/
1030static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock)
1031{
1032
1033 /* Enable output of the clock */
1034 chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 1);
1035}
1036
1037/****************************************************************************/
1038/**
1039* @brief Enables bypass clock of a certain device
1040*
1041* This function enables bypass clock
1042*
1043* @note Doesnot affect the bus interface clock
1044*/
1045/****************************************************************************/
1046static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock)
1047{
1048 /* Enable bypass clock */
1049 chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 1);
1050}
1051
1052/****************************************************************************/
1053/**
1054* @brief Disabled bypass clock of a certain device
1055*
1056* This function disables bypass clock
1057*
1058* @note Doesnot affect the bus interface clock
1059*/
1060/****************************************************************************/
1061static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock)
1062{
1063 /* Disable bypass clock */
1064 chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 0);
1065
1066}
1067
1068/****************************************************************************/
1069/** @brief Checks if software strap is enabled
1070 *
1071 * @return 1 : When enable
1072 * 0 : When disable
1073 */
1074/****************************************************************************/
1075static inline int chipcHw_isSoftwareStrapsEnable(void)
1076{
1077 return readl(&pChipcHw->SoftStraps) & 0x00000001;
1078}
1079
1080/****************************************************************************/
1081/** @brief Enable software strap
1082 */
1083/****************************************************************************/
1084static inline void chipcHw_softwareStrapsEnable(void)
1085{
1086 reg32_modify_or(&pChipcHw->SoftStraps, 0x00000001);
1087}
1088
1089/****************************************************************************/
1090/** @brief Disable software strap
1091 */
1092/****************************************************************************/
1093static inline void chipcHw_softwareStrapsDisable(void)
1094{
1095 reg32_modify_and(&pChipcHw->SoftStraps, (~0x00000001));
1096}
1097
1098/****************************************************************************/
1099/** @brief PLL test enable
1100 */
1101/****************************************************************************/
1102static inline void chipcHw_pllTestEnable(void)
1103{
1104 reg32_modify_or(&pChipcHw->PLLConfig,
1105 chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
1106}
1107
1108/****************************************************************************/
1109/** @brief PLL2 test enable
1110 */
1111/****************************************************************************/
1112static inline void chipcHw_pll2TestEnable(void)
1113{
1114 reg32_modify_or(&pChipcHw->PLLConfig2,
1115 chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
1116}
1117
1118/****************************************************************************/
1119/** @brief PLL test disable
1120 */
1121/****************************************************************************/
1122static inline void chipcHw_pllTestDisable(void)
1123{
1124 reg32_modify_and(&pChipcHw->PLLConfig,
1125 ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
1126}
1127
1128/****************************************************************************/
1129/** @brief PLL2 test disable
1130 */
1131/****************************************************************************/
1132static inline void chipcHw_pll2TestDisable(void)
1133{
1134 reg32_modify_and(&pChipcHw->PLLConfig2,
1135 ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
1136}
1137
1138/****************************************************************************/
1139/** @brief Get PLL test status
1140 */
1141/****************************************************************************/
1142static inline int chipcHw_isPllTestEnable(void)
1143{
1144 return readl(&pChipcHw->PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
1145}
1146
1147/****************************************************************************/
1148/** @brief Get PLL2 test status
1149 */
1150/****************************************************************************/
1151static inline int chipcHw_isPll2TestEnable(void)
1152{
1153 return readl(&pChipcHw->PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
1154}
1155
1156/****************************************************************************/
1157/** @brief PLL test select
1158 */
1159/****************************************************************************/
1160static inline void chipcHw_pllTestSelect(uint32_t val)
1161{
1162 REG_LOCAL_IRQ_SAVE;
1163 pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
1164 pChipcHw->PLLConfig |=
1165 (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT;
1166 REG_LOCAL_IRQ_RESTORE;
1167}
1168
1169/****************************************************************************/
1170/** @brief PLL2 test select
1171 */
1172/****************************************************************************/
1173static inline void chipcHw_pll2TestSelect(uint32_t val)
1174{
1175
1176 REG_LOCAL_IRQ_SAVE;
1177 pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
1178 pChipcHw->PLLConfig2 |=
1179 (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT;
1180 REG_LOCAL_IRQ_RESTORE;
1181}
1182
1183/****************************************************************************/
1184/** @brief Get PLL test selected option
1185 */
1186/****************************************************************************/
1187static inline uint8_t chipcHw_getPllTestSelected(void)
1188{
1189 return (uint8_t) ((readl(&pChipcHw->
1190 PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
1191 >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
1192}
1193
1194/****************************************************************************/
1195/** @brief Get PLL2 test selected option
1196 */
1197/****************************************************************************/
1198static inline uint8_t chipcHw_getPll2TestSelected(void)
1199{
1200 return (uint8_t) ((readl(&pChipcHw->
1201 PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
1202 >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
1203}
1204
1205/****************************************************************************/
1206/**
1207* @brief Disable the PLL1
1208*
1209*/
1210/****************************************************************************/
1211static inline void chipcHw_pll1Disable(void)
1212{
1213 REG_LOCAL_IRQ_SAVE;
1214 writel(readl(&pChipcHw->PLLConfig) | chipcHw_REG_PLL_CONFIG_POWER_DOWN,
1215 &pChipcHw->PLLConfig);
1216 REG_LOCAL_IRQ_RESTORE;
1217}
1218
1219/****************************************************************************/
1220/**
1221* @brief Disable the PLL2
1222*
1223*/
1224/****************************************************************************/
1225static inline void chipcHw_pll2Disable(void)
1226{
1227 REG_LOCAL_IRQ_SAVE;
1228 writel(readl(&pChipcHw->PLLConfig2) | chipcHw_REG_PLL_CONFIG_POWER_DOWN,
1229 &pChipcHw->PLLConfig2);
1230 REG_LOCAL_IRQ_RESTORE;
1231}
1232
1233/****************************************************************************/
1234/**
1235* @brief Enables DDR SW phase alignment interrupt
1236*/
1237/****************************************************************************/
1238static inline void chipcHw_ddrPhaseAlignInterruptEnable(void)
1239{
1240 REG_LOCAL_IRQ_SAVE;
1241 writel(readl(&pChipcHw->Spare1) | chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE,
1242 &pChipcHw->Spare1);
1243 REG_LOCAL_IRQ_RESTORE;
1244}
1245
1246/****************************************************************************/
1247/**
1248* @brief Disables DDR SW phase alignment interrupt
1249*/
1250/****************************************************************************/
1251static inline void chipcHw_ddrPhaseAlignInterruptDisable(void)
1252{
1253 REG_LOCAL_IRQ_SAVE;
1254 writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE,
1255 &pChipcHw->Spare1);
1256 REG_LOCAL_IRQ_RESTORE;
1257}
1258
1259/****************************************************************************/
1260/**
1261* @brief Set VPM SW phase alignment interrupt mode
1262*
1263* This function sets VPM phase alignment interrupt
1264*/
1265/****************************************************************************/
1266static inline void
1267chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode)
1268{
1269 REG_LOCAL_IRQ_SAVE;
1270 if (mode == chipcHw_VPM_HW_PHASE_INTR_DISABLE) {
1271 pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
1272 } else {
1273 pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
1274 }
1275 pChipcHw->VPMPhaseCtrl2 =
1276 (pChipcHw->
1277 VPMPhaseCtrl2 & ~(chipcHw_REG_VPM_INTR_SELECT_MASK <<
1278 chipcHw_REG_VPM_INTR_SELECT_SHIFT)) | mode;
1279 REG_LOCAL_IRQ_RESTORE;
1280}
1281
1282/****************************************************************************/
1283/**
1284* @brief Enable DDR phase alignment in software
1285*
1286*/
1287/****************************************************************************/
1288static inline void chipcHw_ddrSwPhaseAlignEnable(void)
1289{
1290 REG_LOCAL_IRQ_SAVE;
1291 pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
1292 REG_LOCAL_IRQ_RESTORE;
1293}
1294
1295/****************************************************************************/
1296/**
1297* @brief Disable DDR phase alignment in software
1298*
1299*/
1300/****************************************************************************/
1301static inline void chipcHw_ddrSwPhaseAlignDisable(void)
1302{
1303 REG_LOCAL_IRQ_SAVE;
1304 pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
1305 REG_LOCAL_IRQ_RESTORE;
1306}
1307
1308/****************************************************************************/
1309/**
1310* @brief Enable DDR phase alignment in hardware
1311*
1312*/
1313/****************************************************************************/
1314static inline void chipcHw_ddrHwPhaseAlignEnable(void)
1315{
1316 REG_LOCAL_IRQ_SAVE;
1317 pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
1318 REG_LOCAL_IRQ_RESTORE;
1319}
1320
1321/****************************************************************************/
1322/**
1323* @brief Disable DDR phase alignment in hardware
1324*
1325*/
1326/****************************************************************************/
1327static inline void chipcHw_ddrHwPhaseAlignDisable(void)
1328{
1329 REG_LOCAL_IRQ_SAVE;
1330 pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
1331 REG_LOCAL_IRQ_RESTORE;
1332}
1333
1334/****************************************************************************/
1335/**
1336* @brief Enable VPM phase alignment in software
1337*
1338*/
1339/****************************************************************************/
1340static inline void chipcHw_vpmSwPhaseAlignEnable(void)
1341{
1342 REG_LOCAL_IRQ_SAVE;
1343 writel(readl(&pChipcHw->VPMPhaseCtrl1) | chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE,
1344 &pChipcHw->VPMPhaseCtrl1);
1345 REG_LOCAL_IRQ_RESTORE;
1346}
1347
1348/****************************************************************************/
1349/**
1350* @brief Disable VPM phase alignment in software
1351*
1352*/
1353/****************************************************************************/
1354static inline void chipcHw_vpmSwPhaseAlignDisable(void)
1355{
1356 REG_LOCAL_IRQ_SAVE;
1357 pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
1358 REG_LOCAL_IRQ_RESTORE;
1359}
1360
1361/****************************************************************************/
1362/**
1363* @brief Enable VPM phase alignment in hardware
1364*
1365*/
1366/****************************************************************************/
1367static inline void chipcHw_vpmHwPhaseAlignEnable(void)
1368{
1369 REG_LOCAL_IRQ_SAVE;
1370 pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
1371 REG_LOCAL_IRQ_RESTORE;
1372}
1373
1374/****************************************************************************/
1375/**
1376* @brief Disable VPM phase alignment in hardware
1377*
1378*/
1379/****************************************************************************/
1380static inline void chipcHw_vpmHwPhaseAlignDisable(void)
1381{
1382 REG_LOCAL_IRQ_SAVE;
1383 writel(readl(&pChipcHw->VPMPhaseCtrl1) & ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE,
1384 &pChipcHw->VPMPhaseCtrl1);
1385 REG_LOCAL_IRQ_RESTORE;
1386}
1387
1388/****************************************************************************/
1389/**
1390* @brief Set DDR phase alignment margin in hardware
1391*
1392*/
1393/****************************************************************************/
1394static inline void
1395chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin)
1396{
1397 uint32_t ge = 0;
1398 uint32_t le = 0;
1399
1400 switch (margin) {
1401 case chipcHw_DDR_HW_PHASE_MARGIN_STRICT:
1402 ge = 0x0F;
1403 le = 0x0F;
1404 break;
1405 case chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM:
1406 ge = 0x03;
1407 le = 0x3F;
1408 break;
1409 case chipcHw_DDR_HW_PHASE_MARGIN_WIDE:
1410 ge = 0x01;
1411 le = 0x7F;
1412 break;
1413 }
1414
1415 {
1416 REG_LOCAL_IRQ_SAVE;
1417
1418 pChipcHw->DDRPhaseCtrl1 &=
1419 ~((chipcHw_REG_DDR_PHASE_VALUE_GE_MASK <<
1420 chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT)
1421 || (chipcHw_REG_DDR_PHASE_VALUE_LE_MASK <<
1422 chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT));
1423
1424 pChipcHw->DDRPhaseCtrl1 |=
1425 ((ge << chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT)
1426 || (le << chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT));
1427
1428 REG_LOCAL_IRQ_RESTORE;
1429 }
1430}
1431
1432/****************************************************************************/
1433/**
1434* @brief Set VPM phase alignment margin in hardware
1435*
1436*/
1437/****************************************************************************/
1438static inline void
1439chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin)
1440{
1441 uint32_t ge = 0;
1442 uint32_t le = 0;
1443
1444 switch (margin) {
1445 case chipcHw_VPM_HW_PHASE_MARGIN_STRICT:
1446 ge = 0x0F;
1447 le = 0x0F;
1448 break;
1449 case chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM:
1450 ge = 0x03;
1451 le = 0x3F;
1452 break;
1453 case chipcHw_VPM_HW_PHASE_MARGIN_WIDE:
1454 ge = 0x01;
1455 le = 0x7F;
1456 break;
1457 }
1458
1459 {
1460 REG_LOCAL_IRQ_SAVE;
1461
1462 pChipcHw->VPMPhaseCtrl1 &=
1463 ~((chipcHw_REG_VPM_PHASE_VALUE_GE_MASK <<
1464 chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT)
1465 || (chipcHw_REG_VPM_PHASE_VALUE_LE_MASK <<
1466 chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT));
1467
1468 pChipcHw->VPMPhaseCtrl1 |=
1469 ((ge << chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT)
1470 || (le << chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT));
1471
1472 REG_LOCAL_IRQ_RESTORE;
1473 }
1474}
1475
1476/****************************************************************************/
1477/**
1478* @brief Checks DDR phase aligned status done by HW
1479*
1480* @return 1: When aligned
1481* 0: When not aligned
1482*/
1483/****************************************************************************/
1484static inline uint32_t chipcHw_isDdrHwPhaseAligned(void)
1485{
1486 return (readl(&pChipcHw->
1487 PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0;
1488}
1489
1490/****************************************************************************/
1491/**
1492* @brief Checks VPM phase aligned status done by HW
1493*
1494* @return 1: When aligned
1495* 0: When not aligned
1496*/
1497/****************************************************************************/
1498static inline uint32_t chipcHw_isVpmHwPhaseAligned(void)
1499{
1500 return (readl(&pChipcHw->
1501 PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0;
1502}
1503
1504/****************************************************************************/
1505/**
1506* @brief Get DDR phase aligned status done by HW
1507*
1508*/
1509/****************************************************************************/
1510static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void)
1511{
1512 return (readl(&pChipcHw->
1513 PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_STATUS_MASK) >>
1514 chipcHw_REG_DDR_PHASE_STATUS_SHIFT;
1515}
1516
1517/****************************************************************************/
1518/**
1519* @brief Get VPM phase aligned status done by HW
1520*
1521*/
1522/****************************************************************************/
1523static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void)
1524{
1525 return (readl(&pChipcHw->
1526 PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_STATUS_MASK) >>
1527 chipcHw_REG_VPM_PHASE_STATUS_SHIFT;
1528}
1529
1530/****************************************************************************/
1531/**
1532* @brief Get DDR phase control value
1533*
1534*/
1535/****************************************************************************/
1536static inline uint32_t chipcHw_getDdrPhaseControl(void)
1537{
1538 return (readl(&pChipcHw->
1539 PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_CTRL_MASK) >>
1540 chipcHw_REG_DDR_PHASE_CTRL_SHIFT;
1541}
1542
1543/****************************************************************************/
1544/**
1545* @brief Get VPM phase control value
1546*
1547*/
1548/****************************************************************************/
1549static inline uint32_t chipcHw_getVpmPhaseControl(void)
1550{
1551 return (readl(&pChipcHw->
1552 PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_CTRL_MASK) >>
1553 chipcHw_REG_VPM_PHASE_CTRL_SHIFT;
1554}
1555
1556/****************************************************************************/
1557/**
1558* @brief DDR phase alignment timeout count
1559*
1560* @note If HW fails to perform the phase alignment, it will trigger
1561* a DDR phase alignment timeout interrupt.
1562*/
1563/****************************************************************************/
1564static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle)
1565{
1566 REG_LOCAL_IRQ_SAVE;
1567 pChipcHw->DDRPhaseCtrl2 &=
1568 ~(chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK <<
1569 chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT);
1570 pChipcHw->DDRPhaseCtrl2 |=
1571 (busCycle & chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK) <<
1572 chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT;
1573 REG_LOCAL_IRQ_RESTORE;
1574}
1575
1576/****************************************************************************/
1577/**
1578* @brief VPM phase alignment timeout count
1579*
1580* @note If HW fails to perform the phase alignment, it will trigger
1581* a VPM phase alignment timeout interrupt.
1582*/
1583/****************************************************************************/
1584static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle)
1585{
1586 REG_LOCAL_IRQ_SAVE;
1587 pChipcHw->VPMPhaseCtrl2 &=
1588 ~(chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK <<
1589 chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT);
1590 pChipcHw->VPMPhaseCtrl2 |=
1591 (busCycle & chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK) <<
1592 chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT;
1593 REG_LOCAL_IRQ_RESTORE;
1594}
1595
1596/****************************************************************************/
1597/**
1598* @brief Clear DDR phase alignment timeout interrupt
1599*
1600*/
1601/****************************************************************************/
1602static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void)
1603{
1604 REG_LOCAL_IRQ_SAVE;
1605 /* Clear timeout interrupt service bit */
1606 pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_INTR_SERVICED;
1607 pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_INTR_SERVICED;
1608 REG_LOCAL_IRQ_RESTORE;
1609}
1610
1611/****************************************************************************/
1612/**
1613* @brief Clear VPM phase alignment timeout interrupt
1614*
1615*/
1616/****************************************************************************/
1617static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void)
1618{
1619 REG_LOCAL_IRQ_SAVE;
1620 /* Clear timeout interrupt service bit */
1621 pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_INTR_SERVICED;
1622 pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_INTR_SERVICED;
1623 REG_LOCAL_IRQ_RESTORE;
1624}
1625
1626/****************************************************************************/
1627/**
1628* @brief DDR phase alignment timeout interrupt enable
1629*
1630*/
1631/****************************************************************************/
1632static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void)
1633{
1634 REG_LOCAL_IRQ_SAVE;
1635 chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(); /* Recommended */
1636 /* Enable timeout interrupt */
1637 pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
1638 REG_LOCAL_IRQ_RESTORE;
1639}
1640
1641/****************************************************************************/
1642/**
1643* @brief VPM phase alignment timeout interrupt enable
1644*
1645*/
1646/****************************************************************************/
1647static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void)
1648{
1649 REG_LOCAL_IRQ_SAVE;
1650 chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(); /* Recommended */
1651 /* Enable timeout interrupt */
1652 pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;
1653 REG_LOCAL_IRQ_RESTORE;
1654}
1655
1656/****************************************************************************/
1657/**
1658* @brief DDR phase alignment timeout interrupt disable
1659*
1660*/
1661/****************************************************************************/
1662static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void)
1663{
1664 REG_LOCAL_IRQ_SAVE;
1665 pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
1666 REG_LOCAL_IRQ_RESTORE;
1667}
1668
1669/****************************************************************************/
1670/**
1671* @brief VPM phase alignment timeout interrupt disable
1672*
1673*/
1674/****************************************************************************/
1675static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void)
1676{
1677 REG_LOCAL_IRQ_SAVE;
1678 pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;
1679 REG_LOCAL_IRQ_RESTORE;
1680}
1681
1682#endif /* CHIPC_INLINE_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
deleted file mode 100644
index 26f5d0e4e1dd..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
+++ /dev/null
@@ -1,530 +0,0 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file chipcHw_reg.h
18*
19* @brief Definitions for low level chip control registers
20*
21*/
22/****************************************************************************/
23#ifndef CHIPCHW_REG_H
24#define CHIPCHW_REG_H
25
26#include <mach/csp/mm_io.h>
27#include <mach/csp/reg.h>
28#include <mach/csp/ddrcReg.h>
29
30#define chipcHw_BASE_ADDRESS MM_IO_BASE_CHIPC
31
32typedef struct {
33 uint32_t ChipId; /* Chip ID */
34 uint32_t DDRClock; /* PLL1 Channel 1 for DDR clock */
35 uint32_t ARMClock; /* PLL1 Channel 2 for ARM clock */
36 uint32_t ESWClock; /* PLL1 Channel 3 for ESW system clock */
37 uint32_t VPMClock; /* PLL1 Channel 4 for VPM clock */
38 uint32_t ESW125Clock; /* PLL1 Channel 5 for ESW 125MHz clock */
39 uint32_t UARTClock; /* PLL1 Channel 6 for UART clock */
40 uint32_t SDIO0Clock; /* PLL1 Channel 7 for SDIO 0 clock */
41 uint32_t SDIO1Clock; /* PLL1 Channel 8 for SDIO 1 clock */
42 uint32_t SPIClock; /* PLL1 Channel 9 for SPI master Clock */
43 uint32_t ETMClock; /* PLL1 Channel 10 for ARM ETM Clock */
44
45 uint32_t ACLKClock; /* ACLK Clock (Divider) */
46 uint32_t OTPClock; /* OTP Clock (Divider) */
47 uint32_t I2CClock; /* I2C Clock (CK_13m) (Divider) */
48 uint32_t I2S0Clock; /* I2S0 Clock (Divider) */
49 uint32_t RTBUSClock; /* RTBUS (DDR PHY Config.) Clock (Divider) */
50 uint32_t pad1;
51 uint32_t APM100Clock; /* APM 100MHz CLK Clock (Divider) */
52 uint32_t TSCClock; /* TSC Clock (Divider) */
53 uint32_t LEDClock; /* LED Clock (Divider) */
54
55 uint32_t USBClock; /* PLL2 Channel 1 for USB clock */
56 uint32_t LCDClock; /* PLL2 Channel 2 for LCD clock */
57 uint32_t APMClock; /* PLL2 Channel 3 for APM 200 MHz clock */
58
59 uint32_t BusIntfClock; /* Bus interface clock */
60
61 uint32_t PLLStatus; /* PLL status register (PLL1) */
62 uint32_t PLLConfig; /* PLL configuration register (PLL1) */
63 uint32_t PLLPreDivider; /* PLL pre-divider control register (PLL1) */
64 uint32_t PLLDivider; /* PLL divider control register (PLL1) */
65 uint32_t PLLControl1; /* PLL analog control register #1 (PLL1) */
66 uint32_t PLLControl2; /* PLL analog control register #2 (PLL1) */
67
68 uint32_t I2S1Clock; /* I2S1 Clock */
69 uint32_t AudioEnable; /* Enable/ disable audio channel */
70 uint32_t SoftReset1; /* Reset blocks */
71 uint32_t SoftReset2; /* Reset blocks */
72 uint32_t Spare1; /* Phase align interrupts */
73 uint32_t Sticky; /* Sticky bits */
74 uint32_t MiscCtrl; /* Misc. control */
75 uint32_t pad3[3];
76
77 uint32_t PLLStatus2; /* PLL status register (PLL2) */
78 uint32_t PLLConfig2; /* PLL configuration register (PLL2) */
79 uint32_t PLLPreDivider2; /* PLL pre-divider control register (PLL2) */
80 uint32_t PLLDivider2; /* PLL divider control register (PLL2) */
81 uint32_t PLLControl12; /* PLL analog control register #1 (PLL2) */
82 uint32_t PLLControl22; /* PLL analog control register #2 (PLL2) */
83
84 uint32_t DDRPhaseCtrl1; /* DDR Clock Phase Alignment control1 */
85 uint32_t VPMPhaseCtrl1; /* VPM Clock Phase Alignment control1 */
86 uint32_t PhaseAlignStatus; /* DDR/VPM Clock Phase Alignment Status */
87 uint32_t PhaseCtrlStatus; /* DDR/VPM Clock HW DDR/VPM ph_ctrl and load_ch Status */
88 uint32_t DDRPhaseCtrl2; /* DDR Clock Phase Alignment control2 */
89 uint32_t VPMPhaseCtrl2; /* VPM Clock Phase Alignment control2 */
90 uint32_t pad4[9];
91
92 uint32_t SoftOTP1; /* Software OTP control */
93 uint32_t SoftOTP2; /* Software OTP control */
94 uint32_t SoftStraps; /* Software strap */
95 uint32_t PinStraps; /* Pin Straps */
96 uint32_t DiffOscCtrl; /* Diff oscillator control */
97 uint32_t DiagsCtrl; /* Diagnostic control */
98 uint32_t DiagsOutputCtrl; /* Diagnostic output enable */
99 uint32_t DiagsReadBackCtrl; /* Diagnostic read back control */
100
101 uint32_t LcdPifMode; /* LCD/PIF Pin Sharing MUX Mode */
102
103 uint32_t GpioMux_0_7; /* Pin Sharing MUX0 Control */
104 uint32_t GpioMux_8_15; /* Pin Sharing MUX1 Control */
105 uint32_t GpioMux_16_23; /* Pin Sharing MUX2 Control */
106 uint32_t GpioMux_24_31; /* Pin Sharing MUX3 Control */
107 uint32_t GpioMux_32_39; /* Pin Sharing MUX4 Control */
108 uint32_t GpioMux_40_47; /* Pin Sharing MUX5 Control */
109 uint32_t GpioMux_48_55; /* Pin Sharing MUX6 Control */
110 uint32_t GpioMux_56_63; /* Pin Sharing MUX7 Control */
111
112 uint32_t GpioSR_0_7; /* Slew rate for GPIO 0 - 7 */
113 uint32_t GpioSR_8_15; /* Slew rate for GPIO 8 - 15 */
114 uint32_t GpioSR_16_23; /* Slew rate for GPIO 16 - 23 */
115 uint32_t GpioSR_24_31; /* Slew rate for GPIO 24 - 31 */
116 uint32_t GpioSR_32_39; /* Slew rate for GPIO 32 - 39 */
117 uint32_t GpioSR_40_47; /* Slew rate for GPIO 40 - 47 */
118 uint32_t GpioSR_48_55; /* Slew rate for GPIO 48 - 55 */
119 uint32_t GpioSR_56_63; /* Slew rate for GPIO 56 - 63 */
120 uint32_t MiscSR_0_7; /* Slew rate for MISC 0 - 7 */
121 uint32_t MiscSR_8_15; /* Slew rate for MISC 8 - 15 */
122
123 uint32_t GpioPull_0_15; /* Pull up registers for GPIO 0 - 15 */
124 uint32_t GpioPull_16_31; /* Pull up registers for GPIO 16 - 31 */
125 uint32_t GpioPull_32_47; /* Pull up registers for GPIO 32 - 47 */
126 uint32_t GpioPull_48_63; /* Pull up registers for GPIO 48 - 63 */
127 uint32_t MiscPull_0_15; /* Pull up registers for MISC 0 - 15 */
128
129 uint32_t GpioInput_0_31; /* Input type for GPIO 0 - 31 */
130 uint32_t GpioInput_32_63; /* Input type for GPIO 32 - 63 */
131 uint32_t MiscInput_0_15; /* Input type for MISC 0 - 16 */
132} chipcHw_REG_t;
133
134#define pChipcHw ((chipcHw_REG_t __iomem *) chipcHw_BASE_ADDRESS)
135#define pChipcPhysical (MM_ADDR_IO_CHIPC)
136
137#define chipcHw_REG_CHIPID_BASE_MASK 0xFFFFF000
138#define chipcHw_REG_CHIPID_BASE_SHIFT 12
139#define chipcHw_REG_CHIPID_REV_MASK 0x00000FFF
140#define chipcHw_REG_REV_A0 0xA00
141#define chipcHw_REG_REV_B0 0x0B0
142
143#define chipcHw_REG_PLL_STATUS_CONTROL_ENABLE 0x80000000 /* Allow controlling PLL registers */
144#define chipcHw_REG_PLL_STATUS_LOCKED 0x00000001 /* PLL is settled */
145#define chipcHw_REG_PLL_CONFIG_D_RESET 0x00000008 /* Digital reset */
146#define chipcHw_REG_PLL_CONFIG_A_RESET 0x00000004 /* Analog reset */
147#define chipcHw_REG_PLL_CONFIG_BYPASS_ENABLE 0x00000020 /* Bypass enable */
148#define chipcHw_REG_PLL_CONFIG_OUTPUT_ENABLE 0x00000010 /* Output enable */
149#define chipcHw_REG_PLL_CONFIG_POWER_DOWN 0x00000001 /* Power down */
150#define chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ 1600000000 /* 1.6GHz VCO split frequency */
151#define chipcHw_REG_PLL_CONFIG_VCO_800_1600 0x00000000 /* VCO range 800-1600 MHz */
152#define chipcHw_REG_PLL_CONFIG_VCO_1601_3200 0x00000080 /* VCO range 1601-3200 MHz */
153#define chipcHw_REG_PLL_CONFIG_TEST_ENABLE 0x00010000 /* PLL test output enable */
154#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK 0x003E0000 /* Mask to set test values */
155#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT 17
156
157#define chipcHw_REG_PLL_CLOCK_PHASE_COMP 0x00800000 /* Phase comparator output */
158#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK 0x00300000 /* Clock to bus ratio mask */
159#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT 20 /* Number of bits to be shifted */
160#define chipcHw_REG_PLL_CLOCK_POWER_DOWN 0x00080000 /* PLL channel power down */
161#define chipcHw_REG_PLL_CLOCK_SOURCE_GPIO 0x00040000 /* Use GPIO as source */
162#define chipcHw_REG_PLL_CLOCK_BYPASS_SELECT 0x00020000 /* Select bypass clock */
163#define chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE 0x00010000 /* Clock gated ON */
164#define chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE 0x00008000 /* Clock phase update enable */
165#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT 8 /* Number of bits to be shifted */
166#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK 0x00003F00 /* Phase control mask */
167#define chipcHw_REG_PLL_CLOCK_MDIV_MASK 0x000000FF /* Clock post divider mask
168
169 00000000 = divide-by-256
170 00000001 = divide-by-1
171 00000010 = divide-by-2
172 00000011 = divide-by-3
173 00000100 = divide-by-4
174 00000101 = divide-by-5
175 00000110 = divide-by-6
176 .
177 .
178 11111011 = divide-by-251
179 11111100 = divide-by-252
180 11111101 = divide-by-253
181 11111110 = divide-by-254
182 */
183
184#define chipcHw_REG_DIV_CLOCK_SOURCE_OTHER 0x00040000 /* NON-PLL clock source select */
185#define chipcHw_REG_DIV_CLOCK_BYPASS_SELECT 0x00020000 /* NON-PLL clock bypass enable */
186#define chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE 0x00010000 /* NON-PLL clock output enable */
187#define chipcHw_REG_DIV_CLOCK_DIV_MASK 0x000000FF /* NON-PLL clock post-divide mask */
188#define chipcHw_REG_DIV_CLOCK_DIV_256 0x00000000 /* NON-PLL clock post-divide by 256 */
189
190#define chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT 0
191#define chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT 4
192#define chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT 8
193#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK 0x0001FF00
194#define chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN 0x02000000
195#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK 0x00700000 /* Divider mask */
196#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER 0x00000000 /* Integer-N Mode */
197#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_UNIT 0x00100000 /* MASH Sigma-Delta Modulator Unit Mode */
198#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_UNIT 0x00200000 /* MFB Sigma-Delta Modulator Unit Mode */
199#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8 0x00300000 /* MASH Sigma-Delta Modulator 1/8 Mode */
200#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_1_8 0x00400000 /* MFB Sigma-Delta Modulator 1/8 Mode */
201
202#define chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vco) ((vco) / chipcHw_XTAL_FREQ_Hz)
203#define chipcHw_REG_PLL_PREDIVIDER_P1 1
204#define chipcHw_REG_PLL_PREDIVIDER_P2 1
205
206#define chipcHw_REG_PLL_DIVIDER_M1DIV 0x03000000
207#define chipcHw_REG_PLL_DIVIDER_FRAC 0x00FFFFFF /* Fractional divider */
208
209#define chipcHw_REG_PLL_DIVIDER_NDIV_f_SS (0x00FFFFFF) /* To attain spread with max frequency */
210
211#define chipcHw_REG_PLL_DIVIDER_NDIV_f 0 /* ndiv_frac = chipcHw_REG_PLL_DIVIDER_NDIV_f /
212 chipcHw_REG_PLL_DIVIDER_FRAC
213 = 0, when SS is disable
214 */
215
216#define chipcHw_REG_PLL_DIVIDER_MDIV(vco, Hz) ((chipcHw_divide((vco), (Hz)) > 255) ? 0 : chipcHw_divide((vco), (Hz)))
217
218#define chipcHw_REG_ACLKClock_CLK_DIV_MASK 0x3
219
220/* System booting strap options */
221#define chipcHw_STRAPS_SOFT_OVERRIDE 0x00000001 /* Software Strap Override */
222
223#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8 0x00000000 /* 8 bit NAND FLASH Boot */
224#define chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16 0x00000002 /* 16 bit NOR FLASH Boot */
225#define chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH 0x00000004 /* Serial FLASH Boot */
226#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16 0x00000006 /* 16 bit NAND FLASH Boot */
227#define chipcHw_STRAPS_BOOT_DEVICE_UART 0x00000008 /* UART Boot */
228#define chipcHw_STRAPS_BOOT_DEVICE_MASK 0x0000000E /* Mask */
229
230/* System boot option */
231#define chipcHw_STRAPS_BOOT_OPTION_BROM 0x00000000 /* Boot from Boot ROM */
232#define chipcHw_STRAPS_BOOT_OPTION_ARAM 0x00000020 /* Boot from ARAM */
233#define chipcHw_STRAPS_BOOT_OPTION_NOR 0x00000030 /* Boot from NOR flash */
234
235/* NAND Flash page size strap options */
236#define chipcHw_STRAPS_NAND_PAGESIZE_512 0x00000000 /* NAND FLASH page size of 512 bytes */
237#define chipcHw_STRAPS_NAND_PAGESIZE_2048 0x00000040 /* NAND FLASH page size of 2048 bytes */
238#define chipcHw_STRAPS_NAND_PAGESIZE_4096 0x00000080 /* NAND FLASH page size of 4096 bytes */
239#define chipcHw_STRAPS_NAND_PAGESIZE_EXT 0x000000C0 /* NAND FLASH page of extened size */
240#define chipcHw_STRAPS_NAND_PAGESIZE_MASK 0x000000C0 /* Mask */
241
242#define chipcHw_STRAPS_NAND_EXTRA_CYCLE 0x00000400 /* NAND FLASH address cycle configuration */
243#define chipcHw_STRAPS_REBOOT_TO_UART 0x00000800 /* Reboot to UART on error */
244
245/* Secure boot mode strap options */
246#define chipcHw_STRAPS_BOOT_MODE_NORMAL 0x00000000 /* Normal Boot */
247#define chipcHw_STRAPS_BOOT_MODE_DBG_SW 0x00000100 /* Software debugging Boot */
248#define chipcHw_STRAPS_BOOT_MODE_DBG_BOOT 0x00000200 /* Boot rom debugging Boot */
249#define chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET 0x00000300 /* Normal Boot (Quiet BootRom) */
250#define chipcHw_STRAPS_BOOT_MODE_MASK 0x00000300 /* Mask */
251
252/* Slave Mode straps */
253#define chipcHw_STRAPS_I2CS 0x02000000 /* I2C Slave */
254#define chipcHw_STRAPS_SPIS 0x01000000 /* SPI Slave */
255
256/* Strap pin options */
257#define chipcHw_REG_SW_STRAPS ((pChipcHw->PinStraps & 0x0000FC00) >> 10)
258
259/* PIF/LCD pin sharing defines */
260#define chipcHw_REG_LCD_PIN_ENABLE 0x00000001 /* LCD Controller is used and the pins have LCD functions */
261#define chipcHw_REG_PIF_PIN_ENABLE 0x00000002 /* LCD pins are used to perform PIF functions */
262
263#define chipcHw_GPIO_COUNT 61 /* Number of GPIO pin accessible thorugh CHIPC */
264
265/* NOTE: Any changes to these constants will require a corresponding change to chipcHw_str.c */
266#define chipcHw_REG_GPIO_MUX_KEYPAD 0x00000001 /* GPIO mux for Keypad */
267#define chipcHw_REG_GPIO_MUX_I2CH 0x00000002 /* GPIO mux for I2CH */
268#define chipcHw_REG_GPIO_MUX_SPI 0x00000003 /* GPIO mux for SPI */
269#define chipcHw_REG_GPIO_MUX_UART 0x00000004 /* GPIO mux for UART */
270#define chipcHw_REG_GPIO_MUX_LEDMTXP 0x00000005 /* GPIO mux for LEDMTXP */
271#define chipcHw_REG_GPIO_MUX_LEDMTXS 0x00000006 /* GPIO mux for LEDMTXS */
272#define chipcHw_REG_GPIO_MUX_SDIO0 0x00000007 /* GPIO mux for SDIO0 */
273#define chipcHw_REG_GPIO_MUX_SDIO1 0x00000008 /* GPIO mux for SDIO1 */
274#define chipcHw_REG_GPIO_MUX_PCM 0x00000009 /* GPIO mux for PCM */
275#define chipcHw_REG_GPIO_MUX_I2S 0x0000000A /* GPIO mux for I2S */
276#define chipcHw_REG_GPIO_MUX_ETM 0x0000000B /* GPIO mux for ETM */
277#define chipcHw_REG_GPIO_MUX_DEBUG 0x0000000C /* GPIO mux for DEBUG */
278#define chipcHw_REG_GPIO_MUX_MISC 0x0000000D /* GPIO mux for MISC */
279#define chipcHw_REG_GPIO_MUX_GPIO 0x00000000 /* GPIO mux for GPIO */
280#define chipcHw_REG_GPIO_MUX(pin) (&pChipcHw->GpioMux_0_7 + ((pin) >> 3))
281#define chipcHw_REG_GPIO_MUX_POSITION(pin) (((pin) & 0x00000007) << 2)
282#define chipcHw_REG_GPIO_MUX_MASK 0x0000000F /* Mask */
283
284#define chipcHw_REG_SLEW_RATE_HIGH 0x00000000 /* High speed slew rate */
285#define chipcHw_REG_SLEW_RATE_NORMAL 0x00000008 /* Normal slew rate */
286 /* Pins beyond 42 are defined by skipping 8 bits within the register */
287#define chipcHw_REG_SLEW_RATE(pin) (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3)))
288#define chipcHw_REG_SLEW_RATE_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2))
289#define chipcHw_REG_SLEW_RATE_MASK 0x00000008 /* Mask */
290
291#define chipcHw_REG_CURRENT_STRENGTH_2mA 0x00000001 /* Current driving strength 2 milli ampere */
292#define chipcHw_REG_CURRENT_STRENGTH_4mA 0x00000002 /* Current driving strength 4 milli ampere */
293#define chipcHw_REG_CURRENT_STRENGTH_6mA 0x00000004 /* Current driving strength 6 milli ampere */
294#define chipcHw_REG_CURRENT_STRENGTH_8mA 0x00000005 /* Current driving strength 8 milli ampere */
295#define chipcHw_REG_CURRENT_STRENGTH_10mA 0x00000006 /* Current driving strength 10 milli ampere */
296#define chipcHw_REG_CURRENT_STRENGTH_12mA 0x00000007 /* Current driving strength 12 milli ampere */
297#define chipcHw_REG_CURRENT_MASK 0x00000007 /* Mask */
298 /* Pins beyond 42 are defined by skipping 8 bits */
299#define chipcHw_REG_CURRENT(pin) (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3)))
300#define chipcHw_REG_CURRENT_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2))
301
302#define chipcHw_REG_PULL_NONE 0x00000000 /* No pull up register */
303#define chipcHw_REG_PULL_UP 0x00000001 /* Pull up register enable */
304#define chipcHw_REG_PULL_DOWN 0x00000002 /* Pull down register enable */
305#define chipcHw_REG_PULLUP_MASK 0x00000003 /* Mask */
306 /* Pins beyond 42 are defined by skipping 4 bits */
307#define chipcHw_REG_PULLUP(pin) (((pin) > 42) ? (&pChipcHw->GpioPull_0_15 + (((pin) + 2) >> 4)) : (&pChipcHw->GpioPull_0_15 + ((pin) >> 4)))
308#define chipcHw_REG_PULLUP_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x0000000F) << 1) : (((pin) & 0x0000000F) << 1))
309
310#define chipcHw_REG_INPUTTYPE_CMOS 0x00000000 /* Normal CMOS logic */
311#define chipcHw_REG_INPUTTYPE_ST 0x00000001 /* High speed Schmitt Trigger */
312#define chipcHw_REG_INPUTTYPE_MASK 0x00000001 /* Mask */
313 /* Pins beyond 42 are defined by skipping 2 bits */
314#define chipcHw_REG_INPUTTYPE(pin) (((pin) > 42) ? (&pChipcHw->GpioInput_0_31 + (((pin) + 2) >> 5)) : (&pChipcHw->GpioInput_0_31 + ((pin) >> 5)))
315#define chipcHw_REG_INPUTTYPE_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x0000001F)) : (((pin) & 0x0000001F)))
316
317/* Device connected to the bus clock */
318#define chipcHw_REG_BUS_CLOCK_ARM 0x00000001 /* Bus interface clock for ARM */
319#define chipcHw_REG_BUS_CLOCK_VDEC 0x00000002 /* Bus interface clock for VDEC */
320#define chipcHw_REG_BUS_CLOCK_ARAM 0x00000004 /* Bus interface clock for ARAM */
321#define chipcHw_REG_BUS_CLOCK_HPM 0x00000008 /* Bus interface clock for HPM */
322#define chipcHw_REG_BUS_CLOCK_DDRC 0x00000010 /* Bus interface clock for DDRC */
323#define chipcHw_REG_BUS_CLOCK_DMAC0 0x00000020 /* Bus interface clock for DMAC0 */
324#define chipcHw_REG_BUS_CLOCK_DMAC1 0x00000040 /* Bus interface clock for DMAC1 */
325#define chipcHw_REG_BUS_CLOCK_NVI 0x00000080 /* Bus interface clock for NVI */
326#define chipcHw_REG_BUS_CLOCK_ESW 0x00000100 /* Bus interface clock for ESW */
327#define chipcHw_REG_BUS_CLOCK_GE 0x00000200 /* Bus interface clock for GE */
328#define chipcHw_REG_BUS_CLOCK_I2CH 0x00000400 /* Bus interface clock for I2CH */
329#define chipcHw_REG_BUS_CLOCK_I2S0 0x00000800 /* Bus interface clock for I2S0 */
330#define chipcHw_REG_BUS_CLOCK_I2S1 0x00001000 /* Bus interface clock for I2S1 */
331#define chipcHw_REG_BUS_CLOCK_VRAM 0x00002000 /* Bus interface clock for VRAM */
332#define chipcHw_REG_BUS_CLOCK_CLCD 0x00004000 /* Bus interface clock for CLCD */
333#define chipcHw_REG_BUS_CLOCK_LDK 0x00008000 /* Bus interface clock for LDK */
334#define chipcHw_REG_BUS_CLOCK_LED 0x00010000 /* Bus interface clock for LED */
335#define chipcHw_REG_BUS_CLOCK_OTP 0x00020000 /* Bus interface clock for OTP */
336#define chipcHw_REG_BUS_CLOCK_PIF 0x00040000 /* Bus interface clock for PIF */
337#define chipcHw_REG_BUS_CLOCK_SPU 0x00080000 /* Bus interface clock for SPU */
338#define chipcHw_REG_BUS_CLOCK_SDIO0 0x00100000 /* Bus interface clock for SDIO0 */
339#define chipcHw_REG_BUS_CLOCK_SDIO1 0x00200000 /* Bus interface clock for SDIO1 */
340#define chipcHw_REG_BUS_CLOCK_SPIH 0x00400000 /* Bus interface clock for SPIH */
341#define chipcHw_REG_BUS_CLOCK_SPIS 0x00800000 /* Bus interface clock for SPIS */
342#define chipcHw_REG_BUS_CLOCK_UART0 0x01000000 /* Bus interface clock for UART0 */
343#define chipcHw_REG_BUS_CLOCK_UART1 0x02000000 /* Bus interface clock for UART1 */
344#define chipcHw_REG_BUS_CLOCK_BBL 0x04000000 /* Bus interface clock for BBL */
345#define chipcHw_REG_BUS_CLOCK_I2CS 0x08000000 /* Bus interface clock for I2CS */
346#define chipcHw_REG_BUS_CLOCK_USBH 0x10000000 /* Bus interface clock for USB Host */
347#define chipcHw_REG_BUS_CLOCK_USBD 0x20000000 /* Bus interface clock for USB Device */
348#define chipcHw_REG_BUS_CLOCK_BROM 0x40000000 /* Bus interface clock for Boot ROM */
349#define chipcHw_REG_BUS_CLOCK_TSC 0x80000000 /* Bus interface clock for Touch screen */
350
351/* Software resets defines */
352#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD 0x0000000080000000ULL /* Reset Global VPM and hold */
353#define chipcHw_REG_SOFT_RESET_VPM_HOLD 0x0000000040000000ULL /* Reset VPM and hold */
354#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL 0x0000000020000000ULL /* Reset Global VPM */
355#define chipcHw_REG_SOFT_RESET_VPM 0x0000000010000000ULL /* Reset VPM */
356#define chipcHw_REG_SOFT_RESET_KEYPAD 0x0000000008000000ULL /* Reset Key pad */
357#define chipcHw_REG_SOFT_RESET_LED 0x0000000004000000ULL /* Reset LED */
358#define chipcHw_REG_SOFT_RESET_SPU 0x0000000002000000ULL /* Reset SPU */
359#define chipcHw_REG_SOFT_RESET_RNG 0x0000000001000000ULL /* Reset RNG */
360#define chipcHw_REG_SOFT_RESET_PKA 0x0000000000800000ULL /* Reset PKA */
361#define chipcHw_REG_SOFT_RESET_LCD 0x0000000000400000ULL /* Reset LCD */
362#define chipcHw_REG_SOFT_RESET_PIF 0x0000000000200000ULL /* Reset PIF */
363#define chipcHw_REG_SOFT_RESET_I2CS 0x0000000000100000ULL /* Reset I2C Slave */
364#define chipcHw_REG_SOFT_RESET_I2CH 0x0000000000080000ULL /* Reset I2C Host */
365#define chipcHw_REG_SOFT_RESET_SDIO1 0x0000000000040000ULL /* Reset SDIO 1 */
366#define chipcHw_REG_SOFT_RESET_SDIO0 0x0000000000020000ULL /* Reset SDIO 0 */
367#define chipcHw_REG_SOFT_RESET_BBL 0x0000000000010000ULL /* Reset BBL */
368#define chipcHw_REG_SOFT_RESET_I2S1 0x0000000000008000ULL /* Reset I2S1 */
369#define chipcHw_REG_SOFT_RESET_I2S0 0x0000000000004000ULL /* Reset I2S0 */
370#define chipcHw_REG_SOFT_RESET_SPIS 0x0000000000002000ULL /* Reset SPI Slave */
371#define chipcHw_REG_SOFT_RESET_SPIH 0x0000000000001000ULL /* Reset SPI Host */
372#define chipcHw_REG_SOFT_RESET_GPIO1 0x0000000000000800ULL /* Reset GPIO block 1 */
373#define chipcHw_REG_SOFT_RESET_GPIO0 0x0000000000000400ULL /* Reset GPIO block 0 */
374#define chipcHw_REG_SOFT_RESET_UART1 0x0000000000000200ULL /* Reset UART 1 */
375#define chipcHw_REG_SOFT_RESET_UART0 0x0000000000000100ULL /* Reset UART 0 */
376#define chipcHw_REG_SOFT_RESET_NVI 0x0000000000000080ULL /* Reset NVI */
377#define chipcHw_REG_SOFT_RESET_WDOG 0x0000000000000040ULL /* Reset Watch dog */
378#define chipcHw_REG_SOFT_RESET_TMR 0x0000000000000020ULL /* Reset Timer */
379#define chipcHw_REG_SOFT_RESET_ETM 0x0000000000000010ULL /* Reset ETM */
380#define chipcHw_REG_SOFT_RESET_ARM_HOLD 0x0000000000000008ULL /* Reset ARM and HOLD */
381#define chipcHw_REG_SOFT_RESET_ARM 0x0000000000000004ULL /* Reset ARM */
382#define chipcHw_REG_SOFT_RESET_CHIP_WARM 0x0000000000000002ULL /* Chip warm reset */
383#define chipcHw_REG_SOFT_RESET_CHIP_SOFT 0x0000000000000001ULL /* Chip soft reset */
384#define chipcHw_REG_SOFT_RESET_VDEC 0x0000100000000000ULL /* Video decoder */
385#define chipcHw_REG_SOFT_RESET_GE 0x0000080000000000ULL /* Graphics engine */
386#define chipcHw_REG_SOFT_RESET_OTP 0x0000040000000000ULL /* Reset OTP */
387#define chipcHw_REG_SOFT_RESET_USB2 0x0000020000000000ULL /* Reset USB2 */
388#define chipcHw_REG_SOFT_RESET_USB1 0x0000010000000000ULL /* Reset USB 1 */
389#define chipcHw_REG_SOFT_RESET_USB 0x0000008000000000ULL /* Reset USB 1 and USB2 soft reset */
390#define chipcHw_REG_SOFT_RESET_ESW 0x0000004000000000ULL /* Reset Ethernet switch */
391#define chipcHw_REG_SOFT_RESET_ESWCLK 0x0000002000000000ULL /* Reset Ethernet switch clock */
392#define chipcHw_REG_SOFT_RESET_DDRPHY 0x0000001000000000ULL /* Reset DDR Physical */
393#define chipcHw_REG_SOFT_RESET_DDR 0x0000000800000000ULL /* Reset DDR Controller */
394#define chipcHw_REG_SOFT_RESET_TSC 0x0000000400000000ULL /* Reset Touch screen */
395#define chipcHw_REG_SOFT_RESET_PCM 0x0000000200000000ULL /* Reset PCM device */
396#define chipcHw_REG_SOFT_RESET_APM 0x0000200100000000ULL /* Reset APM device */
397
398#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD 0x8000000000000000ULL /* Unhold Global VPM */
399#define chipcHw_REG_SOFT_RESET_VPM_UNHOLD 0x4000000000000000ULL /* Unhold VPM */
400#define chipcHw_REG_SOFT_RESET_ARM_UNHOLD 0x2000000000000000ULL /* Unhold ARM reset */
401#define chipcHw_REG_SOFT_RESET_UNHOLD_MASK 0xF000000000000000ULL /* Mask to handle unhold request */
402
403/* Audio channel control defines */
404#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_ALL 0x00000001 /* Enable all audio channel */
405#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_A 0x00000002 /* Enable channel A */
406#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_B 0x00000004 /* Enable channel B */
407#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_C 0x00000008 /* Enable channel C */
408#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_NTP_CLOCK 0x00000010 /* Enable NTP clock */
409#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM0_CLOCK 0x00000020 /* Enable PCM0 clock */
410#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM1_CLOCK 0x00000040 /* Enable PCM1 clock */
411#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_APM_CLOCK 0x00000080 /* Enable APM clock */
412
413/* Misc. chip control defines */
414#define chipcHw_REG_MISC_CTRL_GE_SEL 0x00040000 /* Select GE2/GE3 */
415#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_ONCHIP 0x00000000 /* Use on chip clock for I2S1 */
416#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_GPIO 0x00020000 /* Use external clock via GPIO pin 26 for I2S1 */
417#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_ONCHIP 0x00000000 /* Use on chip clock for I2S0 */
418#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_GPIO 0x00010000 /* Use external clock via GPIO pin 45 for I2S0 */
419#define chipcHw_REG_MISC_CTRL_ARM_CP15_DISABLE 0x00008000 /* Disable ARM CP15 bit */
420#define chipcHw_REG_MISC_CTRL_RTC_DISABLE 0x00000008 /* Disable RTC registers */
421#define chipcHw_REG_MISC_CTRL_BBRAM_DISABLE 0x00000004 /* Disable Battery Backed RAM */
422#define chipcHw_REG_MISC_CTRL_USB_MODE_HOST 0x00000002 /* Set USB as host */
423#define chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE 0xFFFFFFFD /* Set USB as device */
424#define chipcHw_REG_MISC_CTRL_USB_POWERON 0xFFFFFFFE /* Power up USB */
425#define chipcHw_REG_MISC_CTRL_USB_POWEROFF 0x00000001 /* Power down USB */
426
427/* OTP configuration defines */
428#define chipcHw_REG_OTP_SECURITY_OFF 0x0000020000000000ULL /* Security support is OFF */
429#define chipcHw_REG_OTP_SPU_SLOW 0x0000010000000000ULL /* Limited SPU throughput */
430#define chipcHw_REG_OTP_LCD_SPEED 0x0000000600000000ULL /* Set VPM speed one */
431#define chipcHw_REG_OTP_VPM_SPEED_1 0x0000000100000000ULL /* Set VPM speed one */
432#define chipcHw_REG_OTP_VPM_SPEED_0 0x0000000080000000ULL /* Set VPM speed zero */
433#define chipcHw_REG_OTP_AXI_SPEED 0x0000000060000000ULL /* Set maximum AXI bus speed */
434#define chipcHw_REG_OTP_APM_DISABLE 0x000000001F000000ULL /* Disable APM */
435#define chipcHw_REG_OTP_PIF_DISABLE 0x0000000000200000ULL /* Disable PIF */
436#define chipcHw_REG_OTP_VDEC_DISABLE 0x0000000000100000ULL /* Disable Video decoder */
437#define chipcHw_REG_OTP_BBL_DISABLE 0x0000000000080000ULL /* Disable RTC and BBRAM */
438#define chipcHw_REG_OTP_LED_DISABLE 0x0000000000040000ULL /* Disable LED */
439#define chipcHw_REG_OTP_GE_DISABLE 0x0000000000020000ULL /* Disable Graphics Engine */
440#define chipcHw_REG_OTP_LCD_DISABLE 0x0000000000010000ULL /* Disable LCD */
441#define chipcHw_REG_OTP_KEYPAD_DISABLE 0x0000000000008000ULL /* Disable keypad */
442#define chipcHw_REG_OTP_UART_DISABLE 0x0000000000004000ULL /* Disable UART */
443#define chipcHw_REG_OTP_SDIOH_DISABLE 0x0000000000003000ULL /* Disable SDIO host */
444#define chipcHw_REG_OTP_HSS_DISABLE 0x0000000000000C00ULL /* Disable HSS */
445#define chipcHw_REG_OTP_TSC_DISABLE 0x0000000000000200ULL /* Disable touch screen */
446#define chipcHw_REG_OTP_USB_DISABLE 0x0000000000000180ULL /* Disable USB */
447#define chipcHw_REG_OTP_SGMII_DISABLE 0x0000000000000060ULL /* Disable SGMII */
448#define chipcHw_REG_OTP_ETH_DISABLE 0x0000000000000018ULL /* Disable gigabit ethernet */
449#define chipcHw_REG_OTP_ETH_PHY_DISABLE 0x0000000000000006ULL /* Disable ethernet PHY */
450#define chipcHw_REG_OTP_VPM_DISABLE 0x0000000000000001ULL /* Disable VPM */
451
452/* Sticky bit defines */
453#define chipcHw_REG_STICKY_BOOT_DONE 0x00000001 /* Boot done */
454#define chipcHw_REG_STICKY_SOFT_RESET 0x00000002 /* ARM soft reset */
455#define chipcHw_REG_STICKY_GENERAL_1 0x00000004 /* General purpose bit 1 */
456#define chipcHw_REG_STICKY_GENERAL_2 0x00000008 /* General purpose bit 2 */
457#define chipcHw_REG_STICKY_GENERAL_3 0x00000010 /* General purpose bit 3 */
458#define chipcHw_REG_STICKY_GENERAL_4 0x00000020 /* General purpose bit 4 */
459#define chipcHw_REG_STICKY_GENERAL_5 0x00000040 /* General purpose bit 5 */
460#define chipcHw_REG_STICKY_POR_BROM 0x00000080 /* Special sticky bit for security - set in BROM to avoid other modes being entered */
461#define chipcHw_REG_STICKY_ARM_RESET 0x00000100 /* ARM reset */
462#define chipcHw_REG_STICKY_CHIP_SOFT_RESET 0x00000200 /* Chip soft reset */
463#define chipcHw_REG_STICKY_CHIP_WARM_RESET 0x00000400 /* Chip warm reset */
464#define chipcHw_REG_STICKY_WDOG_RESET 0x00000800 /* Watchdog reset */
465#define chipcHw_REG_STICKY_OTP_RESET 0x00001000 /* OTP reset */
466
467 /* HW phase alignment defines *//* Spare1 register definitions */
468#define chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE 0x80000000 /* Enable DDR phase align panic interrupt */
469#define chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE 0x40000000 /* Enable VPM phase align panic interrupt */
470#define chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE 0x00000002 /* Enable access to VPM using system BUS */
471#define chipcHw_REG_SPARE1_DDR_BUS_ACCESS_ENABLE 0x00000001 /* Enable access to DDR using system BUS */
472 /* DDRPhaseCtrl1 register definitions */
473#define chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE 0x80000000 /* Enable DDR SW phase alignment */
474#define chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE 0x40000000 /* Enable DDR HW phase alignment */
475#define chipcHw_REG_DDR_PHASE_VALUE_GE_MASK 0x0000007F /* DDR lower threshold for phase alignment */
476#define chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT 23
477#define chipcHw_REG_DDR_PHASE_VALUE_LE_MASK 0x0000007F /* DDR upper threshold for phase alignment */
478#define chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT 16
479#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_MASK 0x0000FFFF /* BUS Cycle to wait to run next DDR phase alignment */
480#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_SHIFT 0
481 /* VPMPhaseCtrl1 register definitions */
482#define chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE 0x80000000 /* Enable VPM SW phase alignment */
483#define chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE 0x40000000 /* Enable VPM HW phase alignment */
484#define chipcHw_REG_VPM_PHASE_VALUE_GE_MASK 0x0000007F /* VPM lower threshold for phase alignment */
485#define chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT 23
486#define chipcHw_REG_VPM_PHASE_VALUE_LE_MASK 0x0000007F /* VPM upper threshold for phase alignment */
487#define chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT 16
488#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_MASK 0x0000FFFF /* BUS Cycle to wait to complete the VPM phase alignment */
489#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_SHIFT 0
490 /* PhaseAlignStatus register definitions */
491#define chipcHw_REG_DDR_TIMEOUT_INTR_STATUS 0x80000000 /* DDR time out interrupt status */
492#define chipcHw_REG_DDR_PHASE_STATUS_MASK 0x0000007F /* DDR phase status value */
493#define chipcHw_REG_DDR_PHASE_STATUS_SHIFT 24
494#define chipcHw_REG_DDR_PHASE_ALIGNED 0x00800000 /* DDR Phase aligned status */
495#define chipcHw_REG_DDR_LOAD 0x00400000 /* Load DDR phase status */
496#define chipcHw_REG_DDR_PHASE_CTRL_MASK 0x0000003F /* DDR phase control value */
497#define chipcHw_REG_DDR_PHASE_CTRL_SHIFT 16
498#define chipcHw_REG_VPM_TIMEOUT_INTR_STATUS 0x80000000 /* VPM time out interrupt status */
499#define chipcHw_REG_VPM_PHASE_STATUS_MASK 0x0000007F /* VPM phase status value */
500#define chipcHw_REG_VPM_PHASE_STATUS_SHIFT 8
501#define chipcHw_REG_VPM_PHASE_ALIGNED 0x00000080 /* VPM Phase aligned status */
502#define chipcHw_REG_VPM_LOAD 0x00000040 /* Load VPM phase status */
503#define chipcHw_REG_VPM_PHASE_CTRL_MASK 0x0000003F /* VPM phase control value */
504#define chipcHw_REG_VPM_PHASE_CTRL_SHIFT 0
505 /* DDRPhaseCtrl2 register definitions */
506#define chipcHw_REG_DDR_INTR_SERVICED 0x02000000 /* Acknowledge that interrupt was serviced */
507#define chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE 0x01000000 /* Enable time out interrupt */
508#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_MASK 0x0000000F /* Wait before toggling load_ch */
509#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_SHIFT 20
510#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_MASK 0x0000000F /* Total wait to settle ph_ctrl and load_ch */
511#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_SHIFT 16
512#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK 0x0000FFFF /* Time out value for DDR HW phase alignment */
513#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT 0
514 /* VPMPhaseCtrl2 register definitions */
515#define chipcHw_REG_VPM_INTR_SELECT_MASK 0x00000003 /* Interrupt select */
516#define chipcHw_REG_VPM_INTR_SELECT_SHIFT 26
517#define chipcHw_REG_VPM_INTR_DISABLE 0x00000000
518#define chipcHw_REG_VPM_INTR_FAST (0x1 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)
519#define chipcHw_REG_VPM_INTR_MEDIUM (0x2 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)
520#define chipcHw_REG_VPM_INTR_SLOW (0x3 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)
521#define chipcHw_REG_VPM_INTR_SERVICED 0x02000000 /* Acknowledge that interrupt was serviced */
522#define chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE 0x01000000 /* Enable time out interrupt */
523#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_MASK 0x0000000F /* Wait before toggling load_ch */
524#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_SHIFT 20
525#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_MASK 0x0000000F /* Total wait cycle to settle ph_ctrl and load_ch */
526#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_SHIFT 16
527#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK 0x0000FFFF /* Time out value for VPM HW phase alignment */
528#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT 0
529
530#endif /* CHIPCHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
deleted file mode 100644
index 39da2c1fdafb..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
+++ /dev/null
@@ -1,872 +0,0 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file ddrcReg.h
18*
19* @brief Register definitions for BCMRING DDR2 Controller and PHY
20*
21*/
22/****************************************************************************/
23
24#ifndef DDRC_REG_H
25#define DDRC_REG_H
26
27#ifdef __cplusplus
28extern "C" {
29#endif
30
31/* ---- Include Files ---------------------------------------------------- */
32
33#include <mach/csp/reg.h>
34#include <linux/types.h>
35
36#include <mach/csp/mm_io.h>
37
38/* ---- Public Constants and Types --------------------------------------- */
39
40/*********************************************************************/
41/* DDR2 Controller (ARM PL341) register definitions */
42/*********************************************************************/
43
44/* -------------------------------------------------------------------- */
45/* -------------------------------------------------------------------- */
46/* ARM PL341 DDR2 configuration registers, offset 0x000 */
47/* -------------------------------------------------------------------- */
48/* -------------------------------------------------------------------- */
49
50 typedef struct {
51 uint32_t memcStatus;
52 uint32_t memcCmd;
53 uint32_t directCmd;
54 uint32_t memoryCfg;
55 uint32_t refreshPrd;
56 uint32_t casLatency;
57 uint32_t writeLatency;
58 uint32_t tMrd;
59 uint32_t tRas;
60 uint32_t tRc;
61 uint32_t tRcd;
62 uint32_t tRfc;
63 uint32_t tRp;
64 uint32_t tRrd;
65 uint32_t tWr;
66 uint32_t tWtr;
67 uint32_t tXp;
68 uint32_t tXsr;
69 uint32_t tEsr;
70 uint32_t memoryCfg2;
71 uint32_t memoryCfg3;
72 uint32_t tFaw;
73 } ddrcReg_CTLR_MEMC_REG_t;
74
75#define ddrcReg_CTLR_MEMC_REG_OFFSET 0x0000
76#define ddrcReg_CTLR_MEMC_REGP ((volatile ddrcReg_CTLR_MEMC_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_MEMC_REG_OFFSET))
77
78/* ----------------------------------------------------- */
79
80#define ddrcReg_CTLR_MEMC_STATUS_BANKS_MASK (0x3 << 12)
81#define ddrcReg_CTLR_MEMC_STATUS_BANKS_4 (0x0 << 12)
82#define ddrcReg_CTLR_MEMC_STATUS_BANKS_8 (0x3 << 12)
83
84#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_MASK (0x3 << 10)
85#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_0 (0x0 << 10)
86#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_1 (0x1 << 10)
87#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_2 (0x2 << 10)
88#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_4 (0x3 << 10)
89
90#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_MASK (0x3 << 7)
91#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_1 (0x0 << 7)
92#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_2 (0x1 << 7)
93#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_3 (0x2 << 7)
94#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_4 (0x3 << 7)
95
96#define ddrcReg_CTLR_MEMC_STATUS_TYPE_MASK (0x7 << 4)
97#define ddrcReg_CTLR_MEMC_STATUS_TYPE_DDR2 (0x5 << 4)
98
99#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_MASK (0x3 << 2)
100#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_16 (0x0 << 2)
101#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_32 (0x1 << 2)
102#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_64 (0x2 << 2)
103#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_128 (0x3 << 2)
104
105#define ddrcReg_CTLR_MEMC_STATUS_STATE_MASK (0x3 << 0)
106#define ddrcReg_CTLR_MEMC_STATUS_STATE_CONFIG (0x0 << 0)
107#define ddrcReg_CTLR_MEMC_STATUS_STATE_READY (0x1 << 0)
108#define ddrcReg_CTLR_MEMC_STATUS_STATE_PAUSED (0x2 << 0)
109#define ddrcReg_CTLR_MEMC_STATUS_STATE_LOWPWR (0x3 << 0)
110
111/* ----------------------------------------------------- */
112
113#define ddrcReg_CTLR_MEMC_CMD_MASK (0x7 << 0)
114#define ddrcReg_CTLR_MEMC_CMD_GO (0x0 << 0)
115#define ddrcReg_CTLR_MEMC_CMD_SLEEP (0x1 << 0)
116#define ddrcReg_CTLR_MEMC_CMD_WAKEUP (0x2 << 0)
117#define ddrcReg_CTLR_MEMC_CMD_PAUSE (0x3 << 0)
118#define ddrcReg_CTLR_MEMC_CMD_CONFIGURE (0x4 << 0)
119#define ddrcReg_CTLR_MEMC_CMD_ACTIVE_PAUSE (0x7 << 0)
120
121/* ----------------------------------------------------- */
122
123#define ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT 20
124#define ddrcReg_CTLR_DIRECT_CMD_CHIP_MASK (0x3 << ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT)
125
126#define ddrcReg_CTLR_DIRECT_CMD_TYPE_PRECHARGEALL (0x0 << 18)
127#define ddrcReg_CTLR_DIRECT_CMD_TYPE_AUTOREFRESH (0x1 << 18)
128#define ddrcReg_CTLR_DIRECT_CMD_TYPE_MODEREG (0x2 << 18)
129#define ddrcReg_CTLR_DIRECT_CMD_TYPE_NOP (0x3 << 18)
130
131#define ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT 16
132#define ddrcReg_CTLR_DIRECT_CMD_BANK_MASK (0x3 << ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT)
133
134#define ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT 0
135#define ddrcReg_CTLR_DIRECT_CMD_ADDR_MASK (0x1ffff << ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT)
136
137/* ----------------------------------------------------- */
138
139#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_MASK (0x3 << 21)
140#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_1 (0x0 << 21)
141#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_2 (0x1 << 21)
142#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_3 (0x2 << 21)
143#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_4 (0x3 << 21)
144
145#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_MASK (0x7 << 18)
146#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_3_0 (0x0 << 18)
147#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_4_1 (0x1 << 18)
148#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_5_2 (0x2 << 18)
149#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_6_3 (0x3 << 18)
150#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_7_4 (0x4 << 18)
151#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_8_5 (0x5 << 18)
152#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_9_6 (0x6 << 18)
153#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_10_7 (0x7 << 18)
154
155#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_MASK (0x7 << 15)
156#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_4 (0x2 << 15)
157#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_8 (0x3 << 15) /* @note Not supported in PL341 */
158
159#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_ENABLE (0x1 << 13)
160
161#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT 7
162#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_MASK (0x3f << ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT)
163
164#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_MASK (0x7 << 3)
165#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_11 (0x0 << 3)
166#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_12 (0x1 << 3)
167#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_13 (0x2 << 3)
168#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_14 (0x3 << 3)
169#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_15 (0x4 << 3)
170#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_16 (0x5 << 3)
171
172#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_MASK (0x7 << 0)
173#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_9 (0x1 << 0)
174#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_10 (0x2 << 0)
175#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_11 (0x3 << 0)
176
177/* ----------------------------------------------------- */
178
179#define ddrcReg_CTLR_REFRESH_PRD_SHIFT 0
180#define ddrcReg_CTLR_REFRESH_PRD_MASK (0x7fff << ddrcReg_CTLR_REFRESH_PRD_SHIFT)
181
182/* ----------------------------------------------------- */
183
184#define ddrcReg_CTLR_CAS_LATENCY_SHIFT 1
185#define ddrcReg_CTLR_CAS_LATENCY_MASK (0x7 << ddrcReg_CTLR_CAS_LATENCY_SHIFT)
186
187/* ----------------------------------------------------- */
188
189#define ddrcReg_CTLR_WRITE_LATENCY_SHIFT 0
190#define ddrcReg_CTLR_WRITE_LATENCY_MASK (0x7 << ddrcReg_CTLR_WRITE_LATENCY_SHIFT)
191
192/* ----------------------------------------------------- */
193
194#define ddrcReg_CTLR_T_MRD_SHIFT 0
195#define ddrcReg_CTLR_T_MRD_MASK (0x7f << ddrcReg_CTLR_T_MRD_SHIFT)
196
197/* ----------------------------------------------------- */
198
199#define ddrcReg_CTLR_T_RAS_SHIFT 0
200#define ddrcReg_CTLR_T_RAS_MASK (0x1f << ddrcReg_CTLR_T_RAS_SHIFT)
201
202/* ----------------------------------------------------- */
203
204#define ddrcReg_CTLR_T_RC_SHIFT 0
205#define ddrcReg_CTLR_T_RC_MASK (0x1f << ddrcReg_CTLR_T_RC_SHIFT)
206
207/* ----------------------------------------------------- */
208
209#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT 8
210#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_MASK (0x7 << ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT)
211
212#define ddrcReg_CTLR_T_RCD_SHIFT 0
213#define ddrcReg_CTLR_T_RCD_MASK (0x7 << ddrcReg_CTLR_T_RCD_SHIFT)
214
215/* ----------------------------------------------------- */
216
217#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT 8
218#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_MASK (0x7f << ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT)
219
220#define ddrcReg_CTLR_T_RFC_SHIFT 0
221#define ddrcReg_CTLR_T_RFC_MASK (0x7f << ddrcReg_CTLR_T_RFC_SHIFT)
222
223/* ----------------------------------------------------- */
224
225#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT 8
226#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_MASK (0x7 << ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT)
227
228#define ddrcReg_CTLR_T_RP_SHIFT 0
229#define ddrcReg_CTLR_T_RP_MASK (0xf << ddrcReg_CTLR_T_RP_SHIFT)
230
231/* ----------------------------------------------------- */
232
233#define ddrcReg_CTLR_T_RRD_SHIFT 0
234#define ddrcReg_CTLR_T_RRD_MASK (0xf << ddrcReg_CTLR_T_RRD_SHIFT)
235
236/* ----------------------------------------------------- */
237
238#define ddrcReg_CTLR_T_WR_SHIFT 0
239#define ddrcReg_CTLR_T_WR_MASK (0x7 << ddrcReg_CTLR_T_WR_SHIFT)
240
241/* ----------------------------------------------------- */
242
243#define ddrcReg_CTLR_T_WTR_SHIFT 0
244#define ddrcReg_CTLR_T_WTR_MASK (0x7 << ddrcReg_CTLR_T_WTR_SHIFT)
245
246/* ----------------------------------------------------- */
247
248#define ddrcReg_CTLR_T_XP_SHIFT 0
249#define ddrcReg_CTLR_T_XP_MASK (0xff << ddrcReg_CTLR_T_XP_SHIFT)
250
251/* ----------------------------------------------------- */
252
253#define ddrcReg_CTLR_T_XSR_SHIFT 0
254#define ddrcReg_CTLR_T_XSR_MASK (0xff << ddrcReg_CTLR_T_XSR_SHIFT)
255
256/* ----------------------------------------------------- */
257
258#define ddrcReg_CTLR_T_ESR_SHIFT 0
259#define ddrcReg_CTLR_T_ESR_MASK (0xff << ddrcReg_CTLR_T_ESR_SHIFT)
260
261/* ----------------------------------------------------- */
262
263#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_MASK (0x3 << 6)
264#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_16BITS (0 << 6)
265#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_32BITS (1 << 6)
266#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_64BITS (2 << 6)
267
268#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_MASK (0x3 << 4)
269#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_2 (0 << 4)
270#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_3 (3 << 4)
271
272#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_LOW (0 << 3)
273#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_HIGH (1 << 3)
274
275#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_LOW (0 << 2)
276#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_HIGH (1 << 2)
277
278#define ddrcReg_CTLR_MEMORY_CFG2_CLK_MASK (0x3 << 0)
279#define ddrcReg_CTLR_MEMORY_CFG2_CLK_ASYNC (0 << 0)
280#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_LE_M (1 << 0)
281#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_GT_M (3 << 0)
282
283/* ----------------------------------------------------- */
284
285#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT 0
286#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_MASK (0x7 << ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT)
287
288/* ----------------------------------------------------- */
289
290#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT 8
291#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_MASK (0x1f << ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT)
292
293#define ddrcReg_CTLR_T_FAW_PERIOD_SHIFT 0
294#define ddrcReg_CTLR_T_FAW_PERIOD_MASK (0x1f << ddrcReg_CTLR_T_FAW_PERIOD_SHIFT)
295
296/* -------------------------------------------------------------------- */
297/* -------------------------------------------------------------------- */
298/* ARM PL341 AXI ID QOS configuration registers, offset 0x100 */
299/* -------------------------------------------------------------------- */
300/* -------------------------------------------------------------------- */
301
302#define ddrcReg_CTLR_QOS_CNT 16
303#define ddrcReg_CTLR_QOS_MAX (ddrcReg_CTLR_QOS_CNT - 1)
304
305 typedef struct {
306 uint32_t cfg[ddrcReg_CTLR_QOS_CNT];
307 } ddrcReg_CTLR_QOS_REG_t;
308
309#define ddrcReg_CTLR_QOS_REG_OFFSET 0x100
310#define ddrcReg_CTLR_QOS_REGP ((volatile ddrcReg_CTLR_QOS_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_QOS_REG_OFFSET))
311
312/* ----------------------------------------------------- */
313
314#define ddrcReg_CTLR_QOS_CFG_MAX_SHIFT 2
315#define ddrcReg_CTLR_QOS_CFG_MAX_MASK (0xff << ddrcReg_CTLR_QOS_CFG_MAX_SHIFT)
316
317#define ddrcReg_CTLR_QOS_CFG_MIN_SHIFT 1
318#define ddrcReg_CTLR_QOS_CFG_MIN_MASK (1 << ddrcReg_CTLR_QOS_CFG_MIN_SHIFT)
319
320#define ddrcReg_CTLR_QOS_CFG_ENABLE (1 << 0)
321
322/* -------------------------------------------------------------------- */
323/* -------------------------------------------------------------------- */
324/* ARM PL341 Memory chip configuration registers, offset 0x200 */
325/* -------------------------------------------------------------------- */
326/* -------------------------------------------------------------------- */
327
328#define ddrcReg_CTLR_CHIP_CNT 4
329#define ddrcReg_CTLR_CHIP_MAX (ddrcReg_CTLR_CHIP_CNT - 1)
330
331 typedef struct {
332 uint32_t cfg[ddrcReg_CTLR_CHIP_CNT];
333 } ddrcReg_CTLR_CHIP_REG_t;
334
335#define ddrcReg_CTLR_CHIP_REG_OFFSET 0x200
336#define ddrcReg_CTLR_CHIP_REGP ((volatile ddrcReg_CTLR_CHIP_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_CHIP_REG_OFFSET))
337
338/* ----------------------------------------------------- */
339
340#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_MASK (1 << 16)
341#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_ROW_BANK_COL (0 << 16)
342#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_BANK_ROW_COL (1 << 16)
343
344#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT 8
345#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_MASK (0xff << ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT)
346
347#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT 0
348#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_MASK (0xff << ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT)
349
350/* -------------------------------------------------------------------- */
351/* -------------------------------------------------------------------- */
352/* ARM PL341 User configuration registers, offset 0x300 */
353/* -------------------------------------------------------------------- */
354/* -------------------------------------------------------------------- */
355
356#define ddrcReg_CTLR_USER_OUTPUT_CNT 2
357
358 typedef struct {
359 uint32_t input;
360 uint32_t output[ddrcReg_CTLR_USER_OUTPUT_CNT];
361 uint32_t feature;
362 } ddrcReg_CTLR_USER_REG_t;
363
364#define ddrcReg_CTLR_USER_REG_OFFSET 0x300
365#define ddrcReg_CTLR_USER_REGP ((volatile ddrcReg_CTLR_USER_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_USER_REG_OFFSET))
366
367/* ----------------------------------------------------- */
368
369#define ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT 0
370#define ddrcReg_CTLR_USER_INPUT_STATUS_MASK (0xff << ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT)
371
372/* ----------------------------------------------------- */
373
374#define ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT 0
375#define ddrcReg_CTLR_USER_OUTPUT_CFG_MASK (0xff << ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT)
376
377#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT 1
378#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_MASK (1 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
379#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_BP134 (0 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
380#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301 (1 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
381#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_REGISTERED ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301
382
383/* ----------------------------------------------------- */
384
385#define ddrcReg_CTLR_FEATURE_WRITE_BLOCK_DISABLE (1 << 2)
386#define ddrcReg_CTLR_FEATURE_EARLY_BURST_RSP_DISABLE (1 << 0)
387
388/*********************************************************************/
389/* Broadcom DDR23 PHY register definitions */
390/*********************************************************************/
391
392/* -------------------------------------------------------------------- */
393/* -------------------------------------------------------------------- */
394/* Broadcom DDR23 PHY Address and Control register definitions */
395/* -------------------------------------------------------------------- */
396/* -------------------------------------------------------------------- */
397
398 typedef struct {
399 uint32_t revision;
400 uint32_t pmCtl;
401 REG32_RSVD(0x0008, 0x0010);
402 uint32_t pllStatus;
403 uint32_t pllCfg;
404 uint32_t pllPreDiv;
405 uint32_t pllDiv;
406 uint32_t pllCtl1;
407 uint32_t pllCtl2;
408 uint32_t ssCtl;
409 uint32_t ssCfg;
410 uint32_t vdlStatic;
411 uint32_t vdlDynamic;
412 uint32_t padIdle;
413 uint32_t pvtComp;
414 uint32_t padDrive;
415 uint32_t clkRgltrCtl;
416 } ddrcReg_PHY_ADDR_CTL_REG_t;
417
418#define ddrcReg_PHY_ADDR_CTL_REG_OFFSET 0x0400
419#define ddrcReg_PHY_ADDR_CTL_REGP ((volatile ddrcReg_PHY_ADDR_CTL_REG_t __iomem*) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET))
420
421/* @todo These SS definitions are duplicates of ones below */
422
423#define ddrcReg_PHY_ADDR_SS_CTRL_ENABLE 0x00000001
424#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_MASK 0xFFFF0000
425#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT 16
426#define ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK 10 /* Higher the value, lower the SS modulation frequency */
427#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_MASK 0x0000FFFF
428#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT 0
429
430/* ----------------------------------------------------- */
431
432#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT 8
433#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_MASK (0xff << ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT)
434
435#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT 0
436#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_MASK (0xff << ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT)
437
438/* ----------------------------------------------------- */
439
440#define ddrcReg_PHY_ADDR_CTL_CLK_PM_CTL_DDR_CLK_DISABLE (1 << 0)
441
442/* ----------------------------------------------------- */
443
444#define ddrcReg_PHY_ADDR_CTL_PLL_STATUS_LOCKED (1 << 0)
445
446/* ----------------------------------------------------- */
447
448#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_DIV2_CLK_RESET (1 << 31)
449
450#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT 17
451#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_MASK (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT)
452
453#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_ENABLE (1 << 16)
454
455#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT 12
456#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT)
457
458#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_VCO_RNG (1 << 7)
459#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CH1_PWRDWN (1 << 6)
460#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BYPASS_ENABLE (1 << 5)
461#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CLKOUT_ENABLE (1 << 4)
462#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_D_RESET (1 << 3)
463#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_A_RESET (1 << 2)
464#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_PWRDWN (1 << 0)
465
466/* ----------------------------------------------------- */
467
468#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_DITHER_MFB (1 << 26)
469#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_PWRDWN (1 << 25)
470
471#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT 20
472#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT)
473
474#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT 8
475#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_MASK (0x1ff << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT)
476
477#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT 4
478#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT)
479
480#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT 0
481#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT)
482
483/* ----------------------------------------------------- */
484
485#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT 24
486#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_MASK (0xff << ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT)
487
488#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT 0
489#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_MASK (0xffffff << ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT)
490
491/* ----------------------------------------------------- */
492
493#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT 30
494#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT)
495
496#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT 27
497#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT)
498
499#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT 24
500#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT)
501
502#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT 22
503#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT)
504
505#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LF_ORDER (0x1 << 21)
506
507#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT 19
508#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT)
509
510#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT 17
511#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT)
512
513#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT 15
514#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT)
515
516#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT 13
517#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT)
518
519#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT 10
520#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT)
521
522#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT 5
523#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_MASK (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT)
524
525#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT 0
526#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_MASK (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT)
527
528/* ----------------------------------------------------- */
529#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT 4
530#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT)
531
532#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT 2
533#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT)
534
535#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_LOWCUR_ENABLE (0x1 << 1)
536#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_BIASIN_ENABLE (0x1 << 0)
537
538/* ----------------------------------------------------- */
539
540#define ddrcReg_PHY_ADDR_CTL_PLL_SS_EN_ENABLE (0x1 << 0)
541
542/* ----------------------------------------------------- */
543
544#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT 16
545#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_MASK (0xffff << ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT)
546
547#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT 0
548#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_MASK (0xffff << ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT)
549
550/* ----------------------------------------------------- */
551
552#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FORCE (1 << 20)
553#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_ENABLE (1 << 16)
554
555#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT 12
556#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT)
557
558#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT 8
559#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT)
560
561#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT 0
562#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_MASK (0x3f << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT)
563
564/* ----------------------------------------------------- */
565
566#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_ENABLE (1 << 16)
567
568#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT 12
569#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT)
570
571#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT 8
572#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT)
573
574#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT 0
575#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_MASK (0x3f << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT)
576
577/* ----------------------------------------------------- */
578
579#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_ENABLE (1u << 31)
580#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_RXENB_DISABLE (1 << 8)
581#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_IDDQ_DISABLE (1 << 6)
582#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_REB_DISABLE (1 << 5)
583#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_OEB_DISABLE (1 << 4)
584#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_IDDQ_DISABLE (1 << 2)
585#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_REB_DISABLE (1 << 1)
586#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_OEB_DISABLE (1 << 0)
587
588/* ----------------------------------------------------- */
589
590#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_DONE (1 << 30)
591#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_DONE (1 << 29)
592#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_DONE (1 << 28)
593#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_AUTO_ENABLE (1 << 27)
594#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_ENABLE (1 << 26)
595#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_OVR_ENABLE (1 << 25)
596#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_OVR_ENABLE (1 << 24)
597
598#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT 20
599#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT)
600
601#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT 16
602#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT)
603
604#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT 12
605#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT)
606
607#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT 8
608#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT)
609
610#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT 4
611#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT)
612
613#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT 0
614#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT)
615
616/* ----------------------------------------------------- */
617
618#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_RT60B (1 << 4)
619#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SEL_SSTL18 (1 << 3)
620#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELTXDRV_CI (1 << 2)
621#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELRXDRV (1 << 1)
622#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SLEW (1 << 0)
623
624/* ----------------------------------------------------- */
625
626#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_HALF (1 << 1)
627#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_OFF (1 << 0)
628
629/* -------------------------------------------------------------------- */
630/* -------------------------------------------------------------------- */
631/* Broadcom DDR23 PHY Byte Lane register definitions */
632/* -------------------------------------------------------------------- */
633/* -------------------------------------------------------------------- */
634
635#define ddrcReg_PHY_BYTE_LANE_CNT 2
636#define ddrcReg_PHY_BYTE_LANE_MAX (ddrcReg_CTLR_BYTE_LANE_CNT - 1)
637
638#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT 8
639
640 typedef struct {
641 uint32_t revision;
642 uint32_t vdlCalibrate;
643 uint32_t vdlStatus;
644 REG32_RSVD(0x000c, 0x0010);
645 uint32_t vdlOverride[ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT];
646 uint32_t readCtl;
647 uint32_t readStatus;
648 uint32_t readClear;
649 uint32_t padIdleCtl;
650 uint32_t padDriveCtl;
651 uint32_t padClkCtl;
652 uint32_t writeCtl;
653 uint32_t clkRegCtl;
654 } ddrcReg_PHY_BYTE_LANE_REG_t;
655
656/* There are 2 instances of the byte Lane registers, one for each byte lane. */
657#define ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET 0x0500
658#define ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET 0x0600
659
660#define ddrcReg_PHY_BYTE_LANE_1_REGP ((volatile ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET))
661#define ddrcReg_PHY_BYTE_LANE_2_REGP ((volatile ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET))
662
663/* ----------------------------------------------------- */
664
665#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT 8
666#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_MASK (0xff << ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT)
667
668#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT 0
669#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_MASK (0xff << ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT)
670
671/* ----------------------------------------------------- */
672
673#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_2CYCLE (1 << 4)
674#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_1CYCLE (0 << 4)
675
676#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_TEST (1 << 3)
677#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ALWAYS (1 << 2)
678#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ONCE (1 << 1)
679#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_FAST (1 << 0)
680
681/* ----------------------------------------------------- */
682
683/* The byte lane VDL status calibTotal[9:0] is comprised of [9:4] step value, [3:2] fine fall */
684/* and [1:0] fine rise. Note that calibTotal[9:0] is located at bit 4 in the VDL status */
685/* register. The fine rise and fall are no longer used, so add some definitions for just */
686/* the step setting to simplify things. */
687
688#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT 8
689#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_MASK (0x3f << ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT)
690
691#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT 4
692#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_MASK (0x3ff << ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT)
693
694#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_LOCK (1 << 1)
695#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_IDLE (1 << 0)
696
697/* ----------------------------------------------------- */
698
699#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_ENABLE (1 << 16)
700
701#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT 12
702#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_MASK (0x3 << ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT)
703
704#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT 8
705#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_MASK (0x3 << ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT)
706
707#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT 0
708#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_MASK (0x3f << ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT)
709
710#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_P 0
711#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_N 1
712#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_EN 2
713#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_WRITE_DQ_DQM 3
714#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_P 4
715#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_N 5
716#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_EN 6
717#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_WRITE_DQ_DQM 7
718
719/* ----------------------------------------------------- */
720
721#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT 8
722#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_MASK (0x3 << ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT)
723
724#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ENABLE (1 << 3)
725#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ADJUST (1 << 2)
726#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ENABLE (1 << 1)
727#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ADJUST (1 << 0)
728
729/* ----------------------------------------------------- */
730
731#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT 0
732#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_MASK (0xf << ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT)
733
734/* ----------------------------------------------------- */
735
736#define ddrcReg_PHY_BYTE_LANE_READ_CLEAR_STATUS (1 << 0)
737
738/* ----------------------------------------------------- */
739
740#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_ENABLE (1u << 31)
741#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_RXENB_DISABLE (1 << 19)
742#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_IDDQ_DISABLE (1 << 18)
743#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_REB_DISABLE (1 << 17)
744#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_OEB_DISABLE (1 << 16)
745#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_RXENB_DISABLE (1 << 15)
746#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_IDDQ_DISABLE (1 << 14)
747#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_REB_DISABLE (1 << 13)
748#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_OEB_DISABLE (1 << 12)
749#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_RXENB_DISABLE (1 << 11)
750#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_IDDQ_DISABLE (1 << 10)
751#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_REB_DISABLE (1 << 9)
752#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_OEB_DISABLE (1 << 8)
753#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_RXENB_DISABLE (1 << 7)
754#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_IDDQ_DISABLE (1 << 6)
755#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_REB_DISABLE (1 << 5)
756#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_OEB_DISABLE (1 << 4)
757#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_RXENB_DISABLE (1 << 3)
758#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_IDDQ_DISABLE (1 << 2)
759#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_REB_DISABLE (1 << 1)
760#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_OEB_DISABLE (1 << 0)
761
762/* ----------------------------------------------------- */
763
764#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B_DDR_READ_ENB (1 << 5)
765#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B (1 << 4)
766#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SEL_SSTL18 (1 << 3)
767#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELTXDRV_CI (1 << 2)
768#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELRXDRV (1 << 1)
769#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SLEW (1 << 0)
770
771/* ----------------------------------------------------- */
772
773#define ddrcReg_PHY_BYTE_LANE_PAD_CLK_CTL_DISABLE (1 << 0)
774
775/* ----------------------------------------------------- */
776
777#define ddrcReg_PHY_BYTE_LANE_WRITE_CTL_PREAMBLE_DDR3 (1 << 0)
778
779/* ----------------------------------------------------- */
780
781#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_HALF (1 << 1)
782#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_OFF (1 << 0)
783
784/*********************************************************************/
785/* ARM PL341 DDRC to Broadcom DDR23 PHY glue register definitions */
786/*********************************************************************/
787
788 typedef struct {
789 uint32_t cfg;
790 uint32_t actMonCnt;
791 uint32_t ctl;
792 uint32_t lbistCtl;
793 uint32_t lbistSeed;
794 uint32_t lbistStatus;
795 uint32_t tieOff;
796 uint32_t actMonClear;
797 uint32_t status;
798 uint32_t user;
799 } ddrcReg_CTLR_PHY_GLUE_REG_t;
800
801#define ddrcReg_CTLR_PHY_GLUE_OFFSET 0x0700
802#define ddrcReg_CTLR_PHY_GLUE_REGP ((volatile ddrcReg_CTLR_PHY_GLUE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_PHY_GLUE_OFFSET))
803
804/* ----------------------------------------------------- */
805
806/* DDR2 / AXI block phase alignment interrupt control */
807#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT 18
808#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_MASK (0x3 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
809#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_OFF (0 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
810#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_TIGHT (1 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
811#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_MEDIUM (2 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
812#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_LOOSE (3 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
813
814#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT 17
815#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
816#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_DIFFERENTIAL (0 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
817#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_CMOS (1 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
818
819#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT 16
820#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
821#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_DEEP (0 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
822#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
823#define ddrcReg_CTLR_PHY_GLUE_CFG_HW_FIXED_ALIGNMENT_DISABLED ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW
824
825#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT 15
826#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
827#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_BP134 (0 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
828#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301 (1 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
829#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_REGISTERED ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301
830
831/* Software control of PHY VDL updates from control register settings. Bit 13 enables the use of Bit 14. */
832/* If software control is not enabled, then updates occur when a refresh command is issued by the hardware */
833/* controller. If 2 chips selects are being used, then software control must be enabled. */
834#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_LOAD (1 << 14)
835#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_ENABLE (1 << 13)
836
837/* Use these to bypass a pipeline stage. By default the ADDR is off but the BYTE LANE in / out are on. */
838#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_ADDR_CTL_IN_BYPASS_PIPELINE_STAGE (1 << 12)
839#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_IN_BYPASS_PIPELINE_STAGE (1 << 11)
840#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_OUT_BYPASS_PIPELINE_STAGE (1 << 10)
841
842/* Chip select count */
843#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT 9
844#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
845#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_1 (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
846#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_2 (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
847
848#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT 8
849#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_ASYNC (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT)
850#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SYNC (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT)
851
852#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT 7
853#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_LOW (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT)
854#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_HIGH (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT)
855
856#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT 6
857#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_LOW (0 << ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT)
858#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_HIGH (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT)
859
860#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT 0
861#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_MASK (0x7 << ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT)
862
863/* ----------------------------------------------------- */
864#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT 0
865#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_MASK (0x7f << ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT)
866
867/* ---- Public Function Prototypes --------------------------------------- */
868
869#ifdef __cplusplus
870} /* end extern "C" */
871#endif
872#endif /* DDRC_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h
deleted file mode 100644
index 9dc90f46a84d..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h
+++ /dev/null
@@ -1,596 +0,0 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file dmacHw.h
18*
19* @brief API definitions for low level DMA controller driver
20*
21*/
22/****************************************************************************/
23#ifndef _DMACHW_H
24#define _DMACHW_H
25
26#include <linux/stddef.h>
27
28#include <linux/types.h>
29#include <mach/csp/dmacHw_reg.h>
30
31/* Define DMA Channel ID using DMA controller number (m) and channel number (c).
32
33 System specific channel ID should be defined as follows
34
35 For example:
36
37 #include <dmacHw.h>
38 ...
39 #define systemHw_LCD_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,5)
40 #define systemHw_SWITCH_RX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,0)
41 #define systemHw_SWITCH_TX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,1)
42 #define systemHw_APM_RX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,3)
43 #define systemHw_APM_TX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,4)
44 ...
45 #define systemHw_SHARED1_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(1,4)
46 #define systemHw_SHARED2_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(1,5)
47 #define systemHw_SHARED3_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,6)
48 ...
49*/
50#define dmacHw_MAKE_CHANNEL_ID(m, c) (m << 8 | c)
51
52typedef enum {
53 dmacHw_CHANNEL_PRIORITY_0 = dmacHw_REG_CFG_LO_CH_PRIORITY_0, /* Channel priority 0. Lowest priority DMA channel */
54 dmacHw_CHANNEL_PRIORITY_1 = dmacHw_REG_CFG_LO_CH_PRIORITY_1, /* Channel priority 1 */
55 dmacHw_CHANNEL_PRIORITY_2 = dmacHw_REG_CFG_LO_CH_PRIORITY_2, /* Channel priority 2 */
56 dmacHw_CHANNEL_PRIORITY_3 = dmacHw_REG_CFG_LO_CH_PRIORITY_3, /* Channel priority 3 */
57 dmacHw_CHANNEL_PRIORITY_4 = dmacHw_REG_CFG_LO_CH_PRIORITY_4, /* Channel priority 4 */
58 dmacHw_CHANNEL_PRIORITY_5 = dmacHw_REG_CFG_LO_CH_PRIORITY_5, /* Channel priority 5 */
59 dmacHw_CHANNEL_PRIORITY_6 = dmacHw_REG_CFG_LO_CH_PRIORITY_6, /* Channel priority 6 */
60 dmacHw_CHANNEL_PRIORITY_7 = dmacHw_REG_CFG_LO_CH_PRIORITY_7 /* Channel priority 7. Highest priority DMA channel */
61} dmacHw_CHANNEL_PRIORITY_e;
62
63/* Source destination master interface */
64typedef enum {
65 dmacHw_SRC_MASTER_INTERFACE_1 = dmacHw_REG_CTL_SMS_1, /* Source DMA master interface 1 */
66 dmacHw_SRC_MASTER_INTERFACE_2 = dmacHw_REG_CTL_SMS_2, /* Source DMA master interface 2 */
67 dmacHw_DST_MASTER_INTERFACE_1 = dmacHw_REG_CTL_DMS_1, /* Destination DMA master interface 1 */
68 dmacHw_DST_MASTER_INTERFACE_2 = dmacHw_REG_CTL_DMS_2 /* Destination DMA master interface 2 */
69} dmacHw_MASTER_INTERFACE_e;
70
71typedef enum {
72 dmacHw_SRC_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_SRC_TR_WIDTH_8, /* Source 8 bit (1 byte) per transaction */
73 dmacHw_SRC_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_SRC_TR_WIDTH_16, /* Source 16 bit (2 byte) per transaction */
74 dmacHw_SRC_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_SRC_TR_WIDTH_32, /* Source 32 bit (4 byte) per transaction */
75 dmacHw_SRC_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_SRC_TR_WIDTH_64, /* Source 64 bit (8 byte) per transaction */
76 dmacHw_DST_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_DST_TR_WIDTH_8, /* Destination 8 bit (1 byte) per transaction */
77 dmacHw_DST_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_DST_TR_WIDTH_16, /* Destination 16 bit (2 byte) per transaction */
78 dmacHw_DST_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_DST_TR_WIDTH_32, /* Destination 32 bit (4 byte) per transaction */
79 dmacHw_DST_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_DST_TR_WIDTH_64 /* Destination 64 bit (8 byte) per transaction */
80} dmacHw_TRANSACTION_WIDTH_e;
81
82typedef enum {
83 dmacHw_SRC_BURST_WIDTH_0 = dmacHw_REG_CTL_SRC_MSIZE_0, /* Source No burst */
84 dmacHw_SRC_BURST_WIDTH_4 = dmacHw_REG_CTL_SRC_MSIZE_4, /* Source 4 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
85 dmacHw_SRC_BURST_WIDTH_8 = dmacHw_REG_CTL_SRC_MSIZE_8, /* Source 8 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
86 dmacHw_SRC_BURST_WIDTH_16 = dmacHw_REG_CTL_SRC_MSIZE_16, /* Source 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
87 dmacHw_DST_BURST_WIDTH_0 = dmacHw_REG_CTL_DST_MSIZE_0, /* Destination No burst */
88 dmacHw_DST_BURST_WIDTH_4 = dmacHw_REG_CTL_DST_MSIZE_4, /* Destination 4 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
89 dmacHw_DST_BURST_WIDTH_8 = dmacHw_REG_CTL_DST_MSIZE_8, /* Destination 8 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
90 dmacHw_DST_BURST_WIDTH_16 = dmacHw_REG_CTL_DST_MSIZE_16 /* Destination 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
91} dmacHw_BURST_WIDTH_e;
92
93typedef enum {
94 dmacHw_TRANSFER_TYPE_MEM_TO_MEM = dmacHw_REG_CTL_TTFC_MM_DMAC, /* Memory to memory transfer */
95 dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM = dmacHw_REG_CTL_TTFC_PM_DMAC, /* Peripheral to memory transfer */
96 dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_MP_DMAC, /* Memory to peripheral transfer */
97 dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_PP_DMAC /* Peripheral to peripheral transfer */
98} dmacHw_TRANSFER_TYPE_e;
99
100typedef enum {
101 dmacHw_TRANSFER_MODE_PERREQUEST, /* Block transfer per DMA request */
102 dmacHw_TRANSFER_MODE_CONTINUOUS, /* Continuous transfer of streaming data */
103 dmacHw_TRANSFER_MODE_PERIODIC /* Periodic transfer of streaming data */
104} dmacHw_TRANSFER_MODE_e;
105
106typedef enum {
107 dmacHw_SRC_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_SINC_INC, /* Increment source address after every transaction */
108 dmacHw_SRC_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_SINC_DEC, /* Decrement source address after every transaction */
109 dmacHw_DST_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_DINC_INC, /* Increment destination address after every transaction */
110 dmacHw_DST_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_DINC_DEC, /* Decrement destination address after every transaction */
111 dmacHw_SRC_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_SINC_NC, /* No change in source address after every transaction */
112 dmacHw_DST_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_DINC_NC /* No change in destination address after every transaction */
113} dmacHw_ADDRESS_UPDATE_MODE_e;
114
115typedef enum {
116 dmacHw_FLOW_CONTROL_DMA, /* DMA working as flow controller (default) */
117 dmacHw_FLOW_CONTROL_PERIPHERAL /* Peripheral working as flow controller */
118} dmacHw_FLOW_CONTROL_e;
119
120typedef enum {
121 dmacHw_TRANSFER_STATUS_BUSY, /* DMA Transfer ongoing */
122 dmacHw_TRANSFER_STATUS_DONE, /* DMA Transfer completed */
123 dmacHw_TRANSFER_STATUS_ERROR /* DMA Transfer error */
124} dmacHw_TRANSFER_STATUS_e;
125
126typedef enum {
127 dmacHw_INTERRUPT_DISABLE, /* Interrupt disable */
128 dmacHw_INTERRUPT_ENABLE /* Interrupt enable */
129} dmacHw_INTERRUPT_e;
130
131typedef enum {
132 dmacHw_INTERRUPT_STATUS_NONE = 0x0, /* No DMA interrupt */
133 dmacHw_INTERRUPT_STATUS_TRANS = 0x1, /* End of DMA transfer interrupt */
134 dmacHw_INTERRUPT_STATUS_BLOCK = 0x2, /* End of block transfer interrupt */
135 dmacHw_INTERRUPT_STATUS_ERROR = 0x4 /* Error interrupt */
136} dmacHw_INTERRUPT_STATUS_e;
137
138typedef enum {
139 dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM, /* Number of DMA channel */
140 dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE, /* Maximum channel burst size */
141 dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM, /* Number of DMA master interface */
142 dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH, /* Channel Data bus width */
143 dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE /* Channel FIFO size */
144} dmacHw_CONTROLLER_ATTRIB_e;
145
146typedef unsigned long dmacHw_HANDLE_t; /* DMA channel handle */
147typedef uint32_t dmacHw_ID_t; /* DMA channel Id. Must be created using
148 "dmacHw_MAKE_CHANNEL_ID" macro
149 */
150/* DMA channel configuration parameters */
151typedef struct {
152 uint32_t srcPeripheralPort; /* Source peripheral port */
153 uint32_t dstPeripheralPort; /* Destination peripheral port */
154 uint32_t srcStatusRegisterAddress; /* Source status register address */
155 uint32_t dstStatusRegisterAddress; /* Destination status register address of type */
156
157 uint32_t srcGatherWidth; /* Number of bytes gathered before successive gather opearation */
158 uint32_t srcGatherJump; /* Number of bytes jumpped before successive gather opearation */
159 uint32_t dstScatterWidth; /* Number of bytes sacattered before successive scatter opearation */
160 uint32_t dstScatterJump; /* Number of bytes jumpped before successive scatter opearation */
161 uint32_t maxDataPerBlock; /* Maximum number of bytes to be transferred per block/descrptor.
162 0 = Maximum possible.
163 */
164
165 dmacHw_ADDRESS_UPDATE_MODE_e srcUpdate; /* Source address update mode */
166 dmacHw_ADDRESS_UPDATE_MODE_e dstUpdate; /* Destination address update mode */
167 dmacHw_TRANSFER_TYPE_e transferType; /* DMA transfer type */
168 dmacHw_TRANSFER_MODE_e transferMode; /* DMA transfer mode */
169 dmacHw_MASTER_INTERFACE_e srcMasterInterface; /* DMA source interface */
170 dmacHw_MASTER_INTERFACE_e dstMasterInterface; /* DMA destination interface */
171 dmacHw_TRANSACTION_WIDTH_e srcMaxTransactionWidth; /* Source transaction width */
172 dmacHw_TRANSACTION_WIDTH_e dstMaxTransactionWidth; /* Destination transaction width */
173 dmacHw_BURST_WIDTH_e srcMaxBurstWidth; /* Source burst width */
174 dmacHw_BURST_WIDTH_e dstMaxBurstWidth; /* Destination burst width */
175 dmacHw_INTERRUPT_e blockTransferInterrupt; /* Block trsnafer interrupt */
176 dmacHw_INTERRUPT_e completeTransferInterrupt; /* Complete DMA trsnafer interrupt */
177 dmacHw_INTERRUPT_e errorInterrupt; /* Error interrupt */
178 dmacHw_CHANNEL_PRIORITY_e channelPriority; /* Channel priority */
179 dmacHw_FLOW_CONTROL_e flowControler; /* Data flow controller */
180} dmacHw_CONFIG_t;
181
182/****************************************************************************/
183/**
184* @brief Initializes DMA
185*
186* This function initializes DMA CSP driver
187*
188* @note
189* Must be called before using any DMA channel
190*/
191/****************************************************************************/
192void dmacHw_initDma(void);
193
194/****************************************************************************/
195/**
196* @brief Exit function for DMA
197*
198* This function isolates DMA from the system
199*
200*/
201/****************************************************************************/
202void dmacHw_exitDma(void);
203
204/****************************************************************************/
205/**
206* @brief Gets a handle to a DMA channel
207*
208* This function returns a handle, representing a control block of a particular DMA channel
209*
210* @return -1 - On Failure
211* handle - On Success, representing a channel control block
212*
213* @note
214* None Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro
215*/
216/****************************************************************************/
217dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId /* [ IN ] DMA Channel Id */
218 );
219
220/****************************************************************************/
221/**
222* @brief Initializes a DMA channel for use
223*
224* This function initializes and resets a DMA channel for use
225*
226* @return -1 - On Failure
227* 0 - On Success
228*
229* @note
230* None
231*/
232/****************************************************************************/
233int dmacHw_initChannel(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
234 );
235
236/****************************************************************************/
237/**
238* @brief Estimates number of descriptor needed to perform certain DMA transfer
239*
240*
241* @return On failure : -1
242* On success : Number of descriptor count
243*
244*
245*/
246/****************************************************************************/
247int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
248 void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */
249 void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */
250 size_t dataLen /* [ IN ] Data length in bytes */
251 );
252
253/****************************************************************************/
254/**
255* @brief Initializes descriptor ring
256*
257* This function will initializes the descriptor ring of a DMA channel
258*
259*
260* @return -1 - On failure
261* 0 - On success
262* @note
263* - "len" parameter should be obtained from "dmacHw_descriptorLen"
264* - Descriptor buffer MUST be 32 bit aligned and uncached as it
265* is accessed by ARM and DMA
266*/
267/****************************************************************************/
268int dmacHw_initDescriptor(void *pDescriptorVirt, /* [ IN ] Virtual address of uncahced buffer allocated to form descriptor ring */
269 uint32_t descriptorPhyAddr, /* [ IN ] Physical address of pDescriptorVirt (descriptor buffer) */
270 uint32_t len, /* [ IN ] Size of the pBuf */
271 uint32_t num /* [ IN ] Number of descriptor in the ring */
272 );
273
274/****************************************************************************/
275/**
276* @brief Finds amount of memory required to form a descriptor ring
277*
278*
279* @return Number of bytes required to form a descriptor ring
280*
281*
282* @note
283* None
284*/
285/****************************************************************************/
286uint32_t dmacHw_descriptorLen(uint32_t descCnt /* [ IN ] Number of descriptor in the ring */
287 );
288
289/****************************************************************************/
290/**
291* @brief Configure DMA channel
292*
293* @return 0 : On success
294* -1 : On failure
295*/
296/****************************************************************************/
297int dmacHw_configChannel(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
298 dmacHw_CONFIG_t *pConfig /* [ IN ] Configuration settings */
299 );
300
301/****************************************************************************/
302/**
303* @brief Set descriptors for known data length
304*
305* When DMA has to work as a flow controller, this function prepares the
306* descriptor chain to transfer data
307*
308* from:
309* - Memory to memory
310* - Peripheral to memory
311* - Memory to Peripheral
312* - Peripheral to Peripheral
313*
314* @return -1 - On failure
315* 0 - On success
316*
317*/
318/****************************************************************************/
319int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
320 void *pDescriptor, /* [ IN ] Descriptor buffer */
321 void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */
322 void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */
323 size_t dataLen /* [ IN ] Length in bytes */
324 );
325
326/****************************************************************************/
327/**
328* @brief Indicates whether DMA transfer is in progress or completed
329*
330* @return DMA transfer status
331* dmacHw_TRANSFER_STATUS_BUSY: DMA Transfer ongoing
332* dmacHw_TRANSFER_STATUS_DONE: DMA Transfer completed
333* dmacHw_TRANSFER_STATUS_ERROR: DMA Transfer error
334*
335*/
336/****************************************************************************/
337dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
338 );
339
340/****************************************************************************/
341/**
342* @brief Set descriptor carrying control information
343*
344* This function will be used to send specific control information to the device
345* using the DMA channel
346*
347*
348* @return -1 - On failure
349* 0 - On success
350*
351* @note
352* None
353*/
354/****************************************************************************/
355int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
356 void *pDescriptor, /* [ IN ] Descriptor buffer */
357 uint32_t ctlAddress, /* [ IN ] Address of the device control register */
358 uint32_t control /* [ IN ] Device control information */
359 );
360
361/****************************************************************************/
362/**
363* @brief Read data DMA transferred to memory
364*
365* This function will read data that has been DMAed to memory while transferring from:
366* - Memory to memory
367* - Peripheral to memory
368*
369* @return 0 - No more data is available to read
370* 1 - More data might be available to read
371*
372*/
373/****************************************************************************/
374int dmacHw_readTransferredData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
375 dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
376 void *pDescriptor, /* [ IN ] Descriptor buffer */
377 void **ppBbuf, /* [ OUT ] Data received */
378 size_t *pLlen /* [ OUT ] Length of the data received */
379 );
380
381/****************************************************************************/
382/**
383* @brief Prepares descriptor ring, when source peripheral working as a flow controller
384*
385* This function will form the descriptor ring by allocating buffers, when source peripheral
386* has to work as a flow controller to transfer data from:
387* - Peripheral to memory.
388*
389* @return -1 - On failure
390* 0 - On success
391*
392*
393* @note
394* None
395*/
396/****************************************************************************/
397int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
398 dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
399 void *pDescriptor, /* [ IN ] Descriptor buffer */
400 uint32_t srcAddr, /* [ IN ] Source peripheral address */
401 void *(*fpAlloc) (int len), /* [ IN ] Function pointer that provides destination memory */
402 int len, /* [ IN ] Number of bytes "fpAlloc" will allocate for destination */
403 int num /* [ IN ] Number of descriptor to set */
404 );
405
406/****************************************************************************/
407/**
408* @brief Program channel register to initiate transfer
409*
410* @return void
411*
412*
413* @note
414* - Descriptor buffer MUST ALWAYS be flushed before calling this function
415* - This function should also be called from ISR to program the channel with
416* pending descriptors
417*/
418/****************************************************************************/
419void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
420 dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
421 void *pDescriptor /* [ IN ] Descriptor buffer */
422 );
423
424/****************************************************************************/
425/**
426* @brief Resets descriptor control information
427*
428* @return void
429*/
430/****************************************************************************/
431void dmacHw_resetDescriptorControl(void *pDescriptor /* [ IN ] Descriptor buffer */
432 );
433
434/****************************************************************************/
435/**
436* @brief Program channel register to stop transfer
437*
438* Ensures the channel is not doing any transfer after calling this function
439*
440* @return void
441*
442*/
443/****************************************************************************/
444void dmacHw_stopTransfer(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
445 );
446
447/****************************************************************************/
448/**
449* @brief Check the existence of pending descriptor
450*
451* This function confirmes if there is any pending descriptor in the chain
452* to program the channel
453*
454* @return 1 : Channel need to be programmed with pending descriptor
455* 0 : No more pending descriptor to programe the channel
456*
457* @note
458* - This function should be called from ISR in case there are pending
459* descriptor to program the channel.
460*
461* Example:
462*
463* dmac_isr ()
464* {
465* ...
466* if (dmacHw_descriptorPending (handle))
467* {
468* dmacHw_initiateTransfer (handle);
469* }
470* }
471*
472*/
473/****************************************************************************/
474uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
475 void *pDescriptor /* [ IN ] Descriptor buffer */
476 );
477
478/****************************************************************************/
479/**
480* @brief Deallocates source or destination memory, allocated
481*
482* This function can be called to deallocate data memory that was DMAed successfully
483*
484* @return -1 - On failure
485* 0 - On success
486*
487* @note
488* This function will be called ONLY, when source OR destination address is pointing
489* to dynamic memory
490*/
491/****************************************************************************/
492int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
493 void *pDescriptor, /* [ IN ] Descriptor buffer */
494 void (*fpFree) (void *) /* [ IN ] Function pointer to free data memory */
495 );
496
497/****************************************************************************/
498/**
499* @brief Clears the interrupt
500*
501* This function clears the DMA channel specific interrupt
502*
503* @return N/A
504*
505* @note
506* Must be called under the context of ISR
507*/
508/****************************************************************************/
509void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
510 );
511
512/****************************************************************************/
513/**
514* @brief Returns the cause of channel specific DMA interrupt
515*
516* This function returns the cause of interrupt
517*
518* @return Interrupt status, each bit representing a specific type of interrupt
519* of type dmacHw_INTERRUPT_STATUS_e
520* @note
521* This function should be called under the context of ISR
522*/
523/****************************************************************************/
524dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
525 );
526
527/****************************************************************************/
528/**
529* @brief Indentifies a DMA channel causing interrupt
530*
531* This functions returns a channel causing interrupt of type dmacHw_INTERRUPT_STATUS_e
532*
533* @return NULL : No channel causing DMA interrupt
534* ! NULL : Handle to a channel causing DMA interrupt
535* @note
536* dmacHw_clearInterrupt() must be called with a valid handle after calling this function
537*/
538/****************************************************************************/
539dmacHw_HANDLE_t dmacHw_getInterruptSource(void);
540
541/****************************************************************************/
542/**
543* @brief Sets channel specific user data
544*
545* This function associates user data to a specific DMA channel
546*
547*/
548/****************************************************************************/
549void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
550 void *userData /* [ IN ] User data */
551 );
552
553/****************************************************************************/
554/**
555* @brief Gets channel specific user data
556*
557* This function returns user data specific to a DMA channel
558*
559* @return user data
560*/
561/****************************************************************************/
562void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
563 );
564
565/****************************************************************************/
566/**
567* @brief Displays channel specific registers and other control parameters
568*
569*
570* @return void
571*
572* @note
573* None
574*/
575/****************************************************************************/
576void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
577 void *pDescriptor, /* [ IN ] Descriptor buffer */
578 int (*fpPrint) (const char *, ...) /* [ IN ] Print callback function */
579 );
580
581/****************************************************************************/
582/**
583* @brief Provides DMA controller attributes
584*
585*
586* @return DMA controller attributes
587*
588* @note
589* None
590*/
591/****************************************************************************/
592uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
593 dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controller attribute of type dmacHw_CONTROLLER_ATTRIB_e */
594 );
595
596#endif /* _DMACHW_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
deleted file mode 100644
index 9d9455e0c391..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
+++ /dev/null
@@ -1,145 +0,0 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file dmacHw_priv.h
18*
19* @brief Private Definitions for low level DMA driver
20*
21*/
22/****************************************************************************/
23
24#ifndef _DMACHW_PRIV_H
25#define _DMACHW_PRIV_H
26
27#include <linux/types.h>
28
29/* Data type for DMA Link List Item */
30typedef struct {
31 uint32_t sar; /* Source Address Register.
32 Address must be aligned to CTLx.SRC_TR_WIDTH. */
33 uint32_t dar; /* Destination Address Register.
34 Address must be aligned to CTLx.DST_TR_WIDTH. */
35 uint32_t llpPhy; /* LLP contains the physical address of the next descriptor for block chaining using linked lists.
36 Address MUST be aligned to a 32-bit boundary. */
37 dmacHw_REG64_t ctl; /* Control Register. 64 bits */
38 uint32_t sstat; /* Source Status Register */
39 uint32_t dstat; /* Destination Status Register */
40 uint32_t devCtl; /* Device specific control information */
41 uint32_t llp; /* LLP contains the virtual address of the next descriptor for block chaining using linked lists. */
42} dmacHw_DESC_t;
43
44/*
45 * Descriptor ring pointers
46 */
47typedef struct {
48 int num; /* Number of link items */
49 dmacHw_DESC_t *pHead; /* Head of descriptor ring (for writing) */
50 dmacHw_DESC_t *pTail; /* Tail of descriptor ring (for reading) */
51 dmacHw_DESC_t *pProg; /* Descriptor to program the channel (for programming the channel register) */
52 dmacHw_DESC_t *pEnd; /* End of current descriptor chain */
53 dmacHw_DESC_t *pFree; /* Descriptor to free memory (freeing dynamic memory) */
54 uint32_t virt2PhyOffset; /* Virtual to physical address offset for the descriptor ring */
55} dmacHw_DESC_RING_t;
56
57/*
58 * DMA channel control block
59 */
60typedef struct {
61 uint32_t module; /* DMA controller module (0-1) */
62 uint32_t channel; /* DMA channel (0-7) */
63 volatile uint32_t varDataStarted; /* Flag indicating variable data channel is enabled */
64 volatile uint32_t descUpdated; /* Flag to indicate descriptor update is complete */
65 void *userData; /* Channel specifc user data */
66} dmacHw_CBLK_t;
67
68#define dmacHw_ASSERT(a) if (!(a)) while (1)
69#define dmacHw_MAX_CHANNEL_COUNT 16
70#define dmacHw_FREE_USER_MEMORY 0xFFFFFFFF
71#define dmacHw_DESC_FREE dmacHw_REG_CTL_DONE
72#define dmacHw_DESC_INIT ((dmacHw_DESC_t *) 0xFFFFFFFF)
73#define dmacHw_MAX_BLOCKSIZE 4064
74#define dmacHw_GET_DESC_RING(addr) (dmacHw_DESC_RING_t *)(addr)
75#define dmacHw_ADDRESS_MASK(byte) ((byte) - 1)
76#define dmacHw_NEXT_DESC(rp, dp) ((rp)->dp = (dmacHw_DESC_t *)(rp)->dp->llp)
77#define dmacHw_HANDLE_TO_CBLK(handle) ((dmacHw_CBLK_t *) (handle))
78#define dmacHw_CBLK_TO_HANDLE(cblkp) ((dmacHw_HANDLE_t) (cblkp))
79#define dmacHw_DST_IS_MEMORY(tt) (((tt) == dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) || ((tt) == dmacHw_TRANSFER_TYPE_MEM_TO_MEM)) ? 1 : 0
80
81/****************************************************************************/
82/**
83* @brief Get next available transaction width
84*
85*
86* @return On success : Next available transaction width
87* On failure : dmacHw_TRANSACTION_WIDTH_8
88*
89* @note
90* None
91*/
92/****************************************************************************/
93static inline dmacHw_TRANSACTION_WIDTH_e dmacHw_GetNextTrWidth(dmacHw_TRANSACTION_WIDTH_e tw /* [ IN ] Current transaction width */
94 ) {
95 if (tw & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) {
96 return ((tw >> dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT) -
97 1) << dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT;
98 } else if (tw & dmacHw_REG_CTL_DST_TR_WIDTH_MASK) {
99 return ((tw >> dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT) -
100 1) << dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT;
101 }
102
103 /* Default return */
104 return dmacHw_SRC_TRANSACTION_WIDTH_8;
105}
106
107/****************************************************************************/
108/**
109* @brief Get number of bytes per transaction
110*
111* @return Number of bytes per transaction
112*
113*
114* @note
115* None
116*/
117/****************************************************************************/
118static inline int dmacHw_GetTrWidthInBytes(dmacHw_TRANSACTION_WIDTH_e tw /* [ IN ] Transaction width */
119 ) {
120 int width = 1;
121 switch (tw) {
122 case dmacHw_SRC_TRANSACTION_WIDTH_8:
123 width = 1;
124 break;
125 case dmacHw_SRC_TRANSACTION_WIDTH_16:
126 case dmacHw_DST_TRANSACTION_WIDTH_16:
127 width = 2;
128 break;
129 case dmacHw_SRC_TRANSACTION_WIDTH_32:
130 case dmacHw_DST_TRANSACTION_WIDTH_32:
131 width = 4;
132 break;
133 case dmacHw_SRC_TRANSACTION_WIDTH_64:
134 case dmacHw_DST_TRANSACTION_WIDTH_64:
135 width = 8;
136 break;
137 default:
138 dmacHw_ASSERT(0);
139 }
140
141 /* Default transaction width */
142 return width;
143}
144
145#endif /* _DMACHW_PRIV_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
deleted file mode 100644
index 7cd0aafa6f6e..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
+++ /dev/null
@@ -1,406 +0,0 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file dmacHw_reg.h
18*
19* @brief Definitions for low level DMA registers
20*
21*/
22/****************************************************************************/
23
24#ifndef _DMACHW_REG_H
25#define _DMACHW_REG_H
26
27#include <linux/types.h>
28#include <mach/csp/mm_io.h>
29
30/* Data type for 64 bit little endian register */
31typedef struct {
32 volatile uint32_t lo; /* Lower 32 bit in little endian mode */
33 volatile uint32_t hi; /* Upper 32 bit in little endian mode */
34} dmacHw_REG64_t;
35
36/* Data type representing DMA channel registers */
37typedef struct {
38 dmacHw_REG64_t ChannelSar; /* Source Address Register. 64 bits (upper 32 bits are reserved)
39 Address must be aligned to CTLx.SRC_TR_WIDTH.
40 */
41 dmacHw_REG64_t ChannelDar; /* Destination Address Register.64 bits (upper 32 bits are reserved)
42 Address must be aligned to CTLx.DST_TR_WIDTH.
43 */
44 dmacHw_REG64_t ChannelLlp; /* Link List Pointer.64 bits (upper 32 bits are reserved)
45 LLP contains the pointer to the next LLI for block chaining using linked lists.
46 If LLPis set to 0x0, then transfers using linked lists are not enabled.
47 Address MUST be aligned to a 32-bit boundary.
48 */
49 dmacHw_REG64_t ChannelCtl; /* Control Register. 64 bits */
50 dmacHw_REG64_t ChannelSstat; /* Source Status Register */
51 dmacHw_REG64_t ChannelDstat; /* Destination Status Register */
52 dmacHw_REG64_t ChannelSstatAddr; /* Source Status Address Register */
53 dmacHw_REG64_t ChannelDstatAddr; /* Destination Status Address Register */
54 dmacHw_REG64_t ChannelConfig; /* Channel Configuration Register */
55 dmacHw_REG64_t SrcGather; /* Source gather register */
56 dmacHw_REG64_t DstScatter; /* Destination scatter register */
57} dmacHw_CH_REG_t;
58
59/* Data type for RAW interrupt status registers */
60typedef struct {
61 dmacHw_REG64_t RawTfr; /* Raw Status for IntTfr Interrupt */
62 dmacHw_REG64_t RawBlock; /* Raw Status for IntBlock Interrupt */
63 dmacHw_REG64_t RawSrcTran; /* Raw Status for IntSrcTran Interrupt */
64 dmacHw_REG64_t RawDstTran; /* Raw Status for IntDstTran Interrupt */
65 dmacHw_REG64_t RawErr; /* Raw Status for IntErr Interrupt */
66} dmacHw_INT_RAW_t;
67
68/* Data type for interrupt status registers */
69typedef struct {
70 dmacHw_REG64_t StatusTfr; /* Status for IntTfr Interrupt */
71 dmacHw_REG64_t StatusBlock; /* Status for IntBlock Interrupt */
72 dmacHw_REG64_t StatusSrcTran; /* Status for IntSrcTran Interrupt */
73 dmacHw_REG64_t StatusDstTran; /* Status for IntDstTran Interrupt */
74 dmacHw_REG64_t StatusErr; /* Status for IntErr Interrupt */
75} dmacHw_INT_STATUS_t;
76
77/* Data type for interrupt mask registers*/
78typedef struct {
79 dmacHw_REG64_t MaskTfr; /* Mask for IntTfr Interrupt */
80 dmacHw_REG64_t MaskBlock; /* Mask for IntBlock Interrupt */
81 dmacHw_REG64_t MaskSrcTran; /* Mask for IntSrcTran Interrupt */
82 dmacHw_REG64_t MaskDstTran; /* Mask for IntDstTran Interrupt */
83 dmacHw_REG64_t MaskErr; /* Mask for IntErr Interrupt */
84} dmacHw_INT_MASK_t;
85
86/* Data type for interrupt clear registers */
87typedef struct {
88 dmacHw_REG64_t ClearTfr; /* Clear for IntTfr Interrupt */
89 dmacHw_REG64_t ClearBlock; /* Clear for IntBlock Interrupt */
90 dmacHw_REG64_t ClearSrcTran; /* Clear for IntSrcTran Interrupt */
91 dmacHw_REG64_t ClearDstTran; /* Clear for IntDstTran Interrupt */
92 dmacHw_REG64_t ClearErr; /* Clear for IntErr Interrupt */
93 dmacHw_REG64_t StatusInt; /* Status for each interrupt type */
94} dmacHw_INT_CLEAR_t;
95
96/* Data type for software handshaking registers */
97typedef struct {
98 dmacHw_REG64_t ReqSrcReg; /* Source Software Transaction Request Register */
99 dmacHw_REG64_t ReqDstReg; /* Destination Software Transaction Request Register */
100 dmacHw_REG64_t SglReqSrcReg; /* Single Source Transaction Request Register */
101 dmacHw_REG64_t SglReqDstReg; /* Single Destination Transaction Request Register */
102 dmacHw_REG64_t LstSrcReg; /* Last Source Transaction Request Register */
103 dmacHw_REG64_t LstDstReg; /* Last Destination Transaction Request Register */
104} dmacHw_SW_HANDSHAKE_t;
105
106/* Data type for misc. registers */
107typedef struct {
108 dmacHw_REG64_t DmaCfgReg; /* DMA Configuration Register */
109 dmacHw_REG64_t ChEnReg; /* DMA Channel Enable Register */
110 dmacHw_REG64_t DmaIdReg; /* DMA ID Register */
111 dmacHw_REG64_t DmaTestReg; /* DMA Test Register */
112 dmacHw_REG64_t Reserved0; /* Reserved */
113 dmacHw_REG64_t Reserved1; /* Reserved */
114 dmacHw_REG64_t CompParm6; /* Component Parameter 6 */
115 dmacHw_REG64_t CompParm5; /* Component Parameter 5 */
116 dmacHw_REG64_t CompParm4; /* Component Parameter 4 */
117 dmacHw_REG64_t CompParm3; /* Component Parameter 3 */
118 dmacHw_REG64_t CompParm2; /* Component Parameter 2 */
119 dmacHw_REG64_t CompParm1; /* Component Parameter 1 */
120 dmacHw_REG64_t CompId; /* Compoent ID */
121} dmacHw_MISC_t;
122
123/* Base registers */
124#define dmacHw_0_MODULE_BASE_ADDR (char __iomem*) MM_IO_BASE_DMA0 /* DMAC 0 module's base address */
125#define dmacHw_1_MODULE_BASE_ADDR (char __iomem*) MM_IO_BASE_DMA1 /* DMAC 1 module's base address */
126
127extern uint32_t dmaChannelCount_0;
128extern uint32_t dmaChannelCount_1;
129
130/* Define channel specific registers */
131#define dmacHw_CHAN_BASE(module, chan) ((dmacHw_CH_REG_t __iomem*) ((char __iomem*)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t))))
132
133/* Raw interrupt status registers */
134#define dmacHw_REG_INT_RAW_BASE(module) ((char __iomem *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0)))
135#define dmacHw_REG_INT_RAW_TRAN(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo)
136#define dmacHw_REG_INT_RAW_BLOCK(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo)
137#define dmacHw_REG_INT_RAW_STRAN(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo)
138#define dmacHw_REG_INT_RAW_DTRAN(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo)
139#define dmacHw_REG_INT_RAW_ERROR(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo)
140
141/* Interrupt status registers */
142#define dmacHw_REG_INT_STAT_BASE(module) ((char __iomem*)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t)))
143#define dmacHw_REG_INT_STAT_TRAN(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo)
144#define dmacHw_REG_INT_STAT_BLOCK(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo)
145#define dmacHw_REG_INT_STAT_STRAN(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo)
146#define dmacHw_REG_INT_STAT_DTRAN(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo)
147#define dmacHw_REG_INT_STAT_ERROR(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo)
148
149/* Interrupt status registers */
150#define dmacHw_REG_INT_MASK_BASE(module) ((char __iomem*)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t)))
151#define dmacHw_REG_INT_MASK_TRAN(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo)
152#define dmacHw_REG_INT_MASK_BLOCK(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo)
153#define dmacHw_REG_INT_MASK_STRAN(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo)
154#define dmacHw_REG_INT_MASK_DTRAN(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo)
155#define dmacHw_REG_INT_MASK_ERROR(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo)
156
157/* Interrupt clear registers */
158#define dmacHw_REG_INT_CLEAR_BASE(module) ((char __iomem*)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t)))
159#define dmacHw_REG_INT_CLEAR_TRAN(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo)
160#define dmacHw_REG_INT_CLEAR_BLOCK(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo)
161#define dmacHw_REG_INT_CLEAR_STRAN(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo)
162#define dmacHw_REG_INT_CLEAR_DTRAN(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo)
163#define dmacHw_REG_INT_CLEAR_ERROR(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo)
164#define dmacHw_REG_INT_STATUS(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo)
165
166/* Software handshaking registers */
167#define dmacHw_REG_SW_HS_BASE(module) ((char __iomem*)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t)))
168#define dmacHw_REG_SW_HS_SRC_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo)
169#define dmacHw_REG_SW_HS_DST_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo)
170#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo)
171#define dmacHw_REG_SW_HS_DST_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo)
172#define dmacHw_REG_SW_HS_SRC_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo)
173#define dmacHw_REG_SW_HS_DST_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo)
174
175/* Miscellaneous registers */
176#define dmacHw_REG_MISC_BASE(module) ((char __iomem*)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t)))
177#define dmacHw_REG_MISC_CFG(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo)
178#define dmacHw_REG_MISC_CH_ENABLE(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo)
179#define dmacHw_REG_MISC_ID(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo)
180#define dmacHw_REG_MISC_TEST(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo)
181#define dmacHw_REG_MISC_COMP_PARAM1_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo)
182#define dmacHw_REG_MISC_COMP_PARAM1_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi)
183#define dmacHw_REG_MISC_COMP_PARAM2_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo)
184#define dmacHw_REG_MISC_COMP_PARAM2_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi)
185#define dmacHw_REG_MISC_COMP_PARAM3_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo)
186#define dmacHw_REG_MISC_COMP_PARAM3_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi)
187#define dmacHw_REG_MISC_COMP_PARAM4_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo)
188#define dmacHw_REG_MISC_COMP_PARAM4_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi)
189#define dmacHw_REG_MISC_COMP_PARAM5_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo)
190#define dmacHw_REG_MISC_COMP_PARAM5_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi)
191#define dmacHw_REG_MISC_COMP_PARAM6_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo)
192#define dmacHw_REG_MISC_COMP_PARAM6_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi)
193
194/* Channel control registers */
195#define dmacHw_REG_SAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo)
196#define dmacHw_REG_DAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelDar.lo)
197#define dmacHw_REG_LLP(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelLlp.lo)
198
199#define dmacHw_REG_CTL_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.lo)
200#define dmacHw_REG_CTL_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.hi)
201
202#define dmacHw_REG_SSTAT(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSstat.lo)
203#define dmacHw_REG_DSTAT(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelDstat.lo)
204#define dmacHw_REG_SSTATAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSstatAddr.lo)
205#define dmacHw_REG_DSTATAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelDstatAddr.lo)
206
207#define dmacHw_REG_CFG_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.lo)
208#define dmacHw_REG_CFG_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.hi)
209
210#define dmacHw_REG_SGR_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->SrcGather.lo)
211#define dmacHw_REG_SGR_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->SrcGather.hi)
212
213#define dmacHw_REG_DSR_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->DstScatter.lo)
214#define dmacHw_REG_DSR_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->DstScatter.hi)
215
216#define INT_STATUS_MASK(channel) (0x00000001 << (channel))
217#define CHANNEL_BUSY(mod, channel) (dmacHw_REG_MISC_CH_ENABLE((mod)) & (0x00000001 << (channel)))
218
219/* Bit mask for REG_DMACx_CTL_LO */
220
221#define dmacHw_REG_CTL_INT_EN 0x00000001 /* Channel interrupt enable */
222
223#define dmacHw_REG_CTL_DST_TR_WIDTH_MASK 0x0000000E /* Destination transaction width mask */
224#define dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT 1
225#define dmacHw_REG_CTL_DST_TR_WIDTH_8 0x00000000 /* Destination transaction width 8 bit */
226#define dmacHw_REG_CTL_DST_TR_WIDTH_16 0x00000002 /* Destination transaction width 16 bit */
227#define dmacHw_REG_CTL_DST_TR_WIDTH_32 0x00000004 /* Destination transaction width 32 bit */
228#define dmacHw_REG_CTL_DST_TR_WIDTH_64 0x00000006 /* Destination transaction width 64 bit */
229
230#define dmacHw_REG_CTL_SRC_TR_WIDTH_MASK 0x00000070 /* Source transaction width mask */
231#define dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT 4
232#define dmacHw_REG_CTL_SRC_TR_WIDTH_8 0x00000000 /* Source transaction width 8 bit */
233#define dmacHw_REG_CTL_SRC_TR_WIDTH_16 0x00000010 /* Source transaction width 16 bit */
234#define dmacHw_REG_CTL_SRC_TR_WIDTH_32 0x00000020 /* Source transaction width 32 bit */
235#define dmacHw_REG_CTL_SRC_TR_WIDTH_64 0x00000030 /* Source transaction width 64 bit */
236
237#define dmacHw_REG_CTL_DS_ENABLE 0x00040000 /* Destination scatter enable */
238#define dmacHw_REG_CTL_SG_ENABLE 0x00020000 /* Source gather enable */
239
240#define dmacHw_REG_CTL_DINC_MASK 0x00000180 /* Destination address inc/dec mask */
241#define dmacHw_REG_CTL_DINC_INC 0x00000000 /* Destination address increment */
242#define dmacHw_REG_CTL_DINC_DEC 0x00000080 /* Destination address decrement */
243#define dmacHw_REG_CTL_DINC_NC 0x00000100 /* Destination address no change */
244
245#define dmacHw_REG_CTL_SINC_MASK 0x00000600 /* Source address inc/dec mask */
246#define dmacHw_REG_CTL_SINC_INC 0x00000000 /* Source address increment */
247#define dmacHw_REG_CTL_SINC_DEC 0x00000200 /* Source address decrement */
248#define dmacHw_REG_CTL_SINC_NC 0x00000400 /* Source address no change */
249
250#define dmacHw_REG_CTL_DST_MSIZE_MASK 0x00003800 /* Destination burst transaction length */
251#define dmacHw_REG_CTL_DST_MSIZE_0 0x00000000 /* No Destination burst */
252#define dmacHw_REG_CTL_DST_MSIZE_4 0x00000800 /* Destination burst transaction length 4 */
253#define dmacHw_REG_CTL_DST_MSIZE_8 0x00001000 /* Destination burst transaction length 8 */
254#define dmacHw_REG_CTL_DST_MSIZE_16 0x00001800 /* Destination burst transaction length 16 */
255
256#define dmacHw_REG_CTL_SRC_MSIZE_MASK 0x0001C000 /* Source burst transaction length */
257#define dmacHw_REG_CTL_SRC_MSIZE_0 0x00000000 /* No Source burst */
258#define dmacHw_REG_CTL_SRC_MSIZE_4 0x00004000 /* Source burst transaction length 4 */
259#define dmacHw_REG_CTL_SRC_MSIZE_8 0x00008000 /* Source burst transaction length 8 */
260#define dmacHw_REG_CTL_SRC_MSIZE_16 0x0000C000 /* Source burst transaction length 16 */
261
262#define dmacHw_REG_CTL_TTFC_MASK 0x00700000 /* Transfer type and flow controller */
263#define dmacHw_REG_CTL_TTFC_MM_DMAC 0x00000000 /* Memory to Memory with DMAC as flow controller */
264#define dmacHw_REG_CTL_TTFC_MP_DMAC 0x00100000 /* Memory to Peripheral with DMAC as flow controller */
265#define dmacHw_REG_CTL_TTFC_PM_DMAC 0x00200000 /* Peripheral to Memory with DMAC as flow controller */
266#define dmacHw_REG_CTL_TTFC_PP_DMAC 0x00300000 /* Peripheral to Peripheral with DMAC as flow controller */
267#define dmacHw_REG_CTL_TTFC_PM_PERI 0x00400000 /* Peripheral to Memory with Peripheral as flow controller */
268#define dmacHw_REG_CTL_TTFC_PP_SPERI 0x00500000 /* Peripheral to Peripheral with Source Peripheral as flow controller */
269#define dmacHw_REG_CTL_TTFC_MP_PERI 0x00600000 /* Memory to Peripheral with Peripheral as flow controller */
270#define dmacHw_REG_CTL_TTFC_PP_DPERI 0x00700000 /* Peripheral to Peripheral with Destination Peripheral as flow controller */
271
272#define dmacHw_REG_CTL_DMS_MASK 0x01800000 /* Destination AHB master interface */
273#define dmacHw_REG_CTL_DMS_1 0x00000000 /* Destination AHB master interface 1 */
274#define dmacHw_REG_CTL_DMS_2 0x00800000 /* Destination AHB master interface 2 */
275
276#define dmacHw_REG_CTL_SMS_MASK 0x06000000 /* Source AHB master interface */
277#define dmacHw_REG_CTL_SMS_1 0x00000000 /* Source AHB master interface 1 */
278#define dmacHw_REG_CTL_SMS_2 0x02000000 /* Source AHB master interface 2 */
279
280#define dmacHw_REG_CTL_LLP_DST_EN 0x08000000 /* Block chaining enable for destination side */
281#define dmacHw_REG_CTL_LLP_SRC_EN 0x10000000 /* Block chaining enable for source side */
282
283/* Bit mask for REG_DMACx_CTL_HI */
284#define dmacHw_REG_CTL_BLOCK_TS_MASK 0x00000FFF /* Block transfer size */
285#define dmacHw_REG_CTL_DONE 0x00001000 /* Block trasnfer done */
286
287/* Bit mask for REG_DMACx_CFG_LO */
288#define dmacHw_REG_CFG_LO_CH_PRIORITY_SHIFT 5 /* Channel priority shift */
289#define dmacHw_REG_CFG_LO_CH_PRIORITY_MASK 0x000000E0 /* Channel priority mask */
290#define dmacHw_REG_CFG_LO_CH_PRIORITY_0 0x00000000 /* Channel priority 0 */
291#define dmacHw_REG_CFG_LO_CH_PRIORITY_1 0x00000020 /* Channel priority 1 */
292#define dmacHw_REG_CFG_LO_CH_PRIORITY_2 0x00000040 /* Channel priority 2 */
293#define dmacHw_REG_CFG_LO_CH_PRIORITY_3 0x00000060 /* Channel priority 3 */
294#define dmacHw_REG_CFG_LO_CH_PRIORITY_4 0x00000080 /* Channel priority 4 */
295#define dmacHw_REG_CFG_LO_CH_PRIORITY_5 0x000000A0 /* Channel priority 5 */
296#define dmacHw_REG_CFG_LO_CH_PRIORITY_6 0x000000C0 /* Channel priority 6 */
297#define dmacHw_REG_CFG_LO_CH_PRIORITY_7 0x000000E0 /* Channel priority 7 */
298
299#define dmacHw_REG_CFG_LO_CH_SUSPEND 0x00000100 /* Channel suspend */
300#define dmacHw_REG_CFG_LO_CH_FIFO_EMPTY 0x00000200 /* Channel FIFO empty */
301#define dmacHw_REG_CFG_LO_DST_CH_SW_HS 0x00000400 /* Destination channel SW handshaking */
302#define dmacHw_REG_CFG_LO_SRC_CH_SW_HS 0x00000800 /* Source channel SW handshaking */
303
304#define dmacHw_REG_CFG_LO_CH_LOCK_MASK 0x00003000 /* Channel locking mask */
305#define dmacHw_REG_CFG_LO_CH_LOCK_DMA 0x00000000 /* Channel lock over the entire DMA transfer operation */
306#define dmacHw_REG_CFG_LO_CH_LOCK_BLOCK 0x00001000 /* Channel lock over the block transfer operation */
307#define dmacHw_REG_CFG_LO_CH_LOCK_TRANS 0x00002000 /* Channel lock over the transaction */
308#define dmacHw_REG_CFG_LO_CH_LOCK_ENABLE 0x00010000 /* Channel lock enable */
309
310#define dmacHw_REG_CFG_LO_BUS_LOCK_MASK 0x0000C000 /* Bus locking mask */
311#define dmacHw_REG_CFG_LO_BUS_LOCK_DMA 0x00000000 /* Bus lock over the entire DMA transfer operation */
312#define dmacHw_REG_CFG_LO_BUS_LOCK_BLOCK 0x00004000 /* Bus lock over the block transfer operation */
313#define dmacHw_REG_CFG_LO_BUS_LOCK_TRANS 0x00008000 /* Bus lock over the transaction */
314#define dmacHw_REG_CFG_LO_BUS_LOCK_ENABLE 0x00020000 /* Bus lock enable */
315
316#define dmacHw_REG_CFG_LO_DST_HS_POLARITY_LOW 0x00040000 /* Destination channel handshaking signal polarity low */
317#define dmacHw_REG_CFG_LO_SRC_HS_POLARITY_LOW 0x00080000 /* Source channel handshaking signal polarity low */
318
319#define dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK 0x3FF00000 /* Maximum AMBA burst length */
320
321#define dmacHw_REG_CFG_LO_AUTO_RELOAD_SRC 0x40000000 /* Source address auto reload */
322#define dmacHw_REG_CFG_LO_AUTO_RELOAD_DST 0x80000000 /* Destination address auto reload */
323
324/* Bit mask for REG_DMACx_CFG_HI */
325#define dmacHw_REG_CFG_HI_FC_DST_READY 0x00000001 /* Source transaction request is serviced when destination is ready */
326#define dmacHw_REG_CFG_HI_FIFO_ENOUGH 0x00000002 /* Initiate burst transaction when enough data in available in FIFO */
327
328#define dmacHw_REG_CFG_HI_AHB_HPROT_MASK 0x0000001C /* AHB protection mask */
329#define dmacHw_REG_CFG_HI_AHB_HPROT_1 0x00000004 /* AHB protection 1 */
330#define dmacHw_REG_CFG_HI_AHB_HPROT_2 0x00000008 /* AHB protection 2 */
331#define dmacHw_REG_CFG_HI_AHB_HPROT_3 0x00000010 /* AHB protection 3 */
332
333#define dmacHw_REG_CFG_HI_UPDATE_DST_STAT 0x00000020 /* Destination status update enable */
334#define dmacHw_REG_CFG_HI_UPDATE_SRC_STAT 0x00000040 /* Source status update enable */
335
336#define dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK 0x00000780 /* Source peripheral hardware interface mask */
337#define dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK 0x00007800 /* Destination peripheral hardware interface mask */
338
339/* DMA Configuration Parameters */
340#define dmacHw_REG_COMP_PARAM_NUM_CHANNELS 0x00000700 /* Number of channels */
341#define dmacHw_REG_COMP_PARAM_NUM_INTERFACE 0x00001800 /* Number of master interface */
342#define dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE 0x0000000f /* Maximum brust size */
343#define dmacHw_REG_COMP_PARAM_DATA_WIDTH 0x00006000 /* Data transfer width */
344
345/* Define GET/SET macros to program the registers */
346#define dmacHw_SET_SAR(module, channel, addr) (dmacHw_REG_SAR((module), (channel)) = (uint32_t) (addr))
347#define dmacHw_SET_DAR(module, channel, addr) (dmacHw_REG_DAR((module), (channel)) = (uint32_t) (addr))
348#define dmacHw_SET_LLP(module, channel, ptr) (dmacHw_REG_LLP((module), (channel)) = (uint32_t) (ptr))
349
350#define dmacHw_GET_SSTAT(module, channel) (dmacHw_REG_SSTAT((module), (channel)))
351#define dmacHw_GET_DSTAT(module, channel) (dmacHw_REG_DSTAT((module), (channel)))
352
353#define dmacHw_SET_SSTATAR(module, channel, addr) (dmacHw_REG_SSTATAR((module), (channel)) = (uint32_t) (addr))
354#define dmacHw_SET_DSTATAR(module, channel, addr) (dmacHw_REG_DSTATAR((module), (channel)) = (uint32_t) (addr))
355
356#define dmacHw_SET_CONTROL_LO(module, channel, ctl) (dmacHw_REG_CTL_LO((module), (channel)) |= (ctl))
357#define dmacHw_RESET_CONTROL_LO(module, channel) (dmacHw_REG_CTL_LO((module), (channel)) = 0)
358#define dmacHw_GET_CONTROL_LO(module, channel) (dmacHw_REG_CTL_LO((module), (channel)))
359
360#define dmacHw_SET_CONTROL_HI(module, channel, ctl) (dmacHw_REG_CTL_HI((module), (channel)) |= (ctl))
361#define dmacHw_RESET_CONTROL_HI(module, channel) (dmacHw_REG_CTL_HI((module), (channel)) = 0)
362#define dmacHw_GET_CONTROL_HI(module, channel) (dmacHw_REG_CTL_HI((module), (channel)))
363
364#define dmacHw_GET_BLOCK_SIZE(module, channel) (dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_BLOCK_TS_MASK)
365#define dmacHw_DMA_COMPLETE(module, channel) (dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_DONE)
366
367#define dmacHw_SET_CONFIG_LO(module, channel, cfg) (dmacHw_REG_CFG_LO((module), (channel)) |= (cfg))
368#define dmacHw_RESET_CONFIG_LO(module, channel) (dmacHw_REG_CFG_LO((module), (channel)) = 0)
369#define dmacHw_GET_CONFIG_LO(module, channel) (dmacHw_REG_CFG_LO((module), (channel)))
370#define dmacHw_SET_AMBA_BUSRT_LEN(module, channel, len) (dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), (channel)) & ~(dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK)) | (((len) << 20) & dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK))
371#define dmacHw_SET_CHANNEL_PRIORITY(module, channel, prio) (dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), (channel)) & ~(dmacHw_REG_CFG_LO_CH_PRIORITY_MASK)) | (prio))
372#define dmacHw_SET_AHB_HPROT(module, channel, protect) (dmacHw_REG_CFG_HI(module, channel) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_AHB_HPROT_MASK)) | (protect))
373
374#define dmacHw_SET_CONFIG_HI(module, channel, cfg) (dmacHw_REG_CFG_HI((module), (channel)) |= (cfg))
375#define dmacHw_RESET_CONFIG_HI(module, channel) (dmacHw_REG_CFG_HI((module), (channel)) = 0)
376#define dmacHw_GET_CONFIG_HI(module, channel) (dmacHw_REG_CFG_HI((module), (channel)))
377#define dmacHw_SET_SRC_PERI_INTF(module, channel, intf) (dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)) | (((intf) << 7) & dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK))
378#define dmacHw_SRC_PERI_INTF(intf) (((intf) << 7) & dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)
379#define dmacHw_SET_DST_PERI_INTF(module, channel, intf) (dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)) | (((intf) << 11) & dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK))
380#define dmacHw_DST_PERI_INTF(intf) (((intf) << 11) & dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)
381
382#define dmacHw_DMA_START(module, channel) (dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
383#define dmacHw_DMA_STOP(module, channel) (dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)))
384#define dmacHw_DMA_ENABLE(module) (dmacHw_REG_MISC_CFG((module)) = 1)
385#define dmacHw_DMA_DISABLE(module) (dmacHw_REG_MISC_CFG((module)) = 0)
386
387#define dmacHw_TRAN_INT_ENABLE(module, channel) (dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
388#define dmacHw_BLOCK_INT_ENABLE(module, channel) (dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
389#define dmacHw_ERROR_INT_ENABLE(module, channel) (dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
390
391#define dmacHw_TRAN_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)))
392#define dmacHw_BLOCK_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)))
393#define dmacHw_ERROR_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)))
394#define dmacHw_STRAN_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_STRAN((module)) = (0x00000001 << ((channel) + 8)))
395#define dmacHw_DTRAN_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_DTRAN((module)) = (0x00000001 << ((channel) + 8)))
396
397#define dmacHw_TRAN_INT_CLEAR(module, channel) (dmacHw_REG_INT_CLEAR_TRAN((module)) = (0x00000001 << (channel)))
398#define dmacHw_BLOCK_INT_CLEAR(module, channel) (dmacHw_REG_INT_CLEAR_BLOCK((module)) = (0x00000001 << (channel)))
399#define dmacHw_ERROR_INT_CLEAR(module, channel) (dmacHw_REG_INT_CLEAR_ERROR((module)) = (0x00000001 << (channel)))
400
401#define dmacHw_GET_NUM_CHANNEL(module) (((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_NUM_CHANNELS) >> 8) + 1)
402#define dmacHw_GET_NUM_INTERFACE(module) (((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_NUM_INTERFACE) >> 11) + 1)
403#define dmacHw_GET_MAX_BLOCK_SIZE(module, channel) ((dmacHw_REG_MISC_COMP_PARAM1_LO((module)) >> (4 * (channel))) & dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE)
404#define dmacHw_GET_CHANNEL_DATA_WIDTH(module, channel) ((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_DATA_WIDTH) >> 13)
405
406#endif /* _DMACHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
deleted file mode 100644
index 27f59dd27792..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
+++ /dev/null
@@ -1,73 +0,0 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15
16#ifndef CSP_HW_CFG_H
17#define CSP_HW_CFG_H
18
19/* ---- Include Files ---------------------------------------------------- */
20
21#include <mach/cfg_global.h>
22#include <mach/csp/cap_inline.h>
23
24#if defined(__KERNEL__)
25#include <mach/memory_settings.h>
26#else
27#include <hw_cfg.h>
28#endif
29
30/* Some items that can be defined externally, but will be set to default values */
31/* if they are not defined. */
32/* HW_CFG_PLL_SPREAD_SPECTRUM_DISABLE Default undefined and SS is enabled. */
33/* HW_CFG_SDRAM_CAS_LATENCY 5 Default 5, Values [3..6] */
34/* HW_CFG_SDRAM_CHIP_SELECT_CNT 1 Default 1, Vaules [1..2] */
35/* HW_CFG_SDRAM_SPEED_GRADE 667 Default 667, Values [400,533,667,800] */
36/* HW_CFG_SDRAM_WIDTH_BITS 16 Default 16, Vaules [8,16] */
37/* HW_CFG_SDRAM_ADDR_BRC Default undefined and Row-Bank-Col (RBC) addressing used. Define to use Bank-Row-Col (BRC). */
38/* HW_CFG_SDRAM_CLK_ASYNC Default undefined and DDR clock is synchronous with AXI BUS clock. Define for ASYNC mode. */
39
40#if defined(CFG_GLOBAL_CHIP)
41 #if (CFG_GLOBAL_CHIP == FPGA11107)
42 #define HW_CFG_BUS_CLK_HZ 5000000
43 #define HW_CFG_DDR_CTLR_CLK_HZ 10000000
44 #define HW_CFG_DDR_PHY_OMIT
45 #define HW_CFG_UART_CLK_HZ 7500000
46 #else
47 #define HW_CFG_PLL_VCO_HZ 2000000000
48 #define HW_CFG_PLL2_VCO_HZ 1800000000
49 #define HW_CFG_ARM_CLK_HZ CAP_HW_CFG_ARM_CLK_HZ
50 #define HW_CFG_BUS_CLK_HZ 166666666
51 #define HW_CFG_DDR_CTLR_CLK_HZ 333333333
52 #define HW_CFG_DDR_PHY_CLK_HZ (2 * HW_CFG_DDR_CTLR_CLK_HZ)
53 #define HW_CFG_UART_CLK_HZ 142857142
54 #define HW_CFG_VPM_CLK_HZ CAP_HW_CFG_VPM_CLK_HZ
55 #endif
56#else
57 #define HW_CFG_PLL_VCO_HZ 1800000000
58 #define HW_CFG_PLL2_VCO_HZ 1800000000
59 #define HW_CFG_ARM_CLK_HZ 450000000
60 #define HW_CFG_BUS_CLK_HZ 150000000
61 #define HW_CFG_DDR_CTLR_CLK_HZ 300000000
62 #define HW_CFG_DDR_PHY_CLK_HZ (2 * HW_CFG_DDR_CTLR_CLK_HZ)
63 #define HW_CFG_UART_CLK_HZ 150000000
64 #define HW_CFG_VPM_CLK_HZ 300000000
65#endif
66
67/* ---- Public Constants and Types --------------------------------------- */
68/* ---- Public Variable Externs ------------------------------------------ */
69/* ---- Public Function Prototypes --------------------------------------- */
70
71
72#endif /* CSP_HW_CFG_H */
73
diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
deleted file mode 100644
index f59db25b5632..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
+++ /dev/null
@@ -1,246 +0,0 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file intcHw_reg.h
18*
19* @brief platform specific interrupt controller bit assignments
20*
21* @note
22* None
23*/
24/****************************************************************************/
25
26#ifndef _INTCHW_REG_H
27#define _INTCHW_REG_H
28
29/* ---- Include Files ---------------------------------------------------- */
30#include <linux/types.h>
31#include <mach/csp/reg.h>
32#include <mach/csp/mm_io.h>
33
34/* ---- Public Constants and Types --------------------------------------- */
35
36#define INTCHW_NUM_IRQ_PER_INTC 32 /* Maximum number of interrupt controllers */
37#define INTCHW_NUM_INTC 3
38
39/* Defines for interrupt controllers. This simplifies and cleans up the function calls. */
40#define INTCHW_INTC0 (MM_IO_BASE_INTC0)
41#define INTCHW_INTC1 (MM_IO_BASE_INTC1)
42#define INTCHW_SINTC (MM_IO_BASE_SINTC)
43
44/* INTC0 - interrupt controller 0 */
45#define INTCHW_INTC0_PIF_BITNUM 31 /* Peripheral interface interrupt */
46#define INTCHW_INTC0_CLCD_BITNUM 30 /* LCD Controller interrupt */
47#define INTCHW_INTC0_GE_BITNUM 29 /* Graphic engine interrupt */
48#define INTCHW_INTC0_APM_BITNUM 28 /* Audio process module interrupt */
49#define INTCHW_INTC0_ESW_BITNUM 27 /* Ethernet switch interrupt */
50#define INTCHW_INTC0_SPIH_BITNUM 26 /* SPI host interrupt */
51#define INTCHW_INTC0_TIMER3_BITNUM 25 /* Timer3 interrupt */
52#define INTCHW_INTC0_TIMER2_BITNUM 24 /* Timer2 interrupt */
53#define INTCHW_INTC0_TIMER1_BITNUM 23 /* Timer1 interrupt */
54#define INTCHW_INTC0_TIMER0_BITNUM 22 /* Timer0 interrupt */
55#define INTCHW_INTC0_SDIOH1_BITNUM 21 /* SDIO1 host interrupt */
56#define INTCHW_INTC0_SDIOH0_BITNUM 20 /* SDIO0 host interrupt */
57#define INTCHW_INTC0_USBD_BITNUM 19 /* USB device interrupt */
58#define INTCHW_INTC0_USBH1_BITNUM 18 /* USB1 host interrupt */
59#define INTCHW_INTC0_USBHD2_BITNUM 17 /* USB host2/device2 interrupt */
60#define INTCHW_INTC0_VPM_BITNUM 16 /* Voice process module interrupt */
61#define INTCHW_INTC0_DMA1C7_BITNUM 15 /* DMA1 channel 7 interrupt */
62#define INTCHW_INTC0_DMA1C6_BITNUM 14 /* DMA1 channel 6 interrupt */
63#define INTCHW_INTC0_DMA1C5_BITNUM 13 /* DMA1 channel 5 interrupt */
64#define INTCHW_INTC0_DMA1C4_BITNUM 12 /* DMA1 channel 4 interrupt */
65#define INTCHW_INTC0_DMA1C3_BITNUM 11 /* DMA1 channel 3 interrupt */
66#define INTCHW_INTC0_DMA1C2_BITNUM 10 /* DMA1 channel 2 interrupt */
67#define INTCHW_INTC0_DMA1C1_BITNUM 9 /* DMA1 channel 1 interrupt */
68#define INTCHW_INTC0_DMA1C0_BITNUM 8 /* DMA1 channel 0 interrupt */
69#define INTCHW_INTC0_DMA0C7_BITNUM 7 /* DMA0 channel 7 interrupt */
70#define INTCHW_INTC0_DMA0C6_BITNUM 6 /* DMA0 channel 6 interrupt */
71#define INTCHW_INTC0_DMA0C5_BITNUM 5 /* DMA0 channel 5 interrupt */
72#define INTCHW_INTC0_DMA0C4_BITNUM 4 /* DMA0 channel 4 interrupt */
73#define INTCHW_INTC0_DMA0C3_BITNUM 3 /* DMA0 channel 3 interrupt */
74#define INTCHW_INTC0_DMA0C2_BITNUM 2 /* DMA0 channel 2 interrupt */
75#define INTCHW_INTC0_DMA0C1_BITNUM 1 /* DMA0 channel 1 interrupt */
76#define INTCHW_INTC0_DMA0C0_BITNUM 0 /* DMA0 channel 0 interrupt */
77
78#define INTCHW_INTC0_PIF (1<<INTCHW_INTC0_PIF_BITNUM)
79#define INTCHW_INTC0_CLCD (1<<INTCHW_INTC0_CLCD_BITNUM)
80#define INTCHW_INTC0_GE (1<<INTCHW_INTC0_GE_BITNUM)
81#define INTCHW_INTC0_APM (1<<INTCHW_INTC0_APM_BITNUM)
82#define INTCHW_INTC0_ESW (1<<INTCHW_INTC0_ESW_BITNUM)
83#define INTCHW_INTC0_SPIH (1<<INTCHW_INTC0_SPIH_BITNUM)
84#define INTCHW_INTC0_TIMER3 (1<<INTCHW_INTC0_TIMER3_BITNUM)
85#define INTCHW_INTC0_TIMER2 (1<<INTCHW_INTC0_TIMER2_BITNUM)
86#define INTCHW_INTC0_TIMER1 (1<<INTCHW_INTC0_TIMER1_BITNUM)
87#define INTCHW_INTC0_TIMER0 (1<<INTCHW_INTC0_TIMER0_BITNUM)
88#define INTCHW_INTC0_SDIOH1 (1<<INTCHW_INTC0_SDIOH1_BITNUM)
89#define INTCHW_INTC0_SDIOH0 (1<<INTCHW_INTC0_SDIOH0_BITNUM)
90#define INTCHW_INTC0_USBD (1<<INTCHW_INTC0_USBD_BITNUM)
91#define INTCHW_INTC0_USBH1 (1<<INTCHW_INTC0_USBH1_BITNUM)
92#define INTCHW_INTC0_USBHD2 (1<<INTCHW_INTC0_USBHD2_BITNUM)
93#define INTCHW_INTC0_VPM (1<<INTCHW_INTC0_VPM_BITNUM)
94#define INTCHW_INTC0_DMA1C7 (1<<INTCHW_INTC0_DMA1C7_BITNUM)
95#define INTCHW_INTC0_DMA1C6 (1<<INTCHW_INTC0_DMA1C6_BITNUM)
96#define INTCHW_INTC0_DMA1C5 (1<<INTCHW_INTC0_DMA1C5_BITNUM)
97#define INTCHW_INTC0_DMA1C4 (1<<INTCHW_INTC0_DMA1C4_BITNUM)
98#define INTCHW_INTC0_DMA1C3 (1<<INTCHW_INTC0_DMA1C3_BITNUM)
99#define INTCHW_INTC0_DMA1C2 (1<<INTCHW_INTC0_DMA1C2_BITNUM)
100#define INTCHW_INTC0_DMA1C1 (1<<INTCHW_INTC0_DMA1C1_BITNUM)
101#define INTCHW_INTC0_DMA1C0 (1<<INTCHW_INTC0_DMA1C0_BITNUM)
102#define INTCHW_INTC0_DMA0C7 (1<<INTCHW_INTC0_DMA0C7_BITNUM)
103#define INTCHW_INTC0_DMA0C6 (1<<INTCHW_INTC0_DMA0C6_BITNUM)
104#define INTCHW_INTC0_DMA0C5 (1<<INTCHW_INTC0_DMA0C5_BITNUM)
105#define INTCHW_INTC0_DMA0C4 (1<<INTCHW_INTC0_DMA0C4_BITNUM)
106#define INTCHW_INTC0_DMA0C3 (1<<INTCHW_INTC0_DMA0C3_BITNUM)
107#define INTCHW_INTC0_DMA0C2 (1<<INTCHW_INTC0_DMA0C2_BITNUM)
108#define INTCHW_INTC0_DMA0C1 (1<<INTCHW_INTC0_DMA0C1_BITNUM)
109#define INTCHW_INTC0_DMA0C0 (1<<INTCHW_INTC0_DMA0C0_BITNUM)
110
111/* INTC1 - interrupt controller 1 */
112#define INTCHW_INTC1_DDRVPMP_BITNUM 27 /* DDR and VPM PLL clock phase relationship interrupt (Not for A0) */
113#define INTCHW_INTC1_DDRVPMT_BITNUM 26 /* DDR and VPM HW phase align timeout interrupt (Not for A0) */
114#define INTCHW_INTC1_DDRP_BITNUM 26 /* DDR and PLL clock phase relationship interrupt (For A0 only)) */
115#define INTCHW_INTC1_RTC2_BITNUM 25 /* Real time clock tamper interrupt */
116#define INTCHW_INTC1_VDEC_BITNUM 24 /* Hantro Video Decoder interrupt */
117/* Bits 13-23 are non-secure versions of the corresponding secure bits in SINTC bits 0-10. */
118#define INTCHW_INTC1_SPUM_BITNUM 23 /* Secure process module interrupt */
119#define INTCHW_INTC1_RTC1_BITNUM 22 /* Real time clock one-shot interrupt */
120#define INTCHW_INTC1_RTC0_BITNUM 21 /* Real time clock periodic interrupt */
121#define INTCHW_INTC1_RNG_BITNUM 20 /* Random number generator interrupt */
122#define INTCHW_INTC1_FMPU_BITNUM 19 /* Flash memory parition unit interrupt */
123#define INTCHW_INTC1_VMPU_BITNUM 18 /* VRAM memory partition interrupt */
124#define INTCHW_INTC1_DMPU_BITNUM 17 /* DDR2 memory partition interrupt */
125#define INTCHW_INTC1_KEYC_BITNUM 16 /* Key pad controller interrupt */
126#define INTCHW_INTC1_TSC_BITNUM 15 /* Touch screen controller interrupt */
127#define INTCHW_INTC1_UART0_BITNUM 14 /* UART 0 */
128#define INTCHW_INTC1_WDOG_BITNUM 13 /* Watchdog timer interrupt */
129
130#define INTCHW_INTC1_UART1_BITNUM 12 /* UART 1 */
131#define INTCHW_INTC1_PMUIRQ_BITNUM 11 /* ARM performance monitor interrupt */
132#define INTCHW_INTC1_COMMRX_BITNUM 10 /* ARM DDC receive interrupt */
133#define INTCHW_INTC1_COMMTX_BITNUM 9 /* ARM DDC transmit interrupt */
134#define INTCHW_INTC1_FLASHC_BITNUM 8 /* Flash controller interrupt */
135#define INTCHW_INTC1_GPHY_BITNUM 7 /* Gigabit Phy interrupt */
136#define INTCHW_INTC1_SPIS_BITNUM 6 /* SPI slave interrupt */
137#define INTCHW_INTC1_I2CS_BITNUM 5 /* I2C slave interrupt */
138#define INTCHW_INTC1_I2CH_BITNUM 4 /* I2C host interrupt */
139#define INTCHW_INTC1_I2S1_BITNUM 3 /* I2S1 interrupt */
140#define INTCHW_INTC1_I2S0_BITNUM 2 /* I2S0 interrupt */
141#define INTCHW_INTC1_GPIO1_BITNUM 1 /* GPIO bit 64//32 combined interrupt */
142#define INTCHW_INTC1_GPIO0_BITNUM 0 /* GPIO bit 31//0 combined interrupt */
143
144#define INTCHW_INTC1_DDRVPMT (1<<INTCHW_INTC1_DDRVPMT_BITNUM)
145#define INTCHW_INTC1_DDRVPMP (1<<INTCHW_INTC1_DDRVPMP_BITNUM)
146#define INTCHW_INTC1_DDRP (1<<INTCHW_INTC1_DDRP_BITNUM)
147#define INTCHW_INTC1_VDEC (1<<INTCHW_INTC1_VDEC_BITNUM)
148#define INTCHW_INTC1_SPUM (1<<INTCHW_INTC1_SPUM_BITNUM)
149#define INTCHW_INTC1_RTC2 (1<<INTCHW_INTC1_RTC2_BITNUM)
150#define INTCHW_INTC1_RTC1 (1<<INTCHW_INTC1_RTC1_BITNUM)
151#define INTCHW_INTC1_RTC0 (1<<INTCHW_INTC1_RTC0_BITNUM)
152#define INTCHW_INTC1_RNG (1<<INTCHW_INTC1_RNG_BITNUM)
153#define INTCHW_INTC1_FMPU (1<<INTCHW_INTC1_FMPU_BITNUM)
154#define INTCHW_INTC1_IMPU (1<<INTCHW_INTC1_IMPU_BITNUM)
155#define INTCHW_INTC1_DMPU (1<<INTCHW_INTC1_DMPU_BITNUM)
156#define INTCHW_INTC1_KEYC (1<<INTCHW_INTC1_KEYC_BITNUM)
157#define INTCHW_INTC1_TSC (1<<INTCHW_INTC1_TSC_BITNUM)
158#define INTCHW_INTC1_UART0 (1<<INTCHW_INTC1_UART0_BITNUM)
159#define INTCHW_INTC1_WDOG (1<<INTCHW_INTC1_WDOG_BITNUM)
160#define INTCHW_INTC1_UART1 (1<<INTCHW_INTC1_UART1_BITNUM)
161#define INTCHW_INTC1_PMUIRQ (1<<INTCHW_INTC1_PMUIRQ_BITNUM)
162#define INTCHW_INTC1_COMMRX (1<<INTCHW_INTC1_COMMRX_BITNUM)
163#define INTCHW_INTC1_COMMTX (1<<INTCHW_INTC1_COMMTX_BITNUM)
164#define INTCHW_INTC1_FLASHC (1<<INTCHW_INTC1_FLASHC_BITNUM)
165#define INTCHW_INTC1_GPHY (1<<INTCHW_INTC1_GPHY_BITNUM)
166#define INTCHW_INTC1_SPIS (1<<INTCHW_INTC1_SPIS_BITNUM)
167#define INTCHW_INTC1_I2CS (1<<INTCHW_INTC1_I2CS_BITNUM)
168#define INTCHW_INTC1_I2CH (1<<INTCHW_INTC1_I2CH_BITNUM)
169#define INTCHW_INTC1_I2S1 (1<<INTCHW_INTC1_I2S1_BITNUM)
170#define INTCHW_INTC1_I2S0 (1<<INTCHW_INTC1_I2S0_BITNUM)
171#define INTCHW_INTC1_GPIO1 (1<<INTCHW_INTC1_GPIO1_BITNUM)
172#define INTCHW_INTC1_GPIO0 (1<<INTCHW_INTC1_GPIO0_BITNUM)
173
174/* SINTC secure int controller */
175#define INTCHW_SINTC_RTC2_BITNUM 15 /* Real time clock tamper interrupt */
176#define INTCHW_SINTC_TIMER3_BITNUM 14 /* Secure timer3 interrupt */
177#define INTCHW_SINTC_TIMER2_BITNUM 13 /* Secure timer2 interrupt */
178#define INTCHW_SINTC_TIMER1_BITNUM 12 /* Secure timer1 interrupt */
179#define INTCHW_SINTC_TIMER0_BITNUM 11 /* Secure timer0 interrupt */
180#define INTCHW_SINTC_SPUM_BITNUM 10 /* Secure process module interrupt */
181#define INTCHW_SINTC_RTC1_BITNUM 9 /* Real time clock one-shot interrupt */
182#define INTCHW_SINTC_RTC0_BITNUM 8 /* Real time clock periodic interrupt */
183#define INTCHW_SINTC_RNG_BITNUM 7 /* Random number generator interrupt */
184#define INTCHW_SINTC_FMPU_BITNUM 6 /* Flash memory parition unit interrupt */
185#define INTCHW_SINTC_VMPU_BITNUM 5 /* VRAM memory partition interrupt */
186#define INTCHW_SINTC_DMPU_BITNUM 4 /* DDR2 memory partition interrupt */
187#define INTCHW_SINTC_KEYC_BITNUM 3 /* Key pad controller interrupt */
188#define INTCHW_SINTC_TSC_BITNUM 2 /* Touch screen controller interrupt */
189#define INTCHW_SINTC_UART0_BITNUM 1 /* UART0 interrupt */
190#define INTCHW_SINTC_WDOG_BITNUM 0 /* Watchdog timer interrupt */
191
192#define INTCHW_SINTC_TIMER3 (1<<INTCHW_SINTC_TIMER3_BITNUM)
193#define INTCHW_SINTC_TIMER2 (1<<INTCHW_SINTC_TIMER2_BITNUM)
194#define INTCHW_SINTC_TIMER1 (1<<INTCHW_SINTC_TIMER1_BITNUM)
195#define INTCHW_SINTC_TIMER0 (1<<INTCHW_SINTC_TIMER0_BITNUM)
196#define INTCHW_SINTC_SPUM (1<<INTCHW_SINTC_SPUM_BITNUM)
197#define INTCHW_SINTC_RTC2 (1<<INTCHW_SINTC_RTC2_BITNUM)
198#define INTCHW_SINTC_RTC1 (1<<INTCHW_SINTC_RTC1_BITNUM)
199#define INTCHW_SINTC_RTC0 (1<<INTCHW_SINTC_RTC0_BITNUM)
200#define INTCHW_SINTC_RNG (1<<INTCHW_SINTC_RNG_BITNUM)
201#define INTCHW_SINTC_FMPU (1<<INTCHW_SINTC_FMPU_BITNUM)
202#define INTCHW_SINTC_IMPU (1<<INTCHW_SINTC_IMPU_BITNUM)
203#define INTCHW_SINTC_DMPU (1<<INTCHW_SINTC_DMPU_BITNUM)
204#define INTCHW_SINTC_KEYC (1<<INTCHW_SINTC_KEYC_BITNUM)
205#define INTCHW_SINTC_TSC (1<<INTCHW_SINTC_TSC_BITNUM)
206#define INTCHW_SINTC_UART0 (1<<INTCHW_SINTC_UART0_BITNUM)
207#define INTCHW_SINTC_WDOG (1<<INTCHW_SINTC_WDOG_BITNUM)
208
209/* PL192 Vectored Interrupt Controller (VIC) layout */
210#define INTCHW_IRQSTATUS 0x00 /* IRQ status register */
211#define INTCHW_FIQSTATUS 0x04 /* FIQ status register */
212#define INTCHW_RAWINTR 0x08 /* Raw Interrupt Status register */
213#define INTCHW_INTSELECT 0x0c /* Interrupt Select Register */
214#define INTCHW_INTENABLE 0x10 /* Interrupt Enable Register */
215#define INTCHW_INTENCLEAR 0x14 /* Interrupt Enable Clear Register */
216#define INTCHW_SOFTINT 0x18 /* Soft Interrupt Register */
217#define INTCHW_SOFTINTCLEAR 0x1c /* Soft Interrupt Clear Register */
218#define INTCHW_PROTECTION 0x20 /* Protection Enable Register */
219#define INTCHW_SWPRIOMASK 0x24 /* Software Priority Mask Register */
220#define INTCHW_PRIODAISY 0x28 /* Priority Daisy Chain Register */
221#define INTCHW_VECTADDR0 0x100 /* Vector Address Registers */
222#define INTCHW_VECTPRIO0 0x200 /* Vector Priority Registers 0-31 */
223#define INTCHW_ADDRESS 0xf00 /* Vector Address Register 0-31 */
224#define INTCHW_PID 0xfe0 /* Peripheral ID Register 0-3 */
225#define INTCHW_PCELLID 0xff0 /* PrimeCell ID Register 0-3 */
226
227/* Example Usage: intcHw_irq_enable(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
228/* intcHw_irq_clear(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
229/* uint32_t bits = intcHw_irq_status(INTCHW_INTC0); */
230/* uint32_t bits = intcHw_irq_raw_status(INTCHW_INTC0); */
231
232/* ---- Public Variable Externs ------------------------------------------ */
233/* ---- Public Function Prototypes --------------------------------------- */
234/* Clear one or more IRQ interrupts. */
235static inline void intcHw_irq_disable(void __iomem *basep, uint32_t mask)
236{
237 writel(mask, basep + INTCHW_INTENCLEAR);
238}
239
240/* Enables one or more IRQ interrupts. */
241static inline void intcHw_irq_enable(void __iomem *basep, uint32_t mask)
242{
243 writel(mask, basep + INTCHW_INTENABLE);
244}
245
246#endif /* _INTCHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
deleted file mode 100644
index d571962f2904..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
+++ /dev/null
@@ -1,101 +0,0 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file mm_addr.h
18*
19* @brief Memory Map address definitions
20*
21* @note
22* None
23*/
24/****************************************************************************/
25
26#ifndef _MM_ADDR_H
27#define _MM_ADDR_H
28
29/* ---- Include Files ---------------------------------------------------- */
30
31#if !defined(CSP_SIMULATION)
32#include <mach/cfg_global.h>
33#endif
34
35/* ---- Public Constants and Types --------------------------------------- */
36
37/* Memory Map address definitions */
38
39#define MM_ADDR_DDR 0x00000000
40
41#define MM_ADDR_IO_VPM_EXTMEM_RSVD 0x0F000000 /* 16 MB - Reserved external memory for VPM use */
42
43#define MM_ADDR_IO_FLASHC 0x20000000
44#define MM_ADDR_IO_BROM 0x30000000
45#define MM_ADDR_IO_ARAM 0x30100000 /* 64 KB - extra cycle latency - WS switch */
46#define MM_ADDR_IO_DMA0 0x30200000
47#define MM_ADDR_IO_DMA1 0x30300000
48#define MM_ADDR_IO_ESW 0x30400000
49#define MM_ADDR_IO_CLCD 0x30500000
50#define MM_ADDR_IO_PIF 0x30580000
51#define MM_ADDR_IO_APM 0x30600000
52#define MM_ADDR_IO_SPUM 0x30700000
53#define MM_ADDR_IO_VPM_PROG 0x30800000
54#define MM_ADDR_IO_VPM_DATA 0x30A00000
55#define MM_ADDR_IO_VRAM 0x40000000 /* 64 KB - security block in front of it */
56#define MM_ADDR_IO_CHIPC 0x80000000
57#define MM_ADDR_IO_UMI 0x80001000
58#define MM_ADDR_IO_NAND 0x80001800
59#define MM_ADDR_IO_LEDM 0x80002000
60#define MM_ADDR_IO_PWM 0x80002040
61#define MM_ADDR_IO_VINTC 0x80003000
62#define MM_ADDR_IO_GPIO0 0x80004000
63#define MM_ADDR_IO_GPIO1 0x80004800
64#define MM_ADDR_IO_I2CS 0x80005000
65#define MM_ADDR_IO_SPIS 0x80006000
66#define MM_ADDR_IO_HPM 0x80007400
67#define MM_ADDR_IO_HPM_REMAP 0x80007800
68#define MM_ADDR_IO_TZPC 0x80008000
69#define MM_ADDR_IO_MPU 0x80009000
70#define MM_ADDR_IO_SPUMP 0x8000a000
71#define MM_ADDR_IO_PKA 0x8000b000
72#define MM_ADDR_IO_RNG 0x8000c000
73#define MM_ADDR_IO_KEYC 0x8000d000
74#define MM_ADDR_IO_BBL 0x8000e000
75#define MM_ADDR_IO_OTP 0x8000f000
76#define MM_ADDR_IO_I2S0 0x80010000
77#define MM_ADDR_IO_I2S1 0x80011000
78#define MM_ADDR_IO_UARTA 0x80012000
79#define MM_ADDR_IO_UARTB 0x80013000
80#define MM_ADDR_IO_I2CH 0x80014020
81#define MM_ADDR_IO_SPIH 0x80015000
82#define MM_ADDR_IO_TSC 0x80016000
83#define MM_ADDR_IO_TMR 0x80017000
84#define MM_ADDR_IO_WATCHDOG 0x80017800
85#define MM_ADDR_IO_ETM 0x80018000
86#define MM_ADDR_IO_DDRC 0x80019000
87#define MM_ADDR_IO_SINTC 0x80100000
88#define MM_ADDR_IO_INTC0 0x80200000
89#define MM_ADDR_IO_INTC1 0x80201000
90#define MM_ADDR_IO_GE 0x80300000
91#define MM_ADDR_IO_USB_CTLR0 0x80400000
92#define MM_ADDR_IO_USB_CTLR1 0x80410000
93#define MM_ADDR_IO_USB_PHY 0x80420000
94#define MM_ADDR_IO_SDIOH0 0x80500000
95#define MM_ADDR_IO_SDIOH1 0x80600000
96#define MM_ADDR_IO_VDEC 0x80700000
97
98/* ---- Public Variable Externs ------------------------------------------ */
99/* ---- Public Function Prototypes --------------------------------------- */
100
101#endif /* _MM_ADDR_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
deleted file mode 100644
index 47450c23685a..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
+++ /dev/null
@@ -1,147 +0,0 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file mm_io.h
18*
19* @brief Memory Map I/O definitions
20*
21* @note
22* None
23*/
24/****************************************************************************/
25
26#ifndef _MM_IO_H
27#define _MM_IO_H
28
29/* ---- Include Files ---------------------------------------------------- */
30#include <mach/csp/mm_addr.h>
31
32#if !defined(CSP_SIMULATION)
33#include <mach/cfg_global.h>
34#endif
35
36/* ---- Public Constants and Types --------------------------------------- */
37
38#if defined(CONFIG_MMU)
39
40/* This macro is referenced in <mach/io.h>
41 * Phys to Virtual 0xNyxxxxxx => 0xFNxxxxxx
42 * This macro is referenced in <asm/arch/io.h>
43 *
44 * Assume VPM address is the last x MB of memory. For VPM, map to
45 * 0xf0000000 and up.
46 */
47
48#ifndef MM_IO_PHYS_TO_VIRT
49#ifdef __ASSEMBLY__
50#define MM_IO_PHYS_TO_VIRT(phys) (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF))
51#else
52#define MM_IO_PHYS_TO_VIRT(phys) (void __iomem *)(((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \
53 (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)))
54#endif
55#endif
56
57/* Virtual to Physical 0xFNxxxxxx => 0xN0xxxxxx */
58
59#ifndef MM_IO_VIRT_TO_PHYS
60#ifdef __ASSEMBLY__
61#define MM_IO_VIRT_TO_PHYS(virt) ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF))
62#else
63#define MM_IO_VIRT_TO_PHYS(virt) (((unsigned long)(virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \
64 ((((unsigned long)(virt) & 0x0F000000) << 4) | ((unsigned long)(virt) & 0xFFFFFF)))
65#endif
66#endif
67
68#else
69
70#ifndef MM_IO_PHYS_TO_VIRT
71#define MM_IO_PHYS_TO_VIRT(phys) (phys)
72#endif
73
74#ifndef MM_IO_VIRT_TO_PHYS
75#define MM_IO_VIRT_TO_PHYS(virt) (virt)
76#endif
77
78#endif
79
80/* Registers in 0xExxxxxxx that should be moved to 0xFxxxxxxx */
81#define MM_IO_BASE_FLASHC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_FLASHC)
82#define MM_IO_BASE_NAND MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_NAND)
83#define MM_IO_BASE_UMI MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UMI)
84
85#define MM_IO_START MM_ADDR_IO_FLASHC /* Physical beginning of IO mapped memory */
86#define MM_IO_BASE MM_IO_BASE_FLASHC /* Virtual beginning of IO mapped memory */
87
88#define MM_IO_BASE_BROM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BROM)
89#define MM_IO_BASE_ARAM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ARAM)
90#define MM_IO_BASE_DMA0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA0)
91#define MM_IO_BASE_DMA1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA1)
92#define MM_IO_BASE_ESW MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ESW)
93#define MM_IO_BASE_CLCD MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CLCD)
94#define MM_IO_BASE_PIF MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PIF)
95#define MM_IO_BASE_APM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_APM)
96#define MM_IO_BASE_SPUM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUM)
97#define MM_IO_BASE_VPM_PROG MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_PROG)
98#define MM_IO_BASE_VPM_DATA MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_DATA)
99
100#define MM_IO_BASE_VRAM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VRAM)
101
102#define MM_IO_BASE_CHIPC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CHIPC)
103#define MM_IO_BASE_DDRC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DDRC)
104#define MM_IO_BASE_LEDM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_LEDM)
105#define MM_IO_BASE_PWM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PWM)
106#define MM_IO_BASE_VINTC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VINTC)
107#define MM_IO_BASE_GPIO0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO0)
108#define MM_IO_BASE_GPIO1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO1)
109#define MM_IO_BASE_TMR MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TMR)
110#define MM_IO_BASE_WATCHDOG MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_WATCHDOG)
111#define MM_IO_BASE_ETM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ETM)
112#define MM_IO_BASE_HPM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM)
113#define MM_IO_BASE_HPM_REMAP MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM_REMAP)
114#define MM_IO_BASE_TZPC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TZPC)
115#define MM_IO_BASE_MPU MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_MPU)
116#define MM_IO_BASE_SPUMP MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUMP)
117#define MM_IO_BASE_PKA MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PKA)
118#define MM_IO_BASE_RNG MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_RNG)
119#define MM_IO_BASE_KEYC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_KEYC)
120#define MM_IO_BASE_BBL MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BBL)
121#define MM_IO_BASE_OTP MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_OTP)
122#define MM_IO_BASE_I2S0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S0)
123#define MM_IO_BASE_I2S1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S1)
124#define MM_IO_BASE_UARTA MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTA)
125#define MM_IO_BASE_UARTB MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTB)
126#define MM_IO_BASE_I2CH MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CH)
127#define MM_IO_BASE_SPIH MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIH)
128#define MM_IO_BASE_TSC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TSC)
129#define MM_IO_BASE_I2CS MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CS)
130#define MM_IO_BASE_SPIS MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIS)
131#define MM_IO_BASE_SINTC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SINTC)
132#define MM_IO_BASE_INTC0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC0)
133#define MM_IO_BASE_INTC1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC1)
134#define MM_IO_BASE_GE MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GE)
135#define MM_IO_BASE_USB_CTLR0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR0)
136#define MM_IO_BASE_USB_CTLR1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR1)
137#define MM_IO_BASE_USB_PHY MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_PHY)
138#define MM_IO_BASE_SDIOH0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH0)
139#define MM_IO_BASE_SDIOH1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH1)
140#define MM_IO_BASE_VDEC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VDEC)
141
142#define MM_IO_BASE_VPM_EXTMEM_RSVD MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_EXTMEM_RSVD)
143
144/* ---- Public Variable Externs ------------------------------------------ */
145/* ---- Public Function Prototypes --------------------------------------- */
146
147#endif /* _MM_IO_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/reg.h b/arch/arm/mach-bcmring/include/mach/csp/reg.h
deleted file mode 100644
index d9cbdca8cd25..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/reg.h
+++ /dev/null
@@ -1,115 +0,0 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file reg.h
18*
19* @brief Generic register definitions used in CSP
20*/
21/****************************************************************************/
22
23#ifndef CSP_REG_H
24#define CSP_REG_H
25
26/* ---- Include Files ---------------------------------------------------- */
27
28#include <linux/types.h>
29#include <linux/io.h>
30
31/* ---- Public Constants and Types --------------------------------------- */
32
33#define __REG32(x) (*((volatile uint32_t __iomem *)(x)))
34#define __REG16(x) (*((volatile uint16_t __iomem *)(x)))
35#define __REG8(x) (*((volatile uint8_t __iomem *) (x)))
36
37/* Macros used to define a sequence of reserved registers. The start / end */
38/* are byte offsets in the particular register definition, with the "end" */
39/* being the offset of the next un-reserved register. E.g. if offsets */
40/* 0x10 through to 0x1f are reserved, then this reserved area could be */
41/* specified as follows. */
42/* typedef struct */
43/* { */
44/* uint32_t reg1; offset 0x00 */
45/* uint32_t reg2; offset 0x04 */
46/* uint32_t reg3; offset 0x08 */
47/* uint32_t reg4; offset 0x0c */
48/* REG32_RSVD(0x10, 0x20); */
49/* uint32_t reg5; offset 0x20 */
50/* ... */
51/* } EXAMPLE_REG_t; */
52#define REG8_RSVD(start, end) uint8_t rsvd_##start[(end - start) / sizeof(uint8_t)]
53#define REG16_RSVD(start, end) uint16_t rsvd_##start[(end - start) / sizeof(uint16_t)]
54#define REG32_RSVD(start, end) uint32_t rsvd_##start[(end - start) / sizeof(uint32_t)]
55
56/* ---- Public Variable Externs ------------------------------------------ */
57/* ---- Public Function Prototypes --------------------------------------- */
58
59/* Note: When protecting multiple statements, the REG_LOCAL_IRQ_SAVE and */
60/* REG_LOCAL_IRQ_RESTORE must be enclosed in { } to allow the */
61/* flags variable to be declared locally. */
62/* e.g. */
63/* statement1; */
64/* { */
65/* REG_LOCAL_IRQ_SAVE; */
66/* <multiple statements here> */
67/* REG_LOCAL_IRQ_RESTORE; */
68/* } */
69/* statement2; */
70/* */
71
72#if defined(__KERNEL__) && !defined(STANDALONE)
73#include <mach/hardware.h>
74#include <linux/interrupt.h>
75
76#define REG_LOCAL_IRQ_SAVE HW_DECLARE_SPINLOCK(reg32) \
77 unsigned long flags; HW_IRQ_SAVE(reg32, flags)
78
79#define REG_LOCAL_IRQ_RESTORE HW_IRQ_RESTORE(reg32, flags)
80
81#else
82
83#define REG_LOCAL_IRQ_SAVE
84#define REG_LOCAL_IRQ_RESTORE
85
86#endif
87
88static inline void reg32_modify_and(volatile uint32_t __iomem *reg, uint32_t value)
89{
90 REG_LOCAL_IRQ_SAVE;
91 __raw_writel(__raw_readl(reg) & value, reg);
92 REG_LOCAL_IRQ_RESTORE;
93}
94
95static inline void reg32_modify_or(volatile uint32_t __iomem *reg, uint32_t value)
96{
97 REG_LOCAL_IRQ_SAVE;
98 __raw_writel(__raw_readl(reg) | value, reg);
99 REG_LOCAL_IRQ_RESTORE;
100}
101
102static inline void reg32_modify_mask(volatile uint32_t __iomem *reg, uint32_t mask,
103 uint32_t value)
104{
105 REG_LOCAL_IRQ_SAVE;
106 __raw_writel((__raw_readl(reg) & mask) | value, reg);
107 REG_LOCAL_IRQ_RESTORE;
108}
109
110static inline void reg32_write(volatile uint32_t __iomem *reg, uint32_t value)
111{
112 __raw_writel(value, reg);
113}
114
115#endif /* CSP_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
deleted file mode 100644
index d15f5f3ec2d8..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
+++ /dev/null
@@ -1,100 +0,0 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file secHw_def.h
18*
19* @brief Definitions for configuring/testing secure blocks
20*
21* @note
22* None
23*/
24/****************************************************************************/
25
26#ifndef SECHW_DEF_H
27#define SECHW_DEF_H
28
29#include <mach/csp/mm_io.h>
30
31/* Bit mask for various secure device */
32#define secHw_BLK_MASK_CHIP_CONTROL 0x00000001
33#define secHw_BLK_MASK_KEY_SCAN 0x00000002
34#define secHw_BLK_MASK_TOUCH_SCREEN 0x00000004
35#define secHw_BLK_MASK_UART0 0x00000008
36#define secHw_BLK_MASK_UART1 0x00000010
37#define secHw_BLK_MASK_WATCHDOG 0x00000020
38#define secHw_BLK_MASK_SPUM 0x00000040
39#define secHw_BLK_MASK_DDR2 0x00000080
40#define secHw_BLK_MASK_EXT_MEM 0x00000100
41#define secHw_BLK_MASK_ESW 0x00000200
42#define secHw_BLK_MASK_SPU 0x00010000
43#define secHw_BLK_MASK_PKA 0x00020000
44#define secHw_BLK_MASK_RNG 0x00040000
45#define secHw_BLK_MASK_RTC 0x00080000
46#define secHw_BLK_MASK_OTP 0x00100000
47#define secHw_BLK_MASK_BOOT 0x00200000
48#define secHw_BLK_MASK_MPU 0x00400000
49#define secHw_BLK_MASK_TZCTRL 0x00800000
50#define secHw_BLK_MASK_INTR 0x01000000
51
52/* Trustzone register set */
53typedef struct {
54 volatile uint32_t status; /* read only - reflects status of writes of 2 write registers */
55 volatile uint32_t setUnsecure; /* write only. reads back as 0 */
56 volatile uint32_t setSecure; /* write only. reads back as 0 */
57} secHw_TZREG_t;
58
59/* There are 2 register sets. The first is for the lower 16 bits, the 2nd */
60/* is for the higher 16 bits. */
61
62typedef enum {
63 secHw_IDX_LS = 0,
64 secHw_IDX_MS = 1,
65 secHw_IDX_NUM
66} secHw_IDX_e;
67
68typedef struct {
69 volatile secHw_TZREG_t reg[secHw_IDX_NUM];
70} secHw_REGS_t;
71
72/****************************************************************************/
73/**
74* @brief Configures a device as a secure device
75*
76*/
77/****************************************************************************/
78static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */
79 );
80
81/****************************************************************************/
82/**
83* @brief Configures a device as a non-secure device
84*
85*/
86/****************************************************************************/
87static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */
88 );
89
90/****************************************************************************/
91/**
92* @brief Get the trustzone status for all components. 1 = non-secure, 0 = secure
93*
94*/
95/****************************************************************************/
96static inline uint32_t secHw_getStatus(void);
97
98#include <mach/csp/secHw_inline.h>
99
100#endif /* SECHW_DEF_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
deleted file mode 100644
index 55d3cd4fd1e7..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
+++ /dev/null
@@ -1,79 +0,0 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file secHw_inline.h
18*
19* @brief Definitions for configuring/testing secure blocks
20*
21* @note
22* None
23*/
24/****************************************************************************/
25
26#ifndef SECHW_INLINE_H
27#define SECHW_INLINE_H
28
29/****************************************************************************/
30/**
31* @brief Configures a device as a secure device
32*
33*/
34/****************************************************************************/
35static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */
36 ) {
37 secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC;
38
39 if (mask & 0x0000FFFF) {
40 regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF;
41 }
42
43 if (mask & 0xFFFF0000) {
44 regp->reg[secHw_IDX_MS].setSecure = mask >> 16;
45 }
46}
47
48/****************************************************************************/
49/**
50* @brief Configures a device as a non-secure device
51*
52*/
53/****************************************************************************/
54static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */
55 ) {
56 secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC;
57
58 if (mask & 0x0000FFFF) {
59 writel(mask & 0x0000FFFF, &regp->reg[secHw_IDX_LS].setUnsecure);
60 }
61 if (mask & 0xFFFF0000) {
62 writel(mask >> 16, &regp->reg[secHw_IDX_MS].setUnsecure);
63 }
64}
65
66/****************************************************************************/
67/**
68* @brief Get the trustzone status for all components. 1 = non-secure, 0 = secure
69*
70*/
71/****************************************************************************/
72static inline uint32_t secHw_getStatus(void)
73{
74 secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC;
75
76 return (regp->reg[1].status << 16) + regp->reg[0].status;
77}
78
79#endif /* SECHW_INLINE_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/tmrHw.h b/arch/arm/mach-bcmring/include/mach/csp/tmrHw.h
deleted file mode 100644
index 1cc882ae60f5..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/tmrHw.h
+++ /dev/null
@@ -1,263 +0,0 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file tmrHw.h
18*
19* @brief API definitions for low level Timer driver
20*
21*/
22/****************************************************************************/
23#ifndef _TMRHW_H
24#define _TMRHW_H
25
26#include <linux/types.h>
27
28typedef uint32_t tmrHw_ID_t; /* Timer ID */
29typedef uint32_t tmrHw_COUNT_t; /* Timer count */
30typedef uint32_t tmrHw_INTERVAL_t; /* Timer interval */
31typedef uint32_t tmrHw_RATE_t; /* Timer event (count/interrupt) rate */
32
33typedef enum {
34 tmrHw_INTERRUPT_STATUS_SET, /* Interrupted */
35 tmrHw_INTERRUPT_STATUS_UNSET /* No Interrupt */
36} tmrHw_INTERRUPT_STATUS_e;
37
38typedef enum {
39 tmrHw_CAPABILITY_CLOCK, /* Clock speed in HHz */
40 tmrHw_CAPABILITY_RESOLUTION /* Timer resolution in bits */
41} tmrHw_CAPABILITY_e;
42
43/****************************************************************************/
44/**
45* @brief Get timer capability
46*
47* This function returns various capabilities/attributes of a timer
48*
49* @return Numeric capability
50*
51*/
52/****************************************************************************/
53uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
54 tmrHw_CAPABILITY_e capability /* [ IN ] Timer capability */
55);
56
57/****************************************************************************/
58/**
59* @brief Configures a periodic timer in terms of timer interrupt rate
60*
61* This function initializes a periodic timer to generate specific number of
62* timer interrupt per second
63*
64* @return On success: Effective timer frequency
65* On failure: 0
66*
67*/
68/****************************************************************************/
69tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
70 tmrHw_RATE_t rate /* [ IN ] Number of timer interrupt per second */
71);
72
73/****************************************************************************/
74/**
75* @brief Configures a periodic timer to generate timer interrupt after
76* certain time interval
77*
78* This function initializes a periodic timer to generate timer interrupt
79* after every time interval in millisecond
80*
81* @return On success: Effective interval set in mili-second
82* On failure: 0
83*
84*/
85/****************************************************************************/
86tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
87 tmrHw_INTERVAL_t msec /* [ IN ] Interval in mili-second */
88);
89
90/****************************************************************************/
91/**
92* @brief Configures a periodic timer to generate timer interrupt just once
93* after certain time interval
94*
95* This function initializes a periodic timer to generate a single ticks after
96* certain time interval in millisecond
97*
98* @return On success: Effective interval set in mili-second
99* On failure: 0
100*
101*/
102/****************************************************************************/
103tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
104 tmrHw_INTERVAL_t msec /* [ IN ] Interval in mili-second */
105);
106
107/****************************************************************************/
108/**
109* @brief Configures a timer to run as a free running timer
110*
111* This function initializes a timer to run as a free running timer
112*
113* @return Timer resolution (count / sec)
114*
115*/
116/****************************************************************************/
117tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
118 uint32_t divider /* [ IN ] Dividing the clock frequency */
119) __attribute__ ((section(".aramtext")));
120
121/****************************************************************************/
122/**
123* @brief Starts a timer
124*
125* This function starts a preconfigured timer
126*
127* @return -1 - On Failure
128* 0 - On Success
129*/
130/****************************************************************************/
131int tmrHw_startTimer(tmrHw_ID_t timerId /* [ IN ] Timer id */
132) __attribute__ ((section(".aramtext")));
133
134/****************************************************************************/
135/**
136* @brief Stops a timer
137*
138* This function stops a running timer
139*
140* @return -1 - On Failure
141* 0 - On Success
142*/
143/****************************************************************************/
144int tmrHw_stopTimer(tmrHw_ID_t timerId /* [ IN ] Timer id */
145);
146
147/****************************************************************************/
148/**
149* @brief Gets current timer count
150*
151* This function returns the current timer value
152*
153* @return Current downcounting timer value
154*
155*/
156/****************************************************************************/
157tmrHw_COUNT_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId /* [ IN ] Timer id */
158) __attribute__ ((section(".aramtext")));
159
160/****************************************************************************/
161/**
162* @brief Gets timer count rate
163*
164* This function returns the number of counts per second
165*
166* @return Count rate
167*
168*/
169/****************************************************************************/
170tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId /* [ IN ] Timer id */
171) __attribute__ ((section(".aramtext")));
172
173/****************************************************************************/
174/**
175* @brief Enables timer interrupt
176*
177* This function enables the timer interrupt
178*
179* @return N/A
180*
181*/
182/****************************************************************************/
183void tmrHw_enableInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */
184);
185
186/****************************************************************************/
187/**
188* @brief Disables timer interrupt
189*
190* This function disable the timer interrupt
191*
192* @return N/A
193*/
194/****************************************************************************/
195void tmrHw_disableInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */
196);
197
198/****************************************************************************/
199/**
200* @brief Clears the interrupt
201*
202* This function clears the timer interrupt
203*
204* @return N/A
205*
206* @note
207* Must be called under the context of ISR
208*/
209/****************************************************************************/
210void tmrHw_clearInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */
211);
212
213/****************************************************************************/
214/**
215* @brief Gets the interrupt status
216*
217* This function returns timer interrupt status
218*
219* @return Interrupt status
220*/
221/****************************************************************************/
222tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId /* [ IN ] Timer id */
223);
224
225/****************************************************************************/
226/**
227* @brief Indentifies a timer causing interrupt
228*
229* This functions returns a timer causing interrupt
230*
231* @return 0xFFFFFFFF : No timer causing an interrupt
232* ! 0xFFFFFFFF : timer causing an interrupt
233* @note
234* tmrHw_clearIntrrupt() must be called with a valid timer id after calling this function
235*/
236/****************************************************************************/
237tmrHw_ID_t tmrHw_getInterruptSource(void);
238
239/****************************************************************************/
240/**
241* @brief Displays specific timer registers
242*
243*
244* @return void
245*
246*/
247/****************************************************************************/
248void tmrHw_printDebugInfo(tmrHw_ID_t timerId, /* [ IN ] Timer id */
249 int (*fpPrint) (const char *, ...) /* [ IN ] Print callback function */
250);
251
252/****************************************************************************/
253/**
254* @brief Use a timer to perform a busy wait delay for a number of usecs.
255*
256* @return N/A
257*/
258/****************************************************************************/
259void tmrHw_udelay(tmrHw_ID_t timerId, /* [ IN ] Timer id */
260 unsigned long usecs /* [ IN ] usec to delay */
261) __attribute__ ((section(".aramtext")));
262
263#endif /* _TMRHW_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
deleted file mode 100644
index 3080ac7239a1..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
+++ /dev/null
@@ -1,82 +0,0 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file tmrHw_reg.h
18*
19* @brief Definitions for low level Timer registers
20*
21*/
22/****************************************************************************/
23#ifndef _TMRHW_REG_H
24#define _TMRHW_REG_H
25
26#include <mach/csp/mm_io.h>
27#include <mach/csp/hw_cfg.h>
28/* Base address */
29#define tmrHw_MODULE_BASE_ADDR MM_IO_BASE_TMR
30
31/*
32This platform has four different timers running at different clock speed
33
34Timer one (Timer ID 0) runs at 25 MHz
35Timer two (Timer ID 1) runs at 25 MHz
36Timer three (Timer ID 2) runs at 150 MHz
37Timer four (Timer ID 3) runs at 150 MHz
38*/
39#define tmrHw_LOW_FREQUENCY_MHZ 25 /* Always 25MHz from XTAL */
40#define tmrHw_LOW_FREQUENCY_HZ 25000000
41
42#if defined(CFG_GLOBAL_CHIP) && (CFG_GLOBAL_CHIP == FPGA11107)
43#define tmrHw_HIGH_FREQUENCY_MHZ 150 /* Always 150MHz for FPGA */
44#define tmrHw_HIGH_FREQUENCY_HZ 150000000
45#else
46#define tmrHw_HIGH_FREQUENCY_HZ HW_CFG_BUS_CLK_HZ
47#define tmrHw_HIGH_FREQUENCY_MHZ (HW_CFG_BUS_CLK_HZ / 1000000)
48#endif
49
50#define tmrHw_LOW_RESOLUTION_CLOCK tmrHw_LOW_FREQUENCY_HZ
51#define tmrHw_HIGH_RESOLUTION_CLOCK tmrHw_HIGH_FREQUENCY_HZ
52#define tmrHw_MAX_COUNT (0xFFFFFFFF) /* maximum number of count a timer can count */
53#define tmrHw_TIMER_NUM_COUNT (4) /* Number of timer module supported */
54
55typedef struct {
56 uint32_t LoadValue; /* Load value for timer */
57 uint32_t CurrentValue; /* Current value for timer */
58 uint32_t Control; /* Control register */
59 uint32_t InterruptClear; /* Interrupt clear register */
60 uint32_t RawInterruptStatus; /* Raw interrupt status */
61 uint32_t InterruptStatus; /* Masked interrupt status */
62 uint32_t BackgroundLoad; /* Background load value */
63 uint32_t padding; /* Padding register */
64} tmrHw_REG_t;
65
66/* Control bot masks */
67#define tmrHw_CONTROL_TIMER_ENABLE 0x00000080
68#define tmrHw_CONTROL_PERIODIC 0x00000040
69#define tmrHw_CONTROL_INTERRUPT_ENABLE 0x00000020
70#define tmrHw_CONTROL_PRESCALE_MASK 0x0000000C
71#define tmrHw_CONTROL_PRESCALE_1 0x00000000
72#define tmrHw_CONTROL_PRESCALE_16 0x00000004
73#define tmrHw_CONTROL_PRESCALE_256 0x00000008
74#define tmrHw_CONTROL_32BIT 0x00000002
75#define tmrHw_CONTROL_ONESHOT 0x00000001
76#define tmrHw_CONTROL_FREE_RUNNING 0x00000000
77
78#define tmrHw_CONTROL_MODE_MASK (tmrHw_CONTROL_PERIODIC | tmrHw_CONTROL_ONESHOT)
79
80#define pTmrHw ((volatile tmrHw_REG_t *)tmrHw_MODULE_BASE_ADDR)
81
82#endif /* _TMRHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/dma.h b/arch/arm/mach-bcmring/include/mach/dma.h
deleted file mode 100644
index 13e01384d6fc..000000000000
--- a/arch/arm/mach-bcmring/include/mach/dma.h
+++ /dev/null
@@ -1,630 +0,0 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file dma.h
18*
19* @brief API definitions for the linux DMA interface.
20*/
21/****************************************************************************/
22
23#if !defined(ASM_ARM_ARCH_BCMRING_DMA_H)
24#define ASM_ARM_ARCH_BCMRING_DMA_H
25
26/* ---- Include Files ---------------------------------------------------- */
27
28#include <linux/kernel.h>
29#include <linux/semaphore.h>
30#include <mach/csp/dmacHw.h>
31#include <mach/timer.h>
32
33/* ---- Constants and Types ---------------------------------------------- */
34
35/* If DMA_DEBUG_TRACK_RESERVATION is set to a non-zero value, then the filename */
36/* and line number of the reservation request will be recorded in the channel table */
37
38#define DMA_DEBUG_TRACK_RESERVATION 1
39
40#define DMA_NUM_CONTROLLERS 2
41#define DMA_NUM_CHANNELS 8 /* per controller */
42
43typedef enum {
44 DMA_DEVICE_MEM_TO_MEM, /* For memory to memory transfers */
45 DMA_DEVICE_I2S0_DEV_TO_MEM,
46 DMA_DEVICE_I2S0_MEM_TO_DEV,
47 DMA_DEVICE_I2S1_DEV_TO_MEM,
48 DMA_DEVICE_I2S1_MEM_TO_DEV,
49 DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM,
50 DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV,
51 DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM,
52 DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV,
53 DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM, /* Additional mic input for beam-forming */
54 DMA_DEVICE_APM_PCM0_DEV_TO_MEM,
55 DMA_DEVICE_APM_PCM0_MEM_TO_DEV,
56 DMA_DEVICE_APM_PCM1_DEV_TO_MEM,
57 DMA_DEVICE_APM_PCM1_MEM_TO_DEV,
58 DMA_DEVICE_SPUM_DEV_TO_MEM,
59 DMA_DEVICE_SPUM_MEM_TO_DEV,
60 DMA_DEVICE_SPIH_DEV_TO_MEM,
61 DMA_DEVICE_SPIH_MEM_TO_DEV,
62 DMA_DEVICE_UART_A_DEV_TO_MEM,
63 DMA_DEVICE_UART_A_MEM_TO_DEV,
64 DMA_DEVICE_UART_B_DEV_TO_MEM,
65 DMA_DEVICE_UART_B_MEM_TO_DEV,
66 DMA_DEVICE_PIF_MEM_TO_DEV,
67 DMA_DEVICE_PIF_DEV_TO_MEM,
68 DMA_DEVICE_ESW_DEV_TO_MEM,
69 DMA_DEVICE_ESW_MEM_TO_DEV,
70 DMA_DEVICE_VPM_MEM_TO_MEM,
71 DMA_DEVICE_CLCD_MEM_TO_MEM,
72 DMA_DEVICE_NAND_MEM_TO_MEM,
73 DMA_DEVICE_MEM_TO_VRAM,
74 DMA_DEVICE_VRAM_TO_MEM,
75
76 /* Add new entries before this line. */
77
78 DMA_NUM_DEVICE_ENTRIES,
79 DMA_DEVICE_NONE = 0xff, /* Special value to indicate that no device is currently assigned. */
80
81} DMA_Device_t;
82
83/****************************************************************************
84*
85* The DMA_Handle_t is the primary object used by callers of the API.
86*
87*****************************************************************************/
88
89#define DMA_INVALID_HANDLE ((DMA_Handle_t) -1)
90
91typedef int DMA_Handle_t;
92
93/****************************************************************************
94*
95* The DMA_DescriptorRing_t contains a ring of descriptors which is used
96* to point to regions of memory.
97*
98*****************************************************************************/
99
100typedef struct {
101 void *virtAddr; /* Virtual Address of the descriptor ring */
102 dma_addr_t physAddr; /* Physical address of the descriptor ring */
103 int descriptorsAllocated; /* Number of descriptors allocated in the descriptor ring */
104 size_t bytesAllocated; /* Number of bytes allocated in the descriptor ring */
105
106} DMA_DescriptorRing_t;
107
108/****************************************************************************
109*
110* The DMA_DeviceAttribute_t contains information which describes a
111* particular DMA device (or peripheral).
112*
113* It is anticipated that the arrary of DMA_DeviceAttribute_t's will be
114* statically initialized.
115*
116*****************************************************************************/
117
118/* The device handler is called whenever a DMA operation completes. The reaon */
119/* for it to be called will be a bitmask with one or more of the following bits */
120/* set. */
121
122#define DMA_HANDLER_REASON_BLOCK_COMPLETE dmacHw_INTERRUPT_STATUS_BLOCK
123#define DMA_HANDLER_REASON_TRANSFER_COMPLETE dmacHw_INTERRUPT_STATUS_TRANS
124#define DMA_HANDLER_REASON_ERROR dmacHw_INTERRUPT_STATUS_ERROR
125
126typedef void (*DMA_DeviceHandler_t) (DMA_Device_t dev, int reason,
127 void *userData);
128
129#define DMA_DEVICE_FLAG_ON_DMA0 0x00000001
130#define DMA_DEVICE_FLAG_ON_DMA1 0x00000002
131#define DMA_DEVICE_FLAG_PORT_PER_DMAC 0x00000004 /* If set, it means that the port used on DMAC0 is different from the port used on DMAC1 */
132#define DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST 0x00000008 /* If set, allocate from DMA1 before allocating from DMA0 */
133#define DMA_DEVICE_FLAG_IS_DEDICATED 0x00000100
134#define DMA_DEVICE_FLAG_NO_ISR 0x00000200
135#define DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO 0x00000400
136#define DMA_DEVICE_FLAG_IN_USE 0x00000800 /* If set, device is in use on a channel */
137
138/* Note: Some DMA devices can be used from multiple DMA Controllers. The bitmask is used to */
139/* determine which DMA controllers a given device can be used from, and the interface */
140/* array determeines the actual interface number to use for a given controller. */
141
142typedef struct {
143 uint32_t flags; /* Bitmask of DMA_DEVICE_FLAG_xxx constants */
144 uint8_t dedicatedController; /* Controller number to use if DMA_DEVICE_FLAG_IS_DEDICATED is set. */
145 uint8_t dedicatedChannel; /* Channel number to use if DMA_DEVICE_FLAG_IS_DEDICATED is set. */
146 const char *name; /* Will show up in the /proc entry */
147
148 uint32_t dmacPort[DMA_NUM_CONTROLLERS]; /* Specifies the port number when DMA_DEVICE_FLAG_PORT_PER_DMAC flag is set */
149
150 dmacHw_CONFIG_t config; /* Configuration to use when DMA'ing using this device */
151
152 void *userData; /* Passed to the devHandler */
153 DMA_DeviceHandler_t devHandler; /* Called when DMA operations finish. */
154
155 timer_tick_count_t transferStartTime; /* Time the current transfer was started */
156
157 /* The following statistical information will be collected and presented in a proc entry. */
158 /* Note: With a contiuous bandwidth of 1 Gb/sec, it would take 584 years to overflow */
159 /* a 64 bit counter. */
160
161 uint64_t numTransfers; /* Number of DMA transfers performed */
162 uint64_t transferTicks; /* Total time spent doing DMA transfers (measured in timer_tick_count_t's) */
163 uint64_t transferBytes; /* Total bytes transferred */
164 uint32_t timesBlocked; /* Number of times a channel was unavailable */
165 uint32_t numBytes; /* Last transfer size */
166
167 /* It's not possible to free memory which is allocated for the descriptors from within */
168 /* the ISR. So make the presumption that a given device will tend to use the */
169 /* same sized buffers over and over again, and we keep them around. */
170
171 DMA_DescriptorRing_t ring; /* Ring of descriptors allocated for this device */
172
173 /* We stash away some of the information from the previous transfer. If back-to-back */
174 /* transfers are performed from the same buffer, then we don't have to keep re-initializing */
175 /* the descriptor buffers. */
176
177 uint32_t prevNumBytes;
178 dma_addr_t prevSrcData;
179 dma_addr_t prevDstData;
180
181} DMA_DeviceAttribute_t;
182
183/****************************************************************************
184*
185* DMA_Channel_t, DMA_Controller_t, and DMA_State_t are really internal
186* data structures and don't belong in this header file, but are included
187* merely for discussion.
188*
189* By the time this is implemented, these structures will be moved out into
190* the appropriate C source file instead.
191*
192*****************************************************************************/
193
194/****************************************************************************
195*
196* The DMA_Channel_t contains state information about each DMA channel. Some
197* of the channels are dedicated. Non-dedicated channels are shared
198* amongst the other devices.
199*
200*****************************************************************************/
201
202#define DMA_CHANNEL_FLAG_IN_USE 0x00000001
203#define DMA_CHANNEL_FLAG_IS_DEDICATED 0x00000002
204#define DMA_CHANNEL_FLAG_NO_ISR 0x00000004
205#define DMA_CHANNEL_FLAG_LARGE_FIFO 0x00000008
206
207typedef struct {
208 uint32_t flags; /* bitmask of DMA_CHANNEL_FLAG_xxx constants */
209 DMA_Device_t devType; /* Device this channel is currently reserved for */
210 DMA_Device_t lastDevType; /* Device type that used this previously */
211 char name[20]; /* Name passed onto request_irq */
212
213#if (DMA_DEBUG_TRACK_RESERVATION)
214 const char *fileName; /* Place where channel reservation took place */
215 int lineNum; /* Place where channel reservation took place */
216#endif
217 dmacHw_HANDLE_t dmacHwHandle; /* low level channel handle. */
218
219} DMA_Channel_t;
220
221/****************************************************************************
222*
223* The DMA_Controller_t contains state information about each DMA controller.
224*
225* The freeChannelQ is stored in the controller data structure rather than
226* the channel data structure since several of the devices are accessible
227* from multiple controllers, and there is no way to know which controller
228* will become available first.
229*
230*****************************************************************************/
231
232typedef struct {
233 DMA_Channel_t channel[DMA_NUM_CHANNELS];
234
235} DMA_Controller_t;
236
237/****************************************************************************
238*
239* The DMA_Global_t contains all of the global state information used by
240* the DMA code.
241*
242* Callers which need to allocate a shared channel will be queued up
243* on the freeChannelQ until a channel becomes available.
244*
245*****************************************************************************/
246
247typedef struct {
248 struct semaphore lock; /* acquired when manipulating table entries */
249 wait_queue_head_t freeChannelQ;
250
251 DMA_Controller_t controller[DMA_NUM_CONTROLLERS];
252
253} DMA_Global_t;
254
255/* ---- Variable Externs ------------------------------------------------- */
256
257extern DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES];
258
259/* ---- Function Prototypes ---------------------------------------------- */
260
261#if defined(__KERNEL__)
262
263/****************************************************************************/
264/**
265* Initializes the DMA module.
266*
267* @return
268* 0 - Success
269* < 0 - Error
270*/
271/****************************************************************************/
272
273int dma_init(void);
274
275#if (DMA_DEBUG_TRACK_RESERVATION)
276DMA_Handle_t dma_request_channel_dbg(DMA_Device_t dev, const char *fileName,
277 int lineNum);
278#define dma_request_channel(dev) dma_request_channel_dbg(dev, __FILE__, __LINE__)
279#else
280
281/****************************************************************************/
282/**
283* Reserves a channel for use with @a dev. If the device is setup to use
284* a shared channel, then this function will block until a free channel
285* becomes available.
286*
287* @return
288* >= 0 - A valid DMA Handle.
289* -EBUSY - Device is currently being used.
290* -ENODEV - Device handed in is invalid.
291*/
292/****************************************************************************/
293
294DMA_Handle_t dma_request_channel(DMA_Device_t dev /* Device to use with the allocated channel. */
295 );
296#endif
297
298/****************************************************************************/
299/**
300* Frees a previously allocated DMA Handle.
301*
302* @return
303* 0 - DMA Handle was released successfully.
304* -EINVAL - Invalid DMA handle
305*/
306/****************************************************************************/
307
308int dma_free_channel(DMA_Handle_t channel /* DMA handle. */
309 );
310
311/****************************************************************************/
312/**
313* Determines if a given device has been configured as using a shared
314* channel.
315*
316* @return boolean
317* 0 Device uses a dedicated channel
318* non-zero Device uses a shared channel
319*/
320/****************************************************************************/
321
322int dma_device_is_channel_shared(DMA_Device_t dev /* Device to check. */
323 );
324
325/****************************************************************************/
326/**
327* Allocates memory to hold a descriptor ring. The descriptor ring then
328* needs to be populated by making one or more calls to
329* dna_add_descriptors.
330*
331* The returned descriptor ring will be automatically initialized.
332*
333* @return
334* 0 Descriptor ring was allocated successfully
335* -ENOMEM Unable to allocate memory for the desired number of descriptors.
336*/
337/****************************************************************************/
338
339int dma_alloc_descriptor_ring(DMA_DescriptorRing_t *ring, /* Descriptor ring to populate */
340 int numDescriptors /* Number of descriptors that need to be allocated. */
341 );
342
343/****************************************************************************/
344/**
345* Releases the memory which was previously allocated for a descriptor ring.
346*/
347/****************************************************************************/
348
349void dma_free_descriptor_ring(DMA_DescriptorRing_t *ring /* Descriptor to release */
350 );
351
352/****************************************************************************/
353/**
354* Initializes a descriptor ring, so that descriptors can be added to it.
355* Once a descriptor ring has been allocated, it may be reinitialized for
356* use with additional/different regions of memory.
357*
358* Note that if 7 descriptors are allocated, it's perfectly acceptable to
359* initialize the ring with a smaller number of descriptors. The amount
360* of memory allocated for the descriptor ring will not be reduced, and
361* the descriptor ring may be reinitialized later
362*
363* @return
364* 0 Descriptor ring was initialized successfully
365* -ENOMEM The descriptor which was passed in has insufficient space
366* to hold the desired number of descriptors.
367*/
368/****************************************************************************/
369
370int dma_init_descriptor_ring(DMA_DescriptorRing_t *ring, /* Descriptor ring to initialize */
371 int numDescriptors /* Number of descriptors to initialize. */
372 );
373
374/****************************************************************************/
375/**
376* Determines the number of descriptors which would be required for a
377* transfer of the indicated memory region.
378*
379* This function also needs to know which DMA device this transfer will
380* be destined for, so that the appropriate DMA configuration can be retrieved.
381* DMA parameters such as transfer width, and whether this is a memory-to-memory
382* or memory-to-peripheral, etc can all affect the actual number of descriptors
383* required.
384*
385* @return
386* > 0 Returns the number of descriptors required for the indicated transfer
387* -EINVAL Invalid device type for this kind of transfer
388* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
389* -ENOMEM Memory exhausted
390*/
391/****************************************************************************/
392
393int dma_calculate_descriptor_count(DMA_Device_t device, /* DMA Device that this will be associated with */
394 dma_addr_t srcData, /* Place to get data to write to device */
395 dma_addr_t dstData, /* Pointer to device data address */
396 size_t numBytes /* Number of bytes to transfer to the device */
397 );
398
399/****************************************************************************/
400/**
401* Adds a region of memory to the descriptor ring. Note that it may take
402* multiple descriptors for each region of memory. It is the callers
403* responsibility to allocate a sufficiently large descriptor ring.
404*
405* @return
406* 0 Descriptors were added successfully
407* -EINVAL Invalid device type for this kind of transfer
408* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
409* -ENOMEM Memory exhausted
410*/
411/****************************************************************************/
412
413int dma_add_descriptors(DMA_DescriptorRing_t *ring, /* Descriptor ring to add descriptors to */
414 DMA_Device_t device, /* DMA Device that descriptors are for */
415 dma_addr_t srcData, /* Place to get data (memory or device) */
416 dma_addr_t dstData, /* Place to put data (memory or device) */
417 size_t numBytes /* Number of bytes to transfer to the device */
418 );
419
420/****************************************************************************/
421/**
422* Sets the descriptor ring associated with a device.
423*
424* Once set, the descriptor ring will be associated with the device, even
425* across channel request/free calls. Passing in a NULL descriptor ring
426* will release any descriptor ring currently associated with the device.
427*
428* Note: If you call dma_transfer, or one of the other dma_alloc_ functions
429* the descriptor ring may be released and reallocated.
430*
431* Note: This function will release the descriptor memory for any current
432* descriptor ring associated with this device.
433*/
434/****************************************************************************/
435
436int dma_set_device_descriptor_ring(DMA_Device_t device, /* Device to update the descriptor ring for. */
437 DMA_DescriptorRing_t *ring /* Descriptor ring to add descriptors to */
438 );
439
440/****************************************************************************/
441/**
442* Retrieves the descriptor ring associated with a device.
443*/
444/****************************************************************************/
445
446int dma_get_device_descriptor_ring(DMA_Device_t device, /* Device to retrieve the descriptor ring for. */
447 DMA_DescriptorRing_t *ring /* Place to store retrieved ring */
448 );
449
450/****************************************************************************/
451/**
452* Allocates buffers for the descriptors. This is normally done automatically
453* but needs to be done explicitly when initiating a dma from interrupt
454* context.
455*
456* @return
457* 0 Descriptors were allocated successfully
458* -EINVAL Invalid device type for this kind of transfer
459* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
460* -ENOMEM Memory exhausted
461*/
462/****************************************************************************/
463
464int dma_alloc_descriptors(DMA_Handle_t handle, /* DMA Handle */
465 dmacHw_TRANSFER_TYPE_e transferType, /* Type of transfer being performed */
466 dma_addr_t srcData, /* Place to get data to write to device */
467 dma_addr_t dstData, /* Pointer to device data address */
468 size_t numBytes /* Number of bytes to transfer to the device */
469 );
470
471/****************************************************************************/
472/**
473* Allocates and sets up descriptors for a double buffered circular buffer.
474*
475* This is primarily intended to be used for things like the ingress samples
476* from a microphone.
477*
478* @return
479* > 0 Number of descriptors actually allocated.
480* -EINVAL Invalid device type for this kind of transfer
481* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
482* -ENOMEM Memory exhausted
483*/
484/****************************************************************************/
485
486int dma_alloc_double_dst_descriptors(DMA_Handle_t handle, /* DMA Handle */
487 dma_addr_t srcData, /* Physical address of source data */
488 dma_addr_t dstData1, /* Physical address of first destination buffer */
489 dma_addr_t dstData2, /* Physical address of second destination buffer */
490 size_t numBytes /* Number of bytes in each destination buffer */
491 );
492
493/****************************************************************************/
494/**
495* Initiates a transfer when the descriptors have already been setup.
496*
497* This is a special case, and normally, the dma_transfer_xxx functions should
498* be used.
499*
500* @return
501* 0 Transfer was started successfully
502* -ENODEV Invalid handle
503*/
504/****************************************************************************/
505
506int dma_start_transfer(DMA_Handle_t handle);
507
508/****************************************************************************/
509/**
510* Stops a previously started DMA transfer.
511*
512* @return
513* 0 Transfer was stopped successfully
514* -ENODEV Invalid handle
515*/
516/****************************************************************************/
517
518int dma_stop_transfer(DMA_Handle_t handle);
519
520/****************************************************************************/
521/**
522* Waits for a DMA to complete by polling. This function is only intended
523* to be used for testing. Interrupts should be used for most DMA operations.
524*/
525/****************************************************************************/
526
527int dma_wait_transfer_done(DMA_Handle_t handle);
528
529/****************************************************************************/
530/**
531* Initiates a DMA transfer
532*
533* @return
534* 0 Transfer was started successfully
535* -EINVAL Invalid device type for this kind of transfer
536* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
537*/
538/****************************************************************************/
539
540int dma_transfer(DMA_Handle_t handle, /* DMA Handle */
541 dmacHw_TRANSFER_TYPE_e transferType, /* Type of transfer being performed */
542 dma_addr_t srcData, /* Place to get data to write to device */
543 dma_addr_t dstData, /* Pointer to device data address */
544 size_t numBytes /* Number of bytes to transfer to the device */
545 );
546
547/****************************************************************************/
548/**
549* Initiates a transfer from memory to a device.
550*
551* @return
552* 0 Transfer was started successfully
553* -EINVAL Invalid device type for this kind of transfer
554* (i.e. the device is _DEV_TO_MEM and not _MEM_TO_DEV)
555*/
556/****************************************************************************/
557
558static inline int dma_transfer_to_device(DMA_Handle_t handle, /* DMA Handle */
559 dma_addr_t srcData, /* Place to get data to write to device (physical address) */
560 dma_addr_t dstData, /* Pointer to device data address (physical address) */
561 size_t numBytes /* Number of bytes to transfer to the device */
562 ) {
563 return dma_transfer(handle,
564 dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
565 srcData, dstData, numBytes);
566}
567
568/****************************************************************************/
569/**
570* Initiates a transfer from a device to memory.
571*
572* @return
573* 0 Transfer was started successfully
574* -EINVAL Invalid device type for this kind of transfer
575* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
576*/
577/****************************************************************************/
578
579static inline int dma_transfer_from_device(DMA_Handle_t handle, /* DMA Handle */
580 dma_addr_t srcData, /* Pointer to the device data address (physical address) */
581 dma_addr_t dstData, /* Place to store data retrieved from the device (physical address) */
582 size_t numBytes /* Number of bytes to retrieve from the device */
583 ) {
584 return dma_transfer(handle,
585 dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
586 srcData, dstData, numBytes);
587}
588
589/****************************************************************************/
590/**
591* Initiates a memory to memory transfer.
592*
593* @return
594* 0 Transfer was started successfully
595* -EINVAL Invalid device type for this kind of transfer
596* (i.e. the device wasn't DMA_DEVICE_MEM_TO_MEM)
597*/
598/****************************************************************************/
599
600static inline int dma_transfer_mem_to_mem(DMA_Handle_t handle, /* DMA Handle */
601 dma_addr_t srcData, /* Place to transfer data from (physical address) */
602 dma_addr_t dstData, /* Place to transfer data to (physical address) */
603 size_t numBytes /* Number of bytes to transfer */
604 ) {
605 return dma_transfer(handle,
606 dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
607 srcData, dstData, numBytes);
608}
609
610/****************************************************************************/
611/**
612* Set the callback function which will be called when a transfer completes.
613* If a NULL callback function is set, then no callback will occur.
614*
615* @note @a devHandler will be called from IRQ context.
616*
617* @return
618* 0 - Success
619* -ENODEV - Device handed in is invalid.
620*/
621/****************************************************************************/
622
623int dma_set_device_handler(DMA_Device_t dev, /* Device to set the callback for. */
624 DMA_DeviceHandler_t devHandler, /* Function to call when the DMA completes */
625 void *userData /* Pointer which will be passed to devHandler. */
626 );
627
628#endif
629
630#endif /* ASM_ARM_ARCH_BCMRING_DMA_H */
diff --git a/arch/arm/mach-bcmring/include/mach/entry-macro.S b/arch/arm/mach-bcmring/include/mach/entry-macro.S
deleted file mode 100644
index 2f316f0e6e69..000000000000
--- a/arch/arm/mach-bcmring/include/mach/entry-macro.S
+++ /dev/null
@@ -1,76 +0,0 @@
1/*****************************************************************************
2* Copyright 2006 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/*
16 *
17 * Low-level IRQ helper macros for BCMRing-based platforms
18 *
19 */
20#include <mach/irqs.h>
21#include <mach/hardware.h>
22#include <mach/csp/mm_io.h>
23
24 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
25 ldr \base, =(MM_IO_BASE_INTC0)
26 ldr \irqstat, [\base, #0] @ get status
27 ldr \irqnr, [\base, #0x10] @ mask with enable register
28 ands \irqstat, \irqstat, \irqnr
29 mov \irqnr, #IRQ_INTC0_START
30 cmp \irqstat, #0
31 bne 1001f
32
33 ldr \base, =(MM_IO_BASE_INTC1)
34 ldr \irqstat, [\base, #0] @ get status
35 ldr \irqnr, [\base, #0x10] @ mask with enable register
36 ands \irqstat, \irqstat, \irqnr
37 mov \irqnr, #IRQ_INTC1_START
38 cmp \irqstat, #0
39 bne 1001f
40
41 ldr \base, =(MM_IO_BASE_SINTC)
42 ldr \irqstat, [\base, #0] @ get status
43 ldr \irqnr, [\base, #0x10] @ mask with enable register
44 ands \irqstat, \irqstat, \irqnr
45 mov \irqnr, #0xffffffff @ code meaning no interrupt bits set
46 cmp \irqstat, #0
47 beq 1002f
48
49 mov \irqnr, #IRQ_SINTC_START @ something is set, so fixup return value
50
511001:
52 movs \tmp, \irqstat, lsl #16
53 movne \irqstat, \tmp
54 addeq \irqnr, \irqnr, #16
55
56 movs \tmp, \irqstat, lsl #8
57 movne \irqstat, \tmp
58 addeq \irqnr, \irqnr, #8
59
60 movs \tmp, \irqstat, lsl #4
61 movne \irqstat, \tmp
62 addeq \irqnr, \irqnr, #4
63
64 movs \tmp, \irqstat, lsl #2
65 movne \irqstat, \tmp
66 addeq \irqnr, \irqnr, #2
67
68 movs \tmp, \irqstat, lsl #1
69 addeq \irqnr, \irqnr, #1
70 orrs \base, \base, #1
71
721002: @ irqnr will be set to 0xffffffff if no irq bits are set
73 .endm
74
75 .macro get_irqnr_preamble, base, tmp
76 .endm
diff --git a/arch/arm/mach-bcmring/include/mach/hardware.h b/arch/arm/mach-bcmring/include/mach/hardware.h
deleted file mode 100644
index a0c92b4b8c60..000000000000
--- a/arch/arm/mach-bcmring/include/mach/hardware.h
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 *
3 * This file contains the hardware definitions of the BCMRing.
4 *
5 * Copyright (C) 1999 ARM Limited.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef __ASM_ARCH_HARDWARE_H
22#define __ASM_ARCH_HARDWARE_H
23
24#include <asm/sizes.h>
25#include <mach/cfg_global.h>
26#include <mach/csp/mm_io.h>
27
28/* Hardware addresses of major areas.
29 * *_START is the physical address
30 * *_SIZE is the size of the region
31 * *_BASE is the virtual address
32 */
33#define RAM_START PHYS_OFFSET
34
35#define RAM_SIZE (CFG_GLOBAL_RAM_SIZE-CFG_GLOBAL_RAM_SIZE_RESERVED)
36#define RAM_BASE PAGE_OFFSET
37
38/* Macros to make managing spinlocks a bit more controlled in terms of naming. */
39/* See reg_gpio.h, reg_irq.h, arch.c, gpio.c for example usage. */
40#if defined(__KERNEL__)
41#define HW_DECLARE_SPINLOCK(name) DEFINE_SPINLOCK(bcmring_##name##_reg_lock);
42#define HW_EXTERN_SPINLOCK(name) extern spinlock_t bcmring_##name##_reg_lock;
43#define HW_IRQ_SAVE(name, val) spin_lock_irqsave(&bcmring_##name##_reg_lock, (val))
44#define HW_IRQ_RESTORE(name, val) spin_unlock_irqrestore(&bcmring_##name##_reg_lock, (val))
45#else
46#define HW_DECLARE_SPINLOCK(name)
47#define HW_EXTERN_SPINLOCK(name)
48#define HW_IRQ_SAVE(name, val) {(void)(name); (void)(val); }
49#define HW_IRQ_RESTORE(name, val) {(void)(name); (void)(val); }
50#endif
51
52#ifndef HW_IO_PHYS_TO_VIRT
53#define HW_IO_PHYS_TO_VIRT MM_IO_PHYS_TO_VIRT
54#endif
55#define HW_IO_VIRT_TO_PHYS MM_IO_VIRT_TO_PHYS
56
57#endif
diff --git a/arch/arm/mach-bcmring/include/mach/irqs.h b/arch/arm/mach-bcmring/include/mach/irqs.h
deleted file mode 100644
index b279b825d4a7..000000000000
--- a/arch/arm/mach-bcmring/include/mach/irqs.h
+++ /dev/null
@@ -1,132 +0,0 @@
1/*
2 * Copyright (C) 2007 Broadcom
3 * Copyright (C) 1999 ARM Limited
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#if !defined(ARCH_BCMRING_IRQS_H)
21#define ARCH_BCMRING_IRQS_H
22
23/* INTC0 - interrupt controller 0 */
24#define IRQ_INTC0_START 0
25#define IRQ_DMA0C0 0 /* DMA0 channel 0 interrupt */
26#define IRQ_DMA0C1 1 /* DMA0 channel 1 interrupt */
27#define IRQ_DMA0C2 2 /* DMA0 channel 2 interrupt */
28#define IRQ_DMA0C3 3 /* DMA0 channel 3 interrupt */
29#define IRQ_DMA0C4 4 /* DMA0 channel 4 interrupt */
30#define IRQ_DMA0C5 5 /* DMA0 channel 5 interrupt */
31#define IRQ_DMA0C6 6 /* DMA0 channel 6 interrupt */
32#define IRQ_DMA0C7 7 /* DMA0 channel 7 interrupt */
33#define IRQ_DMA1C0 8 /* DMA1 channel 0 interrupt */
34#define IRQ_DMA1C1 9 /* DMA1 channel 1 interrupt */
35#define IRQ_DMA1C2 10 /* DMA1 channel 2 interrupt */
36#define IRQ_DMA1C3 11 /* DMA1 channel 3 interrupt */
37#define IRQ_DMA1C4 12 /* DMA1 channel 4 interrupt */
38#define IRQ_DMA1C5 13 /* DMA1 channel 5 interrupt */
39#define IRQ_DMA1C6 14 /* DMA1 channel 6 interrupt */
40#define IRQ_DMA1C7 15 /* DMA1 channel 7 interrupt */
41#define IRQ_VPM 16 /* Voice process module interrupt */
42#define IRQ_USBHD2 17 /* USB host2/device2 interrupt */
43#define IRQ_USBH1 18 /* USB1 host interrupt */
44#define IRQ_USBD 19 /* USB device interrupt */
45#define IRQ_SDIOH0 20 /* SDIO0 host interrupt */
46#define IRQ_SDIOH1 21 /* SDIO1 host interrupt */
47#define IRQ_TIMER0 22 /* Timer0 interrupt */
48#define IRQ_TIMER1 23 /* Timer1 interrupt */
49#define IRQ_TIMER2 24 /* Timer2 interrupt */
50#define IRQ_TIMER3 25 /* Timer3 interrupt */
51#define IRQ_SPIH 26 /* SPI host interrupt */
52#define IRQ_ESW 27 /* Ethernet switch interrupt */
53#define IRQ_APM 28 /* Audio process module interrupt */
54#define IRQ_GE 29 /* Graphic engine interrupt */
55#define IRQ_CLCD 30 /* LCD Controller interrupt */
56#define IRQ_PIF 31 /* Peripheral interface interrupt */
57#define IRQ_INTC0_END 31
58
59/* INTC1 - interrupt controller 1 */
60#define IRQ_INTC1_START 32
61#define IRQ_GPIO0 32 /* 0 GPIO bit 31//0 combined interrupt */
62#define IRQ_GPIO1 33 /* 1 GPIO bit 64//32 combined interrupt */
63#define IRQ_I2S0 34 /* 2 I2S0 interrupt */
64#define IRQ_I2S1 35 /* 3 I2S1 interrupt */
65#define IRQ_I2CH 36 /* 4 I2C host interrupt */
66#define IRQ_I2CS 37 /* 5 I2C slave interrupt */
67#define IRQ_SPIS 38 /* 6 SPI slave interrupt */
68#define IRQ_GPHY 39 /* 7 Gigabit Phy interrupt */
69#define IRQ_FLASHC 40 /* 8 Flash controller interrupt */
70#define IRQ_COMMTX 41 /* 9 ARM DDC transmit interrupt */
71#define IRQ_COMMRX 42 /* 10 ARM DDC receive interrupt */
72#define IRQ_PMUIRQ 43 /* 11 ARM performance monitor interrupt */
73#define IRQ_UARTB 44 /* 12 UARTB */
74#define IRQ_WATCHDOG 45 /* 13 Watchdog timer interrupt */
75#define IRQ_UARTA 46 /* 14 UARTA */
76#define IRQ_TSC 47 /* 15 Touch screen controller interrupt */
77#define IRQ_KEYC 48 /* 16 Key pad controller interrupt */
78#define IRQ_DMPU 49 /* 17 DDR2 memory partition interrupt */
79#define IRQ_VMPU 50 /* 18 VRAM memory partition interrupt */
80#define IRQ_FMPU 51 /* 19 Flash memory parition unit interrupt */
81#define IRQ_RNG 52 /* 20 Random number generator interrupt */
82#define IRQ_RTC0 53 /* 21 Real time clock periodic interrupt */
83#define IRQ_RTC1 54 /* 22 Real time clock one-shot interrupt */
84#define IRQ_SPUM 55 /* 23 Secure process module interrupt */
85#define IRQ_VDEC 56 /* 24 Hantro video decoder interrupt */
86#define IRQ_RTC2 57 /* 25 Real time clock tamper interrupt */
87#define IRQ_DDRP 58 /* 26 DDR Panic interrupt */
88#define IRQ_INTC1_END 58
89
90/* SINTC secure int controller */
91#define IRQ_SINTC_START 59
92#define IRQ_SEC_WATCHDOG 59 /* 0 Watchdog timer interrupt */
93#define IRQ_SEC_UARTA 60 /* 1 UARTA interrupt */
94#define IRQ_SEC_TSC 61 /* 2 Touch screen controller interrupt */
95#define IRQ_SEC_KEYC 62 /* 3 Key pad controller interrupt */
96#define IRQ_SEC_DMPU 63 /* 4 DDR2 memory partition interrupt */
97#define IRQ_SEC_VMPU 64 /* 5 VRAM memory partition interrupt */
98#define IRQ_SEC_FMPU 65 /* 6 Flash memory parition unit interrupt */
99#define IRQ_SEC_RNG 66 /* 7 Random number generator interrupt */
100#define IRQ_SEC_RTC0 67 /* 8 Real time clock periodic interrupt */
101#define IRQ_SEC_RTC1 68 /* 9 Real time clock one-shot interrupt */
102#define IRQ_SEC_SPUM 69 /* 10 Secure process module interrupt */
103#define IRQ_SEC_TIMER0 70 /* 11 Secure timer0 interrupt */
104#define IRQ_SEC_TIMER1 71 /* 12 Secure timer1 interrupt */
105#define IRQ_SEC_TIMER2 72 /* 13 Secure timer2 interrupt */
106#define IRQ_SEC_TIMER3 73 /* 14 Secure timer3 interrupt */
107#define IRQ_SEC_RTC2 74 /* 15 Real time clock tamper interrupt */
108
109#define IRQ_SINTC_END 74
110
111/* Note: there are 3 INTC registers of 32 bits each. So internal IRQs could go from 0-95 */
112/* Since IRQs are typically viewed in decimal, we start the gpio based IRQs off at 100 */
113/* to make the mapping easy for humans to decipher. */
114
115#define IRQ_GPIO_0 100
116
117#define NUM_INTERNAL_IRQS (IRQ_SINTC_END+1)
118
119/* I couldn't get the gpioHw_reg.h file to be included cleanly, so I hardcoded it */
120/* define NUM_GPIO_IRQS GPIOHW_TOTAL_NUM_PINS */
121#define NUM_GPIO_IRQS 62
122
123#define NR_IRQS (IRQ_GPIO_0 + NUM_GPIO_IRQS)
124
125#define IRQ_UNKNOWN -1
126
127/* Tune these bits to preclude noisy or unsupported interrupt sources as required. */
128#define IRQ_INTC0_VALID_MASK 0xffffffff
129#define IRQ_INTC1_VALID_MASK 0x07ffffff
130#define IRQ_SINTC_VALID_MASK 0x0000ffff
131
132#endif /* ARCH_BCMRING_IRQS_H */
diff --git a/arch/arm/mach-bcmring/include/mach/memory_settings.h b/arch/arm/mach-bcmring/include/mach/memory_settings.h
deleted file mode 100644
index ce5cd16f2ac4..000000000000
--- a/arch/arm/mach-bcmring/include/mach/memory_settings.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#ifndef MEMORY_SETTINGS_H
16#define MEMORY_SETTINGS_H
17
18/* ---- Include Files ---------------------------------------- */
19/* ---- Constants and Types ---------------------------------- */
20
21/* Memory devices */
22/* NAND Flash timing for 166 MHz setting */
23#define HW_CFG_NAND_tBTA (5 << 16) /* Bus turnaround cycle (n) 0-7 (30 ns) */
24#define HW_CFG_NAND_tWP (4 << 11) /* Write pulse width cycle (n+1) 0-31 (25 ns) */
25#define HW_CFG_NAND_tWR (1 << 9) /* Write recovery cycle (n+1) 0-3 (10 ns) */
26#define HW_CFG_NAND_tAS (0 << 7) /* Write address setup cycle (n+1) 0-3 ( 0 ns) */
27#define HW_CFG_NAND_tOE (3 << 5) /* Output enable delay cycle (n) 0-3 (15 ns) */
28#define HW_CFG_NAND_tRC (7 << 0) /* Read access cycle (n+2) 0-31 (50 ns) */
29
30#define HW_CFG_NAND_TCR (HW_CFG_NAND_tBTA \
31 | HW_CFG_NAND_tWP \
32 | HW_CFG_NAND_tWR \
33 | HW_CFG_NAND_tAS \
34 | HW_CFG_NAND_tOE \
35 | HW_CFG_NAND_tRC)
36
37/* NOR Flash timing for 166 MHz setting */
38#define HW_CFG_NOR_TPRC_TWLC (0 << 19) /* Page read access cycle / Burst write latency (n+2 / n+1) (max 25ns) */
39#define HW_CFG_NOR_TBTA (0 << 16) /* Bus turnaround cycle (n) (DNA) */
40#define HW_CFG_NOR_TWP (6 << 11) /* Write pulse width cycle (n+1) (35ns) */
41#define HW_CFG_NOR_TWR (0 << 9) /* Write recovery cycle (n+1) (0ns) */
42#define HW_CFG_NOR_TAS (0 << 7) /* Write address setup cycle (n+1) (0ns) */
43#define HW_CFG_NOR_TOE (0 << 5) /* Output enable delay cycle (n) (max 25ns) */
44#define HW_CFG_NOR_TRC_TLC (0x10 << 0) /* Read access cycle / Burst read latency (n+2 / n+1) (100ns) */
45
46#define HW_CFG_FLASH0_TCR (HW_CFG_NOR_TPRC_TWLC \
47 | HW_CFG_NOR_TBTA \
48 | HW_CFG_NOR_TWP \
49 | HW_CFG_NOR_TWR \
50 | HW_CFG_NOR_TAS \
51 | HW_CFG_NOR_TOE \
52 | HW_CFG_NOR_TRC_TLC)
53
54#define HW_CFG_FLASH1_TCR HW_CFG_FLASH0_TCR
55#define HW_CFG_FLASH2_TCR HW_CFG_FLASH0_TCR
56
57/* SDRAM Settings */
58/* #define HW_CFG_SDRAM_CAS_LATENCY 5 Default 5, Values [3..6] */
59/* #define HW_CFG_SDRAM_CHIP_SELECT_CNT 1 Default 1, Vaules [1..2] */
60/* #define HW_CFG_SDRAM_SPEED_GRADE 667 Default 667, Values [400,533,667,800] */
61/* #define HW_CFG_SDRAM_WIDTH_BITS 16 Default 16, Vaules [8,16] */
62#define HW_CFG_SDRAM_SIZE_BYTES 0x10000000 /* Total memory, not per device size */
63
64/* ---- Variable Externs ------------------------------------- */
65/* ---- Function Prototypes ---------------------------------- */
66
67#endif /* MEMORY_SETTINGS_H */
diff --git a/arch/arm/mach-bcmring/include/mach/reg_nand.h b/arch/arm/mach-bcmring/include/mach/reg_nand.h
deleted file mode 100644
index f8d51a8b0b15..000000000000
--- a/arch/arm/mach-bcmring/include/mach/reg_nand.h
+++ /dev/null
@@ -1,66 +0,0 @@
1/*****************************************************************************
2* Copyright 2001 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/*
16*
17*****************************************************************************
18*
19* REG_NAND.h
20*
21* PURPOSE:
22*
23* This file contains definitions for the nand registers:
24*
25* NOTES:
26*
27*****************************************************************************/
28
29#if !defined(__ASM_ARCH_REG_NAND_H)
30#define __ASM_ARCH_REG_NAND_H
31
32/* ---- Include Files ---------------------------------------------------- */
33#include <mach/csp/reg.h>
34#include <mach/reg_umi.h>
35
36/* ---- Constants and Types ---------------------------------------------- */
37
38#define HW_NAND_BASE MM_IO_BASE_NAND /* NAND Flash */
39
40/* DMA accesses by the bootstrap need hard nonvirtual addresses */
41#define REG_NAND_CMD __REG16(HW_NAND_BASE + 0)
42#define REG_NAND_ADDR __REG16(HW_NAND_BASE + 4)
43
44#define REG_NAND_PHYS_DATA16 (HW_NAND_BASE + 8)
45#define REG_NAND_PHYS_DATA8 (HW_NAND_BASE + 8)
46#define REG_NAND_DATA16 __REG16(REG_NAND_PHYS_DATA16)
47#define REG_NAND_DATA8 __REG8(REG_NAND_PHYS_DATA8)
48
49/* use appropriate offset to make sure it start at the 1K boundary */
50#define REG_NAND_PHYS_DATA_DMA (HW_NAND_BASE + 0x400)
51#define REG_NAND_DATA_DMA __REG32(REG_NAND_PHYS_DATA_DMA)
52
53/* Linux DMA requires physical address of the data register */
54#define REG_NAND_DATA16_PADDR HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA16)
55#define REG_NAND_DATA8_PADDR HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA8)
56#define REG_NAND_DATA_PADDR HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA_DMA)
57
58#define NAND_BUS_16BIT() (0)
59#define NAND_BUS_8BIT() (!NAND_BUS_16BIT())
60
61/* Register offsets */
62#define REG_NAND_CMD_OFFSET (0)
63#define REG_NAND_ADDR_OFFSET (4)
64#define REG_NAND_DATA8_OFFSET (8)
65
66#endif
diff --git a/arch/arm/mach-bcmring/include/mach/reg_umi.h b/arch/arm/mach-bcmring/include/mach/reg_umi.h
deleted file mode 100644
index 56dd9de7d83f..000000000000
--- a/arch/arm/mach-bcmring/include/mach/reg_umi.h
+++ /dev/null
@@ -1,237 +0,0 @@
1/*****************************************************************************
2* Copyright 2005 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/*
16*
17*****************************************************************************
18*
19* REG_UMI.h
20*
21* PURPOSE:
22*
23* This file contains definitions for the nand registers:
24*
25* NOTES:
26*
27*****************************************************************************/
28
29#if !defined(__ASM_ARCH_REG_UMI_H)
30#define __ASM_ARCH_REG_UMI_H
31
32/* ---- Include Files ---------------------------------------------------- */
33#include <mach/csp/reg.h>
34#include <mach/csp/mm_io.h>
35
36/* ---- Constants and Types ---------------------------------------------- */
37
38/* Unified Memory Interface Ctrl Register */
39#define HW_UMI_BASE MM_IO_BASE_UMI
40
41/* Flash bank 0 timing and control register */
42#define REG_UMI_FLASH0_TCR __REG32(HW_UMI_BASE + 0x00)
43/* Flash bank 1 timing and control register */
44#define REG_UMI_FLASH1_TCR __REG32(HW_UMI_BASE + 0x04)
45/* Flash bank 2 timing and control register */
46#define REG_UMI_FLASH2_TCR __REG32(HW_UMI_BASE + 0x08)
47/* MMD interface and control register */
48#define REG_UMI_MMD_ICR __REG32(HW_UMI_BASE + 0x0c)
49/* NAND timing and control register */
50#define REG_UMI_NAND_TCR __REG32(HW_UMI_BASE + 0x18)
51/* NAND ready/chip select register */
52#define REG_UMI_NAND_RCSR __REG32(HW_UMI_BASE + 0x1c)
53/* NAND ECC control & status register */
54#define REG_UMI_NAND_ECC_CSR __REG32(HW_UMI_BASE + 0x20)
55/* NAND ECC data register XXB2B1B0 */
56#define REG_UMI_NAND_ECC_DATA __REG32(HW_UMI_BASE + 0x24)
57/* BCH ECC Parameter N */
58#define REG_UMI_BCH_N __REG32(HW_UMI_BASE + 0x40)
59/* BCH ECC Parameter T */
60#define REG_UMI_BCH_K __REG32(HW_UMI_BASE + 0x44)
61/* BCH ECC Parameter K */
62#define REG_UMI_BCH_T __REG32(HW_UMI_BASE + 0x48)
63/* BCH ECC Contro Status */
64#define REG_UMI_BCH_CTRL_STATUS __REG32(HW_UMI_BASE + 0x4C)
65/* BCH WR ECC 31:0 */
66#define REG_UMI_BCH_WR_ECC_0 __REG32(HW_UMI_BASE + 0x50)
67/* BCH WR ECC 63:32 */
68#define REG_UMI_BCH_WR_ECC_1 __REG32(HW_UMI_BASE + 0x54)
69/* BCH WR ECC 95:64 */
70#define REG_UMI_BCH_WR_ECC_2 __REG32(HW_UMI_BASE + 0x58)
71/* BCH WR ECC 127:96 */
72#define REG_UMI_BCH_WR_ECC_3 __REG32(HW_UMI_BASE + 0x5c)
73/* BCH WR ECC 155:128 */
74#define REG_UMI_BCH_WR_ECC_4 __REG32(HW_UMI_BASE + 0x60)
75/* BCH Read Error Location 1,0 */
76#define REG_UMI_BCH_RD_ERR_LOC_1_0 __REG32(HW_UMI_BASE + 0x64)
77/* BCH Read Error Location 3,2 */
78#define REG_UMI_BCH_RD_ERR_LOC_3_2 __REG32(HW_UMI_BASE + 0x68)
79/* BCH Read Error Location 5,4 */
80#define REG_UMI_BCH_RD_ERR_LOC_5_4 __REG32(HW_UMI_BASE + 0x6c)
81/* BCH Read Error Location 7,6 */
82#define REG_UMI_BCH_RD_ERR_LOC_7_6 __REG32(HW_UMI_BASE + 0x70)
83/* BCH Read Error Location 9,8 */
84#define REG_UMI_BCH_RD_ERR_LOC_9_8 __REG32(HW_UMI_BASE + 0x74)
85/* BCH Read Error Location 11,10 */
86#define REG_UMI_BCH_RD_ERR_LOC_B_A __REG32(HW_UMI_BASE + 0x78)
87
88/* REG_UMI_FLASH0/1/2_TCR, REG_UMI_SRAM0/1_TCR bits */
89/* Enable wait pin during burst write or read */
90#define REG_UMI_TCR_WAITEN 0x80000000
91/* Enable mem ctrlr to work with ext mem of lower freq than AHB clk */
92#define REG_UMI_TCR_LOWFREQ 0x40000000
93/* 1=synch write, 0=async write */
94#define REG_UMI_TCR_MEMTYPE_SYNCWRITE 0x20000000
95/* 1=synch read, 0=async read */
96#define REG_UMI_TCR_MEMTYPE_SYNCREAD 0x10000000
97/* 1=page mode read, 0=normal mode read */
98#define REG_UMI_TCR_MEMTYPE_PAGEREAD 0x08000000
99/* page size/burst size (wrap only) */
100#define REG_UMI_TCR_MEMTYPE_PGSZ_MASK 0x07000000
101/* 4 word */
102#define REG_UMI_TCR_MEMTYPE_PGSZ_4 0x00000000
103/* 8 word */
104#define REG_UMI_TCR_MEMTYPE_PGSZ_8 0x01000000
105/* 16 word */
106#define REG_UMI_TCR_MEMTYPE_PGSZ_16 0x02000000
107/* 32 word */
108#define REG_UMI_TCR_MEMTYPE_PGSZ_32 0x03000000
109/* 64 word */
110#define REG_UMI_TCR_MEMTYPE_PGSZ_64 0x04000000
111/* 128 word */
112#define REG_UMI_TCR_MEMTYPE_PGSZ_128 0x05000000
113/* 256 word */
114#define REG_UMI_TCR_MEMTYPE_PGSZ_256 0x06000000
115/* 512 word */
116#define REG_UMI_TCR_MEMTYPE_PGSZ_512 0x07000000
117/* Page read access cycle / Burst write latency (n+2 / n+1) */
118#define REG_UMI_TCR_TPRC_TWLC_MASK 0x00f80000
119/* Bus turnaround cycle (n) */
120#define REG_UMI_TCR_TBTA_MASK 0x00070000
121/* Write pulse width cycle (n+1) */
122#define REG_UMI_TCR_TWP_MASK 0x0000f800
123/* Write recovery cycle (n+1) */
124#define REG_UMI_TCR_TWR_MASK 0x00000600
125/* Write address setup cycle (n+1) */
126#define REG_UMI_TCR_TAS_MASK 0x00000180
127/* Output enable delay cycle (n) */
128#define REG_UMI_TCR_TOE_MASK 0x00000060
129/* Read access cycle / Burst read latency (n+2 / n+1) */
130#define REG_UMI_TCR_TRC_TLC_MASK 0x0000001f
131
132/* REG_UMI_MMD_ICR bits */
133/* Flash write protection pin control */
134#define REG_UMI_MMD_ICR_FLASH_WP 0x8000
135/* Extend hold time for sram0, sram1 csn (39 MHz operation) */
136#define REG_UMI_MMD_ICR_XHCS 0x4000
137/* Enable SDRAM 2 interface control */
138#define REG_UMI_MMD_ICR_SDRAM2EN 0x2000
139/* Enable merge of flash banks 0/1 to 512 MBit bank */
140#define REG_UMI_MMD_ICR_INST512 0x1000
141/* Enable merge of flash banks 1/2 to 512 MBit bank */
142#define REG_UMI_MMD_ICR_DATA512 0x0800
143/* Enable SDRAM interface control */
144#define REG_UMI_MMD_ICR_SDRAMEN 0x0400
145/* Polarity of busy state of Burst Wait Signal */
146#define REG_UMI_MMD_ICR_WAITPOL 0x0200
147/* Enable burst clock stopped when not accessing external burst flash/sram */
148#define REG_UMI_MMD_ICR_BCLKSTOP 0x0100
149/* Enable the peri1_csn to replace flash1_csn in 512 Mb flash mode */
150#define REG_UMI_MMD_ICR_PERI1EN 0x0080
151/* Enable the peri2_csn to replace sdram_csn */
152#define REG_UMI_MMD_ICR_PERI2EN 0x0040
153/* Enable the peri3_csn to replace sdram2_csn */
154#define REG_UMI_MMD_ICR_PERI3EN 0x0020
155/* Enable sram bank1 for H/W controlled MRS */
156#define REG_UMI_MMD_ICR_MRSB1 0x0010
157/* Enable sram bank0 for H/W controlled MRS */
158#define REG_UMI_MMD_ICR_MRSB0 0x0008
159/* Polarity for assert3ed state of H/W controlled MRS */
160#define REG_UMI_MMD_ICR_MRSPOL 0x0004
161/* 0: S/W controllable ZZ/MRS/CRE/P-Mode pin */
162/* 1: H/W controlled ZZ/MRS/CRE/P-Mode, same timing as CS */
163#define REG_UMI_MMD_ICR_MRSMODE 0x0002
164/* MRS state for S/W controlled mode */
165#define REG_UMI_MMD_ICR_MRSSTATE 0x0001
166
167/* REG_UMI_NAND_TCR bits */
168/* Enable software to control CS */
169#define REG_UMI_NAND_TCR_CS_SWCTRL 0x80000000
170/* 16-bit nand wordsize if set */
171#define REG_UMI_NAND_TCR_WORD16 0x40000000
172/* Bus turnaround cycle (n) */
173#define REG_UMI_NAND_TCR_TBTA_MASK 0x00070000
174/* Write pulse width cycle (n+1) */
175#define REG_UMI_NAND_TCR_TWP_MASK 0x0000f800
176/* Write recovery cycle (n+1) */
177#define REG_UMI_NAND_TCR_TWR_MASK 0x00000600
178/* Write address setup cycle (n+1) */
179#define REG_UMI_NAND_TCR_TAS_MASK 0x00000180
180/* Output enable delay cycle (n) */
181#define REG_UMI_NAND_TCR_TOE_MASK 0x00000060
182/* Read access cycle (n+2) */
183#define REG_UMI_NAND_TCR_TRC_TLC_MASK 0x0000001f
184
185/* REG_UMI_NAND_RCSR bits */
186/* Status: Ready=1, Busy=0 */
187#define REG_UMI_NAND_RCSR_RDY 0x02
188/* Keep CS asserted during operation */
189#define REG_UMI_NAND_RCSR_CS_ASSERTED 0x01
190
191/* REG_UMI_NAND_ECC_CSR bits */
192/* Interrupt status - read-only */
193#define REG_UMI_NAND_ECC_CSR_NANDINT 0x80000000
194/* Read: Status of ECC done, Write: clear ECC interrupt */
195#define REG_UMI_NAND_ECC_CSR_ECCINT_RAW 0x00800000
196/* Read: Status of R/B, Write: clear R/B interrupt */
197#define REG_UMI_NAND_ECC_CSR_RBINT_RAW 0x00400000
198/* 1 = Enable ECC Interrupt */
199#define REG_UMI_NAND_ECC_CSR_ECCINT_ENABLE 0x00008000
200/* 1 = Assert interrupt at rising edge of R/B_ */
201#define REG_UMI_NAND_ECC_CSR_RBINT_ENABLE 0x00004000
202/* Calculate ECC by 0=512 bytes, 1=256 bytes */
203#define REG_UMI_NAND_ECC_CSR_256BYTE 0x00000080
204/* Enable ECC in hardware */
205#define REG_UMI_NAND_ECC_CSR_ECC_ENABLE 0x00000001
206
207/* REG_UMI_BCH_CTRL_STATUS bits */
208/* Shift to Indicate Number of correctable errors detected */
209#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR_SHIFT 20
210/* Indicate Number of correctable errors detected */
211#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR 0x00F00000
212/* Indicate Errors detected during read but uncorrectable */
213#define REG_UMI_BCH_CTRL_STATUS_UNCORR_ERR 0x00080000
214/* Indicate Errors detected during read and are correctable */
215#define REG_UMI_BCH_CTRL_STATUS_CORR_ERR 0x00040000
216/* Flag indicates BCH's ECC status of read process are valid */
217#define REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID 0x00020000
218/* Flag indicates BCH's ECC status of write process are valid */
219#define REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID 0x00010000
220/* Pause ECC calculation */
221#define REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC 0x00000010
222/* Enable Interrupt */
223#define REG_UMI_BCH_CTRL_STATUS_INT_EN 0x00000004
224/* Enable ECC during read */
225#define REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN 0x00000002
226/* Enable ECC during write */
227#define REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN 0x00000001
228/* Mask for location */
229#define REG_UMI_BCH_ERR_LOC_MASK 0x00001FFF
230/* location within a byte */
231#define REG_UMI_BCH_ERR_LOC_BYTE 0x00000007
232/* location within a word */
233#define REG_UMI_BCH_ERR_LOC_WORD 0x00000018
234/* location within a page (512 byte) */
235#define REG_UMI_BCH_ERR_LOC_PAGE 0x00001FE0
236#define REG_UMI_BCH_ERR_LOC_ADDR(index) (readl(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16))
237#endif
diff --git a/arch/arm/mach-bcmring/include/mach/timer.h b/arch/arm/mach-bcmring/include/mach/timer.h
deleted file mode 100644
index 5a94bbb032b6..000000000000
--- a/arch/arm/mach-bcmring/include/mach/timer.h
+++ /dev/null
@@ -1,77 +0,0 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/*
16*
17*****************************************************************************
18*
19* timer.h
20*
21* PURPOSE:
22*
23*
24*
25* NOTES:
26*
27*****************************************************************************/
28
29#if !defined(BCM_LINUX_TIMER_H)
30#define BCM_LINUX_TIMER_H
31
32#if defined(__KERNEL__)
33
34/* ---- Include Files ---------------------------------------------------- */
35/* ---- Constants and Types ---------------------------------------------- */
36
37typedef unsigned int timer_tick_count_t;
38typedef unsigned int timer_tick_rate_t;
39typedef unsigned int timer_msec_t;
40
41/* ---- Variable Externs ------------------------------------------------- */
42/* ---- Function Prototypes ---------------------------------------------- */
43
44/****************************************************************************
45*
46* timer_get_tick_count
47*
48*
49***************************************************************************/
50timer_tick_count_t timer_get_tick_count(void);
51
52/****************************************************************************
53*
54* timer_get_tick_rate
55*
56*
57***************************************************************************/
58timer_tick_rate_t timer_get_tick_rate(void);
59
60/****************************************************************************
61*
62* timer_get_msec
63*
64*
65***************************************************************************/
66timer_msec_t timer_get_msec(void);
67
68/****************************************************************************
69*
70* timer_ticks_to_msec
71*
72*
73***************************************************************************/
74timer_msec_t timer_ticks_to_msec(timer_tick_count_t ticks);
75
76#endif /* __KERNEL__ */
77#endif /* BCM_LINUX_TIMER_H */
diff --git a/arch/arm/mach-bcmring/include/mach/timex.h b/arch/arm/mach-bcmring/include/mach/timex.h
deleted file mode 100644
index 40d033ec5892..000000000000
--- a/arch/arm/mach-bcmring/include/mach/timex.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 *
3 * Integrator architecture timex specifications
4 *
5 * Copyright (C) 1999 ARM Limited
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/*
23 * Specifies the number of ticks per second
24 */
25#define CLOCK_TICK_RATE 100000 /* REG_SMT_TICKS_PER_SEC */
diff --git a/arch/arm/mach-bcmring/include/mach/uncompress.h b/arch/arm/mach-bcmring/include/mach/uncompress.h
deleted file mode 100644
index 9c9821b77977..000000000000
--- a/arch/arm/mach-bcmring/include/mach/uncompress.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*****************************************************************************
2* Copyright 2005 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14#include <mach/csp/mm_addr.h>
15
16#define BCMRING_UART_0_DR (*(volatile unsigned int *)MM_ADDR_IO_UARTA)
17#define BCMRING_UART_0_FR (*(volatile unsigned int *)(MM_ADDR_IO_UARTA + 0x18))
18/*
19 * This does not append a newline
20 */
21static inline void putc(int c)
22{
23 /* Send out UARTA */
24 while (BCMRING_UART_0_FR & (1 << 5))
25 ;
26
27 BCMRING_UART_0_DR = c;
28}
29
30
31static inline void flush(void)
32{
33 /* Wait for the tx fifo to be empty */
34 while ((BCMRING_UART_0_FR & (1 << 7)) == 0)
35 ;
36
37 /* Wait for the final character to be sent on the txd line */
38 while (BCMRING_UART_0_FR & (1 << 3))
39 ;
40}
41
42#define arch_decomp_setup()
43#define arch_decomp_wdog()
diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c
deleted file mode 100644
index 437fa683bcb2..000000000000
--- a/arch/arm/mach-bcmring/irq.c
+++ /dev/null
@@ -1,126 +0,0 @@
1/*
2 *
3 * Copyright (C) 1999 ARM Limited
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#include <linux/init.h>
20#include <linux/stddef.h>
21#include <linux/list.h>
22#include <linux/timer.h>
23#include <linux/io.h>
24
25#include <mach/hardware.h>
26#include <asm/irq.h>
27
28#include <asm/mach/irq.h>
29#include <mach/csp/intcHw_reg.h>
30#include <mach/csp/mm_io.h>
31
32static void bcmring_mask_irq0(struct irq_data *d)
33{
34 writel(1 << (d->irq - IRQ_INTC0_START),
35 MM_IO_BASE_INTC0 + INTCHW_INTENCLEAR);
36}
37
38static void bcmring_unmask_irq0(struct irq_data *d)
39{
40 writel(1 << (d->irq - IRQ_INTC0_START),
41 MM_IO_BASE_INTC0 + INTCHW_INTENABLE);
42}
43
44static void bcmring_mask_irq1(struct irq_data *d)
45{
46 writel(1 << (d->irq - IRQ_INTC1_START),
47 MM_IO_BASE_INTC1 + INTCHW_INTENCLEAR);
48}
49
50static void bcmring_unmask_irq1(struct irq_data *d)
51{
52 writel(1 << (d->irq - IRQ_INTC1_START),
53 MM_IO_BASE_INTC1 + INTCHW_INTENABLE);
54}
55
56static void bcmring_mask_irq2(struct irq_data *d)
57{
58 writel(1 << (d->irq - IRQ_SINTC_START),
59 MM_IO_BASE_SINTC + INTCHW_INTENCLEAR);
60}
61
62static void bcmring_unmask_irq2(struct irq_data *d)
63{
64 writel(1 << (d->irq - IRQ_SINTC_START),
65 MM_IO_BASE_SINTC + INTCHW_INTENABLE);
66}
67
68static struct irq_chip bcmring_irq0_chip = {
69 .name = "ARM-INTC0",
70 .irq_ack = bcmring_mask_irq0,
71 .irq_mask = bcmring_mask_irq0, /* mask a specific interrupt, blocking its delivery. */
72 .irq_unmask = bcmring_unmask_irq0, /* unmaks an interrupt */
73};
74
75static struct irq_chip bcmring_irq1_chip = {
76 .name = "ARM-INTC1",
77 .irq_ack = bcmring_mask_irq1,
78 .irq_mask = bcmring_mask_irq1,
79 .irq_unmask = bcmring_unmask_irq1,
80};
81
82static struct irq_chip bcmring_irq2_chip = {
83 .name = "ARM-SINTC",
84 .irq_ack = bcmring_mask_irq2,
85 .irq_mask = bcmring_mask_irq2,
86 .irq_unmask = bcmring_unmask_irq2,
87};
88
89static void vic_init(void __iomem *base, struct irq_chip *chip,
90 unsigned int irq_start, unsigned int vic_sources)
91{
92 unsigned int i;
93 for (i = 0; i < 32; i++) {
94 unsigned int irq = irq_start + i;
95 irq_set_chip(irq, chip);
96 irq_set_chip_data(irq, base);
97
98 if (vic_sources & (1 << i)) {
99 irq_set_handler(irq, handle_level_irq);
100 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
101 }
102 }
103 writel(0, base + INTCHW_INTSELECT);
104 writel(0, base + INTCHW_INTENABLE);
105 writel(~0, base + INTCHW_INTENCLEAR);
106 writel(0, base + INTCHW_IRQSTATUS);
107 writel(~0, base + INTCHW_SOFTINTCLEAR);
108}
109
110void __init bcmring_init_irq(void)
111{
112 vic_init((void __iomem *)MM_IO_BASE_INTC0, &bcmring_irq0_chip,
113 IRQ_INTC0_START, IRQ_INTC0_VALID_MASK);
114 vic_init((void __iomem *)MM_IO_BASE_INTC1, &bcmring_irq1_chip,
115 IRQ_INTC1_START, IRQ_INTC1_VALID_MASK);
116 vic_init((void __iomem *)MM_IO_BASE_SINTC, &bcmring_irq2_chip,
117 IRQ_SINTC_START, IRQ_SINTC_VALID_MASK);
118
119 /* special cases */
120 if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) {
121 irq_set_handler(IRQ_GPIO0, handle_simple_irq);
122 }
123 if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) {
124 irq_set_handler(IRQ_GPIO1, handle_simple_irq);
125 }
126}
diff --git a/arch/arm/mach-bcmring/mm.c b/arch/arm/mach-bcmring/mm.c
deleted file mode 100644
index 33824a81cac4..000000000000
--- a/arch/arm/mach-bcmring/mm.c
+++ /dev/null
@@ -1,60 +0,0 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#include <linux/platform_device.h>
16#include <linux/dma-mapping.h>
17#include <asm/page.h>
18#include <asm/mach/map.h>
19
20#include <mach/hardware.h>
21#include <mach/csp/mm_io.h>
22
23#define IO_DESC(va, sz) { .virtual = (unsigned long)va, \
24 .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
25 .length = sz, \
26 .type = MT_DEVICE }
27
28#define MEM_DESC(va, sz) { .virtual = (unsigned long)va, \
29 .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
30 .length = sz, \
31 .type = MT_MEMORY }
32
33static struct map_desc bcmring_io_desc[] __initdata = {
34 IO_DESC(MM_IO_BASE_NAND, SZ_64K), /* phys:0x28000000-0x28000FFF virt:0xE8000000-0xE8000FFF size:0x00010000 */
35 IO_DESC(MM_IO_BASE_UMI, SZ_64K), /* phys:0x2C000000-0x2C000FFF virt:0xEC000000-0xEC000FFF size:0x00010000 */
36
37 IO_DESC(MM_IO_BASE_BROM, SZ_64K), /* phys:0x30000000-0x3000FFFF virt:0xF3000000-0xF300FFFF size:0x00010000 */
38 MEM_DESC(MM_IO_BASE_ARAM, SZ_1M), /* phys:0x31000000-0x31FFFFFF virt:0xF3100000-0xF31FFFFF size:0x01000000 */
39 IO_DESC(MM_IO_BASE_DMA0, SZ_1M), /* phys:0x32000000-0x32FFFFFF virt:0xF3200000-0xF32FFFFF size:0x01000000 */
40 IO_DESC(MM_IO_BASE_DMA1, SZ_1M), /* phys:0x33000000-0x33FFFFFF virt:0xF3300000-0xF33FFFFF size:0x01000000 */
41 IO_DESC(MM_IO_BASE_ESW, SZ_1M), /* phys:0x34000000-0x34FFFFFF virt:0xF3400000-0xF34FFFFF size:0x01000000 */
42 IO_DESC(MM_IO_BASE_CLCD, SZ_1M), /* phys:0x35000000-0x35FFFFFF virt:0xF3500000-0xF35FFFFF size:0x01000000 */
43 IO_DESC(MM_IO_BASE_APM, SZ_1M), /* phys:0x36000000-0x36FFFFFF virt:0xF3600000-0xF36FFFFF size:0x01000000 */
44 IO_DESC(MM_IO_BASE_SPUM, SZ_1M), /* phys:0x37000000-0x37FFFFFF virt:0xF3700000-0xF37FFFFF size:0x01000000 */
45 IO_DESC(MM_IO_BASE_VPM_PROG, SZ_1M), /* phys:0x38000000-0x38FFFFFF virt:0xF3800000-0xF38FFFFF size:0x01000000 */
46 IO_DESC(MM_IO_BASE_VPM_DATA, SZ_1M), /* phys:0x3A000000-0x3AFFFFFF virt:0xF3A00000-0xF3AFFFFF size:0x01000000 */
47
48 IO_DESC(MM_IO_BASE_VRAM, SZ_64K), /* phys:0x40000000-0x4000FFFF virt:0xF4000000-0xF400FFFF size:0x00010000 */
49 IO_DESC(MM_IO_BASE_CHIPC, SZ_16M), /* phys:0x80000000-0x80FFFFFF virt:0xF8000000-0xF8FFFFFF size:0x01000000 */
50 IO_DESC(MM_IO_BASE_VPM_EXTMEM_RSVD,
51 SZ_16M), /* phys:0x0F000000-0x0FFFFFFF virt:0xF0000000-0xF0FFFFFF size:0x01000000 */
52};
53
54void __init bcmring_map_io(void)
55{
56
57 iotable_init(bcmring_io_desc, ARRAY_SIZE(bcmring_io_desc));
58 /* Maximum DMA memory allowed is 14M */
59 init_consistent_dma_size(14 << 20);
60}
diff --git a/arch/arm/mach-bcmring/timer.c b/arch/arm/mach-bcmring/timer.c
deleted file mode 100644
index 59412903466e..000000000000
--- a/arch/arm/mach-bcmring/timer.c
+++ /dev/null
@@ -1,61 +0,0 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#include <linux/types.h>
16#include <linux/module.h>
17#include <mach/csp/tmrHw.h>
18
19#include <mach/timer.h>
20/* The core.c file initializes timers 1 and 3 as a linux clocksource. */
21/* The real time clock should probably be the real linux clocksource. */
22/* In the meantime, this file should agree with core.c as to the */
23/* profiling timer. If the clocksource is moved to rtc later, then */
24/* we can init the profiling timer here instead. */
25
26/* Timer 1 provides 25MHz resolution syncrhonized to scheduling and APM timing */
27/* Timer 3 provides bus freqeuncy sychronized to ACLK, but spread spectrum will */
28/* affect synchronization with scheduling and APM timing. */
29
30#define PROF_TIMER 1
31
32timer_tick_rate_t timer_get_tick_rate(void)
33{
34 return tmrHw_getCountRate(PROF_TIMER);
35}
36
37timer_tick_count_t timer_get_tick_count(void)
38{
39 return tmrHw_GetCurrentCount(PROF_TIMER); /* change downcounter to upcounter */
40}
41
42timer_msec_t timer_ticks_to_msec(timer_tick_count_t ticks)
43{
44 static int tickRateMsec;
45
46 if (tickRateMsec == 0) {
47 tickRateMsec = timer_get_tick_rate() / 1000;
48 }
49
50 return ticks / tickRateMsec;
51}
52
53timer_msec_t timer_get_msec(void)
54{
55 return timer_ticks_to_msec(timer_get_tick_count());
56}
57
58EXPORT_SYMBOL(timer_get_tick_count);
59EXPORT_SYMBOL(timer_ticks_to_msec);
60EXPORT_SYMBOL(timer_get_tick_rate);
61EXPORT_SYMBOL(timer_get_msec);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 01:09:01 -0500