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authorSyed Mohammed, Khasim <khasim@ti.com>2008-10-09 10:51:41 -0400
committerTony Lindgren <tony@atomide.com>2008-10-09 10:51:41 -0400
commitcc26b3b01bc96a8b8c36671b0dc4898b2a152ea8 (patch)
tree8cd836cd32a38c1a849837ab295eeaa3ec104336 /arch/arm
parent2e7509e5b3acc4b8653faa1966e5ac234d36ac82 (diff)
ARM: OMAP3: Add minimal omap3430 support
Add minimal omap3430 support based on earlier patches from Syed Mohammed Khasim. Also merge in omap34xx SRAM support from Karthik Dasu and use consistent naming for sram init functions. Also do following changes that make 34xx support usable: - Remove unused sram.c functions for 34xx - Rename IRQ_SIR_IRQ to INTCPS_SIR_IRQ and define it locally in entry-macro.S - Update mach-omap2/io.c to support 2420, 2430, and 34xx - Also merge in 34xx GPMC changes to add fields wr_access and wr_data_mux_bus from Adrian Hunter - Remove memory initialization call omap2_init_memory() until until more generic memory initialization patches are posted. It's OK to rely on bootloader initialization until then. Signed-off-by: Syed Mohammed, Khasim <khasim@ti.com> Signed-off-by: Karthik Dasu<karthik-dp@ti.com> Signed-off-by: Adrian Hunter <ext-adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/mach-omap2/Kconfig11
-rw-r--r--arch/arm/mach-omap2/Makefile1
-rw-r--r--arch/arm/mach-omap2/gpmc.c5
-rw-r--r--arch/arm/mach-omap2/io.c126
-rw-r--r--arch/arm/mach-omap2/irq.c2
-rw-r--r--arch/arm/mach-omap2/memory.c14
-rw-r--r--arch/arm/mach-omap2/mux.c67
-rw-r--r--arch/arm/mach-omap2/sram34xx.S179
-rw-r--r--arch/arm/plat-omap/Kconfig9
-rw-r--r--arch/arm/plat-omap/devices.c15
-rw-r--r--arch/arm/plat-omap/include/mach/debug-macro.S12
-rw-r--r--arch/arm/plat-omap/include/mach/entry-macro.S12
-rw-r--r--arch/arm/plat-omap/include/mach/gpmc.h4
-rw-r--r--arch/arm/plat-omap/include/mach/io.h3
-rw-r--r--arch/arm/plat-omap/include/mach/irqs.h35
-rw-r--r--arch/arm/plat-omap/include/mach/mcbsp.h2
-rw-r--r--arch/arm/plat-omap/include/mach/memory.h2
-rw-r--r--arch/arm/plat-omap/include/mach/mux.h26
-rw-r--r--arch/arm/plat-omap/include/mach/omap24xx.h1
-rw-r--r--arch/arm/plat-omap/include/mach/sdrc.h4
-rw-r--r--arch/arm/plat-omap/include/mach/sram.h10
-rw-r--r--arch/arm/plat-omap/include/mach/system.h2
-rw-r--r--arch/arm/plat-omap/io.c32
-rw-r--r--arch/arm/plat-omap/sram.c53
25 files changed, 538 insertions, 90 deletions
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 703a44fa0f9b..552ea6d71ea2 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -118,6 +118,7 @@ endif
118 machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx 118 machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx
119 machine-$(CONFIG_ARCH_OMAP1) := omap1 119 machine-$(CONFIG_ARCH_OMAP1) := omap1
120 machine-$(CONFIG_ARCH_OMAP2) := omap2 120 machine-$(CONFIG_ARCH_OMAP2) := omap2
121 machine-$(CONFIG_ARCH_OMAP3) := omap2
121 plat-$(CONFIG_ARCH_OMAP) := omap 122 plat-$(CONFIG_ARCH_OMAP) := omap
122 machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443 123 machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443
123 plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx 124 plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 7069c9d536f1..e2481e4045e7 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -15,8 +15,17 @@ config ARCH_OMAP2430
15 bool "OMAP2430 support" 15 bool "OMAP2430 support"
16 depends on ARCH_OMAP24XX 16 depends on ARCH_OMAP24XX
17 17
18config ARCH_OMAP34XX
19 bool "OMAP34xx Based System"
20 depends on ARCH_OMAP3
21
22config ARCH_OMAP3430
23 bool "OMAP3430 support"
24 depends on ARCH_OMAP3 && ARCH_OMAP34XX
25 select ARCH_OMAP_OTG
26
18comment "OMAP Board Type" 27comment "OMAP Board Type"
19 depends on ARCH_OMAP2 28 depends on ARCH_OMAP2 || ARCH_OMAP3
20 29
21config MACH_OMAP_GENERIC 30config MACH_OMAP_GENERIC
22 bool "Generic OMAP board" 31 bool "Generic OMAP board"
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 800639e7c6a4..0dc40db38119 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
12# Functions loaded to SRAM 12# Functions loaded to SRAM
13obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o 13obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o
14obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o 14obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o
15obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o
15 16
16# Power Management 17# Power Management
17ifeq ($(CONFIG_PM),y) 18ifeq ($(CONFIG_PM),y)
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 149bfba43cfe..375ad27479cc 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -220,6 +220,11 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
220 220
221 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access); 221 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
222 222
223 if (cpu_is_omap34xx()) {
224 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
225 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
226 }
227
223 /* caller is expected to have initialized CONFIG1 to cover 228 /* caller is expected to have initialized CONFIG1 to cover
224 * at least sync vs async 229 * at least sync vs async
225 */ 230 */
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 03c6ab1a3b1f..71a9de382d2d 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -43,7 +43,9 @@
43 * The machine specific code may provide the extra mapping besides the 43 * The machine specific code may provide the extra mapping besides the
44 * default mapping provided here. 44 * default mapping provided here.
45 */ 45 */
46static struct map_desc omap2_io_desc[] __initdata = { 46
47#ifdef CONFIG_ARCH_OMAP24XX
48static struct map_desc omap24xx_io_desc[] __initdata = {
47 { 49 {
48 .virtual = L3_24XX_VIRT, 50 .virtual = L3_24XX_VIRT,
49 .pfn = __phys_to_pfn(L3_24XX_PHYS), 51 .pfn = __phys_to_pfn(L3_24XX_PHYS),
@@ -51,12 +53,39 @@ static struct map_desc omap2_io_desc[] __initdata = {
51 .type = MT_DEVICE 53 .type = MT_DEVICE
52 }, 54 },
53 { 55 {
54 .virtual = L4_24XX_VIRT, 56 .virtual = L4_24XX_VIRT,
55 .pfn = __phys_to_pfn(L4_24XX_PHYS), 57 .pfn = __phys_to_pfn(L4_24XX_PHYS),
56 .length = L4_24XX_SIZE, 58 .length = L4_24XX_SIZE,
57 .type = MT_DEVICE 59 .type = MT_DEVICE
60 },
61};
62
63#ifdef CONFIG_ARCH_OMAP2420
64static struct map_desc omap242x_io_desc[] __initdata = {
65 {
66 .virtual = DSP_MEM_24XX_VIRT,
67 .pfn = __phys_to_pfn(DSP_MEM_24XX_PHYS),
68 .length = DSP_MEM_24XX_SIZE,
69 .type = MT_DEVICE
70 },
71 {
72 .virtual = DSP_IPI_24XX_VIRT,
73 .pfn = __phys_to_pfn(DSP_IPI_24XX_PHYS),
74 .length = DSP_IPI_24XX_SIZE,
75 .type = MT_DEVICE
58 }, 76 },
77 {
78 .virtual = DSP_MMU_24XX_VIRT,
79 .pfn = __phys_to_pfn(DSP_MMU_24XX_PHYS),
80 .length = DSP_MMU_24XX_SIZE,
81 .type = MT_DEVICE
82 },
83};
84
85#endif
86
59#ifdef CONFIG_ARCH_OMAP2430 87#ifdef CONFIG_ARCH_OMAP2430
88static struct map_desc omap243x_io_desc[] __initdata = {
60 { 89 {
61 .virtual = L4_WK_243X_VIRT, 90 .virtual = L4_WK_243X_VIRT,
62 .pfn = __phys_to_pfn(L4_WK_243X_PHYS), 91 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
@@ -69,30 +98,90 @@ static struct map_desc omap2_io_desc[] __initdata = {
69 .length = OMAP243X_GPMC_SIZE, 98 .length = OMAP243X_GPMC_SIZE,
70 .type = MT_DEVICE 99 .type = MT_DEVICE
71 }, 100 },
101 {
102 .virtual = OMAP243X_SDRC_VIRT,
103 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
104 .length = OMAP243X_SDRC_SIZE,
105 .type = MT_DEVICE
106 },
107 {
108 .virtual = OMAP243X_SMS_VIRT,
109 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
110 .length = OMAP243X_SMS_SIZE,
111 .type = MT_DEVICE
112 },
113};
72#endif 114#endif
115#endif
116
117#ifdef CONFIG_ARCH_OMAP34XX
118static struct map_desc omap34xx_io_desc[] __initdata = {
73 { 119 {
74 .virtual = DSP_MEM_24XX_VIRT, 120 .virtual = L3_34XX_VIRT,
75 .pfn = __phys_to_pfn(DSP_MEM_24XX_PHYS), 121 .pfn = __phys_to_pfn(L3_34XX_PHYS),
76 .length = DSP_MEM_24XX_SIZE, 122 .length = L3_34XX_SIZE,
77 .type = MT_DEVICE 123 .type = MT_DEVICE
78 }, 124 },
79 { 125 {
80 .virtual = DSP_IPI_24XX_VIRT, 126 .virtual = L4_34XX_VIRT,
81 .pfn = __phys_to_pfn(DSP_IPI_24XX_PHYS), 127 .pfn = __phys_to_pfn(L4_34XX_PHYS),
82 .length = DSP_IPI_24XX_SIZE, 128 .length = L4_34XX_SIZE,
83 .type = MT_DEVICE 129 .type = MT_DEVICE
84 }, 130 },
85 { 131 {
86 .virtual = DSP_MMU_24XX_VIRT, 132 .virtual = L4_WK_34XX_VIRT,
87 .pfn = __phys_to_pfn(DSP_MMU_24XX_PHYS), 133 .pfn = __phys_to_pfn(L4_WK_34XX_PHYS),
88 .length = DSP_MMU_24XX_SIZE, 134 .length = L4_WK_34XX_SIZE,
135 .type = MT_DEVICE
136 },
137 {
138 .virtual = OMAP34XX_GPMC_VIRT,
139 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
140 .length = OMAP34XX_GPMC_SIZE,
141 .type = MT_DEVICE
142 },
143 {
144 .virtual = OMAP343X_SMS_VIRT,
145 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
146 .length = OMAP343X_SMS_SIZE,
147 .type = MT_DEVICE
148 },
149 {
150 .virtual = OMAP343X_SDRC_VIRT,
151 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
152 .length = OMAP343X_SDRC_SIZE,
89 .type = MT_DEVICE 153 .type = MT_DEVICE
90 } 154 },
155 {
156 .virtual = L4_PER_34XX_VIRT,
157 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
158 .length = L4_PER_34XX_SIZE,
159 .type = MT_DEVICE
160 },
161 {
162 .virtual = L4_EMU_34XX_VIRT,
163 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
164 .length = L4_EMU_34XX_SIZE,
165 .type = MT_DEVICE
166 },
91}; 167};
168#endif
92 169
93void __init omap2_map_common_io(void) 170void __init omap2_map_common_io(void)
94{ 171{
95 iotable_init(omap2_io_desc, ARRAY_SIZE(omap2_io_desc)); 172#if defined(CONFIG_ARCH_OMAP2420)
173 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
174 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
175#endif
176
177#if defined(CONFIG_ARCH_OMAP2430)
178 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
179 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
180#endif
181
182#if defined(CONFIG_ARCH_OMAP34XX)
183 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
184#endif
96 185
97 /* Normally devicemaps_init() would flush caches and tlb after 186 /* Normally devicemaps_init() would flush caches and tlb after
98 * mdesc->map_io(), but we must also do it here because of the CPU 187 * mdesc->map_io(), but we must also do it here because of the CPU
@@ -112,11 +201,6 @@ void __init omap2_init_common_hw(void)
112 pwrdm_init(powerdomains_omap); 201 pwrdm_init(powerdomains_omap);
113 clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); 202 clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
114 omap2_clk_init(); 203 omap2_clk_init();
115/*
116 * Need to Fix this for 2430
117 */
118#ifndef CONFIG_ARCH_OMAP2430
119 omap2_init_memory(); 204 omap2_init_memory();
120#endif
121 gpmc_init(); 205 gpmc_init();
122} 206}
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index c39e26dc5ee3..d354e0fe4477 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -128,6 +128,8 @@ void __init omap_init_irq(void)
128 128
129 if (cpu_is_omap24xx()) 129 if (cpu_is_omap24xx())
130 bank->base_reg = OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE); 130 bank->base_reg = OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE);
131 else if (cpu_is_omap34xx())
132 bank->base_reg = OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE);
131 133
132 omap_irq_bank_init_one(bank); 134 omap_irq_bank_init_one(bank);
133 135
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c
index 6b49cc9cbdcb..48b01f4cebc5 100644
--- a/arch/arm/mach-omap2/memory.c
+++ b/arch/arm/mach-omap2/memory.c
@@ -102,6 +102,17 @@ u32 omap2_reprogram_sdrc(u32 level, u32 force)
102 return prev; 102 return prev;
103} 103}
104 104
105#if !defined(CONFIG_ARCH_OMAP2)
106void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
107 u32 base_cs, u32 force_unlock)
108{
109}
110void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
111 u32 mem_type)
112{
113}
114#endif
115
105void omap2_init_memory_params(u32 force_lock_to_unlock_mode) 116void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
106{ 117{
107 unsigned long dll_cnt; 118 unsigned long dll_cnt;
@@ -166,6 +177,9 @@ void __init omap2_init_memory(void)
166{ 177{
167 u32 l; 178 u32 l;
168 179
180 if (!cpu_is_omap2420())
181 return;
182
169 l = sms_read_reg(SMS_SYSCONFIG); 183 l = sms_read_reg(SMS_SYSCONFIG);
170 l &= ~(0x3 << 3); 184 l &= ~(0x3 << 3);
171 l |= (0x2 << 3); 185 l |= (0x2 << 3);
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 6188e2f97854..5558803cd99e 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -298,13 +298,13 @@ MUX_CFG_34XX("T2_3430_USB2HS_PHY_D7", 0x1d6,
298 298
299/* TLL - HSUSB: 12-pin TLL Port 1*/ 299/* TLL - HSUSB: 12-pin TLL Port 1*/
300MUX_CFG_34XX("Y8_3430_USB1HS_TLL_CLK", 0x5da, 300MUX_CFG_34XX("Y8_3430_USB1HS_TLL_CLK", 0x5da,
301 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
302MUX_CFG_34XX("Y9_3430_USB1HS_TLL_STP", 0x5d8,
303 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) 301 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
302MUX_CFG_34XX("Y9_3430_USB1HS_TLL_STP", 0x5d8,
303 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLUP)
304MUX_CFG_34XX("AA14_3430_USB1HS_TLL_DIR", 0x5ec, 304MUX_CFG_34XX("AA14_3430_USB1HS_TLL_DIR", 0x5ec,
305 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT) 305 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
306MUX_CFG_34XX("AA11_3430_USB1HS_TLL_NXT", 0x5ee, 306MUX_CFG_34XX("AA11_3430_USB1HS_TLL_NXT", 0x5ee,
307 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT) 307 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
308MUX_CFG_34XX("W13_3430_USB1HS_TLL_D0", 0x5dc, 308MUX_CFG_34XX("W13_3430_USB1HS_TLL_D0", 0x5dc,
309 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) 309 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
310MUX_CFG_34XX("W12_3430_USB1HS_TLL_D1", 0x5de, 310MUX_CFG_34XX("W12_3430_USB1HS_TLL_D1", 0x5de,
@@ -324,13 +324,13 @@ MUX_CFG_34XX("Y13_3430_USB1HS_TLL_D7", 0x5e2,
324 324
325/* TLL - HSUSB: 12-pin TLL Port 2*/ 325/* TLL - HSUSB: 12-pin TLL Port 2*/
326MUX_CFG_34XX("AA8_3430_USB2HS_TLL_CLK", 0x5f0, 326MUX_CFG_34XX("AA8_3430_USB2HS_TLL_CLK", 0x5f0,
327 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
328MUX_CFG_34XX("AA10_3430_USB2HS_TLL_STP", 0x5f2,
329 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) 327 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
328MUX_CFG_34XX("AA10_3430_USB2HS_TLL_STP", 0x5f2,
329 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLUP)
330MUX_CFG_34XX("AA9_3430_USB2HS_TLL_DIR", 0x5f4, 330MUX_CFG_34XX("AA9_3430_USB2HS_TLL_DIR", 0x5f4,
331 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT) 331 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
332MUX_CFG_34XX("AB11_3430_USB2HS_TLL_NXT", 0x5f6, 332MUX_CFG_34XX("AB11_3430_USB2HS_TLL_NXT", 0x5f6,
333 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT) 333 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
334MUX_CFG_34XX("AB10_3430_USB2HS_TLL_D0", 0x5f8, 334MUX_CFG_34XX("AB10_3430_USB2HS_TLL_D0", 0x5f8,
335 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) 335 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
336MUX_CFG_34XX("AB9_3430_USB2HS_TLL_D1", 0x5fa, 336MUX_CFG_34XX("AB9_3430_USB2HS_TLL_D1", 0x5fa,
@@ -350,13 +350,13 @@ MUX_CFG_34XX("T2_3430_USB2HS_TLL_D7", 0x1d6,
350 350
351/* TLL - HSUSB: 12-pin TLL Port 3*/ 351/* TLL - HSUSB: 12-pin TLL Port 3*/
352MUX_CFG_34XX("AA6_3430_USB3HS_TLL_CLK", 0x180, 352MUX_CFG_34XX("AA6_3430_USB3HS_TLL_CLK", 0x180,
353 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
354MUX_CFG_34XX("AB3_3430_USB3HS_TLL_STP", 0x166,
355 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) 353 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
354MUX_CFG_34XX("AB3_3430_USB3HS_TLL_STP", 0x166,
355 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLUP)
356MUX_CFG_34XX("AA3_3430_USB3HS_TLL_DIR", 0x168, 356MUX_CFG_34XX("AA3_3430_USB3HS_TLL_DIR", 0x168,
357 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT) 357 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
358MUX_CFG_34XX("Y3_3430_USB3HS_TLL_NXT", 0x16a, 358MUX_CFG_34XX("Y3_3430_USB3HS_TLL_NXT", 0x16a,
359 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT) 359 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
360MUX_CFG_34XX("AA5_3430_USB3HS_TLL_D0", 0x186, 360MUX_CFG_34XX("AA5_3430_USB3HS_TLL_D0", 0x186,
361 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) 361 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
362MUX_CFG_34XX("Y4_3430_USB3HS_TLL_D1", 0x184, 362MUX_CFG_34XX("Y4_3430_USB3HS_TLL_D1", 0x184,
@@ -373,6 +373,49 @@ MUX_CFG_34XX("AA13_3430_USB3HS_TLL_D6", 0x170,
373 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) 373 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
374MUX_CFG_34XX("AA12_3430_USB3HS_TLL_D7", 0x172, 374MUX_CFG_34XX("AA12_3430_USB3HS_TLL_D7", 0x172,
375 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) 375 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
376
377/* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
378MUX_CFG_34XX("AF10_3430_USB1FS_PHY_MM1_RXDP", 0x5d8,
379 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
380MUX_CFG_34XX("AG9_3430_USB1FS_PHY_MM1_RXDM", 0x5ee,
381 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
382MUX_CFG_34XX("W13_3430_USB1FS_PHY_MM1_RXRCV", 0x5dc,
383 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
384MUX_CFG_34XX("W12_3430_USB1FS_PHY_MM1_TXSE0", 0x5de,
385 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
386MUX_CFG_34XX("W11_3430_USB1FS_PHY_MM1_TXDAT", 0x5e0,
387 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
388MUX_CFG_34XX("Y11_3430_USB1FS_PHY_MM1_TXEN_N", 0x5ea,
389 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
390
391/* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
392MUX_CFG_34XX("AF7_3430_USB2FS_PHY_MM2_RXDP", 0x5f2,
393 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
394MUX_CFG_34XX("AH7_3430_USB2FS_PHY_MM2_RXDM", 0x5f6,
395 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
396MUX_CFG_34XX("AB10_3430_USB2FS_PHY_MM2_RXRCV", 0x5f8,
397 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
398MUX_CFG_34XX("AB9_3430_USB2FS_PHY_MM2_TXSE0", 0x5fa,
399 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
400MUX_CFG_34XX("W3_3430_USB2FS_PHY_MM2_TXDAT", 0x1d4,
401 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
402MUX_CFG_34XX("T4_3430_USB2FS_PHY_MM2_TXEN_N", 0x1de,
403 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
404
405/* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
406MUX_CFG_34XX("AH3_3430_USB3FS_PHY_MM3_RXDP", 0x166,
407 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
408MUX_CFG_34XX("AE3_3430_USB3FS_PHY_MM3_RXDM", 0x16a,
409 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
410MUX_CFG_34XX("AD1_3430_USB3FS_PHY_MM3_RXRCV", 0x186,
411 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
412MUX_CFG_34XX("AE1_3430_USB3FS_PHY_MM3_TXSE0", 0x184,
413 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
414MUX_CFG_34XX("AD2_3430_USB3FS_PHY_MM3_TXDAT", 0x188,
415 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
416MUX_CFG_34XX("AC1_3430_USB3FS_PHY_MM3_TXEN_N", 0x18a,
417 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
418
376}; 419};
377 420
378#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins) 421#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins)
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
new file mode 100644
index 000000000000..2c7146136342
--- /dev/null
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -0,0 +1,179 @@
1/*
2 * linux/arch/arm/mach-omap3/sram.S
3 *
4 * Omap3 specific functions that need to be run in internal SRAM
5 *
6 * (C) Copyright 2007
7 * Texas Instruments Inc.
8 * Rajendra Nayak <rnayak@ti.com>
9 *
10 * (C) Copyright 2004
11 * Texas Instruments, <www.ti.com>
12 * Richard Woodruff <r-woodruff2@ti.com>
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29#include <linux/linkage.h>
30#include <asm/assembler.h>
31#include <mach/hardware.h>
32
33#include <mach/io.h>
34
35#include "sdrc.h"
36#include "cm.h"
37
38 .text
39
40/*
41 * Change frequency of core dpll
42 * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
43 */
44ENTRY(omap3_sram_configure_core_dpll)
45 stmfd sp!, {r1-r12, lr} @ store regs to stack
46 cmp r3, #0x2
47 blne configure_sdrc
48 cmp r3, #0x2
49 blne lock_dll
50 cmp r3, #0x1
51 blne unlock_dll
52 bl sdram_in_selfrefresh @ put the SDRAM in self refresh
53 bl configure_core_dpll
54 bl enable_sdrc
55 cmp r3, #0x1
56 blne wait_dll_unlock
57 cmp r3, #0x2
58 blne wait_dll_lock
59 cmp r3, #0x1
60 blne configure_sdrc
61 mov r0, #0 @ return value
62 ldmfd sp!, {r1-r12, pc} @ restore regs and return
63unlock_dll:
64 ldr r4, omap3_sdrc_dlla_ctrl
65 ldr r5, [r4]
66 orr r5, r5, #0x4
67 str r5, [r4]
68 bx lr
69lock_dll:
70 ldr r4, omap3_sdrc_dlla_ctrl
71 ldr r5, [r4]
72 bic r5, r5, #0x4
73 str r5, [r4]
74 bx lr
75sdram_in_selfrefresh:
76 mov r5, #0x0 @ Move 0 to R5
77 mcr p15, 0, r5, c7, c10, 5 @ memory barrier
78 ldr r4, omap3_sdrc_power @ read the SDRC_POWER register
79 ldr r5, [r4] @ read the contents of SDRC_POWER
80 orr r5, r5, #0x40 @ enable self refresh on idle req
81 str r5, [r4] @ write back to SDRC_POWER register
82 ldr r4, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
83 ldr r5, [r4]
84 bic r5, r5, #0x2 @ disable iclk bit for SRDC
85 str r5, [r4]
86wait_sdrc_idle:
87 ldr r4, omap3_cm_idlest1_core
88 ldr r5, [r4]
89 and r5, r5, #0x2 @ check for SDRC idle
90 cmp r5, #2
91 bne wait_sdrc_idle
92 bx lr
93configure_core_dpll:
94 ldr r4, omap3_cm_clksel1_pll
95 ldr r5, [r4]
96 ldr r6, core_m2_mask_val @ modify m2 for core dpll
97 and r5, r5, r6
98 orr r5, r5, r3, lsl #0x1B @ r3 contains the M2 val
99 str r5, [r4]
100 mov r5, #0x800 @ wait for the clock to stabilise
101 cmp r3, #2
102 bne wait_clk_stable
103 bx lr
104wait_clk_stable:
105 subs r5, r5, #1
106 bne wait_clk_stable
107 nop
108 nop
109 nop
110 nop
111 nop
112 nop
113 nop
114 nop
115 nop
116 nop
117 bx lr
118enable_sdrc:
119 ldr r4, omap3_cm_iclken1_core
120 ldr r5, [r4]
121 orr r5, r5, #0x2 @ enable iclk bit for SDRC
122 str r5, [r4]
123wait_sdrc_idle1:
124 ldr r4, omap3_cm_idlest1_core
125 ldr r5, [r4]
126 and r5, r5, #0x2
127 cmp r5, #0
128 bne wait_sdrc_idle1
129 ldr r4, omap3_sdrc_power
130 ldr r5, [r4]
131 bic r5, r5, #0x40
132 str r5, [r4]
133 bx lr
134wait_dll_lock:
135 ldr r4, omap3_sdrc_dlla_status
136 ldr r5, [r4]
137 and r5, r5, #0x4
138 cmp r5, #0x4
139 bne wait_dll_lock
140 bx lr
141wait_dll_unlock:
142 ldr r4, omap3_sdrc_dlla_status
143 ldr r5, [r4]
144 and r5, r5, #0x4
145 cmp r5, #0x0
146 bne wait_dll_unlock
147 bx lr
148configure_sdrc:
149 ldr r4, omap3_sdrc_rfr_ctrl
150 str r0, [r4]
151 ldr r4, omap3_sdrc_actim_ctrla
152 str r1, [r4]
153 ldr r4, omap3_sdrc_actim_ctrlb
154 str r2, [r4]
155 bx lr
156
157omap3_sdrc_power:
158 .word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
159omap3_cm_clksel1_pll:
160 .word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
161omap3_cm_idlest1_core:
162 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
163omap3_cm_iclken1_core:
164 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
165omap3_sdrc_rfr_ctrl:
166 .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
167omap3_sdrc_actim_ctrla:
168 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
169omap3_sdrc_actim_ctrlb:
170 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
171omap3_sdrc_dlla_status:
172 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
173omap3_sdrc_dlla_ctrl:
174 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
175core_m2_mask_val:
176 .word 0x07FFFFFF
177
178ENTRY(omap3_sram_configure_core_dpll_sz)
179 .word . - omap3_sram_configure_core_dpll
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index ef62bf21e179..a94f0c44ebc8 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -15,6 +15,9 @@ config ARCH_OMAP1
15config ARCH_OMAP2 15config ARCH_OMAP2
16 bool "TI OMAP2" 16 bool "TI OMAP2"
17 17
18config ARCH_OMAP3
19 bool "TI OMAP3"
20
18endchoice 21endchoice
19 22
20comment "OMAP Feature Selections" 23comment "OMAP Feature Selections"
@@ -112,13 +115,13 @@ config OMAP_MPU_TIMER
112 115
113config OMAP_32K_TIMER 116config OMAP_32K_TIMER
114 bool "Use 32KHz timer" 117 bool "Use 32KHz timer"
115 depends on ARCH_OMAP16XX || ARCH_OMAP24XX 118 depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX
116 help 119 help
117 Select this option if you want to enable the OMAP 32KHz timer. 120 Select this option if you want to enable the OMAP 32KHz timer.
118 This timer saves power compared to the OMAP_MPU_TIMER, and has 121 This timer saves power compared to the OMAP_MPU_TIMER, and has
119 support for no tick during idle. The 32KHz timer provides less 122 support for no tick during idle. The 32KHz timer provides less
120 intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is 123 intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
121 currently only available for OMAP16XX and 24XX. 124 currently only available for OMAP16XX, 24XX and 34XX.
122 125
123endchoice 126endchoice
124 127
@@ -133,7 +136,7 @@ config OMAP_32K_TIMER_HZ
133 136
134config OMAP_DM_TIMER 137config OMAP_DM_TIMER
135 bool "Use dual-mode timer" 138 bool "Use dual-mode timer"
136 depends on ARCH_OMAP16XX || ARCH_OMAP24XX 139 depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX
137 help 140 help
138 Select this option if you want to use OMAP Dual-Mode timers. 141 Select this option if you want to use OMAP Dual-Mode timers.
139 142
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 1c1d831a0c09..2625ce32e602 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -94,6 +94,10 @@ static inline void omap_init_dsp(void) { }
94 94
95static void omap_init_kp(void) 95static void omap_init_kp(void)
96{ 96{
97 /* 2430 and 34xx keypad is on TWL4030 */
98 if (cpu_is_omap2430() || cpu_is_omap34xx())
99 return;
100
97 if (machine_is_omap_h2() || machine_is_omap_h3()) { 101 if (machine_is_omap_h2() || machine_is_omap_h3()) {
98 omap_cfg_reg(F18_1610_KBC0); 102 omap_cfg_reg(F18_1610_KBC0);
99 omap_cfg_reg(D20_1610_KBC1); 103 omap_cfg_reg(D20_1610_KBC1);
@@ -395,8 +399,17 @@ static inline void omap_init_uwire(void) {}
395 399
396#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE) 400#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
397 401
398#ifdef CONFIG_ARCH_OMAP24XX 402#if defined(CONFIG_ARCH_OMAP34XX)
403#define OMAP_WDT_BASE 0x48314000
404#elif defined(CONFIG_ARCH_OMAP24XX)
405
406#ifdef CONFIG_ARCH_OMAP2430
407/* WDT2 */
408#define OMAP_WDT_BASE 0x49016000
409#else
399#define OMAP_WDT_BASE 0x48022000 410#define OMAP_WDT_BASE 0x48022000
411#endif
412
400#else 413#else
401#define OMAP_WDT_BASE 0xfffeb000 414#define OMAP_WDT_BASE 0xfffeb000
402#endif 415#endif
diff --git a/arch/arm/plat-omap/include/mach/debug-macro.S b/arch/arm/plat-omap/include/mach/debug-macro.S
index 1b0039bdeb4e..1b11f5c6a2d9 100644
--- a/arch/arm/plat-omap/include/mach/debug-macro.S
+++ b/arch/arm/plat-omap/include/mach/debug-macro.S
@@ -35,6 +35,18 @@
35#ifdef CONFIG_OMAP_LL_DEBUG_UART3 35#ifdef CONFIG_OMAP_LL_DEBUG_UART3
36 add \rx, \rx, #0x00004000 @ UART 3 36 add \rx, \rx, #0x00004000 @ UART 3
37#endif 37#endif
38
39#elif CONFIG_ARCH_OMAP3
40 moveq \rx, #0x48000000 @ physical base address
41 movne \rx, #0xd8000000 @ virtual base
42 orr \rx, \rx, #0x0006a000
43#ifdef CONFIG_OMAP_LL_DEBUG_UART2
44 add \rx, \rx, #0x00002000 @ UART 2
45#endif
46#ifdef CONFIG_OMAP_LL_DEBUG_UART3
47 add \rx, \rx, #0x00fb0000 @ UART 3
48 add \rx, \rx, #0x00006000
49#endif
38#endif 50#endif
39 .endm 51 .endm
40 52
diff --git a/arch/arm/plat-omap/include/mach/entry-macro.S b/arch/arm/plat-omap/include/mach/entry-macro.S
index d4e9043bf201..030118ee204a 100644
--- a/arch/arm/plat-omap/include/mach/entry-macro.S
+++ b/arch/arm/plat-omap/include/mach/entry-macro.S
@@ -55,9 +55,17 @@
551510: 551510:
56 .endm 56 .endm
57 57
58#elif defined(CONFIG_ARCH_OMAP24XX) 58#endif
59#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
59 60
61#if defined(CONFIG_ARCH_OMAP24XX)
60#include <mach/omap24xx.h> 62#include <mach/omap24xx.h>
63#endif
64#if defined(CONFIG_ARCH_OMAP34XX)
65#include <mach/omap34xx.h>
66#endif
67
68#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt number */
61 69
62 .macro disable_fiq 70 .macro disable_fiq
63 .endm 71 .endm
@@ -79,7 +87,7 @@
79 ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */ 87 ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
80 cmp \irqnr, #0x0 88 cmp \irqnr, #0x0
812222: 892222:
82 ldrne \irqnr, [\base, #IRQ_SIR_IRQ] 90 ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
83 91
84 .endm 92 .endm
85 93
diff --git a/arch/arm/plat-omap/include/mach/gpmc.h b/arch/arm/plat-omap/include/mach/gpmc.h
index 3c7b425c585e..45b678439bb7 100644
--- a/arch/arm/plat-omap/include/mach/gpmc.h
+++ b/arch/arm/plat-omap/include/mach/gpmc.h
@@ -84,6 +84,10 @@ struct gpmc_timings {
84 u16 access; /* Start-cycle to first data valid delay */ 84 u16 access; /* Start-cycle to first data valid delay */
85 u16 rd_cycle; /* Total read cycle time */ 85 u16 rd_cycle; /* Total read cycle time */
86 u16 wr_cycle; /* Total write cycle time */ 86 u16 wr_cycle; /* Total write cycle time */
87
88 /* The following are only on OMAP3430 */
89 u16 wr_access; /* WRACCESSTIME */
90 u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */
87}; 91};
88 92
89extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns); 93extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h
index dd0cf069431d..adc83b7b8205 100644
--- a/arch/arm/plat-omap/include/mach/io.h
+++ b/arch/arm/plat-omap/include/mach/io.h
@@ -73,7 +73,6 @@
73#define L4_24XX_VIRT 0xd8000000 73#define L4_24XX_VIRT 0xd8000000
74#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */ 74#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
75 75
76#ifdef CONFIG_ARCH_OMAP2430
77#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 */ 76#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 */
78#define L4_WK_243X_VIRT 0xd9000000 77#define L4_WK_243X_VIRT 0xd9000000
79#define L4_WK_243X_SIZE SZ_1M 78#define L4_WK_243X_SIZE SZ_1M
@@ -87,8 +86,6 @@
87#define OMAP243X_SMS_VIRT 0xFC000000 86#define OMAP243X_SMS_VIRT 0xFC000000
88#define OMAP243X_SMS_SIZE SZ_1M 87#define OMAP243X_SMS_SIZE SZ_1M
89 88
90#endif
91
92#define IO_OFFSET 0x90000000 89#define IO_OFFSET 0x90000000
93#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ 90#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
94#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ 91#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h
index e9fd63055cb2..9ee04969d366 100644
--- a/arch/arm/plat-omap/include/mach/irqs.h
+++ b/arch/arm/plat-omap/include/mach/irqs.h
@@ -286,6 +286,41 @@
286#define INT_24XX_USB_IRQ_OTG 80 286#define INT_24XX_USB_IRQ_OTG 80
287#define INT_24XX_MMC_IRQ 83 287#define INT_24XX_MMC_IRQ 83
288 288
289#define INT_34XX_BENCH_MPU_EMUL 3
290#define INT_34XX_ST_MCBSP2_IRQ 4
291#define INT_34XX_ST_MCBSP3_IRQ 5
292#define INT_34XX_SSM_ABORT_IRQ 6
293#define INT_34XX_SYS_NIRQ 7
294#define INT_34XX_D2D_FW_IRQ 8
295#define INT_34XX_PRCM_MPU_IRQ 11
296#define INT_34XX_MCBSP1_IRQ 16
297#define INT_34XX_MCBSP2_IRQ 17
298#define INT_34XX_MCBSP3_IRQ 22
299#define INT_34XX_MCBSP4_IRQ 23
300#define INT_34XX_CAM_IRQ 24
301#define INT_34XX_MCBSP5_IRQ 27
302#define INT_34XX_GPIO_BANK1 29
303#define INT_34XX_GPIO_BANK2 30
304#define INT_34XX_GPIO_BANK3 31
305#define INT_34XX_GPIO_BANK4 32
306#define INT_34XX_GPIO_BANK5 33
307#define INT_34XX_GPIO_BANK6 34
308#define INT_34XX_USIM_IRQ 35
309#define INT_34XX_WDT3_IRQ 36
310#define INT_34XX_SPI4_IRQ 48
311#define INT_34XX_SHA1MD52_IRQ 49
312#define INT_34XX_FPKA_READY_IRQ 50
313#define INT_34XX_SHA1MD51_IRQ 51
314#define INT_34XX_RNG_IRQ 52
315#define INT_34XX_I2C3_IRQ 61
316#define INT_34XX_FPKA_ERROR_IRQ 64
317#define INT_34XX_PBIAS_IRQ 75
318#define INT_34XX_OHCI_IRQ 76
319#define INT_34XX_EHCI_IRQ 77
320#define INT_34XX_TLL_IRQ 78
321#define INT_34XX_PARTHASH_IRQ 79
322#define INT_34XX_MMC3_IRQ 94
323#define INT_34XX_GPT12_IRQ 95
289/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and 324/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and
290 * 16 MPUIO lines */ 325 * 16 MPUIO lines */
291#define OMAP_MAX_GPIO_LINES 192 326#define OMAP_MAX_GPIO_LINES 192
diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/mach/mcbsp.h
index a3074f2fb7ce..c8d0aa118be7 100644
--- a/arch/arm/plat-omap/include/mach/mcbsp.h
+++ b/arch/arm/plat-omap/include/mach/mcbsp.h
@@ -91,7 +91,7 @@
91#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX 91#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX
92#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX 92#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX
93 93
94#elif defined(CONFIG_ARCH_OMAP24XX) 94#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
95 95
96#define OMAP_MCBSP_REG_DRR2 0x00 96#define OMAP_MCBSP_REG_DRR2 0x00
97#define OMAP_MCBSP_REG_DRR1 0x04 97#define OMAP_MCBSP_REG_DRR1 0x04
diff --git a/arch/arm/plat-omap/include/mach/memory.h b/arch/arm/plat-omap/include/mach/memory.h
index a325caf80d04..d40cac60b959 100644
--- a/arch/arm/plat-omap/include/mach/memory.h
+++ b/arch/arm/plat-omap/include/mach/memory.h
@@ -38,7 +38,7 @@
38 */ 38 */
39#if defined(CONFIG_ARCH_OMAP1) 39#if defined(CONFIG_ARCH_OMAP1)
40#define PHYS_OFFSET UL(0x10000000) 40#define PHYS_OFFSET UL(0x10000000)
41#elif defined(CONFIG_ARCH_OMAP2) 41#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
42#define PHYS_OFFSET UL(0x80000000) 42#define PHYS_OFFSET UL(0x80000000)
43#endif 43#endif
44 44
diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h
index 5670d563f378..6bbf1789bed5 100644
--- a/arch/arm/plat-omap/include/mach/mux.h
+++ b/arch/arm/plat-omap/include/mach/mux.h
@@ -723,7 +723,31 @@ enum omap34xx_index {
723 AB12_3430_USB3HS_TLL_DATA4, 723 AB12_3430_USB3HS_TLL_DATA4,
724 AB13_3430_USB3HS_TLL_DATA5, 724 AB13_3430_USB3HS_TLL_DATA5,
725 AA13_3430_USB3HS_TLL_DATA6, 725 AA13_3430_USB3HS_TLL_DATA6,
726 AA12_3430_USB3HS_TLL_DATA7 726 AA12_3430_USB3HS_TLL_DATA7,
727
728 /* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
729 AF10_3430_USB1FS_PHY_MM1_RXDP,
730 AG9_3430_USB1FS_PHY_MM1_RXDM,
731 W13_3430_USB1FS_PHY_MM1_RXRCV,
732 W12_3430_USB1FS_PHY_MM1_TXSE0,
733 W11_3430_USB1FS_PHY_MM1_TXDAT,
734 Y11_3430_USB1FS_PHY_MM1_TXEN_N,
735
736 /* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
737 AF7_3430_USB2FS_PHY_MM2_RXDP,
738 AH7_3430_USB2FS_PHY_MM2_RXDM,
739 AB10_3430_USB2FS_PHY_MM2_RXRCV,
740 AB9_3430_USB2FS_PHY_MM2_TXSE0,
741 W3_3430_USB2FS_PHY_MM2_TXDAT,
742 T4_3430_USB2FS_PHY_MM2_TXEN_N,
743
744 /* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
745 AH3_3430_USB3FS_PHY_MM3_RXDP,
746 AE3_3430_USB3FS_PHY_MM3_RXDM,
747 AD1_3430_USB3FS_PHY_MM3_RXRCV,
748 AE1_3430_USB3FS_PHY_MM3_TXSE0,
749 AD2_3430_USB3FS_PHY_MM3_TXDAT,
750 AC1_3430_USB3FS_PHY_MM3_TXEN_N,
727 751
728}; 752};
729 753
diff --git a/arch/arm/plat-omap/include/mach/omap24xx.h b/arch/arm/plat-omap/include/mach/omap24xx.h
index 556f0eb4d55c..24335d4932f5 100644
--- a/arch/arm/plat-omap/include/mach/omap24xx.h
+++ b/arch/arm/plat-omap/include/mach/omap24xx.h
@@ -39,7 +39,6 @@
39/* interrupt controller */ 39/* interrupt controller */
40#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000) 40#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
41#define OMAP24XX_IVA_INTC_BASE 0x40000000 41#define OMAP24XX_IVA_INTC_BASE 0x40000000
42#define IRQ_SIR_IRQ 0x0040
43 42
44#define OMAP2420_CTRL_BASE L4_24XX_BASE 43#define OMAP2420_CTRL_BASE L4_24XX_BASE
45#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000) 44#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/mach/sdrc.h
index 25ee3819faad..a98c6c3beb2c 100644
--- a/arch/arm/plat-omap/include/mach/sdrc.h
+++ b/arch/arm/plat-omap/include/mach/sdrc.h
@@ -25,8 +25,8 @@
25#define SDRC_DLLB_STATUS 0x06C 25#define SDRC_DLLB_STATUS 0x06C
26#define SDRC_POWER 0x070 26#define SDRC_POWER 0x070
27#define SDRC_MR_0 0x084 27#define SDRC_MR_0 0x084
28#define SDRC_ACTIM_CTRL_A 0x09c 28#define SDRC_ACTIM_CTRL_A_0 0x09c
29#define SDRC_ACTIM_CTRL_B 0x0a0 29#define SDRC_ACTIM_CTRL_B_0 0x0a0
30#define SDRC_RFR_CTRL_0 0x0a4 30#define SDRC_RFR_CTRL_0 0x0a4
31 31
32/* 32/*
diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h
index e09323449981..ab35d622dcf5 100644
--- a/arch/arm/plat-omap/include/mach/sram.h
+++ b/arch/arm/plat-omap/include/mach/sram.h
@@ -21,6 +21,10 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
21 u32 mem_type); 21 u32 mem_type);
22extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); 22extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
23 23
24extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
25 u32 sdrc_actim_ctrla,
26 u32 sdrc_actim_ctrlb, u32 m2);
27
24/* Do not use these */ 28/* Do not use these */
25extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); 29extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
26extern unsigned long omap1_sram_reprogram_clock_sz; 30extern unsigned long omap1_sram_reprogram_clock_sz;
@@ -53,4 +57,10 @@ extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
53 u32 mem_type); 57 u32 mem_type);
54extern unsigned long omap243x_sram_reprogram_sdrc_sz; 58extern unsigned long omap243x_sram_reprogram_sdrc_sz;
55 59
60
61extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
62 u32 sdrc_actim_ctrla,
63 u32 sdrc_actim_ctrlb, u32 m2);
64extern unsigned long omap3_sram_configure_core_dpll_sz;
65
56#endif 66#endif
diff --git a/arch/arm/plat-omap/include/mach/system.h b/arch/arm/plat-omap/include/mach/system.h
index 06a28c7b98de..06923f261545 100644
--- a/arch/arm/plat-omap/include/mach/system.h
+++ b/arch/arm/plat-omap/include/mach/system.h
@@ -40,7 +40,7 @@ static inline void omap1_arch_reset(char mode)
40 40
41static inline void arch_reset(char mode) 41static inline void arch_reset(char mode)
42{ 42{
43 if (!cpu_is_omap24xx()) 43 if (!cpu_class_is_omap2())
44 omap1_arch_reset(mode); 44 omap1_arch_reset(mode);
45 else 45 else
46 omap_prcm_arch_reset(mode); 46 omap_prcm_arch_reset(mode);
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
index 0253c456ed5b..af326efc1ad3 100644
--- a/arch/arm/plat-omap/io.c
+++ b/arch/arm/plat-omap/io.c
@@ -47,11 +47,13 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
47 } 47 }
48#endif 48#endif
49#ifdef CONFIG_ARCH_OMAP2 49#ifdef CONFIG_ARCH_OMAP2
50 if (cpu_class_is_omap2()) { 50 if (cpu_is_omap24xx()) {
51 if (BETWEEN(p, L3_24XX_PHYS, L3_24XX_SIZE)) 51 if (BETWEEN(p, L3_24XX_PHYS, L3_24XX_SIZE))
52 return XLATE(p, L3_24XX_PHYS, L3_24XX_VIRT); 52 return XLATE(p, L3_24XX_PHYS, L3_24XX_VIRT);
53 if (BETWEEN(p, L4_24XX_PHYS, L4_24XX_SIZE)) 53 if (BETWEEN(p, L4_24XX_PHYS, L4_24XX_SIZE))
54 return XLATE(p, L4_24XX_PHYS, L4_24XX_VIRT); 54 return XLATE(p, L4_24XX_PHYS, L4_24XX_VIRT);
55 }
56 if (cpu_is_omap2420()) {
55 if (BETWEEN(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_SIZE)) 57 if (BETWEEN(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_SIZE))
56 return XLATE(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_VIRT); 58 return XLATE(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_VIRT);
57 if (BETWEEN(p, DSP_IPI_24XX_PHYS, DSP_IPI_24XX_SIZE)) 59 if (BETWEEN(p, DSP_IPI_24XX_PHYS, DSP_IPI_24XX_SIZE))
@@ -59,14 +61,36 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
59 if (BETWEEN(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_SIZE)) 61 if (BETWEEN(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_SIZE))
60 return XLATE(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_VIRT); 62 return XLATE(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_VIRT);
61 } 63 }
62#ifdef CONFIG_ARCH_OMAP2430
63 if (cpu_is_omap2430()) { 64 if (cpu_is_omap2430()) {
64 if (BETWEEN(p, L4_WK_243X_PHYS, L4_WK_243X_SIZE)) 65 if (BETWEEN(p, L4_WK_243X_PHYS, L4_WK_243X_SIZE))
65 return XLATE(L4_WK_243X_PHYS, L4_WK_243X_VIRT); 66 return XLATE(p, L4_WK_243X_PHYS, L4_WK_243X_VIRT);
66 if (BETWEEN(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_SIZE)) 67 if (BETWEEN(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_SIZE))
67 return XLATE(OMAP243X_GPMC_PHYS, OMAP243X_GPMC_VIRT); 68 return XLATE(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_VIRT);
69 if (BETWEEN(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_SIZE))
70 return XLATE(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_VIRT);
71 if (BETWEEN(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_SIZE))
72 return XLATE(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_VIRT);
68 } 73 }
69#endif 74#endif
75#ifdef CONFIG_ARCH_OMAP3
76 if (cpu_is_omap34xx()) {
77 if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE))
78 return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT);
79 if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
80 return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
81 if (BETWEEN(p, L4_WK_34XX_PHYS, L4_WK_34XX_SIZE))
82 return XLATE(p, L4_WK_34XX_PHYS, L4_WK_34XX_VIRT);
83 if (BETWEEN(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_SIZE))
84 return XLATE(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_VIRT);
85 if (BETWEEN(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_SIZE))
86 return XLATE(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_VIRT);
87 if (BETWEEN(p, OMAP343X_SDRC_PHYS, OMAP343X_SDRC_SIZE))
88 return XLATE(p, OMAP343X_SDRC_PHYS, OMAP343X_SDRC_VIRT);
89 if (BETWEEN(p, L4_PER_34XX_PHYS, L4_PER_34XX_SIZE))
90 return XLATE(p, L4_PER_34XX_PHYS, L4_PER_34XX_VIRT);
91 if (BETWEEN(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_SIZE))
92 return XLATE(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_VIRT);
93 }
70#endif 94#endif
71 95
72 return __arm_ioremap(p, size, type); 96 return __arm_ioremap(p, size, type);
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index ac67eeb6ca6a..4d22452a0743 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -271,7 +271,7 @@ int __init omap1_sram_init(void)
271#define omap1_sram_init() do {} while (0) 271#define omap1_sram_init() do {} while (0)
272#endif 272#endif
273 273
274#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 274#if defined(CONFIG_ARCH_OMAP2)
275 275
276static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, 276static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
277 u32 base_cs, u32 force_unlock); 277 u32 base_cs, u32 force_unlock);
@@ -352,23 +352,19 @@ static inline int omap243x_sram_init(void)
352 352
353#ifdef CONFIG_ARCH_OMAP3 353#ifdef CONFIG_ARCH_OMAP3
354 354
355static u32 (*_omap2_sram_reprogram_gpmc)(u32 perf_level); 355static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
356u32 omap2_sram_reprogram_gpmc(u32 perf_level) 356 u32 sdrc_actim_ctrla,
357{ 357 u32 sdrc_actim_ctrlb,
358 if (!_omap2_sram_reprogram_gpmc) 358 u32 m2);
359 omap_sram_error(); 359u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
360 360 u32 sdrc_actim_ctrlb, u32 m2)
361 return _omap2_sram_reprogram_gpmc(perf_level);
362}
363
364static u32 (*_omap2_sram_configure_core_dpll)(u32 m, u32 n,
365 u32 freqsel, u32 m2);
366u32 omap2_sram_configure_core_dpll(u32 m, u32 n, u32 freqsel, u32 m2)
367{ 361{
368 if (!_omap2_sram_configure_core_dpll) 362 if (!_omap3_sram_configure_core_dpll)
369 omap_sram_error(); 363 omap_sram_error();
370 364
371 return _omap2_sram_configure_core_dpll(m, n, freqsel, m2); 365 return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
366 sdrc_actim_ctrla,
367 sdrc_actim_ctrlb, m2);
372} 368}
373 369
374/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */ 370/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
@@ -376,31 +372,16 @@ void restore_sram_functions(void)
376{ 372{
377 omap_sram_ceil = omap_sram_base + omap_sram_size; 373 omap_sram_ceil = omap_sram_base + omap_sram_size;
378 374
379 _omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc, 375 _omap3_sram_configure_core_dpll =
380 omap34xx_sram_reprogram_gpmc_sz); 376 omap_sram_push(omap3_sram_configure_core_dpll,
381 377 omap3_sram_configure_core_dpll_sz);
382 _omap2_sram_configure_core_dpll =
383 omap_sram_push(omap34xx_sram_configure_core_dpll,
384 omap34xx_sram_configure_core_dpll_sz);
385} 378}
386 379
387int __init omap34xx_sram_init(void) 380int __init omap34xx_sram_init(void)
388{ 381{
389 _omap2_sram_ddr_init = omap_sram_push(omap34xx_sram_ddr_init, 382 _omap3_sram_configure_core_dpll =
390 omap34xx_sram_ddr_init_sz); 383 omap_sram_push(omap3_sram_configure_core_dpll,
391 384 omap3_sram_configure_core_dpll_sz);
392 _omap2_sram_reprogram_sdrc = omap_sram_push(omap34xx_sram_reprogram_sdrc,
393 omap34xx_sram_reprogram_sdrc_sz);
394
395 _omap2_set_prcm = omap_sram_push(omap34xx_sram_set_prcm,
396 omap34xx_sram_set_prcm_sz);
397
398 _omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc,
399 omap34xx_sram_reprogram_gpmc_sz);
400
401 _omap2_sram_configure_core_dpll =
402 omap_sram_push(omap34xx_sram_configure_core_dpll,
403 omap34xx_sram_configure_core_dpll_sz);
404 385
405 return 0; 386 return 0;
406} 387}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 09:19:25 -0500