diff options
| author | Richard Genoud <richard.genoud@gmail.com> | 2013-03-11 10:12:40 -0400 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@atmel.com> | 2013-03-13 05:25:24 -0400 |
| commit | 7f06472f1c3281abceea36059f94e099bfe4698f (patch) | |
| tree | fba084e7e81897d4bc0a175b7e5a401e9ff327f6 /arch/arm | |
| parent | f04feec2501774fe20fc7c77b5a16b9e23b36f95 (diff) | |
ARM: at91: dt: at91sam9x5: complete NAND pinctrl
There was only chip enable and readdy/busy pins for the nand controller.
This add the rest of the pins.
pinctrl_nand_16bits contains the specific muxes for 16 bits NANDs.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/at91sam9x5.dtsi | 28 |
1 files changed, 26 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 9b5d0480d7ee..a98c0d50fbbe 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi | |||
| @@ -238,8 +238,32 @@ | |||
| 238 | nand { | 238 | nand { |
| 239 | pinctrl_nand: nand-0 { | 239 | pinctrl_nand: nand-0 { |
| 240 | atmel,pins = | 240 | atmel,pins = |
| 241 | <3 4 0x0 0x1 /* PD4 gpio Chip Enable pin pull_up */ | 241 | <3 0 0x1 0x0 /* PD0 periph A Read Enable */ |
| 242 | 3 5 0x0 0x1>; /* PD5 gpio RDY/BUSY pin pull_up */ | 242 | 3 1 0x1 0x0 /* PD1 periph A Write Enable */ |
| 243 | 3 2 0x1 0x0 /* PD2 periph A Address Latch Enable */ | ||
| 244 | 3 3 0x1 0x0 /* PD3 periph A Command Latch Enable */ | ||
| 245 | 3 4 0x0 0x1 /* PD4 gpio Chip Enable pin pull_up */ | ||
| 246 | 3 5 0x0 0x1 /* PD5 gpio RDY/BUSY pin pull_up */ | ||
| 247 | 3 6 0x1 0x0 /* PD6 periph A Data bit 0 */ | ||
| 248 | 3 7 0x1 0x0 /* PD7 periph A Data bit 1 */ | ||
| 249 | 3 8 0x1 0x0 /* PD8 periph A Data bit 2 */ | ||
| 250 | 3 9 0x1 0x0 /* PD9 periph A Data bit 3 */ | ||
| 251 | 3 10 0x1 0x0 /* PD10 periph A Data bit 4 */ | ||
| 252 | 3 11 0x1 0x0 /* PD11 periph A Data bit 5 */ | ||
| 253 | 3 12 0x1 0x0 /* PD12 periph A Data bit 6 */ | ||
| 254 | 3 13 0x1 0x0>; /* PD13 periph A Data bit 7 */ | ||
| 255 | }; | ||
| 256 | |||
| 257 | pinctrl_nand_16bits: nand_16bits-0 { | ||
| 258 | atmel,pins = | ||
| 259 | <3 14 0x1 0x0 /* PD14 periph A Data bit 8 */ | ||
| 260 | 3 15 0x1 0x0 /* PD15 periph A Data bit 9 */ | ||
| 261 | 3 16 0x1 0x0 /* PD16 periph A Data bit 10 */ | ||
| 262 | 3 17 0x1 0x0 /* PD17 periph A Data bit 11 */ | ||
| 263 | 3 18 0x1 0x0 /* PD18 periph A Data bit 12 */ | ||
| 264 | 3 19 0x1 0x0 /* PD19 periph A Data bit 13 */ | ||
| 265 | 3 20 0x1 0x0 /* PD20 periph A Data bit 14 */ | ||
| 266 | 3 21 0x1 0x0>; /* PD21 periph A Data bit 15 */ | ||
| 243 | }; | 267 | }; |
| 244 | }; | 268 | }; |
| 245 | 269 | ||