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authorArnd Bergmann <arnd@arndb.de>2013-04-09 10:32:20 -0400
committerArnd Bergmann <arnd@arndb.de>2013-04-09 10:32:20 -0400
commit6cd2f8e7da502272248f4bdefcb952a68318e02b (patch)
tree849530c371ea05bbdc516c553cbe95da88e2b663 /arch/arm
parent3be1812ea3b7193ee1a3993cadf9a7985121cf16 (diff)
parent38be85de698ef3f2755ee0eabf520530757860aa (diff)
Merge tag 'tegra-for-3.10-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc
From Stephen Warren <swarren@wwwdotorg.org>: ARM: tegra: core SoC support development This branch includes major development on the core Tegra SoC support code in the mach-tegra directory: * SMP support for Tegra114. * Exposes SoC chip ID and revision through standard sysfs files. * System-level suspend/resume for Tegra20/30. At present, this only supports "LP2" mode (CPU power-down), but provides the basis to implement "LP0"/"LP1" (various levels of core/chip power-down) in the hopefully near future. * A minor cleanup of a duplicate include, which was introduced in this branch. This branch is based on the previous cleanup pull request. * tag 'tegra-for-3.10-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: ARM: tegra: pm: remove duplicated include from pm.c ARM: tegra: cpuidle: remove redundant parameters for powered-down mode ARM: tegra: pm: add platform suspend support ARM: dt: tegra: add bindings of power management configurations for PMC ARM: tegra: irq: add wake up handling gpio: tegra: add gpio wakeup source handling ARM: tegra: moving the CPU power timer function to PMC driver ARM: tegra: add clock source of PMC to device trees ARM: tegra: add speedo-based process id for Tegra114 ARM: tegra: expose chip ID and revision ARM: tegra: bring up secondary CPU for Tegra114 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/boot/dts/tegra114-dalmore.dts13
-rw-r--r--arch/arm/boot/dts/tegra114-pluto.dts13
-rw-r--r--arch/arm/boot/dts/tegra114.dtsi2
-rw-r--r--arch/arm/boot/dts/tegra20-colibri-512.dtsi13
-rw-r--r--arch/arm/boot/dts/tegra20-harmony.dts13
-rw-r--r--arch/arm/boot/dts/tegra20-paz00.dts13
-rw-r--r--arch/arm/boot/dts/tegra20-seaboard.dts13
-rw-r--r--arch/arm/boot/dts/tegra20-tamonten.dtsi13
-rw-r--r--arch/arm/boot/dts/tegra20-trimslice.dts13
-rw-r--r--arch/arm/boot/dts/tegra20-ventana.dts13
-rw-r--r--arch/arm/boot/dts/tegra20-whistler.dts13
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi2
-rw-r--r--arch/arm/boot/dts/tegra30-beaver.dts13
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dtsi13
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi2
-rw-r--r--arch/arm/mach-tegra/Makefile1
-rw-r--r--arch/arm/mach-tegra/common.c5
-rw-r--r--arch/arm/mach-tegra/cpuidle-tegra20.c6
-rw-r--r--arch/arm/mach-tegra/cpuidle-tegra30.c6
-rw-r--r--arch/arm/mach-tegra/fuse.c4
-rw-r--r--arch/arm/mach-tegra/fuse.h7
-rw-r--r--arch/arm/mach-tegra/irq.c96
-rw-r--r--arch/arm/mach-tegra/irq.h6
-rw-r--r--arch/arm/mach-tegra/platsmp.c8
-rw-r--r--arch/arm/mach-tegra/pm.c131
-rw-r--r--arch/arm/mach-tegra/pm.h17
-rw-r--r--arch/arm/mach-tegra/pmc.c162
-rw-r--r--arch/arm/mach-tegra/pmc.h14
-rw-r--r--arch/arm/mach-tegra/tegra.c29
-rw-r--r--arch/arm/mach-tegra/tegra114_speedo.c104
31 files changed, 695 insertions, 64 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1e8742b5f839..b6f3dd8ec48f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -673,6 +673,7 @@ config ARCH_TEGRA
673 select HAVE_CLK 673 select HAVE_CLK
674 select HAVE_SMP 674 select HAVE_SMP
675 select MIGHT_HAVE_CACHE_L2X0 675 select MIGHT_HAVE_CACHE_L2X0
676 select SOC_BUS
676 select SPARSE_IRQ 677 select SPARSE_IRQ
677 select USE_OF 678 select USE_OF
678 help 679 help
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index a30aca62658a..6ebc1b704190 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -18,4 +18,17 @@
18 pmc { 18 pmc {
19 nvidia,invert-interrupt; 19 nvidia,invert-interrupt;
20 }; 20 };
21
22 clocks {
23 compatible = "simple-bus";
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 clk32k_in: clock {
28 compatible = "fixed-clock";
29 reg=<0>;
30 #clock-cells = <0>;
31 clock-frequency = <32768>;
32 };
33 };
21}; 34};
diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts
index 9bea8f57aa47..5deb8692b350 100644
--- a/arch/arm/boot/dts/tegra114-pluto.dts
+++ b/arch/arm/boot/dts/tegra114-pluto.dts
@@ -18,4 +18,17 @@
18 pmc { 18 pmc {
19 nvidia,invert-interrupt; 19 nvidia,invert-interrupt;
20 }; 20 };
21
22 clocks {
23 compatible = "simple-bus";
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 clk32k_in: clock {
28 compatible = "fixed-clock";
29 reg=<0>;
30 #clock-cells = <0>;
31 clock-frequency = <32768>;
32 };
33 };
21}; 34};
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index e4ddeddcd437..c0b527d15fda 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -101,6 +101,8 @@
101 pmc { 101 pmc {
102 compatible = "nvidia,tegra114-pmc"; 102 compatible = "nvidia,tegra114-pmc";
103 reg = <0x7000e400 0x400>; 103 reg = <0x7000e400 0x400>;
104 clocks = <&tegra_car 261>, <&clk32k_in>;
105 clock-names = "pclk", "clk32k_in";
104 }; 106 };
105 107
106 iommu { 108 iommu {
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index cb73e62d61a9..4e3afdef28a8 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -447,6 +447,19 @@
447 cd-gpios = <&gpio 23 1>; /* gpio PC7 */ 447 cd-gpios = <&gpio 23 1>; /* gpio PC7 */
448 }; 448 };
449 449
450 clocks {
451 compatible = "simple-bus";
452 #address-cells = <1>;
453 #size-cells = <0>;
454
455 clk32k_in: clock {
456 compatible = "fixed-clock";
457 reg=<0>;
458 #clock-cells = <0>;
459 clock-frequency = <32768>;
460 };
461 };
462
450 sound { 463 sound {
451 compatible = "nvidia,tegra-audio-wm9712-colibri_t20", 464 compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
452 "nvidia,tegra-audio-wm9712"; 465 "nvidia,tegra-audio-wm9712";
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 1f79c0debb05..ae9d5a20834e 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -451,6 +451,19 @@
451 bus-width = <8>; 451 bus-width = <8>;
452 }; 452 };
453 453
454 clocks {
455 compatible = "simple-bus";
456 #address-cells = <1>;
457 #size-cells = <0>;
458
459 clk32k_in: clock {
460 compatible = "fixed-clock";
461 reg=<0>;
462 #clock-cells = <0>;
463 clock-frequency = <32768>;
464 };
465 };
466
454 kbc { 467 kbc {
455 status = "okay"; 468 status = "okay";
456 nvidia,debounce-delay-ms = <2>; 469 nvidia,debounce-delay-ms = <2>;
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 9db36da8e023..fd60940e4063 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -447,6 +447,19 @@
447 bus-width = <8>; 447 bus-width = <8>;
448 }; 448 };
449 449
450 clocks {
451 compatible = "simple-bus";
452 #address-cells = <1>;
453 #size-cells = <0>;
454
455 clk32k_in: clock {
456 compatible = "fixed-clock";
457 reg=<0>;
458 #clock-cells = <0>;
459 clock-frequency = <32768>;
460 };
461 };
462
450 gpio-keys { 463 gpio-keys {
451 compatible = "gpio-keys"; 464 compatible = "gpio-keys";
452 465
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 715a8b8dd9cd..4ee700a33ca5 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -595,6 +595,19 @@
595 bus-width = <8>; 595 bus-width = <8>;
596 }; 596 };
597 597
598 clocks {
599 compatible = "simple-bus";
600 #address-cells = <1>;
601 #size-cells = <0>;
602
603 clk32k_in: clock {
604 compatible = "fixed-clock";
605 reg=<0>;
606 #clock-cells = <0>;
607 clock-frequency = <32768>;
608 };
609 };
610
598 gpio-keys { 611 gpio-keys {
599 compatible = "gpio-keys"; 612 compatible = "gpio-keys";
600 613
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 6e9d91fc6195..c19025725918 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -471,6 +471,19 @@
471 status = "okay"; 471 status = "okay";
472 }; 472 };
473 473
474 clocks {
475 compatible = "simple-bus";
476 #address-cells = <1>;
477 #size-cells = <0>;
478
479 clk32k_in: clock {
480 compatible = "fixed-clock";
481 reg=<0>;
482 #clock-cells = <0>;
483 clock-frequency = <32768>;
484 };
485 };
486
474 regulators { 487 regulators {
475 compatible = "simple-bus"; 488 compatible = "simple-bus";
476 489
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 98f3e44f2a51..a9f3f06580f5 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -330,6 +330,19 @@
330 bus-width = <4>; 330 bus-width = <4>;
331 }; 331 };
332 332
333 clocks {
334 compatible = "simple-bus";
335 #address-cells = <1>;
336 #size-cells = <0>;
337
338 clk32k_in: clock {
339 compatible = "fixed-clock";
340 reg=<0>;
341 #clock-cells = <0>;
342 clock-frequency = <32768>;
343 };
344 };
345
333 poweroff { 346 poweroff {
334 compatible = "gpio-poweroff"; 347 compatible = "gpio-poweroff";
335 gpios = <&gpio 191 1>; /* gpio PX7, active low */ 348 gpios = <&gpio 191 1>; /* gpio PX7, active low */
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 4aef56f2d96a..f544806e9618 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -531,6 +531,19 @@
531 bus-width = <8>; 531 bus-width = <8>;
532 }; 532 };
533 533
534 clocks {
535 compatible = "simple-bus";
536 #address-cells = <1>;
537 #size-cells = <0>;
538
539 clk32k_in: clock {
540 compatible = "fixed-clock";
541 reg=<0>;
542 #clock-cells = <0>;
543 clock-frequency = <32768>;
544 };
545 };
546
534 regulators { 547 regulators {
535 compatible = "simple-bus"; 548 compatible = "simple-bus";
536 #address-cells = <1>; 549 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index 5762188c60ad..258cf945f515 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -520,6 +520,19 @@
520 bus-width = <8>; 520 bus-width = <8>;
521 }; 521 };
522 522
523 clocks {
524 compatible = "simple-bus";
525 #address-cells = <1>;
526 #size-cells = <0>;
527
528 clk32k_in: clock {
529 compatible = "fixed-clock";
530 reg=<0>;
531 #clock-cells = <0>;
532 clock-frequency = <32768>;
533 };
534 };
535
523 kbc { 536 kbc {
524 status = "okay"; 537 status = "okay";
525 nvidia,debounce-delay-ms = <20>; 538 nvidia,debounce-delay-ms = <20>;
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index ad64c8cc9da7..fc7febc2b386 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -418,6 +418,8 @@
418 pmc { 418 pmc {
419 compatible = "nvidia,tegra20-pmc"; 419 compatible = "nvidia,tegra20-pmc";
420 reg = <0x7000e400 0x400>; 420 reg = <0x7000e400 0x400>;
421 clocks = <&tegra_car 110>, <&clk32k_in>;
422 clock-names = "pclk", "clk32k_in";
421 }; 423 };
422 424
423 memory-controller@7000f000 { 425 memory-controller@7000f000 {
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 0a2cd24df853..6248b2445b32 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -268,6 +268,19 @@
268 bus-width = <8>; 268 bus-width = <8>;
269 }; 269 };
270 270
271 clocks {
272 compatible = "simple-bus";
273 #address-cells = <1>;
274 #size-cells = <0>;
275
276 clk32k_in: clock {
277 compatible = "fixed-clock";
278 reg=<0>;
279 #clock-cells = <0>;
280 clock-frequency = <32768>;
281 };
282 };
283
271 regulators { 284 regulators {
272 compatible = "simple-bus"; 285 compatible = "simple-bus";
273 #address-cells = <1>; 286 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 3e2d21018a5b..65bf2b63174e 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -322,6 +322,19 @@
322 bus-width = <8>; 322 bus-width = <8>;
323 }; 323 };
324 324
325 clocks {
326 compatible = "simple-bus";
327 #address-cells = <1>;
328 #size-cells = <0>;
329
330 clk32k_in: clock {
331 compatible = "fixed-clock";
332 reg=<0>;
333 #clock-cells = <0>;
334 clock-frequency = <32768>;
335 };
336 };
337
325 regulators { 338 regulators {
326 compatible = "simple-bus"; 339 compatible = "simple-bus";
327 #address-cells = <1>; 340 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 9491edf1a067..9fe7a92b4c85 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -427,6 +427,8 @@
427 pmc { 427 pmc {
428 compatible = "nvidia,tegra30-pmc"; 428 compatible = "nvidia,tegra30-pmc";
429 reg = <0x7000e400 0x400>; 429 reg = <0x7000e400 0x400>;
430 clocks = <&tegra_car 218>, <&clk32k_in>;
431 clock-names = "pclk", "clk32k_in";
430 }; 432 };
431 433
432 memory-controller { 434 memory-controller {
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 92703f955a37..e40326d0e29f 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
28obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o 28obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o
29obj-$(CONFIG_TEGRA_PCI) += pcie.o 29obj-$(CONFIG_TEGRA_PCI) += pcie.o
30 30
31obj-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114_speedo.o
31ifeq ($(CONFIG_CPU_IDLE),y) 32ifeq ($(CONFIG_CPU_IDLE),y)
32obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o 33obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o
33endif 34endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index f0315c95c76d..eb1f3c8c74cc 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -33,6 +33,7 @@
33#include "common.h" 33#include "common.h"
34#include "fuse.h" 34#include "fuse.h"
35#include "iomap.h" 35#include "iomap.h"
36#include "irq.h"
36#include "pmc.h" 37#include "pmc.h"
37#include "apbio.h" 38#include "apbio.h"
38#include "sleep.h" 39#include "sleep.h"
@@ -61,8 +62,10 @@ u32 tegra_uart_config[4] = {
61void __init tegra_dt_init_irq(void) 62void __init tegra_dt_init_irq(void)
62{ 63{
63 tegra_clocks_init(); 64 tegra_clocks_init();
65 tegra_pmc_init();
64 tegra_init_irq(); 66 tegra_init_irq();
65 irqchip_init(); 67 irqchip_init();
68 tegra_legacy_irq_syscore_init();
66} 69}
67#endif 70#endif
68 71
@@ -100,12 +103,12 @@ void __init tegra_init_early(void)
100 tegra_apb_io_init(); 103 tegra_apb_io_init();
101 tegra_init_fuse(); 104 tegra_init_fuse();
102 tegra_init_cache(); 105 tegra_init_cache();
103 tegra_pmc_init();
104 tegra_powergate_init(); 106 tegra_powergate_init();
105 tegra_hotplug_init(); 107 tegra_hotplug_init();
106} 108}
107 109
108void __init tegra_init_late(void) 110void __init tegra_init_late(void)
109{ 111{
112 tegra_init_suspend();
110 tegra_powergate_debugfs_init(); 113 tegra_powergate_debugfs_init();
111} 114}
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
index 825ced4f7a40..8bbbdebed882 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -130,10 +130,6 @@ static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
130 struct cpuidle_driver *drv, 130 struct cpuidle_driver *drv,
131 int index) 131 int index)
132{ 132{
133 struct cpuidle_state *state = &drv->states[index];
134 u32 cpu_on_time = state->exit_latency;
135 u32 cpu_off_time = state->target_residency - state->exit_latency;
136
137 while (tegra20_cpu_is_resettable_soon()) 133 while (tegra20_cpu_is_resettable_soon())
138 cpu_relax(); 134 cpu_relax();
139 135
@@ -142,7 +138,7 @@ static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
142 138
143 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu); 139 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
144 140
145 tegra_idle_lp2_last(cpu_on_time, cpu_off_time); 141 tegra_idle_lp2_last();
146 142
147 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); 143 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
148 144
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
index 80445ed33d95..c0931c8bb3e5 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -72,10 +72,6 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
72 struct cpuidle_driver *drv, 72 struct cpuidle_driver *drv,
73 int index) 73 int index)
74{ 74{
75 struct cpuidle_state *state = &drv->states[index];
76 u32 cpu_on_time = state->exit_latency;
77 u32 cpu_off_time = state->target_residency - state->exit_latency;
78
79 /* All CPUs entering LP2 is not working. 75 /* All CPUs entering LP2 is not working.
80 * Don't let CPU0 enter LP2 when any secondary CPU is online. 76 * Don't let CPU0 enter LP2 when any secondary CPU is online.
81 */ 77 */
@@ -86,7 +82,7 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
86 82
87 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu); 83 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
88 84
89 tegra_idle_lp2_last(cpu_on_time, cpu_off_time); 85 tegra_idle_lp2_last();
90 86
91 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); 87 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
92 88
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index f7db0782a6b6..e035cd284a6e 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -2,6 +2,7 @@
2 * arch/arm/mach-tegra/fuse.c 2 * arch/arm/mach-tegra/fuse.c
3 * 3 *
4 * Copyright (C) 2010 Google, Inc. 4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
5 * 6 *
6 * Author: 7 * Author:
7 * Colin Cross <ccross@android.com> 8 * Colin Cross <ccross@android.com>
@@ -137,6 +138,9 @@ void tegra_init_fuse(void)
137 tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT; 138 tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT;
138 tegra_init_speedo_data = &tegra30_init_speedo_data; 139 tegra_init_speedo_data = &tegra30_init_speedo_data;
139 break; 140 break;
141 case TEGRA114:
142 tegra_init_speedo_data = &tegra114_init_speedo_data;
143 break;
140 default: 144 default:
141 pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id); 145 pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id);
142 tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT; 146 tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index da78434678c7..aacc00d05980 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright (C) 2010 Google, Inc. 2 * Copyright (C) 2010 Google, Inc.
3 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
3 * 4 *
4 * Author: 5 * Author:
5 * Colin Cross <ccross@android.com> 6 * Colin Cross <ccross@android.com>
@@ -66,4 +67,10 @@ void tegra30_init_speedo_data(void);
66static inline void tegra30_init_speedo_data(void) {} 67static inline void tegra30_init_speedo_data(void) {}
67#endif 68#endif
68 69
70#ifdef CONFIG_ARCH_TEGRA_114_SOC
71void tegra114_init_speedo_data(void);
72#else
73static inline void tegra114_init_speedo_data(void) {}
74#endif
75
69#endif 76#endif
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 1952e82797cc..0de4eed1493d 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -4,7 +4,7 @@
4 * Author: 4 * Author:
5 * Colin Cross <ccross@android.com> 5 * Colin Cross <ccross@android.com>
6 * 6 *
7 * Copyright (C) 2010, NVIDIA Corporation 7 * Copyright (C) 2010,2013, NVIDIA Corporation
8 * 8 *
9 * This software is licensed under the terms of the GNU General Public 9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and 10 * License version 2, as published by the Free Software Foundation, and
@@ -23,6 +23,7 @@
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/of.h> 24#include <linux/of.h>
25#include <linux/irqchip/arm-gic.h> 25#include <linux/irqchip/arm-gic.h>
26#include <linux/syscore_ops.h>
26 27
27#include "board.h" 28#include "board.h"
28#include "iomap.h" 29#include "iomap.h"
@@ -43,6 +44,7 @@
43#define ICTLR_COP_IEP_CLASS 0x3c 44#define ICTLR_COP_IEP_CLASS 0x3c
44 45
45#define FIRST_LEGACY_IRQ 32 46#define FIRST_LEGACY_IRQ 32
47#define TEGRA_MAX_NUM_ICTLRS 5
46 48
47#define SGI_MASK 0xFFFF 49#define SGI_MASK 0xFFFF
48 50
@@ -56,6 +58,15 @@ static void __iomem *ictlr_reg_base[] = {
56 IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE), 58 IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE),
57}; 59};
58 60
61#ifdef CONFIG_PM_SLEEP
62static u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
63static u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
64static u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
65static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
66
67static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
68#endif
69
59bool tegra_pending_sgi(void) 70bool tegra_pending_sgi(void)
60{ 71{
61 u32 pending_set; 72 u32 pending_set;
@@ -125,6 +136,87 @@ static int tegra_retrigger(struct irq_data *d)
125 return 1; 136 return 1;
126} 137}
127 138
139#ifdef CONFIG_PM_SLEEP
140static int tegra_set_wake(struct irq_data *d, unsigned int enable)
141{
142 u32 irq = d->irq;
143 u32 index, mask;
144
145 if (irq < FIRST_LEGACY_IRQ ||
146 irq >= FIRST_LEGACY_IRQ + num_ictlrs * 32)
147 return -EINVAL;
148
149 index = ((irq - FIRST_LEGACY_IRQ) / 32);
150 mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
151 if (enable)
152 ictlr_wake_mask[index] |= mask;
153 else
154 ictlr_wake_mask[index] &= ~mask;
155
156 return 0;
157}
158
159static int tegra_legacy_irq_suspend(void)
160{
161 unsigned long flags;
162 int i;
163
164 local_irq_save(flags);
165 for (i = 0; i < num_ictlrs; i++) {
166 void __iomem *ictlr = ictlr_reg_base[i];
167 /* Save interrupt state */
168 cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER);
169 cpu_iep[i] = readl_relaxed(ictlr + ICTLR_CPU_IEP_CLASS);
170 cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER);
171 cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);
172
173 /* Disable COP interrupts */
174 writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
175
176 /* Disable CPU interrupts */
177 writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
178
179 /* Enable the wakeup sources of ictlr */
180 writel_relaxed(ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET);
181 }
182 local_irq_restore(flags);
183
184 return 0;
185}
186
187static void tegra_legacy_irq_resume(void)
188{
189 unsigned long flags;
190 int i;
191
192 local_irq_save(flags);
193 for (i = 0; i < num_ictlrs; i++) {
194 void __iomem *ictlr = ictlr_reg_base[i];
195 writel_relaxed(cpu_iep[i], ictlr + ICTLR_CPU_IEP_CLASS);
196 writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
197 writel_relaxed(cpu_ier[i], ictlr + ICTLR_CPU_IER_SET);
198 writel_relaxed(cop_iep[i], ictlr + ICTLR_COP_IEP_CLASS);
199 writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
200 writel_relaxed(cop_ier[i], ictlr + ICTLR_COP_IER_SET);
201 }
202 local_irq_restore(flags);
203}
204
205static struct syscore_ops tegra_legacy_irq_syscore_ops = {
206 .suspend = tegra_legacy_irq_suspend,
207 .resume = tegra_legacy_irq_resume,
208};
209
210int tegra_legacy_irq_syscore_init(void)
211{
212 register_syscore_ops(&tegra_legacy_irq_syscore_ops);
213
214 return 0;
215}
216#else
217#define tegra_set_wake NULL
218#endif
219
128void __init tegra_init_irq(void) 220void __init tegra_init_irq(void)
129{ 221{
130 int i; 222 int i;
@@ -150,6 +242,8 @@ void __init tegra_init_irq(void)
150 gic_arch_extn.irq_mask = tegra_mask; 242 gic_arch_extn.irq_mask = tegra_mask;
151 gic_arch_extn.irq_unmask = tegra_unmask; 243 gic_arch_extn.irq_unmask = tegra_unmask;
152 gic_arch_extn.irq_retrigger = tegra_retrigger; 244 gic_arch_extn.irq_retrigger = tegra_retrigger;
245 gic_arch_extn.irq_set_wake = tegra_set_wake;
246 gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND;
153 247
154 /* 248 /*
155 * Check if there is a devicetree present, since the GIC will be 249 * Check if there is a devicetree present, since the GIC will be
diff --git a/arch/arm/mach-tegra/irq.h b/arch/arm/mach-tegra/irq.h
index 5142649bba05..bc05ce5613fb 100644
--- a/arch/arm/mach-tegra/irq.h
+++ b/arch/arm/mach-tegra/irq.h
@@ -19,4 +19,10 @@
19 19
20bool tegra_pending_sgi(void); 20bool tegra_pending_sgi(void);
21 21
22#ifdef CONFIG_PM_SLEEP
23int tegra_legacy_irq_syscore_init(void);
24#else
25static inline int tegra_legacy_irq_syscore_init(void) { return 0; }
26#endif
27
22#endif 28#endif
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 601bd0c3f983..516aab28fe34 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -146,6 +146,12 @@ remove_clamps:
146 return 0; 146 return 0;
147} 147}
148 148
149static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle)
150{
151 cpu = cpu_logical_map(cpu);
152 return tegra_pmc_cpu_power_on(cpu);
153}
154
149static int __cpuinit tegra_boot_secondary(unsigned int cpu, 155static int __cpuinit tegra_boot_secondary(unsigned int cpu,
150 struct task_struct *idle) 156 struct task_struct *idle)
151{ 157{
@@ -153,6 +159,8 @@ static int __cpuinit tegra_boot_secondary(unsigned int cpu,
153 return tegra20_boot_secondary(cpu, idle); 159 return tegra20_boot_secondary(cpu, idle);
154 if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30) 160 if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30)
155 return tegra30_boot_secondary(cpu, idle); 161 return tegra30_boot_secondary(cpu, idle);
162 if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114)
163 return tegra114_boot_secondary(cpu, idle);
156 164
157 return -EINVAL; 165 return -EINVAL;
158} 166}
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index acacbe8d1afc..d647e9e0e197 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -22,7 +22,7 @@
22#include <linux/cpumask.h> 22#include <linux/cpumask.h>
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/cpu_pm.h> 24#include <linux/cpu_pm.h>
25#include <linux/clk.h> 25#include <linux/suspend.h>
26#include <linux/err.h> 26#include <linux/err.h>
27#include <linux/clk/tegra.h> 27#include <linux/clk/tegra.h>
28 28
@@ -37,52 +37,13 @@
37#include "reset.h" 37#include "reset.h"
38#include "flowctrl.h" 38#include "flowctrl.h"
39#include "fuse.h" 39#include "fuse.h"
40#include "pmc.h"
40#include "sleep.h" 41#include "sleep.h"
41 42
42#define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */
43
44#define PMC_CTRL 0x0
45#define PMC_CPUPWRGOOD_TIMER 0xc8
46#define PMC_CPUPWROFF_TIMER 0xcc
47
48#ifdef CONFIG_PM_SLEEP 43#ifdef CONFIG_PM_SLEEP
49static DEFINE_SPINLOCK(tegra_lp2_lock); 44static DEFINE_SPINLOCK(tegra_lp2_lock);
50static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
51static struct clk *tegra_pclk;
52void (*tegra_tear_down_cpu)(void); 45void (*tegra_tear_down_cpu)(void);
53 46
54static void set_power_timers(unsigned long us_on, unsigned long us_off)
55{
56 unsigned long long ticks;
57 unsigned long long pclk;
58 unsigned long rate;
59 static unsigned long tegra_last_pclk;
60
61 if (tegra_pclk == NULL) {
62 tegra_pclk = clk_get_sys(NULL, "pclk");
63 WARN_ON(IS_ERR(tegra_pclk));
64 }
65
66 rate = clk_get_rate(tegra_pclk);
67
68 if (WARN_ON_ONCE(rate <= 0))
69 pclk = 100000000;
70 else
71 pclk = rate;
72
73 if ((rate != tegra_last_pclk)) {
74 ticks = (us_on * pclk) + 999999ull;
75 do_div(ticks, 1000000);
76 writel((unsigned long)ticks, pmc + PMC_CPUPWRGOOD_TIMER);
77
78 ticks = (us_off * pclk) + 999999ull;
79 do_div(ticks, 1000000);
80 writel((unsigned long)ticks, pmc + PMC_CPUPWROFF_TIMER);
81 wmb();
82 }
83 tegra_last_pclk = pclk;
84}
85
86/* 47/*
87 * restore_cpu_complex 48 * restore_cpu_complex
88 * 49 *
@@ -173,16 +134,9 @@ static int tegra_sleep_cpu(unsigned long v2p)
173 return 0; 134 return 0;
174} 135}
175 136
176void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time) 137void tegra_idle_lp2_last(void)
177{ 138{
178 u32 mode; 139 tegra_pmc_pm_set(TEGRA_SUSPEND_LP2);
179
180 /* Only the last cpu down does the final suspend steps */
181 mode = readl(pmc + PMC_CTRL);
182 mode |= TEGRA_POWER_CPU_PWRREQ_OE;
183 writel(mode, pmc + PMC_CTRL);
184
185 set_power_timers(cpu_on_time, cpu_off_time);
186 140
187 cpu_cluster_pm_enter(); 141 cpu_cluster_pm_enter();
188 suspend_cpu_complex(); 142 suspend_cpu_complex();
@@ -192,4 +146,81 @@ void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time)
192 restore_cpu_complex(); 146 restore_cpu_complex();
193 cpu_cluster_pm_exit(); 147 cpu_cluster_pm_exit();
194} 148}
149
150enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
151 enum tegra_suspend_mode mode)
152{
153 /* Tegra114 didn't support any suspending mode yet. */
154 if (tegra_chip_id == TEGRA114)
155 return TEGRA_SUSPEND_NONE;
156
157 /*
158 * The Tegra devices only support suspending to LP2 currently.
159 */
160 if (mode > TEGRA_SUSPEND_LP2)
161 return TEGRA_SUSPEND_LP2;
162
163 return mode;
164}
165
166static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
167 [TEGRA_SUSPEND_NONE] = "none",
168 [TEGRA_SUSPEND_LP2] = "LP2",
169 [TEGRA_SUSPEND_LP1] = "LP1",
170 [TEGRA_SUSPEND_LP0] = "LP0",
171};
172
173static int __cpuinit tegra_suspend_enter(suspend_state_t state)
174{
175 enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
176
177 if (WARN_ON(mode < TEGRA_SUSPEND_NONE ||
178 mode >= TEGRA_MAX_SUSPEND_MODE))
179 return -EINVAL;
180
181 pr_info("Entering suspend state %s\n", lp_state[mode]);
182
183 tegra_pmc_pm_set(mode);
184
185 local_fiq_disable();
186
187 suspend_cpu_complex();
188 switch (mode) {
189 case TEGRA_SUSPEND_LP2:
190 tegra_set_cpu_in_lp2(0);
191 break;
192 default:
193 break;
194 }
195
196 cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
197
198 switch (mode) {
199 case TEGRA_SUSPEND_LP2:
200 tegra_clear_cpu_in_lp2(0);
201 break;
202 default:
203 break;
204 }
205 restore_cpu_complex();
206
207 local_fiq_enable();
208
209 return 0;
210}
211
212static const struct platform_suspend_ops tegra_suspend_ops = {
213 .valid = suspend_valid_only_mem,
214 .enter = tegra_suspend_enter,
215};
216
217void __init tegra_init_suspend(void)
218{
219 if (tegra_pmc_get_suspend_mode() == TEGRA_SUSPEND_NONE)
220 return;
221
222 tegra_pmc_suspend_init();
223
224 suspend_set_ops(&tegra_suspend_ops);
225}
195#endif 226#endif
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
index 787335cc964c..9d2d038bf12e 100644
--- a/arch/arm/mach-tegra/pm.h
+++ b/arch/arm/mach-tegra/pm.h
@@ -21,6 +21,8 @@
21#ifndef _MACH_TEGRA_PM_H_ 21#ifndef _MACH_TEGRA_PM_H_
22#define _MACH_TEGRA_PM_H_ 22#define _MACH_TEGRA_PM_H_
23 23
24#include "pmc.h"
25
24extern unsigned long l2x0_saved_regs_addr; 26extern unsigned long l2x0_saved_regs_addr;
25 27
26void save_cpu_arch_register(void); 28void save_cpu_arch_register(void);
@@ -29,7 +31,20 @@ void restore_cpu_arch_register(void);
29void tegra_clear_cpu_in_lp2(int phy_cpu_id); 31void tegra_clear_cpu_in_lp2(int phy_cpu_id);
30bool tegra_set_cpu_in_lp2(int phy_cpu_id); 32bool tegra_set_cpu_in_lp2(int phy_cpu_id);
31 33
32void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time); 34void tegra_idle_lp2_last(void);
33extern void (*tegra_tear_down_cpu)(void); 35extern void (*tegra_tear_down_cpu)(void);
34 36
37#ifdef CONFIG_PM_SLEEP
38enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
39 enum tegra_suspend_mode mode);
40void tegra_init_suspend(void);
41#else
42enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
43 enum tegra_suspend_mode mode)
44{
45 return TEGRA_SUSPEND_NONE;
46}
47static inline void tegra_init_suspend(void) {}
48#endif
49
35#endif /* _MACH_TEGRA_PM_H_ */ 50#endif /* _MACH_TEGRA_PM_H_ */
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
index b30e921cc3a9..32360e540ce6 100644
--- a/arch/arm/mach-tegra/pmc.c
+++ b/arch/arm/mach-tegra/pmc.c
@@ -16,10 +16,20 @@
16 */ 16 */
17 17
18#include <linux/kernel.h> 18#include <linux/kernel.h>
19#include <linux/clk.h>
19#include <linux/io.h> 20#include <linux/io.h>
20#include <linux/of.h> 21#include <linux/of.h>
21#include <linux/of_address.h> 22#include <linux/of_address.h>
22 23
24#include "fuse.h"
25#include "pm.h"
26#include "pmc.h"
27#include "sleep.h"
28
29#define TEGRA_POWER_EFFECT_LP0 (1 << 14) /* LP0 when CPU pwr gated */
30#define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */
31#define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */
32
23#define PMC_CTRL 0x0 33#define PMC_CTRL 0x0
24#define PMC_CTRL_INTR_LOW (1 << 17) 34#define PMC_CTRL_INTR_LOW (1 << 17)
25#define PMC_PWRGATE_TOGGLE 0x30 35#define PMC_PWRGATE_TOGGLE 0x30
@@ -27,6 +37,9 @@
27#define PMC_REMOVE_CLAMPING 0x34 37#define PMC_REMOVE_CLAMPING 0x34
28#define PMC_PWRGATE_STATUS 0x38 38#define PMC_PWRGATE_STATUS 0x38
29 39
40#define PMC_CPUPWRGOOD_TIMER 0xc8
41#define PMC_CPUPWROFF_TIMER 0xcc
42
30#define TEGRA_POWERGATE_PCIE 3 43#define TEGRA_POWERGATE_PCIE 3
31#define TEGRA_POWERGATE_VDEC 4 44#define TEGRA_POWERGATE_VDEC 4
32#define TEGRA_POWERGATE_CPU1 9 45#define TEGRA_POWERGATE_CPU1 9
@@ -43,6 +56,23 @@ static DEFINE_SPINLOCK(tegra_powergate_lock);
43 56
44static void __iomem *tegra_pmc_base; 57static void __iomem *tegra_pmc_base;
45static bool tegra_pmc_invert_interrupt; 58static bool tegra_pmc_invert_interrupt;
59static struct clk *tegra_pclk;
60
61struct pmc_pm_data {
62 u32 cpu_good_time; /* CPU power good time in uS */
63 u32 cpu_off_time; /* CPU power off time in uS */
64 u32 core_osc_time; /* Core power good osc time in uS */
65 u32 core_pmu_time; /* Core power good pmu time in uS */
66 u32 core_off_time; /* Core power off time in uS */
67 bool corereq_high; /* Core power request active-high */
68 bool sysclkreq_high; /* System clock request active-high */
69 bool combined_req; /* Combined pwr req for CPU & Core */
70 bool cpu_pwr_good_en; /* CPU power good signal is enabled */
71 u32 lp0_vec_phy_addr; /* The phy addr of LP0 warm boot code */
72 u32 lp0_vec_size; /* The size of LP0 warm boot code */
73 enum tegra_suspend_mode suspend_mode;
74};
75static struct pmc_pm_data pmc_pm_data;
46 76
47static inline u32 tegra_pmc_readl(u32 reg) 77static inline u32 tegra_pmc_readl(u32 reg)
48{ 78{
@@ -133,6 +163,70 @@ int tegra_pmc_cpu_remove_clamping(int cpuid)
133 return tegra_pmc_powergate_remove_clamping(id); 163 return tegra_pmc_powergate_remove_clamping(id);
134} 164}
135 165
166#ifdef CONFIG_PM_SLEEP
167static void set_power_timers(u32 us_on, u32 us_off, unsigned long rate)
168{
169 unsigned long long ticks;
170 unsigned long long pclk;
171 static unsigned long tegra_last_pclk;
172
173 if (WARN_ON_ONCE(rate <= 0))
174 pclk = 100000000;
175 else
176 pclk = rate;
177
178 if ((rate != tegra_last_pclk)) {
179 ticks = (us_on * pclk) + 999999ull;
180 do_div(ticks, 1000000);
181 tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWRGOOD_TIMER);
182
183 ticks = (us_off * pclk) + 999999ull;
184 do_div(ticks, 1000000);
185 tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWROFF_TIMER);
186 wmb();
187 }
188 tegra_last_pclk = pclk;
189}
190
191enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
192{
193 return pmc_pm_data.suspend_mode;
194}
195
196void tegra_pmc_pm_set(enum tegra_suspend_mode mode)
197{
198 u32 reg;
199 unsigned long rate = 0;
200
201 reg = tegra_pmc_readl(PMC_CTRL);
202 reg |= TEGRA_POWER_CPU_PWRREQ_OE;
203 reg &= ~TEGRA_POWER_EFFECT_LP0;
204
205 switch (mode) {
206 case TEGRA_SUSPEND_LP2:
207 rate = clk_get_rate(tegra_pclk);
208 break;
209 default:
210 break;
211 }
212
213 set_power_timers(pmc_pm_data.cpu_good_time, pmc_pm_data.cpu_off_time,
214 rate);
215
216 tegra_pmc_writel(reg, PMC_CTRL);
217}
218
219void tegra_pmc_suspend_init(void)
220{
221 u32 reg;
222
223 /* Always enable CPU power request */
224 reg = tegra_pmc_readl(PMC_CTRL);
225 reg |= TEGRA_POWER_CPU_PWRREQ_OE;
226 tegra_pmc_writel(reg, PMC_CTRL);
227}
228#endif
229
136static const struct of_device_id matches[] __initconst = { 230static const struct of_device_id matches[] __initconst = {
137 { .compatible = "nvidia,tegra114-pmc" }, 231 { .compatible = "nvidia,tegra114-pmc" },
138 { .compatible = "nvidia,tegra30-pmc" }, 232 { .compatible = "nvidia,tegra30-pmc" },
@@ -143,6 +237,10 @@ static const struct of_device_id matches[] __initconst = {
143static void tegra_pmc_parse_dt(void) 237static void tegra_pmc_parse_dt(void)
144{ 238{
145 struct device_node *np; 239 struct device_node *np;
240 u32 prop;
241 enum tegra_suspend_mode suspend_mode;
242 u32 core_good_time[2] = {0, 0};
243 u32 lp0_vec[2] = {0, 0};
146 244
147 np = of_find_matching_node(NULL, matches); 245 np = of_find_matching_node(NULL, matches);
148 BUG_ON(!np); 246 BUG_ON(!np);
@@ -151,6 +249,70 @@ static void tegra_pmc_parse_dt(void)
151 249
152 tegra_pmc_invert_interrupt = of_property_read_bool(np, 250 tegra_pmc_invert_interrupt = of_property_read_bool(np,
153 "nvidia,invert-interrupt"); 251 "nvidia,invert-interrupt");
252 tegra_pclk = of_clk_get_by_name(np, "pclk");
253 WARN_ON(IS_ERR(tegra_pclk));
254
255 /* Grabbing the power management configurations */
256 if (of_property_read_u32(np, "nvidia,suspend-mode", &prop)) {
257 suspend_mode = TEGRA_SUSPEND_NONE;
258 } else {
259 switch (prop) {
260 case 0:
261 suspend_mode = TEGRA_SUSPEND_LP0;
262 break;
263 case 1:
264 suspend_mode = TEGRA_SUSPEND_LP1;
265 break;
266 case 2:
267 suspend_mode = TEGRA_SUSPEND_LP2;
268 break;
269 default:
270 suspend_mode = TEGRA_SUSPEND_NONE;
271 break;
272 }
273 }
274 suspend_mode = tegra_pm_validate_suspend_mode(suspend_mode);
275
276 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &prop))
277 suspend_mode = TEGRA_SUSPEND_NONE;
278 pmc_pm_data.cpu_good_time = prop;
279
280 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &prop))
281 suspend_mode = TEGRA_SUSPEND_NONE;
282 pmc_pm_data.cpu_off_time = prop;
283
284 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
285 core_good_time, ARRAY_SIZE(core_good_time)))
286 suspend_mode = TEGRA_SUSPEND_NONE;
287 pmc_pm_data.core_osc_time = core_good_time[0];
288 pmc_pm_data.core_pmu_time = core_good_time[1];
289
290 if (of_property_read_u32(np, "nvidia,core-pwr-off-time",
291 &prop))
292 suspend_mode = TEGRA_SUSPEND_NONE;
293 pmc_pm_data.core_off_time = prop;
294
295 pmc_pm_data.corereq_high = of_property_read_bool(np,
296 "nvidia,core-power-req-active-high");
297
298 pmc_pm_data.sysclkreq_high = of_property_read_bool(np,
299 "nvidia,sys-clock-req-active-high");
300
301 pmc_pm_data.combined_req = of_property_read_bool(np,
302 "nvidia,combined-power-req");
303
304 pmc_pm_data.cpu_pwr_good_en = of_property_read_bool(np,
305 "nvidia,cpu-pwr-good-en");
306
307 if (of_property_read_u32_array(np, "nvidia,lp0-vec", lp0_vec,
308 ARRAY_SIZE(lp0_vec)))
309 if (suspend_mode == TEGRA_SUSPEND_LP0)
310 suspend_mode = TEGRA_SUSPEND_LP1;
311
312 pmc_pm_data.lp0_vec_phy_addr = lp0_vec[0];
313 pmc_pm_data.lp0_vec_size = lp0_vec[1];
314
315 pmc_pm_data.suspend_mode = suspend_mode;
154} 316}
155 317
156void __init tegra_pmc_init(void) 318void __init tegra_pmc_init(void)
diff --git a/arch/arm/mach-tegra/pmc.h b/arch/arm/mach-tegra/pmc.h
index 7d44710368be..e1c2df272f7d 100644
--- a/arch/arm/mach-tegra/pmc.h
+++ b/arch/arm/mach-tegra/pmc.h
@@ -18,6 +18,20 @@
18#ifndef __MACH_TEGRA_PMC_H 18#ifndef __MACH_TEGRA_PMC_H
19#define __MACH_TEGRA_PMC_H 19#define __MACH_TEGRA_PMC_H
20 20
21enum tegra_suspend_mode {
22 TEGRA_SUSPEND_NONE = 0,
23 TEGRA_SUSPEND_LP2, /* CPU voltage off */
24 TEGRA_SUSPEND_LP1, /* CPU voltage off, DRAM self-refresh */
25 TEGRA_SUSPEND_LP0, /* CPU + core voltage off, DRAM self-refresh */
26 TEGRA_MAX_SUSPEND_MODE,
27};
28
29#ifdef CONFIG_PM_SLEEP
30enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
31void tegra_pmc_pm_set(enum tegra_suspend_mode mode);
32void tegra_pmc_suspend_init(void);
33#endif
34
21bool tegra_pmc_cpu_is_powered(int cpuid); 35bool tegra_pmc_cpu_is_powered(int cpuid);
22int tegra_pmc_cpu_power_on(int cpuid); 36int tegra_pmc_cpu_power_on(int cpuid);
23int tegra_pmc_cpu_remove_clamping(int cpuid); 37int tegra_pmc_cpu_remove_clamping(int cpuid);
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index 27232c901a22..84deeab23ee7 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -33,6 +33,8 @@
33#include <linux/io.h> 33#include <linux/io.h>
34#include <linux/i2c.h> 34#include <linux/i2c.h>
35#include <linux/i2c-tegra.h> 35#include <linux/i2c-tegra.h>
36#include <linux/slab.h>
37#include <linux/sys_soc.h>
36#include <linux/usb/tegra_usb_phy.h> 38#include <linux/usb/tegra_usb_phy.h>
37 39
38#include <asm/mach-types.h> 40#include <asm/mach-types.h>
@@ -42,6 +44,7 @@
42 44
43#include "board.h" 45#include "board.h"
44#include "common.h" 46#include "common.h"
47#include "fuse.h"
45#include "iomap.h" 48#include "iomap.h"
46 49
47static struct tegra_ehci_platform_data tegra_ehci1_pdata = { 50static struct tegra_ehci_platform_data tegra_ehci1_pdata = {
@@ -80,12 +83,36 @@ static struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
80 83
81static void __init tegra_dt_init(void) 84static void __init tegra_dt_init(void)
82{ 85{
86 struct soc_device_attribute *soc_dev_attr;
87 struct soc_device *soc_dev;
88 struct device *parent = NULL;
89
90 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
91 if (!soc_dev_attr)
92 goto out;
93
94 soc_dev_attr->family = kasprintf(GFP_KERNEL, "Tegra");
95 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d", tegra_revision);
96 soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%d", tegra_chip_id);
97
98 soc_dev = soc_device_register(soc_dev_attr);
99 if (IS_ERR(soc_dev)) {
100 kfree(soc_dev_attr->family);
101 kfree(soc_dev_attr->revision);
102 kfree(soc_dev_attr->soc_id);
103 kfree(soc_dev_attr);
104 goto out;
105 }
106
107 parent = soc_device_to_device(soc_dev);
108
83 /* 109 /*
84 * Finished with the static registrations now; fill in the missing 110 * Finished with the static registrations now; fill in the missing
85 * devices 111 * devices
86 */ 112 */
113out:
87 of_platform_populate(NULL, of_default_bus_match_table, 114 of_platform_populate(NULL, of_default_bus_match_table,
88 tegra20_auxdata_lookup, NULL); 115 tegra20_auxdata_lookup, parent);
89} 116}
90 117
91static void __init trimslice_init(void) 118static void __init trimslice_init(void)
diff --git a/arch/arm/mach-tegra/tegra114_speedo.c b/arch/arm/mach-tegra/tegra114_speedo.c
new file mode 100644
index 000000000000..5218d4853cd3
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra114_speedo.c
@@ -0,0 +1,104 @@
1/*
2 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/kernel.h>
18#include <linux/bug.h>
19
20#include "fuse.h"
21
22#define CORE_PROCESS_CORNERS_NUM 2
23#define CPU_PROCESS_CORNERS_NUM 2
24
25enum {
26 THRESHOLD_INDEX_0,
27 THRESHOLD_INDEX_1,
28 THRESHOLD_INDEX_COUNT,
29};
30
31static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
32 {1123, UINT_MAX},
33 {0, UINT_MAX},
34};
35
36static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
37 {1695, UINT_MAX},
38 {0, UINT_MAX},
39};
40
41static void rev_sku_to_speedo_ids(int rev, int sku, int *threshold)
42{
43 u32 tmp;
44
45 switch (sku) {
46 case 0x00:
47 case 0x10:
48 case 0x05:
49 case 0x06:
50 tegra_cpu_speedo_id = 1;
51 tegra_soc_speedo_id = 0;
52 *threshold = THRESHOLD_INDEX_0;
53 break;
54
55 case 0x03:
56 case 0x04:
57 tegra_cpu_speedo_id = 2;
58 tegra_soc_speedo_id = 1;
59 *threshold = THRESHOLD_INDEX_1;
60 break;
61
62 default:
63 pr_err("Tegra114 Unknown SKU %d\n", sku);
64 tegra_cpu_speedo_id = 0;
65 tegra_soc_speedo_id = 0;
66 *threshold = THRESHOLD_INDEX_0;
67 break;
68 }
69
70 if (rev == TEGRA_REVISION_A01) {
71 tmp = tegra_fuse_readl(0x270) << 1;
72 tmp |= tegra_fuse_readl(0x26c);
73 if (!tmp)
74 tegra_cpu_speedo_id = 0;
75 }
76}
77
78void tegra114_init_speedo_data(void)
79{
80 u32 cpu_speedo_val;
81 u32 core_speedo_val;
82 int threshold;
83 int i;
84
85 BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
86 THRESHOLD_INDEX_COUNT);
87 BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
88 THRESHOLD_INDEX_COUNT);
89
90 rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id, &threshold);
91
92 cpu_speedo_val = tegra_fuse_readl(0x12c) + 1024;
93 core_speedo_val = tegra_fuse_readl(0x134);
94
95 for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++)
96 if (cpu_speedo_val < cpu_process_speedos[threshold][i])
97 break;
98 tegra_cpu_process_id = i;
99
100 for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++)
101 if (core_speedo_val < core_process_speedos[threshold][i])
102 break;
103 tegra_core_process_id = i;
104}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-04 04:57:09 -0500