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authorKuninori Morimoto <kuninori.morimoto.gx@renesas.com>2012-10-15 04:10:28 -0400
committerSimon Horman <horms@verge.net.au>2012-10-15 19:58:56 -0400
commit11f93576b0b50bf391ffafa544b85e541f5e59a5 (patch)
treeca0feb04bc30f71dc6c30502cfccb7befa75e008 /arch/arm
parentbc8b2428e73ce19aecbf2aac3f5d4c844adb3216 (diff)
ARM: shmobile: r8a7779: use __iomem pointers for MMIO
0a4b04dc299dfb691827a4001b3d8d7e443b71c9 (ARM: shmobile: use __iomem pointers for MMIO) modified iomem pointers so that IOMEM() macro will be used, but clock-r8a7779.c was out of target. This patch fixes it up. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms@verge.net.au>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7779.c22
1 files changed, 11 insertions, 11 deletions
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 3cafb6ab5e9a..37b2a3133b3b 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -24,17 +24,17 @@
24#include <linux/clkdev.h> 24#include <linux/clkdev.h>
25#include <mach/common.h> 25#include <mach/common.h>
26 26
27#define FRQMR 0xffc80014 27#define FRQMR IOMEM(0xffc80014)
28#define MSTPCR0 0xffc80030 28#define MSTPCR0 IOMEM(0xffc80030)
29#define MSTPCR1 0xffc80034 29#define MSTPCR1 IOMEM(0xffc80034)
30#define MSTPCR3 0xffc8003c 30#define MSTPCR3 IOMEM(0xffc8003c)
31#define MSTPSR1 0xffc80044 31#define MSTPSR1 IOMEM(0xffc80044)
32#define MSTPSR4 0xffc80048 32#define MSTPSR4 IOMEM(0xffc80048)
33#define MSTPSR6 0xffc8004c 33#define MSTPSR6 IOMEM(0xffc8004c)
34#define MSTPCR4 0xffc80050 34#define MSTPCR4 IOMEM(0xffc80050)
35#define MSTPCR5 0xffc80054 35#define MSTPCR5 IOMEM(0xffc80054)
36#define MSTPCR6 0xffc80058 36#define MSTPCR6 IOMEM(0xffc80058)
37#define MSTPCR7 0xffc80040 37#define MSTPCR7 IOMEM(0xffc80040)
38 38
39/* ioremap() through clock mapping mandatory to avoid 39/* ioremap() through clock mapping mandatory to avoid
40 * collision with ARM coherent DMA virtual memory range. 40 * collision with ARM coherent DMA virtual memory range.