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authoreric miao <eric.miao@marvell.com>2007-12-19 04:14:02 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-01-26 10:07:52 -0500
commit8f58de7c3932f659fff3b4e5fc14ca8ccf8ec873 (patch)
tree0e8988ff90d6377d124865c94076ca2702585ef8 /arch/arm
parenta333aeb73b45d2b6bbaaebd56f9e7e3a674ac039 (diff)
[ARM] pxa: create arch/arm/mach-pxa/device.c for all on-chip devices
Considering that generic.c is getting more and more bloated by device information, moving that part out side will be much cleaner. Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-pxa/Makefile2
-rw-r--r--arch/arm/mach-pxa/devices.c552
-rw-r--r--arch/arm/mach-pxa/generic.c548
3 files changed, 553 insertions, 549 deletions
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 3133dc4eaa7e..db18c8de7d55 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -3,7 +3,7 @@
3# 3#
4 4
5# Common support (must be linked before board specific support) 5# Common support (must be linked before board specific support)
6obj-y += clock.o generic.o irq.o dma.o time.o 6obj-y += clock.o devices.o generic.o irq.o dma.o time.o
7obj-$(CONFIG_PXA25x) += pxa25x.o 7obj-$(CONFIG_PXA25x) += pxa25x.o
8obj-$(CONFIG_PXA27x) += pxa27x.o 8obj-$(CONFIG_PXA27x) += pxa27x.o
9obj-$(CONFIG_PXA3xx) += pxa3xx.o mfp.o 9obj-$(CONFIG_PXA3xx) += pxa3xx.o mfp.o
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
new file mode 100644
index 000000000000..75949eb3b7bd
--- /dev/null
+++ b/arch/arm/mach-pxa/devices.c
@@ -0,0 +1,552 @@
1#include <linux/module.h>
2#include <linux/kernel.h>
3#include <linux/init.h>
4#include <linux/platform_device.h>
5#include <linux/dma-mapping.h>
6
7#include <asm/arch/gpio.h>
8#include <asm/arch/udc.h>
9#include <asm/arch/pxafb.h>
10#include <asm/arch/mmc.h>
11#include <asm/arch/irda.h>
12#include <asm/arch/i2c.h>
13
14#include "devices.h"
15
16void __init pxa_register_device(struct platform_device *dev, void *data)
17{
18 int ret;
19
20 dev->dev.platform_data = data;
21
22 ret = platform_device_register(dev);
23 if (ret)
24 dev_err(&dev->dev, "unable to register device: %d\n", ret);
25}
26
27static struct resource pxamci_resources[] = {
28 [0] = {
29 .start = 0x41100000,
30 .end = 0x41100fff,
31 .flags = IORESOURCE_MEM,
32 },
33 [1] = {
34 .start = IRQ_MMC,
35 .end = IRQ_MMC,
36 .flags = IORESOURCE_IRQ,
37 },
38 [2] = {
39 .start = 21,
40 .end = 21,
41 .flags = IORESOURCE_DMA,
42 },
43 [3] = {
44 .start = 22,
45 .end = 22,
46 .flags = IORESOURCE_DMA,
47 },
48};
49
50static u64 pxamci_dmamask = 0xffffffffUL;
51
52struct platform_device pxa_device_mci = {
53 .name = "pxa2xx-mci",
54 .id = -1,
55 .dev = {
56 .dma_mask = &pxamci_dmamask,
57 .coherent_dma_mask = 0xffffffff,
58 },
59 .num_resources = ARRAY_SIZE(pxamci_resources),
60 .resource = pxamci_resources,
61};
62
63void __init pxa_set_mci_info(struct pxamci_platform_data *info)
64{
65 pxa_register_device(&pxa_device_mci, info);
66}
67
68
69static struct pxa2xx_udc_mach_info pxa_udc_info;
70
71void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
72{
73 memcpy(&pxa_udc_info, info, sizeof *info);
74}
75
76static struct resource pxa2xx_udc_resources[] = {
77 [0] = {
78 .start = 0x40600000,
79 .end = 0x4060ffff,
80 .flags = IORESOURCE_MEM,
81 },
82 [1] = {
83 .start = IRQ_USB,
84 .end = IRQ_USB,
85 .flags = IORESOURCE_IRQ,
86 },
87};
88
89static u64 udc_dma_mask = ~(u32)0;
90
91struct platform_device pxa_device_udc = {
92 .name = "pxa2xx-udc",
93 .id = -1,
94 .resource = pxa2xx_udc_resources,
95 .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
96 .dev = {
97 .platform_data = &pxa_udc_info,
98 .dma_mask = &udc_dma_mask,
99 }
100};
101
102static struct resource pxafb_resources[] = {
103 [0] = {
104 .start = 0x44000000,
105 .end = 0x4400ffff,
106 .flags = IORESOURCE_MEM,
107 },
108 [1] = {
109 .start = IRQ_LCD,
110 .end = IRQ_LCD,
111 .flags = IORESOURCE_IRQ,
112 },
113};
114
115static u64 fb_dma_mask = ~(u64)0;
116
117struct platform_device pxa_device_fb = {
118 .name = "pxa2xx-fb",
119 .id = -1,
120 .dev = {
121 .dma_mask = &fb_dma_mask,
122 .coherent_dma_mask = 0xffffffff,
123 },
124 .num_resources = ARRAY_SIZE(pxafb_resources),
125 .resource = pxafb_resources,
126};
127
128void __init set_pxa_fb_info(struct pxafb_mach_info *info)
129{
130 pxa_register_device(&pxa_device_fb, info);
131}
132
133void __init set_pxa_fb_parent(struct device *parent_dev)
134{
135 pxa_device_fb.dev.parent = parent_dev;
136}
137
138static struct resource pxa_resource_ffuart[] = {
139 {
140 .start = __PREG(FFUART),
141 .end = __PREG(FFUART) + 35,
142 .flags = IORESOURCE_MEM,
143 }, {
144 .start = IRQ_FFUART,
145 .end = IRQ_FFUART,
146 .flags = IORESOURCE_IRQ,
147 }
148};
149
150struct platform_device pxa_device_ffuart= {
151 .name = "pxa2xx-uart",
152 .id = 0,
153 .resource = pxa_resource_ffuart,
154 .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
155};
156
157static struct resource pxa_resource_btuart[] = {
158 {
159 .start = __PREG(BTUART),
160 .end = __PREG(BTUART) + 35,
161 .flags = IORESOURCE_MEM,
162 }, {
163 .start = IRQ_BTUART,
164 .end = IRQ_BTUART,
165 .flags = IORESOURCE_IRQ,
166 }
167};
168
169struct platform_device pxa_device_btuart = {
170 .name = "pxa2xx-uart",
171 .id = 1,
172 .resource = pxa_resource_btuart,
173 .num_resources = ARRAY_SIZE(pxa_resource_btuart),
174};
175
176static struct resource pxa_resource_stuart[] = {
177 {
178 .start = __PREG(STUART),
179 .end = __PREG(STUART) + 35,
180 .flags = IORESOURCE_MEM,
181 }, {
182 .start = IRQ_STUART,
183 .end = IRQ_STUART,
184 .flags = IORESOURCE_IRQ,
185 }
186};
187
188struct platform_device pxa_device_stuart = {
189 .name = "pxa2xx-uart",
190 .id = 2,
191 .resource = pxa_resource_stuart,
192 .num_resources = ARRAY_SIZE(pxa_resource_stuart),
193};
194
195static struct resource pxa_resource_hwuart[] = {
196 {
197 .start = __PREG(HWUART),
198 .end = __PREG(HWUART) + 47,
199 .flags = IORESOURCE_MEM,
200 }, {
201 .start = IRQ_HWUART,
202 .end = IRQ_HWUART,
203 .flags = IORESOURCE_IRQ,
204 }
205};
206
207struct platform_device pxa_device_hwuart = {
208 .name = "pxa2xx-uart",
209 .id = 3,
210 .resource = pxa_resource_hwuart,
211 .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
212};
213
214static struct resource pxai2c_resources[] = {
215 {
216 .start = 0x40301680,
217 .end = 0x403016a3,
218 .flags = IORESOURCE_MEM,
219 }, {
220 .start = IRQ_I2C,
221 .end = IRQ_I2C,
222 .flags = IORESOURCE_IRQ,
223 },
224};
225
226struct platform_device pxa_device_i2c = {
227 .name = "pxa2xx-i2c",
228 .id = 0,
229 .resource = pxai2c_resources,
230 .num_resources = ARRAY_SIZE(pxai2c_resources),
231};
232
233void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
234{
235 pxa_register_device(&pxa_device_i2c, info);
236}
237
238static struct resource pxai2s_resources[] = {
239 {
240 .start = 0x40400000,
241 .end = 0x40400083,
242 .flags = IORESOURCE_MEM,
243 }, {
244 .start = IRQ_I2S,
245 .end = IRQ_I2S,
246 .flags = IORESOURCE_IRQ,
247 },
248};
249
250struct platform_device pxa_device_i2s = {
251 .name = "pxa2xx-i2s",
252 .id = -1,
253 .resource = pxai2s_resources,
254 .num_resources = ARRAY_SIZE(pxai2s_resources),
255};
256
257static u64 pxaficp_dmamask = ~(u32)0;
258
259struct platform_device pxa_device_ficp = {
260 .name = "pxa2xx-ir",
261 .id = -1,
262 .dev = {
263 .dma_mask = &pxaficp_dmamask,
264 .coherent_dma_mask = 0xffffffff,
265 },
266};
267
268void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
269{
270 pxa_register_device(&pxa_device_ficp, info);
271}
272
273struct platform_device pxa_device_rtc = {
274 .name = "sa1100-rtc",
275 .id = -1,
276};
277
278#ifdef CONFIG_PXA25x
279
280static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
281
282static struct resource pxa25x_resource_ssp[] = {
283 [0] = {
284 .start = 0x41000000,
285 .end = 0x4100001f,
286 .flags = IORESOURCE_MEM,
287 },
288 [1] = {
289 .start = IRQ_SSP,
290 .end = IRQ_SSP,
291 .flags = IORESOURCE_IRQ,
292 },
293 [2] = {
294 /* DRCMR for RX */
295 .start = 13,
296 .end = 13,
297 .flags = IORESOURCE_DMA,
298 },
299 [3] = {
300 /* DRCMR for TX */
301 .start = 14,
302 .end = 14,
303 .flags = IORESOURCE_DMA,
304 },
305};
306
307struct platform_device pxa25x_device_ssp = {
308 .name = "pxa25x-ssp",
309 .id = 0,
310 .dev = {
311 .dma_mask = &pxa25x_ssp_dma_mask,
312 .coherent_dma_mask = DMA_BIT_MASK(32),
313 },
314 .resource = pxa25x_resource_ssp,
315 .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
316};
317
318static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
319
320static struct resource pxa25x_resource_nssp[] = {
321 [0] = {
322 .start = 0x41400000,
323 .end = 0x4140002f,
324 .flags = IORESOURCE_MEM,
325 },
326 [1] = {
327 .start = IRQ_NSSP,
328 .end = IRQ_NSSP,
329 .flags = IORESOURCE_IRQ,
330 },
331 [2] = {
332 /* DRCMR for RX */
333 .start = 15,
334 .end = 15,
335 .flags = IORESOURCE_DMA,
336 },
337 [3] = {
338 /* DRCMR for TX */
339 .start = 16,
340 .end = 16,
341 .flags = IORESOURCE_DMA,
342 },
343};
344
345struct platform_device pxa25x_device_nssp = {
346 .name = "pxa25x-nssp",
347 .id = 1,
348 .dev = {
349 .dma_mask = &pxa25x_nssp_dma_mask,
350 .coherent_dma_mask = DMA_BIT_MASK(32),
351 },
352 .resource = pxa25x_resource_nssp,
353 .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
354};
355
356static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
357
358static struct resource pxa25x_resource_assp[] = {
359 [0] = {
360 .start = 0x41500000,
361 .end = 0x4150002f,
362 .flags = IORESOURCE_MEM,
363 },
364 [1] = {
365 .start = IRQ_ASSP,
366 .end = IRQ_ASSP,
367 .flags = IORESOURCE_IRQ,
368 },
369 [2] = {
370 /* DRCMR for RX */
371 .start = 23,
372 .end = 23,
373 .flags = IORESOURCE_DMA,
374 },
375 [3] = {
376 /* DRCMR for TX */
377 .start = 24,
378 .end = 24,
379 .flags = IORESOURCE_DMA,
380 },
381};
382
383struct platform_device pxa25x_device_assp = {
384 /* ASSP is basically equivalent to NSSP */
385 .name = "pxa25x-nssp",
386 .id = 2,
387 .dev = {
388 .dma_mask = &pxa25x_assp_dma_mask,
389 .coherent_dma_mask = DMA_BIT_MASK(32),
390 },
391 .resource = pxa25x_resource_assp,
392 .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
393};
394#endif /* CONFIG_PXA25x */
395
396#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
397
398static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
399
400static struct resource pxa27x_resource_ssp1[] = {
401 [0] = {
402 .start = 0x41000000,
403 .end = 0x4100003f,
404 .flags = IORESOURCE_MEM,
405 },
406 [1] = {
407 .start = IRQ_SSP,
408 .end = IRQ_SSP,
409 .flags = IORESOURCE_IRQ,
410 },
411 [2] = {
412 /* DRCMR for RX */
413 .start = 13,
414 .end = 13,
415 .flags = IORESOURCE_DMA,
416 },
417 [3] = {
418 /* DRCMR for TX */
419 .start = 14,
420 .end = 14,
421 .flags = IORESOURCE_DMA,
422 },
423};
424
425struct platform_device pxa27x_device_ssp1 = {
426 .name = "pxa27x-ssp",
427 .id = 0,
428 .dev = {
429 .dma_mask = &pxa27x_ssp1_dma_mask,
430 .coherent_dma_mask = DMA_BIT_MASK(32),
431 },
432 .resource = pxa27x_resource_ssp1,
433 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
434};
435
436static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
437
438static struct resource pxa27x_resource_ssp2[] = {
439 [0] = {
440 .start = 0x41700000,
441 .end = 0x4170003f,
442 .flags = IORESOURCE_MEM,
443 },
444 [1] = {
445 .start = IRQ_SSP2,
446 .end = IRQ_SSP2,
447 .flags = IORESOURCE_IRQ,
448 },
449 [2] = {
450 /* DRCMR for RX */
451 .start = 15,
452 .end = 15,
453 .flags = IORESOURCE_DMA,
454 },
455 [3] = {
456 /* DRCMR for TX */
457 .start = 16,
458 .end = 16,
459 .flags = IORESOURCE_DMA,
460 },
461};
462
463struct platform_device pxa27x_device_ssp2 = {
464 .name = "pxa27x-ssp",
465 .id = 1,
466 .dev = {
467 .dma_mask = &pxa27x_ssp2_dma_mask,
468 .coherent_dma_mask = DMA_BIT_MASK(32),
469 },
470 .resource = pxa27x_resource_ssp2,
471 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
472};
473
474static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
475
476static struct resource pxa27x_resource_ssp3[] = {
477 [0] = {
478 .start = 0x41900000,
479 .end = 0x4190003f,
480 .flags = IORESOURCE_MEM,
481 },
482 [1] = {
483 .start = IRQ_SSP3,
484 .end = IRQ_SSP3,
485 .flags = IORESOURCE_IRQ,
486 },
487 [2] = {
488 /* DRCMR for RX */
489 .start = 66,
490 .end = 66,
491 .flags = IORESOURCE_DMA,
492 },
493 [3] = {
494 /* DRCMR for TX */
495 .start = 67,
496 .end = 67,
497 .flags = IORESOURCE_DMA,
498 },
499};
500
501struct platform_device pxa27x_device_ssp3 = {
502 .name = "pxa27x-ssp",
503 .id = 2,
504 .dev = {
505 .dma_mask = &pxa27x_ssp3_dma_mask,
506 .coherent_dma_mask = DMA_BIT_MASK(32),
507 },
508 .resource = pxa27x_resource_ssp3,
509 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
510};
511#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
512
513#ifdef CONFIG_PXA3xx
514static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
515
516static struct resource pxa3xx_resource_ssp4[] = {
517 [0] = {
518 .start = 0x41a00000,
519 .end = 0x41a0003f,
520 .flags = IORESOURCE_MEM,
521 },
522 [1] = {
523 .start = IRQ_SSP4,
524 .end = IRQ_SSP4,
525 .flags = IORESOURCE_IRQ,
526 },
527 [2] = {
528 /* DRCMR for RX */
529 .start = 2,
530 .end = 2,
531 .flags = IORESOURCE_DMA,
532 },
533 [3] = {
534 /* DRCMR for TX */
535 .start = 3,
536 .end = 3,
537 .flags = IORESOURCE_DMA,
538 },
539};
540
541struct platform_device pxa3xx_device_ssp4 = {
542 /* PXA3xx SSP is basically equivalent to PXA27x */
543 .name = "pxa27x-ssp",
544 .id = 3,
545 .dev = {
546 .dma_mask = &pxa3xx_ssp4_dma_mask,
547 .coherent_dma_mask = DMA_BIT_MASK(32),
548 },
549 .resource = pxa3xx_resource_ssp4,
550 .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
551};
552#endif /* CONFIG_PXA3xx */
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index a8d88704c8d4..e4dbdbc2fb15 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -20,11 +20,9 @@
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/delay.h> 22#include <linux/delay.h>
23#include <linux/platform_device.h>
24#include <linux/ioport.h> 23#include <linux/ioport.h>
25#include <linux/pm.h> 24#include <linux/pm.h>
26#include <linux/string.h> 25#include <linux/string.h>
27#include <linux/dma-mapping.h>
28 26
29#include <asm/hardware.h> 27#include <asm/hardware.h>
30#include <asm/irq.h> 28#include <asm/irq.h>
@@ -34,13 +32,7 @@
34 32
35#include <asm/arch/pxa-regs.h> 33#include <asm/arch/pxa-regs.h>
36#include <asm/arch/gpio.h> 34#include <asm/arch/gpio.h>
37#include <asm/arch/udc.h>
38#include <asm/arch/pxafb.h>
39#include <asm/arch/mmc.h>
40#include <asm/arch/irda.h>
41#include <asm/arch/i2c.h>
42 35
43#include "devices.h"
44#include "generic.h" 36#include "generic.h"
45 37
46/* 38/*
@@ -234,543 +226,3 @@ void __init pxa_map_io(void)
234 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); 226 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
235 get_clk_frequency_khz(1); 227 get_clk_frequency_khz(1);
236} 228}
237
238
239void __init pxa_register_device(struct platform_device *dev, void *data)
240{
241 int ret;
242
243 dev->dev.platform_data = data;
244
245 ret = platform_device_register(dev);
246 if (ret)
247 dev_err(&dev->dev, "unable to register device: %d\n", ret);
248}
249
250
251static struct resource pxamci_resources[] = {
252 [0] = {
253 .start = 0x41100000,
254 .end = 0x41100fff,
255 .flags = IORESOURCE_MEM,
256 },
257 [1] = {
258 .start = IRQ_MMC,
259 .end = IRQ_MMC,
260 .flags = IORESOURCE_IRQ,
261 },
262 [2] = {
263 .start = 21,
264 .end = 21,
265 .flags = IORESOURCE_DMA,
266 },
267 [3] = {
268 .start = 22,
269 .end = 22,
270 .flags = IORESOURCE_DMA,
271 },
272};
273
274static u64 pxamci_dmamask = 0xffffffffUL;
275
276struct platform_device pxa_device_mci = {
277 .name = "pxa2xx-mci",
278 .id = -1,
279 .dev = {
280 .dma_mask = &pxamci_dmamask,
281 .coherent_dma_mask = 0xffffffff,
282 },
283 .num_resources = ARRAY_SIZE(pxamci_resources),
284 .resource = pxamci_resources,
285};
286
287void __init pxa_set_mci_info(struct pxamci_platform_data *info)
288{
289 pxa_register_device(&pxa_device_mci, info);
290}
291
292
293static struct pxa2xx_udc_mach_info pxa_udc_info;
294
295void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
296{
297 memcpy(&pxa_udc_info, info, sizeof *info);
298}
299
300static struct resource pxa2xx_udc_resources[] = {
301 [0] = {
302 .start = 0x40600000,
303 .end = 0x4060ffff,
304 .flags = IORESOURCE_MEM,
305 },
306 [1] = {
307 .start = IRQ_USB,
308 .end = IRQ_USB,
309 .flags = IORESOURCE_IRQ,
310 },
311};
312
313static u64 udc_dma_mask = ~(u32)0;
314
315struct platform_device pxa_device_udc = {
316 .name = "pxa2xx-udc",
317 .id = -1,
318 .resource = pxa2xx_udc_resources,
319 .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
320 .dev = {
321 .platform_data = &pxa_udc_info,
322 .dma_mask = &udc_dma_mask,
323 }
324};
325
326static struct resource pxafb_resources[] = {
327 [0] = {
328 .start = 0x44000000,
329 .end = 0x4400ffff,
330 .flags = IORESOURCE_MEM,
331 },
332 [1] = {
333 .start = IRQ_LCD,
334 .end = IRQ_LCD,
335 .flags = IORESOURCE_IRQ,
336 },
337};
338
339static u64 fb_dma_mask = ~(u64)0;
340
341struct platform_device pxa_device_fb = {
342 .name = "pxa2xx-fb",
343 .id = -1,
344 .dev = {
345 .dma_mask = &fb_dma_mask,
346 .coherent_dma_mask = 0xffffffff,
347 },
348 .num_resources = ARRAY_SIZE(pxafb_resources),
349 .resource = pxafb_resources,
350};
351
352void __init set_pxa_fb_info(struct pxafb_mach_info *info)
353{
354 pxa_register_device(&pxa_device_fb, info);
355}
356
357void __init set_pxa_fb_parent(struct device *parent_dev)
358{
359 pxa_device_fb.dev.parent = parent_dev;
360}
361
362static struct resource pxa_resource_ffuart[] = {
363 {
364 .start = __PREG(FFUART),
365 .end = __PREG(FFUART) + 35,
366 .flags = IORESOURCE_MEM,
367 }, {
368 .start = IRQ_FFUART,
369 .end = IRQ_FFUART,
370 .flags = IORESOURCE_IRQ,
371 }
372};
373
374struct platform_device pxa_device_ffuart= {
375 .name = "pxa2xx-uart",
376 .id = 0,
377 .resource = pxa_resource_ffuart,
378 .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
379};
380
381static struct resource pxa_resource_btuart[] = {
382 {
383 .start = __PREG(BTUART),
384 .end = __PREG(BTUART) + 35,
385 .flags = IORESOURCE_MEM,
386 }, {
387 .start = IRQ_BTUART,
388 .end = IRQ_BTUART,
389 .flags = IORESOURCE_IRQ,
390 }
391};
392
393struct platform_device pxa_device_btuart = {
394 .name = "pxa2xx-uart",
395 .id = 1,
396 .resource = pxa_resource_btuart,
397 .num_resources = ARRAY_SIZE(pxa_resource_btuart),
398};
399
400static struct resource pxa_resource_stuart[] = {
401 {
402 .start = __PREG(STUART),
403 .end = __PREG(STUART) + 35,
404 .flags = IORESOURCE_MEM,
405 }, {
406 .start = IRQ_STUART,
407 .end = IRQ_STUART,
408 .flags = IORESOURCE_IRQ,
409 }
410};
411
412struct platform_device pxa_device_stuart = {
413 .name = "pxa2xx-uart",
414 .id = 2,
415 .resource = pxa_resource_stuart,
416 .num_resources = ARRAY_SIZE(pxa_resource_stuart),
417};
418
419static struct resource pxa_resource_hwuart[] = {
420 {
421 .start = __PREG(HWUART),
422 .end = __PREG(HWUART) + 47,
423 .flags = IORESOURCE_MEM,
424 }, {
425 .start = IRQ_HWUART,
426 .end = IRQ_HWUART,
427 .flags = IORESOURCE_IRQ,
428 }
429};
430
431struct platform_device pxa_device_hwuart = {
432 .name = "pxa2xx-uart",
433 .id = 3,
434 .resource = pxa_resource_hwuart,
435 .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
436};
437
438static struct resource pxai2c_resources[] = {
439 {
440 .start = 0x40301680,
441 .end = 0x403016a3,
442 .flags = IORESOURCE_MEM,
443 }, {
444 .start = IRQ_I2C,
445 .end = IRQ_I2C,
446 .flags = IORESOURCE_IRQ,
447 },
448};
449
450struct platform_device pxa_device_i2c = {
451 .name = "pxa2xx-i2c",
452 .id = 0,
453 .resource = pxai2c_resources,
454 .num_resources = ARRAY_SIZE(pxai2c_resources),
455};
456
457void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
458{
459 pxa_register_device(&pxa_device_i2c, info);
460}
461
462static struct resource pxai2s_resources[] = {
463 {
464 .start = 0x40400000,
465 .end = 0x40400083,
466 .flags = IORESOURCE_MEM,
467 }, {
468 .start = IRQ_I2S,
469 .end = IRQ_I2S,
470 .flags = IORESOURCE_IRQ,
471 },
472};
473
474struct platform_device pxa_device_i2s = {
475 .name = "pxa2xx-i2s",
476 .id = -1,
477 .resource = pxai2s_resources,
478 .num_resources = ARRAY_SIZE(pxai2s_resources),
479};
480
481static u64 pxaficp_dmamask = ~(u32)0;
482
483struct platform_device pxa_device_ficp = {
484 .name = "pxa2xx-ir",
485 .id = -1,
486 .dev = {
487 .dma_mask = &pxaficp_dmamask,
488 .coherent_dma_mask = 0xffffffff,
489 },
490};
491
492void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
493{
494 pxa_register_device(&pxa_device_ficp, info);
495}
496
497struct platform_device pxa_device_rtc = {
498 .name = "sa1100-rtc",
499 .id = -1,
500};
501
502#ifdef CONFIG_PXA25x
503
504static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
505
506static struct resource pxa25x_resource_ssp[] = {
507 [0] = {
508 .start = 0x41000000,
509 .end = 0x4100001f,
510 .flags = IORESOURCE_MEM,
511 },
512 [1] = {
513 .start = IRQ_SSP,
514 .end = IRQ_SSP,
515 .flags = IORESOURCE_IRQ,
516 },
517 [2] = {
518 /* DRCMR for RX */
519 .start = 13,
520 .end = 13,
521 .flags = IORESOURCE_DMA,
522 },
523 [3] = {
524 /* DRCMR for TX */
525 .start = 14,
526 .end = 14,
527 .flags = IORESOURCE_DMA,
528 },
529};
530
531struct platform_device pxa25x_device_ssp = {
532 .name = "pxa25x-ssp",
533 .id = 0,
534 .dev = {
535 .dma_mask = &pxa25x_ssp_dma_mask,
536 .coherent_dma_mask = DMA_BIT_MASK(32),
537 },
538 .resource = pxa25x_resource_ssp,
539 .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
540};
541
542static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
543
544static struct resource pxa25x_resource_nssp[] = {
545 [0] = {
546 .start = 0x41400000,
547 .end = 0x4140002f,
548 .flags = IORESOURCE_MEM,
549 },
550 [1] = {
551 .start = IRQ_NSSP,
552 .end = IRQ_NSSP,
553 .flags = IORESOURCE_IRQ,
554 },
555 [2] = {
556 /* DRCMR for RX */
557 .start = 15,
558 .end = 15,
559 .flags = IORESOURCE_DMA,
560 },
561 [3] = {
562 /* DRCMR for TX */
563 .start = 16,
564 .end = 16,
565 .flags = IORESOURCE_DMA,
566 },
567};
568
569struct platform_device pxa25x_device_nssp = {
570 .name = "pxa25x-nssp",
571 .id = 1,
572 .dev = {
573 .dma_mask = &pxa25x_nssp_dma_mask,
574 .coherent_dma_mask = DMA_BIT_MASK(32),
575 },
576 .resource = pxa25x_resource_nssp,
577 .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
578};
579
580static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
581
582static struct resource pxa25x_resource_assp[] = {
583 [0] = {
584 .start = 0x41500000,
585 .end = 0x4150002f,
586 .flags = IORESOURCE_MEM,
587 },
588 [1] = {
589 .start = IRQ_ASSP,
590 .end = IRQ_ASSP,
591 .flags = IORESOURCE_IRQ,
592 },
593 [2] = {
594 /* DRCMR for RX */
595 .start = 23,
596 .end = 23,
597 .flags = IORESOURCE_DMA,
598 },
599 [3] = {
600 /* DRCMR for TX */
601 .start = 24,
602 .end = 24,
603 .flags = IORESOURCE_DMA,
604 },
605};
606
607struct platform_device pxa25x_device_assp = {
608 /* ASSP is basically equivalent to NSSP */
609 .name = "pxa25x-nssp",
610 .id = 2,
611 .dev = {
612 .dma_mask = &pxa25x_assp_dma_mask,
613 .coherent_dma_mask = DMA_BIT_MASK(32),
614 },
615 .resource = pxa25x_resource_assp,
616 .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
617};
618#endif /* CONFIG_PXA25x */
619
620#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
621
622static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
623
624static struct resource pxa27x_resource_ssp1[] = {
625 [0] = {
626 .start = 0x41000000,
627 .end = 0x4100003f,
628 .flags = IORESOURCE_MEM,
629 },
630 [1] = {
631 .start = IRQ_SSP,
632 .end = IRQ_SSP,
633 .flags = IORESOURCE_IRQ,
634 },
635 [2] = {
636 /* DRCMR for RX */
637 .start = 13,
638 .end = 13,
639 .flags = IORESOURCE_DMA,
640 },
641 [3] = {
642 /* DRCMR for TX */
643 .start = 14,
644 .end = 14,
645 .flags = IORESOURCE_DMA,
646 },
647};
648
649struct platform_device pxa27x_device_ssp1 = {
650 .name = "pxa27x-ssp",
651 .id = 0,
652 .dev = {
653 .dma_mask = &pxa27x_ssp1_dma_mask,
654 .coherent_dma_mask = DMA_BIT_MASK(32),
655 },
656 .resource = pxa27x_resource_ssp1,
657 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
658};
659
660static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
661
662static struct resource pxa27x_resource_ssp2[] = {
663 [0] = {
664 .start = 0x41700000,
665 .end = 0x4170003f,
666 .flags = IORESOURCE_MEM,
667 },
668 [1] = {
669 .start = IRQ_SSP2,
670 .end = IRQ_SSP2,
671 .flags = IORESOURCE_IRQ,
672 },
673 [2] = {
674 /* DRCMR for RX */
675 .start = 15,
676 .end = 15,
677 .flags = IORESOURCE_DMA,
678 },
679 [3] = {
680 /* DRCMR for TX */
681 .start = 16,
682 .end = 16,
683 .flags = IORESOURCE_DMA,
684 },
685};
686
687struct platform_device pxa27x_device_ssp2 = {
688 .name = "pxa27x-ssp",
689 .id = 1,
690 .dev = {
691 .dma_mask = &pxa27x_ssp2_dma_mask,
692 .coherent_dma_mask = DMA_BIT_MASK(32),
693 },
694 .resource = pxa27x_resource_ssp2,
695 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
696};
697
698static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
699
700static struct resource pxa27x_resource_ssp3[] = {
701 [0] = {
702 .start = 0x41900000,
703 .end = 0x4190003f,
704 .flags = IORESOURCE_MEM,
705 },
706 [1] = {
707 .start = IRQ_SSP3,
708 .end = IRQ_SSP3,
709 .flags = IORESOURCE_IRQ,
710 },
711 [2] = {
712 /* DRCMR for RX */
713 .start = 66,
714 .end = 66,
715 .flags = IORESOURCE_DMA,
716 },
717 [3] = {
718 /* DRCMR for TX */
719 .start = 67,
720 .end = 67,
721 .flags = IORESOURCE_DMA,
722 },
723};
724
725struct platform_device pxa27x_device_ssp3 = {
726 .name = "pxa27x-ssp",
727 .id = 2,
728 .dev = {
729 .dma_mask = &pxa27x_ssp3_dma_mask,
730 .coherent_dma_mask = DMA_BIT_MASK(32),
731 },
732 .resource = pxa27x_resource_ssp3,
733 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
734};
735#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
736
737#ifdef CONFIG_PXA3xx
738static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
739
740static struct resource pxa3xx_resource_ssp4[] = {
741 [0] = {
742 .start = 0x41a00000,
743 .end = 0x41a0003f,
744 .flags = IORESOURCE_MEM,
745 },
746 [1] = {
747 .start = IRQ_SSP4,
748 .end = IRQ_SSP4,
749 .flags = IORESOURCE_IRQ,
750 },
751 [2] = {
752 /* DRCMR for RX */
753 .start = 2,
754 .end = 2,
755 .flags = IORESOURCE_DMA,
756 },
757 [3] = {
758 /* DRCMR for TX */
759 .start = 3,
760 .end = 3,
761 .flags = IORESOURCE_DMA,
762 },
763};
764
765struct platform_device pxa3xx_device_ssp4 = {
766 /* PXA3xx SSP is basically equivalent to PXA27x */
767 .name = "pxa27x-ssp",
768 .id = 3,
769 .dev = {
770 .dma_mask = &pxa3xx_ssp4_dma_mask,
771 .coherent_dma_mask = DMA_BIT_MASK(32),
772 },
773 .resource = pxa3xx_resource_ssp4,
774 .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
775};
776#endif /* CONFIG_PXA3xx */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-20 05:43:38 -0500