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authorRob Herring <rob.herring@calxeda.com>2012-03-04 23:00:46 -0500
committerRob Herring <rob.herring@calxeda.com>2012-03-04 23:00:46 -0500
commitd50673ed97a7ce609cf62bcd40c57517ada31806 (patch)
treede1464fe1a4126be6b34762015afb8ad8a90a2f0 /arch/arm
parentab15e0e80c02b8b9f3392a6173b9109348eed1c3 (diff)
parent7eca30aef7961e68ad74c0ef920546c2be7f6579 (diff)
Merge remote-tracking branch 'arm-soc/at91/base2+cleanup' into cleanup-base
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/Kconfig.debug2
-rw-r--r--arch/arm/boot/dts/at91sam9g25ek.dts37
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi172
-rw-r--r--arch/arm/boot/dts/at91sam9x5cm.dtsi14
-rw-r--r--arch/arm/configs/at91cap9_defconfig108
-rw-r--r--arch/arm/mach-at91/Kconfig23
-rw-r--r--arch/arm/mach-at91/Makefile5
-rw-r--r--arch/arm/mach-at91/Makefile.boot14
-rw-r--r--arch/arm/mach-at91/at91cap9.c404
-rw-r--r--arch/arm/mach-at91/at91cap9_devices.c1273
-rw-r--r--arch/arm/mach-at91/at91rm9200.c8
-rw-r--r--arch/arm/mach-at91/at91rm9200_devices.c14
-rw-r--r--arch/arm/mach-at91/at91rm9200_time.c37
-rw-r--r--arch/arm/mach-at91/at91sam9260.c23
-rw-r--r--arch/arm/mach-at91/at91sam9260_devices.c38
-rw-r--r--arch/arm/mach-at91/at91sam9261.c10
-rw-r--r--arch/arm/mach-at91/at91sam9261_devices.c31
-rw-r--r--arch/arm/mach-at91/at91sam9263.c11
-rw-r--r--arch/arm/mach-at91/at91sam9263_devices.c72
-rw-r--r--arch/arm/mach-at91/at91sam9_alt_reset.S12
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c11
-rw-r--r--arch/arm/mach-at91/at91sam9g45_devices.c144
-rw-r--r--arch/arm/mach-at91/at91sam9g45_reset.S12
-rw-r--r--arch/arm/mach-at91/at91sam9rl.c10
-rw-r--r--arch/arm/mach-at91/at91sam9rl_devices.c39
-rw-r--r--arch/arm/mach-at91/at91sam9x5.c370
-rw-r--r--arch/arm/mach-at91/at91x40.c2
-rw-r--r--arch/arm/mach-at91/at91x40_time.c28
-rw-r--r--arch/arm/mach-at91/board-cap9adk.c396
-rw-r--r--arch/arm/mach-at91/board-cpu9krea.c5
-rw-r--r--arch/arm/mach-at91/board-cpuat91.c1
-rw-r--r--arch/arm/mach-at91/board-dt.c7
-rw-r--r--arch/arm/mach-at91/board-eco920.c5
-rw-r--r--arch/arm/mach-at91/board-flexibity.c12
-rw-r--r--arch/arm/mach-at91/board-kb9202.c1
-rw-r--r--arch/arm/mach-at91/board-picotux200.c1
-rw-r--r--arch/arm/mach-at91/board-rm9200dk.c1
-rw-r--r--arch/arm/mach-at91/board-rm9200ek.c1
-rw-r--r--arch/arm/mach-at91/board-sam9m10g45ek.c80
-rw-r--r--arch/arm/mach-at91/board-yl-9200.c3
-rw-r--r--arch/arm/mach-at91/clock.c176
-rw-r--r--arch/arm/mach-at91/cpuidle.c11
-rw-r--r--arch/arm/mach-at91/generic.h11
-rw-r--r--arch/arm/mach-at91/include/mach/at91_matrix.h23
-rw-r--r--arch/arm/mach-at91/include/mach/at91_pmc.h118
-rw-r--r--arch/arm/mach-at91/include/mach/at91_ramc.h32
-rw-r--r--arch/arm/mach-at91/include/mach/at91_st.h32
-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9.h122
-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9_matrix.h137
-rw-r--r--arch/arm/mach-at91/include/mach/at91rm9200.h10
-rw-r--r--arch/arm/mach-at91/include/mach/at91rm9200_mc.h58
-rw-r--r--arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h63
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9260.h14
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9260_matrix.h36
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9261.h10
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9261_matrix.h18
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9263.h12
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9263_matrix.h74
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h16
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_sdramc.h6
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9g45.h12
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h84
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9rl.h7
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h42
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9x5.h79
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h53
-rw-r--r--arch/arm/mach-at91/include/mach/at91x40.h18
-rw-r--r--arch/arm/mach-at91/include/mach/board.h6
-rw-r--r--arch/arm/mach-at91/include/mach/cpu.h21
-rw-r--r--arch/arm/mach-at91/include/mach/hardware.h9
-rw-r--r--arch/arm/mach-at91/include/mach/io.h18
-rw-r--r--arch/arm/mach-at91/pm.c52
-rw-r--r--arch/arm/mach-at91/pm.h96
-rw-r--r--arch/arm/mach-at91/pm_slowclock.S275
-rw-r--r--arch/arm/mach-at91/setup.c26
-rw-r--r--arch/arm/mach-at91/soc.h5
77 files changed, 1968 insertions, 3253 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7d809b7e0504..f2574fef1e41 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -327,7 +327,7 @@ config ARCH_AT91
327 select CLKDEV_LOOKUP 327 select CLKDEV_LOOKUP
328 help 328 help
329 This enables support for systems based on the Atmel AT91RM9200, 329 This enables support for systems based on the Atmel AT91RM9200,
330 AT91SAM9 and AT91CAP9 processors. 330 AT91SAM9 processors.
331 331
332config ARCH_BCMRING 332config ARCH_BCMRING
333 bool "Broadcom BCMRING" 333 bool "Broadcom BCMRING"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 03646c4c13d1..b895a2a92da8 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -86,7 +86,7 @@ choice
86 depends on HAVE_AT91_DBGU0 86 depends on HAVE_AT91_DBGU0
87 87
88 config AT91_DEBUG_LL_DBGU1 88 config AT91_DEBUG_LL_DBGU1
89 bool "Kernel low-level debugging on 9263, 9g45 and cap9" 89 bool "Kernel low-level debugging on 9263 and 9g45"
90 depends on HAVE_AT91_DBGU1 90 depends on HAVE_AT91_DBGU1
91 91
92 config DEBUG_CLPS711X_UART1 92 config DEBUG_CLPS711X_UART1
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
new file mode 100644
index 000000000000..e64eb932083b
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -0,0 +1,37 @@
1/*
2 * at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9x5.dtsi"
11/include/ "at91sam9x5cm.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9G25-EK";
15 compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16
17 chosen {
18 bootargs = "128M console=ttyS0,115200 mtdparts=atmel_nand:8M(bootstrap/uboot/kernel)ro,-(rootfs) root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
19 };
20
21 ahb {
22 apb {
23 dbgu: serial@fffff200 {
24 status = "okay";
25 };
26
27 usart0: serial@f801c000 {
28 status = "okay";
29 };
30
31 macb0: ethernet@f802c000 {
32 phy-mode = "rmii";
33 status = "okay";
34 };
35 };
36 };
37};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
new file mode 100644
index 000000000000..e91391f50730
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -0,0 +1,172 @@
1/*
2 * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
3 * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
4 * AT91SAM9X25, AT91SAM9X35 SoC
5 *
6 * Copyright (C) 2012 Atmel,
7 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 model = "Atmel AT91SAM9x5 family SoC";
16 compatible = "atmel,at91sam9x5";
17 interrupt-parent = <&aic>;
18
19 aliases {
20 serial0 = &dbgu;
21 serial1 = &usart0;
22 serial2 = &usart1;
23 serial3 = &usart2;
24 gpio0 = &pioA;
25 gpio1 = &pioB;
26 gpio2 = &pioC;
27 gpio3 = &pioD;
28 tcb0 = &tcb0;
29 tcb1 = &tcb1;
30 };
31 cpus {
32 cpu@0 {
33 compatible = "arm,arm926ejs";
34 };
35 };
36
37 memory@20000000 {
38 reg = <0x20000000 0x10000000>;
39 };
40
41 ahb {
42 compatible = "simple-bus";
43 #address-cells = <1>;
44 #size-cells = <1>;
45 ranges;
46
47 apb {
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 ranges;
52
53 aic: interrupt-controller@fffff000 {
54 #interrupt-cells = <2>;
55 compatible = "atmel,at91rm9200-aic";
56 interrupt-controller;
57 interrupt-parent;
58 reg = <0xfffff000 0x200>;
59 };
60
61 pit: timer@fffffe30 {
62 compatible = "atmel,at91sam9260-pit";
63 reg = <0xfffffe30 0xf>;
64 interrupts = <1 4>;
65 };
66
67 tcb0: timer@f8008000 {
68 compatible = "atmel,at91sam9x5-tcb";
69 reg = <0xf8008000 0x100>;
70 interrupts = <17 4>;
71 };
72
73 tcb1: timer@f800c000 {
74 compatible = "atmel,at91sam9x5-tcb";
75 reg = <0xf800c000 0x100>;
76 interrupts = <17 4>;
77 };
78
79 dma0: dma-controller@ffffec00 {
80 compatible = "atmel,at91sam9g45-dma";
81 reg = <0xffffec00 0x200>;
82 interrupts = <20 4>;
83 };
84
85 dma1: dma-controller@ffffee00 {
86 compatible = "atmel,at91sam9g45-dma";
87 reg = <0xffffee00 0x200>;
88 interrupts = <21 4>;
89 };
90
91 pioA: gpio@fffff400 {
92 compatible = "atmel,at91rm9200-gpio";
93 reg = <0xfffff400 0x100>;
94 interrupts = <2 4>;
95 #gpio-cells = <2>;
96 gpio-controller;
97 };
98
99 pioB: gpio@fffff600 {
100 compatible = "atmel,at91rm9200-gpio";
101 reg = <0xfffff600 0x100>;
102 interrupts = <2 4>;
103 #gpio-cells = <2>;
104 gpio-controller;
105 };
106
107 pioC: gpio@fffff800 {
108 compatible = "atmel,at91rm9200-gpio";
109 reg = <0xfffff800 0x100>;
110 interrupts = <3 4>;
111 #gpio-cells = <2>;
112 gpio-controller;
113 };
114
115 pioD: gpio@fffffa00 {
116 compatible = "atmel,at91rm9200-gpio";
117 reg = <0xfffffa00 0x100>;
118 interrupts = <3 4>;
119 #gpio-cells = <2>;
120 gpio-controller;
121 };
122
123 dbgu: serial@fffff200 {
124 compatible = "atmel,at91sam9260-usart";
125 reg = <0xfffff200 0x200>;
126 interrupts = <1 4>;
127 status = "disabled";
128 };
129
130 usart0: serial@f801c000 {
131 compatible = "atmel,at91sam9260-usart";
132 reg = <0xf801c000 0x200>;
133 interrupts = <5 4>;
134 atmel,use-dma-rx;
135 atmel,use-dma-tx;
136 status = "disabled";
137 };
138
139 usart1: serial@f8020000 {
140 compatible = "atmel,at91sam9260-usart";
141 reg = <0xf8020000 0x200>;
142 interrupts = <6 4>;
143 atmel,use-dma-rx;
144 atmel,use-dma-tx;
145 status = "disabled";
146 };
147
148 usart2: serial@f8024000 {
149 compatible = "atmel,at91sam9260-usart";
150 reg = <0xf8024000 0x200>;
151 interrupts = <7 4>;
152 atmel,use-dma-rx;
153 atmel,use-dma-tx;
154 status = "disabled";
155 };
156
157 macb0: ethernet@f802c000 {
158 compatible = "cdns,at32ap7000-macb", "cdns,macb";
159 reg = <0xf802c000 0x100>;
160 interrupts = <24 4>;
161 status = "disabled";
162 };
163
164 macb1: ethernet@f8030000 {
165 compatible = "cdns,at32ap7000-macb", "cdns,macb";
166 reg = <0xf8030000 0x100>;
167 interrupts = <27 4>;
168 status = "disabled";
169 };
170 };
171 };
172};
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi
new file mode 100644
index 000000000000..4ab5a77f4afc
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi
@@ -0,0 +1,14 @@
1/*
2 * at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10/ {
11 memory@20000000 {
12 reg = <0x20000000 0x8000000>;
13 };
14};
diff --git a/arch/arm/configs/at91cap9_defconfig b/arch/arm/configs/at91cap9_defconfig
deleted file mode 100644
index 8826eb218e73..000000000000
--- a/arch/arm/configs/at91cap9_defconfig
+++ /dev/null
@@ -1,108 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2# CONFIG_LOCALVERSION_AUTO is not set
3# CONFIG_SWAP is not set
4CONFIG_SYSVIPC=y
5CONFIG_LOG_BUF_SHIFT=14
6CONFIG_BLK_DEV_INITRD=y
7CONFIG_SLAB=y
8CONFIG_MODULES=y
9CONFIG_MODULE_UNLOAD=y
10# CONFIG_BLK_DEV_BSG is not set
11# CONFIG_IOSCHED_DEADLINE is not set
12# CONFIG_IOSCHED_CFQ is not set
13CONFIG_ARCH_AT91=y
14CONFIG_ARCH_AT91CAP9=y
15CONFIG_MACH_AT91CAP9ADK=y
16CONFIG_MTD_AT91_DATAFLASH_CARD=y
17CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
18# CONFIG_ARM_THUMB is not set
19CONFIG_AEABI=y
20CONFIG_LEDS=y
21CONFIG_LEDS_CPU=y
22CONFIG_ZBOOT_ROM_TEXT=0x0
23CONFIG_ZBOOT_ROM_BSS=0x0
24CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/ram0 rw"
25CONFIG_FPE_NWFPE=y
26CONFIG_NET=y
27CONFIG_PACKET=y
28CONFIG_UNIX=y
29CONFIG_INET=y
30CONFIG_IP_PNP=y
31CONFIG_IP_PNP_BOOTP=y
32CONFIG_IP_PNP_RARP=y
33# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
34# CONFIG_INET_XFRM_MODE_TUNNEL is not set
35# CONFIG_INET_XFRM_MODE_BEET is not set
36# CONFIG_INET_LRO is not set
37# CONFIG_INET_DIAG is not set
38# CONFIG_IPV6 is not set
39CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
40CONFIG_MTD=y
41CONFIG_MTD_CMDLINE_PARTS=y
42CONFIG_MTD_CHAR=y
43CONFIG_MTD_BLOCK=y
44CONFIG_MTD_CFI=y
45CONFIG_MTD_JEDECPROBE=y
46CONFIG_MTD_CFI_AMDSTD=y
47CONFIG_MTD_PHYSMAP=y
48CONFIG_MTD_DATAFLASH=y
49CONFIG_MTD_NAND=y
50CONFIG_MTD_NAND_ATMEL=y
51CONFIG_BLK_DEV_LOOP=y
52CONFIG_BLK_DEV_RAM=y
53CONFIG_BLK_DEV_RAM_SIZE=8192
54CONFIG_SCSI=y
55CONFIG_BLK_DEV_SD=y
56CONFIG_SCSI_MULTI_LUN=y
57CONFIG_NETDEVICES=y
58CONFIG_MII=y
59CONFIG_MACB=y
60# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
61CONFIG_INPUT_EVDEV=y
62# CONFIG_INPUT_KEYBOARD is not set
63# CONFIG_INPUT_MOUSE is not set
64CONFIG_INPUT_TOUCHSCREEN=y
65CONFIG_TOUCHSCREEN_ADS7846=y
66# CONFIG_SERIO is not set
67CONFIG_SERIAL_ATMEL=y
68CONFIG_SERIAL_ATMEL_CONSOLE=y
69CONFIG_HW_RANDOM=y
70CONFIG_I2C=y
71CONFIG_I2C_CHARDEV=y
72CONFIG_SPI=y
73CONFIG_SPI_ATMEL=y
74# CONFIG_HWMON is not set
75CONFIG_WATCHDOG=y
76CONFIG_WATCHDOG_NOWAYOUT=y
77CONFIG_FB=y
78CONFIG_FB_ATMEL=y
79CONFIG_LOGO=y
80# CONFIG_LOGO_LINUX_MONO is not set
81# CONFIG_LOGO_LINUX_CLUT224 is not set
82# CONFIG_USB_HID is not set
83CONFIG_USB=y
84CONFIG_USB_DEVICEFS=y
85CONFIG_USB_MON=y
86CONFIG_USB_OHCI_HCD=y
87CONFIG_USB_STORAGE=y
88CONFIG_USB_GADGET=y
89CONFIG_USB_ETH=m
90CONFIG_USB_FILE_STORAGE=m
91CONFIG_MMC=y
92CONFIG_MMC_AT91=m
93CONFIG_RTC_CLASS=y
94CONFIG_RTC_DRV_AT91SAM9=y
95CONFIG_EXT2_FS=y
96CONFIG_VFAT_FS=y
97CONFIG_TMPFS=y
98CONFIG_JFFS2_FS=y
99CONFIG_CRAMFS=y
100CONFIG_NFS_FS=y
101CONFIG_ROOT_NFS=y
102CONFIG_NLS_CODEPAGE_437=y
103CONFIG_NLS_CODEPAGE_850=y
104CONFIG_NLS_ISO8859_1=y
105CONFIG_DEBUG_FS=y
106CONFIG_DEBUG_KERNEL=y
107CONFIG_DEBUG_INFO=y
108CONFIG_DEBUG_USER=y
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 71feb00a1e99..e55cdcbd81fb 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -102,13 +102,13 @@ config ARCH_AT91SAM9G45
102 select HAVE_AT91_DBGU1 102 select HAVE_AT91_DBGU1
103 select AT91_SAM9G45_RESET 103 select AT91_SAM9G45_RESET
104 104
105config ARCH_AT91CAP9 105config ARCH_AT91SAM9X5
106 bool "AT91CAP9" 106 bool "AT91SAM9x5 family"
107 select CPU_ARM926T 107 select CPU_ARM926T
108 select GENERIC_CLOCKEVENTS 108 select GENERIC_CLOCKEVENTS
109 select HAVE_FB_ATMEL 109 select HAVE_FB_ATMEL
110 select HAVE_NET_MACB 110 select HAVE_NET_MACB
111 select HAVE_AT91_DBGU1 111 select HAVE_AT91_DBGU0
112 select AT91_SAM9G45_RESET 112 select AT91_SAM9G45_RESET
113 113
114config ARCH_AT91X40 114config ARCH_AT91X40
@@ -447,21 +447,6 @@ endif
447 447
448# ---------------------------------------------------------- 448# ----------------------------------------------------------
449 449
450if ARCH_AT91CAP9
451
452comment "AT91CAP9 Board Type"
453
454config MACH_AT91CAP9ADK
455 bool "Atmel AT91CAP9A-DK Evaluation Kit"
456 select HAVE_AT91_DATAFLASH_CARD
457 help
458 Select this if you are using Atmel's AT91CAP9A-DK Evaluation Kit.
459 <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4138>
460
461endif
462
463# ----------------------------------------------------------
464
465if ARCH_AT91X40 450if ARCH_AT91X40
466 451
467comment "AT91X40 Board Type" 452comment "AT91X40 Board Type"
@@ -544,7 +529,7 @@ config AT91_EARLY_DBGU0
544 depends on HAVE_AT91_DBGU0 529 depends on HAVE_AT91_DBGU0
545 530
546config AT91_EARLY_DBGU1 531config AT91_EARLY_DBGU1
547 bool "DBGU on 9263, 9g45 and cap9" 532 bool "DBGU on 9263 and 9g45"
548 depends on HAVE_AT91_DBGU1 533 depends on HAVE_AT91_DBGU1
549 534
550config AT91_EARLY_USART0 535config AT91_EARLY_USART0
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 705e1fbded39..1b6518518d99 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -20,7 +20,7 @@ obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_d
20obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o 20obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
21obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o 21obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
22obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o 22obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
23obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o 23obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam926x_time.o
24obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o 24obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
25 25
26# AT91RM9200 board-specific support 26# AT91RM9200 board-specific support
@@ -81,9 +81,6 @@ obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
81# AT91SAM board with device-tree 81# AT91SAM board with device-tree
82obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o 82obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o
83 83
84# AT91CAP9 board-specific support
85obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o
86
87# AT91X40 board-specific support 84# AT91X40 board-specific support
88obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o 85obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o
89 86
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index 8ddafadfdc7d..0da66ca4a4f8 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -3,11 +3,7 @@
3# PARAMS_PHYS must be within 4MB of ZRELADDR 3# PARAMS_PHYS must be within 4MB of ZRELADDR
4# INITRD_PHYS must be in RAM 4# INITRD_PHYS must be in RAM
5 5
6ifeq ($(CONFIG_ARCH_AT91CAP9),y) 6ifeq ($(CONFIG_ARCH_AT91SAM9G45),y)
7 zreladdr-y += 0x70008000
8params_phys-y := 0x70000100
9initrd_phys-y := 0x70410000
10else ifeq ($(CONFIG_ARCH_AT91SAM9G45),y)
11 zreladdr-y += 0x70008000 7 zreladdr-y += 0x70008000
12params_phys-y := 0x70000100 8params_phys-y := 0x70000100
13initrd_phys-y := 0x70410000 9initrd_phys-y := 0x70410000
@@ -17,4 +13,10 @@ params_phys-y := 0x20000100
17initrd_phys-y := 0x20410000 13initrd_phys-y := 0x20410000
18endif 14endif
19 15
20dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb usb_a9g20.dtb 16# Keep dtb files sorted alphabetically for each SoC
17# sam9g20
18dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9g20.dtb
19# sam9g45
20dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb
21# sam9x5
22dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g25ek.dtb
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c
deleted file mode 100644
index 8967d75c2ea3..000000000000
--- a/arch/arm/mach-at91/at91cap9.c
+++ /dev/null
@@ -1,404 +0,0 @@
1/*
2 * arch/arm/mach-at91/at91cap9.c
3 *
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2007 Atmel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 */
14
15#include <linux/module.h>
16
17#include <asm/proc-fns.h>
18#include <asm/irq.h>
19#include <asm/mach/arch.h>
20#include <asm/mach/map.h>
21
22#include <mach/cpu.h>
23#include <mach/at91cap9.h>
24#include <mach/at91_pmc.h>
25
26#include "soc.h"
27#include "generic.h"
28#include "clock.h"
29#include "sam9_smc.h"
30
31/* --------------------------------------------------------------------
32 * Clocks
33 * -------------------------------------------------------------------- */
34
35/*
36 * The peripheral clocks.
37 */
38static struct clk pioABCD_clk = {
39 .name = "pioABCD_clk",
40 .pmc_mask = 1 << AT91CAP9_ID_PIOABCD,
41 .type = CLK_TYPE_PERIPHERAL,
42};
43static struct clk mpb0_clk = {
44 .name = "mpb0_clk",
45 .pmc_mask = 1 << AT91CAP9_ID_MPB0,
46 .type = CLK_TYPE_PERIPHERAL,
47};
48static struct clk mpb1_clk = {
49 .name = "mpb1_clk",
50 .pmc_mask = 1 << AT91CAP9_ID_MPB1,
51 .type = CLK_TYPE_PERIPHERAL,
52};
53static struct clk mpb2_clk = {
54 .name = "mpb2_clk",
55 .pmc_mask = 1 << AT91CAP9_ID_MPB2,
56 .type = CLK_TYPE_PERIPHERAL,
57};
58static struct clk mpb3_clk = {
59 .name = "mpb3_clk",
60 .pmc_mask = 1 << AT91CAP9_ID_MPB3,
61 .type = CLK_TYPE_PERIPHERAL,
62};
63static struct clk mpb4_clk = {
64 .name = "mpb4_clk",
65 .pmc_mask = 1 << AT91CAP9_ID_MPB4,
66 .type = CLK_TYPE_PERIPHERAL,
67};
68static struct clk usart0_clk = {
69 .name = "usart0_clk",
70 .pmc_mask = 1 << AT91CAP9_ID_US0,
71 .type = CLK_TYPE_PERIPHERAL,
72};
73static struct clk usart1_clk = {
74 .name = "usart1_clk",
75 .pmc_mask = 1 << AT91CAP9_ID_US1,
76 .type = CLK_TYPE_PERIPHERAL,
77};
78static struct clk usart2_clk = {
79 .name = "usart2_clk",
80 .pmc_mask = 1 << AT91CAP9_ID_US2,
81 .type = CLK_TYPE_PERIPHERAL,
82};
83static struct clk mmc0_clk = {
84 .name = "mci0_clk",
85 .pmc_mask = 1 << AT91CAP9_ID_MCI0,
86 .type = CLK_TYPE_PERIPHERAL,
87};
88static struct clk mmc1_clk = {
89 .name = "mci1_clk",
90 .pmc_mask = 1 << AT91CAP9_ID_MCI1,
91 .type = CLK_TYPE_PERIPHERAL,
92};
93static struct clk can_clk = {
94 .name = "can_clk",
95 .pmc_mask = 1 << AT91CAP9_ID_CAN,
96 .type = CLK_TYPE_PERIPHERAL,
97};
98static struct clk twi_clk = {
99 .name = "twi_clk",
100 .pmc_mask = 1 << AT91CAP9_ID_TWI,
101 .type = CLK_TYPE_PERIPHERAL,
102};
103static struct clk spi0_clk = {
104 .name = "spi0_clk",
105 .pmc_mask = 1 << AT91CAP9_ID_SPI0,
106 .type = CLK_TYPE_PERIPHERAL,
107};
108static struct clk spi1_clk = {
109 .name = "spi1_clk",
110 .pmc_mask = 1 << AT91CAP9_ID_SPI1,
111 .type = CLK_TYPE_PERIPHERAL,
112};
113static struct clk ssc0_clk = {
114 .name = "ssc0_clk",
115 .pmc_mask = 1 << AT91CAP9_ID_SSC0,
116 .type = CLK_TYPE_PERIPHERAL,
117};
118static struct clk ssc1_clk = {
119 .name = "ssc1_clk",
120 .pmc_mask = 1 << AT91CAP9_ID_SSC1,
121 .type = CLK_TYPE_PERIPHERAL,
122};
123static struct clk ac97_clk = {
124 .name = "ac97_clk",
125 .pmc_mask = 1 << AT91CAP9_ID_AC97C,
126 .type = CLK_TYPE_PERIPHERAL,
127};
128static struct clk tcb_clk = {
129 .name = "tcb_clk",
130 .pmc_mask = 1 << AT91CAP9_ID_TCB,
131 .type = CLK_TYPE_PERIPHERAL,
132};
133static struct clk pwm_clk = {
134 .name = "pwm_clk",
135 .pmc_mask = 1 << AT91CAP9_ID_PWMC,
136 .type = CLK_TYPE_PERIPHERAL,
137};
138static struct clk macb_clk = {
139 .name = "pclk",
140 .pmc_mask = 1 << AT91CAP9_ID_EMAC,
141 .type = CLK_TYPE_PERIPHERAL,
142};
143static struct clk aestdes_clk = {
144 .name = "aestdes_clk",
145 .pmc_mask = 1 << AT91CAP9_ID_AESTDES,
146 .type = CLK_TYPE_PERIPHERAL,
147};
148static struct clk adc_clk = {
149 .name = "adc_clk",
150 .pmc_mask = 1 << AT91CAP9_ID_ADC,
151 .type = CLK_TYPE_PERIPHERAL,
152};
153static struct clk isi_clk = {
154 .name = "isi_clk",
155 .pmc_mask = 1 << AT91CAP9_ID_ISI,
156 .type = CLK_TYPE_PERIPHERAL,
157};
158static struct clk lcdc_clk = {
159 .name = "lcdc_clk",
160 .pmc_mask = 1 << AT91CAP9_ID_LCDC,
161 .type = CLK_TYPE_PERIPHERAL,
162};
163static struct clk dma_clk = {
164 .name = "dma_clk",
165 .pmc_mask = 1 << AT91CAP9_ID_DMA,
166 .type = CLK_TYPE_PERIPHERAL,
167};
168static struct clk udphs_clk = {
169 .name = "udphs_clk",
170 .pmc_mask = 1 << AT91CAP9_ID_UDPHS,
171 .type = CLK_TYPE_PERIPHERAL,
172};
173static struct clk ohci_clk = {
174 .name = "ohci_clk",
175 .pmc_mask = 1 << AT91CAP9_ID_UHP,
176 .type = CLK_TYPE_PERIPHERAL,
177};
178
179static struct clk *periph_clocks[] __initdata = {
180 &pioABCD_clk,
181 &mpb0_clk,
182 &mpb1_clk,
183 &mpb2_clk,
184 &mpb3_clk,
185 &mpb4_clk,
186 &usart0_clk,
187 &usart1_clk,
188 &usart2_clk,
189 &mmc0_clk,
190 &mmc1_clk,
191 &can_clk,
192 &twi_clk,
193 &spi0_clk,
194 &spi1_clk,
195 &ssc0_clk,
196 &ssc1_clk,
197 &ac97_clk,
198 &tcb_clk,
199 &pwm_clk,
200 &macb_clk,
201 &aestdes_clk,
202 &adc_clk,
203 &isi_clk,
204 &lcdc_clk,
205 &dma_clk,
206 &udphs_clk,
207 &ohci_clk,
208 // irq0 .. irq1
209};
210
211static struct clk_lookup periph_clocks_lookups[] = {
212 /* One additional fake clock for macb_hclk */
213 CLKDEV_CON_ID("hclk", &macb_clk),
214 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
215 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
216 CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
217 CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
218 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
219 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
220 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
221 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
222 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
223 /* fake hclk clock */
224 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
225 CLKDEV_CON_ID("pioA", &pioABCD_clk),
226 CLKDEV_CON_ID("pioB", &pioABCD_clk),
227 CLKDEV_CON_ID("pioC", &pioABCD_clk),
228 CLKDEV_CON_ID("pioD", &pioABCD_clk),
229};
230
231static struct clk_lookup usart_clocks_lookups[] = {
232 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
233 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
234 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
235 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
236};
237
238/*
239 * The four programmable clocks.
240 * You must configure pin multiplexing to bring these signals out.
241 */
242static struct clk pck0 = {
243 .name = "pck0",
244 .pmc_mask = AT91_PMC_PCK0,
245 .type = CLK_TYPE_PROGRAMMABLE,
246 .id = 0,
247};
248static struct clk pck1 = {
249 .name = "pck1",
250 .pmc_mask = AT91_PMC_PCK1,
251 .type = CLK_TYPE_PROGRAMMABLE,
252 .id = 1,
253};
254static struct clk pck2 = {
255 .name = "pck2",
256 .pmc_mask = AT91_PMC_PCK2,
257 .type = CLK_TYPE_PROGRAMMABLE,
258 .id = 2,
259};
260static struct clk pck3 = {
261 .name = "pck3",
262 .pmc_mask = AT91_PMC_PCK3,
263 .type = CLK_TYPE_PROGRAMMABLE,
264 .id = 3,
265};
266
267static void __init at91cap9_register_clocks(void)
268{
269 int i;
270
271 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
272 clk_register(periph_clocks[i]);
273
274 clkdev_add_table(periph_clocks_lookups,
275 ARRAY_SIZE(periph_clocks_lookups));
276 clkdev_add_table(usart_clocks_lookups,
277 ARRAY_SIZE(usart_clocks_lookups));
278
279 clk_register(&pck0);
280 clk_register(&pck1);
281 clk_register(&pck2);
282 clk_register(&pck3);
283}
284
285static struct clk_lookup console_clock_lookup;
286
287void __init at91cap9_set_console_clock(int id)
288{
289 if (id >= ARRAY_SIZE(usart_clocks_lookups))
290 return;
291
292 console_clock_lookup.con_id = "usart";
293 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
294 clkdev_add(&console_clock_lookup);
295}
296
297/* --------------------------------------------------------------------
298 * GPIO
299 * -------------------------------------------------------------------- */
300
301static struct at91_gpio_bank at91cap9_gpio[] __initdata = {
302 {
303 .id = AT91CAP9_ID_PIOABCD,
304 .regbase = AT91CAP9_BASE_PIOA,
305 }, {
306 .id = AT91CAP9_ID_PIOABCD,
307 .regbase = AT91CAP9_BASE_PIOB,
308 }, {
309 .id = AT91CAP9_ID_PIOABCD,
310 .regbase = AT91CAP9_BASE_PIOC,
311 }, {
312 .id = AT91CAP9_ID_PIOABCD,
313 .regbase = AT91CAP9_BASE_PIOD,
314 }
315};
316
317static void at91cap9_idle(void)
318{
319 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
320 cpu_do_idle();
321}
322
323/* --------------------------------------------------------------------
324 * AT91CAP9 processor initialization
325 * -------------------------------------------------------------------- */
326
327static void __init at91cap9_map_io(void)
328{
329 at91_init_sram(0, AT91CAP9_SRAM_BASE, AT91CAP9_SRAM_SIZE);
330}
331
332static void __init at91cap9_ioremap_registers(void)
333{
334 at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC);
335 at91_ioremap_rstc(AT91CAP9_BASE_RSTC);
336 at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
337 at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC);
338}
339
340static void __init at91cap9_initialize(void)
341{
342 arm_pm_idle = at91cap9_idle;
343 arm_pm_restart = at91sam9g45_restart;
344 at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
345
346 /* Register GPIO subsystem */
347 at91_gpio_init(at91cap9_gpio, 4);
348
349 /* Remember the silicon revision */
350 if (cpu_is_at91cap9_revB())
351 system_rev = 0xB;
352 else if (cpu_is_at91cap9_revC())
353 system_rev = 0xC;
354}
355
356/* --------------------------------------------------------------------
357 * Interrupt initialization
358 * -------------------------------------------------------------------- */
359
360/*
361 * The default interrupt priority levels (0 = lowest, 7 = highest).
362 */
363static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
364 7, /* Advanced Interrupt Controller (FIQ) */
365 7, /* System Peripherals */
366 1, /* Parallel IO Controller A, B, C and D */
367 0, /* MP Block Peripheral 0 */
368 0, /* MP Block Peripheral 1 */
369 0, /* MP Block Peripheral 2 */
370 0, /* MP Block Peripheral 3 */
371 0, /* MP Block Peripheral 4 */
372 5, /* USART 0 */
373 5, /* USART 1 */
374 5, /* USART 2 */
375 0, /* Multimedia Card Interface 0 */
376 0, /* Multimedia Card Interface 1 */
377 3, /* CAN */
378 6, /* Two-Wire Interface */
379 5, /* Serial Peripheral Interface 0 */
380 5, /* Serial Peripheral Interface 1 */
381 4, /* Serial Synchronous Controller 0 */
382 4, /* Serial Synchronous Controller 1 */
383 5, /* AC97 Controller */
384 0, /* Timer Counter 0, 1 and 2 */
385 0, /* Pulse Width Modulation Controller */
386 3, /* Ethernet */
387 0, /* Advanced Encryption Standard, Triple DES*/
388 0, /* Analog-to-Digital Converter */
389 0, /* Image Sensor Interface */
390 3, /* LCD Controller */
391 0, /* DMA Controller */
392 2, /* USB Device Port */
393 2, /* USB Host port */
394 0, /* Advanced Interrupt Controller (IRQ0) */
395 0, /* Advanced Interrupt Controller (IRQ1) */
396};
397
398struct at91_init_soc __initdata at91cap9_soc = {
399 .map_io = at91cap9_map_io,
400 .default_irq_priority = at91cap9_default_irq_priority,
401 .ioremap_registers = at91cap9_ioremap_registers,
402 .register_clocks = at91cap9_register_clocks,
403 .init = at91cap9_initialize,
404};
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c
deleted file mode 100644
index d298fb7cb210..000000000000
--- a/arch/arm/mach-at91/at91cap9_devices.c
+++ /dev/null
@@ -1,1273 +0,0 @@
1/*
2 * arch/arm/mach-at91/at91cap9_devices.c
3 *
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2007 Atmel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 */
14#include <asm/mach/arch.h>
15#include <asm/mach/map.h>
16#include <asm/mach/irq.h>
17
18#include <linux/dma-mapping.h>
19#include <linux/gpio.h>
20#include <linux/platform_device.h>
21#include <linux/i2c-gpio.h>
22
23#include <video/atmel_lcdc.h>
24
25#include <mach/board.h>
26#include <mach/cpu.h>
27#include <mach/at91cap9.h>
28#include <mach/at91cap9_matrix.h>
29#include <mach/at91sam9_smc.h>
30
31#include "generic.h"
32
33
34/* --------------------------------------------------------------------
35 * USB Host
36 * -------------------------------------------------------------------- */
37
38#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
39static u64 ohci_dmamask = DMA_BIT_MASK(32);
40static struct at91_usbh_data usbh_data;
41
42static struct resource usbh_resources[] = {
43 [0] = {
44 .start = AT91CAP9_UHP_BASE,
45 .end = AT91CAP9_UHP_BASE + SZ_1M - 1,
46 .flags = IORESOURCE_MEM,
47 },
48 [1] = {
49 .start = AT91CAP9_ID_UHP,
50 .end = AT91CAP9_ID_UHP,
51 .flags = IORESOURCE_IRQ,
52 },
53};
54
55static struct platform_device at91_usbh_device = {
56 .name = "at91_ohci",
57 .id = -1,
58 .dev = {
59 .dma_mask = &ohci_dmamask,
60 .coherent_dma_mask = DMA_BIT_MASK(32),
61 .platform_data = &usbh_data,
62 },
63 .resource = usbh_resources,
64 .num_resources = ARRAY_SIZE(usbh_resources),
65};
66
67void __init at91_add_device_usbh(struct at91_usbh_data *data)
68{
69 int i;
70
71 if (!data)
72 return;
73
74 if (cpu_is_at91cap9_revB())
75 irq_set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH);
76
77 /* Enable VBus control for UHP ports */
78 for (i = 0; i < data->ports; i++) {
79 if (gpio_is_valid(data->vbus_pin[i]))
80 at91_set_gpio_output(data->vbus_pin[i], 0);
81 }
82
83 /* Enable overcurrent notification */
84 for (i = 0; i < data->ports; i++) {
85 if (data->overcurrent_pin[i])
86 at91_set_gpio_input(data->overcurrent_pin[i], 1);
87 }
88
89 usbh_data = *data;
90 platform_device_register(&at91_usbh_device);
91}
92#else
93void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
94#endif
95
96
97/* --------------------------------------------------------------------
98 * USB HS Device (Gadget)
99 * -------------------------------------------------------------------- */
100
101#if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
102
103static struct resource usba_udc_resources[] = {
104 [0] = {
105 .start = AT91CAP9_UDPHS_FIFO,
106 .end = AT91CAP9_UDPHS_FIFO + SZ_512K - 1,
107 .flags = IORESOURCE_MEM,
108 },
109 [1] = {
110 .start = AT91CAP9_BASE_UDPHS,
111 .end = AT91CAP9_BASE_UDPHS + SZ_1K - 1,
112 .flags = IORESOURCE_MEM,
113 },
114 [2] = {
115 .start = AT91CAP9_ID_UDPHS,
116 .end = AT91CAP9_ID_UDPHS,
117 .flags = IORESOURCE_IRQ,
118 },
119};
120
121#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
122 [idx] = { \
123 .name = nam, \
124 .index = idx, \
125 .fifo_size = maxpkt, \
126 .nr_banks = maxbk, \
127 .can_dma = dma, \
128 .can_isoc = isoc, \
129 }
130
131static struct usba_ep_data usba_udc_ep[] = {
132 EP("ep0", 0, 64, 1, 0, 0),
133 EP("ep1", 1, 1024, 3, 1, 1),
134 EP("ep2", 2, 1024, 3, 1, 1),
135 EP("ep3", 3, 1024, 2, 1, 1),
136 EP("ep4", 4, 1024, 2, 1, 1),
137 EP("ep5", 5, 1024, 2, 1, 0),
138 EP("ep6", 6, 1024, 2, 1, 0),
139 EP("ep7", 7, 1024, 2, 0, 0),
140};
141
142#undef EP
143
144/*
145 * pdata doesn't have room for any endpoints, so we need to
146 * append room for the ones we need right after it.
147 */
148static struct {
149 struct usba_platform_data pdata;
150 struct usba_ep_data ep[8];
151} usba_udc_data;
152
153static struct platform_device at91_usba_udc_device = {
154 .name = "atmel_usba_udc",
155 .id = -1,
156 .dev = {
157 .platform_data = &usba_udc_data.pdata,
158 },
159 .resource = usba_udc_resources,
160 .num_resources = ARRAY_SIZE(usba_udc_resources),
161};
162
163void __init at91_add_device_usba(struct usba_platform_data *data)
164{
165 if (cpu_is_at91cap9_revB()) {
166 irq_set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH);
167 at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS |
168 AT91_MATRIX_UDPHS_BYPASS_LOCK);
169 }
170 else
171 at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS);
172
173 /*
174 * Invalid pins are 0 on AT91, but the usba driver is shared
175 * with AVR32, which use negative values instead. Once/if
176 * gpio_is_valid() is ported to AT91, revisit this code.
177 */
178 usba_udc_data.pdata.vbus_pin = -EINVAL;
179 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
180 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
181
182 if (data && gpio_is_valid(data->vbus_pin)) {
183 at91_set_gpio_input(data->vbus_pin, 0);
184 at91_set_deglitch(data->vbus_pin, 1);
185 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
186 }
187
188 /* Pullup pin is handled internally by USB device peripheral */
189
190 platform_device_register(&at91_usba_udc_device);
191}
192#else
193void __init at91_add_device_usba(struct usba_platform_data *data) {}
194#endif
195
196
197/* --------------------------------------------------------------------
198 * Ethernet
199 * -------------------------------------------------------------------- */
200
201#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
202static u64 eth_dmamask = DMA_BIT_MASK(32);
203static struct macb_platform_data eth_data;
204
205static struct resource eth_resources[] = {
206 [0] = {
207 .start = AT91CAP9_BASE_EMAC,
208 .end = AT91CAP9_BASE_EMAC + SZ_16K - 1,
209 .flags = IORESOURCE_MEM,
210 },
211 [1] = {
212 .start = AT91CAP9_ID_EMAC,
213 .end = AT91CAP9_ID_EMAC,
214 .flags = IORESOURCE_IRQ,
215 },
216};
217
218static struct platform_device at91cap9_eth_device = {
219 .name = "macb",
220 .id = -1,
221 .dev = {
222 .dma_mask = &eth_dmamask,
223 .coherent_dma_mask = DMA_BIT_MASK(32),
224 .platform_data = &eth_data,
225 },
226 .resource = eth_resources,
227 .num_resources = ARRAY_SIZE(eth_resources),
228};
229
230void __init at91_add_device_eth(struct macb_platform_data *data)
231{
232 if (!data)
233 return;
234
235 if (gpio_is_valid(data->phy_irq_pin)) {
236 at91_set_gpio_input(data->phy_irq_pin, 0);
237 at91_set_deglitch(data->phy_irq_pin, 1);
238 }
239
240 /* Pins used for MII and RMII */
241 at91_set_A_periph(AT91_PIN_PB21, 0); /* ETXCK_EREFCK */
242 at91_set_A_periph(AT91_PIN_PB22, 0); /* ERXDV */
243 at91_set_A_periph(AT91_PIN_PB25, 0); /* ERX0 */
244 at91_set_A_periph(AT91_PIN_PB26, 0); /* ERX1 */
245 at91_set_A_periph(AT91_PIN_PB27, 0); /* ERXER */
246 at91_set_A_periph(AT91_PIN_PB28, 0); /* ETXEN */
247 at91_set_A_periph(AT91_PIN_PB23, 0); /* ETX0 */
248 at91_set_A_periph(AT91_PIN_PB24, 0); /* ETX1 */
249 at91_set_A_periph(AT91_PIN_PB30, 0); /* EMDIO */
250 at91_set_A_periph(AT91_PIN_PB29, 0); /* EMDC */
251
252 if (!data->is_rmii) {
253 at91_set_B_periph(AT91_PIN_PC25, 0); /* ECRS */
254 at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
255 at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
256 at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
257 at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
258 at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
259 at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
260 at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
261 }
262
263 eth_data = *data;
264 platform_device_register(&at91cap9_eth_device);
265}
266#else
267void __init at91_add_device_eth(struct macb_platform_data *data) {}
268#endif
269
270
271/* --------------------------------------------------------------------
272 * MMC / SD
273 * -------------------------------------------------------------------- */
274
275#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
276static u64 mmc_dmamask = DMA_BIT_MASK(32);
277static struct at91_mmc_data mmc0_data, mmc1_data;
278
279static struct resource mmc0_resources[] = {
280 [0] = {
281 .start = AT91CAP9_BASE_MCI0,
282 .end = AT91CAP9_BASE_MCI0 + SZ_16K - 1,
283 .flags = IORESOURCE_MEM,
284 },
285 [1] = {
286 .start = AT91CAP9_ID_MCI0,
287 .end = AT91CAP9_ID_MCI0,
288 .flags = IORESOURCE_IRQ,
289 },
290};
291
292static struct platform_device at91cap9_mmc0_device = {
293 .name = "at91_mci",
294 .id = 0,
295 .dev = {
296 .dma_mask = &mmc_dmamask,
297 .coherent_dma_mask = DMA_BIT_MASK(32),
298 .platform_data = &mmc0_data,
299 },
300 .resource = mmc0_resources,
301 .num_resources = ARRAY_SIZE(mmc0_resources),
302};
303
304static struct resource mmc1_resources[] = {
305 [0] = {
306 .start = AT91CAP9_BASE_MCI1,
307 .end = AT91CAP9_BASE_MCI1 + SZ_16K - 1,
308 .flags = IORESOURCE_MEM,
309 },
310 [1] = {
311 .start = AT91CAP9_ID_MCI1,
312 .end = AT91CAP9_ID_MCI1,
313 .flags = IORESOURCE_IRQ,
314 },
315};
316
317static struct platform_device at91cap9_mmc1_device = {
318 .name = "at91_mci",
319 .id = 1,
320 .dev = {
321 .dma_mask = &mmc_dmamask,
322 .coherent_dma_mask = DMA_BIT_MASK(32),
323 .platform_data = &mmc1_data,
324 },
325 .resource = mmc1_resources,
326 .num_resources = ARRAY_SIZE(mmc1_resources),
327};
328
329void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
330{
331 if (!data)
332 return;
333
334 /* input/irq */
335 if (gpio_is_valid(data->det_pin)) {
336 at91_set_gpio_input(data->det_pin, 1);
337 at91_set_deglitch(data->det_pin, 1);
338 }
339 if (gpio_is_valid(data->wp_pin))
340 at91_set_gpio_input(data->wp_pin, 1);
341 if (gpio_is_valid(data->vcc_pin))
342 at91_set_gpio_output(data->vcc_pin, 0);
343
344 if (mmc_id == 0) { /* MCI0 */
345 /* CLK */
346 at91_set_A_periph(AT91_PIN_PA2, 0);
347
348 /* CMD */
349 at91_set_A_periph(AT91_PIN_PA1, 1);
350
351 /* DAT0, maybe DAT1..DAT3 */
352 at91_set_A_periph(AT91_PIN_PA0, 1);
353 if (data->wire4) {
354 at91_set_A_periph(AT91_PIN_PA3, 1);
355 at91_set_A_periph(AT91_PIN_PA4, 1);
356 at91_set_A_periph(AT91_PIN_PA5, 1);
357 }
358
359 mmc0_data = *data;
360 platform_device_register(&at91cap9_mmc0_device);
361 } else { /* MCI1 */
362 /* CLK */
363 at91_set_A_periph(AT91_PIN_PA16, 0);
364
365 /* CMD */
366 at91_set_A_periph(AT91_PIN_PA17, 1);
367
368 /* DAT0, maybe DAT1..DAT3 */
369 at91_set_A_periph(AT91_PIN_PA18, 1);
370 if (data->wire4) {
371 at91_set_A_periph(AT91_PIN_PA19, 1);
372 at91_set_A_periph(AT91_PIN_PA20, 1);
373 at91_set_A_periph(AT91_PIN_PA21, 1);
374 }
375
376 mmc1_data = *data;
377 platform_device_register(&at91cap9_mmc1_device);
378 }
379}
380#else
381void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
382#endif
383
384
385/* --------------------------------------------------------------------
386 * NAND / SmartMedia
387 * -------------------------------------------------------------------- */
388
389#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
390static struct atmel_nand_data nand_data;
391
392#define NAND_BASE AT91_CHIPSELECT_3
393
394static struct resource nand_resources[] = {
395 [0] = {
396 .start = NAND_BASE,
397 .end = NAND_BASE + SZ_256M - 1,
398 .flags = IORESOURCE_MEM,
399 },
400 [1] = {
401 .start = AT91CAP9_BASE_ECC,
402 .end = AT91CAP9_BASE_ECC + SZ_512 - 1,
403 .flags = IORESOURCE_MEM,
404 }
405};
406
407static struct platform_device at91cap9_nand_device = {
408 .name = "atmel_nand",
409 .id = -1,
410 .dev = {
411 .platform_data = &nand_data,
412 },
413 .resource = nand_resources,
414 .num_resources = ARRAY_SIZE(nand_resources),
415};
416
417void __init at91_add_device_nand(struct atmel_nand_data *data)
418{
419 unsigned long csa;
420
421 if (!data)
422 return;
423
424 csa = at91_sys_read(AT91_MATRIX_EBICSA);
425 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
426
427 /* enable pin */
428 if (gpio_is_valid(data->enable_pin))
429 at91_set_gpio_output(data->enable_pin, 1);
430
431 /* ready/busy pin */
432 if (gpio_is_valid(data->rdy_pin))
433 at91_set_gpio_input(data->rdy_pin, 1);
434
435 /* card detect pin */
436 if (gpio_is_valid(data->det_pin))
437 at91_set_gpio_input(data->det_pin, 1);
438
439 nand_data = *data;
440 platform_device_register(&at91cap9_nand_device);
441}
442#else
443void __init at91_add_device_nand(struct atmel_nand_data *data) {}
444#endif
445
446
447/* --------------------------------------------------------------------
448 * TWI (i2c)
449 * -------------------------------------------------------------------- */
450
451/*
452 * Prefer the GPIO code since the TWI controller isn't robust
453 * (gets overruns and underruns under load) and can only issue
454 * repeated STARTs in one scenario (the driver doesn't yet handle them).
455 */
456#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
457
458static struct i2c_gpio_platform_data pdata = {
459 .sda_pin = AT91_PIN_PB4,
460 .sda_is_open_drain = 1,
461 .scl_pin = AT91_PIN_PB5,
462 .scl_is_open_drain = 1,
463 .udelay = 2, /* ~100 kHz */
464};
465
466static struct platform_device at91cap9_twi_device = {
467 .name = "i2c-gpio",
468 .id = -1,
469 .dev.platform_data = &pdata,
470};
471
472void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
473{
474 at91_set_GPIO_periph(AT91_PIN_PB4, 1); /* TWD (SDA) */
475 at91_set_multi_drive(AT91_PIN_PB4, 1);
476
477 at91_set_GPIO_periph(AT91_PIN_PB5, 1); /* TWCK (SCL) */
478 at91_set_multi_drive(AT91_PIN_PB5, 1);
479
480 i2c_register_board_info(0, devices, nr_devices);
481 platform_device_register(&at91cap9_twi_device);
482}
483
484#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
485
486static struct resource twi_resources[] = {
487 [0] = {
488 .start = AT91CAP9_BASE_TWI,
489 .end = AT91CAP9_BASE_TWI + SZ_16K - 1,
490 .flags = IORESOURCE_MEM,
491 },
492 [1] = {
493 .start = AT91CAP9_ID_TWI,
494 .end = AT91CAP9_ID_TWI,
495 .flags = IORESOURCE_IRQ,
496 },
497};
498
499static struct platform_device at91cap9_twi_device = {
500 .name = "at91_i2c",
501 .id = -1,
502 .resource = twi_resources,
503 .num_resources = ARRAY_SIZE(twi_resources),
504};
505
506void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
507{
508 /* pins used for TWI interface */
509 at91_set_B_periph(AT91_PIN_PB4, 0); /* TWD */
510 at91_set_multi_drive(AT91_PIN_PB4, 1);
511
512 at91_set_B_periph(AT91_PIN_PB5, 0); /* TWCK */
513 at91_set_multi_drive(AT91_PIN_PB5, 1);
514
515 i2c_register_board_info(0, devices, nr_devices);
516 platform_device_register(&at91cap9_twi_device);
517}
518#else
519void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
520#endif
521
522/* --------------------------------------------------------------------
523 * SPI
524 * -------------------------------------------------------------------- */
525
526#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
527static u64 spi_dmamask = DMA_BIT_MASK(32);
528
529static struct resource spi0_resources[] = {
530 [0] = {
531 .start = AT91CAP9_BASE_SPI0,
532 .end = AT91CAP9_BASE_SPI0 + SZ_16K - 1,
533 .flags = IORESOURCE_MEM,
534 },
535 [1] = {
536 .start = AT91CAP9_ID_SPI0,
537 .end = AT91CAP9_ID_SPI0,
538 .flags = IORESOURCE_IRQ,
539 },
540};
541
542static struct platform_device at91cap9_spi0_device = {
543 .name = "atmel_spi",
544 .id = 0,
545 .dev = {
546 .dma_mask = &spi_dmamask,
547 .coherent_dma_mask = DMA_BIT_MASK(32),
548 },
549 .resource = spi0_resources,
550 .num_resources = ARRAY_SIZE(spi0_resources),
551};
552
553static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA5, AT91_PIN_PA3, AT91_PIN_PD0, AT91_PIN_PD1 };
554
555static struct resource spi1_resources[] = {
556 [0] = {
557 .start = AT91CAP9_BASE_SPI1,
558 .end = AT91CAP9_BASE_SPI1 + SZ_16K - 1,
559 .flags = IORESOURCE_MEM,
560 },
561 [1] = {
562 .start = AT91CAP9_ID_SPI1,
563 .end = AT91CAP9_ID_SPI1,
564 .flags = IORESOURCE_IRQ,
565 },
566};
567
568static struct platform_device at91cap9_spi1_device = {
569 .name = "atmel_spi",
570 .id = 1,
571 .dev = {
572 .dma_mask = &spi_dmamask,
573 .coherent_dma_mask = DMA_BIT_MASK(32),
574 },
575 .resource = spi1_resources,
576 .num_resources = ARRAY_SIZE(spi1_resources),
577};
578
579static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB15, AT91_PIN_PB16, AT91_PIN_PB17, AT91_PIN_PB18 };
580
581void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
582{
583 int i;
584 unsigned long cs_pin;
585 short enable_spi0 = 0;
586 short enable_spi1 = 0;
587
588 /* Choose SPI chip-selects */
589 for (i = 0; i < nr_devices; i++) {
590 if (devices[i].controller_data)
591 cs_pin = (unsigned long) devices[i].controller_data;
592 else if (devices[i].bus_num == 0)
593 cs_pin = spi0_standard_cs[devices[i].chip_select];
594 else
595 cs_pin = spi1_standard_cs[devices[i].chip_select];
596
597 if (devices[i].bus_num == 0)
598 enable_spi0 = 1;
599 else
600 enable_spi1 = 1;
601
602 /* enable chip-select pin */
603 at91_set_gpio_output(cs_pin, 1);
604
605 /* pass chip-select pin to driver */
606 devices[i].controller_data = (void *) cs_pin;
607 }
608
609 spi_register_board_info(devices, nr_devices);
610
611 /* Configure SPI bus(es) */
612 if (enable_spi0) {
613 at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
614 at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
615 at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
616
617 platform_device_register(&at91cap9_spi0_device);
618 }
619 if (enable_spi1) {
620 at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */
621 at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */
622 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */
623
624 platform_device_register(&at91cap9_spi1_device);
625 }
626}
627#else
628void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
629#endif
630
631
632/* --------------------------------------------------------------------
633 * Timer/Counter block
634 * -------------------------------------------------------------------- */
635
636#ifdef CONFIG_ATMEL_TCLIB
637
638static struct resource tcb_resources[] = {
639 [0] = {
640 .start = AT91CAP9_BASE_TCB0,
641 .end = AT91CAP9_BASE_TCB0 + SZ_16K - 1,
642 .flags = IORESOURCE_MEM,
643 },
644 [1] = {
645 .start = AT91CAP9_ID_TCB,
646 .end = AT91CAP9_ID_TCB,
647 .flags = IORESOURCE_IRQ,
648 },
649};
650
651static struct platform_device at91cap9_tcb_device = {
652 .name = "atmel_tcb",
653 .id = 0,
654 .resource = tcb_resources,
655 .num_resources = ARRAY_SIZE(tcb_resources),
656};
657
658static void __init at91_add_device_tc(void)
659{
660 platform_device_register(&at91cap9_tcb_device);
661}
662#else
663static void __init at91_add_device_tc(void) { }
664#endif
665
666
667/* --------------------------------------------------------------------
668 * RTT
669 * -------------------------------------------------------------------- */
670
671static struct resource rtt_resources[] = {
672 {
673 .start = AT91CAP9_BASE_RTT,
674 .end = AT91CAP9_BASE_RTT + SZ_16 - 1,
675 .flags = IORESOURCE_MEM,
676 }
677};
678
679static struct platform_device at91cap9_rtt_device = {
680 .name = "at91_rtt",
681 .id = 0,
682 .resource = rtt_resources,
683 .num_resources = ARRAY_SIZE(rtt_resources),
684};
685
686static void __init at91_add_device_rtt(void)
687{
688 platform_device_register(&at91cap9_rtt_device);
689}
690
691
692/* --------------------------------------------------------------------
693 * Watchdog
694 * -------------------------------------------------------------------- */
695
696#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
697static struct resource wdt_resources[] = {
698 {
699 .start = AT91CAP9_BASE_WDT,
700 .end = AT91CAP9_BASE_WDT + SZ_16 - 1,
701 .flags = IORESOURCE_MEM,
702 }
703};
704
705static struct platform_device at91cap9_wdt_device = {
706 .name = "at91_wdt",
707 .id = -1,
708 .resource = wdt_resources,
709 .num_resources = ARRAY_SIZE(wdt_resources),
710};
711
712static void __init at91_add_device_watchdog(void)
713{
714 platform_device_register(&at91cap9_wdt_device);
715}
716#else
717static void __init at91_add_device_watchdog(void) {}
718#endif
719
720
721/* --------------------------------------------------------------------
722 * PWM
723 * --------------------------------------------------------------------*/
724
725#if defined(CONFIG_ATMEL_PWM)
726static u32 pwm_mask;
727
728static struct resource pwm_resources[] = {
729 [0] = {
730 .start = AT91CAP9_BASE_PWMC,
731 .end = AT91CAP9_BASE_PWMC + SZ_16K - 1,
732 .flags = IORESOURCE_MEM,
733 },
734 [1] = {
735 .start = AT91CAP9_ID_PWMC,
736 .end = AT91CAP9_ID_PWMC,
737 .flags = IORESOURCE_IRQ,
738 },
739};
740
741static struct platform_device at91cap9_pwm0_device = {
742 .name = "atmel_pwm",
743 .id = -1,
744 .dev = {
745 .platform_data = &pwm_mask,
746 },
747 .resource = pwm_resources,
748 .num_resources = ARRAY_SIZE(pwm_resources),
749};
750
751void __init at91_add_device_pwm(u32 mask)
752{
753 if (mask & (1 << AT91_PWM0))
754 at91_set_A_periph(AT91_PIN_PB19, 1); /* enable PWM0 */
755
756 if (mask & (1 << AT91_PWM1))
757 at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM1 */
758
759 if (mask & (1 << AT91_PWM2))
760 at91_set_B_periph(AT91_PIN_PC29, 1); /* enable PWM2 */
761
762 if (mask & (1 << AT91_PWM3))
763 at91_set_B_periph(AT91_PIN_PA11, 1); /* enable PWM3 */
764
765 pwm_mask = mask;
766
767 platform_device_register(&at91cap9_pwm0_device);
768}
769#else
770void __init at91_add_device_pwm(u32 mask) {}
771#endif
772
773
774
775/* --------------------------------------------------------------------
776 * AC97
777 * -------------------------------------------------------------------- */
778
779#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
780static u64 ac97_dmamask = DMA_BIT_MASK(32);
781static struct ac97c_platform_data ac97_data;
782
783static struct resource ac97_resources[] = {
784 [0] = {
785 .start = AT91CAP9_BASE_AC97C,
786 .end = AT91CAP9_BASE_AC97C + SZ_16K - 1,
787 .flags = IORESOURCE_MEM,
788 },
789 [1] = {
790 .start = AT91CAP9_ID_AC97C,
791 .end = AT91CAP9_ID_AC97C,
792 .flags = IORESOURCE_IRQ,
793 },
794};
795
796static struct platform_device at91cap9_ac97_device = {
797 .name = "atmel_ac97c",
798 .id = 1,
799 .dev = {
800 .dma_mask = &ac97_dmamask,
801 .coherent_dma_mask = DMA_BIT_MASK(32),
802 .platform_data = &ac97_data,
803 },
804 .resource = ac97_resources,
805 .num_resources = ARRAY_SIZE(ac97_resources),
806};
807
808void __init at91_add_device_ac97(struct ac97c_platform_data *data)
809{
810 if (!data)
811 return;
812
813 at91_set_A_periph(AT91_PIN_PA6, 0); /* AC97FS */
814 at91_set_A_periph(AT91_PIN_PA7, 0); /* AC97CK */
815 at91_set_A_periph(AT91_PIN_PA8, 0); /* AC97TX */
816 at91_set_A_periph(AT91_PIN_PA9, 0); /* AC97RX */
817
818 /* reset */
819 if (gpio_is_valid(data->reset_pin))
820 at91_set_gpio_output(data->reset_pin, 0);
821
822 ac97_data = *data;
823 platform_device_register(&at91cap9_ac97_device);
824}
825#else
826void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
827#endif
828
829
830/* --------------------------------------------------------------------
831 * LCD Controller
832 * -------------------------------------------------------------------- */
833
834#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
835static u64 lcdc_dmamask = DMA_BIT_MASK(32);
836static struct atmel_lcdfb_info lcdc_data;
837
838static struct resource lcdc_resources[] = {
839 [0] = {
840 .start = AT91CAP9_LCDC_BASE,
841 .end = AT91CAP9_LCDC_BASE + SZ_4K - 1,
842 .flags = IORESOURCE_MEM,
843 },
844 [1] = {
845 .start = AT91CAP9_ID_LCDC,
846 .end = AT91CAP9_ID_LCDC,
847 .flags = IORESOURCE_IRQ,
848 },
849};
850
851static struct platform_device at91_lcdc_device = {
852 .name = "atmel_lcdfb",
853 .id = 0,
854 .dev = {
855 .dma_mask = &lcdc_dmamask,
856 .coherent_dma_mask = DMA_BIT_MASK(32),
857 .platform_data = &lcdc_data,
858 },
859 .resource = lcdc_resources,
860 .num_resources = ARRAY_SIZE(lcdc_resources),
861};
862
863void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
864{
865 if (!data)
866 return;
867
868 if (cpu_is_at91cap9_revB())
869 irq_set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH);
870
871 at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
872 at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
873 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
874 at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
875 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
876 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
877 at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
878 at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
879 at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
880 at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
881 at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
882 at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
883 at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
884 at91_set_A_periph(AT91_PIN_PC17, 0); /* LCDD13 */
885 at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
886 at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
887 at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
888 at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
889 at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
890 at91_set_A_periph(AT91_PIN_PC25, 0); /* LCDD21 */
891 at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
892 at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
893
894 lcdc_data = *data;
895 platform_device_register(&at91_lcdc_device);
896}
897#else
898void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
899#endif
900
901
902/* --------------------------------------------------------------------
903 * SSC -- Synchronous Serial Controller
904 * -------------------------------------------------------------------- */
905
906#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
907static u64 ssc0_dmamask = DMA_BIT_MASK(32);
908
909static struct resource ssc0_resources[] = {
910 [0] = {
911 .start = AT91CAP9_BASE_SSC0,
912 .end = AT91CAP9_BASE_SSC0 + SZ_16K - 1,
913 .flags = IORESOURCE_MEM,
914 },
915 [1] = {
916 .start = AT91CAP9_ID_SSC0,
917 .end = AT91CAP9_ID_SSC0,
918 .flags = IORESOURCE_IRQ,
919 },
920};
921
922static struct platform_device at91cap9_ssc0_device = {
923 .name = "ssc",
924 .id = 0,
925 .dev = {
926 .dma_mask = &ssc0_dmamask,
927 .coherent_dma_mask = DMA_BIT_MASK(32),
928 },
929 .resource = ssc0_resources,
930 .num_resources = ARRAY_SIZE(ssc0_resources),
931};
932
933static inline void configure_ssc0_pins(unsigned pins)
934{
935 if (pins & ATMEL_SSC_TF)
936 at91_set_A_periph(AT91_PIN_PB0, 1);
937 if (pins & ATMEL_SSC_TK)
938 at91_set_A_periph(AT91_PIN_PB1, 1);
939 if (pins & ATMEL_SSC_TD)
940 at91_set_A_periph(AT91_PIN_PB2, 1);
941 if (pins & ATMEL_SSC_RD)
942 at91_set_A_periph(AT91_PIN_PB3, 1);
943 if (pins & ATMEL_SSC_RK)
944 at91_set_A_periph(AT91_PIN_PB4, 1);
945 if (pins & ATMEL_SSC_RF)
946 at91_set_A_periph(AT91_PIN_PB5, 1);
947}
948
949static u64 ssc1_dmamask = DMA_BIT_MASK(32);
950
951static struct resource ssc1_resources[] = {
952 [0] = {
953 .start = AT91CAP9_BASE_SSC1,
954 .end = AT91CAP9_BASE_SSC1 + SZ_16K - 1,
955 .flags = IORESOURCE_MEM,
956 },
957 [1] = {
958 .start = AT91CAP9_ID_SSC1,
959 .end = AT91CAP9_ID_SSC1,
960 .flags = IORESOURCE_IRQ,
961 },
962};
963
964static struct platform_device at91cap9_ssc1_device = {
965 .name = "ssc",
966 .id = 1,
967 .dev = {
968 .dma_mask = &ssc1_dmamask,
969 .coherent_dma_mask = DMA_BIT_MASK(32),
970 },
971 .resource = ssc1_resources,
972 .num_resources = ARRAY_SIZE(ssc1_resources),
973};
974
975static inline void configure_ssc1_pins(unsigned pins)
976{
977 if (pins & ATMEL_SSC_TF)
978 at91_set_A_periph(AT91_PIN_PB6, 1);
979 if (pins & ATMEL_SSC_TK)
980 at91_set_A_periph(AT91_PIN_PB7, 1);
981 if (pins & ATMEL_SSC_TD)
982 at91_set_A_periph(AT91_PIN_PB8, 1);
983 if (pins & ATMEL_SSC_RD)
984 at91_set_A_periph(AT91_PIN_PB9, 1);
985 if (pins & ATMEL_SSC_RK)
986 at91_set_A_periph(AT91_PIN_PB10, 1);
987 if (pins & ATMEL_SSC_RF)
988 at91_set_A_periph(AT91_PIN_PB11, 1);
989}
990
991/*
992 * SSC controllers are accessed through library code, instead of any
993 * kind of all-singing/all-dancing driver. For example one could be
994 * used by a particular I2S audio codec's driver, while another one
995 * on the same system might be used by a custom data capture driver.
996 */
997void __init at91_add_device_ssc(unsigned id, unsigned pins)
998{
999 struct platform_device *pdev;
1000
1001 /*
1002 * NOTE: caller is responsible for passing information matching
1003 * "pins" to whatever will be using each particular controller.
1004 */
1005 switch (id) {
1006 case AT91CAP9_ID_SSC0:
1007 pdev = &at91cap9_ssc0_device;
1008 configure_ssc0_pins(pins);
1009 break;
1010 case AT91CAP9_ID_SSC1:
1011 pdev = &at91cap9_ssc1_device;
1012 configure_ssc1_pins(pins);
1013 break;
1014 default:
1015 return;
1016 }
1017
1018 platform_device_register(pdev);
1019}
1020
1021#else
1022void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1023#endif
1024
1025
1026/* --------------------------------------------------------------------
1027 * UART
1028 * -------------------------------------------------------------------- */
1029
1030#if defined(CONFIG_SERIAL_ATMEL)
1031static struct resource dbgu_resources[] = {
1032 [0] = {
1033 .start = AT91CAP9_BASE_DBGU,
1034 .end = AT91CAP9_BASE_DBGU + SZ_512 - 1,
1035 .flags = IORESOURCE_MEM,
1036 },
1037 [1] = {
1038 .start = AT91_ID_SYS,
1039 .end = AT91_ID_SYS,
1040 .flags = IORESOURCE_IRQ,
1041 },
1042};
1043
1044static struct atmel_uart_data dbgu_data = {
1045 .use_dma_tx = 0,
1046 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
1047};
1048
1049static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1050
1051static struct platform_device at91cap9_dbgu_device = {
1052 .name = "atmel_usart",
1053 .id = 0,
1054 .dev = {
1055 .dma_mask = &dbgu_dmamask,
1056 .coherent_dma_mask = DMA_BIT_MASK(32),
1057 .platform_data = &dbgu_data,
1058 },
1059 .resource = dbgu_resources,
1060 .num_resources = ARRAY_SIZE(dbgu_resources),
1061};
1062
1063static inline void configure_dbgu_pins(void)
1064{
1065 at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
1066 at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
1067}
1068
1069static struct resource uart0_resources[] = {
1070 [0] = {
1071 .start = AT91CAP9_BASE_US0,
1072 .end = AT91CAP9_BASE_US0 + SZ_16K - 1,
1073 .flags = IORESOURCE_MEM,
1074 },
1075 [1] = {
1076 .start = AT91CAP9_ID_US0,
1077 .end = AT91CAP9_ID_US0,
1078 .flags = IORESOURCE_IRQ,
1079 },
1080};
1081
1082static struct atmel_uart_data uart0_data = {
1083 .use_dma_tx = 1,
1084 .use_dma_rx = 1,
1085};
1086
1087static u64 uart0_dmamask = DMA_BIT_MASK(32);
1088
1089static struct platform_device at91cap9_uart0_device = {
1090 .name = "atmel_usart",
1091 .id = 1,
1092 .dev = {
1093 .dma_mask = &uart0_dmamask,
1094 .coherent_dma_mask = DMA_BIT_MASK(32),
1095 .platform_data = &uart0_data,
1096 },
1097 .resource = uart0_resources,
1098 .num_resources = ARRAY_SIZE(uart0_resources),
1099};
1100
1101static inline void configure_usart0_pins(unsigned pins)
1102{
1103 at91_set_A_periph(AT91_PIN_PA22, 1); /* TXD0 */
1104 at91_set_A_periph(AT91_PIN_PA23, 0); /* RXD0 */
1105
1106 if (pins & ATMEL_UART_RTS)
1107 at91_set_A_periph(AT91_PIN_PA24, 0); /* RTS0 */
1108 if (pins & ATMEL_UART_CTS)
1109 at91_set_A_periph(AT91_PIN_PA25, 0); /* CTS0 */
1110}
1111
1112static struct resource uart1_resources[] = {
1113 [0] = {
1114 .start = AT91CAP9_BASE_US1,
1115 .end = AT91CAP9_BASE_US1 + SZ_16K - 1,
1116 .flags = IORESOURCE_MEM,
1117 },
1118 [1] = {
1119 .start = AT91CAP9_ID_US1,
1120 .end = AT91CAP9_ID_US1,
1121 .flags = IORESOURCE_IRQ,
1122 },
1123};
1124
1125static struct atmel_uart_data uart1_data = {
1126 .use_dma_tx = 1,
1127 .use_dma_rx = 1,
1128};
1129
1130static u64 uart1_dmamask = DMA_BIT_MASK(32);
1131
1132static struct platform_device at91cap9_uart1_device = {
1133 .name = "atmel_usart",
1134 .id = 2,
1135 .dev = {
1136 .dma_mask = &uart1_dmamask,
1137 .coherent_dma_mask = DMA_BIT_MASK(32),
1138 .platform_data = &uart1_data,
1139 },
1140 .resource = uart1_resources,
1141 .num_resources = ARRAY_SIZE(uart1_resources),
1142};
1143
1144static inline void configure_usart1_pins(unsigned pins)
1145{
1146 at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
1147 at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
1148
1149 if (pins & ATMEL_UART_RTS)
1150 at91_set_B_periph(AT91_PIN_PD7, 0); /* RTS1 */
1151 if (pins & ATMEL_UART_CTS)
1152 at91_set_B_periph(AT91_PIN_PD8, 0); /* CTS1 */
1153}
1154
1155static struct resource uart2_resources[] = {
1156 [0] = {
1157 .start = AT91CAP9_BASE_US2,
1158 .end = AT91CAP9_BASE_US2 + SZ_16K - 1,
1159 .flags = IORESOURCE_MEM,
1160 },
1161 [1] = {
1162 .start = AT91CAP9_ID_US2,
1163 .end = AT91CAP9_ID_US2,
1164 .flags = IORESOURCE_IRQ,
1165 },
1166};
1167
1168static struct atmel_uart_data uart2_data = {
1169 .use_dma_tx = 1,
1170 .use_dma_rx = 1,
1171};
1172
1173static u64 uart2_dmamask = DMA_BIT_MASK(32);
1174
1175static struct platform_device at91cap9_uart2_device = {
1176 .name = "atmel_usart",
1177 .id = 3,
1178 .dev = {
1179 .dma_mask = &uart2_dmamask,
1180 .coherent_dma_mask = DMA_BIT_MASK(32),
1181 .platform_data = &uart2_data,
1182 },
1183 .resource = uart2_resources,
1184 .num_resources = ARRAY_SIZE(uart2_resources),
1185};
1186
1187static inline void configure_usart2_pins(unsigned pins)
1188{
1189 at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
1190 at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
1191
1192 if (pins & ATMEL_UART_RTS)
1193 at91_set_B_periph(AT91_PIN_PD5, 0); /* RTS2 */
1194 if (pins & ATMEL_UART_CTS)
1195 at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */
1196}
1197
1198static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1199struct platform_device *atmel_default_console_device; /* the serial console device */
1200
1201void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1202{
1203 struct platform_device *pdev;
1204 struct atmel_uart_data *pdata;
1205
1206 switch (id) {
1207 case 0: /* DBGU */
1208 pdev = &at91cap9_dbgu_device;
1209 configure_dbgu_pins();
1210 break;
1211 case AT91CAP9_ID_US0:
1212 pdev = &at91cap9_uart0_device;
1213 configure_usart0_pins(pins);
1214 break;
1215 case AT91CAP9_ID_US1:
1216 pdev = &at91cap9_uart1_device;
1217 configure_usart1_pins(pins);
1218 break;
1219 case AT91CAP9_ID_US2:
1220 pdev = &at91cap9_uart2_device;
1221 configure_usart2_pins(pins);
1222 break;
1223 default:
1224 return;
1225 }
1226 pdata = pdev->dev.platform_data;
1227 pdata->num = portnr; /* update to mapped ID */
1228
1229 if (portnr < ATMEL_MAX_UART)
1230 at91_uarts[portnr] = pdev;
1231}
1232
1233void __init at91_set_serial_console(unsigned portnr)
1234{
1235 if (portnr < ATMEL_MAX_UART) {
1236 atmel_default_console_device = at91_uarts[portnr];
1237 at91cap9_set_console_clock(at91_uarts[portnr]->id);
1238 }
1239}
1240
1241void __init at91_add_device_serial(void)
1242{
1243 int i;
1244
1245 for (i = 0; i < ATMEL_MAX_UART; i++) {
1246 if (at91_uarts[i])
1247 platform_device_register(at91_uarts[i]);
1248 }
1249
1250 if (!atmel_default_console_device)
1251 printk(KERN_INFO "AT91: No default serial console defined.\n");
1252}
1253#else
1254void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1255void __init at91_set_serial_console(unsigned portnr) {}
1256void __init at91_add_device_serial(void) {}
1257#endif
1258
1259
1260/* -------------------------------------------------------------------- */
1261/*
1262 * These devices are always present and don't need any board-specific
1263 * setup.
1264 */
1265static int __init at91_add_standard_devices(void)
1266{
1267 at91_add_device_rtt();
1268 at91_add_device_watchdog();
1269 at91_add_device_tc();
1270 return 0;
1271}
1272
1273arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index dd6e2de13420..0df1045311e4 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -295,7 +295,7 @@ static void at91rm9200_idle(void)
295 * Disable the processor clock. The processor will be automatically 295 * Disable the processor clock. The processor will be automatically
296 * re-enabled by an interrupt or by a reset. 296 * re-enabled by an interrupt or by a reset.
297 */ 297 */
298 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK); 298 at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
299} 299}
300 300
301static void at91rm9200_restart(char mode, const char *cmd) 301static void at91rm9200_restart(char mode, const char *cmd)
@@ -303,8 +303,8 @@ static void at91rm9200_restart(char mode, const char *cmd)
303 /* 303 /*
304 * Perform a hardware reset with the use of the Watchdog timer. 304 * Perform a hardware reset with the use of the Watchdog timer.
305 */ 305 */
306 at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1); 306 at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
307 at91_sys_write(AT91_ST_CR, AT91_ST_WDRST); 307 at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
308} 308}
309 309
310/* -------------------------------------------------------------------- 310/* --------------------------------------------------------------------
@@ -319,6 +319,8 @@ static void __init at91rm9200_map_io(void)
319 319
320static void __init at91rm9200_ioremap_registers(void) 320static void __init at91rm9200_ioremap_registers(void)
321{ 321{
322 at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
323 at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);
322} 324}
323 325
324static void __init at91rm9200_initialize(void) 326static void __init at91rm9200_initialize(void)
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 18bacec2b094..640520c04c46 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -21,6 +21,7 @@
21#include <mach/board.h> 21#include <mach/board.h>
22#include <mach/at91rm9200.h> 22#include <mach/at91rm9200.h>
23#include <mach/at91rm9200_mc.h> 23#include <mach/at91rm9200_mc.h>
24#include <mach/at91_ramc.h>
24 25
25#include "generic.h" 26#include "generic.h"
26 27
@@ -241,15 +242,15 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
241 data->chipselect = 4; /* can only use EBI ChipSelect 4 */ 242 data->chipselect = 4; /* can only use EBI ChipSelect 4 */
242 243
243 /* CF takes over CS4, CS5, CS6 */ 244 /* CF takes over CS4, CS5, CS6 */
244 csa = at91_sys_read(AT91_EBI_CSA); 245 csa = at91_ramc_read(0, AT91_EBI_CSA);
245 at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH); 246 at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
246 247
247 /* 248 /*
248 * Static memory controller timing adjustments. 249 * Static memory controller timing adjustments.
249 * REVISIT: these timings are in terms of MCK cycles, so 250 * REVISIT: these timings are in terms of MCK cycles, so
250 * when MCK changes (cpufreq etc) so must these values... 251 * when MCK changes (cpufreq etc) so must these values...
251 */ 252 */
252 at91_sys_write(AT91_SMC_CSR(4), 253 at91_ramc_write(0, AT91_SMC_CSR(4),
253 AT91_SMC_ACSS_STD 254 AT91_SMC_ACSS_STD
254 | AT91_SMC_DBW_16 255 | AT91_SMC_DBW_16
255 | AT91_SMC_BAT 256 | AT91_SMC_BAT
@@ -407,11 +408,11 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
407 return; 408 return;
408 409
409 /* enable the address range of CS3 */ 410 /* enable the address range of CS3 */
410 csa = at91_sys_read(AT91_EBI_CSA); 411 csa = at91_ramc_read(0, AT91_EBI_CSA);
411 at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA); 412 at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
412 413
413 /* set the bus interface characteristics */ 414 /* set the bus interface characteristics */
414 at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN 415 at91_ramc_write(0, AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
415 | AT91_SMC_NWS_(5) 416 | AT91_SMC_NWS_(5)
416 | AT91_SMC_TDF_(1) 417 | AT91_SMC_TDF_(1)
417 | AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */ 418 | AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */
@@ -1114,7 +1115,6 @@ static inline void configure_usart3_pins(unsigned pins)
1114} 1115}
1115 1116
1116static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ 1117static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1117struct platform_device *atmel_default_console_device; /* the serial console device */
1118 1118
1119void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) 1119void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1120{ 1120{
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index a028cdf8f974..dd7f782b0b91 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -43,9 +43,9 @@ static inline unsigned long read_CRTR(void)
43{ 43{
44 unsigned long x1, x2; 44 unsigned long x1, x2;
45 45
46 x1 = at91_sys_read(AT91_ST_CRTR); 46 x1 = at91_st_read(AT91_ST_CRTR);
47 do { 47 do {
48 x2 = at91_sys_read(AT91_ST_CRTR); 48 x2 = at91_st_read(AT91_ST_CRTR);
49 if (x1 == x2) 49 if (x1 == x2)
50 break; 50 break;
51 x1 = x2; 51 x1 = x2;
@@ -58,7 +58,7 @@ static inline unsigned long read_CRTR(void)
58 */ 58 */
59static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id) 59static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
60{ 60{
61 u32 sr = at91_sys_read(AT91_ST_SR) & irqmask; 61 u32 sr = at91_st_read(AT91_ST_SR) & irqmask;
62 62
63 /* 63 /*
64 * irqs should be disabled here, but as the irq is shared they are only 64 * irqs should be disabled here, but as the irq is shared they are only
@@ -110,22 +110,22 @@ static void
110clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev) 110clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
111{ 111{
112 /* Disable and flush pending timer interrupts */ 112 /* Disable and flush pending timer interrupts */
113 at91_sys_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS); 113 at91_st_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
114 (void) at91_sys_read(AT91_ST_SR); 114 at91_st_read(AT91_ST_SR);
115 115
116 last_crtr = read_CRTR(); 116 last_crtr = read_CRTR();
117 switch (mode) { 117 switch (mode) {
118 case CLOCK_EVT_MODE_PERIODIC: 118 case CLOCK_EVT_MODE_PERIODIC:
119 /* PIT for periodic irqs; fixed rate of 1/HZ */ 119 /* PIT for periodic irqs; fixed rate of 1/HZ */
120 irqmask = AT91_ST_PITS; 120 irqmask = AT91_ST_PITS;
121 at91_sys_write(AT91_ST_PIMR, RM9200_TIMER_LATCH); 121 at91_st_write(AT91_ST_PIMR, RM9200_TIMER_LATCH);
122 break; 122 break;
123 case CLOCK_EVT_MODE_ONESHOT: 123 case CLOCK_EVT_MODE_ONESHOT:
124 /* ALM for oneshot irqs, set by next_event() 124 /* ALM for oneshot irqs, set by next_event()
125 * before 32 seconds have passed 125 * before 32 seconds have passed
126 */ 126 */
127 irqmask = AT91_ST_ALMS; 127 irqmask = AT91_ST_ALMS;
128 at91_sys_write(AT91_ST_RTAR, last_crtr); 128 at91_st_write(AT91_ST_RTAR, last_crtr);
129 break; 129 break;
130 case CLOCK_EVT_MODE_SHUTDOWN: 130 case CLOCK_EVT_MODE_SHUTDOWN:
131 case CLOCK_EVT_MODE_UNUSED: 131 case CLOCK_EVT_MODE_UNUSED:
@@ -133,7 +133,7 @@ clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
133 irqmask = 0; 133 irqmask = 0;
134 break; 134 break;
135 } 135 }
136 at91_sys_write(AT91_ST_IER, irqmask); 136 at91_st_write(AT91_ST_IER, irqmask);
137} 137}
138 138
139static int 139static int
@@ -156,12 +156,12 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
156 alm = read_CRTR(); 156 alm = read_CRTR();
157 157
158 /* Cancel any pending alarm; flush any pending IRQ */ 158 /* Cancel any pending alarm; flush any pending IRQ */
159 at91_sys_write(AT91_ST_RTAR, alm); 159 at91_st_write(AT91_ST_RTAR, alm);
160 (void) at91_sys_read(AT91_ST_SR); 160 at91_st_read(AT91_ST_SR);
161 161
162 /* Schedule alarm by writing RTAR. */ 162 /* Schedule alarm by writing RTAR. */
163 alm += delta; 163 alm += delta;
164 at91_sys_write(AT91_ST_RTAR, alm); 164 at91_st_write(AT91_ST_RTAR, alm);
165 165
166 return status; 166 return status;
167} 167}
@@ -175,15 +175,24 @@ static struct clock_event_device clkevt = {
175 .set_mode = clkevt32k_mode, 175 .set_mode = clkevt32k_mode,
176}; 176};
177 177
178void __iomem *at91_st_base;
179
180void __init at91rm9200_ioremap_st(u32 addr)
181{
182 at91_st_base = ioremap(addr, 256);
183 if (!at91_st_base)
184 panic("Impossible to ioremap ST\n");
185}
186
178/* 187/*
179 * ST (system timer) module supports both clockevents and clocksource. 188 * ST (system timer) module supports both clockevents and clocksource.
180 */ 189 */
181void __init at91rm9200_timer_init(void) 190void __init at91rm9200_timer_init(void)
182{ 191{
183 /* Disable all timer interrupts, and clear any pending ones */ 192 /* Disable all timer interrupts, and clear any pending ones */
184 at91_sys_write(AT91_ST_IDR, 193 at91_st_write(AT91_ST_IDR,
185 AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS); 194 AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
186 (void) at91_sys_read(AT91_ST_SR); 195 at91_st_read(AT91_ST_SR);
187 196
188 /* Make IRQs happen for the system timer */ 197 /* Make IRQs happen for the system timer */
189 setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq); 198 setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq);
@@ -192,7 +201,7 @@ void __init at91rm9200_timer_init(void)
192 * directly for the clocksource and all clockevents, after adjusting 201 * directly for the clocksource and all clockevents, after adjusting
193 * its prescaler from the 1 Hz default. 202 * its prescaler from the 1 Hz default.
194 */ 203 */
195 at91_sys_write(AT91_ST_RTMR, 1); 204 at91_st_write(AT91_ST_RTMR, 1);
196 205
197 /* Setup timer clockevent, with minimum of two ticks (important!!) */ 206 /* Setup timer clockevent, with minimum of two ticks (important!!) */
198 clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift); 207 clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 9ac8c6fe3363..4ade265be805 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -310,34 +310,27 @@ static void __init at91sam9xe_map_io(void)
310 310
311static void __init at91sam9260_map_io(void) 311static void __init at91sam9260_map_io(void)
312{ 312{
313 if (cpu_is_at91sam9xe()) { 313 if (cpu_is_at91sam9xe())
314 at91sam9xe_map_io(); 314 at91sam9xe_map_io();
315 } else if (cpu_is_at91sam9g20()) { 315 else if (cpu_is_at91sam9g20())
316 at91_init_sram(0, AT91SAM9G20_SRAM0_BASE, AT91SAM9G20_SRAM0_SIZE); 316 at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE);
317 at91_init_sram(1, AT91SAM9G20_SRAM1_BASE, AT91SAM9G20_SRAM1_SIZE); 317 else
318 } else { 318 at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
319 at91_init_sram(0, AT91SAM9260_SRAM0_BASE, AT91SAM9260_SRAM0_SIZE);
320 at91_init_sram(1, AT91SAM9260_SRAM1_BASE, AT91SAM9260_SRAM1_SIZE);
321 }
322} 319}
323 320
324static void __init at91sam9260_ioremap_registers(void) 321static void __init at91sam9260_ioremap_registers(void)
325{ 322{
326 at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC); 323 at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
327 at91_ioremap_rstc(AT91SAM9260_BASE_RSTC); 324 at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
325 at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
328 at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT); 326 at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
329 at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC); 327 at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
330} 328 at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
331
332static void at91sam9260_idle(void)
333{
334 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
335 cpu_do_idle();
336} 329}
337 330
338static void __init at91sam9260_initialize(void) 331static void __init at91sam9260_initialize(void)
339{ 332{
340 arm_pm_idle = at91sam9260_idle; 333 arm_pm_idle = at91sam9_idle;
341 arm_pm_restart = at91sam9_alt_restart; 334 arm_pm_restart = at91sam9_alt_restart;
342 at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1) 335 at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
343 | (1 << AT91SAM9260_ID_IRQ2); 336 | (1 << AT91SAM9260_ID_IRQ2);
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 642ccb6d26b2..df487ce83c5e 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -21,6 +21,7 @@
21#include <mach/cpu.h> 21#include <mach/cpu.h>
22#include <mach/at91sam9260.h> 22#include <mach/at91sam9260.h>
23#include <mach/at91sam9260_matrix.h> 23#include <mach/at91sam9260_matrix.h>
24#include <mach/at91_matrix.h>
24#include <mach/at91sam9_smc.h> 25#include <mach/at91sam9_smc.h>
25 26
26#include "generic.h" 27#include "generic.h"
@@ -422,8 +423,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
422 if (!data) 423 if (!data)
423 return; 424 return;
424 425
425 csa = at91_sys_read(AT91_MATRIX_EBICSA); 426 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
426 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); 427 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
427 428
428 /* enable pin */ 429 /* enable pin */
429 if (gpio_is_valid(data->enable_pin)) 430 if (gpio_is_valid(data->enable_pin))
@@ -717,18 +718,42 @@ static struct resource rtt_resources[] = {
717 .start = AT91SAM9260_BASE_RTT, 718 .start = AT91SAM9260_BASE_RTT,
718 .end = AT91SAM9260_BASE_RTT + SZ_16 - 1, 719 .end = AT91SAM9260_BASE_RTT + SZ_16 - 1,
719 .flags = IORESOURCE_MEM, 720 .flags = IORESOURCE_MEM,
720 } 721 }, {
722 .flags = IORESOURCE_MEM,
723 },
721}; 724};
722 725
723static struct platform_device at91sam9260_rtt_device = { 726static struct platform_device at91sam9260_rtt_device = {
724 .name = "at91_rtt", 727 .name = "at91_rtt",
725 .id = 0, 728 .id = 0,
726 .resource = rtt_resources, 729 .resource = rtt_resources,
727 .num_resources = ARRAY_SIZE(rtt_resources),
728}; 730};
729 731
732
733#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
734static void __init at91_add_device_rtt_rtc(void)
735{
736 at91sam9260_rtt_device.name = "rtc-at91sam9";
737 /*
738 * The second resource is needed:
739 * GPBR will serve as the storage for RTC time offset
740 */
741 at91sam9260_rtt_device.num_resources = 2;
742 rtt_resources[1].start = AT91SAM9260_BASE_GPBR +
743 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
744 rtt_resources[1].end = rtt_resources[1].start + 3;
745}
746#else
747static void __init at91_add_device_rtt_rtc(void)
748{
749 /* Only one resource is needed: RTT not used as RTC */
750 at91sam9260_rtt_device.num_resources = 1;
751}
752#endif
753
730static void __init at91_add_device_rtt(void) 754static void __init at91_add_device_rtt(void)
731{ 755{
756 at91_add_device_rtt_rtc();
732 platform_device_register(&at91sam9260_rtt_device); 757 platform_device_register(&at91sam9260_rtt_device);
733} 758}
734 759
@@ -1139,7 +1164,6 @@ static inline void configure_usart5_pins(void)
1139} 1164}
1140 1165
1141static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ 1166static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1142struct platform_device *atmel_default_console_device; /* the serial console device */
1143 1167
1144void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) 1168void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1145{ 1169{
@@ -1265,7 +1289,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
1265 if (!data) 1289 if (!data)
1266 return; 1290 return;
1267 1291
1268 csa = at91_sys_read(AT91_MATRIX_EBICSA); 1292 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
1269 1293
1270 switch (data->chipselect) { 1294 switch (data->chipselect) {
1271 case 4: 1295 case 4:
@@ -1288,7 +1312,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
1288 return; 1312 return;
1289 } 1313 }
1290 1314
1291 at91_sys_write(AT91_MATRIX_EBICSA, csa); 1315 at91_matrix_write(AT91_MATRIX_EBICSA, csa);
1292 1316
1293 if (gpio_is_valid(data->rst_pin)) { 1317 if (gpio_is_valid(data->rst_pin)) {
1294 at91_set_multi_drive(data->rst_pin, 0); 1318 at91_set_multi_drive(data->rst_pin, 0);
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index ab76868f01f5..684c5dfd92ac 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -283,19 +283,15 @@ static void __init at91sam9261_ioremap_registers(void)
283{ 283{
284 at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC); 284 at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
285 at91_ioremap_rstc(AT91SAM9261_BASE_RSTC); 285 at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
286 at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512);
286 at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT); 287 at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
287 at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC); 288 at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
288} 289 at91_ioremap_matrix(AT91SAM9261_BASE_MATRIX);
289
290static void at91sam9261_idle(void)
291{
292 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
293 cpu_do_idle();
294} 290}
295 291
296static void __init at91sam9261_initialize(void) 292static void __init at91sam9261_initialize(void)
297{ 293{
298 arm_pm_idle = at91sam9261_idle; 294 arm_pm_idle = at91sam9_idle;
299 arm_pm_restart = at91sam9_alt_restart; 295 arm_pm_restart = at91sam9_alt_restart;
300 at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1) 296 at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
301 | (1 << AT91SAM9261_ID_IRQ2); 297 | (1 << AT91SAM9261_ID_IRQ2);
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index fc59cbdb0e3c..3bd10ce4854e 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -24,6 +24,7 @@
24#include <mach/board.h> 24#include <mach/board.h>
25#include <mach/at91sam9261.h> 25#include <mach/at91sam9261.h>
26#include <mach/at91sam9261_matrix.h> 26#include <mach/at91sam9261_matrix.h>
27#include <mach/at91_matrix.h>
27#include <mach/at91sam9_smc.h> 28#include <mach/at91sam9_smc.h>
28 29
29#include "generic.h" 30#include "generic.h"
@@ -236,8 +237,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
236 if (!data) 237 if (!data)
237 return; 238 return;
238 239
239 csa = at91_sys_read(AT91_MATRIX_EBICSA); 240 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
240 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); 241 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
241 242
242 /* enable pin */ 243 /* enable pin */
243 if (gpio_is_valid(data->enable_pin)) 244 if (gpio_is_valid(data->enable_pin))
@@ -603,6 +604,8 @@ static struct resource rtt_resources[] = {
603 .start = AT91SAM9261_BASE_RTT, 604 .start = AT91SAM9261_BASE_RTT,
604 .end = AT91SAM9261_BASE_RTT + SZ_16 - 1, 605 .end = AT91SAM9261_BASE_RTT + SZ_16 - 1,
605 .flags = IORESOURCE_MEM, 606 .flags = IORESOURCE_MEM,
607 }, {
608 .flags = IORESOURCE_MEM,
606 } 609 }
607}; 610};
608 611
@@ -610,11 +613,32 @@ static struct platform_device at91sam9261_rtt_device = {
610 .name = "at91_rtt", 613 .name = "at91_rtt",
611 .id = 0, 614 .id = 0,
612 .resource = rtt_resources, 615 .resource = rtt_resources,
613 .num_resources = ARRAY_SIZE(rtt_resources),
614}; 616};
615 617
618#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
619static void __init at91_add_device_rtt_rtc(void)
620{
621 at91sam9261_rtt_device.name = "rtc-at91sam9";
622 /*
623 * The second resource is needed:
624 * GPBR will serve as the storage for RTC time offset
625 */
626 at91sam9261_rtt_device.num_resources = 2;
627 rtt_resources[1].start = AT91SAM9261_BASE_GPBR +
628 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
629 rtt_resources[1].end = rtt_resources[1].start + 3;
630}
631#else
632static void __init at91_add_device_rtt_rtc(void)
633{
634 /* Only one resource is needed: RTT not used as RTC */
635 at91sam9261_rtt_device.num_resources = 1;
636}
637#endif
638
616static void __init at91_add_device_rtt(void) 639static void __init at91_add_device_rtt(void)
617{ 640{
641 at91_add_device_rtt_rtc();
618 platform_device_register(&at91sam9261_rtt_device); 642 platform_device_register(&at91sam9261_rtt_device);
619} 643}
620 644
@@ -991,7 +1015,6 @@ static inline void configure_usart2_pins(unsigned pins)
991} 1015}
992 1016
993static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ 1017static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
994struct platform_device *atmel_default_console_device; /* the serial console device */
995 1018
996void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) 1019void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
997{ 1020{
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 247ab633abcc..0b4fa5a7f685 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -303,20 +303,17 @@ static void __init at91sam9263_ioremap_registers(void)
303{ 303{
304 at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC); 304 at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
305 at91_ioremap_rstc(AT91SAM9263_BASE_RSTC); 305 at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
306 at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
307 at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
306 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT); 308 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
307 at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0); 309 at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
308 at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1); 310 at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
309} 311 at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
310
311static void at91sam9263_idle(void)
312{
313 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
314 cpu_do_idle();
315} 312}
316 313
317static void __init at91sam9263_initialize(void) 314static void __init at91sam9263_initialize(void)
318{ 315{
319 arm_pm_idle = at91sam9263_idle; 316 arm_pm_idle = at91sam9_idle;
320 arm_pm_restart = at91sam9_alt_restart; 317 arm_pm_restart = at91sam9_alt_restart;
321 at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1); 318 at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
322 319
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 7b46b2787022..7792de5b83d4 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -23,6 +23,7 @@
23#include <mach/board.h> 23#include <mach/board.h>
24#include <mach/at91sam9263.h> 24#include <mach/at91sam9263.h>
25#include <mach/at91sam9263_matrix.h> 25#include <mach/at91sam9263_matrix.h>
26#include <mach/at91_matrix.h>
26#include <mach/at91sam9_smc.h> 27#include <mach/at91sam9_smc.h>
27 28
28#include "generic.h" 29#include "generic.h"
@@ -409,7 +410,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
409 * we assume SMC timings are configured by board code, 410 * we assume SMC timings are configured by board code,
410 * except True IDE where timings are controlled by driver 411 * except True IDE where timings are controlled by driver
411 */ 412 */
412 ebi0_csa = at91_sys_read(AT91_MATRIX_EBI0CSA); 413 ebi0_csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
413 switch (data->chipselect) { 414 switch (data->chipselect) {
414 case 4: 415 case 4:
415 at91_set_A_periph(AT91_PIN_PD6, 0); /* EBI0_NCS4/CFCS0 */ 416 at91_set_A_periph(AT91_PIN_PD6, 0); /* EBI0_NCS4/CFCS0 */
@@ -428,7 +429,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
428 data->chipselect); 429 data->chipselect);
429 return; 430 return;
430 } 431 }
431 at91_sys_write(AT91_MATRIX_EBI0CSA, ebi0_csa); 432 at91_matrix_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
432 433
433 if (gpio_is_valid(data->det_pin)) { 434 if (gpio_is_valid(data->det_pin)) {
434 at91_set_gpio_input(data->det_pin, 1); 435 at91_set_gpio_input(data->det_pin, 1);
@@ -496,8 +497,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
496 if (!data) 497 if (!data)
497 return; 498 return;
498 499
499 csa = at91_sys_read(AT91_MATRIX_EBI0CSA); 500 csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
500 at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA); 501 at91_matrix_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
501 502
502 /* enable pin */ 503 /* enable pin */
503 if (gpio_is_valid(data->enable_pin)) 504 if (gpio_is_valid(data->enable_pin))
@@ -891,7 +892,8 @@ static struct platform_device at91sam9263_isi_device = {
891 .num_resources = ARRAY_SIZE(isi_resources), 892 .num_resources = ARRAY_SIZE(isi_resources),
892}; 893};
893 894
894void __init at91_add_device_isi(void) 895void __init at91_add_device_isi(struct isi_platform_data *data,
896 bool use_pck_as_mck)
895{ 897{
896 at91_set_A_periph(AT91_PIN_PE0, 0); /* ISI_D0 */ 898 at91_set_A_periph(AT91_PIN_PE0, 0); /* ISI_D0 */
897 at91_set_A_periph(AT91_PIN_PE1, 0); /* ISI_D1 */ 899 at91_set_A_periph(AT91_PIN_PE1, 0); /* ISI_D1 */
@@ -904,14 +906,20 @@ void __init at91_add_device_isi(void)
904 at91_set_A_periph(AT91_PIN_PE8, 0); /* ISI_PCK */ 906 at91_set_A_periph(AT91_PIN_PE8, 0); /* ISI_PCK */
905 at91_set_A_periph(AT91_PIN_PE9, 0); /* ISI_HSYNC */ 907 at91_set_A_periph(AT91_PIN_PE9, 0); /* ISI_HSYNC */
906 at91_set_A_periph(AT91_PIN_PE10, 0); /* ISI_VSYNC */ 908 at91_set_A_periph(AT91_PIN_PE10, 0); /* ISI_VSYNC */
907 at91_set_B_periph(AT91_PIN_PE11, 0); /* ISI_MCK (PCK3) */
908 at91_set_B_periph(AT91_PIN_PE12, 0); /* ISI_PD8 */ 909 at91_set_B_periph(AT91_PIN_PE12, 0); /* ISI_PD8 */
909 at91_set_B_periph(AT91_PIN_PE13, 0); /* ISI_PD9 */ 910 at91_set_B_periph(AT91_PIN_PE13, 0); /* ISI_PD9 */
910 at91_set_B_periph(AT91_PIN_PE14, 0); /* ISI_PD10 */ 911 at91_set_B_periph(AT91_PIN_PE14, 0); /* ISI_PD10 */
911 at91_set_B_periph(AT91_PIN_PE15, 0); /* ISI_PD11 */ 912 at91_set_B_periph(AT91_PIN_PE15, 0); /* ISI_PD11 */
913
914 if (use_pck_as_mck) {
915 at91_set_B_periph(AT91_PIN_PE11, 0); /* ISI_MCK (PCK3) */
916
917 /* TODO: register the PCK for ISI_MCK and set its parent */
918 }
912} 919}
913#else 920#else
914void __init at91_add_device_isi(void) {} 921void __init at91_add_device_isi(struct isi_platform_data *data,
922 bool use_pck_as_mck) {}
915#endif 923#endif
916 924
917 925
@@ -959,6 +967,8 @@ static struct resource rtt0_resources[] = {
959 .start = AT91SAM9263_BASE_RTT0, 967 .start = AT91SAM9263_BASE_RTT0,
960 .end = AT91SAM9263_BASE_RTT0 + SZ_16 - 1, 968 .end = AT91SAM9263_BASE_RTT0 + SZ_16 - 1,
961 .flags = IORESOURCE_MEM, 969 .flags = IORESOURCE_MEM,
970 }, {
971 .flags = IORESOURCE_MEM,
962 } 972 }
963}; 973};
964 974
@@ -966,7 +976,6 @@ static struct platform_device at91sam9263_rtt0_device = {
966 .name = "at91_rtt", 976 .name = "at91_rtt",
967 .id = 0, 977 .id = 0,
968 .resource = rtt0_resources, 978 .resource = rtt0_resources,
969 .num_resources = ARRAY_SIZE(rtt0_resources),
970}; 979};
971 980
972static struct resource rtt1_resources[] = { 981static struct resource rtt1_resources[] = {
@@ -974,6 +983,8 @@ static struct resource rtt1_resources[] = {
974 .start = AT91SAM9263_BASE_RTT1, 983 .start = AT91SAM9263_BASE_RTT1,
975 .end = AT91SAM9263_BASE_RTT1 + SZ_16 - 1, 984 .end = AT91SAM9263_BASE_RTT1 + SZ_16 - 1,
976 .flags = IORESOURCE_MEM, 985 .flags = IORESOURCE_MEM,
986 }, {
987 .flags = IORESOURCE_MEM,
977 } 988 }
978}; 989};
979 990
@@ -981,11 +992,53 @@ static struct platform_device at91sam9263_rtt1_device = {
981 .name = "at91_rtt", 992 .name = "at91_rtt",
982 .id = 1, 993 .id = 1,
983 .resource = rtt1_resources, 994 .resource = rtt1_resources,
984 .num_resources = ARRAY_SIZE(rtt1_resources),
985}; 995};
986 996
997#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
998static void __init at91_add_device_rtt_rtc(void)
999{
1000 struct platform_device *pdev;
1001 struct resource *r;
1002
1003 switch (CONFIG_RTC_DRV_AT91SAM9_RTT) {
1004 case 0:
1005 /*
1006 * The second resource is needed only for the chosen RTT:
1007 * GPBR will serve as the storage for RTC time offset
1008 */
1009 at91sam9263_rtt0_device.num_resources = 2;
1010 at91sam9263_rtt1_device.num_resources = 1;
1011 pdev = &at91sam9263_rtt0_device;
1012 r = rtt0_resources;
1013 break;
1014 case 1:
1015 at91sam9263_rtt0_device.num_resources = 1;
1016 at91sam9263_rtt1_device.num_resources = 2;
1017 pdev = &at91sam9263_rtt1_device;
1018 r = rtt1_resources;
1019 break;
1020 default:
1021 pr_err("at91sam9263: only supports 2 RTT (%d)\n",
1022 CONFIG_RTC_DRV_AT91SAM9_RTT);
1023 return;
1024 }
1025
1026 pdev->name = "rtc-at91sam9";
1027 r[1].start = AT91SAM9263_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
1028 r[1].end = r[1].start + 3;
1029}
1030#else
1031static void __init at91_add_device_rtt_rtc(void)
1032{
1033 /* Only one resource is needed: RTT not used as RTC */
1034 at91sam9263_rtt0_device.num_resources = 1;
1035 at91sam9263_rtt1_device.num_resources = 1;
1036}
1037#endif
1038
987static void __init at91_add_device_rtt(void) 1039static void __init at91_add_device_rtt(void)
988{ 1040{
1041 at91_add_device_rtt_rtc();
989 platform_device_register(&at91sam9263_rtt0_device); 1042 platform_device_register(&at91sam9263_rtt0_device);
990 platform_device_register(&at91sam9263_rtt1_device); 1043 platform_device_register(&at91sam9263_rtt1_device);
991} 1044}
@@ -1371,7 +1424,6 @@ static inline void configure_usart2_pins(unsigned pins)
1371} 1424}
1372 1425
1373static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ 1426static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1374struct platform_device *atmel_default_console_device; /* the serial console device */
1375 1427
1376void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) 1428void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1377{ 1429{
diff --git a/arch/arm/mach-at91/at91sam9_alt_reset.S b/arch/arm/mach-at91/at91sam9_alt_reset.S
index 518e42377171..7af2e108b8a0 100644
--- a/arch/arm/mach-at91/at91sam9_alt_reset.S
+++ b/arch/arm/mach-at91/at91sam9_alt_reset.S
@@ -15,16 +15,17 @@
15 15
16#include <linux/linkage.h> 16#include <linux/linkage.h>
17#include <mach/hardware.h> 17#include <mach/hardware.h>
18#include <mach/at91sam9_sdramc.h> 18#include <mach/at91_ramc.h>
19#include <mach/at91_rstc.h> 19#include <mach/at91_rstc.h>
20 20
21 .arm 21 .arm
22 22
23 .globl at91sam9_alt_restart 23 .globl at91sam9_alt_restart
24 24
25at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants 25at91sam9_alt_restart: ldr r0, =at91_ramc_base @ preload constants
26 ldr r1, =at91_rstc_base 26 ldr r0, [r0]
27 ldr r1, [r1] 27 ldr r4, =at91_rstc_base
28 ldr r1, [r4]
28 29
29 mov r2, #1 30 mov r2, #1
30 mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN 31 mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN
@@ -37,6 +38,3 @@ at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants
37 str r4, [r1, #AT91_RSTC_CR] @ reset processor 38 str r4, [r1, #AT91_RSTC_CR] @ reset processor
38 39
39 b . 40 b .
40
41.at91_va_base_sdramc:
42 .word AT91_VA_BASE_SYS + AT91_SDRAMC0
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 5b12192e52ec..a41622ea61b8 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -317,12 +317,6 @@ static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
317 } 317 }
318}; 318};
319 319
320static void at91sam9g45_idle(void)
321{
322 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
323 cpu_do_idle();
324}
325
326/* -------------------------------------------------------------------- 320/* --------------------------------------------------------------------
327 * AT91SAM9G45 processor initialization 321 * AT91SAM9G45 processor initialization
328 * -------------------------------------------------------------------- */ 322 * -------------------------------------------------------------------- */
@@ -337,13 +331,16 @@ static void __init at91sam9g45_ioremap_registers(void)
337{ 331{
338 at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC); 332 at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
339 at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC); 333 at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
334 at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512);
335 at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512);
340 at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT); 336 at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
341 at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC); 337 at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
338 at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX);
342} 339}
343 340
344static void __init at91sam9g45_initialize(void) 341static void __init at91sam9g45_initialize(void)
345{ 342{
346 arm_pm_idle = at91sam9g45_idle; 343 arm_pm_idle = at91sam9_idle;
347 arm_pm_restart = at91sam9g45_restart; 344 arm_pm_restart = at91sam9g45_restart;
348 at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0); 345 at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
349 346
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index b7582dd10dc3..410829532aab 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -14,6 +14,7 @@
14 14
15#include <linux/dma-mapping.h> 15#include <linux/dma-mapping.h>
16#include <linux/gpio.h> 16#include <linux/gpio.h>
17#include <linux/clk.h>
17#include <linux/platform_device.h> 18#include <linux/platform_device.h>
18#include <linux/i2c-gpio.h> 19#include <linux/i2c-gpio.h>
19#include <linux/atmel-mci.h> 20#include <linux/atmel-mci.h>
@@ -24,11 +25,15 @@
24#include <mach/board.h> 25#include <mach/board.h>
25#include <mach/at91sam9g45.h> 26#include <mach/at91sam9g45.h>
26#include <mach/at91sam9g45_matrix.h> 27#include <mach/at91sam9g45_matrix.h>
28#include <mach/at91_matrix.h>
27#include <mach/at91sam9_smc.h> 29#include <mach/at91sam9_smc.h>
28#include <mach/at_hdmac.h> 30#include <mach/at_hdmac.h>
29#include <mach/atmel-mci.h> 31#include <mach/atmel-mci.h>
30 32
33#include <media/atmel-isi.h>
34
31#include "generic.h" 35#include "generic.h"
36#include "clock.h"
32 37
33 38
34/* -------------------------------------------------------------------- 39/* --------------------------------------------------------------------
@@ -38,10 +43,6 @@
38#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE) 43#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
39static u64 hdmac_dmamask = DMA_BIT_MASK(32); 44static u64 hdmac_dmamask = DMA_BIT_MASK(32);
40 45
41static struct at_dma_platform_data atdma_pdata = {
42 .nr_channels = 8,
43};
44
45static struct resource hdmac_resources[] = { 46static struct resource hdmac_resources[] = {
46 [0] = { 47 [0] = {
47 .start = AT91SAM9G45_BASE_DMA, 48 .start = AT91SAM9G45_BASE_DMA,
@@ -56,12 +57,11 @@ static struct resource hdmac_resources[] = {
56}; 57};
57 58
58static struct platform_device at_hdmac_device = { 59static struct platform_device at_hdmac_device = {
59 .name = "at_hdmac", 60 .name = "at91sam9g45_dma",
60 .id = -1, 61 .id = -1,
61 .dev = { 62 .dev = {
62 .dma_mask = &hdmac_dmamask, 63 .dma_mask = &hdmac_dmamask,
63 .coherent_dma_mask = DMA_BIT_MASK(32), 64 .coherent_dma_mask = DMA_BIT_MASK(32),
64 .platform_data = &atdma_pdata,
65 }, 65 },
66 .resource = hdmac_resources, 66 .resource = hdmac_resources,
67 .num_resources = ARRAY_SIZE(hdmac_resources), 67 .num_resources = ARRAY_SIZE(hdmac_resources),
@@ -69,9 +69,15 @@ static struct platform_device at_hdmac_device = {
69 69
70void __init at91_add_device_hdmac(void) 70void __init at91_add_device_hdmac(void)
71{ 71{
72 dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask); 72#if defined(CONFIG_OF)
73 dma_cap_set(DMA_SLAVE, atdma_pdata.cap_mask); 73 struct device_node *of_node =
74 platform_device_register(&at_hdmac_device); 74 of_find_node_by_name(NULL, "dma-controller");
75
76 if (of_node)
77 of_node_put(of_node);
78 else
79#endif
80 platform_device_register(&at_hdmac_device);
75} 81}
76#else 82#else
77void __init at91_add_device_hdmac(void) {} 83void __init at91_add_device_hdmac(void) {}
@@ -552,8 +558,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
552 if (!data) 558 if (!data)
553 return; 559 return;
554 560
555 csa = at91_sys_read(AT91_MATRIX_EBICSA); 561 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
556 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); 562 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
557 563
558 /* enable pin */ 564 /* enable pin */
559 if (gpio_is_valid(data->enable_pin)) 565 if (gpio_is_valid(data->enable_pin))
@@ -869,6 +875,96 @@ void __init at91_add_device_ac97(struct ac97c_platform_data *data)
869void __init at91_add_device_ac97(struct ac97c_platform_data *data) {} 875void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
870#endif 876#endif
871 877
878/* --------------------------------------------------------------------
879 * Image Sensor Interface
880 * -------------------------------------------------------------------- */
881#if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE)
882static u64 isi_dmamask = DMA_BIT_MASK(32);
883static struct isi_platform_data isi_data;
884
885struct resource isi_resources[] = {
886 [0] = {
887 .start = AT91SAM9G45_BASE_ISI,
888 .end = AT91SAM9G45_BASE_ISI + SZ_16K - 1,
889 .flags = IORESOURCE_MEM,
890 },
891 [1] = {
892 .start = AT91SAM9G45_ID_ISI,
893 .end = AT91SAM9G45_ID_ISI,
894 .flags = IORESOURCE_IRQ,
895 },
896};
897
898static struct platform_device at91sam9g45_isi_device = {
899 .name = "atmel_isi",
900 .id = 0,
901 .dev = {
902 .dma_mask = &isi_dmamask,
903 .coherent_dma_mask = DMA_BIT_MASK(32),
904 .platform_data = &isi_data,
905 },
906 .resource = isi_resources,
907 .num_resources = ARRAY_SIZE(isi_resources),
908};
909
910static struct clk_lookup isi_mck_lookups[] = {
911 CLKDEV_CON_DEV_ID("isi_mck", "atmel_isi.0", NULL),
912};
913
914void __init at91_add_device_isi(struct isi_platform_data *data,
915 bool use_pck_as_mck)
916{
917 struct clk *pck;
918 struct clk *parent;
919
920 if (!data)
921 return;
922 isi_data = *data;
923
924 at91_set_A_periph(AT91_PIN_PB20, 0); /* ISI_D0 */
925 at91_set_A_periph(AT91_PIN_PB21, 0); /* ISI_D1 */
926 at91_set_A_periph(AT91_PIN_PB22, 0); /* ISI_D2 */
927 at91_set_A_periph(AT91_PIN_PB23, 0); /* ISI_D3 */
928 at91_set_A_periph(AT91_PIN_PB24, 0); /* ISI_D4 */
929 at91_set_A_periph(AT91_PIN_PB25, 0); /* ISI_D5 */
930 at91_set_A_periph(AT91_PIN_PB26, 0); /* ISI_D6 */
931 at91_set_A_periph(AT91_PIN_PB27, 0); /* ISI_D7 */
932 at91_set_A_periph(AT91_PIN_PB28, 0); /* ISI_PCK */
933 at91_set_A_periph(AT91_PIN_PB30, 0); /* ISI_HSYNC */
934 at91_set_A_periph(AT91_PIN_PB29, 0); /* ISI_VSYNC */
935 at91_set_B_periph(AT91_PIN_PB8, 0); /* ISI_PD8 */
936 at91_set_B_periph(AT91_PIN_PB9, 0); /* ISI_PD9 */
937 at91_set_B_periph(AT91_PIN_PB10, 0); /* ISI_PD10 */
938 at91_set_B_periph(AT91_PIN_PB11, 0); /* ISI_PD11 */
939
940 platform_device_register(&at91sam9g45_isi_device);
941
942 if (use_pck_as_mck) {
943 at91_set_B_periph(AT91_PIN_PB31, 0); /* ISI_MCK (PCK1) */
944
945 pck = clk_get(NULL, "pck1");
946 parent = clk_get(NULL, "plla");
947
948 BUG_ON(IS_ERR(pck) || IS_ERR(parent));
949
950 if (clk_set_parent(pck, parent)) {
951 pr_err("Failed to set PCK's parent\n");
952 } else {
953 /* Register PCK as ISI_MCK */
954 isi_mck_lookups[0].clk = pck;
955 clkdev_add_table(isi_mck_lookups,
956 ARRAY_SIZE(isi_mck_lookups));
957 }
958
959 clk_put(pck);
960 clk_put(parent);
961 }
962}
963#else
964void __init at91_add_device_isi(struct isi_platform_data *data,
965 bool use_pck_as_mck) {}
966#endif
967
872 968
873/* -------------------------------------------------------------------- 969/* --------------------------------------------------------------------
874 * LCD Controller 970 * LCD Controller
@@ -1098,6 +1194,8 @@ static struct resource rtt_resources[] = {
1098 .start = AT91SAM9G45_BASE_RTT, 1194 .start = AT91SAM9G45_BASE_RTT,
1099 .end = AT91SAM9G45_BASE_RTT + SZ_16 - 1, 1195 .end = AT91SAM9G45_BASE_RTT + SZ_16 - 1,
1100 .flags = IORESOURCE_MEM, 1196 .flags = IORESOURCE_MEM,
1197 }, {
1198 .flags = IORESOURCE_MEM,
1101 } 1199 }
1102}; 1200};
1103 1201
@@ -1105,11 +1203,32 @@ static struct platform_device at91sam9g45_rtt_device = {
1105 .name = "at91_rtt", 1203 .name = "at91_rtt",
1106 .id = 0, 1204 .id = 0,
1107 .resource = rtt_resources, 1205 .resource = rtt_resources,
1108 .num_resources = ARRAY_SIZE(rtt_resources),
1109}; 1206};
1110 1207
1208#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
1209static void __init at91_add_device_rtt_rtc(void)
1210{
1211 at91sam9g45_rtt_device.name = "rtc-at91sam9";
1212 /*
1213 * The second resource is needed:
1214 * GPBR will serve as the storage for RTC time offset
1215 */
1216 at91sam9g45_rtt_device.num_resources = 2;
1217 rtt_resources[1].start = AT91SAM9G45_BASE_GPBR +
1218 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
1219 rtt_resources[1].end = rtt_resources[1].start + 3;
1220}
1221#else
1222static void __init at91_add_device_rtt_rtc(void)
1223{
1224 /* Only one resource is needed: RTT not used as RTC */
1225 at91sam9g45_rtt_device.num_resources = 1;
1226}
1227#endif
1228
1111static void __init at91_add_device_rtt(void) 1229static void __init at91_add_device_rtt(void)
1112{ 1230{
1231 at91_add_device_rtt_rtc();
1113 platform_device_register(&at91sam9g45_rtt_device); 1232 platform_device_register(&at91sam9g45_rtt_device);
1114} 1233}
1115 1234
@@ -1564,7 +1683,6 @@ static inline void configure_usart3_pins(unsigned pins)
1564} 1683}
1565 1684
1566static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ 1685static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1567struct platform_device *atmel_default_console_device; /* the serial console device */
1568 1686
1569void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) 1687void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1570{ 1688{
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S
index 0468be10980b..9d457182c86c 100644
--- a/arch/arm/mach-at91/at91sam9g45_reset.S
+++ b/arch/arm/mach-at91/at91sam9g45_reset.S
@@ -12,7 +12,7 @@
12 12
13#include <linux/linkage.h> 13#include <linux/linkage.h>
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15#include <mach/at91sam9_ddrsdr.h> 15#include <mach/at91_ramc.h>
16#include <mach/at91_rstc.h> 16#include <mach/at91_rstc.h>
17 17
18 .arm 18 .arm
@@ -20,9 +20,10 @@
20 .globl at91sam9g45_restart 20 .globl at91sam9g45_restart
21 21
22at91sam9g45_restart: 22at91sam9g45_restart:
23 ldr r0, .at91_va_base_sdramc0 @ preload constants 23 ldr r5, =at91_ramc_base @ preload constants
24 ldr r1, =at91_rstc_base 24 ldr r0, [r5]
25 ldr r1, [r1] 25 ldr r4, =at91_rstc_base
26 ldr r1, [r4]
26 27
27 mov r2, #1 28 mov r2, #1
28 mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN 29 mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
@@ -35,6 +36,3 @@ at91sam9g45_restart:
35 str r4, [r1, #AT91_RSTC_CR] @ reset processor 36 str r4, [r1, #AT91_RSTC_CR] @ reset processor
36 37
37 b . 38 b .
38
39.at91_va_base_sdramc0:
40 .word AT91_VA_BASE_SYS + AT91_DDRSDRC0
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index fd60e226a987..63d9372eb18e 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -288,19 +288,15 @@ static void __init at91sam9rl_ioremap_registers(void)
288{ 288{
289 at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC); 289 at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
290 at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC); 290 at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
291 at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
291 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT); 292 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
292 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC); 293 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
293} 294 at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
294
295static void at91sam9rl_idle(void)
296{
297 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
298 cpu_do_idle();
299} 295}
300 296
301static void __init at91sam9rl_initialize(void) 297static void __init at91sam9rl_initialize(void)
302{ 298{
303 arm_pm_idle = at91sam9rl_idle; 299 arm_pm_idle = at91sam9_idle;
304 arm_pm_restart = at91sam9_alt_restart; 300 arm_pm_restart = at91sam9_alt_restart;
305 at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0); 301 at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
306 302
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index 61908dce9784..eda72e83037d 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -20,6 +20,7 @@
20#include <mach/board.h> 20#include <mach/board.h>
21#include <mach/at91sam9rl.h> 21#include <mach/at91sam9rl.h>
22#include <mach/at91sam9rl_matrix.h> 22#include <mach/at91sam9rl_matrix.h>
23#include <mach/at91_matrix.h>
23#include <mach/at91sam9_smc.h> 24#include <mach/at91sam9_smc.h>
24#include <mach/at_hdmac.h> 25#include <mach/at_hdmac.h>
25 26
@@ -33,10 +34,6 @@
33#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE) 34#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
34static u64 hdmac_dmamask = DMA_BIT_MASK(32); 35static u64 hdmac_dmamask = DMA_BIT_MASK(32);
35 36
36static struct at_dma_platform_data atdma_pdata = {
37 .nr_channels = 2,
38};
39
40static struct resource hdmac_resources[] = { 37static struct resource hdmac_resources[] = {
41 [0] = { 38 [0] = {
42 .start = AT91SAM9RL_BASE_DMA, 39 .start = AT91SAM9RL_BASE_DMA,
@@ -51,12 +48,11 @@ static struct resource hdmac_resources[] = {
51}; 48};
52 49
53static struct platform_device at_hdmac_device = { 50static struct platform_device at_hdmac_device = {
54 .name = "at_hdmac", 51 .name = "at91sam9rl_dma",
55 .id = -1, 52 .id = -1,
56 .dev = { 53 .dev = {
57 .dma_mask = &hdmac_dmamask, 54 .dma_mask = &hdmac_dmamask,
58 .coherent_dma_mask = DMA_BIT_MASK(32), 55 .coherent_dma_mask = DMA_BIT_MASK(32),
59 .platform_data = &atdma_pdata,
60 }, 56 },
61 .resource = hdmac_resources, 57 .resource = hdmac_resources,
62 .num_resources = ARRAY_SIZE(hdmac_resources), 58 .num_resources = ARRAY_SIZE(hdmac_resources),
@@ -64,7 +60,6 @@ static struct platform_device at_hdmac_device = {
64 60
65void __init at91_add_device_hdmac(void) 61void __init at91_add_device_hdmac(void)
66{ 62{
67 dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
68 platform_device_register(&at_hdmac_device); 63 platform_device_register(&at_hdmac_device);
69} 64}
70#else 65#else
@@ -271,8 +266,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
271 if (!data) 266 if (!data)
272 return; 267 return;
273 268
274 csa = at91_sys_read(AT91_MATRIX_EBICSA); 269 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
275 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); 270 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
276 271
277 /* enable pin */ 272 /* enable pin */
278 if (gpio_is_valid(data->enable_pin)) 273 if (gpio_is_valid(data->enable_pin))
@@ -688,6 +683,8 @@ static struct resource rtt_resources[] = {
688 .start = AT91SAM9RL_BASE_RTT, 683 .start = AT91SAM9RL_BASE_RTT,
689 .end = AT91SAM9RL_BASE_RTT + SZ_16 - 1, 684 .end = AT91SAM9RL_BASE_RTT + SZ_16 - 1,
690 .flags = IORESOURCE_MEM, 685 .flags = IORESOURCE_MEM,
686 }, {
687 .flags = IORESOURCE_MEM,
691 } 688 }
692}; 689};
693 690
@@ -695,11 +692,32 @@ static struct platform_device at91sam9rl_rtt_device = {
695 .name = "at91_rtt", 692 .name = "at91_rtt",
696 .id = 0, 693 .id = 0,
697 .resource = rtt_resources, 694 .resource = rtt_resources,
698 .num_resources = ARRAY_SIZE(rtt_resources),
699}; 695};
700 696
697#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
698static void __init at91_add_device_rtt_rtc(void)
699{
700 at91sam9rl_rtt_device.name = "rtc-at91sam9";
701 /*
702 * The second resource is needed:
703 * GPBR will serve as the storage for RTC time offset
704 */
705 at91sam9rl_rtt_device.num_resources = 2;
706 rtt_resources[1].start = AT91SAM9RL_BASE_GPBR +
707 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
708 rtt_resources[1].end = rtt_resources[1].start + 3;
709}
710#else
711static void __init at91_add_device_rtt_rtc(void)
712{
713 /* Only one resource is needed: RTT not used as RTC */
714 at91sam9rl_rtt_device.num_resources = 1;
715}
716#endif
717
701static void __init at91_add_device_rtt(void) 718static void __init at91_add_device_rtt(void)
702{ 719{
720 at91_add_device_rtt_rtc();
703 platform_device_register(&at91sam9rl_rtt_device); 721 platform_device_register(&at91sam9rl_rtt_device);
704} 722}
705 723
@@ -1134,7 +1152,6 @@ static inline void configure_usart3_pins(unsigned pins)
1134} 1152}
1135 1153
1136static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ 1154static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1137struct platform_device *atmel_default_console_device; /* the serial console device */
1138 1155
1139void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) 1156void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1140{ 1157{
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
new file mode 100644
index 000000000000..d17d4262665b
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -0,0 +1,370 @@
1/*
2 * Chip-specific setup code for the AT91SAM9x5 family
3 *
4 * Copyright (C) 2010-2012 Atmel Corporation.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/module.h>
10#include <linux/dma-mapping.h>
11
12#include <asm/irq.h>
13#include <asm/mach/arch.h>
14#include <asm/mach/map.h>
15#include <mach/at91sam9x5.h>
16#include <mach/at91_pmc.h>
17#include <mach/cpu.h>
18#include <mach/board.h>
19
20#include "soc.h"
21#include "generic.h"
22#include "clock.h"
23#include "sam9_smc.h"
24
25/* --------------------------------------------------------------------
26 * Clocks
27 * -------------------------------------------------------------------- */
28
29/*
30 * The peripheral clocks.
31 */
32static struct clk pioAB_clk = {
33 .name = "pioAB_clk",
34 .pmc_mask = 1 << AT91SAM9X5_ID_PIOAB,
35 .type = CLK_TYPE_PERIPHERAL,
36};
37static struct clk pioCD_clk = {
38 .name = "pioCD_clk",
39 .pmc_mask = 1 << AT91SAM9X5_ID_PIOCD,
40 .type = CLK_TYPE_PERIPHERAL,
41};
42static struct clk smd_clk = {
43 .name = "smd_clk",
44 .pmc_mask = 1 << AT91SAM9X5_ID_SMD,
45 .type = CLK_TYPE_PERIPHERAL,
46};
47static struct clk usart0_clk = {
48 .name = "usart0_clk",
49 .pmc_mask = 1 << AT91SAM9X5_ID_USART0,
50 .type = CLK_TYPE_PERIPHERAL,
51};
52static struct clk usart1_clk = {
53 .name = "usart1_clk",
54 .pmc_mask = 1 << AT91SAM9X5_ID_USART1,
55 .type = CLK_TYPE_PERIPHERAL,
56};
57static struct clk usart2_clk = {
58 .name = "usart2_clk",
59 .pmc_mask = 1 << AT91SAM9X5_ID_USART2,
60 .type = CLK_TYPE_PERIPHERAL,
61};
62/* USART3 clock - Only for sam9g25/sam9x25 */
63static struct clk usart3_clk = {
64 .name = "usart3_clk",
65 .pmc_mask = 1 << AT91SAM9X5_ID_USART3,
66 .type = CLK_TYPE_PERIPHERAL,
67};
68static struct clk twi0_clk = {
69 .name = "twi0_clk",
70 .pmc_mask = 1 << AT91SAM9X5_ID_TWI0,
71 .type = CLK_TYPE_PERIPHERAL,
72};
73static struct clk twi1_clk = {
74 .name = "twi1_clk",
75 .pmc_mask = 1 << AT91SAM9X5_ID_TWI1,
76 .type = CLK_TYPE_PERIPHERAL,
77};
78static struct clk twi2_clk = {
79 .name = "twi2_clk",
80 .pmc_mask = 1 << AT91SAM9X5_ID_TWI2,
81 .type = CLK_TYPE_PERIPHERAL,
82};
83static struct clk mmc0_clk = {
84 .name = "mci0_clk",
85 .pmc_mask = 1 << AT91SAM9X5_ID_MCI0,
86 .type = CLK_TYPE_PERIPHERAL,
87};
88static struct clk spi0_clk = {
89 .name = "spi0_clk",
90 .pmc_mask = 1 << AT91SAM9X5_ID_SPI0,
91 .type = CLK_TYPE_PERIPHERAL,
92};
93static struct clk spi1_clk = {
94 .name = "spi1_clk",
95 .pmc_mask = 1 << AT91SAM9X5_ID_SPI1,
96 .type = CLK_TYPE_PERIPHERAL,
97};
98static struct clk uart0_clk = {
99 .name = "uart0_clk",
100 .pmc_mask = 1 << AT91SAM9X5_ID_UART0,
101 .type = CLK_TYPE_PERIPHERAL,
102};
103static struct clk uart1_clk = {
104 .name = "uart1_clk",
105 .pmc_mask = 1 << AT91SAM9X5_ID_UART1,
106 .type = CLK_TYPE_PERIPHERAL,
107};
108static struct clk tcb0_clk = {
109 .name = "tcb0_clk",
110 .pmc_mask = 1 << AT91SAM9X5_ID_TCB,
111 .type = CLK_TYPE_PERIPHERAL,
112};
113static struct clk pwm_clk = {
114 .name = "pwm_clk",
115 .pmc_mask = 1 << AT91SAM9X5_ID_PWM,
116 .type = CLK_TYPE_PERIPHERAL,
117};
118static struct clk adc_clk = {
119 .name = "adc_clk",
120 .pmc_mask = 1 << AT91SAM9X5_ID_ADC,
121 .type = CLK_TYPE_PERIPHERAL,
122};
123static struct clk dma0_clk = {
124 .name = "dma0_clk",
125 .pmc_mask = 1 << AT91SAM9X5_ID_DMA0,
126 .type = CLK_TYPE_PERIPHERAL,
127};
128static struct clk dma1_clk = {
129 .name = "dma1_clk",
130 .pmc_mask = 1 << AT91SAM9X5_ID_DMA1,
131 .type = CLK_TYPE_PERIPHERAL,
132};
133static struct clk uhphs_clk = {
134 .name = "uhphs_clk",
135 .pmc_mask = 1 << AT91SAM9X5_ID_UHPHS,
136 .type = CLK_TYPE_PERIPHERAL,
137};
138static struct clk udphs_clk = {
139 .name = "udphs_clk",
140 .pmc_mask = 1 << AT91SAM9X5_ID_UDPHS,
141 .type = CLK_TYPE_PERIPHERAL,
142};
143/* emac0 clock - Only for sam9g25/sam9x25/sam9g35/sam9x35 */
144static struct clk macb0_clk = {
145 .name = "pclk",
146 .pmc_mask = 1 << AT91SAM9X5_ID_EMAC0,
147 .type = CLK_TYPE_PERIPHERAL,
148};
149/* lcd clock - Only for sam9g15/sam9g35/sam9x35 */
150static struct clk lcdc_clk = {
151 .name = "lcdc_clk",
152 .pmc_mask = 1 << AT91SAM9X5_ID_LCDC,
153 .type = CLK_TYPE_PERIPHERAL,
154};
155/* isi clock - Only for sam9g25 */
156static struct clk isi_clk = {
157 .name = "isi_clk",
158 .pmc_mask = 1 << AT91SAM9X5_ID_ISI,
159 .type = CLK_TYPE_PERIPHERAL,
160};
161static struct clk mmc1_clk = {
162 .name = "mci1_clk",
163 .pmc_mask = 1 << AT91SAM9X5_ID_MCI1,
164 .type = CLK_TYPE_PERIPHERAL,
165};
166/* emac1 clock - Only for sam9x25 */
167static struct clk macb1_clk = {
168 .name = "pclk",
169 .pmc_mask = 1 << AT91SAM9X5_ID_EMAC1,
170 .type = CLK_TYPE_PERIPHERAL,
171};
172static struct clk ssc_clk = {
173 .name = "ssc_clk",
174 .pmc_mask = 1 << AT91SAM9X5_ID_SSC,
175 .type = CLK_TYPE_PERIPHERAL,
176};
177/* can0 clock - Only for sam9x35 */
178static struct clk can0_clk = {
179 .name = "can0_clk",
180 .pmc_mask = 1 << AT91SAM9X5_ID_CAN0,
181 .type = CLK_TYPE_PERIPHERAL,
182};
183/* can1 clock - Only for sam9x35 */
184static struct clk can1_clk = {
185 .name = "can1_clk",
186 .pmc_mask = 1 << AT91SAM9X5_ID_CAN1,
187 .type = CLK_TYPE_PERIPHERAL,
188};
189
190static struct clk *periph_clocks[] __initdata = {
191 &pioAB_clk,
192 &pioCD_clk,
193 &smd_clk,
194 &usart0_clk,
195 &usart1_clk,
196 &usart2_clk,
197 &twi0_clk,
198 &twi1_clk,
199 &twi2_clk,
200 &mmc0_clk,
201 &spi0_clk,
202 &spi1_clk,
203 &uart0_clk,
204 &uart1_clk,
205 &tcb0_clk,
206 &pwm_clk,
207 &adc_clk,
208 &dma0_clk,
209 &dma1_clk,
210 &uhphs_clk,
211 &udphs_clk,
212 &mmc1_clk,
213 &ssc_clk,
214 // irq0
215};
216
217static struct clk_lookup periph_clocks_lookups[] = {
218 /* lookup table for DT entries */
219 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
220 CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
221 CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
222 CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
223 CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
224 CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
225 CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
226 CLKDEV_CON_ID("pioA", &pioAB_clk),
227 CLKDEV_CON_ID("pioB", &pioAB_clk),
228 CLKDEV_CON_ID("pioC", &pioCD_clk),
229 CLKDEV_CON_ID("pioD", &pioCD_clk),
230 /* additional fake clock for macb_hclk */
231 CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
232 CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
233};
234
235/*
236 * The two programmable clocks.
237 * You must configure pin multiplexing to bring these signals out.
238 */
239static struct clk pck0 = {
240 .name = "pck0",
241 .pmc_mask = AT91_PMC_PCK0,
242 .type = CLK_TYPE_PROGRAMMABLE,
243 .id = 0,
244};
245static struct clk pck1 = {
246 .name = "pck1",
247 .pmc_mask = AT91_PMC_PCK1,
248 .type = CLK_TYPE_PROGRAMMABLE,
249 .id = 1,
250};
251
252static void __init at91sam9x5_register_clocks(void)
253{
254 int i;
255
256 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
257 clk_register(periph_clocks[i]);
258
259 clkdev_add_table(periph_clocks_lookups,
260 ARRAY_SIZE(periph_clocks_lookups));
261
262 if (cpu_is_at91sam9g25()
263 || cpu_is_at91sam9x25())
264 clk_register(&usart3_clk);
265
266 if (cpu_is_at91sam9g25()
267 || cpu_is_at91sam9x25()
268 || cpu_is_at91sam9g35()
269 || cpu_is_at91sam9x35())
270 clk_register(&macb0_clk);
271
272 if (cpu_is_at91sam9g15()
273 || cpu_is_at91sam9g35()
274 || cpu_is_at91sam9x35())
275 clk_register(&lcdc_clk);
276
277 if (cpu_is_at91sam9g25())
278 clk_register(&isi_clk);
279
280 if (cpu_is_at91sam9x25())
281 clk_register(&macb1_clk);
282
283 if (cpu_is_at91sam9x25()
284 || cpu_is_at91sam9x35()) {
285 clk_register(&can0_clk);
286 clk_register(&can1_clk);
287 }
288
289 clk_register(&pck0);
290 clk_register(&pck1);
291}
292
293/* --------------------------------------------------------------------
294 * AT91SAM9x5 processor initialization
295 * -------------------------------------------------------------------- */
296
297static void __init at91sam9x5_map_io(void)
298{
299 at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
300}
301
302static void __init at91sam9x5_ioremap_registers(void)
303{
304 if (of_at91sam926x_pit_init() < 0)
305 panic("Impossible to find PIT\n");
306 at91_ioremap_ramc(0, AT91SAM9X5_BASE_DDRSDRC0, 512);
307}
308
309void __init at91sam9x5_initialize(void)
310{
311 arm_pm_restart = at91sam9g45_restart;
312 at91_extern_irq = (1 << AT91SAM9X5_ID_IRQ0);
313
314 /* Register GPIO subsystem (using DT) */
315 at91_gpio_init(NULL, 0);
316}
317
318/* --------------------------------------------------------------------
319 * AT91SAM9x5 devices (temporary before modification of code)
320 * -------------------------------------------------------------------- */
321void __init at91_add_device_nand(struct atmel_nand_data *data) {}
322
323/* --------------------------------------------------------------------
324 * Interrupt initialization
325 * -------------------------------------------------------------------- */
326/*
327 * The default interrupt priority levels (0 = lowest, 7 = highest).
328 */
329static unsigned int at91sam9x5_default_irq_priority[NR_AIC_IRQS] __initdata = {
330 7, /* Advanced Interrupt Controller (FIQ) */
331 7, /* System Peripherals */
332 1, /* Parallel IO Controller A and B */
333 1, /* Parallel IO Controller C and D */
334 4, /* Soft Modem */
335 5, /* USART 0 */
336 5, /* USART 1 */
337 5, /* USART 2 */
338 5, /* USART 3 */
339 6, /* Two-Wire Interface 0 */
340 6, /* Two-Wire Interface 1 */
341 6, /* Two-Wire Interface 2 */
342 0, /* Multimedia Card Interface 0 */
343 5, /* Serial Peripheral Interface 0 */
344 5, /* Serial Peripheral Interface 1 */
345 5, /* UART 0 */
346 5, /* UART 1 */
347 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
348 0, /* Pulse Width Modulation Controller */
349 0, /* ADC Controller */
350 0, /* DMA Controller 0 */
351 0, /* DMA Controller 1 */
352 2, /* USB Host High Speed port */
353 2, /* USB Device High speed port */
354 3, /* Ethernet MAC 0 */
355 3, /* LDC Controller or Image Sensor Interface */
356 0, /* Multimedia Card Interface 1 */
357 3, /* Ethernet MAC 1 */
358 4, /* Synchronous Serial Interface */
359 4, /* CAN Controller 0 */
360 4, /* CAN Controller 1 */
361 0, /* Advanced Interrupt Controller (IRQ0) */
362};
363
364struct at91_init_soc __initdata at91sam9x5_soc = {
365 .map_io = at91sam9x5_map_io,
366 .default_irq_priority = at91sam9x5_default_irq_priority,
367 .ioremap_registers = at91sam9x5_ioremap_registers,
368 .register_clocks = at91sam9x5_register_clocks,
369 .init = at91sam9x5_initialize,
370};
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
index 0154b7f44ff1..5400a1d65035 100644
--- a/arch/arm/mach-at91/at91x40.c
+++ b/arch/arm/mach-at91/at91x40.c
@@ -44,7 +44,7 @@ static void at91x40_idle(void)
44 * Disable the processor clock. The processor will be automatically 44 * Disable the processor clock. The processor will be automatically
45 * re-enabled by an interrupt or by a reset. 45 * re-enabled by an interrupt or by a reset.
46 */ 46 */
47 at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU); 47 __raw_writel(AT91_PS_CR_CPU, AT91_PS_CR);
48 cpu_do_idle(); 48 cpu_do_idle();
49} 49}
50 50
diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c
index dfff2895f4b2..6ca680a1d5d1 100644
--- a/arch/arm/mach-at91/at91x40_time.c
+++ b/arch/arm/mach-at91/at91x40_time.c
@@ -28,6 +28,12 @@
28#include <asm/mach/time.h> 28#include <asm/mach/time.h>
29#include <mach/at91_tc.h> 29#include <mach/at91_tc.h>
30 30
31#define at91_tc_read(field) \
32 __raw_readl(AT91_TC + field)
33
34#define at91_tc_write(field, value) \
35 __raw_writel(value, AT91_TC + field);
36
31/* 37/*
32 * 3 counter/timer units present. 38 * 3 counter/timer units present.
33 */ 39 */
@@ -37,12 +43,12 @@
37 43
38static unsigned long at91x40_gettimeoffset(void) 44static unsigned long at91x40_gettimeoffset(void)
39{ 45{
40 return (at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128)); 46 return (at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128));
41} 47}
42 48
43static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id) 49static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id)
44{ 50{
45 at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_SR); 51 at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_SR);
46 timer_tick(); 52 timer_tick();
47 return IRQ_HANDLED; 53 return IRQ_HANDLED;
48} 54}
@@ -57,20 +63,20 @@ void __init at91x40_timer_init(void)
57{ 63{
58 unsigned int v; 64 unsigned int v;
59 65
60 at91_sys_write(AT91_TC + AT91_TC_BCR, 0); 66 at91_tc_write(AT91_TC_BCR, 0);
61 v = at91_sys_read(AT91_TC + AT91_TC_BMR); 67 v = at91_tc_read(AT91_TC_BMR);
62 v = (v & ~AT91_TC_TC1XC1S) | AT91_TC_TC1XC1S_NONE; 68 v = (v & ~AT91_TC_TC1XC1S) | AT91_TC_TC1XC1S_NONE;
63 at91_sys_write(AT91_TC + AT91_TC_BMR, v); 69 at91_tc_write(AT91_TC_BMR, v);
64 70
65 at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS); 71 at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS);
66 at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG)); 72 at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
67 at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff); 73 at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
68 at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1); 74 at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1);
69 at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4)); 75 at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
70 76
71 setup_irq(AT91X40_ID_TC1, &at91x40_timer_irq); 77 setup_irq(AT91X40_ID_TC1, &at91x40_timer_irq);
72 78
73 at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN)); 79 at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
74} 80}
75 81
76struct sys_timer at91x40_timer = { 82struct sys_timer at91x40_timer = {
diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c
deleted file mode 100644
index ac3de4f7c31d..000000000000
--- a/arch/arm/mach-at91/board-cap9adk.c
+++ /dev/null
@@ -1,396 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-cap9adk.c
3 *
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2005 SAN People
7 * Copyright (C) 2007 Atmel Corporation.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/types.h>
25#include <linux/gpio.h>
26#include <linux/init.h>
27#include <linux/mm.h>
28#include <linux/module.h>
29#include <linux/platform_device.h>
30#include <linux/spi/spi.h>
31#include <linux/spi/ads7846.h>
32#include <linux/fb.h>
33#include <linux/mtd/physmap.h>
34
35#include <video/atmel_lcdc.h>
36
37#include <mach/hardware.h>
38#include <asm/setup.h>
39#include <asm/mach-types.h>
40
41#include <asm/mach/arch.h>
42#include <asm/mach/map.h>
43
44#include <mach/board.h>
45#include <mach/at91cap9_matrix.h>
46#include <mach/at91sam9_smc.h>
47#include <mach/system_rev.h>
48
49#include "sam9_smc.h"
50#include "generic.h"
51
52
53static void __init cap9adk_init_early(void)
54{
55 /* Initialize processor: 12 MHz crystal */
56 at91_initialize(12000000);
57
58 /* Setup the LEDs: USER1 and USER2 LED for cpu/timer... */
59 at91_init_leds(AT91_PIN_PA10, AT91_PIN_PA11);
60 /* ... POWER LED always on */
61 at91_set_gpio_output(AT91_PIN_PC29, 1);
62
63 /* Setup the serial ports and console */
64 at91_register_uart(0, 0, 0); /* DBGU = ttyS0 */
65 at91_set_serial_console(0);
66}
67
68/*
69 * USB Host port
70 */
71static struct at91_usbh_data __initdata cap9adk_usbh_data = {
72 .ports = 2,
73 .vbus_pin = {-EINVAL, -EINVAL},
74 .overcurrent_pin= {-EINVAL, -EINVAL},
75};
76
77/*
78 * USB HS Device port
79 */
80static struct usba_platform_data __initdata cap9adk_usba_udc_data = {
81 .vbus_pin = AT91_PIN_PB31,
82};
83
84/*
85 * ADS7846 Touchscreen
86 */
87#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
88static int ads7843_pendown_state(void)
89{
90 return !at91_get_gpio_value(AT91_PIN_PC4); /* Touchscreen PENIRQ */
91}
92
93static struct ads7846_platform_data ads_info = {
94 .model = 7843,
95 .x_min = 150,
96 .x_max = 3830,
97 .y_min = 190,
98 .y_max = 3830,
99 .vref_delay_usecs = 100,
100 .x_plate_ohms = 450,
101 .y_plate_ohms = 250,
102 .pressure_max = 15000,
103 .debounce_max = 1,
104 .debounce_rep = 0,
105 .debounce_tol = (~0),
106 .get_pendown_state = ads7843_pendown_state,
107};
108
109static void __init cap9adk_add_device_ts(void)
110{
111 at91_set_gpio_input(AT91_PIN_PC4, 1); /* Touchscreen PENIRQ */
112 at91_set_gpio_input(AT91_PIN_PC5, 1); /* Touchscreen BUSY */
113}
114#else
115static void __init cap9adk_add_device_ts(void) {}
116#endif
117
118
119/*
120 * SPI devices.
121 */
122static struct spi_board_info cap9adk_spi_devices[] = {
123#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
124 { /* DataFlash card */
125 .modalias = "mtd_dataflash",
126 .chip_select = 0,
127 .max_speed_hz = 15 * 1000 * 1000,
128 .bus_num = 0,
129 },
130#endif
131#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
132 {
133 .modalias = "ads7846",
134 .chip_select = 3, /* can be 2 or 3, depending on J2 jumper */
135 .max_speed_hz = 125000 * 26, /* (max sample rate @ 3V) * (cmd + data + overhead) */
136 .bus_num = 0,
137 .platform_data = &ads_info,
138 .irq = AT91_PIN_PC4,
139 },
140#endif
141};
142
143
144/*
145 * MCI (SD/MMC)
146 */
147static struct at91_mmc_data __initdata cap9adk_mmc_data = {
148 .wire4 = 1,
149 .det_pin = -EINVAL,
150 .wp_pin = -EINVAL,
151 .vcc_pin = -EINVAL,
152};
153
154
155/*
156 * MACB Ethernet device
157 */
158static struct macb_platform_data __initdata cap9adk_macb_data = {
159 .phy_irq_pin = -EINVAL,
160 .is_rmii = 1,
161};
162
163
164/*
165 * NAND flash
166 */
167static struct mtd_partition __initdata cap9adk_nand_partitions[] = {
168 {
169 .name = "NAND partition",
170 .offset = 0,
171 .size = MTDPART_SIZ_FULL,
172 },
173};
174
175static struct atmel_nand_data __initdata cap9adk_nand_data = {
176 .ale = 21,
177 .cle = 22,
178 .det_pin = -EINVAL,
179 .rdy_pin = -EINVAL,
180 .enable_pin = AT91_PIN_PD15,
181 .parts = cap9adk_nand_partitions,
182 .num_parts = ARRAY_SIZE(cap9adk_nand_partitions),
183};
184
185static struct sam9_smc_config __initdata cap9adk_nand_smc_config = {
186 .ncs_read_setup = 1,
187 .nrd_setup = 2,
188 .ncs_write_setup = 1,
189 .nwe_setup = 2,
190
191 .ncs_read_pulse = 6,
192 .nrd_pulse = 4,
193 .ncs_write_pulse = 6,
194 .nwe_pulse = 4,
195
196 .read_cycle = 8,
197 .write_cycle = 8,
198
199 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
200 .tdf_cycles = 1,
201};
202
203static void __init cap9adk_add_device_nand(void)
204{
205 unsigned long csa;
206
207 csa = at91_sys_read(AT91_MATRIX_EBICSA);
208 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
209
210 cap9adk_nand_data.bus_width_16 = board_have_nand_16bit();
211 /* setup bus-width (8 or 16) */
212 if (cap9adk_nand_data.bus_width_16)
213 cap9adk_nand_smc_config.mode |= AT91_SMC_DBW_16;
214 else
215 cap9adk_nand_smc_config.mode |= AT91_SMC_DBW_8;
216
217 /* configure chip-select 3 (NAND) */
218 sam9_smc_configure(0, 3, &cap9adk_nand_smc_config);
219
220 at91_add_device_nand(&cap9adk_nand_data);
221}
222
223
224/*
225 * NOR flash
226 */
227static struct mtd_partition cap9adk_nor_partitions[] = {
228 {
229 .name = "NOR partition",
230 .offset = 0,
231 .size = MTDPART_SIZ_FULL,
232 },
233};
234
235static struct physmap_flash_data cap9adk_nor_data = {
236 .width = 2,
237 .parts = cap9adk_nor_partitions,
238 .nr_parts = ARRAY_SIZE(cap9adk_nor_partitions),
239};
240
241#define NOR_BASE AT91_CHIPSELECT_0
242#define NOR_SIZE SZ_8M
243
244static struct resource nor_flash_resources[] = {
245 {
246 .start = NOR_BASE,
247 .end = NOR_BASE + NOR_SIZE - 1,
248 .flags = IORESOURCE_MEM,
249 }
250};
251
252static struct platform_device cap9adk_nor_flash = {
253 .name = "physmap-flash",
254 .id = 0,
255 .dev = {
256 .platform_data = &cap9adk_nor_data,
257 },
258 .resource = nor_flash_resources,
259 .num_resources = ARRAY_SIZE(nor_flash_resources),
260};
261
262static struct sam9_smc_config __initdata cap9adk_nor_smc_config = {
263 .ncs_read_setup = 2,
264 .nrd_setup = 4,
265 .ncs_write_setup = 2,
266 .nwe_setup = 4,
267
268 .ncs_read_pulse = 10,
269 .nrd_pulse = 8,
270 .ncs_write_pulse = 10,
271 .nwe_pulse = 8,
272
273 .read_cycle = 16,
274 .write_cycle = 16,
275
276 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16,
277 .tdf_cycles = 1,
278};
279
280static __init void cap9adk_add_device_nor(void)
281{
282 unsigned long csa;
283
284 csa = at91_sys_read(AT91_MATRIX_EBICSA);
285 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
286
287 /* configure chip-select 0 (NOR) */
288 sam9_smc_configure(0, 0, &cap9adk_nor_smc_config);
289
290 platform_device_register(&cap9adk_nor_flash);
291}
292
293
294/*
295 * LCD Controller
296 */
297#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
298static struct fb_videomode at91_tft_vga_modes[] = {
299 {
300 .name = "TX09D50VM1CCA @ 60",
301 .refresh = 60,
302 .xres = 240, .yres = 320,
303 .pixclock = KHZ2PICOS(4965),
304
305 .left_margin = 1, .right_margin = 33,
306 .upper_margin = 1, .lower_margin = 0,
307 .hsync_len = 5, .vsync_len = 1,
308
309 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
310 .vmode = FB_VMODE_NONINTERLACED,
311 },
312};
313
314static struct fb_monspecs at91fb_default_monspecs = {
315 .manufacturer = "HIT",
316 .monitor = "TX09D70VM1CCA",
317
318 .modedb = at91_tft_vga_modes,
319 .modedb_len = ARRAY_SIZE(at91_tft_vga_modes),
320 .hfmin = 15000,
321 .hfmax = 64000,
322 .vfmin = 50,
323 .vfmax = 150,
324};
325
326#define AT91CAP9_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
327 | ATMEL_LCDC_DISTYPE_TFT \
328 | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
329
330static void at91_lcdc_power_control(int on)
331{
332 if (on)
333 at91_set_gpio_value(AT91_PIN_PC0, 0); /* power up */
334 else
335 at91_set_gpio_value(AT91_PIN_PC0, 1); /* power down */
336}
337
338/* Driver datas */
339static struct atmel_lcdfb_info __initdata cap9adk_lcdc_data = {
340 .default_bpp = 16,
341 .default_dmacon = ATMEL_LCDC_DMAEN,
342 .default_lcdcon2 = AT91CAP9_DEFAULT_LCDCON2,
343 .default_monspecs = &at91fb_default_monspecs,
344 .atmel_lcdfb_power_control = at91_lcdc_power_control,
345 .guard_time = 1,
346};
347
348#else
349static struct atmel_lcdfb_info __initdata cap9adk_lcdc_data;
350#endif
351
352
353/*
354 * AC97
355 */
356static struct ac97c_platform_data cap9adk_ac97_data = {
357 .reset_pin = -EINVAL,
358};
359
360
361static void __init cap9adk_board_init(void)
362{
363 /* Serial */
364 at91_add_device_serial();
365 /* USB Host */
366 at91_add_device_usbh(&cap9adk_usbh_data);
367 /* USB HS */
368 at91_add_device_usba(&cap9adk_usba_udc_data);
369 /* SPI */
370 at91_add_device_spi(cap9adk_spi_devices, ARRAY_SIZE(cap9adk_spi_devices));
371 /* Touchscreen */
372 cap9adk_add_device_ts();
373 /* MMC */
374 at91_add_device_mmc(1, &cap9adk_mmc_data);
375 /* Ethernet */
376 at91_add_device_eth(&cap9adk_macb_data);
377 /* NAND */
378 cap9adk_add_device_nand();
379 /* NOR Flash */
380 cap9adk_add_device_nor();
381 /* I2C */
382 at91_add_device_i2c(NULL, 0);
383 /* LCD Controller */
384 at91_add_device_lcdc(&cap9adk_lcdc_data);
385 /* AC97 */
386 at91_add_device_ac97(&cap9adk_ac97_data);
387}
388
389MACHINE_START(AT91CAP9ADK, "Atmel AT91CAP9A-DK")
390 /* Maintainer: Stelian Pop <stelian.pop@leadtechdesign.com> */
391 .timer = &at91sam926x_timer,
392 .map_io = at91_map_io,
393 .init_early = cap9adk_init_early,
394 .init_irq = at91_init_irq_default,
395 .init_machine = cap9adk_board_init,
396MACHINE_END
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index 9ab3d1ea326d..989e1c5a9ca0 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -43,6 +43,7 @@
43#include <mach/board.h> 43#include <mach/board.h>
44#include <mach/at91sam9_smc.h> 44#include <mach/at91sam9_smc.h>
45#include <mach/at91sam9260_matrix.h> 45#include <mach/at91sam9260_matrix.h>
46#include <mach/at91_matrix.h>
46 47
47#include "sam9_smc.h" 48#include "sam9_smc.h"
48#include "generic.h" 49#include "generic.h"
@@ -238,8 +239,8 @@ static __init void cpu9krea_add_device_nor(void)
238{ 239{
239 unsigned long csa; 240 unsigned long csa;
240 241
241 csa = at91_sys_read(AT91_MATRIX_EBICSA); 242 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
242 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V); 243 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V);
243 244
244 /* configure chip-select 0 (NOR) */ 245 /* configure chip-select 0 (NOR) */
245 sam9_smc_configure(0, 0, &cpu9krea_nor_smc_config); 246 sam9_smc_configure(0, 0, &cpu9krea_nor_smc_config);
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index 368e1427ad99..e094cc81fe25 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -38,6 +38,7 @@
38 38
39#include <mach/board.h> 39#include <mach/board.h>
40#include <mach/at91rm9200_mc.h> 40#include <mach/at91rm9200_mc.h>
41#include <mach/at91_ramc.h>
41#include <mach/cpu.h> 42#include <mach/cpu.h>
42 43
43#include "generic.h" 44#include "generic.h"
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
index bb6b434ec0c1..08c8ad8609b7 100644
--- a/arch/arm/mach-at91/board-dt.c
+++ b/arch/arm/mach-at91/board-dt.c
@@ -38,12 +38,6 @@ static void __init ek_init_early(void)
38{ 38{
39 /* Initialize processor: 12.000 MHz crystal */ 39 /* Initialize processor: 12.000 MHz crystal */
40 at91_initialize(12000000); 40 at91_initialize(12000000);
41
42 /* DGBU on ttyS0. (Rx & Tx only) */
43 at91_register_uart(0, 0, 0);
44
45 /* set serial console to ttyS0 (ie, DBGU) */
46 at91_set_serial_console(0);
47} 41}
48 42
49/* det_pin is not connected */ 43/* det_pin is not connected */
@@ -109,6 +103,7 @@ static void __init at91_dt_device_init(void)
109 103
110static const char *at91_dt_board_compat[] __initdata = { 104static const char *at91_dt_board_compat[] __initdata = {
111 "atmel,at91sam9m10g45ek", 105 "atmel,at91sam9m10g45ek",
106 "atmel,at91sam9x5ek",
112 "calao,usb-a9g20", 107 "calao,usb-a9g20",
113 NULL 108 NULL
114}; 109};
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 07ef35b0ec2c..f23aabef8551 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -26,6 +26,7 @@
26 26
27#include <mach/board.h> 27#include <mach/board.h>
28#include <mach/at91rm9200_mc.h> 28#include <mach/at91rm9200_mc.h>
29#include <mach/at91_ramc.h>
29#include <mach/cpu.h> 30#include <mach/cpu.h>
30 31
31#include "generic.h" 32#include "generic.h"
@@ -110,7 +111,7 @@ static void __init eco920_board_init(void)
110 at91_add_device_mmc(0, &eco920_mmc_data); 111 at91_add_device_mmc(0, &eco920_mmc_data);
111 platform_device_register(&eco920_flash); 112 platform_device_register(&eco920_flash);
112 113
113 at91_sys_write(AT91_SMC_CSR(7), AT91_SMC_RWHOLD_(1) 114 at91_ramc_write(0, AT91_SMC_CSR(7), AT91_SMC_RWHOLD_(1)
114 | AT91_SMC_RWSETUP_(1) 115 | AT91_SMC_RWSETUP_(1)
115 | AT91_SMC_DBW_8 116 | AT91_SMC_DBW_8
116 | AT91_SMC_WSEN 117 | AT91_SMC_WSEN
@@ -122,7 +123,7 @@ static void __init eco920_board_init(void)
122 at91_set_deglitch(AT91_PIN_PA23, 1); 123 at91_set_deglitch(AT91_PIN_PA23, 1);
123 124
124/* Initialization of the Static Memory Controller for Chip Select 3 */ 125/* Initialization of the Static Memory Controller for Chip Select 3 */
125 at91_sys_write(AT91_SMC_CSR(3), 126 at91_ramc_write(0, AT91_SMC_CSR(3),
126 AT91_SMC_DBW_16 | /* 16 bit */ 127 AT91_SMC_DBW_16 | /* 16 bit */
127 AT91_SMC_WSEN | 128 AT91_SMC_WSEN |
128 AT91_SMC_NWS_(5) | /* wait states */ 129 AT91_SMC_NWS_(5) | /* wait states */
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index eec02cd57ced..1815152001f7 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/arch/arm/mach-at91/board-flexibity.c 2 * linux/arch/arm/mach-at91/board-flexibity.c
3 * 3 *
4 * Copyright (C) 2010 Flexibity 4 * Copyright (C) 2010-2011 Flexibity
5 * Copyright (C) 2005 SAN People 5 * Copyright (C) 2005 SAN People
6 * Copyright (C) 2006 Atmel 6 * Copyright (C) 2006 Atmel
7 * 7 *
@@ -62,6 +62,13 @@ static struct at91_udc_data __initdata flexibity_udc_data = {
62 .pullup_pin = -EINVAL, /* pull-up driven by UDC */ 62 .pullup_pin = -EINVAL, /* pull-up driven by UDC */
63}; 63};
64 64
65/* I2C devices */
66static struct i2c_board_info __initdata flexibity_i2c_devices[] = {
67 {
68 I2C_BOARD_INFO("ds1307", 0x68),
69 },
70};
71
65/* SPI devices */ 72/* SPI devices */
66static struct spi_board_info flexibity_spi_devices[] = { 73static struct spi_board_info flexibity_spi_devices[] = {
67 { /* DataFlash chip */ 74 { /* DataFlash chip */
@@ -141,6 +148,9 @@ static void __init flexibity_board_init(void)
141 at91_add_device_usbh(&flexibity_usbh_data); 148 at91_add_device_usbh(&flexibity_usbh_data);
142 /* USB Device */ 149 /* USB Device */
143 at91_add_device_udc(&flexibity_udc_data); 150 at91_add_device_udc(&flexibity_udc_data);
151 /* I2C */
152 at91_add_device_i2c(flexibity_i2c_devices,
153 ARRAY_SIZE(flexibity_i2c_devices));
144 /* SPI */ 154 /* SPI */
145 at91_add_device_spi(flexibity_spi_devices, 155 at91_add_device_spi(flexibity_spi_devices,
146 ARRAY_SIZE(flexibity_spi_devices)); 156 ARRAY_SIZE(flexibity_spi_devices));
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index d75a4a2ad9c2..bb9914582013 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -38,6 +38,7 @@
38#include <mach/board.h> 38#include <mach/board.h>
39#include <mach/cpu.h> 39#include <mach/cpu.h>
40#include <mach/at91rm9200_mc.h> 40#include <mach/at91rm9200_mc.h>
41#include <mach/at91_ramc.h>
41 42
42#include "generic.h" 43#include "generic.h"
43 44
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index ab024fa11d5c..59e35dd14863 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -39,6 +39,7 @@
39 39
40#include <mach/board.h> 40#include <mach/board.h>
41#include <mach/at91rm9200_mc.h> 41#include <mach/at91rm9200_mc.h>
42#include <mach/at91_ramc.h>
42 43
43#include "generic.h" 44#include "generic.h"
44 45
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index 782f37946af5..9083df04e7ed 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -41,6 +41,7 @@
41#include <mach/hardware.h> 41#include <mach/hardware.h>
42#include <mach/board.h> 42#include <mach/board.h>
43#include <mach/at91rm9200_mc.h> 43#include <mach/at91rm9200_mc.h>
44#include <mach/at91_ramc.h>
44 45
45#include "generic.h" 46#include "generic.h"
46 47
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index ef7c12a92246..11cbaa8946fe 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -41,6 +41,7 @@
41#include <mach/hardware.h> 41#include <mach/hardware.h>
42#include <mach/board.h> 42#include <mach/board.h>
43#include <mach/at91rm9200_mc.h> 43#include <mach/at91rm9200_mc.h>
44#include <mach/at91_ramc.h>
44 45
45#include "generic.h" 46#include "generic.h"
46 47
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index ea0d1b9c2b7b..57497e2b8878 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -24,11 +24,13 @@
24#include <linux/gpio_keys.h> 24#include <linux/gpio_keys.h>
25#include <linux/input.h> 25#include <linux/input.h>
26#include <linux/leds.h> 26#include <linux/leds.h>
27#include <linux/clk.h>
28#include <linux/atmel-mci.h> 27#include <linux/atmel-mci.h>
28#include <linux/delay.h>
29 29
30#include <mach/hardware.h> 30#include <mach/hardware.h>
31#include <video/atmel_lcdc.h> 31#include <video/atmel_lcdc.h>
32#include <media/soc_camera.h>
33#include <media/atmel-isi.h>
32 34
33#include <asm/setup.h> 35#include <asm/setup.h>
34#include <asm/mach-types.h> 36#include <asm/mach-types.h>
@@ -185,6 +187,71 @@ static void __init ek_add_device_nand(void)
185 187
186 188
187/* 189/*
190 * ISI
191 */
192static struct isi_platform_data __initdata isi_data = {
193 .frate = ISI_CFG1_FRATE_CAPTURE_ALL,
194 /* to use codec and preview path simultaneously */
195 .full_mode = 1,
196 .data_width_flags = ISI_DATAWIDTH_8 | ISI_DATAWIDTH_10,
197 /* ISI_MCK is provided by programmable clock or external clock */
198 .mck_hz = 25000000,
199};
200
201
202/*
203 * soc-camera OV2640
204 */
205#if defined(CONFIG_SOC_CAMERA_OV2640) || \
206 defined(CONFIG_SOC_CAMERA_OV2640_MODULE)
207static unsigned long isi_camera_query_bus_param(struct soc_camera_link *link)
208{
209 /* ISI board for ek using default 8-bits connection */
210 return SOCAM_DATAWIDTH_8;
211}
212
213static int i2c_camera_power(struct device *dev, int on)
214{
215 /* enable or disable the camera */
216 pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
217 at91_set_gpio_output(AT91_PIN_PD13, !on);
218
219 if (!on)
220 goto out;
221
222 /* If enabled, give a reset impulse */
223 at91_set_gpio_output(AT91_PIN_PD12, 0);
224 msleep(20);
225 at91_set_gpio_output(AT91_PIN_PD12, 1);
226 msleep(100);
227
228out:
229 return 0;
230}
231
232static struct i2c_board_info i2c_camera = {
233 I2C_BOARD_INFO("ov2640", 0x30),
234};
235
236static struct soc_camera_link iclink_ov2640 = {
237 .bus_id = 0,
238 .board_info = &i2c_camera,
239 .i2c_adapter_id = 0,
240 .power = i2c_camera_power,
241 .query_bus_param = isi_camera_query_bus_param,
242};
243
244static struct platform_device isi_ov2640 = {
245 .name = "soc-camera-pdrv",
246 .id = 0,
247 .dev = {
248 .platform_data = &iclink_ov2640,
249 },
250};
251#endif
252
253
254/*
188 * LCD Controller 255 * LCD Controller
189 */ 256 */
190#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) 257#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
@@ -377,7 +444,12 @@ static struct gpio_led ek_pwm_led[] = {
377#endif 444#endif
378}; 445};
379 446
380 447static struct platform_device *devices[] __initdata = {
448#if defined(CONFIG_SOC_CAMERA_OV2640) || \
449 defined(CONFIG_SOC_CAMERA_OV2640_MODULE)
450 &isi_ov2640,
451#endif
452};
381 453
382static void __init ek_board_init(void) 454static void __init ek_board_init(void)
383{ 455{
@@ -399,6 +471,8 @@ static void __init ek_board_init(void)
399 ek_add_device_nand(); 471 ek_add_device_nand();
400 /* I2C */ 472 /* I2C */
401 at91_add_device_i2c(0, NULL, 0); 473 at91_add_device_i2c(0, NULL, 0);
474 /* ISI, using programmable clock as ISI_MCK */
475 at91_add_device_isi(&isi_data, true);
402 /* LCD Controller */ 476 /* LCD Controller */
403 at91_add_device_lcdc(&ek_lcdc_data); 477 at91_add_device_lcdc(&ek_lcdc_data);
404 /* Touch Screen */ 478 /* Touch Screen */
@@ -410,6 +484,8 @@ static void __init ek_board_init(void)
410 /* LEDs */ 484 /* LEDs */
411 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); 485 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
412 at91_pwm_leds(ek_pwm_led, ARRAY_SIZE(ek_pwm_led)); 486 at91_pwm_leds(ek_pwm_led, ARRAY_SIZE(ek_pwm_led));
487 /* Other platform devices */
488 platform_add_devices(devices, ARRAY_SIZE(devices));
413} 489}
414 490
415MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK") 491MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index bbd553e1cd93..52f460768f71 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -45,6 +45,7 @@
45#include <mach/hardware.h> 45#include <mach/hardware.h>
46#include <mach/board.h> 46#include <mach/board.h>
47#include <mach/at91rm9200_mc.h> 47#include <mach/at91rm9200_mc.h>
48#include <mach/at91_ramc.h>
48#include <mach/cpu.h> 49#include <mach/cpu.h>
49 50
50#include "generic.h" 51#include "generic.h"
@@ -393,7 +394,7 @@ static void yl9200_init_video(void)
393 at91_set_A_periph(AT91_PIN_PC6, 0); 394 at91_set_A_periph(AT91_PIN_PC6, 0);
394 395
395 /* Initialization of the Static Memory Controller for Chip Select 2 */ 396 /* Initialization of the Static Memory Controller for Chip Select 2 */
396 at91_sys_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */ 397 at91_ramc_write(0, AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */
397 | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4) /* wait states */ 398 | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4) /* wait states */
398 | AT91_SMC_TDF_(0x100) /* float time */ 399 | AT91_SMC_TDF_(0x100) /* float time */
399 ); 400 );
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 61873f3aa92d..be51ca7f694d 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -28,9 +28,12 @@
28#include <mach/at91_pmc.h> 28#include <mach/at91_pmc.h>
29#include <mach/cpu.h> 29#include <mach/cpu.h>
30 30
31#include <asm/proc-fns.h>
32
31#include "clock.h" 33#include "clock.h"
32#include "generic.h" 34#include "generic.h"
33 35
36void __iomem *at91_pmc_base;
34 37
35/* 38/*
36 * There's a lot more which can be done with clocks, including cpufreq 39 * There's a lot more which can be done with clocks, including cpufreq
@@ -47,26 +50,38 @@
47/* 50/*
48 * Chips have some kind of clocks : group them by functionality 51 * Chips have some kind of clocks : group them by functionality
49 */ 52 */
50#define cpu_has_utmi() ( cpu_is_at91cap9() \ 53#define cpu_has_utmi() ( cpu_is_at91sam9rl() \
51 || cpu_is_at91sam9rl() \ 54 || cpu_is_at91sam9g45() \
52 || cpu_is_at91sam9g45()) 55 || cpu_is_at91sam9x5())
53 56
54#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \ 57#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
55 || cpu_is_at91sam9g45()) 58 || cpu_is_at91sam9g45() \
59 || cpu_is_at91sam9x5())
56 60
57#define cpu_has_300M_plla() (cpu_is_at91sam9g10()) 61#define cpu_has_300M_plla() (cpu_is_at91sam9g10())
58 62
59#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \ 63#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
60 || cpu_is_at91sam9g45())) 64 || cpu_is_at91sam9g45() \
65 || cpu_is_at91sam9x5()))
61 66
62#define cpu_has_upll() (cpu_is_at91sam9g45()) 67#define cpu_has_upll() (cpu_is_at91sam9g45() \
68 || cpu_is_at91sam9x5())
63 69
64/* USB host HS & FS */ 70/* USB host HS & FS */
65#define cpu_has_uhp() (!cpu_is_at91sam9rl()) 71#define cpu_has_uhp() (!cpu_is_at91sam9rl())
66 72
67/* USB device FS only */ 73/* USB device FS only */
68#define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \ 74#define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \
69 || cpu_is_at91sam9g45())) 75 || cpu_is_at91sam9g45() \
76 || cpu_is_at91sam9x5()))
77
78#define cpu_has_plladiv2() (cpu_is_at91sam9g45() \
79 || cpu_is_at91sam9x5())
80
81#define cpu_has_mdiv3() (cpu_is_at91sam9g45() \
82 || cpu_is_at91sam9x5())
83
84#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5())
70 85
71static LIST_HEAD(clocks); 86static LIST_HEAD(clocks);
72static DEFINE_SPINLOCK(clk_lock); 87static DEFINE_SPINLOCK(clk_lock);
@@ -111,11 +126,11 @@ static void pllb_mode(struct clk *clk, int is_on)
111 value = 0; 126 value = 0;
112 127
113 // REVISIT: Add work-around for AT91RM9200 Errata #26 ? 128 // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
114 at91_sys_write(AT91_CKGR_PLLBR, value); 129 at91_pmc_write(AT91_CKGR_PLLBR, value);
115 130
116 do { 131 do {
117 cpu_relax(); 132 cpu_relax();
118 } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on); 133 } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
119} 134}
120 135
121static struct clk pllb = { 136static struct clk pllb = {
@@ -130,31 +145,24 @@ static struct clk pllb = {
130static void pmc_sys_mode(struct clk *clk, int is_on) 145static void pmc_sys_mode(struct clk *clk, int is_on)
131{ 146{
132 if (is_on) 147 if (is_on)
133 at91_sys_write(AT91_PMC_SCER, clk->pmc_mask); 148 at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask);
134 else 149 else
135 at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask); 150 at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask);
136} 151}
137 152
138static void pmc_uckr_mode(struct clk *clk, int is_on) 153static void pmc_uckr_mode(struct clk *clk, int is_on)
139{ 154{
140 unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR); 155 unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
141
142 if (cpu_is_at91sam9g45()) {
143 if (is_on)
144 uckr |= AT91_PMC_BIASEN;
145 else
146 uckr &= ~AT91_PMC_BIASEN;
147 }
148 156
149 if (is_on) { 157 if (is_on) {
150 is_on = AT91_PMC_LOCKU; 158 is_on = AT91_PMC_LOCKU;
151 at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask); 159 at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
152 } else 160 } else
153 at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask)); 161 at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
154 162
155 do { 163 do {
156 cpu_relax(); 164 cpu_relax();
157 } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on); 165 } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
158} 166}
159 167
160/* USB function clocks (PLLB must be 48 MHz) */ 168/* USB function clocks (PLLB must be 48 MHz) */
@@ -190,9 +198,9 @@ struct clk mck = {
190static void pmc_periph_mode(struct clk *clk, int is_on) 198static void pmc_periph_mode(struct clk *clk, int is_on)
191{ 199{
192 if (is_on) 200 if (is_on)
193 at91_sys_write(AT91_PMC_PCER, clk->pmc_mask); 201 at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
194 else 202 else
195 at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask); 203 at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
196} 204}
197 205
198static struct clk __init *at91_css_to_clk(unsigned long css) 206static struct clk __init *at91_css_to_clk(unsigned long css)
@@ -210,11 +218,24 @@ static struct clk __init *at91_css_to_clk(unsigned long css)
210 return &utmi_clk; 218 return &utmi_clk;
211 else if (cpu_has_pllb()) 219 else if (cpu_has_pllb())
212 return &pllb; 220 return &pllb;
221 break;
222 /* alternate PMC: can use master clock */
223 case AT91_PMC_CSS_MASTER:
224 return &mck;
213 } 225 }
214 226
215 return NULL; 227 return NULL;
216} 228}
217 229
230static int pmc_prescaler_divider(u32 reg)
231{
232 if (cpu_has_alt_prescaler()) {
233 return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET);
234 } else {
235 return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET);
236 }
237}
238
218static void __clk_enable(struct clk *clk) 239static void __clk_enable(struct clk *clk)
219{ 240{
220 if (clk->parent) 241 if (clk->parent)
@@ -316,12 +337,22 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
316{ 337{
317 unsigned long flags; 338 unsigned long flags;
318 unsigned prescale; 339 unsigned prescale;
340 unsigned long prescale_offset, css_mask;
319 unsigned long actual; 341 unsigned long actual;
320 342
321 if (!clk_is_programmable(clk)) 343 if (!clk_is_programmable(clk))
322 return -EINVAL; 344 return -EINVAL;
323 if (clk->users) 345 if (clk->users)
324 return -EBUSY; 346 return -EBUSY;
347
348 if (cpu_has_alt_prescaler()) {
349 prescale_offset = PMC_ALT_PRES_OFFSET;
350 css_mask = AT91_PMC_ALT_PCKR_CSS;
351 } else {
352 prescale_offset = PMC_PRES_OFFSET;
353 css_mask = AT91_PMC_CSS;
354 }
355
325 spin_lock_irqsave(&clk_lock, flags); 356 spin_lock_irqsave(&clk_lock, flags);
326 357
327 actual = clk->parent->rate_hz; 358 actual = clk->parent->rate_hz;
@@ -329,10 +360,10 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
329 if (actual && actual <= rate) { 360 if (actual && actual <= rate) {
330 u32 pckr; 361 u32 pckr;
331 362
332 pckr = at91_sys_read(AT91_PMC_PCKR(clk->id)); 363 pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
333 pckr &= AT91_PMC_CSS; /* clock selection */ 364 pckr &= css_mask; /* keep clock selection */
334 pckr |= prescale << 2; 365 pckr |= prescale << prescale_offset;
335 at91_sys_write(AT91_PMC_PCKR(clk->id), pckr); 366 at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr);
336 clk->rate_hz = actual; 367 clk->rate_hz = actual;
337 break; 368 break;
338 } 369 }
@@ -366,7 +397,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
366 397
367 clk->rate_hz = parent->rate_hz; 398 clk->rate_hz = parent->rate_hz;
368 clk->parent = parent; 399 clk->parent = parent;
369 at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id); 400 at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id);
370 401
371 spin_unlock_irqrestore(&clk_lock, flags); 402 spin_unlock_irqrestore(&clk_lock, flags);
372 return 0; 403 return 0;
@@ -378,11 +409,17 @@ static void __init init_programmable_clock(struct clk *clk)
378{ 409{
379 struct clk *parent; 410 struct clk *parent;
380 u32 pckr; 411 u32 pckr;
412 unsigned int css_mask;
413
414 if (cpu_has_alt_prescaler())
415 css_mask = AT91_PMC_ALT_PCKR_CSS;
416 else
417 css_mask = AT91_PMC_CSS;
381 418
382 pckr = at91_sys_read(AT91_PMC_PCKR(clk->id)); 419 pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
383 parent = at91_css_to_clk(pckr & AT91_PMC_CSS); 420 parent = at91_css_to_clk(pckr & css_mask);
384 clk->parent = parent; 421 clk->parent = parent;
385 clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2)); 422 clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
386} 423}
387 424
388#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */ 425#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
@@ -396,19 +433,24 @@ static int at91_clk_show(struct seq_file *s, void *unused)
396 u32 scsr, pcsr, uckr = 0, sr; 433 u32 scsr, pcsr, uckr = 0, sr;
397 struct clk *clk; 434 struct clk *clk;
398 435
399 seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR)); 436 scsr = at91_pmc_read(AT91_PMC_SCSR);
400 seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR)); 437 pcsr = at91_pmc_read(AT91_PMC_PCSR);
401 seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR)); 438 sr = at91_pmc_read(AT91_PMC_SR);
402 seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR)); 439 seq_printf(s, "SCSR = %8x\n", scsr);
403 seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR)); 440 seq_printf(s, "PCSR = %8x\n", pcsr);
441 seq_printf(s, "MOR = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
442 seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
443 seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
404 if (cpu_has_pllb()) 444 if (cpu_has_pllb())
405 seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR)); 445 seq_printf(s, "PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR));
406 if (cpu_has_utmi()) 446 if (cpu_has_utmi()) {
407 seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR)); 447 uckr = at91_pmc_read(AT91_CKGR_UCKR);
408 seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR)); 448 seq_printf(s, "UCKR = %8x\n", uckr);
449 }
450 seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
409 if (cpu_has_upll()) 451 if (cpu_has_upll())
410 seq_printf(s, "USB = %8x\n", at91_sys_read(AT91_PMC_USB)); 452 seq_printf(s, "USB = %8x\n", at91_pmc_read(AT91_PMC_USB));
411 seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR)); 453 seq_printf(s, "SR = %8x\n", sr);
412 454
413 seq_printf(s, "\n"); 455 seq_printf(s, "\n");
414 456
@@ -596,16 +638,14 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
596 if (cpu_is_at91rm9200()) { 638 if (cpu_is_at91rm9200()) {
597 uhpck.pmc_mask = AT91RM9200_PMC_UHP; 639 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
598 udpck.pmc_mask = AT91RM9200_PMC_UDP; 640 udpck.pmc_mask = AT91RM9200_PMC_UDP;
599 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); 641 at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
600 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || 642 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
601 cpu_is_at91sam9263() || cpu_is_at91sam9g20() || 643 cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
602 cpu_is_at91sam9g10()) { 644 cpu_is_at91sam9g10()) {
603 uhpck.pmc_mask = AT91SAM926x_PMC_UHP; 645 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
604 udpck.pmc_mask = AT91SAM926x_PMC_UDP; 646 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
605 } else if (cpu_is_at91cap9()) {
606 uhpck.pmc_mask = AT91CAP9_PMC_UHP;
607 } 647 }
608 at91_sys_write(AT91_CKGR_PLLBR, 0); 648 at91_pmc_write(AT91_CKGR_PLLBR, 0);
609 649
610 udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); 650 udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
611 uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); 651 uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
@@ -622,13 +662,13 @@ static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
622 /* Setup divider by 10 to reach 48 MHz */ 662 /* Setup divider by 10 to reach 48 MHz */
623 usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV; 663 usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
624 664
625 at91_sys_write(AT91_PMC_USB, usbr); 665 at91_pmc_write(AT91_PMC_USB, usbr);
626 666
627 /* Now set uhpck values */ 667 /* Now set uhpck values */
628 uhpck.parent = &utmi_clk; 668 uhpck.parent = &utmi_clk;
629 uhpck.pmc_mask = AT91SAM926x_PMC_UHP; 669 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
630 uhpck.rate_hz = utmi_clk.rate_hz; 670 uhpck.rate_hz = utmi_clk.rate_hz;
631 uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8); 671 uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
632} 672}
633 673
634int __init at91_clock_init(unsigned long main_clock) 674int __init at91_clock_init(unsigned long main_clock)
@@ -637,6 +677,10 @@ int __init at91_clock_init(unsigned long main_clock)
637 int i; 677 int i;
638 int pll_overclock = false; 678 int pll_overclock = false;
639 679
680 at91_pmc_base = ioremap(AT91_PMC, 256);
681 if (!at91_pmc_base)
682 panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
683
640 /* 684 /*
641 * When the bootloader initialized the main oscillator correctly, 685 * When the bootloader initialized the main oscillator correctly,
642 * there's no problem using the cycle counter. But if it didn't, 686 * there's no problem using the cycle counter. But if it didn't,
@@ -645,14 +689,14 @@ int __init at91_clock_init(unsigned long main_clock)
645 */ 689 */
646 if (!main_clock) { 690 if (!main_clock) {
647 do { 691 do {
648 tmp = at91_sys_read(AT91_CKGR_MCFR); 692 tmp = at91_pmc_read(AT91_CKGR_MCFR);
649 } while (!(tmp & AT91_PMC_MAINRDY)); 693 } while (!(tmp & AT91_PMC_MAINRDY));
650 main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); 694 main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
651 } 695 }
652 main_clk.rate_hz = main_clock; 696 main_clk.rate_hz = main_clock;
653 697
654 /* report if PLLA is more than mildly overclocked */ 698 /* report if PLLA is more than mildly overclocked */
655 plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); 699 plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
656 if (cpu_has_300M_plla()) { 700 if (cpu_has_300M_plla()) {
657 if (plla.rate_hz > 300000000) 701 if (plla.rate_hz > 300000000)
658 pll_overclock = true; 702 pll_overclock = true;
@@ -666,8 +710,8 @@ int __init at91_clock_init(unsigned long main_clock)
666 if (pll_overclock) 710 if (pll_overclock)
667 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); 711 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
668 712
669 if (cpu_is_at91sam9g45()) { 713 if (cpu_has_plladiv2()) {
670 mckr = at91_sys_read(AT91_PMC_MCKR); 714 mckr = at91_pmc_read(AT91_PMC_MCKR);
671 plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */ 715 plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */
672 } 716 }
673 717
@@ -688,6 +732,10 @@ int __init at91_clock_init(unsigned long main_clock)
688 * (obtain the USB High Speed 480 MHz when input is 12 MHz) 732 * (obtain the USB High Speed 480 MHz when input is 12 MHz)
689 */ 733 */
690 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz; 734 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
735
736 /* UTMI bias and PLL are managed at the same time */
737 if (cpu_has_upll())
738 utmi_clk.pmc_mask |= AT91_PMC_BIASEN;
691 } 739 }
692 740
693 /* 741 /*
@@ -703,10 +751,10 @@ int __init at91_clock_init(unsigned long main_clock)
703 * MCK and CPU derive from one of those primary clocks. 751 * MCK and CPU derive from one of those primary clocks.
704 * For now, assume this parentage won't change. 752 * For now, assume this parentage won't change.
705 */ 753 */
706 mckr = at91_sys_read(AT91_PMC_MCKR); 754 mckr = at91_pmc_read(AT91_PMC_MCKR);
707 mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); 755 mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
708 freq = mck.parent->rate_hz; 756 freq = mck.parent->rate_hz;
709 freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ 757 freq /= pmc_prescaler_divider(mckr); /* prescale */
710 if (cpu_is_at91rm9200()) { 758 if (cpu_is_at91rm9200()) {
711 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ 759 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
712 } else if (cpu_is_at91sam9g20()) { 760 } else if (cpu_is_at91sam9g20()) {
@@ -714,13 +762,19 @@ int __init at91_clock_init(unsigned long main_clock)
714 freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ 762 freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
715 if (mckr & AT91_PMC_PDIV) 763 if (mckr & AT91_PMC_PDIV)
716 freq /= 2; /* processor clock division */ 764 freq /= 2; /* processor clock division */
717 } else if (cpu_is_at91sam9g45()) { 765 } else if (cpu_has_mdiv3()) {
718 mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ? 766 mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
719 freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ 767 freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
720 } else { 768 } else {
721 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ 769 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
722 } 770 }
723 771
772 if (cpu_has_alt_prescaler()) {
773 /* Programmable clocks can use MCK */
774 mck.type |= CLK_TYPE_PRIMARY;
775 mck.id = 4;
776 }
777
724 /* Register the PMC's standard clocks */ 778 /* Register the PMC's standard clocks */
725 for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) 779 for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
726 at91_clk_add(standard_pmc_clocks[i]); 780 at91_clk_add(standard_pmc_clocks[i]);
@@ -770,9 +824,15 @@ static int __init at91_clock_reset(void)
770 pr_debug("Clocks: disable unused %s\n", clk->name); 824 pr_debug("Clocks: disable unused %s\n", clk->name);
771 } 825 }
772 826
773 at91_sys_write(AT91_PMC_PCDR, pcdr); 827 at91_pmc_write(AT91_PMC_PCDR, pcdr);
774 at91_sys_write(AT91_PMC_SCDR, scdr); 828 at91_pmc_write(AT91_PMC_SCDR, scdr);
775 829
776 return 0; 830 return 0;
777} 831}
778late_initcall(at91_clock_reset); 832late_initcall(at91_clock_reset);
833
834void at91sam9_idle(void)
835{
836 at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
837 cpu_do_idle();
838}
diff --git a/arch/arm/mach-at91/cpuidle.c b/arch/arm/mach-at91/cpuidle.c
index a851e6c98421..555d956b3a57 100644
--- a/arch/arm/mach-at91/cpuidle.c
+++ b/arch/arm/mach-at91/cpuidle.c
@@ -39,20 +39,15 @@ static int at91_enter_idle(struct cpuidle_device *dev,
39{ 39{
40 struct timeval before, after; 40 struct timeval before, after;
41 int idle_time; 41 int idle_time;
42 u32 saved_lpr;
43 42
44 local_irq_disable(); 43 local_irq_disable();
45 do_gettimeofday(&before); 44 do_gettimeofday(&before);
46 if (index == 0) 45 if (index == 0)
47 /* Wait for interrupt state */ 46 /* Wait for interrupt state */
48 cpu_do_idle(); 47 cpu_do_idle();
49 else if (index == 1) { 48 else if (index == 1)
50 asm("b 1f; .align 5; 1:"); 49 at91_standby();
51 asm("mcr p15, 0, r0, c7, c10, 4"); /* drain write buffer */ 50
52 saved_lpr = sdram_selfrefresh_enable();
53 cpu_do_idle();
54 sdram_selfrefresh_disable(saved_lpr);
55 }
56 do_gettimeofday(&after); 51 do_gettimeofday(&after);
57 local_irq_enable(); 52 local_irq_enable();
58 idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC + 53 idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 594133451c0c..4cad85e57470 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -28,6 +28,7 @@ extern void __init at91_aic_init(unsigned int priority[]);
28 28
29 /* Timer */ 29 /* Timer */
30struct sys_timer; 30struct sys_timer;
31extern void at91rm9200_ioremap_st(u32 addr);
31extern struct sys_timer at91rm9200_timer; 32extern struct sys_timer at91rm9200_timer;
32extern void at91sam926x_ioremap_pit(u32 addr); 33extern void at91sam926x_ioremap_pit(u32 addr);
33extern struct sys_timer at91sam926x_timer; 34extern struct sys_timer at91sam926x_timer;
@@ -45,7 +46,6 @@ extern void __init at91sam9261_set_console_clock(int id);
45extern void __init at91sam9263_set_console_clock(int id); 46extern void __init at91sam9263_set_console_clock(int id);
46extern void __init at91sam9rl_set_console_clock(int id); 47extern void __init at91sam9rl_set_console_clock(int id);
47extern void __init at91sam9g45_set_console_clock(int id); 48extern void __init at91sam9g45_set_console_clock(int id);
48extern void __init at91cap9_set_console_clock(int id);
49#ifdef CONFIG_AT91_PMC_UNIT 49#ifdef CONFIG_AT91_PMC_UNIT
50extern int __init at91_clock_init(unsigned long main_clock); 50extern int __init at91_clock_init(unsigned long main_clock);
51#else 51#else
@@ -57,6 +57,9 @@ struct device;
57extern void at91_irq_suspend(void); 57extern void at91_irq_suspend(void);
58extern void at91_irq_resume(void); 58extern void at91_irq_resume(void);
59 59
60/* idle */
61extern void at91sam9_idle(void);
62
60/* reset */ 63/* reset */
61extern void at91_ioremap_rstc(u32 base_addr); 64extern void at91_ioremap_rstc(u32 base_addr);
62extern void at91sam9_alt_restart(char, const char *); 65extern void at91sam9_alt_restart(char, const char *);
@@ -65,6 +68,12 @@ extern void at91sam9g45_restart(char, const char *);
65/* shutdown */ 68/* shutdown */
66extern void at91_ioremap_shdwc(u32 base_addr); 69extern void at91_ioremap_shdwc(u32 base_addr);
67 70
71/* Matrix */
72extern void at91_ioremap_matrix(u32 base_addr);
73
74/* Ram Controler */
75extern void at91_ioremap_ramc(int id, u32 addr, u32 size);
76
68 /* GPIO */ 77 /* GPIO */
69#define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */ 78#define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */
70#define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */ 79#define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */
diff --git a/arch/arm/mach-at91/include/mach/at91_matrix.h b/arch/arm/mach-at91/include/mach/at91_matrix.h
new file mode 100644
index 000000000000..02fae9de746b
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_matrix.h
@@ -0,0 +1,23 @@
1/*
2 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
3 *
4 * Under GPLv2
5 */
6
7#ifndef __MACH_AT91_MATRIX_H__
8#define __MACH_AT91_MATRIX_H__
9
10#ifndef __ASSEMBLY__
11extern void __iomem *at91_matrix_base;
12
13#define at91_matrix_read(field) \
14 __raw_readl(at91_matrix_base + field)
15
16#define at91_matrix_write(field, value) \
17 __raw_writel(value, at91_matrix_base + field);
18
19#else
20.extern at91_matrix_base
21#endif
22
23#endif /* __MACH_AT91_MATRIX_H__ */
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index e46f93e34aab..36604782a78f 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -16,17 +16,27 @@
16#ifndef AT91_PMC_H 16#ifndef AT91_PMC_H
17#define AT91_PMC_H 17#define AT91_PMC_H
18 18
19#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ 19#ifndef __ASSEMBLY__
20#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ 20extern void __iomem *at91_pmc_base;
21 21
22#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ 22#define at91_pmc_read(field) \
23 __raw_readl(at91_pmc_base + field)
24
25#define at91_pmc_write(field, value) \
26 __raw_writel(value, at91_pmc_base + field)
27#else
28.extern at91_aic_base
29#endif
30
31#define AT91_PMC_SCER 0x00 /* System Clock Enable Register */
32#define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */
33
34#define AT91_PMC_SCSR 0x08 /* System Clock Status Register */
23#define AT91_PMC_PCK (1 << 0) /* Processor Clock */ 35#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
24#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ 36#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
25#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ 37#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
26#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [CAP9 revC & some SAM9 only] */
27#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ 38#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
28#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ 39#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
29#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */
30#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ 40#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
31#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ 41#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
32#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ 42#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
@@ -36,27 +46,31 @@
36#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ 46#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
37#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ 47#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
38 48
39#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ 49#define AT91_PMC_PCER 0x10 /* Peripheral Clock Enable Register */
40#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ 50#define AT91_PMC_PCDR 0x14 /* Peripheral Clock Disable Register */
41#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ 51#define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */
42 52
43#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [some SAM9, CAP9] */ 53#define AT91_CKGR_UCKR 0x1C /* UTMI Clock Register [some SAM9] */
44#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ 54#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
45#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ 55#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
46#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ 56#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
47#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ 57#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */
48 58
49#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ 59#define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */
50#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ 60#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
51#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ 61#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */
52#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ 62#define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */
63#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
64#define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */
65#define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */
66#define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */
53 67
54#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ 68#define AT91_CKGR_MCFR 0x24 /* Main Clock Frequency Register */
55#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ 69#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
56#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ 70#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
57 71
58#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ 72#define AT91_CKGR_PLLAR 0x28 /* PLL A Register */
59#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ 73#define AT91_CKGR_PLLBR 0x2c /* PLL B Register */
60#define AT91_PMC_DIV (0xff << 0) /* Divider */ 74#define AT91_PMC_DIV (0xff << 0) /* Divider */
61#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ 75#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
62#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ 76#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
@@ -67,27 +81,37 @@
67#define AT91_PMC_USBDIV_4 (2 << 28) 81#define AT91_PMC_USBDIV_4 (2 << 28)
68#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ 82#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
69 83
70#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ 84#define AT91_PMC_MCKR 0x30 /* Master Clock Register */
71#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ 85#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
72#define AT91_PMC_CSS_SLOW (0 << 0) 86#define AT91_PMC_CSS_SLOW (0 << 0)
73#define AT91_PMC_CSS_MAIN (1 << 0) 87#define AT91_PMC_CSS_MAIN (1 << 0)
74#define AT91_PMC_CSS_PLLA (2 << 0) 88#define AT91_PMC_CSS_PLLA (2 << 0)
75#define AT91_PMC_CSS_PLLB (3 << 0) 89#define AT91_PMC_CSS_PLLB (3 << 0)
76#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */ 90#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */
77#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ 91#define PMC_PRES_OFFSET 2
78#define AT91_PMC_PRES_1 (0 << 2) 92#define AT91_PMC_PRES (7 << PMC_PRES_OFFSET) /* Master Clock Prescaler */
79#define AT91_PMC_PRES_2 (1 << 2) 93#define AT91_PMC_PRES_1 (0 << PMC_PRES_OFFSET)
80#define AT91_PMC_PRES_4 (2 << 2) 94#define AT91_PMC_PRES_2 (1 << PMC_PRES_OFFSET)
81#define AT91_PMC_PRES_8 (3 << 2) 95#define AT91_PMC_PRES_4 (2 << PMC_PRES_OFFSET)
82#define AT91_PMC_PRES_16 (4 << 2) 96#define AT91_PMC_PRES_8 (3 << PMC_PRES_OFFSET)
83#define AT91_PMC_PRES_32 (5 << 2) 97#define AT91_PMC_PRES_16 (4 << PMC_PRES_OFFSET)
84#define AT91_PMC_PRES_64 (6 << 2) 98#define AT91_PMC_PRES_32 (5 << PMC_PRES_OFFSET)
99#define AT91_PMC_PRES_64 (6 << PMC_PRES_OFFSET)
100#define PMC_ALT_PRES_OFFSET 4
101#define AT91_PMC_ALT_PRES (7 << PMC_ALT_PRES_OFFSET) /* Master Clock Prescaler [alternate location] */
102#define AT91_PMC_ALT_PRES_1 (0 << PMC_ALT_PRES_OFFSET)
103#define AT91_PMC_ALT_PRES_2 (1 << PMC_ALT_PRES_OFFSET)
104#define AT91_PMC_ALT_PRES_4 (2 << PMC_ALT_PRES_OFFSET)
105#define AT91_PMC_ALT_PRES_8 (3 << PMC_ALT_PRES_OFFSET)
106#define AT91_PMC_ALT_PRES_16 (4 << PMC_ALT_PRES_OFFSET)
107#define AT91_PMC_ALT_PRES_32 (5 << PMC_ALT_PRES_OFFSET)
108#define AT91_PMC_ALT_PRES_64 (6 << PMC_ALT_PRES_OFFSET)
85#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ 109#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
86#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ 110#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
87#define AT91RM9200_PMC_MDIV_2 (1 << 8) 111#define AT91RM9200_PMC_MDIV_2 (1 << 8)
88#define AT91RM9200_PMC_MDIV_3 (2 << 8) 112#define AT91RM9200_PMC_MDIV_3 (2 << 8)
89#define AT91RM9200_PMC_MDIV_4 (3 << 8) 113#define AT91RM9200_PMC_MDIV_4 (3 << 8)
90#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */ 114#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */
91#define AT91SAM9_PMC_MDIV_2 (1 << 8) 115#define AT91SAM9_PMC_MDIV_2 (1 << 8)
92#define AT91SAM9_PMC_MDIV_4 (2 << 8) 116#define AT91SAM9_PMC_MDIV_4 (2 << 8)
93#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */ 117#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */
@@ -99,35 +123,55 @@
99#define AT91_PMC_PLLADIV2_OFF (0 << 12) 123#define AT91_PMC_PLLADIV2_OFF (0 << 12)
100#define AT91_PMC_PLLADIV2_ON (1 << 12) 124#define AT91_PMC_PLLADIV2_ON (1 << 12)
101 125
102#define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register [some SAM9 only] */ 126#define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */
103#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ 127#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */
104#define AT91_PMC_USBS_PLLA (0 << 0) 128#define AT91_PMC_USBS_PLLA (0 << 0)
105#define AT91_PMC_USBS_UPLL (1 << 0) 129#define AT91_PMC_USBS_UPLL (1 << 0)
106#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ 130#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */
107 131
108#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ 132#define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */
133#define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */
134#define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */
135#define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV)
136
137#define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
138#define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */
139#define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */
109#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */ 140#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */
110#define AT91_PMC_CSSMCK_CSS (0 << 8) 141#define AT91_PMC_CSSMCK_CSS (0 << 8)
111#define AT91_PMC_CSSMCK_MCK (1 << 8) 142#define AT91_PMC_CSSMCK_MCK (1 << 8)
112 143
113#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ 144#define AT91_PMC_IER 0x60 /* Interrupt Enable Register */
114#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ 145#define AT91_PMC_IDR 0x64 /* Interrupt Disable Register */
115#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ 146#define AT91_PMC_SR 0x68 /* Status Register */
116#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ 147#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
117#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ 148#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
118#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ 149#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
119#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ 150#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
120#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9, AT91CAP9 only] */ 151#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9] */
121#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */
122#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ 152#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
123#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ 153#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
124#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ 154#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
125#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ 155#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
126#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ 156#define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */
157#define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */
158#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */
159#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */
160
161#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */
162#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */
163#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */
164#define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */
127 165
128#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */ 166#define AT91_PMC_WPSR 0xe8 /* Write Protect Status Register [some SAM9] */
129#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ 167#define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */
168#define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */
130 169
131#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ 170#define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9] */
171#define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */
172#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command */
173#define AT91_PMC_PCR_DIV (0x3 << 16) /* Divisor Value */
174#define AT91_PMC_PCRDIV(n) (((n) << 16) & AT91_PMC_PCR_DIV)
175#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
132 176
133#endif 177#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_ramc.h b/arch/arm/mach-at91/include/mach/at91_ramc.h
new file mode 100644
index 000000000000..d8aeb278614e
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_ramc.h
@@ -0,0 +1,32 @@
1/*
2 * Header file for the Atmel RAM Controller
3 *
4 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Under GPLv2 only
7 */
8
9#ifndef __AT91_RAMC_H__
10#define __AT91_RAMC_H__
11
12#ifndef __ASSEMBLY__
13extern void __iomem *at91_ramc_base[];
14
15#define at91_ramc_read(id, field) \
16 __raw_readl(at91_ramc_base[id] + field)
17
18#define at91_ramc_write(id, field, value) \
19 __raw_writel(value, at91_ramc_base[id] + field)
20#else
21.extern at91_ramc_base
22#endif
23
24#define AT91_MEMCTRL_MC 0
25#define AT91_MEMCTRL_SDRAMC 1
26#define AT91_MEMCTRL_DDRSDR 2
27
28#include <mach/at91rm9200_sdramc.h>
29#include <mach/at91sam9_ddrsdr.h>
30#include <mach/at91sam9_sdramc.h>
31
32#endif /* __AT91_RAMC_H__ */
diff --git a/arch/arm/mach-at91/include/mach/at91_st.h b/arch/arm/mach-at91/include/mach/at91_st.h
index 8847173e4101..969aac27109f 100644
--- a/arch/arm/mach-at91/include/mach/at91_st.h
+++ b/arch/arm/mach-at91/include/mach/at91_st.h
@@ -16,34 +16,46 @@
16#ifndef AT91_ST_H 16#ifndef AT91_ST_H
17#define AT91_ST_H 17#define AT91_ST_H
18 18
19#define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */ 19#ifndef __ASSEMBLY__
20extern void __iomem *at91_st_base;
21
22#define at91_st_read(field) \
23 __raw_readl(at91_st_base + field)
24
25#define at91_st_write(field, value) \
26 __raw_writel(value, at91_st_base + field);
27#else
28.extern at91_st_base
29#endif
30
31#define AT91_ST_CR 0x00 /* Control Register */
20#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */ 32#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */
21 33
22#define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */ 34#define AT91_ST_PIMR 0x04 /* Period Interval Mode Register */
23#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */ 35#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */
24 36
25#define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */ 37#define AT91_ST_WDMR 0x08 /* Watchdog Mode Register */
26#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */ 38#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */
27#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */ 39#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */
28#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */ 40#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */
29 41
30#define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */ 42#define AT91_ST_RTMR 0x0c /* Real-time Mode Register */
31#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */ 43#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */
32 44
33#define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */ 45#define AT91_ST_SR 0x10 /* Status Register */
34#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */ 46#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */
35#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */ 47#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */
36#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */ 48#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */
37#define AT91_ST_ALMS (1 << 3) /* Alarm Status */ 49#define AT91_ST_ALMS (1 << 3) /* Alarm Status */
38 50
39#define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */ 51#define AT91_ST_IER 0x14 /* Interrupt Enable Register */
40#define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */ 52#define AT91_ST_IDR 0x18 /* Interrupt Disable Register */
41#define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */ 53#define AT91_ST_IMR 0x1c /* Interrupt Mask Register */
42 54
43#define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */ 55#define AT91_ST_RTAR 0x20 /* Real-time Alarm Register */
44#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */ 56#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */
45 57
46#define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */ 58#define AT91_ST_CRTR 0x24 /* Current Real-time Register */
47#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */ 59#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */
48 60
49#endif 61#endif
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h
deleted file mode 100644
index 61d952902f2b..000000000000
--- a/arch/arm/mach-at91/include/mach/at91cap9.h
+++ /dev/null
@@ -1,122 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91cap9.h
3 *
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2007 Atmel Corporation.
7 *
8 * Common definitions.
9 * Based on AT91CAP9 datasheet revision B (Preliminary).
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#ifndef AT91CAP9_H
18#define AT91CAP9_H
19
20/*
21 * Peripheral identifiers/interrupts.
22 */
23#define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */
24#define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */
25#define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */
26#define AT91CAP9_ID_MPB2 5 /* MP Block Peripheral 2 */
27#define AT91CAP9_ID_MPB3 6 /* MP Block Peripheral 3 */
28#define AT91CAP9_ID_MPB4 7 /* MP Block Peripheral 4 */
29#define AT91CAP9_ID_US0 8 /* USART 0 */
30#define AT91CAP9_ID_US1 9 /* USART 1 */
31#define AT91CAP9_ID_US2 10 /* USART 2 */
32#define AT91CAP9_ID_MCI0 11 /* Multimedia Card Interface 0 */
33#define AT91CAP9_ID_MCI1 12 /* Multimedia Card Interface 1 */
34#define AT91CAP9_ID_CAN 13 /* CAN */
35#define AT91CAP9_ID_TWI 14 /* Two-Wire Interface */
36#define AT91CAP9_ID_SPI0 15 /* Serial Peripheral Interface 0 */
37#define AT91CAP9_ID_SPI1 16 /* Serial Peripheral Interface 0 */
38#define AT91CAP9_ID_SSC0 17 /* Serial Synchronous Controller 0 */
39#define AT91CAP9_ID_SSC1 18 /* Serial Synchronous Controller 1 */
40#define AT91CAP9_ID_AC97C 19 /* AC97 Controller */
41#define AT91CAP9_ID_TCB 20 /* Timer Counter 0, 1 and 2 */
42#define AT91CAP9_ID_PWMC 21 /* Pulse Width Modulation Controller */
43#define AT91CAP9_ID_EMAC 22 /* Ethernet */
44#define AT91CAP9_ID_AESTDES 23 /* Advanced Encryption Standard, Triple DES */
45#define AT91CAP9_ID_ADC 24 /* Analog-to-Digital Converter */
46#define AT91CAP9_ID_ISI 25 /* Image Sensor Interface */
47#define AT91CAP9_ID_LCDC 26 /* LCD Controller */
48#define AT91CAP9_ID_DMA 27 /* DMA Controller */
49#define AT91CAP9_ID_UDPHS 28 /* USB High Speed Device Port */
50#define AT91CAP9_ID_UHP 29 /* USB Host Port */
51#define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
52#define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
53
54/*
55 * User Peripheral physical base addresses.
56 */
57#define AT91CAP9_BASE_UDPHS 0xfff78000
58#define AT91CAP9_BASE_TCB0 0xfff7c000
59#define AT91CAP9_BASE_TC0 0xfff7c000
60#define AT91CAP9_BASE_TC1 0xfff7c040
61#define AT91CAP9_BASE_TC2 0xfff7c080
62#define AT91CAP9_BASE_MCI0 0xfff80000
63#define AT91CAP9_BASE_MCI1 0xfff84000
64#define AT91CAP9_BASE_TWI 0xfff88000
65#define AT91CAP9_BASE_US0 0xfff8c000
66#define AT91CAP9_BASE_US1 0xfff90000
67#define AT91CAP9_BASE_US2 0xfff94000
68#define AT91CAP9_BASE_SSC0 0xfff98000
69#define AT91CAP9_BASE_SSC1 0xfff9c000
70#define AT91CAP9_BASE_AC97C 0xfffa0000
71#define AT91CAP9_BASE_SPI0 0xfffa4000
72#define AT91CAP9_BASE_SPI1 0xfffa8000
73#define AT91CAP9_BASE_CAN 0xfffac000
74#define AT91CAP9_BASE_PWMC 0xfffb8000
75#define AT91CAP9_BASE_EMAC 0xfffbc000
76#define AT91CAP9_BASE_ADC 0xfffc0000
77#define AT91CAP9_BASE_ISI 0xfffc4000
78
79/*
80 * System Peripherals (offset from AT91_BASE_SYS)
81 */
82#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS)
83#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
84#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
85#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
86#define AT91_GPBR (cpu_is_at91cap9_revB() ? \
87 (0xfffffd50 - AT91_BASE_SYS) : \
88 (0xfffffd60 - AT91_BASE_SYS))
89
90#define AT91CAP9_BASE_ECC 0xffffe200
91#define AT91CAP9_BASE_DMA 0xffffec00
92#define AT91CAP9_BASE_SMC 0xffffe800
93#define AT91CAP9_BASE_DBGU AT91_BASE_DBGU1
94#define AT91CAP9_BASE_PIOA 0xfffff200
95#define AT91CAP9_BASE_PIOB 0xfffff400
96#define AT91CAP9_BASE_PIOC 0xfffff600
97#define AT91CAP9_BASE_PIOD 0xfffff800
98#define AT91CAP9_BASE_RSTC 0xfffffd00
99#define AT91CAP9_BASE_SHDWC 0xfffffd10
100#define AT91CAP9_BASE_RTT 0xfffffd20
101#define AT91CAP9_BASE_PIT 0xfffffd30
102#define AT91CAP9_BASE_WDT 0xfffffd40
103
104#define AT91_USART0 AT91CAP9_BASE_US0
105#define AT91_USART1 AT91CAP9_BASE_US1
106#define AT91_USART2 AT91CAP9_BASE_US2
107
108
109/*
110 * Internal Memory.
111 */
112#define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */
113#define AT91CAP9_SRAM_SIZE (32 * SZ_1K) /* Internal SRAM size (32Kb) */
114
115#define AT91CAP9_ROM_BASE 0x00400000 /* Internal ROM base address */
116#define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */
117
118#define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */
119#define AT91CAP9_UDPHS_FIFO 0x00600000 /* USB High Speed Device Port */
120#define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */
121
122#endif
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_matrix.h b/arch/arm/mach-at91/include/mach/at91cap9_matrix.h
deleted file mode 100644
index 4b9d4aff4b4f..000000000000
--- a/arch/arm/mach-at91/include/mach/at91cap9_matrix.h
+++ /dev/null
@@ -1,137 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91cap9_matrix.h
3 *
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2006 Atmel Corporation.
7 *
8 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
9 * Based on AT91CAP9 datasheet revision B (Preliminary).
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#ifndef AT91CAP9_MATRIX_H
18#define AT91CAP9_MATRIX_H
19
20#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
21#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
22#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
23#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
24#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
25#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
26#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
27#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
28#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
29#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */
30#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */
31#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */
32#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
33#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
34#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
35#define AT91_MATRIX_ULBT_FOUR (2 << 0)
36#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
37#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
38
39#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
40#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
41#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
42#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
43#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
44#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
45#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
46#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
47#define AT91_MATRIX_SCFG8 (AT91_MATRIX + 0x60) /* Slave Configuration Register 8 */
48#define AT91_MATRIX_SCFG9 (AT91_MATRIX + 0x64) /* Slave Configuration Register 9 */
49#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
50#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
51#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
52#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
53#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
54#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
55#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
56#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
57#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
58
59#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
60#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
61#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
62#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
63#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
64#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
65#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
66#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
67#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
68#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
69#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
70#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
71#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
72#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
73#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
74#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
75#define AT91_MATRIX_PRAS8 (AT91_MATRIX + 0xC0) /* Priority Register A for Slave 8 */
76#define AT91_MATRIX_PRBS8 (AT91_MATRIX + 0xC4) /* Priority Register B for Slave 8 */
77#define AT91_MATRIX_PRAS9 (AT91_MATRIX + 0xC8) /* Priority Register A for Slave 9 */
78#define AT91_MATRIX_PRBS9 (AT91_MATRIX + 0xCC) /* Priority Register B for Slave 9 */
79#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
80#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
81#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
82#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
83#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
84#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
85#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
86#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
87#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
88#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
89#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
90#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
91
92#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
93#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
94#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
95#define AT91_MATRIX_RCB2 (1 << 2)
96#define AT91_MATRIX_RCB3 (1 << 3)
97#define AT91_MATRIX_RCB4 (1 << 4)
98#define AT91_MATRIX_RCB5 (1 << 5)
99#define AT91_MATRIX_RCB6 (1 << 6)
100#define AT91_MATRIX_RCB7 (1 << 7)
101#define AT91_MATRIX_RCB8 (1 << 8)
102#define AT91_MATRIX_RCB9 (1 << 9)
103#define AT91_MATRIX_RCB10 (1 << 10)
104#define AT91_MATRIX_RCB11 (1 << 11)
105
106#define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */
107#define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */
108
109#define AT91_MATRIX_UDPHS (AT91_MATRIX + 0x118) /* USBHS Special Function Register [AT91CAP9 only] */
110#define AT91_MATRIX_SELECT_UDPHS (0 << 31) /* select High Speed UDP */
111#define AT91_MATRIX_SELECT_UDP (1 << 31) /* select standard UDP */
112#define AT91_MATRIX_UDPHS_BYPASS_LOCK (1 << 30) /* bypass lock bit */
113
114#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
115#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
116#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
117#define AT91_MATRIX_EBI_CS1A_BCRAMC (1 << 1)
118#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
119#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
120#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
121#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
122#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
123#define AT91_MATRIX_EBI_CS4A_SMC_CF1 (1 << 4)
124#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
125#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
126#define AT91_MATRIX_EBI_CS5A_SMC_CF2 (1 << 5)
127#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
128#define AT91_MATRIX_EBI_DQSPDC (1 << 9) /* Data Qualifier Strobe Pull-Down Configuration */
129#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
130#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
131#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
132
133#define AT91_MPBS2_SFR (AT91_MATRIX + 0x12C) /* MPBlock Slave 2 Special Function Register */
134#define AT91_MPBS3_SFR (AT91_MATRIX + 0x130) /* MPBlock Slave 3 Special Function Register */
135#define AT91_APB_SFR (AT91_MATRIX + 0x134) /* APB Bridge Special Function Register */
136
137#endif
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
index bacb51141819..603e6aac2a4f 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
@@ -77,26 +77,22 @@
77 77
78 78
79/* 79/*
80 * System Peripherals (offset from AT91_BASE_SYS) 80 * System Peripherals
81 */ 81 */
82#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */
83#define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */
84#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */
85
86#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */ 82#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */
87#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */ 83#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */
88#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */ 84#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */
89#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */ 85#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */
90#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */ 86#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */
87#define AT91RM9200_BASE_ST 0xfffffd00 /* System Timer */
91#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */ 88#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */
89#define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */
92 90
93#define AT91_USART0 AT91RM9200_BASE_US0 91#define AT91_USART0 AT91RM9200_BASE_US0
94#define AT91_USART1 AT91RM9200_BASE_US1 92#define AT91_USART1 AT91RM9200_BASE_US1
95#define AT91_USART2 AT91RM9200_BASE_US2 93#define AT91_USART2 AT91RM9200_BASE_US2
96#define AT91_USART3 AT91RM9200_BASE_US3 94#define AT91_USART3 AT91RM9200_BASE_US3
97 95
98#define AT91_MATRIX 0 /* not supported */
99
100/* 96/*
101 * Internal Memory. 97 * Internal Memory.
102 */ 98 */
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
index d34e4ed89349..aeaadfb452af 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
@@ -17,10 +17,10 @@
17#define AT91RM9200_MC_H 17#define AT91RM9200_MC_H
18 18
19/* Memory Controller */ 19/* Memory Controller */
20#define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */ 20#define AT91_MC_RCR 0x00 /* MC Remap Control Register */
21#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */ 21#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
22 22
23#define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */ 23#define AT91_MC_ASR 0x04 /* MC Abort Status Register */
24#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */ 24#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
25#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */ 25#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
26#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */ 26#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
@@ -40,16 +40,16 @@
40#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */ 40#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
41#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */ 41#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
42 42
43#define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */ 43#define AT91_MC_AASR 0x08 /* MC Abort Address Status Register */
44 44
45#define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */ 45#define AT91_MC_MPR 0x0c /* MC Master Priority Register */
46#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */ 46#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
47#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */ 47#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
48#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */ 48#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
49#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */ 49#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
50 50
51/* External Bus Interface (EBI) registers */ 51/* External Bus Interface (EBI) registers */
52#define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */ 52#define AT91_EBI_CSA 0x60 /* Chip Select Assignment Register */
53#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */ 53#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
54#define AT91_EBI_CS0A_SMC (0 << 0) 54#define AT91_EBI_CS0A_SMC (0 << 0)
55#define AT91_EBI_CS0A_BFC (1 << 0) 55#define AT91_EBI_CS0A_BFC (1 << 0)
@@ -66,7 +66,7 @@
66#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */ 66#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
67 67
68/* Static Memory Controller (SMC) registers */ 68/* Static Memory Controller (SMC) registers */
69#define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */ 69#define AT91_SMC_CSR(n) (0x70 + ((n) * 4)) /* SMC Chip Select Register */
70#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */ 70#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
71#define AT91_SMC_NWS_(x) ((x) << 0) 71#define AT91_SMC_NWS_(x) ((x) << 0)
72#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */ 72#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
@@ -87,52 +87,8 @@
87#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */ 87#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
88#define AT91_SMC_RWHOLD_(x) ((x) << 28) 88#define AT91_SMC_RWHOLD_(x) ((x) << 28)
89 89
90/* SDRAM Controller registers */
91#define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */
92#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
93#define AT91_SDRAMC_MODE_NORMAL (0 << 0)
94#define AT91_SDRAMC_MODE_NOP (1 << 0)
95#define AT91_SDRAMC_MODE_PRECHARGE (2 << 0)
96#define AT91_SDRAMC_MODE_LMR (3 << 0)
97#define AT91_SDRAMC_MODE_REFRESH (4 << 0)
98#define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */
99#define AT91_SDRAMC_DBW_32 (0 << 4)
100#define AT91_SDRAMC_DBW_16 (1 << 4)
101
102#define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */
103#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
104
105#define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */
106#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
107#define AT91_SDRAMC_NC_8 (0 << 0)
108#define AT91_SDRAMC_NC_9 (1 << 0)
109#define AT91_SDRAMC_NC_10 (2 << 0)
110#define AT91_SDRAMC_NC_11 (3 << 0)
111#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
112#define AT91_SDRAMC_NR_11 (0 << 2)
113#define AT91_SDRAMC_NR_12 (1 << 2)
114#define AT91_SDRAMC_NR_13 (2 << 2)
115#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
116#define AT91_SDRAMC_NB_2 (0 << 4)
117#define AT91_SDRAMC_NB_4 (1 << 4)
118#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
119#define AT91_SDRAMC_CAS_2 (2 << 5)
120#define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
121#define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
122#define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
123#define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
124#define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
125#define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
126
127#define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */
128#define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */
129#define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */
130#define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */
131#define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */
132#define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */
133
134/* Burst Flash Controller register */ 90/* Burst Flash Controller register */
135#define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */ 91#define AT91_BFC_MR 0xc0 /* Mode Register */
136#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */ 92#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
137#define AT91_BFC_BFCOM_DISABLED (0 << 0) 93#define AT91_BFC_BFCOM_DISABLED (0 << 0)
138#define AT91_BFC_BFCOM_ASYNC (1 << 0) 94#define AT91_BFC_BFCOM_ASYNC (1 << 0)
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h b/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
new file mode 100644
index 000000000000..aa047f458f1b
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
@@ -0,0 +1,63 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Memory Controllers (SDRAMC only) - System peripherals registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91RM9200_SDRAMC_H
17#define AT91RM9200_SDRAMC_H
18
19/* SDRAM Controller registers */
20#define AT91RM9200_SDRAMC_MR 0x90 /* Mode Register */
21#define AT91RM9200_SDRAMC_MODE (0xf << 0) /* Command Mode */
22#define AT91RM9200_SDRAMC_MODE_NORMAL (0 << 0)
23#define AT91RM9200_SDRAMC_MODE_NOP (1 << 0)
24#define AT91RM9200_SDRAMC_MODE_PRECHARGE (2 << 0)
25#define AT91RM9200_SDRAMC_MODE_LMR (3 << 0)
26#define AT91RM9200_SDRAMC_MODE_REFRESH (4 << 0)
27#define AT91RM9200_SDRAMC_DBW (1 << 4) /* Data Bus Width */
28#define AT91RM9200_SDRAMC_DBW_32 (0 << 4)
29#define AT91RM9200_SDRAMC_DBW_16 (1 << 4)
30
31#define AT91RM9200_SDRAMC_TR 0x94 /* Refresh Timer Register */
32#define AT91RM9200_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
33
34#define AT91RM9200_SDRAMC_CR 0x98 /* Configuration Register */
35#define AT91RM9200_SDRAMC_NC (3 << 0) /* Number of Column Bits */
36#define AT91RM9200_SDRAMC_NC_8 (0 << 0)
37#define AT91RM9200_SDRAMC_NC_9 (1 << 0)
38#define AT91RM9200_SDRAMC_NC_10 (2 << 0)
39#define AT91RM9200_SDRAMC_NC_11 (3 << 0)
40#define AT91RM9200_SDRAMC_NR (3 << 2) /* Number of Row Bits */
41#define AT91RM9200_SDRAMC_NR_11 (0 << 2)
42#define AT91RM9200_SDRAMC_NR_12 (1 << 2)
43#define AT91RM9200_SDRAMC_NR_13 (2 << 2)
44#define AT91RM9200_SDRAMC_NB (1 << 4) /* Number of Banks */
45#define AT91RM9200_SDRAMC_NB_2 (0 << 4)
46#define AT91RM9200_SDRAMC_NB_4 (1 << 4)
47#define AT91RM9200_SDRAMC_CAS (3 << 5) /* CAS Latency */
48#define AT91RM9200_SDRAMC_CAS_2 (2 << 5)
49#define AT91RM9200_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
50#define AT91RM9200_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
51#define AT91RM9200_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
52#define AT91RM9200_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
53#define AT91RM9200_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
54#define AT91RM9200_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
55
56#define AT91RM9200_SDRAMC_SRR 0x9c /* Self Refresh Register */
57#define AT91RM9200_SDRAMC_LPR 0xa0 /* Low Power Register */
58#define AT91RM9200_SDRAMC_IER 0xa4 /* Interrupt Enable Register */
59#define AT91RM9200_SDRAMC_IDR 0xa8 /* Interrupt Disable Register */
60#define AT91RM9200_SDRAMC_IMR 0xac /* Interrupt Mask Register */
61#define AT91RM9200_SDRAMC_ISR 0xb0 /* Interrupt Status Register */
62
63#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index fa5ca278adeb..08ae9afd00fe 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -78,15 +78,12 @@
78#define AT91SAM9260_BASE_ADC 0xfffe0000 78#define AT91SAM9260_BASE_ADC 0xfffe0000
79 79
80/* 80/*
81 * System Peripherals (offset from AT91_BASE_SYS) 81 * System Peripherals
82 */ 82 */
83#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
84#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
85#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
86#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
87
88#define AT91SAM9260_BASE_ECC 0xffffe800 83#define AT91SAM9260_BASE_ECC 0xffffe800
84#define AT91SAM9260_BASE_SDRAMC 0xffffea00
89#define AT91SAM9260_BASE_SMC 0xffffec00 85#define AT91SAM9260_BASE_SMC 0xffffec00
86#define AT91SAM9260_BASE_MATRIX 0xffffee00
90#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0 87#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0
91#define AT91SAM9260_BASE_PIOA 0xfffff400 88#define AT91SAM9260_BASE_PIOA 0xfffff400
92#define AT91SAM9260_BASE_PIOB 0xfffff600 89#define AT91SAM9260_BASE_PIOB 0xfffff600
@@ -96,6 +93,7 @@
96#define AT91SAM9260_BASE_RTT 0xfffffd20 93#define AT91SAM9260_BASE_RTT 0xfffffd20
97#define AT91SAM9260_BASE_PIT 0xfffffd30 94#define AT91SAM9260_BASE_PIT 0xfffffd30
98#define AT91SAM9260_BASE_WDT 0xfffffd40 95#define AT91SAM9260_BASE_WDT 0xfffffd40
96#define AT91SAM9260_BASE_GPBR 0xfffffd50
99 97
100#define AT91_USART0 AT91SAM9260_BASE_US0 98#define AT91_USART0 AT91SAM9260_BASE_US0
101#define AT91_USART1 AT91SAM9260_BASE_US1 99#define AT91_USART1 AT91SAM9260_BASE_US1
@@ -115,6 +113,8 @@
115#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */ 113#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */
116#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ 114#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
117#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */ 115#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */
116#define AT91SAM9260_SRAM_BASE 0x002FF000 /* Internal SRAM base address */
117#define AT91SAM9260_SRAM_SIZE SZ_8K /* Internal SRAM size (8Kb) */
118 118
119#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */ 119#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */
120 120
@@ -128,6 +128,8 @@
128#define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */ 128#define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */
129#define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ 129#define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
130#define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ 130#define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
131#define AT91SAM9G20_SRAM_BASE 0x002FC000 /* Internal SRAM base address */
132#define AT91SAM9G20_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
131 133
132#define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */ 134#define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */
133 135
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
index 020f02ed921a..f459df420629 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
@@ -15,12 +15,12 @@
15#ifndef AT91SAM9260_MATRIX_H 15#ifndef AT91SAM9260_MATRIX_H
16#define AT91SAM9260_MATRIX_H 16#define AT91SAM9260_MATRIX_H
17 17
18#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ 18#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
19#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ 19#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
20#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ 20#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
21#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ 21#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
22#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ 22#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
23#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ 23#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
24#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ 24#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
25#define AT91_MATRIX_ULBT_INFINITE (0 << 0) 25#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
26#define AT91_MATRIX_ULBT_SINGLE (1 << 0) 26#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
@@ -28,11 +28,11 @@
28#define AT91_MATRIX_ULBT_EIGHT (3 << 0) 28#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
29#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) 29#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
30 30
31#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ 31#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
32#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ 32#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
33#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ 33#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
34#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ 34#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
35#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ 35#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
36#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ 36#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
37#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ 37#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
38#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 38#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
@@ -43,11 +43,11 @@
43#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) 43#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
44#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) 44#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
45 45
46#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ 46#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
47#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ 47#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
48#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ 48#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
49#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ 49#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
50#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ 50#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
51#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ 51#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
52#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ 52#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
53#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ 53#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
@@ -55,11 +55,11 @@
55#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ 55#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
56#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ 56#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
57 57
58#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ 58#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
59#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 59#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
60#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 60#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
61 61
62#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */ 62#define AT91_MATRIX_EBICSA 0x11C /* EBI Chip Select Assignment Register */
63#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ 63#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
64#define AT91_MATRIX_CS1A_SMC (0 << 1) 64#define AT91_MATRIX_CS1A_SMC (0 << 1)
65#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) 65#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 7cde2d36570e..44fbdc12ee62 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -63,14 +63,11 @@
63 63
64 64
65/* 65/*
66 * System Peripherals (offset from AT91_BASE_SYS) 66 * System Peripherals
67 */ 67 */
68#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
69#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
70#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
71#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
72
73#define AT91SAM9261_BASE_SMC 0xffffec00 68#define AT91SAM9261_BASE_SMC 0xffffec00
69#define AT91SAM9261_BASE_MATRIX 0xffffee00
70#define AT91SAM9261_BASE_SDRAMC 0xffffea00
74#define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0 71#define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0
75#define AT91SAM9261_BASE_PIOA 0xfffff400 72#define AT91SAM9261_BASE_PIOA 0xfffff400
76#define AT91SAM9261_BASE_PIOB 0xfffff600 73#define AT91SAM9261_BASE_PIOB 0xfffff600
@@ -80,6 +77,7 @@
80#define AT91SAM9261_BASE_RTT 0xfffffd20 77#define AT91SAM9261_BASE_RTT 0xfffffd20
81#define AT91SAM9261_BASE_PIT 0xfffffd30 78#define AT91SAM9261_BASE_PIT 0xfffffd30
82#define AT91SAM9261_BASE_WDT 0xfffffd40 79#define AT91SAM9261_BASE_WDT 0xfffffd40
80#define AT91SAM9261_BASE_GPBR 0xfffffd50
83 81
84#define AT91_USART0 AT91SAM9261_BASE_US0 82#define AT91_USART0 AT91SAM9261_BASE_US0
85#define AT91_USART1 AT91SAM9261_BASE_US1 83#define AT91_USART1 AT91SAM9261_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
index 69c6501915d9..a50cdf8b8ca4 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
@@ -15,15 +15,15 @@
15#ifndef AT91SAM9261_MATRIX_H 15#ifndef AT91SAM9261_MATRIX_H
16#define AT91SAM9261_MATRIX_H 16#define AT91SAM9261_MATRIX_H
17 17
18#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */ 18#define AT91_MATRIX_MCFG 0x00 /* Master Configuration Register */
19#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 19#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
20#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 20#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
21 21
22#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */ 22#define AT91_MATRIX_SCFG0 0x04 /* Slave Configuration Register 0 */
23#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */ 23#define AT91_MATRIX_SCFG1 0x08 /* Slave Configuration Register 1 */
24#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */ 24#define AT91_MATRIX_SCFG2 0x0C /* Slave Configuration Register 2 */
25#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */ 25#define AT91_MATRIX_SCFG3 0x10 /* Slave Configuration Register 3 */
26#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */ 26#define AT91_MATRIX_SCFG4 0x14 /* Slave Configuration Register 4 */
27#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ 27#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
28#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ 28#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
29#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 29#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
@@ -31,7 +31,7 @@
31#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) 31#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
32#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ 32#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
33 33
34#define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */ 34#define AT91_MATRIX_TCR 0x24 /* TCM Configuration Register */
35#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ 35#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
36#define AT91_MATRIX_ITCM_0 (0 << 0) 36#define AT91_MATRIX_ITCM_0 (0 << 0)
37#define AT91_MATRIX_ITCM_16 (5 << 0) 37#define AT91_MATRIX_ITCM_16 (5 << 0)
@@ -43,7 +43,7 @@
43#define AT91_MATRIX_DTCM_32 (6 << 4) 43#define AT91_MATRIX_DTCM_32 (6 << 4)
44#define AT91_MATRIX_DTCM_64 (7 << 4) 44#define AT91_MATRIX_DTCM_64 (7 << 4)
45 45
46#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */ 46#define AT91_MATRIX_EBICSA 0x30 /* EBI Chip Select Assignment Register */
47#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ 47#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
48#define AT91_MATRIX_CS1A_SMC (0 << 1) 48#define AT91_MATRIX_CS1A_SMC (0 << 1)
49#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) 49#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
@@ -58,7 +58,7 @@
58#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) 58#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
59#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ 59#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
60 60
61#define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */ 61#define AT91_MATRIX_USBPUCR 0x34 /* USB Pad Pull-Up Control Register */
62#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */ 62#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */
63 63
64#endif 64#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index 5949abda962b..d96cbb2e03c4 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -72,18 +72,15 @@
72#define AT91SAM9263_BASE_2DGE 0xfffc8000 72#define AT91SAM9263_BASE_2DGE 0xfffc8000
73 73
74/* 74/*
75 * System Peripherals (offset from AT91_BASE_SYS) 75 * System Peripherals
76 */ 76 */
77#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS)
78#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
79#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
80#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
81#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
82
83#define AT91SAM9263_BASE_ECC0 0xffffe000 77#define AT91SAM9263_BASE_ECC0 0xffffe000
78#define AT91SAM9263_BASE_SDRAMC0 0xffffe200
84#define AT91SAM9263_BASE_SMC0 0xffffe400 79#define AT91SAM9263_BASE_SMC0 0xffffe400
85#define AT91SAM9263_BASE_ECC1 0xffffe600 80#define AT91SAM9263_BASE_ECC1 0xffffe600
81#define AT91SAM9263_BASE_SDRAMC1 0xffffe800
86#define AT91SAM9263_BASE_SMC1 0xffffea00 82#define AT91SAM9263_BASE_SMC1 0xffffea00
83#define AT91SAM9263_BASE_MATRIX 0xffffec00
87#define AT91SAM9263_BASE_DBGU AT91_BASE_DBGU1 84#define AT91SAM9263_BASE_DBGU AT91_BASE_DBGU1
88#define AT91SAM9263_BASE_PIOA 0xfffff200 85#define AT91SAM9263_BASE_PIOA 0xfffff200
89#define AT91SAM9263_BASE_PIOB 0xfffff400 86#define AT91SAM9263_BASE_PIOB 0xfffff400
@@ -96,6 +93,7 @@
96#define AT91SAM9263_BASE_PIT 0xfffffd30 93#define AT91SAM9263_BASE_PIT 0xfffffd30
97#define AT91SAM9263_BASE_WDT 0xfffffd40 94#define AT91SAM9263_BASE_WDT 0xfffffd40
98#define AT91SAM9263_BASE_RTT1 0xfffffd50 95#define AT91SAM9263_BASE_RTT1 0xfffffd50
96#define AT91SAM9263_BASE_GPBR 0xfffffd60
99 97
100#define AT91_USART0 AT91SAM9263_BASE_US0 98#define AT91_USART0 AT91SAM9263_BASE_US0
101#define AT91_USART1 AT91SAM9263_BASE_US1 99#define AT91_USART1 AT91SAM9263_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
index 9b3efd3eb2f3..ebb5fdb565e0 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
@@ -15,15 +15,15 @@
15#ifndef AT91SAM9263_MATRIX_H 15#ifndef AT91SAM9263_MATRIX_H
16#define AT91SAM9263_MATRIX_H 16#define AT91SAM9263_MATRIX_H
17 17
18#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ 18#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
19#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ 19#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
20#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ 20#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
21#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ 21#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
22#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ 22#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
23#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ 23#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
24#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ 24#define AT91_MATRIX_MCFG6 0x18 /* Master Configuration Register 6 */
25#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ 25#define AT91_MATRIX_MCFG7 0x1C /* Master Configuration Register 7 */
26#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ 26#define AT91_MATRIX_MCFG8 0x20 /* Master Configuration Register 8 */
27#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ 27#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
28#define AT91_MATRIX_ULBT_INFINITE (0 << 0) 28#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
29#define AT91_MATRIX_ULBT_SINGLE (1 << 0) 29#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
@@ -31,14 +31,14 @@
31#define AT91_MATRIX_ULBT_EIGHT (3 << 0) 31#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
32#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) 32#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
33 33
34#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ 34#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
35#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ 35#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
36#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ 36#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
37#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ 37#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
38#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ 38#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
39#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ 39#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
40#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ 40#define AT91_MATRIX_SCFG6 0x58 /* Slave Configuration Register 6 */
41#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ 41#define AT91_MATRIX_SCFG7 0x5C /* Slave Configuration Register 7 */
42#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ 42#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
43#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ 43#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
44#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 44#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
@@ -49,22 +49,22 @@
49#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) 49#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
50#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) 50#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
51 51
52#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ 52#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
53#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ 53#define AT91_MATRIX_PRBS0 0x84 /* Priority Register B for Slave 0 */
54#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ 54#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
55#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ 55#define AT91_MATRIX_PRBS1 0x8C /* Priority Register B for Slave 1 */
56#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ 56#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
57#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ 57#define AT91_MATRIX_PRBS2 0x94 /* Priority Register B for Slave 2 */
58#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ 58#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
59#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ 59#define AT91_MATRIX_PRBS3 0x9C /* Priority Register B for Slave 3 */
60#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ 60#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
61#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ 61#define AT91_MATRIX_PRBS4 0xA4 /* Priority Register B for Slave 4 */
62#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ 62#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
63#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ 63#define AT91_MATRIX_PRBS5 0xAC /* Priority Register B for Slave 5 */
64#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ 64#define AT91_MATRIX_PRAS6 0xB0 /* Priority Register A for Slave 6 */
65#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ 65#define AT91_MATRIX_PRBS6 0xB4 /* Priority Register B for Slave 6 */
66#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ 66#define AT91_MATRIX_PRAS7 0xB8 /* Priority Register A for Slave 7 */
67#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ 67#define AT91_MATRIX_PRBS7 0xBC /* Priority Register B for Slave 7 */
68#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ 68#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
69#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ 69#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
70#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ 70#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
@@ -75,7 +75,7 @@
75#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ 75#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
76#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ 76#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
77 77
78#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ 78#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
79#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 79#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
80#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 80#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
81#define AT91_MATRIX_RCB2 (1 << 2) 81#define AT91_MATRIX_RCB2 (1 << 2)
@@ -86,7 +86,7 @@
86#define AT91_MATRIX_RCB7 (1 << 7) 86#define AT91_MATRIX_RCB7 (1 << 7)
87#define AT91_MATRIX_RCB8 (1 << 8) 87#define AT91_MATRIX_RCB8 (1 << 8)
88 88
89#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ 89#define AT91_MATRIX_TCMR 0x114 /* TCM Configuration Register */
90#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ 90#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
91#define AT91_MATRIX_ITCM_0 (0 << 0) 91#define AT91_MATRIX_ITCM_0 (0 << 0)
92#define AT91_MATRIX_ITCM_16 (5 << 0) 92#define AT91_MATRIX_ITCM_16 (5 << 0)
@@ -96,7 +96,7 @@
96#define AT91_MATRIX_DTCM_16 (5 << 4) 96#define AT91_MATRIX_DTCM_16 (5 << 4)
97#define AT91_MATRIX_DTCM_32 (6 << 4) 97#define AT91_MATRIX_DTCM_32 (6 << 4)
98 98
99#define AT91_MATRIX_EBI0CSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ 99#define AT91_MATRIX_EBI0CSA 0x120 /* EBI0 Chip Select Assignment Register */
100#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */ 100#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */
101#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1) 101#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1)
102#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1) 102#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1)
@@ -114,7 +114,7 @@
114#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16) 114#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16)
115#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16) 115#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16)
116 116
117#define AT91_MATRIX_EBI1CSA (AT91_MATRIX + 0x124) /* EBI1 Chip Select Assignment Register */ 117#define AT91_MATRIX_EBI1CSA 0x124 /* EBI1 Chip Select Assignment Register */
118#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */ 118#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */
119#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1) 119#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1)
120#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1) 120#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
index e2f8da8ce5bc..0210797abf2e 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -59,7 +59,6 @@
59#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ 59#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
60#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ 60#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
61#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */ 61#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
62#define AT91CAP9_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
63#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */ 62#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
64#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ 63#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
65 64
@@ -76,7 +75,6 @@
76#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */ 75#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */
77 76
78#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */ 77#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
79#define AT91CAP9_DDRSDRC_LPR 0x18 /* Low Power Register */
80#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ 78#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
81#define AT91_DDRSDRC_LPCB_DISABLE 0 79#define AT91_DDRSDRC_LPCB_DISABLE 0
82#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 80#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
@@ -94,11 +92,9 @@
94#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */ 92#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
95 93
96#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */ 94#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
97#define AT91CAP9_DDRSDRC_MDR 0x1C /* Memory Device Register */
98#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ 95#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
99#define AT91_DDRSDRC_MD_SDR 0 96#define AT91_DDRSDRC_MD_SDR 0
100#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 97#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
101#define AT91CAP9_DDRSDRC_MD_DDR 2
102#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 98#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
103#define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */ 99#define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */
104#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */ 100#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
@@ -106,16 +102,10 @@
106#define AT91_DDRSDRC_DBW_16BITS (1 << 4) 102#define AT91_DDRSDRC_DBW_16BITS (1 << 4)
107 103
108#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */ 104#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */
109#define AT91CAP9_DDRSDRC_DLL 0x20 /* DLL Information Register */
110#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ 105#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
111#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ 106#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
112#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ 107#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
113#define AT91CAP9_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */
114#define AT91CAP9_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */
115#define AT91CAP9_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */
116#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ 108#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
117#define AT91CAP9_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
118#define AT91CAP9_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
119 109
120#define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */ 110#define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */
121#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */ 111#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */
@@ -131,10 +121,4 @@
131#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */ 121#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */
132#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */ 122#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */
133 123
134/* Register access macros */
135#define at91_ramc_read(num, reg) \
136 at91_sys_read(AT91_DDRSDRC##num + reg)
137#define at91_ramc_write(num, reg, value) \
138 at91_sys_write(AT91_DDRSDRC##num + reg, value)
139
140#endif 124#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
index 100f5a592926..3d085a9a7450 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
@@ -82,10 +82,4 @@
82#define AT91_SDRAMC_MD_SDRAM 0 82#define AT91_SDRAMC_MD_SDRAM 0
83#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 83#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
84 84
85/* Register access macros */
86#define at91_ramc_read(num, reg) \
87 at91_sys_read(AT91_SDRAMC##num + reg)
88#define at91_ramc_write(num, reg, value) \
89 at91_sys_write(AT91_SDRAMC##num + reg, value)
90
91#endif 85#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index dd9c95ea0862..d052abcff852 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -84,17 +84,14 @@
84#define AT91SAM9G45_BASE_TC5 0xfffd4080 84#define AT91SAM9G45_BASE_TC5 0xfffd4080
85 85
86/* 86/*
87 * System Peripherals (offset from AT91_BASE_SYS) 87 * System Peripherals
88 */ 88 */
89#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS)
90#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
91#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
92#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
93#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
94
95#define AT91SAM9G45_BASE_ECC 0xffffe200 89#define AT91SAM9G45_BASE_ECC 0xffffe200
90#define AT91SAM9G45_BASE_DDRSDRC1 0xffffe400
91#define AT91SAM9G45_BASE_DDRSDRC0 0xffffe600
96#define AT91SAM9G45_BASE_DMA 0xffffec00 92#define AT91SAM9G45_BASE_DMA 0xffffec00
97#define AT91SAM9G45_BASE_SMC 0xffffe800 93#define AT91SAM9G45_BASE_SMC 0xffffe800
94#define AT91SAM9G45_BASE_MATRIX 0xffffea00
98#define AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1 95#define AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1
99#define AT91SAM9G45_BASE_PIOA 0xfffff200 96#define AT91SAM9G45_BASE_PIOA 0xfffff200
100#define AT91SAM9G45_BASE_PIOB 0xfffff400 97#define AT91SAM9G45_BASE_PIOB 0xfffff400
@@ -107,6 +104,7 @@
107#define AT91SAM9G45_BASE_PIT 0xfffffd30 104#define AT91SAM9G45_BASE_PIT 0xfffffd30
108#define AT91SAM9G45_BASE_WDT 0xfffffd40 105#define AT91SAM9G45_BASE_WDT 0xfffffd40
109#define AT91SAM9G45_BASE_RTC 0xfffffdb0 106#define AT91SAM9G45_BASE_RTC 0xfffffdb0
107#define AT91SAM9G45_BASE_GPBR 0xfffffd60
110 108
111#define AT91_USART0 AT91SAM9G45_BASE_US0 109#define AT91_USART0 AT91SAM9G45_BASE_US0
112#define AT91_USART1 AT91SAM9G45_BASE_US1 110#define AT91_USART1 AT91SAM9G45_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
index c972d60e0aeb..b76e2ed2fbc2 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
@@ -15,18 +15,18 @@
15#ifndef AT91SAM9G45_MATRIX_H 15#ifndef AT91SAM9G45_MATRIX_H
16#define AT91SAM9G45_MATRIX_H 16#define AT91SAM9G45_MATRIX_H
17 17
18#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ 18#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
19#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ 19#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
20#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ 20#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
21#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ 21#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
22#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ 22#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
23#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ 23#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
24#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ 24#define AT91_MATRIX_MCFG6 0x18 /* Master Configuration Register 6 */
25#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ 25#define AT91_MATRIX_MCFG7 0x1C /* Master Configuration Register 7 */
26#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ 26#define AT91_MATRIX_MCFG8 0x20 /* Master Configuration Register 8 */
27#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */ 27#define AT91_MATRIX_MCFG9 0x24 /* Master Configuration Register 9 */
28#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */ 28#define AT91_MATRIX_MCFG10 0x28 /* Master Configuration Register 10 */
29#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */ 29#define AT91_MATRIX_MCFG11 0x2C /* Master Configuration Register 11 */
30#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ 30#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
31#define AT91_MATRIX_ULBT_INFINITE (0 << 0) 31#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
32#define AT91_MATRIX_ULBT_SINGLE (1 << 0) 32#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
@@ -37,14 +37,14 @@
37#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) 37#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
38#define AT91_MATRIX_ULBT_128 (7 << 0) 38#define AT91_MATRIX_ULBT_128 (7 << 0)
39 39
40#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ 40#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
41#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ 41#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
42#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ 42#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
43#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ 43#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
44#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ 44#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
45#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ 45#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
46#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ 46#define AT91_MATRIX_SCFG6 0x58 /* Slave Configuration Register 6 */
47#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ 47#define AT91_MATRIX_SCFG7 0x5C /* Slave Configuration Register 7 */
48#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */ 48#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
49#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ 49#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
50#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 50#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
@@ -52,22 +52,22 @@
52#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) 52#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
53#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ 53#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
54 54
55#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ 55#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
56#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ 56#define AT91_MATRIX_PRBS0 0x84 /* Priority Register B for Slave 0 */
57#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ 57#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
58#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ 58#define AT91_MATRIX_PRBS1 0x8C /* Priority Register B for Slave 1 */
59#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ 59#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
60#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ 60#define AT91_MATRIX_PRBS2 0x94 /* Priority Register B for Slave 2 */
61#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ 61#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
62#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ 62#define AT91_MATRIX_PRBS3 0x9C /* Priority Register B for Slave 3 */
63#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ 63#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
64#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ 64#define AT91_MATRIX_PRBS4 0xA4 /* Priority Register B for Slave 4 */
65#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ 65#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
66#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ 66#define AT91_MATRIX_PRBS5 0xAC /* Priority Register B for Slave 5 */
67#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ 67#define AT91_MATRIX_PRAS6 0xB0 /* Priority Register A for Slave 6 */
68#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ 68#define AT91_MATRIX_PRBS6 0xB4 /* Priority Register B for Slave 6 */
69#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ 69#define AT91_MATRIX_PRAS7 0xB8 /* Priority Register A for Slave 7 */
70#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ 70#define AT91_MATRIX_PRBS7 0xBC /* Priority Register B for Slave 7 */
71#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ 71#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
72#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ 72#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
73#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ 73#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
@@ -81,7 +81,7 @@
81#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */ 81#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
82#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */ 82#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
83 83
84#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ 84#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
85#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 85#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
86#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 86#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
87#define AT91_MATRIX_RCB2 (1 << 2) 87#define AT91_MATRIX_RCB2 (1 << 2)
@@ -95,7 +95,7 @@
95#define AT91_MATRIX_RCB10 (1 << 10) 95#define AT91_MATRIX_RCB10 (1 << 10)
96#define AT91_MATRIX_RCB11 (1 << 11) 96#define AT91_MATRIX_RCB11 (1 << 11)
97 97
98#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x110) /* TCM Configuration Register */ 98#define AT91_MATRIX_TCMR 0x110 /* TCM Configuration Register */
99#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ 99#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
100#define AT91_MATRIX_ITCM_0 (0 << 0) 100#define AT91_MATRIX_ITCM_0 (0 << 0)
101#define AT91_MATRIX_ITCM_32 (6 << 0) 101#define AT91_MATRIX_ITCM_32 (6 << 0)
@@ -107,12 +107,12 @@
107#define AT91_MATRIX_TCM_NO_WS (0x0 << 11) 107#define AT91_MATRIX_TCM_NO_WS (0x0 << 11)
108#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11) 108#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11)
109 109
110#define AT91_MATRIX_VIDEO (AT91_MATRIX + 0x118) /* Video Mode Configuration Register */ 110#define AT91_MATRIX_VIDEO 0x118 /* Video Mode Configuration Register */
111#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */ 111#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */
112#define AT91C_VDEC_SEL_OFF (0 << 0) 112#define AT91C_VDEC_SEL_OFF (0 << 0)
113#define AT91C_VDEC_SEL_ON (1 << 0) 113#define AT91C_VDEC_SEL_ON (1 << 0)
114 114
115#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x128) /* EBI Chip Select Assignment Register */ 115#define AT91_MATRIX_EBICSA 0x128 /* EBI Chip Select Assignment Register */
116#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ 116#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
117#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) 117#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
118#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) 118#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
@@ -138,13 +138,13 @@
138#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) 138#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
139#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) 139#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
140 140
141#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */ 141#define AT91_MATRIX_WPMR 0x1E4 /* Write Protect Mode Register */
142#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ 142#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
143#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0) 143#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
144#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0) 144#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
145#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ 145#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
146 146
147#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */ 147#define AT91_MATRIX_WPSR 0x1E8 /* Write Protect Status Register */
148#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ 148#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
149#define AT91_MATRIX_WPSR_NO_WPV (0 << 0) 149#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
150#define AT91_MATRIX_WPSR_WPV (1 << 0) 150#define AT91_MATRIX_WPSR_WPV (1 << 0)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index d7bead7118da..e0073eb10144 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -69,15 +69,13 @@
69/* 69/*
70 * System Peripherals (offset from AT91_BASE_SYS) 70 * System Peripherals (offset from AT91_BASE_SYS)
71 */ 71 */
72#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
73#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
74#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
75#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) 72#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
76#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
77 73
78#define AT91SAM9RL_BASE_DMA 0xffffe600 74#define AT91SAM9RL_BASE_DMA 0xffffe600
79#define AT91SAM9RL_BASE_ECC 0xffffe800 75#define AT91SAM9RL_BASE_ECC 0xffffe800
76#define AT91SAM9RL_BASE_SDRAMC 0xffffea00
80#define AT91SAM9RL_BASE_SMC 0xffffec00 77#define AT91SAM9RL_BASE_SMC 0xffffec00
78#define AT91SAM9RL_BASE_MATRIX 0xffffee00
81#define AT91SAM9RL_BASE_DBGU AT91_BASE_DBGU0 79#define AT91SAM9RL_BASE_DBGU AT91_BASE_DBGU0
82#define AT91SAM9RL_BASE_PIOA 0xfffff400 80#define AT91SAM9RL_BASE_PIOA 0xfffff400
83#define AT91SAM9RL_BASE_PIOB 0xfffff600 81#define AT91SAM9RL_BASE_PIOB 0xfffff600
@@ -88,6 +86,7 @@
88#define AT91SAM9RL_BASE_RTT 0xfffffd20 86#define AT91SAM9RL_BASE_RTT 0xfffffd20
89#define AT91SAM9RL_BASE_PIT 0xfffffd30 87#define AT91SAM9RL_BASE_PIT 0xfffffd30
90#define AT91SAM9RL_BASE_WDT 0xfffffd40 88#define AT91SAM9RL_BASE_WDT 0xfffffd40
89#define AT91SAM9RL_BASE_GPBR 0xfffffd60
91#define AT91SAM9RL_BASE_RTC 0xfffffe00 90#define AT91SAM9RL_BASE_RTC 0xfffffe00
92 91
93#define AT91_USART0 AT91SAM9RL_BASE_US0 92#define AT91_USART0 AT91SAM9RL_BASE_US0
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
index 5f9149071fe5..6d160adadafc 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
@@ -14,12 +14,12 @@
14#ifndef AT91SAM9RL_MATRIX_H 14#ifndef AT91SAM9RL_MATRIX_H
15#define AT91SAM9RL_MATRIX_H 15#define AT91SAM9RL_MATRIX_H
16 16
17#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ 17#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
18#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ 18#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
19#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ 19#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
20#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ 20#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
21#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ 21#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
22#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ 22#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
23#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ 23#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
24#define AT91_MATRIX_ULBT_INFINITE (0 << 0) 24#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
25#define AT91_MATRIX_ULBT_SINGLE (1 << 0) 25#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
@@ -27,12 +27,12 @@
27#define AT91_MATRIX_ULBT_EIGHT (3 << 0) 27#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
28#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) 28#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
29 29
30#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ 30#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
31#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ 31#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
32#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ 32#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
33#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ 33#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
34#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ 34#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
35#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ 35#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
36#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ 36#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
37#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ 37#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
38#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 38#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
@@ -43,12 +43,12 @@
43#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) 43#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
44#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) 44#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
45 45
46#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ 46#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
47#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ 47#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
48#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ 48#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
49#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ 49#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
50#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ 50#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
51#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ 51#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
52#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ 52#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
53#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ 53#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
54#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ 54#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
@@ -56,7 +56,7 @@
56#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ 56#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
57#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ 57#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
58 58
59#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ 59#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
60#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 60#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
61#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 61#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
62#define AT91_MATRIX_RCB2 (1 << 2) 62#define AT91_MATRIX_RCB2 (1 << 2)
@@ -64,7 +64,7 @@
64#define AT91_MATRIX_RCB4 (1 << 4) 64#define AT91_MATRIX_RCB4 (1 << 4)
65#define AT91_MATRIX_RCB5 (1 << 5) 65#define AT91_MATRIX_RCB5 (1 << 5)
66 66
67#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ 67#define AT91_MATRIX_TCMR 0x114 /* TCM Configuration Register */
68#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ 68#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
69#define AT91_MATRIX_ITCM_0 (0 << 0) 69#define AT91_MATRIX_ITCM_0 (0 << 0)
70#define AT91_MATRIX_ITCM_16 (5 << 0) 70#define AT91_MATRIX_ITCM_16 (5 << 0)
@@ -74,7 +74,7 @@
74#define AT91_MATRIX_DTCM_16 (5 << 4) 74#define AT91_MATRIX_DTCM_16 (5 << 4)
75#define AT91_MATRIX_DTCM_32 (6 << 4) 75#define AT91_MATRIX_DTCM_32 (6 << 4)
76 76
77#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ 77#define AT91_MATRIX_EBICSA 0x120 /* EBI0 Chip Select Assignment Register */
78#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ 78#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
79#define AT91_MATRIX_CS1A_SMC (0 << 1) 79#define AT91_MATRIX_CS1A_SMC (0 << 1)
80#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) 80#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
new file mode 100644
index 000000000000..a297a77d88e2
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -0,0 +1,79 @@
1/*
2 * Chip-specific header file for the AT91SAM9x5 family
3 *
4 * Copyright (C) 2009-2012 Atmel Corporation.
5 *
6 * Common definitions.
7 * Based on AT91SAM9x5 datasheet.
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12#ifndef AT91SAM9X5_H
13#define AT91SAM9X5_H
14
15/*
16 * Peripheral identifiers/interrupts.
17 */
18#define AT91SAM9X5_ID_PIOAB 2 /* Parallel I/O Controller A and B */
19#define AT91SAM9X5_ID_PIOCD 3 /* Parallel I/O Controller C and D */
20#define AT91SAM9X5_ID_SMD 4 /* SMD Soft Modem (SMD) */
21#define AT91SAM9X5_ID_USART0 5 /* USART 0 */
22#define AT91SAM9X5_ID_USART1 6 /* USART 1 */
23#define AT91SAM9X5_ID_USART2 7 /* USART 2 */
24#define AT91SAM9X5_ID_USART3 8 /* USART 3 */
25#define AT91SAM9X5_ID_TWI0 9 /* Two-Wire Interface 0 */
26#define AT91SAM9X5_ID_TWI1 10 /* Two-Wire Interface 1 */
27#define AT91SAM9X5_ID_TWI2 11 /* Two-Wire Interface 2 */
28#define AT91SAM9X5_ID_MCI0 12 /* High Speed Multimedia Card Interface 0 */
29#define AT91SAM9X5_ID_SPI0 13 /* Serial Peripheral Interface 0 */
30#define AT91SAM9X5_ID_SPI1 14 /* Serial Peripheral Interface 1 */
31#define AT91SAM9X5_ID_UART0 15 /* UART 0 */
32#define AT91SAM9X5_ID_UART1 16 /* UART 1 */
33#define AT91SAM9X5_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
34#define AT91SAM9X5_ID_PWM 18 /* Pulse Width Modulation Controller */
35#define AT91SAM9X5_ID_ADC 19 /* ADC Controller */
36#define AT91SAM9X5_ID_DMA0 20 /* DMA Controller 0 */
37#define AT91SAM9X5_ID_DMA1 21 /* DMA Controller 1 */
38#define AT91SAM9X5_ID_UHPHS 22 /* USB Host High Speed */
39#define AT91SAM9X5_ID_UDPHS 23 /* USB Device High Speed */
40#define AT91SAM9X5_ID_EMAC0 24 /* Ethernet MAC0 */
41#define AT91SAM9X5_ID_LCDC 25 /* LCD Controller */
42#define AT91SAM9X5_ID_ISI 25 /* Image Sensor Interface */
43#define AT91SAM9X5_ID_MCI1 26 /* High Speed Multimedia Card Interface 1 */
44#define AT91SAM9X5_ID_EMAC1 27 /* Ethernet MAC1 */
45#define AT91SAM9X5_ID_SSC 28 /* Synchronous Serial Controller */
46#define AT91SAM9X5_ID_CAN0 29 /* CAN Controller 0 */
47#define AT91SAM9X5_ID_CAN1 30 /* CAN Controller 1 */
48#define AT91SAM9X5_ID_IRQ0 31 /* Advanced Interrupt Controller */
49
50/*
51 * User Peripheral physical base addresses.
52 */
53#define AT91SAM9X5_BASE_USART0 0xf801c000
54#define AT91SAM9X5_BASE_USART1 0xf8020000
55#define AT91SAM9X5_BASE_USART2 0xf8024000
56
57/*
58 * System Peripherals
59 */
60#define AT91SAM9X5_BASE_DDRSDRC0 0xffffe800
61
62/*
63 * Base addresses for early serial code (uncompress.h)
64 */
65#define AT91_DBGU AT91_BASE_DBGU0
66#define AT91_USART0 AT91SAM9X5_BASE_USART0
67#define AT91_USART1 AT91SAM9X5_BASE_USART1
68#define AT91_USART2 AT91SAM9X5_BASE_USART2
69
70/*
71 * Internal Memory.
72 */
73#define AT91SAM9X5_SRAM_BASE 0x00300000 /* Internal SRAM base address */
74#define AT91SAM9X5_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
75
76#define AT91SAM9X5_ROM_BASE 0x00400000 /* Internal ROM base address */
77#define AT91SAM9X5_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */
78
79#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h
new file mode 100644
index 000000000000..a606d3966470
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h
@@ -0,0 +1,53 @@
1/*
2 * Matrix-centric header file for the AT91SAM9x5 family
3 *
4 * Copyright (C) 2009-2012 Atmel Corporation.
5 *
6 * Only EBI related registers.
7 * Write Protect register definitions may be useful.
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12#ifndef AT91SAM9X5_MATRIX_H
13#define AT91SAM9X5_MATRIX_H
14
15#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
16#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
17#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
18#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
19#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
20#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
21#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
22#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
23#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
24#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
25#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
26#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
27#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
28#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
29#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
30#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
31#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
32#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
33#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
34#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
35#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
36#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
37#define AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */
38#define AT91_MATRIX_MP_OFF (0 << 25)
39#define AT91_MATRIX_MP_ON (1 << 25)
40
41#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
42#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
43#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
44#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
45#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
46
47#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
48#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
49#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
50#define AT91_MATRIX_WPSR_WPV (1 << 0)
51#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
52
53#endif
diff --git a/arch/arm/mach-at91/include/mach/at91x40.h b/arch/arm/mach-at91/include/mach/at91x40.h
index a57829f4fd18..90680217064e 100644
--- a/arch/arm/mach-at91/include/mach/at91x40.h
+++ b/arch/arm/mach-at91/include/mach/at91x40.h
@@ -28,18 +28,18 @@
28#define AT91X40_ID_IRQ2 18 /* External IRQ 2 */ 28#define AT91X40_ID_IRQ2 18 /* External IRQ 2 */
29 29
30/* 30/*
31 * System Peripherals (offset from AT91_BASE_SYS) 31 * System Peripherals
32 */ 32 */
33#define AT91_BASE_SYS 0xffc00000 33#define AT91_BASE_SYS 0xffc00000
34 34
35#define AT91_EBI (0xffe00000 - AT91_BASE_SYS) /* External Bus Interface */ 35#define AT91_EBI 0xffe00000 /* External Bus Interface */
36#define AT91_SF (0xfff00000 - AT91_BASE_SYS) /* Special Function */ 36#define AT91_SF 0xfff00000 /* Special Function */
37#define AT91_USART1 (0xfffcc000 - AT91_BASE_SYS) /* USART 1 */ 37#define AT91_USART1 0xfffcc000 /* USART 1 */
38#define AT91_USART0 (0xfffd0000 - AT91_BASE_SYS) /* USART 0 */ 38#define AT91_USART0 0xfffd0000 /* USART 0 */
39#define AT91_TC (0xfffe0000 - AT91_BASE_SYS) /* Timer Counter */ 39#define AT91_TC 0xfffe0000 /* Timer Counter */
40#define AT91_PIOA (0xffff0000 - AT91_BASE_SYS) /* PIO Controller A */ 40#define AT91_PIOA 0xffff0000 /* PIO Controller A */
41#define AT91_PS (0xffff4000 - AT91_BASE_SYS) /* Power Save */ 41#define AT91_PS 0xffff4000 /* Power Save */
42#define AT91_WD (0xffff8000 - AT91_BASE_SYS) /* Watchdog Timer */ 42#define AT91_WD 0xffff8000 /* Watchdog Timer */
43 43
44/* 44/*
45 * The AT91x40 series doesn't have a debug unit like the other AT91 parts. 45 * The AT91x40 series doesn't have a debug unit like the other AT91 parts.
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index 3b33f07b1e11..dc8d6d4f17cf 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -107,6 +107,8 @@ struct atmel_nand_data {
107 u8 ale; /* address line number connected to ALE */ 107 u8 ale; /* address line number connected to ALE */
108 u8 cle; /* address line number connected to CLE */ 108 u8 cle; /* address line number connected to CLE */
109 u8 bus_width_16; /* buswidth is 16 bit */ 109 u8 bus_width_16; /* buswidth is 16 bit */
110 u8 correction_cap; /* PMECC correction capability */
111 u16 sector_size; /* Sector size for PMECC */
110 struct mtd_partition *parts; 112 struct mtd_partition *parts;
111 unsigned int num_parts; 113 unsigned int num_parts;
112}; 114};
@@ -179,7 +181,9 @@ extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
179extern void __init at91_add_device_ac97(struct ac97c_platform_data *data); 181extern void __init at91_add_device_ac97(struct ac97c_platform_data *data);
180 182
181 /* ISI */ 183 /* ISI */
182extern void __init at91_add_device_isi(void); 184struct isi_platform_data;
185extern void __init at91_add_device_isi(struct isi_platform_data *data,
186 bool use_pck_as_mck);
183 187
184 /* Touchscreen Controller */ 188 /* Touchscreen Controller */
185struct at91_tsadcc_data { 189struct at91_tsadcc_data {
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index f6ce936dba2b..0118c3338552 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -25,7 +25,6 @@
25#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */ 25#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */
26#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */ 26#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */
27#define ARCH_ID_AT91SAM9X5 0x819a05a0 27#define ARCH_ID_AT91SAM9X5 0x819a05a0
28#define ARCH_ID_AT91CAP9 0x039A03A0
29 28
30#define ARCH_ID_AT91SAM9XE128 0x329973a0 29#define ARCH_ID_AT91SAM9XE128 0x329973a0
31#define ARCH_ID_AT91SAM9XE256 0x329a93a0 30#define ARCH_ID_AT91SAM9XE256 0x329a93a0
@@ -51,10 +50,6 @@
51#define ARCH_FAMILY_AT91SAM9 0x01900000 50#define ARCH_FAMILY_AT91SAM9 0x01900000
52#define ARCH_FAMILY_AT91SAM9XE 0x02900000 51#define ARCH_FAMILY_AT91SAM9XE 0x02900000
53 52
54/* PMC revision */
55#define ARCH_REVISION_CAP9_B 0x399
56#define ARCH_REVISION_CAP9_C 0x601
57
58/* RM9200 type */ 53/* RM9200 type */
59#define ARCH_REVISON_9200_BGA (0 << 0) 54#define ARCH_REVISON_9200_BGA (0 << 0)
60#define ARCH_REVISON_9200_PQFP (1 << 0) 55#define ARCH_REVISON_9200_PQFP (1 << 0)
@@ -63,9 +58,6 @@ enum at91_soc_type {
63 /* 920T */ 58 /* 920T */
64 AT91_SOC_RM9200, 59 AT91_SOC_RM9200,
65 60
66 /* CAP */
67 AT91_SOC_CAP9,
68
69 /* SAM92xx */ 61 /* SAM92xx */
70 AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263, 62 AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263,
71 63
@@ -86,9 +78,6 @@ enum at91_soc_subtype {
86 /* RM9200 */ 78 /* RM9200 */
87 AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP, 79 AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP,
88 80
89 /* CAP9 */
90 AT91_SOC_CAP9_REV_B, AT91_SOC_CAP9_REV_C,
91
92 /* SAM9260 */ 81 /* SAM9260 */
93 AT91_SOC_SAM9XE, 82 AT91_SOC_SAM9XE,
94 83
@@ -195,16 +184,6 @@ static inline int at91_soc_is_detected(void)
195#define cpu_is_at91sam9x25() (0) 184#define cpu_is_at91sam9x25() (0)
196#endif 185#endif
197 186
198#ifdef CONFIG_ARCH_AT91CAP9
199#define cpu_is_at91cap9() (at91_soc_initdata.type == AT91_SOC_CAP9)
200#define cpu_is_at91cap9_revB() (at91_soc_initdata.subtype == AT91_SOC_CAP9_REV_B)
201#define cpu_is_at91cap9_revC() (at91_soc_initdata.subtype == AT91_SOC_CAP9_REV_C)
202#else
203#define cpu_is_at91cap9() (0)
204#define cpu_is_at91cap9_revB() (0)
205#define cpu_is_at91cap9_revC() (0)
206#endif
207
208/* 187/*
209 * Since this is ARM, we will never run on any AVR32 CPU. But these 188 * Since this is ARM, we will never run on any AVR32 CPU. But these
210 * definitions may reduce clutter in common drivers. 189 * definitions may reduce clutter in common drivers.
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index 2d0e4e998566..e9e29a6c3868 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -19,7 +19,7 @@
19/* DBGU base */ 19/* DBGU base */
20/* rm9200, 9260/9g20, 9261/9g10, 9rl */ 20/* rm9200, 9260/9g20, 9261/9g10, 9rl */
21#define AT91_BASE_DBGU0 0xfffff200 21#define AT91_BASE_DBGU0 0xfffff200
22/* 9263, 9g45, cap9 */ 22/* 9263, 9g45 */
23#define AT91_BASE_DBGU1 0xffffee00 23#define AT91_BASE_DBGU1 0xffffee00
24 24
25#if defined(CONFIG_ARCH_AT91RM9200) 25#if defined(CONFIG_ARCH_AT91RM9200)
@@ -34,8 +34,8 @@
34#include <mach/at91sam9rl.h> 34#include <mach/at91sam9rl.h>
35#elif defined(CONFIG_ARCH_AT91SAM9G45) 35#elif defined(CONFIG_ARCH_AT91SAM9G45)
36#include <mach/at91sam9g45.h> 36#include <mach/at91sam9g45.h>
37#elif defined(CONFIG_ARCH_AT91CAP9) 37#elif defined(CONFIG_ARCH_AT91SAM9X5)
38#include <mach/at91cap9.h> 38#include <mach/at91sam9x5.h>
39#elif defined(CONFIG_ARCH_AT91X40) 39#elif defined(CONFIG_ARCH_AT91X40)
40#include <mach/at91x40.h> 40#include <mach/at91x40.h>
41#else 41#else
@@ -59,9 +59,10 @@
59 59
60/* 60/*
61 * On all at91 have the Advanced Interrupt Controller starts at address 61 * On all at91 have the Advanced Interrupt Controller starts at address
62 * 0xfffff000 62 * 0xfffff000 and the Power Management Controller starts at 0xfffffc00
63 */ 63 */
64#define AT91_AIC 0xfffff000 64#define AT91_AIC 0xfffff000
65#define AT91_PMC 0xfffffc00
65 66
66/* 67/*
67 * Peripheral identifiers/interrupts. 68 * Peripheral identifiers/interrupts.
diff --git a/arch/arm/mach-at91/include/mach/io.h b/arch/arm/mach-at91/include/mach/io.h
index 4ca09ef7ca29..4003001eca3d 100644
--- a/arch/arm/mach-at91/include/mach/io.h
+++ b/arch/arm/mach-at91/include/mach/io.h
@@ -28,22 +28,4 @@
28#define __io(a) __typesafe_io(a) 28#define __io(a) __typesafe_io(a)
29#define __mem_pci(a) (a) 29#define __mem_pci(a) (a)
30 30
31#ifndef __ASSEMBLY__
32
33static inline unsigned int at91_sys_read(unsigned int reg_offset)
34{
35 void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
36
37 return __raw_readl(addr + reg_offset);
38}
39
40static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
41{
42 void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
43
44 __raw_writel(value, addr + reg_offset);
45}
46
47#endif
48
49#endif 31#endif
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 1606379ac284..6c9d5e69ac28 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -136,7 +136,7 @@ static int at91_pm_verify_clocks(void)
136 unsigned long scsr; 136 unsigned long scsr;
137 int i; 137 int i;
138 138
139 scsr = at91_sys_read(AT91_PMC_SCSR); 139 scsr = at91_pmc_read(AT91_PMC_SCSR);
140 140
141 /* USB must not be using PLLB */ 141 /* USB must not be using PLLB */
142 if (cpu_is_at91rm9200()) { 142 if (cpu_is_at91rm9200()) {
@@ -150,11 +150,6 @@ static int at91_pm_verify_clocks(void)
150 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); 150 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
151 return 0; 151 return 0;
152 } 152 }
153 } else if (cpu_is_at91cap9()) {
154 if ((scsr & AT91CAP9_PMC_UHP) != 0) {
155 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
156 return 0;
157 }
158 } 153 }
159 154
160#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS 155#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
@@ -165,7 +160,7 @@ static int at91_pm_verify_clocks(void)
165 if ((scsr & (AT91_PMC_PCK0 << i)) == 0) 160 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
166 continue; 161 continue;
167 162
168 css = at91_sys_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS; 163 css = at91_pmc_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
169 if (css != AT91_PMC_CSS_SLOW) { 164 if (css != AT91_PMC_CSS_SLOW) {
170 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css); 165 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
171 return 0; 166 return 0;
@@ -193,23 +188,36 @@ int at91_suspend_entering_slow_clock(void)
193EXPORT_SYMBOL(at91_suspend_entering_slow_clock); 188EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
194 189
195 190
196static void (*slow_clock)(void); 191static void (*slow_clock)(void __iomem *pmc, void __iomem *ramc0,
192 void __iomem *ramc1, int memctrl);
197 193
198#ifdef CONFIG_AT91_SLOW_CLOCK 194#ifdef CONFIG_AT91_SLOW_CLOCK
199extern void at91_slow_clock(void); 195extern void at91_slow_clock(void __iomem *pmc, void __iomem *ramc0,
196 void __iomem *ramc1, int memctrl);
200extern u32 at91_slow_clock_sz; 197extern u32 at91_slow_clock_sz;
201#endif 198#endif
202 199
200void __iomem *at91_ramc_base[2];
201
202void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
203{
204 if (id < 0 || id > 1) {
205 pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
206 BUG();
207 }
208 at91_ramc_base[id] = ioremap(addr, size);
209 if (!at91_ramc_base[id])
210 panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr);
211}
203 212
204static int at91_pm_enter(suspend_state_t state) 213static int at91_pm_enter(suspend_state_t state)
205{ 214{
206 u32 saved_lpr;
207 at91_gpio_suspend(); 215 at91_gpio_suspend();
208 at91_irq_suspend(); 216 at91_irq_suspend();
209 217
210 pr_debug("AT91: PM - wake mask %08x, pm state %d\n", 218 pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
211 /* remember all the always-wake irqs */ 219 /* remember all the always-wake irqs */
212 (at91_sys_read(AT91_PMC_PCSR) 220 (at91_pmc_read(AT91_PMC_PCSR)
213 | (1 << AT91_ID_FIQ) 221 | (1 << AT91_ID_FIQ)
214 | (1 << AT91_ID_SYS) 222 | (1 << AT91_ID_SYS)
215 | (at91_extern_irq)) 223 | (at91_extern_irq))
@@ -234,11 +242,18 @@ static int at91_pm_enter(suspend_state_t state)
234 * turning off the main oscillator; reverse on wakeup. 242 * turning off the main oscillator; reverse on wakeup.
235 */ 243 */
236 if (slow_clock) { 244 if (slow_clock) {
245 int memctrl = AT91_MEMCTRL_SDRAMC;
246
247 if (cpu_is_at91rm9200())
248 memctrl = AT91_MEMCTRL_MC;
249 else if (cpu_is_at91sam9g45())
250 memctrl = AT91_MEMCTRL_DDRSDR;
237#ifdef CONFIG_AT91_SLOW_CLOCK 251#ifdef CONFIG_AT91_SLOW_CLOCK
238 /* copy slow_clock handler to SRAM, and call it */ 252 /* copy slow_clock handler to SRAM, and call it */
239 memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz); 253 memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
240#endif 254#endif
241 slow_clock(); 255 slow_clock(at91_pmc_base, at91_ramc_base[0],
256 at91_ramc_base[1], memctrl);
242 break; 257 break;
243 } else { 258 } else {
244 pr_info("AT91: PM - no slow clock mode enabled ...\n"); 259 pr_info("AT91: PM - no slow clock mode enabled ...\n");
@@ -259,16 +274,7 @@ static int at91_pm_enter(suspend_state_t state)
259 * For ARM 926 based chips, this requirement is weaker 274 * For ARM 926 based chips, this requirement is weaker
260 * as at91sam9 can access a RAM in self-refresh mode. 275 * as at91sam9 can access a RAM in self-refresh mode.
261 */ 276 */
262 asm volatile ( "mov r0, #0\n\t" 277 at91_standby();
263 "b 1f\n\t"
264 ".align 5\n\t"
265 "1: mcr p15, 0, r0, c7, c10, 4\n\t"
266 : /* no output */
267 : /* no input */
268 : "r0");
269 saved_lpr = sdram_selfrefresh_enable();
270 wait_for_interrupt_enable();
271 sdram_selfrefresh_disable(saved_lpr);
272 break; 278 break;
273 279
274 case PM_SUSPEND_ON: 280 case PM_SUSPEND_ON:
@@ -316,7 +322,7 @@ static int __init at91_pm_init(void)
316 322
317#ifdef CONFIG_ARCH_AT91RM9200 323#ifdef CONFIG_ARCH_AT91RM9200
318 /* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */ 324 /* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */
319 at91_sys_write(AT91_SDRAMC_LPR, 0); 325 at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0);
320#endif 326#endif
321 327
322 suspend_set_ops(&at91_pm_ops); 328 suspend_set_ops(&at91_pm_ops);
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 7eb40d24242f..89f56f3a802e 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -1,5 +1,19 @@
1/*
2 * AT91 Power Management
3 *
4 * Copyright (C) 2005 David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11#ifndef __ARCH_ARM_MACH_AT91_PM
12#define __ARCH_ARM_MACH_AT91_PM
13
14#include <mach/at91_ramc.h>
1#ifdef CONFIG_ARCH_AT91RM9200 15#ifdef CONFIG_ARCH_AT91RM9200
2#include <mach/at91rm9200_mc.h> 16#include <mach/at91rm9200_sdramc.h>
3 17
4/* 18/*
5 * The AT91RM9200 goes into self-refresh mode with this command, and will 19 * The AT91RM9200 goes into self-refresh mode with this command, and will
@@ -11,51 +25,37 @@
11 * still in self-refresh is "not recommended", but seems to work. 25 * still in self-refresh is "not recommended", but seems to work.
12 */ 26 */
13 27
14static inline u32 sdram_selfrefresh_enable(void) 28static inline void at91rm9200_standby(void)
15{ 29{
16 u32 saved_lpr = at91_sys_read(AT91_SDRAMC_LPR); 30 u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
17 31
18 at91_sys_write(AT91_SDRAMC_LPR, 0); 32 asm volatile(
19 at91_sys_write(AT91_SDRAMC_SRR, 1); 33 "b 1f\n\t"
20 return saved_lpr; 34 ".align 5\n\t"
35 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
36 " str %0, [%1, %2]\n\t"
37 " str %3, [%1, %4]\n\t"
38 " mcr p15, 0, %0, c7, c0, 4\n\t"
39 " str %5, [%1, %2]"
40 :
41 : "r" (0), "r" (AT91_BASE_SYS), "r" (AT91RM9200_SDRAMC_LPR),
42 "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
43 "r" (lpr));
21} 44}
22 45
23#define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_SDRAMC_LPR, saved_lpr) 46#define at91_standby at91rm9200_standby
24#define wait_for_interrupt_enable() asm volatile ("mcr p15, 0, %0, c7, c0, 4" \
25 : : "r" (0))
26
27#elif defined(CONFIG_ARCH_AT91CAP9)
28#include <mach/at91sam9_ddrsdr.h>
29
30
31static inline u32 sdram_selfrefresh_enable(void)
32{
33 u32 saved_lpr, lpr;
34
35 saved_lpr = at91_ramc_read(0, AT91CAP9_DDRSDRC_LPR);
36
37 lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
38 at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
39 return saved_lpr;
40}
41
42#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, saved_lpr)
43#define wait_for_interrupt_enable() cpu_do_idle()
44 47
45#elif defined(CONFIG_ARCH_AT91SAM9G45) 48#elif defined(CONFIG_ARCH_AT91SAM9G45)
46#include <mach/at91sam9_ddrsdr.h>
47 49
48/* We manage both DDRAM/SDRAM controllers, we need more than one value to 50/* We manage both DDRAM/SDRAM controllers, we need more than one value to
49 * remember. 51 * remember.
50 */ 52 */
51static u32 saved_lpr1; 53static inline void at91sam9g45_standby(void)
52
53static inline u32 sdram_selfrefresh_enable(void)
54{ 54{
55 /* Those tow values allow us to delay self-refresh activation 55 /* Those two values allow us to delay self-refresh activation
56 * to the maximum. */ 56 * to the maximum. */
57 u32 lpr0, lpr1; 57 u32 lpr0, lpr1;
58 u32 saved_lpr0; 58 u32 saved_lpr0, saved_lpr1;
59 59
60 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); 60 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
61 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; 61 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
@@ -69,18 +69,15 @@ static inline u32 sdram_selfrefresh_enable(void)
69 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); 69 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
70 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); 70 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
71 71
72 return saved_lpr0; 72 cpu_do_idle();
73
74 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
75 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
73} 76}
74 77
75#define sdram_selfrefresh_disable(saved_lpr0) \ 78#define at91_standby at91sam9g45_standby
76 do { \
77 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \
78 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \
79 } while (0)
80#define wait_for_interrupt_enable() cpu_do_idle()
81 79
82#else 80#else
83#include <mach/at91sam9_sdramc.h>
84 81
85#ifdef CONFIG_ARCH_AT91SAM9263 82#ifdef CONFIG_ARCH_AT91SAM9263
86/* 83/*
@@ -90,18 +87,23 @@ static inline u32 sdram_selfrefresh_enable(void)
90#warning Assuming EB1 SDRAM controller is *NOT* used 87#warning Assuming EB1 SDRAM controller is *NOT* used
91#endif 88#endif
92 89
93static inline u32 sdram_selfrefresh_enable(void) 90static inline void at91sam9_standby(void)
94{ 91{
95 u32 saved_lpr, lpr; 92 u32 saved_lpr, lpr;
96 93
97 saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR); 94 saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
98 95
99 lpr = saved_lpr & ~AT91_SDRAMC_LPCB; 96 lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
100 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH); 97 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr |
101 return saved_lpr; 98 AT91_SDRAMC_LPCB_SELF_REFRESH);
99
100 cpu_do_idle();
101
102 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr);
102} 103}
103 104
104#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr) 105#define at91_standby at91sam9_standby
105#define wait_for_interrupt_enable() cpu_do_idle() 106
107#endif
106 108
107#endif 109#endif
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 92dfb8461392..db5452123f17 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -15,15 +15,7 @@
15#include <linux/linkage.h> 15#include <linux/linkage.h>
16#include <mach/hardware.h> 16#include <mach/hardware.h>
17#include <mach/at91_pmc.h> 17#include <mach/at91_pmc.h>
18 18#include <mach/at91_ramc.h>
19#if defined(CONFIG_ARCH_AT91RM9200)
20#include <mach/at91rm9200_mc.h>
21#elif defined(CONFIG_ARCH_AT91CAP9) \
22 || defined(CONFIG_ARCH_AT91SAM9G45)
23#include <mach/at91sam9_ddrsdr.h>
24#else
25#include <mach/at91sam9_sdramc.h>
26#endif
27 19
28 20
29#ifdef CONFIG_ARCH_AT91SAM9263 21#ifdef CONFIG_ARCH_AT91SAM9263
@@ -47,17 +39,23 @@
47#define PLLALOCK_TIMEOUT 1000 39#define PLLALOCK_TIMEOUT 1000
48#define PLLBLOCK_TIMEOUT 1000 40#define PLLBLOCK_TIMEOUT 1000
49 41
42pmc .req r0
43sdramc .req r1
44ramc1 .req r2
45memctrl .req r3
46tmp1 .req r4
47tmp2 .req r5
50 48
51/* 49/*
52 * Wait until master clock is ready (after switching master clock source) 50 * Wait until master clock is ready (after switching master clock source)
53 */ 51 */
54 .macro wait_mckrdy 52 .macro wait_mckrdy
55 mov r4, #MCKRDY_TIMEOUT 53 mov tmp2, #MCKRDY_TIMEOUT
561: sub r4, r4, #1 541: sub tmp2, tmp2, #1
57 cmp r4, #0 55 cmp tmp2, #0
58 beq 2f 56 beq 2f
59 ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)] 57 ldr tmp1, [pmc, #AT91_PMC_SR]
60 tst r3, #AT91_PMC_MCKRDY 58 tst tmp1, #AT91_PMC_MCKRDY
61 beq 1b 59 beq 1b
622: 602:
63 .endm 61 .endm
@@ -66,12 +64,12 @@
66 * Wait until master oscillator has stabilized. 64 * Wait until master oscillator has stabilized.
67 */ 65 */
68 .macro wait_moscrdy 66 .macro wait_moscrdy
69 mov r4, #MOSCRDY_TIMEOUT 67 mov tmp2, #MOSCRDY_TIMEOUT
701: sub r4, r4, #1 681: sub tmp2, tmp2, #1
71 cmp r4, #0 69 cmp tmp2, #0
72 beq 2f 70 beq 2f
73 ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)] 71 ldr tmp1, [pmc, #AT91_PMC_SR]
74 tst r3, #AT91_PMC_MOSCS 72 tst tmp1, #AT91_PMC_MOSCS
75 beq 1b 73 beq 1b
762: 742:
77 .endm 75 .endm
@@ -80,12 +78,12 @@
80 * Wait until PLLA has locked. 78 * Wait until PLLA has locked.
81 */ 79 */
82 .macro wait_pllalock 80 .macro wait_pllalock
83 mov r4, #PLLALOCK_TIMEOUT 81 mov tmp2, #PLLALOCK_TIMEOUT
841: sub r4, r4, #1 821: sub tmp2, tmp2, #1
85 cmp r4, #0 83 cmp tmp2, #0
86 beq 2f 84 beq 2f
87 ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)] 85 ldr tmp1, [pmc, #AT91_PMC_SR]
88 tst r3, #AT91_PMC_LOCKA 86 tst tmp1, #AT91_PMC_LOCKA
89 beq 1b 87 beq 1b
902: 882:
91 .endm 89 .endm
@@ -94,80 +92,98 @@
94 * Wait until PLLB has locked. 92 * Wait until PLLB has locked.
95 */ 93 */
96 .macro wait_pllblock 94 .macro wait_pllblock
97 mov r4, #PLLBLOCK_TIMEOUT 95 mov tmp2, #PLLBLOCK_TIMEOUT
981: sub r4, r4, #1 961: sub tmp2, tmp2, #1
99 cmp r4, #0 97 cmp tmp2, #0
100 beq 2f 98 beq 2f
101 ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)] 99 ldr tmp1, [pmc, #AT91_PMC_SR]
102 tst r3, #AT91_PMC_LOCKB 100 tst tmp1, #AT91_PMC_LOCKB
103 beq 1b 101 beq 1b
1042: 1022:
105 .endm 103 .endm
106 104
107 .text 105 .text
108 106
107/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc,
108 * void __iomem *ramc1, int memctrl)
109 */
109ENTRY(at91_slow_clock) 110ENTRY(at91_slow_clock)
110 /* Save registers on stack */ 111 /* Save registers on stack */
111 stmfd sp!, {r0 - r12, lr} 112 stmfd sp!, {r4 - r12, lr}
112 113
113 /* 114 /*
114 * Register usage: 115 * Register usage:
115 * R1 = Base address of AT91_PMC 116 * R0 = Base address of AT91_PMC
116 * R2 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS) 117 * R1 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
117 * R3 = temporary register 118 * R2 = Base address of second RAM Controller or 0 if not present
119 * R3 = Memory controller
118 * R4 = temporary register 120 * R4 = temporary register
119 * R5 = Base address of second RAM Controller or 0 if not present 121 * R5 = temporary register
120 */ 122 */
121 ldr r1, .at91_va_base_pmc
122 ldr r2, .at91_va_base_sdramc
123 ldr r5, .at91_va_base_ramc1
124 123
125 /* Drain write buffer */ 124 /* Drain write buffer */
126 mov r0, #0 125 mov tmp1, #0
127 mcr p15, 0, r0, c7, c10, 4 126 mcr p15, 0, tmp1, c7, c10, 4
127
128 cmp memctrl, #AT91_MEMCTRL_MC
129 bne ddr_sr_enable
128 130
129#ifdef CONFIG_ARCH_AT91RM9200 131 /*
132 * at91rm9200 Memory controller
133 */
130 /* Put SDRAM in self-refresh mode */ 134 /* Put SDRAM in self-refresh mode */
131 mov r3, #1 135 mov tmp1, #1
132 str r3, [r2, #AT91_SDRAMC_SRR] 136 str tmp1, [sdramc, #AT91RM9200_SDRAMC_SRR]
133#elif defined(CONFIG_ARCH_AT91CAP9) \ 137 b sdr_sr_done
134 || defined(CONFIG_ARCH_AT91SAM9G45) 138
139 /*
140 * DDRSDR Memory controller
141 */
142ddr_sr_enable:
143 cmp memctrl, #AT91_MEMCTRL_DDRSDR
144 bne sdr_sr_enable
135 145
136 /* prepare for DDRAM self-refresh mode */ 146 /* prepare for DDRAM self-refresh mode */
137 ldr r3, [r2, #AT91_DDRSDRC_LPR] 147 ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR]
138 str r3, .saved_sam9_lpr 148 str tmp1, .saved_sam9_lpr
139 bic r3, #AT91_DDRSDRC_LPCB 149 bic tmp1, #AT91_DDRSDRC_LPCB
140 orr r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH 150 orr tmp1, #AT91_DDRSDRC_LPCB_SELF_REFRESH
141 151
142 /* figure out if we use the second ram controller */ 152 /* figure out if we use the second ram controller */
143 cmp r5, #0 153 cmp ramc1, #0
144 ldrne r4, [r5, #AT91_DDRSDRC_LPR] 154 ldrne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
145 strne r4, .saved_sam9_lpr1 155 strne tmp2, .saved_sam9_lpr1
146 bicne r4, #AT91_DDRSDRC_LPCB 156 bicne tmp2, #AT91_DDRSDRC_LPCB
147 orrne r4, #AT91_DDRSDRC_LPCB_SELF_REFRESH 157 orrne tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
148 158
149 /* Enable DDRAM self-refresh mode */ 159 /* Enable DDRAM self-refresh mode */
150 str r3, [r2, #AT91_DDRSDRC_LPR] 160 str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
151 strne r4, [r5, #AT91_DDRSDRC_LPR] 161 strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
152#else 162
163 b sdr_sr_done
164
165 /*
166 * SDRAMC Memory controller
167 */
168sdr_sr_enable:
153 /* Enable SDRAM self-refresh mode */ 169 /* Enable SDRAM self-refresh mode */
154 ldr r3, [r2, #AT91_SDRAMC_LPR] 170 ldr tmp1, [sdramc, #AT91_SDRAMC_LPR]
155 str r3, .saved_sam9_lpr 171 str tmp1, .saved_sam9_lpr
156 172
157 bic r3, #AT91_SDRAMC_LPCB 173 bic tmp1, #AT91_SDRAMC_LPCB
158 orr r3, #AT91_SDRAMC_LPCB_SELF_REFRESH 174 orr tmp1, #AT91_SDRAMC_LPCB_SELF_REFRESH
159 str r3, [r2, #AT91_SDRAMC_LPR] 175 str tmp1, [sdramc, #AT91_SDRAMC_LPR]
160#endif
161 176
177sdr_sr_done:
162 /* Save Master clock setting */ 178 /* Save Master clock setting */
163 ldr r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)] 179 ldr tmp1, [pmc, #AT91_PMC_MCKR]
164 str r3, .saved_mckr 180 str tmp1, .saved_mckr
165 181
166 /* 182 /*
167 * Set the Master clock source to slow clock 183 * Set the Master clock source to slow clock
168 */ 184 */
169 bic r3, r3, #AT91_PMC_CSS 185 bic tmp1, tmp1, #AT91_PMC_CSS
170 str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)] 186 str tmp1, [pmc, #AT91_PMC_MCKR]
171 187
172 wait_mckrdy 188 wait_mckrdy
173 189
@@ -177,61 +193,61 @@ ENTRY(at91_slow_clock)
177 * 193 *
178 * See AT91RM9200 errata #27 and #28 for details. 194 * See AT91RM9200 errata #27 and #28 for details.
179 */ 195 */
180 mov r3, #0 196 mov tmp1, #0
181 str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)] 197 str tmp1, [pmc, #AT91_PMC_MCKR]
182 198
183 wait_mckrdy 199 wait_mckrdy
184#endif 200#endif
185 201
186 /* Save PLLA setting and disable it */ 202 /* Save PLLA setting and disable it */
187 ldr r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)] 203 ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
188 str r3, .saved_pllar 204 str tmp1, .saved_pllar
189 205
190 mov r3, #AT91_PMC_PLLCOUNT 206 mov tmp1, #AT91_PMC_PLLCOUNT
191 orr r3, r3, #(1 << 29) /* bit 29 always set */ 207 orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
192 str r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)] 208 str tmp1, [pmc, #AT91_CKGR_PLLAR]
193 209
194 /* Save PLLB setting and disable it */ 210 /* Save PLLB setting and disable it */
195 ldr r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)] 211 ldr tmp1, [pmc, #AT91_CKGR_PLLBR]
196 str r3, .saved_pllbr 212 str tmp1, .saved_pllbr
197 213
198 mov r3, #AT91_PMC_PLLCOUNT 214 mov tmp1, #AT91_PMC_PLLCOUNT
199 str r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)] 215 str tmp1, [pmc, #AT91_CKGR_PLLBR]
200 216
201 /* Turn off the main oscillator */ 217 /* Turn off the main oscillator */
202 ldr r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)] 218 ldr tmp1, [pmc, #AT91_CKGR_MOR]
203 bic r3, r3, #AT91_PMC_MOSCEN 219 bic tmp1, tmp1, #AT91_PMC_MOSCEN
204 str r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)] 220 str tmp1, [pmc, #AT91_CKGR_MOR]
205 221
206 /* Wait for interrupt */ 222 /* Wait for interrupt */
207 mcr p15, 0, r0, c7, c0, 4 223 mcr p15, 0, tmp1, c7, c0, 4
208 224
209 /* Turn on the main oscillator */ 225 /* Turn on the main oscillator */
210 ldr r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)] 226 ldr tmp1, [pmc, #AT91_CKGR_MOR]
211 orr r3, r3, #AT91_PMC_MOSCEN 227 orr tmp1, tmp1, #AT91_PMC_MOSCEN
212 str r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)] 228 str tmp1, [pmc, #AT91_CKGR_MOR]
213 229
214 wait_moscrdy 230 wait_moscrdy
215 231
216 /* Restore PLLB setting */ 232 /* Restore PLLB setting */
217 ldr r3, .saved_pllbr 233 ldr tmp1, .saved_pllbr
218 str r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)] 234 str tmp1, [pmc, #AT91_CKGR_PLLBR]
219 235
220 tst r3, #(AT91_PMC_MUL & 0xff0000) 236 tst tmp1, #(AT91_PMC_MUL & 0xff0000)
221 bne 1f 237 bne 1f
222 tst r3, #(AT91_PMC_MUL & ~0xff0000) 238 tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
223 beq 2f 239 beq 2f
2241: 2401:
225 wait_pllblock 241 wait_pllblock
2262: 2422:
227 243
228 /* Restore PLLA setting */ 244 /* Restore PLLA setting */
229 ldr r3, .saved_pllar 245 ldr tmp1, .saved_pllar
230 str r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)] 246 str tmp1, [pmc, #AT91_CKGR_PLLAR]
231 247
232 tst r3, #(AT91_PMC_MUL & 0xff0000) 248 tst tmp1, #(AT91_PMC_MUL & 0xff0000)
233 bne 3f 249 bne 3f
234 tst r3, #(AT91_PMC_MUL & ~0xff0000) 250 tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
235 beq 4f 251 beq 4f
2363: 2523:
237 wait_pllalock 253 wait_pllalock
@@ -244,11 +260,11 @@ ENTRY(at91_slow_clock)
244 * 260 *
245 * See AT91RM9200 errata #27 and #28 for details. 261 * See AT91RM9200 errata #27 and #28 for details.
246 */ 262 */
247 ldr r3, .saved_mckr 263 ldr tmp1, .saved_mckr
248 tst r3, #AT91_PMC_PRES 264 tst tmp1, #AT91_PMC_PRES
249 beq 2f 265 beq 2f
250 and r3, r3, #AT91_PMC_PRES 266 and tmp1, tmp1, #AT91_PMC_PRES
251 str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)] 267 str tmp1, [pmc, #AT91_PMC_MCKR]
252 268
253 wait_mckrdy 269 wait_mckrdy
254#endif 270#endif
@@ -256,32 +272,45 @@ ENTRY(at91_slow_clock)
256 /* 272 /*
257 * Restore master clock setting 273 * Restore master clock setting
258 */ 274 */
2592: ldr r3, .saved_mckr 2752: ldr tmp1, .saved_mckr
260 str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)] 276 str tmp1, [pmc, #AT91_PMC_MCKR]
261 277
262 wait_mckrdy 278 wait_mckrdy
263 279
264#ifdef CONFIG_ARCH_AT91RM9200 280 /*
265 /* Do nothing - self-refresh is automatically disabled. */ 281 * at91rm9200 Memory controller
266#elif defined(CONFIG_ARCH_AT91CAP9) \ 282 * Do nothing - self-refresh is automatically disabled.
267 || defined(CONFIG_ARCH_AT91SAM9G45) 283 */
284 cmp memctrl, #AT91_MEMCTRL_MC
285 beq ram_restored
286
287 /*
288 * DDRSDR Memory controller
289 */
290 cmp memctrl, #AT91_MEMCTRL_DDRSDR
291 bne sdr_en_restore
268 /* Restore LPR on AT91 with DDRAM */ 292 /* Restore LPR on AT91 with DDRAM */
269 ldr r3, .saved_sam9_lpr 293 ldr tmp1, .saved_sam9_lpr
270 str r3, [r2, #AT91_DDRSDRC_LPR] 294 str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
271 295
272 /* if we use the second ram controller */ 296 /* if we use the second ram controller */
273 cmp r5, #0 297 cmp ramc1, #0
274 ldrne r4, .saved_sam9_lpr1 298 ldrne tmp2, .saved_sam9_lpr1
275 strne r4, [r5, #AT91_DDRSDRC_LPR] 299 strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
300
301 b ram_restored
276 302
277#else 303 /*
304 * SDRAMC Memory controller
305 */
306sdr_en_restore:
278 /* Restore LPR on AT91 with SDRAM */ 307 /* Restore LPR on AT91 with SDRAM */
279 ldr r3, .saved_sam9_lpr 308 ldr tmp1, .saved_sam9_lpr
280 str r3, [r2, #AT91_SDRAMC_LPR] 309 str tmp1, [sdramc, #AT91_SDRAMC_LPR]
281#endif
282 310
311ram_restored:
283 /* Restore registers, and return */ 312 /* Restore registers, and return */
284 ldmfd sp!, {r0 - r12, pc} 313 ldmfd sp!, {r4 - r12, pc}
285 314
286 315
287.saved_mckr: 316.saved_mckr:
@@ -299,27 +328,5 @@ ENTRY(at91_slow_clock)
299.saved_sam9_lpr1: 328.saved_sam9_lpr1:
300 .word 0 329 .word 0
301 330
302.at91_va_base_pmc:
303 .word AT91_VA_BASE_SYS + AT91_PMC
304
305#ifdef CONFIG_ARCH_AT91RM9200
306.at91_va_base_sdramc:
307 .word AT91_VA_BASE_SYS
308#elif defined(CONFIG_ARCH_AT91CAP9) \
309 || defined(CONFIG_ARCH_AT91SAM9G45)
310.at91_va_base_sdramc:
311 .word AT91_VA_BASE_SYS + AT91_DDRSDRC0
312#else
313.at91_va_base_sdramc:
314 .word AT91_VA_BASE_SYS + AT91_SDRAMC0
315#endif
316
317.at91_va_base_ramc1:
318#if defined(CONFIG_ARCH_AT91SAM9G45)
319 .word AT91_VA_BASE_SYS + AT91_DDRSDRC1
320#else
321 .word 0
322#endif
323
324ENTRY(at91_slow_clock_sz) 331ENTRY(at91_slow_clock_sz)
325 .word .-at91_slow_clock 332 .word .-at91_slow_clock
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 69d3fc4c46f3..372396c2ecb6 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -86,20 +86,6 @@ static void __init soc_detect(u32 dbgu_base)
86 socid = cidr & ~AT91_CIDR_VERSION; 86 socid = cidr & ~AT91_CIDR_VERSION;
87 87
88 switch (socid) { 88 switch (socid) {
89 case ARCH_ID_AT91CAP9: {
90#ifdef CONFIG_AT91_PMC_UNIT
91 u32 pmc_ver = at91_sys_read(AT91_PMC_VER);
92
93 if (pmc_ver == ARCH_REVISION_CAP9_B)
94 at91_soc_initdata.subtype = AT91_SOC_CAP9_REV_B;
95 else if (pmc_ver == ARCH_REVISION_CAP9_C)
96 at91_soc_initdata.subtype = AT91_SOC_CAP9_REV_C;
97#endif
98 at91_soc_initdata.type = AT91_SOC_CAP9;
99 at91_boot_soc = at91cap9_soc;
100 break;
101 }
102
103 case ARCH_ID_AT91RM9200: 89 case ARCH_ID_AT91RM9200:
104 at91_soc_initdata.type = AT91_SOC_RM9200; 90 at91_soc_initdata.type = AT91_SOC_RM9200;
105 at91_boot_soc = at91rm9200_soc; 91 at91_boot_soc = at91rm9200_soc;
@@ -200,7 +186,6 @@ static void __init soc_detect(u32 dbgu_base)
200 186
201static const char *soc_name[] = { 187static const char *soc_name[] = {
202 [AT91_SOC_RM9200] = "at91rm9200", 188 [AT91_SOC_RM9200] = "at91rm9200",
203 [AT91_SOC_CAP9] = "at91cap9",
204 [AT91_SOC_SAM9260] = "at91sam9260", 189 [AT91_SOC_SAM9260] = "at91sam9260",
205 [AT91_SOC_SAM9261] = "at91sam9261", 190 [AT91_SOC_SAM9261] = "at91sam9261",
206 [AT91_SOC_SAM9263] = "at91sam9263", 191 [AT91_SOC_SAM9263] = "at91sam9263",
@@ -221,8 +206,6 @@ EXPORT_SYMBOL(at91_get_soc_type);
221static const char *soc_subtype_name[] = { 206static const char *soc_subtype_name[] = {
222 [AT91_SOC_RM9200_BGA] = "at91rm9200 BGA", 207 [AT91_SOC_RM9200_BGA] = "at91rm9200 BGA",
223 [AT91_SOC_RM9200_PQFP] = "at91rm9200 PQFP", 208 [AT91_SOC_RM9200_PQFP] = "at91rm9200 PQFP",
224 [AT91_SOC_CAP9_REV_B] = "at91cap9 revB",
225 [AT91_SOC_CAP9_REV_C] = "at91cap9 revC",
226 [AT91_SOC_SAM9XE] = "at91sam9xe", 209 [AT91_SOC_SAM9XE] = "at91sam9xe",
227 [AT91_SOC_SAM9G45ES] = "at91sam9g45es", 210 [AT91_SOC_SAM9G45ES] = "at91sam9g45es",
228 [AT91_SOC_SAM9M10] = "at91sam9m10", 211 [AT91_SOC_SAM9M10] = "at91sam9m10",
@@ -293,6 +276,15 @@ void __init at91_ioremap_rstc(u32 base_addr)
293 panic("Impossible to ioremap at91_rstc_base\n"); 276 panic("Impossible to ioremap at91_rstc_base\n");
294} 277}
295 278
279void __iomem *at91_matrix_base;
280
281void __init at91_ioremap_matrix(u32 base_addr)
282{
283 at91_matrix_base = ioremap(base_addr, 512);
284 if (!at91_matrix_base)
285 panic("Impossible to ioremap at91_matrix_base\n");
286}
287
296void __init at91_initialize(unsigned long main_clock) 288void __init at91_initialize(unsigned long main_clock)
297{ 289{
298 at91_boot_soc.ioremap_registers(); 290 at91_boot_soc.ioremap_registers();
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
index 4588ae6f7acd..5db4aa45404a 100644
--- a/arch/arm/mach-at91/soc.h
+++ b/arch/arm/mach-at91/soc.h
@@ -13,7 +13,6 @@ struct at91_init_soc {
13}; 13};
14 14
15extern struct at91_init_soc at91_boot_soc; 15extern struct at91_init_soc at91_boot_soc;
16extern struct at91_init_soc at91cap9_soc;
17extern struct at91_init_soc at91rm9200_soc; 16extern struct at91_init_soc at91rm9200_soc;
18extern struct at91_init_soc at91sam9260_soc; 17extern struct at91_init_soc at91sam9260_soc;
19extern struct at91_init_soc at91sam9261_soc; 18extern struct at91_init_soc at91sam9261_soc;
@@ -27,10 +26,6 @@ static inline int at91_soc_is_enabled(void)
27 return at91_boot_soc.init != NULL; 26 return at91_boot_soc.init != NULL;
28} 27}
29 28
30#if !defined(CONFIG_ARCH_AT91CAP9)
31#define at91cap9_soc at91_boot_soc
32#endif
33
34#if !defined(CONFIG_ARCH_AT91RM9200) 29#if !defined(CONFIG_ARCH_AT91RM9200)
35#define at91rm9200_soc at91_boot_soc 30#define at91rm9200_soc at91_boot_soc
36#endif 31#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-13 21:50:39 -0500