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authorHeiko Stuebner <heiko@sntech.de>2014-07-26 12:44:35 -0400
committerHeiko Stuebner <heiko@sntech.de>2014-07-26 17:19:06 -0400
commitc3030d30d9c99c057b5ddfa289cffa637a2775f5 (patch)
tree2d221f06754ccb8f400ca7c1259d4fbb547722cf /arch/arm
parentd356d96f8558d69d4b0d4c72d95002e9b6533531 (diff)
ARM: dts: rockchip: remove soc subnodes
Comments received from the rk3288 submission indicated that a generic subnode to group soc components should not be used. So to keep all rockchip devicetree files similar, remove it from rk3066 and rk3188. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/rk3066a-bqcurie2.dts134
-rw-r--r--arch/arm/boot/dts/rk3066a.dtsi390
-rw-r--r--arch/arm/boot/dts/rk3188-radxarock.dts83
-rw-r--r--arch/arm/boot/dts/rk3188.dtsi334
-rw-r--r--arch/arm/boot/dts/rk3xxx.dtsi221
5 files changed, 573 insertions, 589 deletions
diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index afb327322a4a..6131675695eb 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -24,87 +24,85 @@
24 reg = <0x60000000 0x40000000>; 24 reg = <0x60000000 0x40000000>;
25 }; 25 };
26 26
27 soc { 27 uart0: serial@10124000 {
28 uart0: serial@10124000 { 28 status = "okay";
29 status = "okay"; 29 };
30 };
31 30
32 uart1: serial@10126000 { 31 uart1: serial@10126000 {
33 status = "okay"; 32 status = "okay";
34 }; 33 };
35 34
36 uart2: serial@20064000 { 35 uart2: serial@20064000 {
37 pinctrl-names = "default"; 36 pinctrl-names = "default";
38 pinctrl-0 = <&uart2_xfer>; 37 pinctrl-0 = <&uart2_xfer>;
39 status = "okay"; 38 status = "okay";
40 }; 39 };
41 40
42 uart3: serial@20068000 { 41 uart3: serial@20068000 {
43 status = "okay"; 42 status = "okay";
44 }; 43 };
45 44
46 vcc_sd0: fixed-regulator { 45 vcc_sd0: fixed-regulator {
47 compatible = "regulator-fixed"; 46 compatible = "regulator-fixed";
48 regulator-name = "sdmmc-supply"; 47 regulator-name = "sdmmc-supply";
49 regulator-min-microvolt = <3000000>; 48 regulator-min-microvolt = <3000000>;
50 regulator-max-microvolt = <3000000>; 49 regulator-max-microvolt = <3000000>;
51 gpio = <&gpio3 7 GPIO_ACTIVE_LOW>; 50 gpio = <&gpio3 7 GPIO_ACTIVE_LOW>;
52 startup-delay-us = <100000>; 51 startup-delay-us = <100000>;
53 }; 52 };
54 53
55 dwmmc@10214000 { /* sdmmc */ 54 dwmmc@10214000 { /* sdmmc */
56 num-slots = <1>; 55 num-slots = <1>;
57 status = "okay"; 56 status = "okay";
58 57
59 pinctrl-names = "default"; 58 pinctrl-names = "default";
60 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; 59 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
61 vmmc-supply = <&vcc_sd0>; 60 vmmc-supply = <&vcc_sd0>;
62 61
63 slot@0 { 62 slot@0 {
64 reg = <0>; 63 reg = <0>;
65 bus-width = <4>; 64 bus-width = <4>;
66 disable-wp; 65 disable-wp;
67 };
68 }; 66 };
67 };
69 68
70 dwmmc@10218000 { /* wifi */ 69 dwmmc@10218000 { /* wifi */
71 num-slots = <1>; 70 num-slots = <1>;
72 status = "okay"; 71 status = "okay";
73 non-removable; 72 non-removable;
74 73
75 pinctrl-names = "default"; 74 pinctrl-names = "default";
76 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; 75 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>;
77 76
78 slot@0 { 77 slot@0 {
79 reg = <0>; 78 reg = <0>;
80 bus-width = <4>; 79 bus-width = <4>;
81 disable-wp; 80 disable-wp;
82 };
83 }; 81 };
82 };
84 83
85 gpio-keys { 84 gpio-keys {
86 compatible = "gpio-keys"; 85 compatible = "gpio-keys";
87 #address-cells = <1>; 86 #address-cells = <1>;
88 #size-cells = <0>; 87 #size-cells = <0>;
89 autorepeat; 88 autorepeat;
90 89
91 button@0 { 90 button@0 {
92 gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */ 91 gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */
93 linux,code = <116>; 92 linux,code = <116>;
94 label = "GPIO Key Power"; 93 label = "GPIO Key Power";
95 linux,input-type = <1>; 94 linux,input-type = <1>;
96 gpio-key,wakeup = <1>; 95 gpio-key,wakeup = <1>;
97 debounce-interval = <100>; 96 debounce-interval = <100>;
98 }; 97 };
99 button@1 { 98 button@1 {
100 gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */ 99 gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */
101 linux,code = <104>; 100 linux,code = <104>;
102 label = "GPIO Key Vol-"; 101 label = "GPIO Key Vol-";
103 linux,input-type = <1>; 102 linux,input-type = <1>;
104 gpio-key,wakeup = <0>; 103 gpio-key,wakeup = <0>;
105 debounce-interval = <100>; 104 debounce-interval = <100>;
106 };
107 /* VOL+ comes somehow thru the ADC */
108 }; 105 };
106 /* VOL+ comes somehow thru the ADC */
109 }; 107 };
110}; 108};
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 6476ce7a2987..4ad8f59503dd 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -40,255 +40,253 @@
40 }; 40 };
41 }; 41 };
42 42
43 soc { 43 timer@20038000 {
44 timer@20038000 { 44 compatible = "snps,dw-apb-timer-osc";
45 compatible = "snps,dw-apb-timer-osc"; 45 reg = <0x20038000 0x100>;
46 reg = <0x20038000 0x100>; 46 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
47 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 47 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
48 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; 48 clock-names = "timer", "pclk";
49 clock-names = "timer", "pclk"; 49 };
50 }; 50
51 timer@2003a000 {
52 compatible = "snps,dw-apb-timer-osc";
53 reg = <0x2003a000 0x100>;
54 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
55 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
56 clock-names = "timer", "pclk";
57 };
58
59 timer@2000e000 {
60 compatible = "snps,dw-apb-timer-osc";
61 reg = <0x2000e000 0x100>;
62 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
63 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
64 clock-names = "timer", "pclk";
65 };
51 66
52 timer@2003a000 { 67 sram: sram@10080000 {
53 compatible = "snps,dw-apb-timer-osc"; 68 compatible = "mmio-sram";
54 reg = <0x2003a000 0x100>; 69 reg = <0x10080000 0x10000>;
55 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 70 #address-cells = <1>;
56 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; 71 #size-cells = <1>;
57 clock-names = "timer", "pclk"; 72 ranges = <0 0x10080000 0x10000>;
73
74 smp-sram@0 {
75 compatible = "rockchip,rk3066-smp-sram";
76 reg = <0x0 0x50>;
58 }; 77 };
78 };
79
80 cru: clock-controller@20000000 {
81 compatible = "rockchip,rk3066a-cru";
82 reg = <0x20000000 0x1000>;
83 rockchip,grf = <&grf>;
84
85 #clock-cells = <1>;
86 #reset-cells = <1>;
87 };
88
89 pinctrl@20008000 {
90 compatible = "rockchip,rk3066a-pinctrl";
91 rockchip,grf = <&grf>;
92 #address-cells = <1>;
93 #size-cells = <1>;
94 ranges;
59 95
60 timer@2000e000 { 96 gpio0: gpio0@20034000 {
61 compatible = "snps,dw-apb-timer-osc"; 97 compatible = "rockchip,gpio-bank";
62 reg = <0x2000e000 0x100>; 98 reg = <0x20034000 0x100>;
63 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 99 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
64 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; 100 clocks = <&cru PCLK_GPIO0>;
65 clock-names = "timer", "pclk"; 101
102 gpio-controller;
103 #gpio-cells = <2>;
104
105 interrupt-controller;
106 #interrupt-cells = <2>;
66 }; 107 };
67 108
68 sram: sram@10080000 { 109 gpio1: gpio1@2003c000 {
69 compatible = "mmio-sram"; 110 compatible = "rockchip,gpio-bank";
70 reg = <0x10080000 0x10000>; 111 reg = <0x2003c000 0x100>;
71 #address-cells = <1>; 112 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
72 #size-cells = <1>; 113 clocks = <&cru PCLK_GPIO1>;
73 ranges = <0 0x10080000 0x10000>;
74 114
75 smp-sram@0 { 115 gpio-controller;
76 compatible = "rockchip,rk3066-smp-sram"; 116 #gpio-cells = <2>;
77 reg = <0x0 0x50>; 117
78 }; 118 interrupt-controller;
119 #interrupt-cells = <2>;
79 }; 120 };
80 121
81 cru: clock-controller@20000000 { 122 gpio2: gpio2@2003e000 {
82 compatible = "rockchip,rk3066a-cru"; 123 compatible = "rockchip,gpio-bank";
83 reg = <0x20000000 0x1000>; 124 reg = <0x2003e000 0x100>;
84 rockchip,grf = <&grf>; 125 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
126 clocks = <&cru PCLK_GPIO2>;
127
128 gpio-controller;
129 #gpio-cells = <2>;
85 130
86 #clock-cells = <1>; 131 interrupt-controller;
87 #reset-cells = <1>; 132 #interrupt-cells = <2>;
88 }; 133 };
89 134
90 pinctrl@20008000 { 135 gpio3: gpio3@20080000 {
91 compatible = "rockchip,rk3066a-pinctrl"; 136 compatible = "rockchip,gpio-bank";
92 rockchip,grf = <&grf>; 137 reg = <0x20080000 0x100>;
93 #address-cells = <1>; 138 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
94 #size-cells = <1>; 139 clocks = <&cru PCLK_GPIO3>;
95 ranges;
96 140
97 gpio0: gpio0@20034000 { 141 gpio-controller;
98 compatible = "rockchip,gpio-bank"; 142 #gpio-cells = <2>;
99 reg = <0x20034000 0x100>;
100 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
101 clocks = <&cru PCLK_GPIO0>;
102 143
103 gpio-controller; 144 interrupt-controller;
104 #gpio-cells = <2>; 145 #interrupt-cells = <2>;
146 };
105 147
106 interrupt-controller; 148 gpio4: gpio4@20084000 {
107 #interrupt-cells = <2>; 149 compatible = "rockchip,gpio-bank";
108 }; 150 reg = <0x20084000 0x100>;
151 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
152 clocks = <&cru PCLK_GPIO4>;
109 153
110 gpio1: gpio1@2003c000 { 154 gpio-controller;
111 compatible = "rockchip,gpio-bank"; 155 #gpio-cells = <2>;
112 reg = <0x2003c000 0x100>;
113 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
114 clocks = <&cru PCLK_GPIO1>;
115 156
116 gpio-controller; 157 interrupt-controller;
117 #gpio-cells = <2>; 158 #interrupt-cells = <2>;
159 };
118 160
119 interrupt-controller; 161 gpio6: gpio6@2000a000 {
120 #interrupt-cells = <2>; 162 compatible = "rockchip,gpio-bank";
121 }; 163 reg = <0x2000a000 0x100>;
164 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&cru PCLK_GPIO6>;
122 166
123 gpio2: gpio2@2003e000 { 167 gpio-controller;
124 compatible = "rockchip,gpio-bank"; 168 #gpio-cells = <2>;
125 reg = <0x2003e000 0x100>;
126 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
127 clocks = <&cru PCLK_GPIO2>;
128 169
129 gpio-controller; 170 interrupt-controller;
130 #gpio-cells = <2>; 171 #interrupt-cells = <2>;
172 };
131 173
132 interrupt-controller; 174 pcfg_pull_default: pcfg_pull_default {
133 #interrupt-cells = <2>; 175 bias-pull-pin-default;
134 }; 176 };
135 177
136 gpio3: gpio3@20080000 { 178 pcfg_pull_none: pcfg_pull_none {
137 compatible = "rockchip,gpio-bank"; 179 bias-disable;
138 reg = <0x20080000 0x100>; 180 };
139 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
140 clocks = <&cru PCLK_GPIO3>;
141 181
142 gpio-controller; 182 uart0 {
143 #gpio-cells = <2>; 183 uart0_xfer: uart0-xfer {
184 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
185 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
186 };
144 187
145 interrupt-controller; 188 uart0_cts: uart0-cts {
146 #interrupt-cells = <2>; 189 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
147 }; 190 };
148 191
149 gpio4: gpio4@20084000 { 192 uart0_rts: uart0-rts {
150 compatible = "rockchip,gpio-bank"; 193 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
151 reg = <0x20084000 0x100>; 194 };
152 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 195 };
153 clocks = <&cru PCLK_GPIO4>;
154 196
155 gpio-controller; 197 uart1 {
156 #gpio-cells = <2>; 198 uart1_xfer: uart1-xfer {
199 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
200 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
201 };
157 202
158 interrupt-controller; 203 uart1_cts: uart1-cts {
159 #interrupt-cells = <2>; 204 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
160 }; 205 };
161 206
162 gpio6: gpio6@2000a000 { 207 uart1_rts: uart1-rts {
163 compatible = "rockchip,gpio-bank"; 208 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
164 reg = <0x2000a000 0x100>; 209 };
165 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 210 };
166 clocks = <&cru PCLK_GPIO6>;
167 211
168 gpio-controller; 212 uart2 {
169 #gpio-cells = <2>; 213 uart2_xfer: uart2-xfer {
214 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
215 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
216 };
217 /* no rts / cts for uart2 */
218 };
170 219
171 interrupt-controller; 220 uart3 {
172 #interrupt-cells = <2>; 221 uart3_xfer: uart3-xfer {
222 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
223 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
173 }; 224 };
174 225
175 pcfg_pull_default: pcfg_pull_default { 226 uart3_cts: uart3-cts {
176 bias-pull-pin-default; 227 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
177 }; 228 };
178 229
179 pcfg_pull_none: pcfg_pull_none { 230 uart3_rts: uart3-rts {
180 bias-disable; 231 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
181 }; 232 };
233 };
182 234
183 uart0 { 235 sd0 {
184 uart0_xfer: uart0-xfer { 236 sd0_clk: sd0-clk {
185 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>, 237 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
186 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>; 238 };
187 };
188 239
189 uart0_cts: uart0-cts { 240 sd0_cmd: sd0-cmd {
190 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>; 241 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
191 }; 242 };
192 243
193 uart0_rts: uart0-rts { 244 sd0_cd: sd0-cd {
194 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>; 245 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
195 };
196 }; 246 };
197 247
198 uart1 { 248 sd0_wp: sd0-wp {
199 uart1_xfer: uart1-xfer { 249 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
200 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>, 250 };
201 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
202 };
203 251
204 uart1_cts: uart1-cts { 252 sd0_bus1: sd0-bus-width1 {
205 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>; 253 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
206 }; 254 };
207 255
208 uart1_rts: uart1-rts { 256 sd0_bus4: sd0-bus-width4 {
209 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>; 257 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
210 }; 258 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
259 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
260 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
211 }; 261 };
262 };
212 263
213 uart2 { 264 sd1 {
214 uart2_xfer: uart2-xfer { 265 sd1_clk: sd1-clk {
215 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>, 266 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
216 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
217 };
218 /* no rts / cts for uart2 */
219 }; 267 };
220 268
221 uart3 { 269 sd1_cmd: sd1-cmd {
222 uart3_xfer: uart3-xfer { 270 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
223 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>, 271 };
224 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
225 };
226 272
227 uart3_cts: uart3-cts { 273 sd1_cd: sd1-cd {
228 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>; 274 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
229 }; 275 };
230 276
231 uart3_rts: uart3-rts { 277 sd1_wp: sd1-wp {
232 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>; 278 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
233 };
234 }; 279 };
235 280
236 sd0 { 281 sd1_bus1: sd1-bus-width1 {
237 sd0_clk: sd0-clk { 282 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
238 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
239 };
240
241 sd0_cmd: sd0-cmd {
242 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
243 };
244
245 sd0_cd: sd0-cd {
246 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
247 };
248
249 sd0_wp: sd0-wp {
250 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
251 };
252
253 sd0_bus1: sd0-bus-width1 {
254 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
255 };
256
257 sd0_bus4: sd0-bus-width4 {
258 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
259 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
260 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
261 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
262 };
263 }; 283 };
264 284
265 sd1 { 285 sd1_bus4: sd1-bus-width4 {
266 sd1_clk: sd1-clk { 286 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
267 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>; 287 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
268 }; 288 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
269 289 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
270 sd1_cmd: sd1-cmd {
271 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
272 };
273
274 sd1_cd: sd1-cd {
275 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
276 };
277
278 sd1_wp: sd1-wp {
279 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
280 };
281
282 sd1_bus1: sd1-bus-width1 {
283 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
284 };
285
286 sd1_bus4: sd1-bus-width4 {
287 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
288 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
289 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
290 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
291 };
292 }; 290 };
293 }; 291 };
294 }; 292 };
diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index a5eee55079cb..7a002f523ec4 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -23,59 +23,56 @@
23 reg = <0x60000000 0x80000000>; 23 reg = <0x60000000 0x80000000>;
24 }; 24 };
25 25
26 soc { 26 uart0: serial@10124000 {
27 uart0: serial@10124000 { 27 status = "okay";
28 status = "okay"; 28 };
29 };
30 29
31 uart1: serial@10126000 { 30 uart1: serial@10126000 {
32 status = "okay"; 31 status = "okay";
33 }; 32 };
34 33
35 uart2: serial@20064000 { 34 uart2: serial@20064000 {
36 pinctrl-names = "default"; 35 pinctrl-names = "default";
37 pinctrl-0 = <&uart2_xfer>; 36 pinctrl-0 = <&uart2_xfer>;
38 status = "okay"; 37 status = "okay";
39 }; 38 };
40 39
41 uart3: serial@20068000 { 40 uart3: serial@20068000 {
42 status = "okay"; 41 status = "okay";
43 }; 42 };
44 43
45 gpio-keys { 44 gpio-keys {
46 compatible = "gpio-keys"; 45 compatible = "gpio-keys";
47 #address-cells = <1>; 46 #address-cells = <1>;
48 #size-cells = <0>; 47 #size-cells = <0>;
49 autorepeat; 48 autorepeat;
50 49
51 button@0 { 50 button@0 {
52 gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; 51 gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
53 linux,code = <116>; 52 linux,code = <116>;
54 label = "GPIO Key Power"; 53 label = "GPIO Key Power";
55 linux,input-type = <1>; 54 linux,input-type = <1>;
56 gpio-key,wakeup = <1>; 55 gpio-key,wakeup = <1>;
57 debounce-interval = <100>; 56 debounce-interval = <100>;
58 };
59 }; 57 };
58 };
60 59
61 gpio-leds { 60 gpio-leds {
62 compatible = "gpio-leds"; 61 compatible = "gpio-leds";
63
64 green {
65 gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
66 default-state = "off";
67 };
68 62
69 yellow { 63 green {
70 gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; 64 gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
71 default-state = "off"; 65 default-state = "off";
72 }; 66 };
73 67
74 sleep { 68 yellow {
75 gpios = <&gpio0 15 0>; 69 gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
76 default-state = "off"; 70 default-state = "off";
77 };
78 }; 71 };
79 72
73 sleep {
74 gpios = <&gpio0 15 0>;
75 default-state = "off";
76 };
80 }; 77 };
81}; 78};
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 0db541c4e7b3..038d9d45264c 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -52,223 +52,221 @@
52 }; 52 };
53 }; 53 };
54 54
55 soc { 55 global-timer@1013c200 {
56 global-timer@1013c200 { 56 interrupts = <GIC_PPI 11 0xf04>;
57 interrupts = <GIC_PPI 11 0xf04>; 57 };
58
59 local-timer@1013c600 {
60 interrupts = <GIC_PPI 13 0xf04>;
61 };
62
63 sram: sram@10080000 {
64 compatible = "mmio-sram";
65 reg = <0x10080000 0x8000>;
66 #address-cells = <1>;
67 #size-cells = <1>;
68 ranges = <0 0x10080000 0x8000>;
69
70 smp-sram@0 {
71 compatible = "rockchip,rk3066-smp-sram";
72 reg = <0x0 0x50>;
58 }; 73 };
74 };
75
76 cru: clock-controller@20000000 {
77 compatible = "rockchip,rk3188-cru";
78 reg = <0x20000000 0x1000>;
79 rockchip,grf = <&grf>;
80
81 #clock-cells = <1>;
82 #reset-cells = <1>;
83 };
59 84
60 local-timer@1013c600 { 85 pinctrl@20008000 {
61 interrupts = <GIC_PPI 13 0xf04>; 86 compatible = "rockchip,rk3188-pinctrl";
87 rockchip,grf = <&grf>;
88 rockchip,pmu = <&pmu>;
89
90 #address-cells = <1>;
91 #size-cells = <1>;
92 ranges;
93
94 gpio0: gpio0@0x2000a000 {
95 compatible = "rockchip,rk3188-gpio-bank0";
96 reg = <0x2000a000 0x100>;
97 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
98 clocks = <&cru PCLK_GPIO0>;
99
100 gpio-controller;
101 #gpio-cells = <2>;
102
103 interrupt-controller;
104 #interrupt-cells = <2>;
62 }; 105 };
63 106
64 sram: sram@10080000 { 107 gpio1: gpio1@0x2003c000 {
65 compatible = "mmio-sram"; 108 compatible = "rockchip,gpio-bank";
66 reg = <0x10080000 0x8000>; 109 reg = <0x2003c000 0x100>;
67 #address-cells = <1>; 110 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
68 #size-cells = <1>; 111 clocks = <&cru PCLK_GPIO1>;
69 ranges = <0 0x10080000 0x8000>;
70 112
71 smp-sram@0 { 113 gpio-controller;
72 compatible = "rockchip,rk3066-smp-sram"; 114 #gpio-cells = <2>;
73 reg = <0x0 0x50>; 115
74 }; 116 interrupt-controller;
117 #interrupt-cells = <2>;
75 }; 118 };
76 119
77 cru: clock-controller@20000000 { 120 gpio2: gpio2@2003e000 {
78 compatible = "rockchip,rk3188-cru"; 121 compatible = "rockchip,gpio-bank";
79 reg = <0x20000000 0x1000>; 122 reg = <0x2003e000 0x100>;
80 rockchip,grf = <&grf>; 123 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
124 clocks = <&cru PCLK_GPIO2>;
125
126 gpio-controller;
127 #gpio-cells = <2>;
81 128
82 #clock-cells = <1>; 129 interrupt-controller;
83 #reset-cells = <1>; 130 #interrupt-cells = <2>;
84 }; 131 };
85 132
86 pinctrl@20008000 { 133 gpio3: gpio3@20080000 {
87 compatible = "rockchip,rk3188-pinctrl"; 134 compatible = "rockchip,gpio-bank";
88 rockchip,grf = <&grf>; 135 reg = <0x20080000 0x100>;
89 rockchip,pmu = <&pmu>; 136 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&cru PCLK_GPIO3>;
90 138
91 #address-cells = <1>; 139 gpio-controller;
92 #size-cells = <1>; 140 #gpio-cells = <2>;
93 ranges;
94 141
95 gpio0: gpio0@0x2000a000 { 142 interrupt-controller;
96 compatible = "rockchip,rk3188-gpio-bank0"; 143 #interrupt-cells = <2>;
97 reg = <0x2000a000 0x100>; 144 };
98 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
99 clocks = <&cru PCLK_GPIO0>;
100 145
101 gpio-controller; 146 pcfg_pull_up: pcfg_pull_up {
102 #gpio-cells = <2>; 147 bias-pull-up;
148 };
103 149
104 interrupt-controller; 150 pcfg_pull_down: pcfg_pull_down {
105 #interrupt-cells = <2>; 151 bias-pull-down;
106 }; 152 };
107 153
108 gpio1: gpio1@0x2003c000 { 154 pcfg_pull_none: pcfg_pull_none {
109 compatible = "rockchip,gpio-bank"; 155 bias-disable;
110 reg = <0x2003c000 0x100>; 156 };
111 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
112 clocks = <&cru PCLK_GPIO1>;
113 157
114 gpio-controller; 158 uart0 {
115 #gpio-cells = <2>; 159 uart0_xfer: uart0-xfer {
160 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
161 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
162 };
116 163
117 interrupt-controller; 164 uart0_cts: uart0-cts {
118 #interrupt-cells = <2>; 165 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
119 }; 166 };
120 167
121 gpio2: gpio2@2003e000 { 168 uart0_rts: uart0-rts {
122 compatible = "rockchip,gpio-bank"; 169 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
123 reg = <0x2003e000 0x100>; 170 };
124 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 171 };
125 clocks = <&cru PCLK_GPIO2>;
126 172
127 gpio-controller; 173 uart1 {
128 #gpio-cells = <2>; 174 uart1_xfer: uart1-xfer {
175 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
176 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
177 };
129 178
130 interrupt-controller; 179 uart1_cts: uart1-cts {
131 #interrupt-cells = <2>; 180 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
132 }; 181 };
133 182
134 gpio3: gpio3@20080000 { 183 uart1_rts: uart1-rts {
135 compatible = "rockchip,gpio-bank"; 184 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
136 reg = <0x20080000 0x100>; 185 };
137 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 186 };
138 clocks = <&cru PCLK_GPIO3>;
139 187
140 gpio-controller; 188 uart2 {
141 #gpio-cells = <2>; 189 uart2_xfer: uart2-xfer {
190 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
191 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
192 };
193 /* no rts / cts for uart2 */
194 };
142 195
143 interrupt-controller; 196 uart3 {
144 #interrupt-cells = <2>; 197 uart3_xfer: uart3-xfer {
198 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
199 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
145 }; 200 };
146 201
147 pcfg_pull_up: pcfg_pull_up { 202 uart3_cts: uart3-cts {
148 bias-pull-up; 203 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
149 }; 204 };
150 205
151 pcfg_pull_down: pcfg_pull_down { 206 uart3_rts: uart3-rts {
152 bias-pull-down; 207 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
153 }; 208 };
209 };
154 210
155 pcfg_pull_none: pcfg_pull_none { 211 sd0 {
156 bias-disable; 212 sd0_clk: sd0-clk {
213 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
157 }; 214 };
158 215
159 uart0 { 216 sd0_cmd: sd0-cmd {
160 uart0_xfer: uart0-xfer { 217 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
161 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>, 218 };
162 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
163 };
164 219
165 uart0_cts: uart0-cts { 220 sd0_cd: sd0-cd {
166 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>; 221 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
167 }; 222 };
168 223
169 uart0_rts: uart0-rts { 224 sd0_wp: sd0-wp {
170 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>; 225 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
171 };
172 }; 226 };
173 227
174 uart1 { 228 sd0_pwr: sd0-pwr {
175 uart1_xfer: uart1-xfer { 229 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
176 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>, 230 };
177 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
178 };
179 231
180 uart1_cts: uart1-cts { 232 sd0_bus1: sd0-bus-width1 {
181 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>; 233 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
182 }; 234 };
183 235
184 uart1_rts: uart1-rts { 236 sd0_bus4: sd0-bus-width4 {
185 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>; 237 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
186 }; 238 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
239 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
240 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
187 }; 241 };
242 };
188 243
189 uart2 { 244 sd1 {
190 uart2_xfer: uart2-xfer { 245 sd1_clk: sd1-clk {
191 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>, 246 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
192 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
193 };
194 /* no rts / cts for uart2 */
195 }; 247 };
196 248
197 uart3 { 249 sd1_cmd: sd1-cmd {
198 uart3_xfer: uart3-xfer { 250 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
199 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>, 251 };
200 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
201 };
202 252
203 uart3_cts: uart3-cts { 253 sd1_cd: sd1-cd {
204 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>; 254 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
205 }; 255 };
206 256
207 uart3_rts: uart3-rts { 257 sd1_wp: sd1-wp {
208 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>; 258 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
209 };
210 }; 259 };
211 260
212 sd0 { 261 sd1_bus1: sd1-bus-width1 {
213 sd0_clk: sd0-clk { 262 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
214 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
215 };
216
217 sd0_cmd: sd0-cmd {
218 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
219 };
220
221 sd0_cd: sd0-cd {
222 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
223 };
224
225 sd0_wp: sd0-wp {
226 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
227 };
228
229 sd0_pwr: sd0-pwr {
230 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
231 };
232
233 sd0_bus1: sd0-bus-width1 {
234 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
235 };
236
237 sd0_bus4: sd0-bus-width4 {
238 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
239 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
240 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
241 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
242 };
243 }; 263 };
244 264
245 sd1 { 265 sd1_bus4: sd1-bus-width4 {
246 sd1_clk: sd1-clk { 266 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
247 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>; 267 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
248 }; 268 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
249 269 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
250 sd1_cmd: sd1-cmd {
251 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
252 };
253
254 sd1_cd: sd1-cd {
255 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
256 };
257
258 sd1_wp: sd1-wp {
259 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
260 };
261
262 sd1_bus1: sd1-bus-width1 {
263 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
264 };
265
266 sd1_bus4: sd1-bus-width4 {
267 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
268 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
269 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
270 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
271 };
272 }; 270 };
273 }; 271 };
274 }; 272 };
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 6d163644c7cd..f70addd793a7 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -27,120 +27,113 @@
27 clock-output-names = "xin24m"; 27 clock-output-names = "xin24m";
28 }; 28 };
29 29
30 soc { 30 scu@1013c000 {
31 compatible = "arm,cortex-a9-scu";
32 reg = <0x1013c000 0x100>;
33 };
34
35 pmu: pmu@20004000 {
36 compatible = "rockchip,rk3066-pmu", "syscon";
37 reg = <0x20004000 0x100>;
38 };
39
40 grf: grf@20008000 {
41 compatible = "syscon";
42 reg = <0x20008000 0x200>;
43 };
44
45 gic: interrupt-controller@1013d000 {
46 compatible = "arm,cortex-a9-gic";
47 interrupt-controller;
48 #interrupt-cells = <3>;
49 reg = <0x1013d000 0x1000>,
50 <0x1013c100 0x0100>;
51 };
52
53 L2: l2-cache-controller@10138000 {
54 compatible = "arm,pl310-cache";
55 reg = <0x10138000 0x1000>;
56 cache-unified;
57 cache-level = <2>;
58 };
59
60 global-timer@1013c200 {
61 compatible = "arm,cortex-a9-global-timer";
62 reg = <0x1013c200 0x20>;
63 interrupts = <GIC_PPI 11 0x304>;
64 clocks = <&cru CORE_PERI>;
65 };
66
67 local-timer@1013c600 {
68 compatible = "arm,cortex-a9-twd-timer";
69 reg = <0x1013c600 0x20>;
70 interrupts = <GIC_PPI 13 0x304>;
71 clocks = <&cru CORE_PERI>;
72 };
73
74 uart0: serial@10124000 {
75 compatible = "snps,dw-apb-uart";
76 reg = <0x10124000 0x400>;
77 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
78 reg-shift = <2>;
79 reg-io-width = <1>;
80 clocks = <&cru SCLK_UART0>;
81 status = "disabled";
82 };
83
84 uart1: serial@10126000 {
85 compatible = "snps,dw-apb-uart";
86 reg = <0x10126000 0x400>;
87 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
88 reg-shift = <2>;
89 reg-io-width = <1>;
90 clocks = <&cru SCLK_UART1>;
91 status = "disabled";
92 };
93
94 uart2: serial@20064000 {
95 compatible = "snps,dw-apb-uart";
96 reg = <0x20064000 0x400>;
97 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
98 reg-shift = <2>;
99 reg-io-width = <1>;
100 clocks = <&cru SCLK_UART2>;
101 status = "disabled";
102 };
103
104 uart3: serial@20068000 {
105 compatible = "snps,dw-apb-uart";
106 reg = <0x20068000 0x400>;
107 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
108 reg-shift = <2>;
109 reg-io-width = <1>;
110 clocks = <&cru SCLK_UART3>;
111 status = "disabled";
112 };
113
114 dwmmc@10214000 {
115 compatible = "rockchip,rk2928-dw-mshc";
116 reg = <0x10214000 0x1000>;
117 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
31 #address-cells = <1>; 118 #address-cells = <1>;
32 #size-cells = <1>; 119 #size-cells = <0>;
33 compatible = "simple-bus"; 120
34 ranges; 121 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
35 122 clock-names = "biu", "ciu";
36 scu@1013c000 { 123
37 compatible = "arm,cortex-a9-scu"; 124 status = "disabled";
38 reg = <0x1013c000 0x100>; 125 };
39 }; 126
40 127 dwmmc@10218000 {
41 pmu: pmu@20004000 { 128 compatible = "rockchip,rk2928-dw-mshc";
42 compatible = "rockchip,rk3066-pmu", "syscon"; 129 reg = <0x10218000 0x1000>;
43 reg = <0x20004000 0x100>; 130 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
44 }; 131 #address-cells = <1>;
45 132 #size-cells = <0>;
46 grf: grf@20008000 { 133
47 compatible = "syscon"; 134 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
48 reg = <0x20008000 0x200>; 135 clock-names = "biu", "ciu";
49 }; 136
50 137 status = "disabled";
51 gic: interrupt-controller@1013d000 {
52 compatible = "arm,cortex-a9-gic";
53 interrupt-controller;
54 #interrupt-cells = <3>;
55 reg = <0x1013d000 0x1000>,
56 <0x1013c100 0x0100>;
57 };
58
59 L2: l2-cache-controller@10138000 {
60 compatible = "arm,pl310-cache";
61 reg = <0x10138000 0x1000>;
62 cache-unified;
63 cache-level = <2>;
64 };
65
66 global-timer@1013c200 {
67 compatible = "arm,cortex-a9-global-timer";
68 reg = <0x1013c200 0x20>;
69 interrupts = <GIC_PPI 11 0x304>;
70 clocks = <&cru CORE_PERI>;
71 };
72
73 local-timer@1013c600 {
74 compatible = "arm,cortex-a9-twd-timer";
75 reg = <0x1013c600 0x20>;
76 interrupts = <GIC_PPI 13 0x304>;
77 clocks = <&cru CORE_PERI>;
78 };
79
80 uart0: serial@10124000 {
81 compatible = "snps,dw-apb-uart";
82 reg = <0x10124000 0x400>;
83 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
84 reg-shift = <2>;
85 reg-io-width = <1>;
86 clocks = <&cru SCLK_UART0>;
87 status = "disabled";
88 };
89
90 uart1: serial@10126000 {
91 compatible = "snps,dw-apb-uart";
92 reg = <0x10126000 0x400>;
93 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
94 reg-shift = <2>;
95 reg-io-width = <1>;
96 clocks = <&cru SCLK_UART1>;
97 status = "disabled";
98 };
99
100 uart2: serial@20064000 {
101 compatible = "snps,dw-apb-uart";
102 reg = <0x20064000 0x400>;
103 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
104 reg-shift = <2>;
105 reg-io-width = <1>;
106 clocks = <&cru SCLK_UART2>;
107 status = "disabled";
108 };
109
110 uart3: serial@20068000 {
111 compatible = "snps,dw-apb-uart";
112 reg = <0x20068000 0x400>;
113 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
114 reg-shift = <2>;
115 reg-io-width = <1>;
116 clocks = <&cru SCLK_UART3>;
117 status = "disabled";
118 };
119
120 dwmmc@10214000 {
121 compatible = "rockchip,rk2928-dw-mshc";
122 reg = <0x10214000 0x1000>;
123 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
124 #address-cells = <1>;
125 #size-cells = <0>;
126
127 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
128 clock-names = "biu", "ciu";
129
130 status = "disabled";
131 };
132
133 dwmmc@10218000 {
134 compatible = "rockchip,rk2928-dw-mshc";
135 reg = <0x10218000 0x1000>;
136 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
137 #address-cells = <1>;
138 #size-cells = <0>;
139
140 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
141 clock-names = "biu", "ciu";
142
143 status = "disabled";
144 };
145 }; 138 };
146}; 139};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-13 18:19:40 -0500