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authorLinus Walleij <linus.walleij@linaro.org>2015-01-30 04:38:15 -0500
committerLinus Walleij <linus.walleij@linaro.org>2015-01-30 04:38:15 -0500
commitb6afdbe8e841e20297a38e2af0a053d8eb26c19b (patch)
tree4a336799dcd7d77a7d1f1e9b46b9e48551053524 /arch/arm
parent8090f7917b5d7cc2390afe33cb12f819173ef9c8 (diff)
parent26bc420b59a38e4e6685a73345a0def461136dce (diff)
Merge tag 'v3.19-rc6' into devel
Linux 3.19-rc6
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/armada-370-db.dts24
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi2
-rw-r--r--arch/arm/boot/dts/berlin2q-marvell-dmp.dts2
-rw-r--r--arch/arm/boot/dts/berlin2q.dtsi63
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts10
-rw-r--r--arch/arm/boot/dts/dra7.dtsi6
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos5420-arndale-octa.dts4
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi6
-rw-r--r--arch/arm/boot/dts/imx25.dtsi10
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts22
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi4
-rw-r--r--arch/arm/boot/dts/imx6sx-sdb.dts15
-rw-r--r--arch/arm/boot/dts/ls1021a.dtsi1
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts4
-rw-r--r--arch/arm/boot/dts/rk3288-evb.dtsi30
-rw-r--r--arch/arm/boot/dts/sama5d3xmb.dtsi2
-rw-r--r--arch/arm/boot/dts/sama5d4.dtsi2
-rw-r--r--arch/arm/boot/dts/ste-nomadik-nhk15.dts8
-rw-r--r--arch/arm/boot/dts/tegra20-seaboard.dts2
-rw-r--r--arch/arm/boot/dts/vf610-twr.dts15
-rw-r--r--arch/arm/configs/exynos_defconfig18
-rw-r--r--arch/arm/configs/multi_v7_defconfig1
-rw-r--r--arch/arm/configs/omap2plus_defconfig2
-rw-r--r--arch/arm/include/uapi/asm/unistd.h1
-rw-r--r--arch/arm/kernel/calls.S1
-rw-r--r--arch/arm/kernel/entry-header.S13
-rw-r--r--arch/arm/kernel/perf_event.c10
-rw-r--r--arch/arm/kernel/perf_regs.c8
-rw-r--r--arch/arm/kernel/setup.c16
-rw-r--r--arch/arm/kernel/smp.c12
-rw-r--r--arch/arm/mach-at91/board-dt-sama5.c18
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c2
-rw-r--r--arch/arm/mach-imx/clk-imx6sx.c3
-rw-r--r--arch/arm/mach-mvebu/coherency.c7
-rw-r--r--arch/arm/mach-omap2/board-generic.c18
-rw-r--r--arch/arm/mach-omap2/common.h2
-rw-r--r--arch/arm/mach-omap2/control.h4
-rw-r--r--arch/arm/mach-omap2/omap-headsmp.S21
-rw-r--r--arch/arm/mach-omap2/omap-smp.c13
-rw-r--r--arch/arm/mach-omap2/omap4-common.c32
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c10
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.h1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c5
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_54xx_data.c1
-rw-r--r--arch/arm/mach-omap2/prcm-common.h1
-rw-r--r--arch/arm/mach-omap2/prm44xx.c5
-rw-r--r--arch/arm/mach-omap2/prm_common.c14
-rw-r--r--arch/arm/mach-omap2/timer.c44
-rw-r--r--arch/arm/mach-omap2/twl-common.c7
-rw-r--r--arch/arm/mach-rockchip/rockchip.c27
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7740.c7
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7778.c9
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7779.c9
-rw-r--r--arch/arm/mach-shmobile/setup-sh73a0.c3
-rw-r--r--arch/arm/mm/dump.c9
-rw-r--r--arch/arm/mm/init.c4
-rw-r--r--arch/arm/mm/mmu.c4
58 files changed, 457 insertions, 139 deletions
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index 1466580be295..70b1943a86b1 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -203,27 +203,3 @@
203 compatible = "linux,spdif-dir"; 203 compatible = "linux,spdif-dir";
204 }; 204 };
205}; 205};
206
207&pinctrl {
208 /*
209 * These pins might be muxed as I2S by
210 * the bootloader, but it conflicts
211 * with the real I2S pins that are
212 * muxed using i2s_pins. We must mux
213 * those pins to a function other than
214 * I2S.
215 */
216 pinctrl-0 = <&hog_pins1 &hog_pins2>;
217 pinctrl-names = "default";
218
219 hog_pins1: hog-pins1 {
220 marvell,pins = "mpp6", "mpp8", "mpp10",
221 "mpp12", "mpp13";
222 marvell,function = "gpio";
223 };
224
225 hog_pins2: hog-pins2 {
226 marvell,pins = "mpp5", "mpp7", "mpp9";
227 marvell,function = "gpo";
228 };
229};
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 1467750e3377..e8c6c600a5b6 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -953,6 +953,8 @@
953 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>; 953 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>;
954 pinctrl-names = "default"; 954 pinctrl-names = "default";
955 pinctrl-0 = <&pinctrl_fb>; 955 pinctrl-0 = <&pinctrl_fb>;
956 clocks = <&lcd_clk>, <&lcd_clk>;
957 clock-names = "lcdc_clk", "hclk";
956 status = "disabled"; 958 status = "disabled";
957 }; 959 };
958 960
diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
index 28e7e2060c33..a98ac1bd8f65 100644
--- a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
+++ b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
@@ -65,6 +65,8 @@
65}; 65};
66 66
67&sdhci2 { 67&sdhci2 {
68 broken-cd;
69 bus-width = <8>;
68 non-removable; 70 non-removable;
69 status = "okay"; 71 status = "okay";
70}; 72};
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 35253c947a7c..e2f61f27944e 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -83,7 +83,8 @@
83 compatible = "mrvl,pxav3-mmc"; 83 compatible = "mrvl,pxav3-mmc";
84 reg = <0xab1000 0x200>; 84 reg = <0xab1000 0x200>;
85 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 85 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
86 clocks = <&chip CLKID_SDIO1XIN>; 86 clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>;
87 clock-names = "io", "core";
87 status = "disabled"; 88 status = "disabled";
88 }; 89 };
89 90
@@ -348,36 +349,6 @@
348 interrupt-parent = <&gic>; 349 interrupt-parent = <&gic>;
349 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 350 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
350 }; 351 };
351
352 gpio4: gpio@5000 {
353 compatible = "snps,dw-apb-gpio";
354 reg = <0x5000 0x400>;
355 #address-cells = <1>;
356 #size-cells = <0>;
357
358 porte: gpio-port@4 {
359 compatible = "snps,dw-apb-gpio-port";
360 gpio-controller;
361 #gpio-cells = <2>;
362 snps,nr-gpios = <32>;
363 reg = <0>;
364 };
365 };
366
367 gpio5: gpio@c000 {
368 compatible = "snps,dw-apb-gpio";
369 reg = <0xc000 0x400>;
370 #address-cells = <1>;
371 #size-cells = <0>;
372
373 portf: gpio-port@5 {
374 compatible = "snps,dw-apb-gpio-port";
375 gpio-controller;
376 #gpio-cells = <2>;
377 snps,nr-gpios = <32>;
378 reg = <0>;
379 };
380 };
381 }; 352 };
382 353
383 chip: chip-control@ea0000 { 354 chip: chip-control@ea0000 {
@@ -466,6 +437,21 @@
466 ranges = <0 0xfc0000 0x10000>; 437 ranges = <0 0xfc0000 0x10000>;
467 interrupt-parent = <&sic>; 438 interrupt-parent = <&sic>;
468 439
440 sm_gpio1: gpio@5000 {
441 compatible = "snps,dw-apb-gpio";
442 reg = <0x5000 0x400>;
443 #address-cells = <1>;
444 #size-cells = <0>;
445
446 portf: gpio-port@5 {
447 compatible = "snps,dw-apb-gpio-port";
448 gpio-controller;
449 #gpio-cells = <2>;
450 snps,nr-gpios = <32>;
451 reg = <0>;
452 };
453 };
454
469 i2c2: i2c@7000 { 455 i2c2: i2c@7000 {
470 compatible = "snps,designware-i2c"; 456 compatible = "snps,designware-i2c";
471 #address-cells = <1>; 457 #address-cells = <1>;
@@ -516,6 +502,21 @@
516 status = "disabled"; 502 status = "disabled";
517 }; 503 };
518 504
505 sm_gpio0: gpio@c000 {
506 compatible = "snps,dw-apb-gpio";
507 reg = <0xc000 0x400>;
508 #address-cells = <1>;
509 #size-cells = <0>;
510
511 porte: gpio-port@4 {
512 compatible = "snps,dw-apb-gpio-port";
513 gpio-controller;
514 #gpio-cells = <2>;
515 snps,nr-gpios = <32>;
516 reg = <0>;
517 };
518 };
519
519 sysctrl: pin-controller@d000 { 520 sysctrl: pin-controller@d000 {
520 compatible = "marvell,berlin2q-system-ctrl"; 521 compatible = "marvell,berlin2q-system-ctrl";
521 reg = <0xd000 0x100>; 522 reg = <0xd000 0x100>;
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 10b725c7bfc0..ad4118f7e1a6 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -499,23 +499,23 @@
499 }; 499 };
500 partition@5 { 500 partition@5 {
501 label = "QSPI.u-boot-spl-os"; 501 label = "QSPI.u-boot-spl-os";
502 reg = <0x00140000 0x00010000>; 502 reg = <0x00140000 0x00080000>;
503 }; 503 };
504 partition@6 { 504 partition@6 {
505 label = "QSPI.u-boot-env"; 505 label = "QSPI.u-boot-env";
506 reg = <0x00150000 0x00010000>; 506 reg = <0x001c0000 0x00010000>;
507 }; 507 };
508 partition@7 { 508 partition@7 {
509 label = "QSPI.u-boot-env.backup1"; 509 label = "QSPI.u-boot-env.backup1";
510 reg = <0x00160000 0x0010000>; 510 reg = <0x001d0000 0x0010000>;
511 }; 511 };
512 partition@8 { 512 partition@8 {
513 label = "QSPI.kernel"; 513 label = "QSPI.kernel";
514 reg = <0x00170000 0x0800000>; 514 reg = <0x001e0000 0x0800000>;
515 }; 515 };
516 partition@9 { 516 partition@9 {
517 label = "QSPI.file-system"; 517 label = "QSPI.file-system";
518 reg = <0x00970000 0x01690000>; 518 reg = <0x009e0000 0x01620000>;
519 }; 519 };
520 }; 520 };
521}; 521};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 22771bc1643a..63f8b007bdc5 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1257,6 +1257,8 @@
1257 tx-fifo-resize; 1257 tx-fifo-resize;
1258 maximum-speed = "super-speed"; 1258 maximum-speed = "super-speed";
1259 dr_mode = "otg"; 1259 dr_mode = "otg";
1260 snps,dis_u3_susphy_quirk;
1261 snps,dis_u2_susphy_quirk;
1260 }; 1262 };
1261 }; 1263 };
1262 1264
@@ -1278,6 +1280,8 @@
1278 tx-fifo-resize; 1280 tx-fifo-resize;
1279 maximum-speed = "high-speed"; 1281 maximum-speed = "high-speed";
1280 dr_mode = "otg"; 1282 dr_mode = "otg";
1283 snps,dis_u3_susphy_quirk;
1284 snps,dis_u2_susphy_quirk;
1281 }; 1285 };
1282 }; 1286 };
1283 1287
@@ -1299,6 +1303,8 @@
1299 tx-fifo-resize; 1303 tx-fifo-resize;
1300 maximum-speed = "high-speed"; 1304 maximum-speed = "high-speed";
1301 dr_mode = "otg"; 1305 dr_mode = "otg";
1306 snps,dis_u3_susphy_quirk;
1307 snps,dis_u2_susphy_quirk;
1302 }; 1308 };
1303 }; 1309 };
1304 1310
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 0a229fcd7acf..d75c89d7666a 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -736,7 +736,7 @@
736 736
737 dp_phy: video-phy@10040720 { 737 dp_phy: video-phy@10040720 {
738 compatible = "samsung,exynos5250-dp-video-phy"; 738 compatible = "samsung,exynos5250-dp-video-phy";
739 reg = <0x10040720 4>; 739 samsung,pmu-syscon = <&pmu_system_controller>;
740 #phy-cells = <0>; 740 #phy-cells = <0>;
741 }; 741 };
742 742
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index aa7a7d727a7e..db2c1c4cd900 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -372,3 +372,7 @@
372&usbdrd_dwc3_1 { 372&usbdrd_dwc3_1 {
373 dr_mode = "host"; 373 dr_mode = "host";
374}; 374};
375
376&cci {
377 status = "disabled";
378};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 517e50f6760b..6d38f8bfd0e6 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -120,7 +120,7 @@
120 }; 120 };
121 }; 121 };
122 122
123 cci@10d20000 { 123 cci: cci@10d20000 {
124 compatible = "arm,cci-400"; 124 compatible = "arm,cci-400";
125 #address-cells = <1>; 125 #address-cells = <1>;
126 #size-cells = <1>; 126 #size-cells = <1>;
@@ -503,8 +503,8 @@
503 }; 503 };
504 504
505 dp_phy: video-phy@10040728 { 505 dp_phy: video-phy@10040728 {
506 compatible = "samsung,exynos5250-dp-video-phy"; 506 compatible = "samsung,exynos5420-dp-video-phy";
507 reg = <0x10040728 4>; 507 samsung,pmu-syscon = <&pmu_system_controller>;
508 #phy-cells = <0>; 508 #phy-cells = <0>;
509 }; 509 };
510 510
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index 58d3c3cf2923..e4d3aecc4ed2 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -162,7 +162,7 @@
162 #size-cells = <0>; 162 #size-cells = <0>;
163 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; 163 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
164 reg = <0x43fa4000 0x4000>; 164 reg = <0x43fa4000 0x4000>;
165 clocks = <&clks 62>, <&clks 62>; 165 clocks = <&clks 78>, <&clks 78>;
166 clock-names = "ipg", "per"; 166 clock-names = "ipg", "per";
167 interrupts = <14>; 167 interrupts = <14>;
168 status = "disabled"; 168 status = "disabled";
@@ -369,7 +369,7 @@
369 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; 369 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
370 #pwm-cells = <2>; 370 #pwm-cells = <2>;
371 reg = <0x53fa0000 0x4000>; 371 reg = <0x53fa0000 0x4000>;
372 clocks = <&clks 106>, <&clks 36>; 372 clocks = <&clks 106>, <&clks 52>;
373 clock-names = "ipg", "per"; 373 clock-names = "ipg", "per";
374 interrupts = <36>; 374 interrupts = <36>;
375 }; 375 };
@@ -388,7 +388,7 @@
388 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; 388 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
389 #pwm-cells = <2>; 389 #pwm-cells = <2>;
390 reg = <0x53fa8000 0x4000>; 390 reg = <0x53fa8000 0x4000>;
391 clocks = <&clks 107>, <&clks 36>; 391 clocks = <&clks 107>, <&clks 52>;
392 clock-names = "ipg", "per"; 392 clock-names = "ipg", "per";
393 interrupts = <41>; 393 interrupts = <41>;
394 }; 394 };
@@ -429,7 +429,7 @@
429 pwm4: pwm@53fc8000 { 429 pwm4: pwm@53fc8000 {
430 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; 430 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
431 reg = <0x53fc8000 0x4000>; 431 reg = <0x53fc8000 0x4000>;
432 clocks = <&clks 108>, <&clks 36>; 432 clocks = <&clks 108>, <&clks 52>;
433 clock-names = "ipg", "per"; 433 clock-names = "ipg", "per";
434 interrupts = <42>; 434 interrupts = <42>;
435 }; 435 };
@@ -476,7 +476,7 @@
476 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; 476 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
477 #pwm-cells = <2>; 477 #pwm-cells = <2>;
478 reg = <0x53fe0000 0x4000>; 478 reg = <0x53fe0000 0x4000>;
479 clocks = <&clks 105>, <&clks 36>; 479 clocks = <&clks 105>, <&clks 52>;
480 clock-names = "ipg", "per"; 480 clock-names = "ipg", "per";
481 interrupts = <26>; 481 interrupts = <26>;
482 }; 482 };
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 56569cecaa78..649befeb2cf9 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -127,24 +127,12 @@
127 #address-cells = <1>; 127 #address-cells = <1>;
128 #size-cells = <0>; 128 #size-cells = <0>;
129 129
130 reg_usbh1_vbus: regulator@0 { 130 reg_hub_reset: regulator@0 {
131 compatible = "regulator-fixed";
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_usbh1reg>;
134 reg = <0>;
135 regulator-name = "usbh1_vbus";
136 regulator-min-microvolt = <5000000>;
137 regulator-max-microvolt = <5000000>;
138 gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>;
139 enable-active-high;
140 };
141
142 reg_usbotg_vbus: regulator@1 {
143 compatible = "regulator-fixed"; 131 compatible = "regulator-fixed";
144 pinctrl-names = "default"; 132 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_usbotgreg>; 133 pinctrl-0 = <&pinctrl_usbotgreg>;
146 reg = <1>; 134 reg = <0>;
147 regulator-name = "usbotg_vbus"; 135 regulator-name = "hub_reset";
148 regulator-min-microvolt = <5000000>; 136 regulator-min-microvolt = <5000000>;
149 regulator-max-microvolt = <5000000>; 137 regulator-max-microvolt = <5000000>;
150 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; 138 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
@@ -176,6 +164,7 @@
176 reg = <0>; 164 reg = <0>;
177 clocks = <&clks IMX5_CLK_DUMMY>; 165 clocks = <&clks IMX5_CLK_DUMMY>;
178 clock-names = "main_clk"; 166 clock-names = "main_clk";
167 reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
179 }; 168 };
180 }; 169 };
181}; 170};
@@ -419,7 +408,7 @@
419&usbh1 { 408&usbh1 {
420 pinctrl-names = "default"; 409 pinctrl-names = "default";
421 pinctrl-0 = <&pinctrl_usbh1>; 410 pinctrl-0 = <&pinctrl_usbh1>;
422 vbus-supply = <&reg_usbh1_vbus>; 411 vbus-supply = <&reg_hub_reset>;
423 fsl,usbphy = <&usbh1phy>; 412 fsl,usbphy = <&usbh1phy>;
424 phy_type = "ulpi"; 413 phy_type = "ulpi";
425 status = "okay"; 414 status = "okay";
@@ -429,7 +418,6 @@
429 dr_mode = "otg"; 418 dr_mode = "otg";
430 disable-over-current; 419 disable-over-current;
431 phy_type = "utmi_wide"; 420 phy_type = "utmi_wide";
432 vbus-supply = <&reg_usbotg_vbus>;
433 status = "okay"; 421 status = "okay";
434}; 422};
435 423
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 4fc03b7f1cee..2109d0763c1b 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -335,8 +335,8 @@
335 vpu: vpu@02040000 { 335 vpu: vpu@02040000 {
336 compatible = "cnm,coda960"; 336 compatible = "cnm,coda960";
337 reg = <0x02040000 0x3c000>; 337 reg = <0x02040000 0x3c000>;
338 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>, 338 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
339 <0 12 IRQ_TYPE_LEVEL_HIGH>; 339 <0 3 IRQ_TYPE_LEVEL_HIGH>;
340 interrupt-names = "bit", "jpeg"; 340 interrupt-names = "bit", "jpeg";
341 clocks = <&clks IMX6QDL_CLK_VPU_AXI>, 341 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
342 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>, 342 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>,
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index 1e6e5cc1c14c..8c1febd7e3f2 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -159,13 +159,28 @@
159 pinctrl-0 = <&pinctrl_enet1>; 159 pinctrl-0 = <&pinctrl_enet1>;
160 phy-supply = <&reg_enet_3v3>; 160 phy-supply = <&reg_enet_3v3>;
161 phy-mode = "rgmii"; 161 phy-mode = "rgmii";
162 phy-handle = <&ethphy1>;
162 status = "okay"; 163 status = "okay";
164
165 mdio {
166 #address-cells = <1>;
167 #size-cells = <0>;
168
169 ethphy1: ethernet-phy@0 {
170 reg = <0>;
171 };
172
173 ethphy2: ethernet-phy@1 {
174 reg = <1>;
175 };
176 };
163}; 177};
164 178
165&fec2 { 179&fec2 {
166 pinctrl-names = "default"; 180 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_enet2>; 181 pinctrl-0 = <&pinctrl_enet2>;
168 phy-mode = "rgmii"; 182 phy-mode = "rgmii";
183 phy-handle = <&ethphy2>;
169 status = "okay"; 184 status = "okay";
170}; 185};
171 186
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 657da14cb4b5..c70bb27ac65a 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -142,6 +142,7 @@
142 scfg: scfg@1570000 { 142 scfg: scfg@1570000 {
143 compatible = "fsl,ls1021a-scfg", "syscon"; 143 compatible = "fsl,ls1021a-scfg", "syscon";
144 reg = <0x0 0x1570000 0x0 0x10000>; 144 reg = <0x0 0x1570000 0x0 0x10000>;
145 big-endian;
145 }; 146 };
146 147
147 clockgen: clocking@1ee1000 { 148 clockgen: clocking@1ee1000 {
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 53f3ca064140..b550c41b46f1 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -700,11 +700,9 @@
700 }; 700 };
701 }; 701 };
702 702
703 /* Ethernet is on some early development boards and qemu */
703 ethernet@gpmc { 704 ethernet@gpmc {
704 compatible = "smsc,lan91c94"; 705 compatible = "smsc,lan91c94";
705
706 status = "disabled";
707
708 interrupt-parent = <&gpio2>; 706 interrupt-parent = <&gpio2>;
709 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */ 707 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */
710 reg = <1 0x300 0xf>; /* 16 byte IO range at offset 0x300 */ 708 reg = <1 0x300 0xf>; /* 16 byte IO range at offset 0x300 */
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
index 3e067dd65d0c..6194d673e80b 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -155,6 +155,15 @@
155}; 155};
156 156
157&pinctrl { 157&pinctrl {
158 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
159 drive-strength = <8>;
160 };
161
162 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
163 bias-pull-up;
164 drive-strength = <8>;
165 };
166
158 backlight { 167 backlight {
159 bl_en: bl-en { 168 bl_en: bl-en {
160 rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; 169 rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -173,6 +182,27 @@
173 }; 182 };
174 }; 183 };
175 184
185 sdmmc {
186 /*
187 * Default drive strength isn't enough to achieve even
188 * high-speed mode on EVB board so bump up to 8ma.
189 */
190 sdmmc_bus4: sdmmc-bus4 {
191 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
192 <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
193 <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
194 <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
195 };
196
197 sdmmc_clk: sdmmc-clk {
198 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
199 };
200
201 sdmmc_cmd: sdmmc-cmd {
202 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
203 };
204 };
205
176 usb { 206 usb {
177 host_vbus_drv: host-vbus-drv { 207 host_vbus_drv: host-vbus-drv {
178 rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; 208 rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi
index 49c10d33df30..77e03655aca3 100644
--- a/arch/arm/boot/dts/sama5d3xmb.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -176,7 +176,7 @@
176 "Headphone Jack", "HPOUTR", 176 "Headphone Jack", "HPOUTR",
177 "IN2L", "Line In Jack", 177 "IN2L", "Line In Jack",
178 "IN2R", "Line In Jack", 178 "IN2R", "Line In Jack",
179 "MICBIAS", "IN1L", 179 "Mic", "MICBIAS",
180 "IN1L", "Mic"; 180 "IN1L", "Mic";
181 181
182 atmel,ssc-controller = <&ssc0>; 182 atmel,ssc-controller = <&ssc0>;
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index 1b0f30c2c4a5..b94995d1889f 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -1008,7 +1008,7 @@
1008 1008
1009 pit: timer@fc068630 { 1009 pit: timer@fc068630 {
1010 compatible = "atmel,at91sam9260-pit"; 1010 compatible = "atmel,at91sam9260-pit";
1011 reg = <0xfc068630 0xf>; 1011 reg = <0xfc068630 0x10>;
1012 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; 1012 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1013 clocks = <&h32ck>; 1013 clocks = <&h32ck>;
1014 }; 1014 };
diff --git a/arch/arm/boot/dts/ste-nomadik-nhk15.dts b/arch/arm/boot/dts/ste-nomadik-nhk15.dts
index a8c00ee7522a..3d0b8755caee 100644
--- a/arch/arm/boot/dts/ste-nomadik-nhk15.dts
+++ b/arch/arm/boot/dts/ste-nomadik-nhk15.dts
@@ -25,11 +25,11 @@
25 stmpe2401_1 { 25 stmpe2401_1 {
26 stmpe2401_1_nhk_mode: stmpe2401_1_nhk { 26 stmpe2401_1_nhk_mode: stmpe2401_1_nhk {
27 nhk_cfg1 { 27 nhk_cfg1 {
28 ste,pins = "GPIO76_B20"; // IRQ line 28 pins = "GPIO76_B20"; // IRQ line
29 ste,input = <0>; 29 ste,input = <0>;
30 }; 30 };
31 nhk_cfg2 { 31 nhk_cfg2 {
32 ste,pins = "GPIO77_B8"; // reset line 32 pins = "GPIO77_B8"; // reset line
33 ste,output = <1>; 33 ste,output = <1>;
34 }; 34 };
35 }; 35 };
@@ -37,11 +37,11 @@
37 stmpe2401_2 { 37 stmpe2401_2 {
38 stmpe2401_2_nhk_mode: stmpe2401_2_nhk { 38 stmpe2401_2_nhk_mode: stmpe2401_2_nhk {
39 nhk_cfg1 { 39 nhk_cfg1 {
40 ste,pins = "GPIO78_A8"; // IRQ line 40 pins = "GPIO78_A8"; // IRQ line
41 ste,input = <0>; 41 ste,input = <0>;
42 }; 42 };
43 nhk_cfg2 { 43 nhk_cfg2 {
44 ste,pins = "GPIO79_C9"; // reset line 44 pins = "GPIO79_C9"; // reset line
45 ste,output = <1>; 45 ste,output = <1>;
46 }; 46 };
47 }; 47 };
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index ea282c7c0ca5..e2fed2712249 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -406,7 +406,7 @@
406 clock-frequency = <400000>; 406 clock-frequency = <400000>;
407 407
408 magnetometer@c { 408 magnetometer@c {
409 compatible = "ak,ak8975"; 409 compatible = "asahi-kasei,ak8975";
410 reg = <0xc>; 410 reg = <0xc>;
411 interrupt-parent = <&gpio>; 411 interrupt-parent = <&gpio>;
412 interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>; 412 interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index a0f762159cb2..f2b64b1b00fa 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -129,13 +129,28 @@
129 129
130&fec0 { 130&fec0 {
131 phy-mode = "rmii"; 131 phy-mode = "rmii";
132 phy-handle = <&ethphy0>;
132 pinctrl-names = "default"; 133 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_fec0>; 134 pinctrl-0 = <&pinctrl_fec0>;
134 status = "okay"; 135 status = "okay";
136
137 mdio {
138 #address-cells = <1>;
139 #size-cells = <0>;
140
141 ethphy0: ethernet-phy@0 {
142 reg = <0>;
143 };
144
145 ethphy1: ethernet-phy@1 {
146 reg = <1>;
147 };
148 };
135}; 149};
136 150
137&fec1 { 151&fec1 {
138 phy-mode = "rmii"; 152 phy-mode = "rmii";
153 phy-handle = <&ethphy1>;
139 pinctrl-names = "default"; 154 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_fec1>; 155 pinctrl-0 = <&pinctrl_fec1>;
141 status = "okay"; 156 status = "okay";
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index 5ef14de00a29..3d0c5d65c741 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -84,7 +84,8 @@ CONFIG_DEBUG_GPIO=y
84CONFIG_POWER_SUPPLY=y 84CONFIG_POWER_SUPPLY=y
85CONFIG_BATTERY_SBS=y 85CONFIG_BATTERY_SBS=y
86CONFIG_CHARGER_TPS65090=y 86CONFIG_CHARGER_TPS65090=y
87# CONFIG_HWMON is not set 87CONFIG_HWMON=y
88CONFIG_SENSORS_LM90=y
88CONFIG_THERMAL=y 89CONFIG_THERMAL=y
89CONFIG_EXYNOS_THERMAL=y 90CONFIG_EXYNOS_THERMAL=y
90CONFIG_EXYNOS_THERMAL_CORE=y 91CONFIG_EXYNOS_THERMAL_CORE=y
@@ -109,11 +110,26 @@ CONFIG_REGULATOR_S2MPA01=y
109CONFIG_REGULATOR_S2MPS11=y 110CONFIG_REGULATOR_S2MPS11=y
110CONFIG_REGULATOR_S5M8767=y 111CONFIG_REGULATOR_S5M8767=y
111CONFIG_REGULATOR_TPS65090=y 112CONFIG_REGULATOR_TPS65090=y
113CONFIG_DRM=y
114CONFIG_DRM_BRIDGE=y
115CONFIG_DRM_PTN3460=y
116CONFIG_DRM_PS8622=y
117CONFIG_DRM_EXYNOS=y
118CONFIG_DRM_EXYNOS_FIMD=y
119CONFIG_DRM_EXYNOS_DP=y
120CONFIG_DRM_PANEL=y
121CONFIG_DRM_PANEL_SIMPLE=y
112CONFIG_FB=y 122CONFIG_FB=y
113CONFIG_FB_MODE_HELPERS=y 123CONFIG_FB_MODE_HELPERS=y
114CONFIG_FB_SIMPLE=y 124CONFIG_FB_SIMPLE=y
115CONFIG_EXYNOS_VIDEO=y 125CONFIG_EXYNOS_VIDEO=y
116CONFIG_EXYNOS_MIPI_DSI=y 126CONFIG_EXYNOS_MIPI_DSI=y
127CONFIG_BACKLIGHT_LCD_SUPPORT=y
128CONFIG_LCD_CLASS_DEVICE=y
129CONFIG_LCD_PLATFORM=y
130CONFIG_BACKLIGHT_CLASS_DEVICE=y
131CONFIG_BACKLIGHT_GENERIC=y
132CONFIG_BACKLIGHT_PWM=y
117CONFIG_FRAMEBUFFER_CONSOLE=y 133CONFIG_FRAMEBUFFER_CONSOLE=y
118CONFIG_FONTS=y 134CONFIG_FONTS=y
119CONFIG_FONT_7x14=y 135CONFIG_FONT_7x14=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 2328fe752e9c..bc393b7e5ece 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -338,6 +338,7 @@ CONFIG_USB=y
338CONFIG_USB_XHCI_HCD=y 338CONFIG_USB_XHCI_HCD=y
339CONFIG_USB_XHCI_MVEBU=y 339CONFIG_USB_XHCI_MVEBU=y
340CONFIG_USB_EHCI_HCD=y 340CONFIG_USB_EHCI_HCD=y
341CONFIG_USB_EHCI_EXYNOS=y
341CONFIG_USB_EHCI_TEGRA=y 342CONFIG_USB_EHCI_TEGRA=y
342CONFIG_USB_EHCI_HCD_STI=y 343CONFIG_USB_EHCI_HCD_STI=y
343CONFIG_USB_EHCI_HCD_PLATFORM=y 344CONFIG_USB_EHCI_HCD_PLATFORM=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index c2c3a852af9f..667d9d52aa01 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -68,7 +68,7 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
68CONFIG_CPU_FREQ_GOV_POWERSAVE=y 68CONFIG_CPU_FREQ_GOV_POWERSAVE=y
69CONFIG_CPU_FREQ_GOV_USERSPACE=y 69CONFIG_CPU_FREQ_GOV_USERSPACE=y
70CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y 70CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
71CONFIG_GENERIC_CPUFREQ_CPU0=y 71CONFIG_CPUFREQ_DT=y
72# CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set 72# CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set
73CONFIG_CPU_IDLE=y 73CONFIG_CPU_IDLE=y
74CONFIG_BINFMT_MISC=y 74CONFIG_BINFMT_MISC=y
diff --git a/arch/arm/include/uapi/asm/unistd.h b/arch/arm/include/uapi/asm/unistd.h
index 705bb7620673..0c3f5a0dafd3 100644
--- a/arch/arm/include/uapi/asm/unistd.h
+++ b/arch/arm/include/uapi/asm/unistd.h
@@ -413,6 +413,7 @@
413#define __NR_getrandom (__NR_SYSCALL_BASE+384) 413#define __NR_getrandom (__NR_SYSCALL_BASE+384)
414#define __NR_memfd_create (__NR_SYSCALL_BASE+385) 414#define __NR_memfd_create (__NR_SYSCALL_BASE+385)
415#define __NR_bpf (__NR_SYSCALL_BASE+386) 415#define __NR_bpf (__NR_SYSCALL_BASE+386)
416#define __NR_execveat (__NR_SYSCALL_BASE+387)
416 417
417/* 418/*
418 * The following SWIs are ARM private. 419 * The following SWIs are ARM private.
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
index e51833f8cc38..05745eb838c5 100644
--- a/arch/arm/kernel/calls.S
+++ b/arch/arm/kernel/calls.S
@@ -396,6 +396,7 @@
396 CALL(sys_getrandom) 396 CALL(sys_getrandom)
397/* 385 */ CALL(sys_memfd_create) 397/* 385 */ CALL(sys_memfd_create)
398 CALL(sys_bpf) 398 CALL(sys_bpf)
399 CALL(sys_execveat)
399#ifndef syscalls_counted 400#ifndef syscalls_counted
400.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls 401.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
401#define syscalls_counted 402#define syscalls_counted
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 4176df721bf0..1a0045abead7 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -253,21 +253,22 @@
253 .endm 253 .endm
254 254
255 .macro restore_user_regs, fast = 0, offset = 0 255 .macro restore_user_regs, fast = 0, offset = 0
256 ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr 256 mov r2, sp
257 ldr lr, [sp, #\offset + S_PC]! @ get pc 257 ldr r1, [r2, #\offset + S_PSR] @ get calling cpsr
258 ldr lr, [r2, #\offset + S_PC]! @ get pc
258 msr spsr_cxsf, r1 @ save in spsr_svc 259 msr spsr_cxsf, r1 @ save in spsr_svc
259#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_32v6K) 260#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_32v6K)
260 @ We must avoid clrex due to Cortex-A15 erratum #830321 261 @ We must avoid clrex due to Cortex-A15 erratum #830321
261 strex r1, r2, [sp] @ clear the exclusive monitor 262 strex r1, r2, [r2] @ clear the exclusive monitor
262#endif 263#endif
263 .if \fast 264 .if \fast
264 ldmdb sp, {r1 - lr}^ @ get calling r1 - lr 265 ldmdb r2, {r1 - lr}^ @ get calling r1 - lr
265 .else 266 .else
266 ldmdb sp, {r0 - lr}^ @ get calling r0 - lr 267 ldmdb r2, {r0 - lr}^ @ get calling r0 - lr
267 .endif 268 .endif
268 mov r0, r0 @ ARMv5T and earlier require a nop 269 mov r0, r0 @ ARMv5T and earlier require a nop
269 @ after ldm {}^ 270 @ after ldm {}^
270 add sp, sp, #S_FRAME_SIZE - S_PC 271 add sp, sp, #\offset + S_FRAME_SIZE
271 movs pc, lr @ return & move spsr_svc into cpsr 272 movs pc, lr @ return & move spsr_svc into cpsr
272 .endm 273 .endm
273 274
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index f7c65adaa428..557e128e4df0 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -116,8 +116,14 @@ int armpmu_event_set_period(struct perf_event *event)
116 ret = 1; 116 ret = 1;
117 } 117 }
118 118
119 if (left > (s64)armpmu->max_period) 119 /*
120 left = armpmu->max_period; 120 * Limit the maximum period to prevent the counter value
121 * from overtaking the one we are about to program. In
122 * effect we are reducing max_period to account for
123 * interrupt latency (and we are being very conservative).
124 */
125 if (left > (armpmu->max_period >> 1))
126 left = armpmu->max_period >> 1;
121 127
122 local64_set(&hwc->prev_count, (u64)-left); 128 local64_set(&hwc->prev_count, (u64)-left);
123 129
diff --git a/arch/arm/kernel/perf_regs.c b/arch/arm/kernel/perf_regs.c
index 6e4379c67cbc..592dda3f21ff 100644
--- a/arch/arm/kernel/perf_regs.c
+++ b/arch/arm/kernel/perf_regs.c
@@ -28,3 +28,11 @@ u64 perf_reg_abi(struct task_struct *task)
28{ 28{
29 return PERF_SAMPLE_REGS_ABI_32; 29 return PERF_SAMPLE_REGS_ABI_32;
30} 30}
31
32void perf_get_regs_user(struct perf_regs *regs_user,
33 struct pt_regs *regs,
34 struct pt_regs *regs_user_copy)
35{
36 regs_user->regs = task_pt_regs(current);
37 regs_user->abi = perf_reg_abi(current);
38}
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index f9c863911038..e55408e96559 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -657,10 +657,13 @@ int __init arm_add_memory(u64 start, u64 size)
657 657
658 /* 658 /*
659 * Ensure that start/size are aligned to a page boundary. 659 * Ensure that start/size are aligned to a page boundary.
660 * Size is appropriately rounded down, start is rounded up. 660 * Size is rounded down, start is rounded up.
661 */ 661 */
662 size -= start & ~PAGE_MASK;
663 aligned_start = PAGE_ALIGN(start); 662 aligned_start = PAGE_ALIGN(start);
663 if (aligned_start > start + size)
664 size = 0;
665 else
666 size -= aligned_start - start;
664 667
665#ifndef CONFIG_ARCH_PHYS_ADDR_T_64BIT 668#ifndef CONFIG_ARCH_PHYS_ADDR_T_64BIT
666 if (aligned_start > ULONG_MAX) { 669 if (aligned_start > ULONG_MAX) {
@@ -1046,6 +1049,15 @@ static int c_show(struct seq_file *m, void *v)
1046 seq_printf(m, "model name\t: %s rev %d (%s)\n", 1049 seq_printf(m, "model name\t: %s rev %d (%s)\n",
1047 cpu_name, cpuid & 15, elf_platform); 1050 cpu_name, cpuid & 15, elf_platform);
1048 1051
1052#if defined(CONFIG_SMP)
1053 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
1054 per_cpu(cpu_data, i).loops_per_jiffy / (500000UL/HZ),
1055 (per_cpu(cpu_data, i).loops_per_jiffy / (5000UL/HZ)) % 100);
1056#else
1057 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
1058 loops_per_jiffy / (500000/HZ),
1059 (loops_per_jiffy / (5000/HZ)) % 100);
1060#endif
1049 /* dump out the processor features */ 1061 /* dump out the processor features */
1050 seq_puts(m, "Features\t: "); 1062 seq_puts(m, "Features\t: ");
1051 1063
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 5e6052e18850..86ef244c5a24 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -387,6 +387,18 @@ asmlinkage void secondary_start_kernel(void)
387 387
388void __init smp_cpus_done(unsigned int max_cpus) 388void __init smp_cpus_done(unsigned int max_cpus)
389{ 389{
390 int cpu;
391 unsigned long bogosum = 0;
392
393 for_each_online_cpu(cpu)
394 bogosum += per_cpu(cpu_data, cpu).loops_per_jiffy;
395
396 printk(KERN_INFO "SMP: Total of %d processors activated "
397 "(%lu.%02lu BogoMIPS).\n",
398 num_online_cpus(),
399 bogosum / (500000/HZ),
400 (bogosum / (5000/HZ)) % 100);
401
390 hyp_mode_check(); 402 hyp_mode_check();
391} 403}
392 404
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index 8fb9ef5333f1..97f7367d32b8 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -17,6 +17,7 @@
17#include <linux/of_platform.h> 17#include <linux/of_platform.h>
18#include <linux/phy.h> 18#include <linux/phy.h>
19#include <linux/clk-provider.h> 19#include <linux/clk-provider.h>
20#include <linux/phy.h>
20 21
21#include <asm/setup.h> 22#include <asm/setup.h>
22#include <asm/irq.h> 23#include <asm/irq.h>
@@ -26,8 +27,25 @@
26 27
27#include "generic.h" 28#include "generic.h"
28 29
30static int ksz8081_phy_fixup(struct phy_device *phy)
31{
32 int value;
33
34 value = phy_read(phy, 0x16);
35 value &= ~0x20;
36 phy_write(phy, 0x16, value);
37
38 return 0;
39}
40
29static void __init sama5_dt_device_init(void) 41static void __init sama5_dt_device_init(void)
30{ 42{
43 if (of_machine_is_compatible("atmel,sama5d4ek") &&
44 IS_ENABLED(CONFIG_PHYLIB)) {
45 phy_register_fixup_for_id("fc028000.etherne:00",
46 ksz8081_phy_fixup);
47 }
48
31 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 49 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
32} 50}
33 51
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 5951660d1bd2..2daef619d053 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -144,7 +144,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
144 post_div_table[1].div = 1; 144 post_div_table[1].div = 1;
145 post_div_table[2].div = 1; 145 post_div_table[2].div = 1;
146 video_div_table[1].div = 1; 146 video_div_table[1].div = 1;
147 video_div_table[2].div = 1; 147 video_div_table[3].div = 1;
148 } 148 }
149 149
150 clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 150 clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c
index 17354a11356f..5a3e5a159e70 100644
--- a/arch/arm/mach-imx/clk-imx6sx.c
+++ b/arch/arm/mach-imx/clk-imx6sx.c
@@ -558,6 +558,9 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
558 clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); 558 clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
559 clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); 559 clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
560 560
561 clk_set_parent(clks[IMX6SX_CLK_QSPI1_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
562 clk_set_parent(clks[IMX6SX_CLK_QSPI2_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
563
561 /* Set initial power mode */ 564 /* Set initial power mode */
562 imx6q_set_lpm(WAIT_CLOCKED); 565 imx6q_set_lpm(WAIT_CLOCKED);
563} 566}
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index 3585cb394e9b..caa21e9b8cd9 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -246,9 +246,14 @@ static int coherency_type(void)
246 return type; 246 return type;
247} 247}
248 248
249/*
250 * As a precaution, we currently completely disable hardware I/O
251 * coherency, until enough testing is done with automatic I/O
252 * synchronization barriers to validate that it is a proper solution.
253 */
249int coherency_available(void) 254int coherency_available(void)
250{ 255{
251 return coherency_type() != COHERENCY_FABRIC_TYPE_NONE; 256 return false;
252} 257}
253 258
254int __init coherency_init(void) 259int __init coherency_init(void)
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 608079a1aba6..b61c049f92d6 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -77,6 +77,24 @@ MACHINE_END
77#endif 77#endif
78 78
79#ifdef CONFIG_ARCH_OMAP3 79#ifdef CONFIG_ARCH_OMAP3
80/* Some boards need board name for legacy userspace in /proc/cpuinfo */
81static const char *const n900_boards_compat[] __initconst = {
82 "nokia,omap3-n900",
83 NULL,
84};
85
86DT_MACHINE_START(OMAP3_N900_DT, "Nokia RX-51 board")
87 .reserve = omap_reserve,
88 .map_io = omap3_map_io,
89 .init_early = omap3430_init_early,
90 .init_machine = omap_generic_init,
91 .init_late = omap3_init_late,
92 .init_time = omap3_sync32k_timer_init,
93 .dt_compat = n900_boards_compat,
94 .restart = omap3xxx_restart,
95MACHINE_END
96
97/* Generic omap3 boards, most boards can use these */
80static const char *const omap3_boards_compat[] __initconst = { 98static const char *const omap3_boards_compat[] __initconst = {
81 "ti,omap3430", 99 "ti,omap3430",
82 "ti,omap3", 100 "ti,omap3",
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 377eea849e7b..64e44d6d07c0 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -211,6 +211,7 @@ extern struct device *omap2_get_iva_device(void);
211extern struct device *omap2_get_l3_device(void); 211extern struct device *omap2_get_l3_device(void);
212extern struct device *omap4_get_dsp_device(void); 212extern struct device *omap4_get_dsp_device(void);
213 213
214unsigned int omap4_xlate_irq(unsigned int hwirq);
214void omap_gic_of_init(void); 215void omap_gic_of_init(void);
215 216
216#ifdef CONFIG_CACHE_L2X0 217#ifdef CONFIG_CACHE_L2X0
@@ -249,6 +250,7 @@ extern void omap4_cpu_die(unsigned int cpu);
249extern struct smp_operations omap4_smp_ops; 250extern struct smp_operations omap4_smp_ops;
250 251
251extern void omap5_secondary_startup(void); 252extern void omap5_secondary_startup(void);
253extern void omap5_secondary_hyp_startup(void);
252#endif 254#endif
253 255
254#if defined(CONFIG_SMP) && defined(CONFIG_PM) 256#if defined(CONFIG_SMP) && defined(CONFIG_PM)
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index a3c013345c45..a80ac2d70bb1 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -286,6 +286,10 @@
286#define OMAP5XXX_CONTROL_STATUS 0x134 286#define OMAP5XXX_CONTROL_STATUS 0x134
287#define OMAP5_DEVICETYPE_MASK (0x7 << 6) 287#define OMAP5_DEVICETYPE_MASK (0x7 << 6)
288 288
289/* DRA7XX CONTROL CORE BOOTSTRAP */
290#define DRA7_CTRL_CORE_BOOTSTRAP 0x6c4
291#define DRA7_SPEEDSELECT_MASK (0x3 << 8)
292
289/* 293/*
290 * REVISIT: This list of registers is not comprehensive - there are more 294 * REVISIT: This list of registers is not comprehensive - there are more
291 * that should be added. 295 * that should be added.
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 4993d4bfe9b2..6d1dffca6c7b 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -22,6 +22,7 @@
22 22
23/* Physical address needed since MMU not enabled yet on secondary core */ 23/* Physical address needed since MMU not enabled yet on secondary core */
24#define AUX_CORE_BOOT0_PA 0x48281800 24#define AUX_CORE_BOOT0_PA 0x48281800
25#define API_HYP_ENTRY 0x102
25 26
26/* 27/*
27 * OMAP5 specific entry point for secondary CPU to jump from ROM 28 * OMAP5 specific entry point for secondary CPU to jump from ROM
@@ -41,6 +42,26 @@ wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
41 b secondary_startup 42 b secondary_startup
42ENDPROC(omap5_secondary_startup) 43ENDPROC(omap5_secondary_startup)
43/* 44/*
45 * Same as omap5_secondary_startup except we call into the ROM to
46 * enable HYP mode first. This is called instead of
47 * omap5_secondary_startup if the primary CPU was put into HYP mode by
48 * the boot loader.
49 */
50ENTRY(omap5_secondary_hyp_startup)
51wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
52 ldr r0, [r2]
53 mov r0, r0, lsr #5
54 mrc p15, 0, r4, c0, c0, 5
55 and r4, r4, #0x0f
56 cmp r0, r4
57 bne wait_2
58 ldr r12, =API_HYP_ENTRY
59 adr r0, hyp_boot
60 smc #0
61hyp_boot:
62 b secondary_startup
63ENDPROC(omap5_secondary_hyp_startup)
64/*
44 * OMAP4 specific entry point for secondary CPU to jump from ROM 65 * OMAP4 specific entry point for secondary CPU to jump from ROM
45 * code. This routine also provides a holding flag into which 66 * code. This routine also provides a holding flag into which
46 * secondary core is held until we're ready for it to initialise. 67 * secondary core is held until we're ready for it to initialise.
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 256e84ef0f67..5305ec7341ec 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -22,6 +22,7 @@
22#include <linux/irqchip/arm-gic.h> 22#include <linux/irqchip/arm-gic.h>
23 23
24#include <asm/smp_scu.h> 24#include <asm/smp_scu.h>
25#include <asm/virt.h>
25 26
26#include "omap-secure.h" 27#include "omap-secure.h"
27#include "omap-wakeupgen.h" 28#include "omap-wakeupgen.h"
@@ -227,8 +228,16 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
227 if (omap_secure_apis_support()) 228 if (omap_secure_apis_support())
228 omap_auxcoreboot_addr(virt_to_phys(startup_addr)); 229 omap_auxcoreboot_addr(virt_to_phys(startup_addr));
229 else 230 else
230 writel_relaxed(virt_to_phys(omap5_secondary_startup), 231 /*
231 base + OMAP_AUX_CORE_BOOT_1); 232 * If the boot CPU is in HYP mode then start secondary
233 * CPU in HYP mode as well.
234 */
235 if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
236 writel_relaxed(virt_to_phys(omap5_secondary_hyp_startup),
237 base + OMAP_AUX_CORE_BOOT_1);
238 else
239 writel_relaxed(virt_to_phys(omap5_secondary_startup),
240 base + OMAP_AUX_CORE_BOOT_1);
232 241
233} 242}
234 243
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index b7cb44abe49b..cc30e49a4cc2 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -256,6 +256,38 @@ static int __init omap4_sar_ram_init(void)
256} 256}
257omap_early_initcall(omap4_sar_ram_init); 257omap_early_initcall(omap4_sar_ram_init);
258 258
259static struct of_device_id gic_match[] = {
260 { .compatible = "arm,cortex-a9-gic", },
261 { .compatible = "arm,cortex-a15-gic", },
262 { },
263};
264
265static struct device_node *gic_node;
266
267unsigned int omap4_xlate_irq(unsigned int hwirq)
268{
269 struct of_phandle_args irq_data;
270 unsigned int irq;
271
272 if (!gic_node)
273 gic_node = of_find_matching_node(NULL, gic_match);
274
275 if (WARN_ON(!gic_node))
276 return hwirq;
277
278 irq_data.np = gic_node;
279 irq_data.args_count = 3;
280 irq_data.args[0] = 0;
281 irq_data.args[1] = hwirq - OMAP44XX_IRQ_GIC_START;
282 irq_data.args[2] = IRQ_TYPE_LEVEL_HIGH;
283
284 irq = irq_create_of_mapping(&irq_data);
285 if (WARN_ON(!irq))
286 irq = hwirq;
287
288 return irq;
289}
290
259void __init omap_gic_of_init(void) 291void __init omap_gic_of_init(void)
260{ 292{
261 struct device_node *np; 293 struct device_node *np;
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index cbb908dc5cf0..9025ffffd2dc 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -3534,9 +3534,15 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
3534 3534
3535 mpu_irqs_cnt = _count_mpu_irqs(oh); 3535 mpu_irqs_cnt = _count_mpu_irqs(oh);
3536 for (i = 0; i < mpu_irqs_cnt; i++) { 3536 for (i = 0; i < mpu_irqs_cnt; i++) {
3537 unsigned int irq;
3538
3539 if (oh->xlate_irq)
3540 irq = oh->xlate_irq((oh->mpu_irqs + i)->irq);
3541 else
3542 irq = (oh->mpu_irqs + i)->irq;
3537 (res + r)->name = (oh->mpu_irqs + i)->name; 3543 (res + r)->name = (oh->mpu_irqs + i)->name;
3538 (res + r)->start = (oh->mpu_irqs + i)->irq; 3544 (res + r)->start = irq;
3539 (res + r)->end = (oh->mpu_irqs + i)->irq; 3545 (res + r)->end = irq;
3540 (res + r)->flags = IORESOURCE_IRQ; 3546 (res + r)->flags = IORESOURCE_IRQ;
3541 r++; 3547 r++;
3542 } 3548 }
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 35ca6efbec31..5b42fafcaf55 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -676,6 +676,7 @@ struct omap_hwmod {
676 spinlock_t _lock; 676 spinlock_t _lock;
677 struct list_head node; 677 struct list_head node;
678 struct omap_hwmod_ocp_if *_mpu_port; 678 struct omap_hwmod_ocp_if *_mpu_port;
679 unsigned int (*xlate_irq)(unsigned int);
679 u16 flags; 680 u16 flags;
680 u8 mpu_rt_idx; 681 u8 mpu_rt_idx;
681 u8 response_lat; 682 u8 response_lat;
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index c314b3c31117..f5e68a782025 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -479,6 +479,7 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
479 .class = &omap44xx_dma_hwmod_class, 479 .class = &omap44xx_dma_hwmod_class,
480 .clkdm_name = "l3_dma_clkdm", 480 .clkdm_name = "l3_dma_clkdm",
481 .mpu_irqs = omap44xx_dma_system_irqs, 481 .mpu_irqs = omap44xx_dma_system_irqs,
482 .xlate_irq = omap4_xlate_irq,
482 .main_clk = "l3_div_ck", 483 .main_clk = "l3_div_ck",
483 .prcm = { 484 .prcm = {
484 .omap4 = { 485 .omap4 = {
@@ -640,6 +641,7 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
640 .class = &omap44xx_dispc_hwmod_class, 641 .class = &omap44xx_dispc_hwmod_class,
641 .clkdm_name = "l3_dss_clkdm", 642 .clkdm_name = "l3_dss_clkdm",
642 .mpu_irqs = omap44xx_dss_dispc_irqs, 643 .mpu_irqs = omap44xx_dss_dispc_irqs,
644 .xlate_irq = omap4_xlate_irq,
643 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, 645 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
644 .main_clk = "dss_dss_clk", 646 .main_clk = "dss_dss_clk",
645 .prcm = { 647 .prcm = {
@@ -693,6 +695,7 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
693 .class = &omap44xx_dsi_hwmod_class, 695 .class = &omap44xx_dsi_hwmod_class,
694 .clkdm_name = "l3_dss_clkdm", 696 .clkdm_name = "l3_dss_clkdm",
695 .mpu_irqs = omap44xx_dss_dsi1_irqs, 697 .mpu_irqs = omap44xx_dss_dsi1_irqs,
698 .xlate_irq = omap4_xlate_irq,
696 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, 699 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
697 .main_clk = "dss_dss_clk", 700 .main_clk = "dss_dss_clk",
698 .prcm = { 701 .prcm = {
@@ -726,6 +729,7 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
726 .class = &omap44xx_dsi_hwmod_class, 729 .class = &omap44xx_dsi_hwmod_class,
727 .clkdm_name = "l3_dss_clkdm", 730 .clkdm_name = "l3_dss_clkdm",
728 .mpu_irqs = omap44xx_dss_dsi2_irqs, 731 .mpu_irqs = omap44xx_dss_dsi2_irqs,
732 .xlate_irq = omap4_xlate_irq,
729 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, 733 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
730 .main_clk = "dss_dss_clk", 734 .main_clk = "dss_dss_clk",
731 .prcm = { 735 .prcm = {
@@ -784,6 +788,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
784 */ 788 */
785 .flags = HWMOD_SWSUP_SIDLE, 789 .flags = HWMOD_SWSUP_SIDLE,
786 .mpu_irqs = omap44xx_dss_hdmi_irqs, 790 .mpu_irqs = omap44xx_dss_hdmi_irqs,
791 .xlate_irq = omap4_xlate_irq,
787 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, 792 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
788 .main_clk = "dss_48mhz_clk", 793 .main_clk = "dss_48mhz_clk",
789 .prcm = { 794 .prcm = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
index 3e9523084b2a..7c3fac035e93 100644
--- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -288,6 +288,7 @@ static struct omap_hwmod omap54xx_dma_system_hwmod = {
288 .class = &omap54xx_dma_hwmod_class, 288 .class = &omap54xx_dma_hwmod_class,
289 .clkdm_name = "dma_clkdm", 289 .clkdm_name = "dma_clkdm",
290 .mpu_irqs = omap54xx_dma_system_irqs, 290 .mpu_irqs = omap54xx_dma_system_irqs,
291 .xlate_irq = omap4_xlate_irq,
291 .main_clk = "l3_iclk_div", 292 .main_clk = "l3_iclk_div",
292 .prcm = { 293 .prcm = {
293 .omap4 = { 294 .omap4 = {
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index a8e4b582c527..6163d66102a3 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -498,6 +498,7 @@ struct omap_prcm_irq_setup {
498 u8 nr_irqs; 498 u8 nr_irqs;
499 const struct omap_prcm_irq *irqs; 499 const struct omap_prcm_irq *irqs;
500 int irq; 500 int irq;
501 unsigned int (*xlate_irq)(unsigned int);
501 void (*read_pending_irqs)(unsigned long *events); 502 void (*read_pending_irqs)(unsigned long *events);
502 void (*ocp_barrier)(void); 503 void (*ocp_barrier)(void);
503 void (*save_and_clear_irqen)(u32 *saved_mask); 504 void (*save_and_clear_irqen)(u32 *saved_mask);
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index cc170fb81ff7..408c64efb807 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -49,6 +49,7 @@ static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
49 .irqs = omap4_prcm_irqs, 49 .irqs = omap4_prcm_irqs,
50 .nr_irqs = ARRAY_SIZE(omap4_prcm_irqs), 50 .nr_irqs = ARRAY_SIZE(omap4_prcm_irqs),
51 .irq = 11 + OMAP44XX_IRQ_GIC_START, 51 .irq = 11 + OMAP44XX_IRQ_GIC_START,
52 .xlate_irq = omap4_xlate_irq,
52 .read_pending_irqs = &omap44xx_prm_read_pending_irqs, 53 .read_pending_irqs = &omap44xx_prm_read_pending_irqs,
53 .ocp_barrier = &omap44xx_prm_ocp_barrier, 54 .ocp_barrier = &omap44xx_prm_ocp_barrier,
54 .save_and_clear_irqen = &omap44xx_prm_save_and_clear_irqen, 55 .save_and_clear_irqen = &omap44xx_prm_save_and_clear_irqen,
@@ -751,8 +752,10 @@ static int omap44xx_prm_late_init(void)
751 } 752 }
752 753
753 /* Once OMAP4 DT is filled as well */ 754 /* Once OMAP4 DT is filled as well */
754 if (irq_num >= 0) 755 if (irq_num >= 0) {
755 omap4_prcm_irq_setup.irq = irq_num; 756 omap4_prcm_irq_setup.irq = irq_num;
757 omap4_prcm_irq_setup.xlate_irq = NULL;
758 }
756 } 759 }
757 760
758 omap44xx_prm_enable_io_wakeup(); 761 omap44xx_prm_enable_io_wakeup();
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 779940cb6e56..dea2833ca627 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -187,6 +187,7 @@ int omap_prcm_event_to_irq(const char *name)
187 */ 187 */
188void omap_prcm_irq_cleanup(void) 188void omap_prcm_irq_cleanup(void)
189{ 189{
190 unsigned int irq;
190 int i; 191 int i;
191 192
192 if (!prcm_irq_setup) { 193 if (!prcm_irq_setup) {
@@ -211,7 +212,11 @@ void omap_prcm_irq_cleanup(void)
211 kfree(prcm_irq_setup->priority_mask); 212 kfree(prcm_irq_setup->priority_mask);
212 prcm_irq_setup->priority_mask = NULL; 213 prcm_irq_setup->priority_mask = NULL;
213 214
214 irq_set_chained_handler(prcm_irq_setup->irq, NULL); 215 if (prcm_irq_setup->xlate_irq)
216 irq = prcm_irq_setup->xlate_irq(prcm_irq_setup->irq);
217 else
218 irq = prcm_irq_setup->irq;
219 irq_set_chained_handler(irq, NULL);
215 220
216 if (prcm_irq_setup->base_irq > 0) 221 if (prcm_irq_setup->base_irq > 0)
217 irq_free_descs(prcm_irq_setup->base_irq, 222 irq_free_descs(prcm_irq_setup->base_irq,
@@ -259,6 +264,7 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
259 int offset, i; 264 int offset, i;
260 struct irq_chip_generic *gc; 265 struct irq_chip_generic *gc;
261 struct irq_chip_type *ct; 266 struct irq_chip_type *ct;
267 unsigned int irq;
262 268
263 if (!irq_setup) 269 if (!irq_setup)
264 return -EINVAL; 270 return -EINVAL;
@@ -298,7 +304,11 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
298 1 << (offset & 0x1f); 304 1 << (offset & 0x1f);
299 } 305 }
300 306
301 irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler); 307 if (irq_setup->xlate_irq)
308 irq = irq_setup->xlate_irq(irq_setup->irq);
309 else
310 irq = irq_setup->irq;
311 irq_set_chained_handler(irq, omap_prcm_irq_handler);
302 312
303 irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32, 313 irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
304 0); 314 0);
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 4f61148ec168..7d45c84c69ba 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -54,6 +54,7 @@
54 54
55#include "soc.h" 55#include "soc.h"
56#include "common.h" 56#include "common.h"
57#include "control.h"
57#include "powerdomain.h" 58#include "powerdomain.h"
58#include "omap-secure.h" 59#include "omap-secure.h"
59 60
@@ -496,7 +497,8 @@ static void __init realtime_counter_init(void)
496 void __iomem *base; 497 void __iomem *base;
497 static struct clk *sys_clk; 498 static struct clk *sys_clk;
498 unsigned long rate; 499 unsigned long rate;
499 unsigned int reg, num, den; 500 unsigned int reg;
501 unsigned long long num, den;
500 502
501 base = ioremap(REALTIME_COUNTER_BASE, SZ_32); 503 base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
502 if (!base) { 504 if (!base) {
@@ -511,13 +513,42 @@ static void __init realtime_counter_init(void)
511 } 513 }
512 514
513 rate = clk_get_rate(sys_clk); 515 rate = clk_get_rate(sys_clk);
516
517 if (soc_is_dra7xx()) {
518 /*
519 * Errata i856 says the 32.768KHz crystal does not start at
520 * power on, so the CPU falls back to an emulated 32KHz clock
521 * based on sysclk / 610 instead. This causes the master counter
522 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
523 * (OR sysclk * 75 / 244)
524 *
525 * This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
526 * Of course any board built without a populated 32.768KHz
527 * crystal would also need this fix even if the CPU is fixed
528 * later.
529 *
530 * Either case can be detected by using the two speedselect bits
531 * If they are not 0, then the 32.768KHz clock driving the
532 * coarse counter that corrects the fine counter every time it
533 * ticks is actually rate/610 rather than 32.768KHz and we
534 * should compensate to avoid the 570ppm (at 20MHz, much worse
535 * at other rates) too fast system time.
536 */
537 reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
538 if (reg & DRA7_SPEEDSELECT_MASK) {
539 num = 75;
540 den = 244;
541 goto sysclk1_based;
542 }
543 }
544
514 /* Numerator/denumerator values refer TRM Realtime Counter section */ 545 /* Numerator/denumerator values refer TRM Realtime Counter section */
515 switch (rate) { 546 switch (rate) {
516 case 1200000: 547 case 12000000:
517 num = 64; 548 num = 64;
518 den = 125; 549 den = 125;
519 break; 550 break;
520 case 1300000: 551 case 13000000:
521 num = 768; 552 num = 768;
522 den = 1625; 553 den = 1625;
523 break; 554 break;
@@ -529,11 +560,11 @@ static void __init realtime_counter_init(void)
529 num = 192; 560 num = 192;
530 den = 625; 561 den = 625;
531 break; 562 break;
532 case 2600000: 563 case 26000000:
533 num = 384; 564 num = 384;
534 den = 1625; 565 den = 1625;
535 break; 566 break;
536 case 2700000: 567 case 27000000:
537 num = 256; 568 num = 256;
538 den = 1125; 569 den = 1125;
539 break; 570 break;
@@ -545,6 +576,7 @@ static void __init realtime_counter_init(void)
545 break; 576 break;
546 } 577 }
547 578
579sysclk1_based:
548 /* Program numerator and denumerator registers */ 580 /* Program numerator and denumerator registers */
549 reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) & 581 reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
550 NUMERATOR_DENUMERATOR_MASK; 582 NUMERATOR_DENUMERATOR_MASK;
@@ -556,7 +588,7 @@ static void __init realtime_counter_init(void)
556 reg |= den; 588 reg |= den;
557 writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); 589 writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
558 590
559 arch_timer_freq = (rate / den) * num; 591 arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
560 set_cntfreq(); 592 set_cntfreq();
561 593
562 iounmap(base); 594 iounmap(base);
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 4457e731f7a4..292eca0e78ed 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -66,19 +66,24 @@ void __init omap_pmic_init(int bus, u32 clkrate,
66 omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1); 66 omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
67} 67}
68 68
69#ifdef CONFIG_ARCH_OMAP4
69void __init omap4_pmic_init(const char *pmic_type, 70void __init omap4_pmic_init(const char *pmic_type,
70 struct twl4030_platform_data *pmic_data, 71 struct twl4030_platform_data *pmic_data,
71 struct i2c_board_info *devices, int nr_devices) 72 struct i2c_board_info *devices, int nr_devices)
72{ 73{
73 /* PMIC part*/ 74 /* PMIC part*/
75 unsigned int irq;
76
74 omap_mux_init_signal("sys_nirq1", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE); 77 omap_mux_init_signal("sys_nirq1", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
75 omap_mux_init_signal("fref_clk0_out.sys_drm_msecure", OMAP_PIN_OUTPUT); 78 omap_mux_init_signal("fref_clk0_out.sys_drm_msecure", OMAP_PIN_OUTPUT);
76 omap_pmic_init(1, 400, pmic_type, 7 + OMAP44XX_IRQ_GIC_START, pmic_data); 79 irq = omap4_xlate_irq(7 + OMAP44XX_IRQ_GIC_START);
80 omap_pmic_init(1, 400, pmic_type, irq, pmic_data);
77 81
78 /* Register additional devices on i2c1 bus if needed */ 82 /* Register additional devices on i2c1 bus if needed */
79 if (devices) 83 if (devices)
80 i2c_register_board_info(1, devices, nr_devices); 84 i2c_register_board_info(1, devices, nr_devices);
81} 85}
86#endif
82 87
83void __init omap_pmic_late_init(void) 88void __init omap_pmic_late_init(void)
84{ 89{
diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
index d226b71d21d5..a611f4852582 100644
--- a/arch/arm/mach-rockchip/rockchip.c
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -19,11 +19,37 @@
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/of_platform.h> 20#include <linux/of_platform.h>
21#include <linux/irqchip.h> 21#include <linux/irqchip.h>
22#include <linux/clk-provider.h>
23#include <linux/clocksource.h>
24#include <linux/mfd/syscon.h>
25#include <linux/regmap.h>
22#include <asm/mach/arch.h> 26#include <asm/mach/arch.h>
23#include <asm/mach/map.h> 27#include <asm/mach/map.h>
24#include <asm/hardware/cache-l2x0.h> 28#include <asm/hardware/cache-l2x0.h>
25#include "core.h" 29#include "core.h"
26 30
31#define RK3288_GRF_SOC_CON0 0x244
32
33static void __init rockchip_timer_init(void)
34{
35 if (of_machine_is_compatible("rockchip,rk3288")) {
36 struct regmap *grf;
37
38 /*
39 * Disable auto jtag/sdmmc switching that causes issues
40 * with the mmc controllers making them unreliable
41 */
42 grf = syscon_regmap_lookup_by_compatible("rockchip,rk3288-grf");
43 if (!IS_ERR(grf))
44 regmap_write(grf, RK3288_GRF_SOC_CON0, 0x10000000);
45 else
46 pr_err("rockchip: could not get grf syscon\n");
47 }
48
49 of_clk_init(NULL);
50 clocksource_of_init();
51}
52
27static void __init rockchip_dt_init(void) 53static void __init rockchip_dt_init(void)
28{ 54{
29 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 55 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
@@ -42,6 +68,7 @@ static const char * const rockchip_board_dt_compat[] = {
42DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)") 68DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)")
43 .l2c_aux_val = 0, 69 .l2c_aux_val = 0,
44 .l2c_aux_mask = ~0, 70 .l2c_aux_mask = ~0,
71 .init_time = rockchip_timer_init,
45 .dt_compat = rockchip_board_dt_compat, 72 .dt_compat = rockchip_board_dt_compat,
46 .init_machine = rockchip_dt_init, 73 .init_machine = rockchip_dt_init,
47MACHINE_END 74MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 79ad93dfdae4..d191cf419731 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -800,7 +800,14 @@ void __init r8a7740_init_irq_of(void)
800 void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10); 800 void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
801 void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4); 801 void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
802 802
803#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
804 void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000);
805 void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000);
806
807 gic_init(0, 29, gic_dist_base, gic_cpu_base);
808#else
803 irqchip_init(); 809 irqchip_init();
810#endif
804 811
805 /* route signals to GIC */ 812 /* route signals to GIC */
806 iowrite32(0x0, pfc_inta_ctrl); 813 iowrite32(0x0, pfc_inta_ctrl);
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 170bd146ba17..cef8895a9b82 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -576,11 +576,18 @@ void __init r8a7778_init_irq_extpin(int irlm)
576void __init r8a7778_init_irq_dt(void) 576void __init r8a7778_init_irq_dt(void)
577{ 577{
578 void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); 578 void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
579#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
580 void __iomem *gic_dist_base = ioremap_nocache(0xfe438000, 0x1000);
581 void __iomem *gic_cpu_base = ioremap_nocache(0xfe430000, 0x1000);
582#endif
579 583
580 BUG_ON(!base); 584 BUG_ON(!base);
581 585
586#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
587 gic_init(0, 29, gic_dist_base, gic_cpu_base);
588#else
582 irqchip_init(); 589 irqchip_init();
583 590#endif
584 /* route all interrupts to ARM */ 591 /* route all interrupts to ARM */
585 __raw_writel(0x73ffffff, base + INT2NTSR0); 592 __raw_writel(0x73ffffff, base + INT2NTSR0);
586 __raw_writel(0xffffffff, base + INT2NTSR1); 593 __raw_writel(0xffffffff, base + INT2NTSR1);
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 6156d172cf31..27dceaf9e688 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -720,10 +720,17 @@ static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
720 720
721void __init r8a7779_init_irq_dt(void) 721void __init r8a7779_init_irq_dt(void)
722{ 722{
723#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
724 void __iomem *gic_dist_base = ioremap_nocache(0xf0001000, 0x1000);
725 void __iomem *gic_cpu_base = ioremap_nocache(0xf0000100, 0x1000);
726#endif
723 gic_arch_extn.irq_set_wake = r8a7779_set_wake; 727 gic_arch_extn.irq_set_wake = r8a7779_set_wake;
724 728
729#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
730 gic_init(0, 29, gic_dist_base, gic_cpu_base);
731#else
725 irqchip_init(); 732 irqchip_init();
726 733#endif
727 /* route all interrupts to ARM */ 734 /* route all interrupts to ARM */
728 __raw_writel(0xffffffff, INT2NTSR0); 735 __raw_writel(0xffffffff, INT2NTSR0);
729 __raw_writel(0x3fffffff, INT2NTSR1); 736 __raw_writel(0x3fffffff, INT2NTSR1);
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 93ebe3430bfe..fb5e1bb34be8 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -595,6 +595,7 @@ static struct platform_device ipmmu_device = {
595 595
596static struct renesas_intc_irqpin_config irqpin0_platform_data = { 596static struct renesas_intc_irqpin_config irqpin0_platform_data = {
597 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */ 597 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
598 .control_parent = true,
598}; 599};
599 600
600static struct resource irqpin0_resources[] = { 601static struct resource irqpin0_resources[] = {
@@ -656,6 +657,7 @@ static struct platform_device irqpin1_device = {
656 657
657static struct renesas_intc_irqpin_config irqpin2_platform_data = { 658static struct renesas_intc_irqpin_config irqpin2_platform_data = {
658 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */ 659 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
660 .control_parent = true,
659}; 661};
660 662
661static struct resource irqpin2_resources[] = { 663static struct resource irqpin2_resources[] = {
@@ -686,6 +688,7 @@ static struct platform_device irqpin2_device = {
686 688
687static struct renesas_intc_irqpin_config irqpin3_platform_data = { 689static struct renesas_intc_irqpin_config irqpin3_platform_data = {
688 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */ 690 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
691 .control_parent = true,
689}; 692};
690 693
691static struct resource irqpin3_resources[] = { 694static struct resource irqpin3_resources[] = {
diff --git a/arch/arm/mm/dump.c b/arch/arm/mm/dump.c
index 59424937e52b..9fe8e241335c 100644
--- a/arch/arm/mm/dump.c
+++ b/arch/arm/mm/dump.c
@@ -220,9 +220,6 @@ static void note_page(struct pg_state *st, unsigned long addr, unsigned level, u
220 static const char units[] = "KMGTPE"; 220 static const char units[] = "KMGTPE";
221 u64 prot = val & pg_level[level].mask; 221 u64 prot = val & pg_level[level].mask;
222 222
223 if (addr < USER_PGTABLES_CEILING)
224 return;
225
226 if (!st->level) { 223 if (!st->level) {
227 st->level = level; 224 st->level = level;
228 st->current_prot = prot; 225 st->current_prot = prot;
@@ -308,15 +305,13 @@ static void walk_pgd(struct seq_file *m)
308 pgd_t *pgd = swapper_pg_dir; 305 pgd_t *pgd = swapper_pg_dir;
309 struct pg_state st; 306 struct pg_state st;
310 unsigned long addr; 307 unsigned long addr;
311 unsigned i, pgdoff = USER_PGTABLES_CEILING / PGDIR_SIZE; 308 unsigned i;
312 309
313 memset(&st, 0, sizeof(st)); 310 memset(&st, 0, sizeof(st));
314 st.seq = m; 311 st.seq = m;
315 st.marker = address_markers; 312 st.marker = address_markers;
316 313
317 pgd += pgdoff; 314 for (i = 0; i < PTRS_PER_PGD; i++, pgd++) {
318
319 for (i = pgdoff; i < PTRS_PER_PGD; i++, pgd++) {
320 addr = i * PGDIR_SIZE; 315 addr = i * PGDIR_SIZE;
321 if (!pgd_none(*pgd)) { 316 if (!pgd_none(*pgd)) {
322 walk_pud(&st, pgd, addr); 317 walk_pud(&st, pgd, addr);
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 98ad9c79ea0e..2495c8cb47ba 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -658,8 +658,8 @@ static struct section_perm ro_perms[] = {
658 .start = (unsigned long)_stext, 658 .start = (unsigned long)_stext,
659 .end = (unsigned long)__init_begin, 659 .end = (unsigned long)__init_begin,
660#ifdef CONFIG_ARM_LPAE 660#ifdef CONFIG_ARM_LPAE
661 .mask = ~PMD_SECT_RDONLY, 661 .mask = ~L_PMD_SECT_RDONLY,
662 .prot = PMD_SECT_RDONLY, 662 .prot = L_PMD_SECT_RDONLY,
663#else 663#else
664 .mask = ~(PMD_SECT_APX | PMD_SECT_AP_WRITE), 664 .mask = ~(PMD_SECT_APX | PMD_SECT_AP_WRITE),
665 .prot = PMD_SECT_APX | PMD_SECT_AP_WRITE, 665 .prot = PMD_SECT_APX | PMD_SECT_AP_WRITE,
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index cda7c40999b6..4e6ef896c619 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -1329,8 +1329,8 @@ static void __init kmap_init(void)
1329static void __init map_lowmem(void) 1329static void __init map_lowmem(void)
1330{ 1330{
1331 struct memblock_region *reg; 1331 struct memblock_region *reg;
1332 unsigned long kernel_x_start = round_down(__pa(_stext), SECTION_SIZE); 1332 phys_addr_t kernel_x_start = round_down(__pa(_stext), SECTION_SIZE);
1333 unsigned long kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE); 1333 phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE);
1334 1334
1335 /* Map all the lowmem memory banks. */ 1335 /* Map all the lowmem memory banks. */
1336 for_each_memblock(memory, reg) { 1336 for_each_memblock(memory, reg) {
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-25 16:08:08 -0500