diff options
author | Tony Lindgren <tony@atomide.com> | 2009-11-22 13:08:43 -0500 |
---|---|---|
committer | Tony Lindgren <tony@atomide.com> | 2009-11-22 13:08:43 -0500 |
commit | a76df42a675c9936e8bf3607226e74c8a5e2d847 (patch) | |
tree | 96d93706d884dea956393653452fa4d78d8d7f76 /arch/arm | |
parent | 648f4e3e50c4793d9dbf9a09afa193631f76fa26 (diff) | |
parent | 8171d88089ad63fc442b2bf32af7c18653adc5cb (diff) |
Merge 7xx-iosplit-plat-merge with omap-fixes
Merge branch '7xx-iosplit-plat-merge' into omap-for-linus
Diffstat (limited to 'arch/arm')
216 files changed, 3715 insertions, 1545 deletions
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index 8ad5cc3e83e3..7fc11c34b696 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c | |||
@@ -25,13 +25,13 @@ | |||
25 | #include <asm/mach/arch.h> | 25 | #include <asm/mach/arch.h> |
26 | #include <asm/mach/map.h> | 26 | #include <asm/mach/map.h> |
27 | 27 | ||
28 | #include <mach/board-ams-delta.h> | 28 | #include <plat/board-ams-delta.h> |
29 | #include <mach/gpio.h> | 29 | #include <mach/gpio.h> |
30 | #include <mach/keypad.h> | 30 | #include <plat/keypad.h> |
31 | #include <mach/mux.h> | 31 | #include <plat/mux.h> |
32 | #include <mach/usb.h> | 32 | #include <plat/usb.h> |
33 | #include <mach/board.h> | 33 | #include <plat/board.h> |
34 | #include <mach/common.h> | 34 | #include <plat/common.h> |
35 | 35 | ||
36 | static u8 ams_delta_latch1_reg; | 36 | static u8 ams_delta_latch1_reg; |
37 | static u16 ams_delta_latch2_reg; | 37 | static u16 ams_delta_latch2_reg; |
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c index a7ead1b93226..f4b72c1654f5 100644 --- a/arch/arm/mach-omap1/board-fsample.c +++ b/arch/arm/mach-omap1/board-fsample.c | |||
@@ -26,14 +26,14 @@ | |||
26 | #include <asm/mach/flash.h> | 26 | #include <asm/mach/flash.h> |
27 | #include <asm/mach/map.h> | 27 | #include <asm/mach/map.h> |
28 | 28 | ||
29 | #include <mach/tc.h> | 29 | #include <plat/tc.h> |
30 | #include <mach/gpio.h> | 30 | #include <mach/gpio.h> |
31 | #include <mach/mux.h> | 31 | #include <plat/mux.h> |
32 | #include <mach/fpga.h> | 32 | #include <plat/fpga.h> |
33 | #include <mach/nand.h> | 33 | #include <plat/nand.h> |
34 | #include <mach/keypad.h> | 34 | #include <plat/keypad.h> |
35 | #include <mach/common.h> | 35 | #include <plat/common.h> |
36 | #include <mach/board.h> | 36 | #include <plat/board.h> |
37 | 37 | ||
38 | /* fsample is pretty close to p2-sample */ | 38 | /* fsample is pretty close to p2-sample */ |
39 | 39 | ||
@@ -107,7 +107,7 @@ static struct resource smc91x_resources[] = { | |||
107 | .flags = IORESOURCE_MEM, | 107 | .flags = IORESOURCE_MEM, |
108 | }, | 108 | }, |
109 | [1] = { | 109 | [1] = { |
110 | .start = INT_730_MPU_EXT_NIRQ, | 110 | .start = INT_7XX_MPU_EXT_NIRQ, |
111 | .end = 0, | 111 | .end = 0, |
112 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, | 112 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, |
113 | }, | 113 | }, |
@@ -196,8 +196,8 @@ static struct platform_device smc91x_device = { | |||
196 | 196 | ||
197 | static struct resource kp_resources[] = { | 197 | static struct resource kp_resources[] = { |
198 | [0] = { | 198 | [0] = { |
199 | .start = INT_730_MPUIO_KEYPAD, | 199 | .start = INT_7XX_MPUIO_KEYPAD, |
200 | .end = INT_730_MPUIO_KEYPAD, | 200 | .end = INT_7XX_MPUIO_KEYPAD, |
201 | .flags = IORESOURCE_IRQ, | 201 | .flags = IORESOURCE_IRQ, |
202 | }, | 202 | }, |
203 | }; | 203 | }; |
@@ -309,7 +309,7 @@ static void __init omap_fsample_map_io(void) | |||
309 | /* | 309 | /* |
310 | * Hold GSM Reset until needed | 310 | * Hold GSM Reset until needed |
311 | */ | 311 | */ |
312 | omap_writew(omap_readw(OMAP730_DSP_M_CTL) & ~1, OMAP730_DSP_M_CTL); | 312 | omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL); |
313 | 313 | ||
314 | /* | 314 | /* |
315 | * UARTs -> done automagically by 8250 driver | 315 | * UARTs -> done automagically by 8250 driver |
@@ -320,21 +320,21 @@ static void __init omap_fsample_map_io(void) | |||
320 | */ | 320 | */ |
321 | 321 | ||
322 | /* Flash: CS0 timings setup */ | 322 | /* Flash: CS0 timings setup */ |
323 | omap_writel(0x0000fff3, OMAP730_FLASH_CFG_0); | 323 | omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0); |
324 | omap_writel(0x00000088, OMAP730_FLASH_ACFG_0); | 324 | omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0); |
325 | 325 | ||
326 | /* | 326 | /* |
327 | * Ethernet support through the debug board | 327 | * Ethernet support through the debug board |
328 | * CS1 timings setup | 328 | * CS1 timings setup |
329 | */ | 329 | */ |
330 | omap_writel(0x0000fff3, OMAP730_FLASH_CFG_1); | 330 | omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1); |
331 | omap_writel(0x00000000, OMAP730_FLASH_ACFG_1); | 331 | omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1); |
332 | 332 | ||
333 | /* | 333 | /* |
334 | * Configure MPU_EXT_NIRQ IO in IO_CONF9 register, | 334 | * Configure MPU_EXT_NIRQ IO in IO_CONF9 register, |
335 | * It is used as the Ethernet controller interrupt | 335 | * It is used as the Ethernet controller interrupt |
336 | */ | 336 | */ |
337 | omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFFFFFF, OMAP730_IO_CONF_9); | 337 | omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF, OMAP7XX_IO_CONF_9); |
338 | } | 338 | } |
339 | 339 | ||
340 | MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample") | 340 | MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample") |
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c index 6c8a41f20e51..e1195a3467b8 100644 --- a/arch/arm/mach-omap1/board-generic.c +++ b/arch/arm/mach-omap1/board-generic.c | |||
@@ -23,10 +23,10 @@ | |||
23 | #include <asm/mach/map.h> | 23 | #include <asm/mach/map.h> |
24 | 24 | ||
25 | #include <mach/gpio.h> | 25 | #include <mach/gpio.h> |
26 | #include <mach/mux.h> | 26 | #include <plat/mux.h> |
27 | #include <mach/usb.h> | 27 | #include <plat/usb.h> |
28 | #include <mach/board.h> | 28 | #include <plat/board.h> |
29 | #include <mach/common.h> | 29 | #include <plat/common.h> |
30 | 30 | ||
31 | static void __init omap_generic_init_irq(void) | 31 | static void __init omap_generic_init_irq(void) |
32 | { | 32 | { |
diff --git a/arch/arm/mach-omap1/board-h2-mmc.c b/arch/arm/mach-omap1/board-h2-mmc.c index 46098f546824..b30c4990744d 100644 --- a/arch/arm/mach-omap1/board-h2-mmc.c +++ b/arch/arm/mach-omap1/board-h2-mmc.c | |||
@@ -16,7 +16,7 @@ | |||
16 | 16 | ||
17 | #include <linux/i2c/tps65010.h> | 17 | #include <linux/i2c/tps65010.h> |
18 | 18 | ||
19 | #include <mach/mmc.h> | 19 | #include <plat/mmc.h> |
20 | #include <mach/gpio.h> | 20 | #include <mach/gpio.h> |
21 | 21 | ||
22 | #include "board-h2.h" | 22 | #include "board-h2.h" |
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index aab860307dca..89ba8ec4bbf4 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c | |||
@@ -37,14 +37,14 @@ | |||
37 | #include <asm/mach/flash.h> | 37 | #include <asm/mach/flash.h> |
38 | #include <asm/mach/map.h> | 38 | #include <asm/mach/map.h> |
39 | 39 | ||
40 | #include <mach/mux.h> | 40 | #include <plat/mux.h> |
41 | #include <mach/dma.h> | 41 | #include <plat/dma.h> |
42 | #include <mach/tc.h> | 42 | #include <plat/tc.h> |
43 | #include <mach/nand.h> | 43 | #include <plat/nand.h> |
44 | #include <mach/irda.h> | 44 | #include <plat/irda.h> |
45 | #include <mach/usb.h> | 45 | #include <plat/usb.h> |
46 | #include <mach/keypad.h> | 46 | #include <plat/keypad.h> |
47 | #include <mach/common.h> | 47 | #include <plat/common.h> |
48 | 48 | ||
49 | #include "board-h2.h" | 49 | #include "board-h2.h" |
50 | 50 | ||
diff --git a/arch/arm/mach-omap1/board-h3-mmc.c b/arch/arm/mach-omap1/board-h3-mmc.c index 5e8877ce35e0..54b0f063e263 100644 --- a/arch/arm/mach-omap1/board-h3-mmc.c +++ b/arch/arm/mach-omap1/board-h3-mmc.c | |||
@@ -16,7 +16,7 @@ | |||
16 | 16 | ||
17 | #include <linux/i2c/tps65010.h> | 17 | #include <linux/i2c/tps65010.h> |
18 | 18 | ||
19 | #include <mach/mmc.h> | 19 | #include <plat/mmc.h> |
20 | #include <mach/gpio.h> | 20 | #include <mach/gpio.h> |
21 | 21 | ||
22 | #include "board-h3.h" | 22 | #include "board-h3.h" |
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index 89586b80b8d5..f5cc0a730524 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c | |||
@@ -40,13 +40,13 @@ | |||
40 | #include <asm/mach/map.h> | 40 | #include <asm/mach/map.h> |
41 | 41 | ||
42 | #include <mach/irqs.h> | 42 | #include <mach/irqs.h> |
43 | #include <mach/mux.h> | 43 | #include <plat/mux.h> |
44 | #include <mach/tc.h> | 44 | #include <plat/tc.h> |
45 | #include <mach/nand.h> | 45 | #include <plat/nand.h> |
46 | #include <mach/usb.h> | 46 | #include <plat/usb.h> |
47 | #include <mach/keypad.h> | 47 | #include <plat/keypad.h> |
48 | #include <mach/dma.h> | 48 | #include <plat/dma.h> |
49 | #include <mach/common.h> | 49 | #include <plat/common.h> |
50 | 50 | ||
51 | #include "board-h3.h" | 51 | #include "board-h3.h" |
52 | 52 | ||
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c index cd6c39514826..cf0fdb9c182f 100644 --- a/arch/arm/mach-omap1/board-innovator.c +++ b/arch/arm/mach-omap1/board-innovator.c | |||
@@ -30,14 +30,14 @@ | |||
30 | #include <asm/mach/flash.h> | 30 | #include <asm/mach/flash.h> |
31 | #include <asm/mach/map.h> | 31 | #include <asm/mach/map.h> |
32 | 32 | ||
33 | #include <mach/mux.h> | 33 | #include <plat/mux.h> |
34 | #include <mach/fpga.h> | 34 | #include <plat/fpga.h> |
35 | #include <mach/gpio.h> | 35 | #include <mach/gpio.h> |
36 | #include <mach/tc.h> | 36 | #include <plat/tc.h> |
37 | #include <mach/usb.h> | 37 | #include <plat/usb.h> |
38 | #include <mach/keypad.h> | 38 | #include <plat/keypad.h> |
39 | #include <mach/common.h> | 39 | #include <plat/common.h> |
40 | #include <mach/mmc.h> | 40 | #include <plat/mmc.h> |
41 | 41 | ||
42 | /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ | 42 | /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ |
43 | #define INNOVATOR1610_ETHR_START 0x04000300 | 43 | #define INNOVATOR1610_ETHR_START 0x04000300 |
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index ed2a48a9ce74..5a275bab2dfe 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c | |||
@@ -26,17 +26,17 @@ | |||
26 | #include <asm/mach/map.h> | 26 | #include <asm/mach/map.h> |
27 | 27 | ||
28 | #include <mach/gpio.h> | 28 | #include <mach/gpio.h> |
29 | #include <mach/mux.h> | 29 | #include <plat/mux.h> |
30 | #include <mach/usb.h> | 30 | #include <plat/usb.h> |
31 | #include <mach/board.h> | 31 | #include <plat/board.h> |
32 | #include <mach/keypad.h> | 32 | #include <plat/keypad.h> |
33 | #include <mach/common.h> | 33 | #include <plat/common.h> |
34 | #include <mach/dsp_common.h> | 34 | #include <plat/dsp_common.h> |
35 | #include <mach/omapfb.h> | 35 | #include <plat/omapfb.h> |
36 | #include <mach/hwa742.h> | 36 | #include <plat/hwa742.h> |
37 | #include <mach/lcd_mipid.h> | 37 | #include <plat/lcd_mipid.h> |
38 | #include <mach/mmc.h> | 38 | #include <plat/mmc.h> |
39 | #include <mach/clock.h> | 39 | #include <plat/clock.h> |
40 | 40 | ||
41 | #define ADS7846_PENDOWN_GPIO 15 | 41 | #define ADS7846_PENDOWN_GPIO 15 |
42 | 42 | ||
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index ed891b8a6b15..50c92c13e48a 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c | |||
@@ -47,10 +47,10 @@ | |||
47 | #include <asm/mach/map.h> | 47 | #include <asm/mach/map.h> |
48 | #include <asm/mach/flash.h> | 48 | #include <asm/mach/flash.h> |
49 | 49 | ||
50 | #include <mach/usb.h> | 50 | #include <plat/usb.h> |
51 | #include <mach/mux.h> | 51 | #include <plat/mux.h> |
52 | #include <mach/tc.h> | 52 | #include <plat/tc.h> |
53 | #include <mach/common.h> | 53 | #include <plat/common.h> |
54 | 54 | ||
55 | /* At OMAP5912 OSK the Ethernet is directly connected to CS1 */ | 55 | /* At OMAP5912 OSK the Ethernet is directly connected to CS1 */ |
56 | #define OMAP_OSK_ETHR_START 0x04800300 | 56 | #define OMAP_OSK_ETHR_START 0x04800300 |
@@ -312,7 +312,7 @@ static struct omap_board_config_kernel osk_config[] __initdata = { | |||
312 | #include <linux/spi/spi.h> | 312 | #include <linux/spi/spi.h> |
313 | #include <linux/spi/ads7846.h> | 313 | #include <linux/spi/ads7846.h> |
314 | 314 | ||
315 | #include <mach/keypad.h> | 315 | #include <plat/keypad.h> |
316 | 316 | ||
317 | static struct at24_platform_data at24c04 = { | 317 | static struct at24_platform_data at24c04 = { |
318 | .byte_len = SZ_4K / 8, | 318 | .byte_len = SZ_4K / 8, |
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index 4de258420f39..9fe887262bdf 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c | |||
@@ -34,14 +34,14 @@ | |||
34 | #include <asm/mach/flash.h> | 34 | #include <asm/mach/flash.h> |
35 | 35 | ||
36 | #include <mach/gpio.h> | 36 | #include <mach/gpio.h> |
37 | #include <mach/mux.h> | 37 | #include <plat/mux.h> |
38 | #include <mach/usb.h> | 38 | #include <plat/usb.h> |
39 | #include <mach/tc.h> | 39 | #include <plat/tc.h> |
40 | #include <mach/dma.h> | 40 | #include <plat/dma.h> |
41 | #include <mach/board.h> | 41 | #include <plat/board.h> |
42 | #include <mach/irda.h> | 42 | #include <plat/irda.h> |
43 | #include <mach/keypad.h> | 43 | #include <plat/keypad.h> |
44 | #include <mach/common.h> | 44 | #include <plat/common.h> |
45 | 45 | ||
46 | #define PALMTE_USBDETECT_GPIO 0 | 46 | #define PALMTE_USBDETECT_GPIO 0 |
47 | #define PALMTE_USB_OR_DC_GPIO 1 | 47 | #define PALMTE_USB_OR_DC_GPIO 1 |
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c index d972cf941b76..af068e3e0fe7 100644 --- a/arch/arm/mach-omap1/board-palmtt.c +++ b/arch/arm/mach-omap1/board-palmtt.c | |||
@@ -29,16 +29,16 @@ | |||
29 | #include <asm/mach/map.h> | 29 | #include <asm/mach/map.h> |
30 | #include <asm/mach/flash.h> | 30 | #include <asm/mach/flash.h> |
31 | 31 | ||
32 | #include <mach/led.h> | 32 | #include <plat/led.h> |
33 | #include <mach/gpio.h> | 33 | #include <mach/gpio.h> |
34 | #include <mach/mux.h> | 34 | #include <plat/mux.h> |
35 | #include <mach/usb.h> | 35 | #include <plat/usb.h> |
36 | #include <mach/dma.h> | 36 | #include <plat/dma.h> |
37 | #include <mach/tc.h> | 37 | #include <plat/tc.h> |
38 | #include <mach/board.h> | 38 | #include <plat/board.h> |
39 | #include <mach/irda.h> | 39 | #include <plat/irda.h> |
40 | #include <mach/keypad.h> | 40 | #include <plat/keypad.h> |
41 | #include <mach/common.h> | 41 | #include <plat/common.h> |
42 | 42 | ||
43 | #include <linux/spi/spi.h> | 43 | #include <linux/spi/spi.h> |
44 | #include <linux/spi/ads7846.h> | 44 | #include <linux/spi/ads7846.h> |
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index 986bd4df0e97..c7a3b6f36500 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c | |||
@@ -33,15 +33,15 @@ | |||
33 | #include <asm/mach/flash.h> | 33 | #include <asm/mach/flash.h> |
34 | 34 | ||
35 | #include <mach/gpio.h> | 35 | #include <mach/gpio.h> |
36 | #include <mach/mux.h> | 36 | #include <plat/mux.h> |
37 | #include <mach/usb.h> | 37 | #include <plat/usb.h> |
38 | #include <mach/dma.h> | 38 | #include <plat/dma.h> |
39 | #include <mach/tc.h> | 39 | #include <plat/tc.h> |
40 | #include <mach/board.h> | 40 | #include <plat/board.h> |
41 | #include <mach/irda.h> | 41 | #include <plat/irda.h> |
42 | #include <mach/keypad.h> | 42 | #include <plat/keypad.h> |
43 | #include <mach/common.h> | 43 | #include <plat/common.h> |
44 | #include <mach/omap-alsa.h> | 44 | #include <plat/omap-alsa.h> |
45 | 45 | ||
46 | #include <linux/spi/spi.h> | 46 | #include <linux/spi/spi.h> |
47 | #include <linux/spi/ads7846.h> | 47 | #include <linux/spi/ads7846.h> |
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c index 83406699f310..ca7df1e93efc 100644 --- a/arch/arm/mach-omap1/board-perseus2.c +++ b/arch/arm/mach-omap1/board-perseus2.c | |||
@@ -26,14 +26,14 @@ | |||
26 | #include <asm/mach/flash.h> | 26 | #include <asm/mach/flash.h> |
27 | #include <asm/mach/map.h> | 27 | #include <asm/mach/map.h> |
28 | 28 | ||
29 | #include <mach/tc.h> | 29 | #include <plat/tc.h> |
30 | #include <mach/gpio.h> | 30 | #include <mach/gpio.h> |
31 | #include <mach/mux.h> | 31 | #include <plat/mux.h> |
32 | #include <mach/fpga.h> | 32 | #include <plat/fpga.h> |
33 | #include <mach/nand.h> | 33 | #include <plat/nand.h> |
34 | #include <mach/keypad.h> | 34 | #include <plat/keypad.h> |
35 | #include <mach/common.h> | 35 | #include <plat/common.h> |
36 | #include <mach/board.h> | 36 | #include <plat/board.h> |
37 | 37 | ||
38 | static int p2_keymap[] = { | 38 | static int p2_keymap[] = { |
39 | KEY(0,0,KEY_UP), | 39 | KEY(0,0,KEY_UP), |
@@ -74,7 +74,7 @@ static struct resource smc91x_resources[] = { | |||
74 | .flags = IORESOURCE_MEM, | 74 | .flags = IORESOURCE_MEM, |
75 | }, | 75 | }, |
76 | [1] = { | 76 | [1] = { |
77 | .start = INT_730_MPU_EXT_NIRQ, | 77 | .start = INT_7XX_MPU_EXT_NIRQ, |
78 | .end = 0, | 78 | .end = 0, |
79 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, | 79 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, |
80 | }, | 80 | }, |
@@ -163,8 +163,8 @@ static struct platform_device smc91x_device = { | |||
163 | 163 | ||
164 | static struct resource kp_resources[] = { | 164 | static struct resource kp_resources[] = { |
165 | [0] = { | 165 | [0] = { |
166 | .start = INT_730_MPUIO_KEYPAD, | 166 | .start = INT_7XX_MPUIO_KEYPAD, |
167 | .end = INT_730_MPUIO_KEYPAD, | 167 | .end = INT_7XX_MPUIO_KEYPAD, |
168 | .flags = IORESOURCE_IRQ, | 168 | .flags = IORESOURCE_IRQ, |
169 | }, | 169 | }, |
170 | }; | 170 | }; |
@@ -270,7 +270,7 @@ static void __init omap_perseus2_map_io(void) | |||
270 | /* | 270 | /* |
271 | * Hold GSM Reset until needed | 271 | * Hold GSM Reset until needed |
272 | */ | 272 | */ |
273 | omap_writew(omap_readw(OMAP730_DSP_M_CTL) & ~1, OMAP730_DSP_M_CTL); | 273 | omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL); |
274 | 274 | ||
275 | /* | 275 | /* |
276 | * UARTs -> done automagically by 8250 driver | 276 | * UARTs -> done automagically by 8250 driver |
@@ -281,21 +281,21 @@ static void __init omap_perseus2_map_io(void) | |||
281 | */ | 281 | */ |
282 | 282 | ||
283 | /* Flash: CS0 timings setup */ | 283 | /* Flash: CS0 timings setup */ |
284 | omap_writel(0x0000fff3, OMAP730_FLASH_CFG_0); | 284 | omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0); |
285 | omap_writel(0x00000088, OMAP730_FLASH_ACFG_0); | 285 | omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0); |
286 | 286 | ||
287 | /* | 287 | /* |
288 | * Ethernet support through the debug board | 288 | * Ethernet support through the debug board |
289 | * CS1 timings setup | 289 | * CS1 timings setup |
290 | */ | 290 | */ |
291 | omap_writel(0x0000fff3, OMAP730_FLASH_CFG_1); | 291 | omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1); |
292 | omap_writel(0x00000000, OMAP730_FLASH_ACFG_1); | 292 | omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1); |
293 | 293 | ||
294 | /* | 294 | /* |
295 | * Configure MPU_EXT_NIRQ IO in IO_CONF9 register, | 295 | * Configure MPU_EXT_NIRQ IO in IO_CONF9 register, |
296 | * It is used as the Ethernet controller interrupt | 296 | * It is used as the Ethernet controller interrupt |
297 | */ | 297 | */ |
298 | omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFFFFFF, OMAP730_IO_CONF_9); | 298 | omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF, OMAP7XX_IO_CONF_9); |
299 | } | 299 | } |
300 | 300 | ||
301 | MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2") | 301 | MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2") |
diff --git a/arch/arm/mach-omap1/board-sx1-mmc.c b/arch/arm/mach-omap1/board-sx1-mmc.c index 58a46e4e45c3..5b33ae8141bc 100644 --- a/arch/arm/mach-omap1/board-sx1-mmc.c +++ b/arch/arm/mach-omap1/board-sx1-mmc.c | |||
@@ -15,9 +15,9 @@ | |||
15 | #include <linux/platform_device.h> | 15 | #include <linux/platform_device.h> |
16 | 16 | ||
17 | #include <mach/hardware.h> | 17 | #include <mach/hardware.h> |
18 | #include <mach/mmc.h> | 18 | #include <plat/mmc.h> |
19 | #include <mach/gpio.h> | 19 | #include <mach/gpio.h> |
20 | #include <mach/board-sx1.h> | 20 | #include <plat/board-sx1.h> |
21 | 21 | ||
22 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) | 22 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) |
23 | 23 | ||
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index 056ae64e0f55..7a97fac83d8d 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c | |||
@@ -33,15 +33,15 @@ | |||
33 | #include <asm/mach/map.h> | 33 | #include <asm/mach/map.h> |
34 | 34 | ||
35 | #include <mach/gpio.h> | 35 | #include <mach/gpio.h> |
36 | #include <mach/mux.h> | 36 | #include <plat/mux.h> |
37 | #include <mach/dma.h> | 37 | #include <plat/dma.h> |
38 | #include <mach/irda.h> | 38 | #include <plat/irda.h> |
39 | #include <mach/usb.h> | 39 | #include <plat/usb.h> |
40 | #include <mach/tc.h> | 40 | #include <plat/tc.h> |
41 | #include <mach/board.h> | 41 | #include <plat/board.h> |
42 | #include <mach/common.h> | 42 | #include <plat/common.h> |
43 | #include <mach/keypad.h> | 43 | #include <plat/keypad.h> |
44 | #include <mach/board-sx1.h> | 44 | #include <plat/board-sx1.h> |
45 | 45 | ||
46 | /* Write to I2C device */ | 46 | /* Write to I2C device */ |
47 | int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value) | 47 | int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value) |
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index 07b07522d5bf..35c75c1bd0aa 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c | |||
@@ -29,11 +29,11 @@ | |||
29 | #include <asm/mach/flash.h> | 29 | #include <asm/mach/flash.h> |
30 | #include <asm/mach/map.h> | 30 | #include <asm/mach/map.h> |
31 | 31 | ||
32 | #include <mach/common.h> | 32 | #include <plat/common.h> |
33 | #include <mach/gpio.h> | 33 | #include <mach/gpio.h> |
34 | #include <mach/mux.h> | 34 | #include <plat/mux.h> |
35 | #include <mach/tc.h> | 35 | #include <plat/tc.h> |
36 | #include <mach/usb.h> | 36 | #include <plat/usb.h> |
37 | 37 | ||
38 | static struct plat_serial8250_port voiceblue_ports[] = { | 38 | static struct plat_serial8250_port voiceblue_ports[] = { |
39 | { | 39 | { |
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index 436eed22801b..b4fec9a6e89e 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c | |||
@@ -22,10 +22,10 @@ | |||
22 | #include <asm/mach-types.h> | 22 | #include <asm/mach-types.h> |
23 | #include <asm/clkdev.h> | 23 | #include <asm/clkdev.h> |
24 | 24 | ||
25 | #include <mach/cpu.h> | 25 | #include <plat/cpu.h> |
26 | #include <mach/usb.h> | 26 | #include <plat/usb.h> |
27 | #include <mach/clock.h> | 27 | #include <plat/clock.h> |
28 | #include <mach/sram.h> | 28 | #include <plat/sram.h> |
29 | 29 | ||
30 | static const struct clkops clkops_generic; | 30 | static const struct clkops clkops_generic; |
31 | static const struct clkops clkops_uart; | 31 | static const struct clkops clkops_uart; |
@@ -69,13 +69,13 @@ struct omap_clk { | |||
69 | } | 69 | } |
70 | 70 | ||
71 | #define CK_310 (1 << 0) | 71 | #define CK_310 (1 << 0) |
72 | #define CK_730 (1 << 1) | 72 | #define CK_7XX (1 << 1) |
73 | #define CK_1510 (1 << 2) | 73 | #define CK_1510 (1 << 2) |
74 | #define CK_16XX (1 << 3) | 74 | #define CK_16XX (1 << 3) |
75 | 75 | ||
76 | static struct omap_clk omap_clks[] = { | 76 | static struct omap_clk omap_clks[] = { |
77 | /* non-ULPD clocks */ | 77 | /* non-ULPD clocks */ |
78 | CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310), | 78 | CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX), |
79 | CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310), | 79 | CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310), |
80 | /* CK_GEN1 clocks */ | 80 | /* CK_GEN1 clocks */ |
81 | CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX), | 81 | CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX), |
@@ -83,7 +83,7 @@ static struct omap_clk omap_clks[] = { | |||
83 | CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310), | 83 | CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310), |
84 | CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), | 84 | CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), |
85 | CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310), | 85 | CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310), |
86 | CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310), | 86 | CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), |
87 | CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310), | 87 | CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310), |
88 | CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310), | 88 | CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310), |
89 | CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX), | 89 | CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX), |
@@ -97,7 +97,7 @@ static struct omap_clk omap_clks[] = { | |||
97 | CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), | 97 | CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), |
98 | CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310), | 98 | CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310), |
99 | /* CK_GEN3 clocks */ | 99 | /* CK_GEN3 clocks */ |
100 | CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_730), | 100 | CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), |
101 | CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310), | 101 | CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310), |
102 | CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX), | 102 | CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX), |
103 | CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX), | 103 | CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX), |
@@ -108,7 +108,7 @@ static struct omap_clk omap_clks[] = { | |||
108 | CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310), | 108 | CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310), |
109 | CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX), | 109 | CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX), |
110 | CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX), | 110 | CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX), |
111 | CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_730), | 111 | CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX), |
112 | CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310), | 112 | CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310), |
113 | /* ULPD clocks */ | 113 | /* ULPD clocks */ |
114 | CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310), | 114 | CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310), |
@@ -398,7 +398,7 @@ static int omap1_select_table_rate(struct clk * clk, unsigned long rate) | |||
398 | * Reprogramming the DPLL is tricky, it must be done from SRAM. | 398 | * Reprogramming the DPLL is tricky, it must be done from SRAM. |
399 | * (on 730, bit 13 must always be 1) | 399 | * (on 730, bit 13 must always be 1) |
400 | */ | 400 | */ |
401 | if (cpu_is_omap730()) | 401 | if (cpu_is_omap7xx()) |
402 | omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000); | 402 | omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000); |
403 | else | 403 | else |
404 | omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); | 404 | omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); |
@@ -783,8 +783,8 @@ int __init omap1_clk_init(void) | |||
783 | cpu_mask |= CK_16XX; | 783 | cpu_mask |= CK_16XX; |
784 | if (cpu_is_omap1510()) | 784 | if (cpu_is_omap1510()) |
785 | cpu_mask |= CK_1510; | 785 | cpu_mask |= CK_1510; |
786 | if (cpu_is_omap730()) | 786 | if (cpu_is_omap7xx()) |
787 | cpu_mask |= CK_730; | 787 | cpu_mask |= CK_7XX; |
788 | if (cpu_is_omap310()) | 788 | if (cpu_is_omap310()) |
789 | cpu_mask |= CK_310; | 789 | cpu_mask |= CK_310; |
790 | 790 | ||
@@ -800,7 +800,7 @@ int __init omap1_clk_init(void) | |||
800 | crystal_type = info->system_clock_type; | 800 | crystal_type = info->system_clock_type; |
801 | } | 801 | } |
802 | 802 | ||
803 | #if defined(CONFIG_ARCH_OMAP730) | 803 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
804 | ck_ref.rate = 13000000; | 804 | ck_ref.rate = 13000000; |
805 | #elif defined(CONFIG_ARCH_OMAP16XX) | 805 | #elif defined(CONFIG_ARCH_OMAP16XX) |
806 | if (crystal_type == 2) | 806 | if (crystal_type == 2) |
@@ -847,7 +847,7 @@ int __init omap1_clk_init(void) | |||
847 | printk(KERN_ERR "System frequencies not set. Check your config.\n"); | 847 | printk(KERN_ERR "System frequencies not set. Check your config.\n"); |
848 | /* Guess sane values (60MHz) */ | 848 | /* Guess sane values (60MHz) */ |
849 | omap_writew(0x2290, DPLL_CTL); | 849 | omap_writew(0x2290, DPLL_CTL); |
850 | omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL); | 850 | omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL); |
851 | ck_dpll1.rate = 60000000; | 851 | ck_dpll1.rate = 60000000; |
852 | } | 852 | } |
853 | #endif | 853 | #endif |
@@ -862,7 +862,7 @@ int __init omap1_clk_init(void) | |||
862 | 862 | ||
863 | #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE) | 863 | #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE) |
864 | /* Select slicer output as OMAP input clock */ | 864 | /* Select slicer output as OMAP input clock */ |
865 | omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL); | 865 | omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL); |
866 | #endif | 866 | #endif |
867 | 867 | ||
868 | /* Amstrad Delta wants BCLK high when inactive */ | 868 | /* Amstrad Delta wants BCLK high when inactive */ |
@@ -873,7 +873,7 @@ int __init omap1_clk_init(void) | |||
873 | 873 | ||
874 | /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ | 874 | /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ |
875 | /* (on 730, bit 13 must not be cleared) */ | 875 | /* (on 730, bit 13 must not be cleared) */ |
876 | if (cpu_is_omap730()) | 876 | if (cpu_is_omap7xx()) |
877 | omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); | 877 | omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); |
878 | else | 878 | else |
879 | omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); | 879 | omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); |
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index 06808434ea04..6d2f72dcbb04 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c | |||
@@ -18,11 +18,11 @@ | |||
18 | #include <mach/hardware.h> | 18 | #include <mach/hardware.h> |
19 | #include <asm/mach/map.h> | 19 | #include <asm/mach/map.h> |
20 | 20 | ||
21 | #include <mach/tc.h> | 21 | #include <plat/tc.h> |
22 | #include <mach/board.h> | 22 | #include <plat/board.h> |
23 | #include <mach/mux.h> | 23 | #include <plat/mux.h> |
24 | #include <mach/gpio.h> | 24 | #include <mach/gpio.h> |
25 | #include <mach/mmc.h> | 25 | #include <plat/mmc.h> |
26 | 26 | ||
27 | /*-------------------------------------------------------------------------*/ | 27 | /*-------------------------------------------------------------------------*/ |
28 | 28 | ||
diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c index 4f2b8a7adb19..5cfce1636da0 100644 --- a/arch/arm/mach-omap1/fpga.c +++ b/arch/arm/mach-omap1/fpga.c | |||
@@ -27,7 +27,7 @@ | |||
27 | #include <asm/irq.h> | 27 | #include <asm/irq.h> |
28 | #include <asm/mach/irq.h> | 28 | #include <asm/mach/irq.h> |
29 | 29 | ||
30 | #include <mach/fpga.h> | 30 | #include <plat/fpga.h> |
31 | #include <mach/gpio.h> | 31 | #include <mach/gpio.h> |
32 | 32 | ||
33 | static void fpga_mask_irq(unsigned int irq) | 33 | static void fpga_mask_irq(unsigned int irq) |
diff --git a/arch/arm/mach-omap1/id.c b/arch/arm/mach-omap1/id.c index e5dcdf764c91..a0e3560b39db 100644 --- a/arch/arm/mach-omap1/id.c +++ b/arch/arm/mach-omap1/id.c | |||
@@ -15,7 +15,7 @@ | |||
15 | #include <linux/kernel.h> | 15 | #include <linux/kernel.h> |
16 | #include <linux/init.h> | 16 | #include <linux/init.h> |
17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
18 | #include <mach/cpu.h> | 18 | #include <plat/cpu.h> |
19 | 19 | ||
20 | #define OMAP_DIE_ID_0 0xfffe1800 | 20 | #define OMAP_DIE_ID_0 0xfffe1800 |
21 | #define OMAP_DIE_ID_1 0xfffe1804 | 21 | #define OMAP_DIE_ID_1 0xfffe1804 |
diff --git a/arch/arm/mach-omap1/include/mach/clkdev.h b/arch/arm/mach-omap1/include/mach/clkdev.h new file mode 100644 index 000000000000..ea8640e4603e --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/clkdev.h | |||
@@ -0,0 +1,5 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-omap1/include/mach/clkdev.h | ||
3 | */ | ||
4 | |||
5 | #include <plat/clkdev.h> | ||
diff --git a/arch/arm/mach-omap1/include/mach/debug-macro.S b/arch/arm/mach-omap1/include/mach/debug-macro.S new file mode 100644 index 000000000000..aedb746fc33c --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/debug-macro.S | |||
@@ -0,0 +1,45 @@ | |||
1 | /* arch/arm/mach-omap1/include/mach/debug-macro.S | ||
2 | * | ||
3 | * Debugging macro include header | ||
4 | * | ||
5 | * Copyright (C) 1994-1999 Russell King | ||
6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | .macro addruart,rx | ||
15 | mrc p15, 0, \rx, c1, c0 | ||
16 | tst \rx, #1 @ MMU enabled? | ||
17 | moveq \rx, #0xff000000 @ physical base address | ||
18 | movne \rx, #0xfe000000 @ virtual base | ||
19 | orr \rx, \rx, #0x00fb0000 | ||
20 | #ifdef CONFIG_OMAP_LL_DEBUG_UART3 | ||
21 | orr \rx, \rx, #0x00009000 @ UART 3 | ||
22 | #endif | ||
23 | #if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3) | ||
24 | orr \rx, \rx, #0x00000800 @ UART 2 & 3 | ||
25 | #endif | ||
26 | .endm | ||
27 | |||
28 | .macro senduart,rd,rx | ||
29 | strb \rd, [\rx] | ||
30 | .endm | ||
31 | |||
32 | .macro busyuart,rd,rx | ||
33 | 1001: ldrb \rd, [\rx, #(0x5 << 2)] @ OMAP-1510 and friends | ||
34 | and \rd, \rd, #0x60 | ||
35 | teq \rd, #0x60 | ||
36 | beq 1002f | ||
37 | ldrb \rd, [\rx, #(0x5 << 0)] @ OMAP-730 only | ||
38 | and \rd, \rd, #0x60 | ||
39 | teq \rd, #0x60 | ||
40 | bne 1001b | ||
41 | 1002: | ||
42 | .endm | ||
43 | |||
44 | .macro waituart,rd,rx | ||
45 | .endm | ||
diff --git a/arch/arm/mach-omap1/include/mach/entry-macro.S b/arch/arm/mach-omap1/include/mach/entry-macro.S new file mode 100644 index 000000000000..df9060edda28 --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/entry-macro.S | |||
@@ -0,0 +1,58 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-omap1/include/mach/entry-macro.S | ||
3 | * | ||
4 | * Low-level IRQ helper macros for OMAP-based platforms | ||
5 | * | ||
6 | * Copyright (C) 2009 Texas Instruments | ||
7 | * | ||
8 | * This file is licensed under the terms of the GNU General Public | ||
9 | * License version 2. This program is licensed "as is" without any | ||
10 | * warranty of any kind, whether express or implied. | ||
11 | */ | ||
12 | #include <mach/hardware.h> | ||
13 | #include <mach/io.h> | ||
14 | #include <mach/irqs.h> | ||
15 | #include <asm/hardware/gic.h> | ||
16 | |||
17 | #if (defined(CONFIG_ARCH_OMAP730)||defined(CONFIG_ARCH_OMAP850)) && \ | ||
18 | (defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)) | ||
19 | #error "FIXME: OMAP7XX doesn't support multiple-OMAP" | ||
20 | #elif defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) | ||
21 | #define INT_IH2_IRQ INT_7XX_IH2_IRQ | ||
22 | #elif defined(CONFIG_ARCH_OMAP15XX) | ||
23 | #define INT_IH2_IRQ INT_1510_IH2_IRQ | ||
24 | #elif defined(CONFIG_ARCH_OMAP16XX) | ||
25 | #define INT_IH2_IRQ INT_1610_IH2_IRQ | ||
26 | #else | ||
27 | #warning "IH2 IRQ defaulted" | ||
28 | #define INT_IH2_IRQ INT_1510_IH2_IRQ | ||
29 | #endif | ||
30 | |||
31 | .macro disable_fiq | ||
32 | .endm | ||
33 | |||
34 | .macro get_irqnr_preamble, base, tmp | ||
35 | .endm | ||
36 | |||
37 | .macro arch_ret_to_user, tmp1, tmp2 | ||
38 | .endm | ||
39 | |||
40 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
41 | ldr \base, =OMAP1_IO_ADDRESS(OMAP_IH1_BASE) | ||
42 | ldr \irqnr, [\base, #IRQ_ITR_REG_OFFSET] | ||
43 | ldr \tmp, [\base, #IRQ_MIR_REG_OFFSET] | ||
44 | mov \irqstat, #0xffffffff | ||
45 | bic \tmp, \irqstat, \tmp | ||
46 | tst \irqnr, \tmp | ||
47 | beq 1510f | ||
48 | |||
49 | ldr \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET] | ||
50 | cmp \irqnr, #0 | ||
51 | ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET] | ||
52 | cmpeq \irqnr, #INT_IH2_IRQ | ||
53 | ldreq \base, =OMAP1_IO_ADDRESS(OMAP_IH2_BASE) | ||
54 | ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET] | ||
55 | addeqs \irqnr, \irqnr, #32 | ||
56 | 1510: | ||
57 | .endm | ||
58 | |||
diff --git a/arch/arm/mach-omap1/include/mach/gpio.h b/arch/arm/mach-omap1/include/mach/gpio.h new file mode 100644 index 000000000000..e737706a8fe1 --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/gpio.h | |||
@@ -0,0 +1,5 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-omap1/include/mach/gpio.h | ||
3 | */ | ||
4 | |||
5 | #include <plat/gpio.h> | ||
diff --git a/arch/arm/mach-omap1/include/mach/hardware.h b/arch/arm/mach-omap1/include/mach/hardware.h new file mode 100644 index 000000000000..a3f6287b2007 --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/hardware.h | |||
@@ -0,0 +1,5 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-omap1/include/mach/hardware.h | ||
3 | */ | ||
4 | |||
5 | #include <plat/hardware.h> | ||
diff --git a/arch/arm/mach-omap1/include/mach/io.h b/arch/arm/mach-omap1/include/mach/io.h new file mode 100644 index 000000000000..57bdf74a3e64 --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/io.h | |||
@@ -0,0 +1,5 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-omap1/include/mach/io.h | ||
3 | */ | ||
4 | |||
5 | #include <plat/io.h> | ||
diff --git a/arch/arm/mach-omap1/include/mach/irqs.h b/arch/arm/mach-omap1/include/mach/irqs.h new file mode 100644 index 000000000000..9292fdc1cb0b --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/irqs.h | |||
@@ -0,0 +1,5 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-omap1/include/mach/irqs.h | ||
3 | */ | ||
4 | |||
5 | #include <plat/irqs.h> | ||
diff --git a/arch/arm/mach-omap1/include/mach/memory.h b/arch/arm/mach-omap1/include/mach/memory.h new file mode 100644 index 000000000000..e9b600c113ef --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/memory.h | |||
@@ -0,0 +1,5 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-omap1/include/mach/memory.h | ||
3 | */ | ||
4 | |||
5 | #include <plat/memory.h> | ||
diff --git a/arch/arm/plat-omap/include/mach/mtd-xip.h b/arch/arm/mach-omap1/include/mach/mtd-xip.h index f82a8dcaad94..f82a8dcaad94 100644 --- a/arch/arm/plat-omap/include/mach/mtd-xip.h +++ b/arch/arm/mach-omap1/include/mach/mtd-xip.h | |||
diff --git a/arch/arm/mach-omap1/include/mach/smp.h b/arch/arm/mach-omap1/include/mach/smp.h new file mode 100644 index 000000000000..80a371c06e59 --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/smp.h | |||
@@ -0,0 +1,5 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-omap1/include/mach/smp.h | ||
3 | */ | ||
4 | |||
5 | #include <plat/smp.h> | ||
diff --git a/arch/arm/mach-omap1/include/mach/system.h b/arch/arm/mach-omap1/include/mach/system.h new file mode 100644 index 000000000000..a6c1b3a16dfc --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/system.h | |||
@@ -0,0 +1,5 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-omap1/include/mach/system.h | ||
3 | */ | ||
4 | |||
5 | #include <plat/system.h> | ||
diff --git a/arch/arm/mach-omap1/include/mach/timex.h b/arch/arm/mach-omap1/include/mach/timex.h new file mode 100644 index 000000000000..4793790d53cc --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/timex.h | |||
@@ -0,0 +1,5 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-omap1/include/mach/timex.h | ||
3 | */ | ||
4 | |||
5 | #include <plat/timex.h> | ||
diff --git a/arch/arm/mach-omap1/include/mach/uncompress.h b/arch/arm/mach-omap1/include/mach/uncompress.h new file mode 100644 index 000000000000..0ff22dc075c7 --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/uncompress.h | |||
@@ -0,0 +1,5 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-omap1/include/mach/uncompress.h | ||
3 | */ | ||
4 | |||
5 | #include <plat/uncompress.h> | ||
diff --git a/arch/arm/mach-omap1/include/mach/vmalloc.h b/arch/arm/mach-omap1/include/mach/vmalloc.h new file mode 100644 index 000000000000..1b2af14df151 --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/vmalloc.h | |||
@@ -0,0 +1,20 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-omap1/include/mach/vmalloc.h | ||
3 | * | ||
4 | * Copyright (C) 2000 Russell King. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | */ | ||
20 | #define VMALLOC_END (PAGE_OFFSET + 0x18000000) | ||
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c index 7030f9281ea1..2a6d68aa3489 100644 --- a/arch/arm/mach-omap1/io.c +++ b/arch/arm/mach-omap1/io.c | |||
@@ -15,8 +15,8 @@ | |||
15 | 15 | ||
16 | #include <asm/tlb.h> | 16 | #include <asm/tlb.h> |
17 | #include <asm/mach/map.h> | 17 | #include <asm/mach/map.h> |
18 | #include <mach/mux.h> | 18 | #include <plat/mux.h> |
19 | #include <mach/tc.h> | 19 | #include <plat/tc.h> |
20 | 20 | ||
21 | extern int omap1_clk_init(void); | 21 | extern int omap1_clk_init(void); |
22 | extern void omap_check_revision(void); | 22 | extern void omap_check_revision(void); |
@@ -36,33 +36,17 @@ static struct map_desc omap_io_desc[] __initdata = { | |||
36 | } | 36 | } |
37 | }; | 37 | }; |
38 | 38 | ||
39 | #ifdef CONFIG_ARCH_OMAP730 | 39 | #if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850) |
40 | static struct map_desc omap730_io_desc[] __initdata = { | 40 | static struct map_desc omap7xx_io_desc[] __initdata = { |
41 | { | 41 | { |
42 | .virtual = OMAP730_DSP_BASE, | 42 | .virtual = OMAP7XX_DSP_BASE, |
43 | .pfn = __phys_to_pfn(OMAP730_DSP_START), | 43 | .pfn = __phys_to_pfn(OMAP7XX_DSP_START), |
44 | .length = OMAP730_DSP_SIZE, | 44 | .length = OMAP7XX_DSP_SIZE, |
45 | .type = MT_DEVICE | 45 | .type = MT_DEVICE |
46 | }, { | 46 | }, { |
47 | .virtual = OMAP730_DSPREG_BASE, | 47 | .virtual = OMAP7XX_DSPREG_BASE, |
48 | .pfn = __phys_to_pfn(OMAP730_DSPREG_START), | 48 | .pfn = __phys_to_pfn(OMAP7XX_DSPREG_START), |
49 | .length = OMAP730_DSPREG_SIZE, | 49 | .length = OMAP7XX_DSPREG_SIZE, |
50 | .type = MT_DEVICE | ||
51 | } | ||
52 | }; | ||
53 | #endif | ||
54 | |||
55 | #ifdef CONFIG_ARCH_OMAP850 | ||
56 | static struct map_desc omap850_io_desc[] __initdata = { | ||
57 | { | ||
58 | .virtual = OMAP850_DSP_BASE, | ||
59 | .pfn = __phys_to_pfn(OMAP850_DSP_START), | ||
60 | .length = OMAP850_DSP_SIZE, | ||
61 | .type = MT_DEVICE | ||
62 | }, { | ||
63 | .virtual = OMAP850_DSPREG_BASE, | ||
64 | .pfn = __phys_to_pfn(OMAP850_DSPREG_START), | ||
65 | .length = OMAP850_DSPREG_SIZE, | ||
66 | .type = MT_DEVICE | 50 | .type = MT_DEVICE |
67 | } | 51 | } |
68 | }; | 52 | }; |
@@ -120,18 +104,11 @@ void __init omap1_map_common_io(void) | |||
120 | */ | 104 | */ |
121 | omap_check_revision(); | 105 | omap_check_revision(); |
122 | 106 | ||
123 | #ifdef CONFIG_ARCH_OMAP730 | 107 | #if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850) |
124 | if (cpu_is_omap730()) { | 108 | if (cpu_is_omap7xx()) { |
125 | iotable_init(omap730_io_desc, ARRAY_SIZE(omap730_io_desc)); | 109 | iotable_init(omap7xx_io_desc, ARRAY_SIZE(omap7xx_io_desc)); |
126 | } | ||
127 | #endif | ||
128 | |||
129 | #ifdef CONFIG_ARCH_OMAP850 | ||
130 | if (cpu_is_omap850()) { | ||
131 | iotable_init(omap850_io_desc, ARRAY_SIZE(omap850_io_desc)); | ||
132 | } | 110 | } |
133 | #endif | 111 | #endif |
134 | |||
135 | #ifdef CONFIG_ARCH_OMAP15XX | 112 | #ifdef CONFIG_ARCH_OMAP15XX |
136 | if (cpu_is_omap15xx()) { | 113 | if (cpu_is_omap15xx()) { |
137 | iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc)); | 114 | iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc)); |
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c index de03c8448994..db913c34d1fe 100644 --- a/arch/arm/mach-omap1/irq.c +++ b/arch/arm/mach-omap1/irq.c | |||
@@ -46,7 +46,7 @@ | |||
46 | #include <asm/irq.h> | 46 | #include <asm/irq.h> |
47 | #include <asm/mach/irq.h> | 47 | #include <asm/mach/irq.h> |
48 | #include <mach/gpio.h> | 48 | #include <mach/gpio.h> |
49 | #include <mach/cpu.h> | 49 | #include <plat/cpu.h> |
50 | 50 | ||
51 | #define IRQ_BANK(irq) ((irq) >> 5) | 51 | #define IRQ_BANK(irq) ((irq) >> 5) |
52 | #define IRQ_BIT(irq) ((irq) & 0x1f) | 52 | #define IRQ_BIT(irq) ((irq) & 0x1f) |
@@ -137,16 +137,8 @@ static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger) | |||
137 | irq_bank_writel(val, bank, offset); | 137 | irq_bank_writel(val, bank, offset); |
138 | } | 138 | } |
139 | 139 | ||
140 | #ifdef CONFIG_ARCH_OMAP730 | 140 | #if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850) |
141 | static struct omap_irq_bank omap730_irq_banks[] = { | 141 | static struct omap_irq_bank omap7xx_irq_banks[] = { |
142 | { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f }, | ||
143 | { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 }, | ||
144 | { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 }, | ||
145 | }; | ||
146 | #endif | ||
147 | |||
148 | #ifdef CONFIG_ARCH_OMAP850 | ||
149 | static struct omap_irq_bank omap850_irq_banks[] = { | ||
150 | { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f }, | 142 | { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f }, |
151 | { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 }, | 143 | { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 }, |
152 | { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 }, | 144 | { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 }, |
@@ -186,16 +178,10 @@ void __init omap_init_irq(void) | |||
186 | { | 178 | { |
187 | int i, j; | 179 | int i, j; |
188 | 180 | ||
189 | #ifdef CONFIG_ARCH_OMAP730 | 181 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
190 | if (cpu_is_omap730()) { | 182 | if (cpu_is_omap7xx()) { |
191 | irq_banks = omap730_irq_banks; | 183 | irq_banks = omap7xx_irq_banks; |
192 | irq_bank_count = ARRAY_SIZE(omap730_irq_banks); | 184 | irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks); |
193 | } | ||
194 | #endif | ||
195 | #ifdef CONFIG_ARCH_OMAP850 | ||
196 | if (cpu_is_omap850()) { | ||
197 | irq_banks = omap850_irq_banks; | ||
198 | irq_bank_count = ARRAY_SIZE(omap850_irq_banks); | ||
199 | } | 185 | } |
200 | #endif | 186 | #endif |
201 | #ifdef CONFIG_ARCH_OMAP15XX | 187 | #ifdef CONFIG_ARCH_OMAP15XX |
@@ -247,10 +233,8 @@ void __init omap_init_irq(void) | |||
247 | 233 | ||
248 | /* Unmask level 2 handler */ | 234 | /* Unmask level 2 handler */ |
249 | 235 | ||
250 | if (cpu_is_omap730()) | 236 | if (cpu_is_omap7xx()) |
251 | omap_unmask_irq(INT_730_IH2_IRQ); | 237 | omap_unmask_irq(INT_7XX_IH2_IRQ); |
252 | else if (cpu_is_omap850()) | ||
253 | omap_unmask_irq(INT_850_IH2_IRQ); | ||
254 | else if (cpu_is_omap15xx()) | 238 | else if (cpu_is_omap15xx()) |
255 | omap_unmask_irq(INT_1510_IH2_IRQ); | 239 | omap_unmask_irq(INT_1510_IH2_IRQ); |
256 | else if (cpu_is_omap16xx()) | 240 | else if (cpu_is_omap16xx()) |
diff --git a/arch/arm/mach-omap1/leds-h2p2-debug.c b/arch/arm/mach-omap1/leds-h2p2-debug.c index 17c9d0e04216..b4f9be52e1e8 100644 --- a/arch/arm/mach-omap1/leds-h2p2-debug.c +++ b/arch/arm/mach-omap1/leds-h2p2-debug.c | |||
@@ -19,7 +19,7 @@ | |||
19 | #include <asm/system.h> | 19 | #include <asm/system.h> |
20 | #include <asm/mach-types.h> | 20 | #include <asm/mach-types.h> |
21 | 21 | ||
22 | #include <mach/fpga.h> | 22 | #include <plat/fpga.h> |
23 | #include <mach/gpio.h> | 23 | #include <mach/gpio.h> |
24 | 24 | ||
25 | #include "leds.h" | 25 | #include "leds.h" |
diff --git a/arch/arm/mach-omap1/leds.c b/arch/arm/mach-omap1/leds.c index 8cbf2562dcaa..277f356d4cd0 100644 --- a/arch/arm/mach-omap1/leds.c +++ b/arch/arm/mach-omap1/leds.c | |||
@@ -10,7 +10,7 @@ | |||
10 | #include <asm/mach-types.h> | 10 | #include <asm/mach-types.h> |
11 | 11 | ||
12 | #include <mach/gpio.h> | 12 | #include <mach/gpio.h> |
13 | #include <mach/mux.h> | 13 | #include <plat/mux.h> |
14 | 14 | ||
15 | #include "leds.h" | 15 | #include "leds.h" |
16 | 16 | ||
diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c index 6810b4aeb02c..caf889aaa248 100644 --- a/arch/arm/mach-omap1/mailbox.c +++ b/arch/arm/mach-omap1/mailbox.c | |||
@@ -14,7 +14,7 @@ | |||
14 | #include <linux/interrupt.h> | 14 | #include <linux/interrupt.h> |
15 | #include <linux/platform_device.h> | 15 | #include <linux/platform_device.h> |
16 | #include <linux/io.h> | 16 | #include <linux/io.h> |
17 | #include <mach/mailbox.h> | 17 | #include <plat/mailbox.h> |
18 | #include <mach/irqs.h> | 18 | #include <mach/irqs.h> |
19 | 19 | ||
20 | #define MAILBOX_ARM2DSP1 0x00 | 20 | #define MAILBOX_ARM2DSP1 0x00 |
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c index 505d98cfe508..6bddce104ee9 100644 --- a/arch/arm/mach-omap1/mcbsp.c +++ b/arch/arm/mach-omap1/mcbsp.c | |||
@@ -18,11 +18,11 @@ | |||
18 | #include <linux/platform_device.h> | 18 | #include <linux/platform_device.h> |
19 | 19 | ||
20 | #include <mach/irqs.h> | 20 | #include <mach/irqs.h> |
21 | #include <mach/dma.h> | 21 | #include <plat/dma.h> |
22 | #include <mach/mux.h> | 22 | #include <plat/mux.h> |
23 | #include <mach/cpu.h> | 23 | #include <plat/cpu.h> |
24 | #include <mach/mcbsp.h> | 24 | #include <plat/mcbsp.h> |
25 | #include <mach/dsp_common.h> | 25 | #include <plat/dsp_common.h> |
26 | 26 | ||
27 | #define DPS_RSTCT2_PER_EN (1 << 0) | 27 | #define DPS_RSTCT2_PER_EN (1 << 0) |
28 | #define DSP_RSTCT2_WD_PER_EN (1 << 1) | 28 | #define DSP_RSTCT2_WD_PER_EN (1 << 1) |
@@ -79,29 +79,29 @@ static struct omap_mcbsp_ops omap1_mcbsp_ops = { | |||
79 | .free = omap1_mcbsp_free, | 79 | .free = omap1_mcbsp_free, |
80 | }; | 80 | }; |
81 | 81 | ||
82 | #ifdef CONFIG_ARCH_OMAP730 | 82 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
83 | static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = { | 83 | static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = { |
84 | { | 84 | { |
85 | .phys_base = OMAP730_MCBSP1_BASE, | 85 | .phys_base = OMAP7XX_MCBSP1_BASE, |
86 | .dma_rx_sync = OMAP_DMA_MCBSP1_RX, | 86 | .dma_rx_sync = OMAP_DMA_MCBSP1_RX, |
87 | .dma_tx_sync = OMAP_DMA_MCBSP1_TX, | 87 | .dma_tx_sync = OMAP_DMA_MCBSP1_TX, |
88 | .rx_irq = INT_730_McBSP1RX, | 88 | .rx_irq = INT_7XX_McBSP1RX, |
89 | .tx_irq = INT_730_McBSP1TX, | 89 | .tx_irq = INT_7XX_McBSP1TX, |
90 | .ops = &omap1_mcbsp_ops, | 90 | .ops = &omap1_mcbsp_ops, |
91 | }, | 91 | }, |
92 | { | 92 | { |
93 | .phys_base = OMAP730_MCBSP2_BASE, | 93 | .phys_base = OMAP7XX_MCBSP2_BASE, |
94 | .dma_rx_sync = OMAP_DMA_MCBSP3_RX, | 94 | .dma_rx_sync = OMAP_DMA_MCBSP3_RX, |
95 | .dma_tx_sync = OMAP_DMA_MCBSP3_TX, | 95 | .dma_tx_sync = OMAP_DMA_MCBSP3_TX, |
96 | .rx_irq = INT_730_McBSP2RX, | 96 | .rx_irq = INT_7XX_McBSP2RX, |
97 | .tx_irq = INT_730_McBSP2TX, | 97 | .tx_irq = INT_7XX_McBSP2TX, |
98 | .ops = &omap1_mcbsp_ops, | 98 | .ops = &omap1_mcbsp_ops, |
99 | }, | 99 | }, |
100 | }; | 100 | }; |
101 | #define OMAP730_MCBSP_PDATA_SZ ARRAY_SIZE(omap730_mcbsp_pdata) | 101 | #define OMAP7XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap7xx_mcbsp_pdata) |
102 | #else | 102 | #else |
103 | #define omap730_mcbsp_pdata NULL | 103 | #define omap7xx_mcbsp_pdata NULL |
104 | #define OMAP730_MCBSP_PDATA_SZ 0 | 104 | #define OMAP7XX_MCBSP_PDATA_SZ 0 |
105 | #endif | 105 | #endif |
106 | 106 | ||
107 | #ifdef CONFIG_ARCH_OMAP15XX | 107 | #ifdef CONFIG_ARCH_OMAP15XX |
@@ -172,8 +172,8 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = { | |||
172 | 172 | ||
173 | int __init omap1_mcbsp_init(void) | 173 | int __init omap1_mcbsp_init(void) |
174 | { | 174 | { |
175 | if (cpu_is_omap730()) | 175 | if (cpu_is_omap7xx()) |
176 | omap_mcbsp_count = OMAP730_MCBSP_PDATA_SZ; | 176 | omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ; |
177 | if (cpu_is_omap15xx()) | 177 | if (cpu_is_omap15xx()) |
178 | omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ; | 178 | omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ; |
179 | if (cpu_is_omap16xx()) | 179 | if (cpu_is_omap16xx()) |
@@ -184,9 +184,9 @@ int __init omap1_mcbsp_init(void) | |||
184 | if (!mcbsp_ptr) | 184 | if (!mcbsp_ptr) |
185 | return -ENOMEM; | 185 | return -ENOMEM; |
186 | 186 | ||
187 | if (cpu_is_omap730()) | 187 | if (cpu_is_omap7xx()) |
188 | omap_mcbsp_register_board_cfg(omap730_mcbsp_pdata, | 188 | omap_mcbsp_register_board_cfg(omap7xx_mcbsp_pdata, |
189 | OMAP730_MCBSP_PDATA_SZ); | 189 | OMAP7XX_MCBSP_PDATA_SZ); |
190 | 190 | ||
191 | if (cpu_is_omap15xx()) | 191 | if (cpu_is_omap15xx()) |
192 | omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata, | 192 | omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata, |
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c index 721e0d9d8b1d..1e6145c9ee93 100644 --- a/arch/arm/mach-omap1/mux.c +++ b/arch/arm/mach-omap1/mux.c | |||
@@ -29,53 +29,34 @@ | |||
29 | 29 | ||
30 | #include <asm/system.h> | 30 | #include <asm/system.h> |
31 | 31 | ||
32 | #include <mach/mux.h> | 32 | #include <plat/mux.h> |
33 | 33 | ||
34 | #ifdef CONFIG_OMAP_MUX | 34 | #ifdef CONFIG_OMAP_MUX |
35 | 35 | ||
36 | static struct omap_mux_cfg arch_mux_cfg; | 36 | static struct omap_mux_cfg arch_mux_cfg; |
37 | 37 | ||
38 | #ifdef CONFIG_ARCH_OMAP730 | 38 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
39 | static struct pin_config __initdata_or_module omap730_pins[] = { | 39 | static struct pin_config __initdata_or_module omap7xx_pins[] = { |
40 | MUX_CFG_730("E2_730_KBR0", 12, 21, 0, 20, 1, 0) | 40 | MUX_CFG_7XX("E2_7XX_KBR0", 12, 21, 0, 20, 1, 0) |
41 | MUX_CFG_730("J7_730_KBR1", 12, 25, 0, 24, 1, 0) | 41 | MUX_CFG_7XX("J7_7XX_KBR1", 12, 25, 0, 24, 1, 0) |
42 | MUX_CFG_730("E1_730_KBR2", 12, 29, 0, 28, 1, 0) | 42 | MUX_CFG_7XX("E1_7XX_KBR2", 12, 29, 0, 28, 1, 0) |
43 | MUX_CFG_730("F3_730_KBR3", 13, 1, 0, 0, 1, 0) | 43 | MUX_CFG_7XX("F3_7XX_KBR3", 13, 1, 0, 0, 1, 0) |
44 | MUX_CFG_730("D2_730_KBR4", 13, 5, 0, 4, 1, 0) | 44 | MUX_CFG_7XX("D2_7XX_KBR4", 13, 5, 0, 4, 1, 0) |
45 | MUX_CFG_730("C2_730_KBC0", 13, 9, 0, 8, 1, 0) | 45 | MUX_CFG_7XX("C2_7XX_KBC0", 13, 9, 0, 8, 1, 0) |
46 | MUX_CFG_730("D3_730_KBC1", 13, 13, 0, 12, 1, 0) | 46 | MUX_CFG_7XX("D3_7XX_KBC1", 13, 13, 0, 12, 1, 0) |
47 | MUX_CFG_730("E4_730_KBC2", 13, 17, 0, 16, 1, 0) | 47 | MUX_CFG_7XX("E4_7XX_KBC2", 13, 17, 0, 16, 1, 0) |
48 | MUX_CFG_730("F4_730_KBC3", 13, 21, 0, 20, 1, 0) | 48 | MUX_CFG_7XX("F4_7XX_KBC3", 13, 21, 0, 20, 1, 0) |
49 | MUX_CFG_730("E3_730_KBC4", 13, 25, 0, 24, 1, 0) | 49 | MUX_CFG_7XX("E3_7XX_KBC4", 13, 25, 0, 24, 1, 0) |
50 | 50 | ||
51 | MUX_CFG_730("AA17_730_USB_DM", 2, 21, 0, 20, 0, 0) | 51 | MUX_CFG_7XX("AA17_7XX_USB_DM", 2, 21, 0, 20, 0, 0) |
52 | MUX_CFG_730("W16_730_USB_PU_EN", 2, 25, 0, 24, 0, 0) | 52 | MUX_CFG_7XX("W16_7XX_USB_PU_EN", 2, 25, 0, 24, 0, 0) |
53 | MUX_CFG_730("W17_730_USB_VBUSI", 2, 29, 0, 28, 0, 0) | 53 | MUX_CFG_7XX("W17_7XX_USB_VBUSI", 2, 29, 0, 28, 0, 0) |
54 | }; | 54 | }; |
55 | #define OMAP730_PINS_SZ ARRAY_SIZE(omap730_pins) | 55 | #define OMAP7XX_PINS_SZ ARRAY_SIZE(omap7xx_pins) |
56 | #else | 56 | #else |
57 | #define omap730_pins NULL | 57 | #define omap7xx_pins NULL |
58 | #define OMAP730_PINS_SZ 0 | 58 | #define OMAP7XX_PINS_SZ 0 |
59 | #endif /* CONFIG_ARCH_OMAP730 */ | 59 | #endif /* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */ |
60 | |||
61 | #ifdef CONFIG_ARCH_OMAP850 | ||
62 | struct pin_config __initdata_or_module omap850_pins[] = { | ||
63 | MUX_CFG_850("E2_850_KBR0", 12, 21, 0, 20, 1, 0) | ||
64 | MUX_CFG_850("J7_850_KBR1", 12, 25, 0, 24, 1, 0) | ||
65 | MUX_CFG_850("E1_850_KBR2", 12, 29, 0, 28, 1, 0) | ||
66 | MUX_CFG_850("F3_850_KBR3", 13, 1, 0, 0, 1, 0) | ||
67 | MUX_CFG_850("D2_850_KBR4", 13, 5, 0, 4, 1, 0) | ||
68 | MUX_CFG_850("C2_850_KBC0", 13, 9, 0, 8, 1, 0) | ||
69 | MUX_CFG_850("D3_850_KBC1", 13, 13, 0, 12, 1, 0) | ||
70 | MUX_CFG_850("E4_850_KBC2", 13, 17, 0, 16, 1, 0) | ||
71 | MUX_CFG_850("F4_850_KBC3", 13, 21, 0, 20, 1, 0) | ||
72 | MUX_CFG_850("E3_850_KBC4", 13, 25, 0, 24, 1, 0) | ||
73 | |||
74 | MUX_CFG_850("AA17_850_USB_DM", 2, 21, 0, 20, 0, 0) | ||
75 | MUX_CFG_850("W16_850_USB_PU_EN", 2, 25, 0, 24, 0, 0) | ||
76 | MUX_CFG_850("W17_850_USB_VBUSI", 2, 29, 0, 28, 0, 0) | ||
77 | }; | ||
78 | #endif | ||
79 | 60 | ||
80 | #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) | 61 | #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) |
81 | static struct pin_config __initdata_or_module omap1xxx_pins[] = { | 62 | static struct pin_config __initdata_or_module omap1xxx_pins[] = { |
@@ -438,11 +419,6 @@ int __init_or_module omap1_cfg_reg(const struct pin_config *cfg) | |||
438 | printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n", | 419 | printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n", |
439 | cfg->pull_name, cfg->pull_reg, pull_orig, pull); | 420 | cfg->pull_name, cfg->pull_reg, pull_orig, pull); |
440 | } | 421 | } |
441 | |||
442 | #ifdef CONFIG_ARCH_OMAP850 | ||
443 | omap_mux_register(omap850_pins, ARRAY_SIZE(omap850_pins)); | ||
444 | #endif | ||
445 | |||
446 | #endif | 422 | #endif |
447 | 423 | ||
448 | #ifdef CONFIG_OMAP_MUX_ERRORS | 424 | #ifdef CONFIG_OMAP_MUX_ERRORS |
@@ -454,9 +430,9 @@ int __init_or_module omap1_cfg_reg(const struct pin_config *cfg) | |||
454 | 430 | ||
455 | int __init omap1_mux_init(void) | 431 | int __init omap1_mux_init(void) |
456 | { | 432 | { |
457 | if (cpu_is_omap730()) { | 433 | if (cpu_is_omap7xx()) { |
458 | arch_mux_cfg.pins = omap730_pins; | 434 | arch_mux_cfg.pins = omap7xx_pins; |
459 | arch_mux_cfg.size = OMAP730_PINS_SZ; | 435 | arch_mux_cfg.size = OMAP7XX_PINS_SZ; |
460 | arch_mux_cfg.cfg_reg = omap1_cfg_reg; | 436 | arch_mux_cfg.cfg_reg = omap1_cfg_reg; |
461 | } | 437 | } |
462 | 438 | ||
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c index 5218943c91c0..b1d3f9fade23 100644 --- a/arch/arm/mach-omap1/pm.c +++ b/arch/arm/mach-omap1/pm.c | |||
@@ -48,21 +48,21 @@ | |||
48 | #include <asm/mach/time.h> | 48 | #include <asm/mach/time.h> |
49 | #include <asm/mach/irq.h> | 49 | #include <asm/mach/irq.h> |
50 | 50 | ||
51 | #include <mach/cpu.h> | 51 | #include <plat/cpu.h> |
52 | #include <mach/irqs.h> | 52 | #include <mach/irqs.h> |
53 | #include <mach/clock.h> | 53 | #include <plat/clock.h> |
54 | #include <mach/sram.h> | 54 | #include <plat/sram.h> |
55 | #include <mach/tc.h> | 55 | #include <plat/tc.h> |
56 | #include <mach/mux.h> | 56 | #include <plat/mux.h> |
57 | #include <mach/dma.h> | 57 | #include <plat/dma.h> |
58 | #include <mach/dmtimer.h> | 58 | #include <plat/dmtimer.h> |
59 | 59 | ||
60 | #include "pm.h" | 60 | #include "pm.h" |
61 | 61 | ||
62 | static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE]; | 62 | static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE]; |
63 | static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE]; | 63 | static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE]; |
64 | static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE]; | 64 | static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE]; |
65 | static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE]; | 65 | static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE]; |
66 | static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE]; | 66 | static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE]; |
67 | static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE]; | 67 | static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE]; |
68 | 68 | ||
@@ -183,9 +183,9 @@ static void omap_pm_wakeup_setup(void) | |||
183 | * drivers must still separately call omap_set_gpio_wakeup() to | 183 | * drivers must still separately call omap_set_gpio_wakeup() to |
184 | * wake up to a GPIO interrupt. | 184 | * wake up to a GPIO interrupt. |
185 | */ | 185 | */ |
186 | if (cpu_is_omap730()) | 186 | if (cpu_is_omap7xx()) |
187 | level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) | | 187 | level1_wake = OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1) | |
188 | OMAP_IRQ_BIT(INT_730_IH2_IRQ); | 188 | OMAP_IRQ_BIT(INT_7XX_IH2_IRQ); |
189 | else if (cpu_is_omap15xx()) | 189 | else if (cpu_is_omap15xx()) |
190 | level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) | | 190 | level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) | |
191 | OMAP_IRQ_BIT(INT_1510_IH2_IRQ); | 191 | OMAP_IRQ_BIT(INT_1510_IH2_IRQ); |
@@ -195,10 +195,10 @@ static void omap_pm_wakeup_setup(void) | |||
195 | 195 | ||
196 | omap_writel(~level1_wake, OMAP_IH1_MIR); | 196 | omap_writel(~level1_wake, OMAP_IH1_MIR); |
197 | 197 | ||
198 | if (cpu_is_omap730()) { | 198 | if (cpu_is_omap7xx()) { |
199 | omap_writel(~level2_wake, OMAP_IH2_0_MIR); | 199 | omap_writel(~level2_wake, OMAP_IH2_0_MIR); |
200 | omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) | | 200 | omap_writel(~(OMAP_IRQ_BIT(INT_7XX_WAKE_UP_REQ) | |
201 | OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)), | 201 | OMAP_IRQ_BIT(INT_7XX_MPUIO_KEYPAD)), |
202 | OMAP_IH2_1_MIR); | 202 | OMAP_IH2_1_MIR); |
203 | } else if (cpu_is_omap15xx()) { | 203 | } else if (cpu_is_omap15xx()) { |
204 | level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD); | 204 | level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD); |
@@ -253,15 +253,15 @@ void omap1_pm_suspend(void) | |||
253 | * Save interrupt, MPUI, ARM and UPLD control registers. | 253 | * Save interrupt, MPUI, ARM and UPLD control registers. |
254 | */ | 254 | */ |
255 | 255 | ||
256 | if (cpu_is_omap730()) { | 256 | if (cpu_is_omap7xx()) { |
257 | MPUI730_SAVE(OMAP_IH1_MIR); | 257 | MPUI7XX_SAVE(OMAP_IH1_MIR); |
258 | MPUI730_SAVE(OMAP_IH2_0_MIR); | 258 | MPUI7XX_SAVE(OMAP_IH2_0_MIR); |
259 | MPUI730_SAVE(OMAP_IH2_1_MIR); | 259 | MPUI7XX_SAVE(OMAP_IH2_1_MIR); |
260 | MPUI730_SAVE(MPUI_CTRL); | 260 | MPUI7XX_SAVE(MPUI_CTRL); |
261 | MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG); | 261 | MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG); |
262 | MPUI730_SAVE(MPUI_DSP_API_CONFIG); | 262 | MPUI7XX_SAVE(MPUI_DSP_API_CONFIG); |
263 | MPUI730_SAVE(EMIFS_CONFIG); | 263 | MPUI7XX_SAVE(EMIFS_CONFIG); |
264 | MPUI730_SAVE(EMIFF_SDRAM_CONFIG); | 264 | MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG); |
265 | 265 | ||
266 | } else if (cpu_is_omap15xx()) { | 266 | } else if (cpu_is_omap15xx()) { |
267 | MPUI1510_SAVE(OMAP_IH1_MIR); | 267 | MPUI1510_SAVE(OMAP_IH1_MIR); |
@@ -306,7 +306,7 @@ void omap1_pm_suspend(void) | |||
306 | omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1); | 306 | omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1); |
307 | 307 | ||
308 | /* shut down dsp_ck */ | 308 | /* shut down dsp_ck */ |
309 | if (!cpu_is_omap730()) | 309 | if (!cpu_is_omap7xx()) |
310 | omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL); | 310 | omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL); |
311 | 311 | ||
312 | /* temporarily enabling api_ck to access DSP registers */ | 312 | /* temporarily enabling api_ck to access DSP registers */ |
@@ -383,12 +383,12 @@ void omap1_pm_suspend(void) | |||
383 | ULPD_RESTORE(ULPD_CLOCK_CTRL); | 383 | ULPD_RESTORE(ULPD_CLOCK_CTRL); |
384 | ULPD_RESTORE(ULPD_STATUS_REQ); | 384 | ULPD_RESTORE(ULPD_STATUS_REQ); |
385 | 385 | ||
386 | if (cpu_is_omap730()) { | 386 | if (cpu_is_omap7xx()) { |
387 | MPUI730_RESTORE(EMIFS_CONFIG); | 387 | MPUI7XX_RESTORE(EMIFS_CONFIG); |
388 | MPUI730_RESTORE(EMIFF_SDRAM_CONFIG); | 388 | MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG); |
389 | MPUI730_RESTORE(OMAP_IH1_MIR); | 389 | MPUI7XX_RESTORE(OMAP_IH1_MIR); |
390 | MPUI730_RESTORE(OMAP_IH2_0_MIR); | 390 | MPUI7XX_RESTORE(OMAP_IH2_0_MIR); |
391 | MPUI730_RESTORE(OMAP_IH2_1_MIR); | 391 | MPUI7XX_RESTORE(OMAP_IH2_1_MIR); |
392 | } else if (cpu_is_omap15xx()) { | 392 | } else if (cpu_is_omap15xx()) { |
393 | MPUI1510_RESTORE(MPUI_CTRL); | 393 | MPUI1510_RESTORE(MPUI_CTRL); |
394 | MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG); | 394 | MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG); |
@@ -461,13 +461,13 @@ static int omap_pm_read_proc( | |||
461 | ULPD_SAVE(ULPD_DPLL_CTRL); | 461 | ULPD_SAVE(ULPD_DPLL_CTRL); |
462 | ULPD_SAVE(ULPD_POWER_CTRL); | 462 | ULPD_SAVE(ULPD_POWER_CTRL); |
463 | 463 | ||
464 | if (cpu_is_omap730()) { | 464 | if (cpu_is_omap7xx()) { |
465 | MPUI730_SAVE(MPUI_CTRL); | 465 | MPUI7XX_SAVE(MPUI_CTRL); |
466 | MPUI730_SAVE(MPUI_DSP_STATUS); | 466 | MPUI7XX_SAVE(MPUI_DSP_STATUS); |
467 | MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG); | 467 | MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG); |
468 | MPUI730_SAVE(MPUI_DSP_API_CONFIG); | 468 | MPUI7XX_SAVE(MPUI_DSP_API_CONFIG); |
469 | MPUI730_SAVE(EMIFF_SDRAM_CONFIG); | 469 | MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG); |
470 | MPUI730_SAVE(EMIFS_CONFIG); | 470 | MPUI7XX_SAVE(EMIFS_CONFIG); |
471 | } else if (cpu_is_omap15xx()) { | 471 | } else if (cpu_is_omap15xx()) { |
472 | MPUI1510_SAVE(MPUI_CTRL); | 472 | MPUI1510_SAVE(MPUI_CTRL); |
473 | MPUI1510_SAVE(MPUI_DSP_STATUS); | 473 | MPUI1510_SAVE(MPUI_DSP_STATUS); |
@@ -517,20 +517,20 @@ static int omap_pm_read_proc( | |||
517 | ULPD_SHOW(ULPD_STATUS_REQ), | 517 | ULPD_SHOW(ULPD_STATUS_REQ), |
518 | ULPD_SHOW(ULPD_POWER_CTRL)); | 518 | ULPD_SHOW(ULPD_POWER_CTRL)); |
519 | 519 | ||
520 | if (cpu_is_omap730()) { | 520 | if (cpu_is_omap7xx()) { |
521 | my_buffer_offset += sprintf(my_base + my_buffer_offset, | 521 | my_buffer_offset += sprintf(my_base + my_buffer_offset, |
522 | "MPUI730_CTRL_REG 0x%-8x \n" | 522 | "MPUI7XX_CTRL_REG 0x%-8x \n" |
523 | "MPUI730_DSP_STATUS_REG: 0x%-8x \n" | 523 | "MPUI7XX_DSP_STATUS_REG: 0x%-8x \n" |
524 | "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n" | 524 | "MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n" |
525 | "MPUI730_DSP_API_CONFIG_REG: 0x%-8x \n" | 525 | "MPUI7XX_DSP_API_CONFIG_REG: 0x%-8x \n" |
526 | "MPUI730_SDRAM_CONFIG_REG: 0x%-8x \n" | 526 | "MPUI7XX_SDRAM_CONFIG_REG: 0x%-8x \n" |
527 | "MPUI730_EMIFS_CONFIG_REG: 0x%-8x \n", | 527 | "MPUI7XX_EMIFS_CONFIG_REG: 0x%-8x \n", |
528 | MPUI730_SHOW(MPUI_CTRL), | 528 | MPUI7XX_SHOW(MPUI_CTRL), |
529 | MPUI730_SHOW(MPUI_DSP_STATUS), | 529 | MPUI7XX_SHOW(MPUI_DSP_STATUS), |
530 | MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG), | 530 | MPUI7XX_SHOW(MPUI_DSP_BOOT_CONFIG), |
531 | MPUI730_SHOW(MPUI_DSP_API_CONFIG), | 531 | MPUI7XX_SHOW(MPUI_DSP_API_CONFIG), |
532 | MPUI730_SHOW(EMIFF_SDRAM_CONFIG), | 532 | MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG), |
533 | MPUI730_SHOW(EMIFS_CONFIG)); | 533 | MPUI7XX_SHOW(EMIFS_CONFIG)); |
534 | } else if (cpu_is_omap15xx()) { | 534 | } else if (cpu_is_omap15xx()) { |
535 | my_buffer_offset += sprintf(my_base + my_buffer_offset, | 535 | my_buffer_offset += sprintf(my_base + my_buffer_offset, |
536 | "MPUI1510_CTRL_REG 0x%-8x \n" | 536 | "MPUI1510_CTRL_REG 0x%-8x \n" |
@@ -668,9 +668,9 @@ static int __init omap_pm_init(void) | |||
668 | * These routines need to be in SRAM as that's the only | 668 | * These routines need to be in SRAM as that's the only |
669 | * memory the MPU can see when it wakes up. | 669 | * memory the MPU can see when it wakes up. |
670 | */ | 670 | */ |
671 | if (cpu_is_omap730()) { | 671 | if (cpu_is_omap7xx()) { |
672 | omap_sram_suspend = omap_sram_push(omap730_cpu_suspend, | 672 | omap_sram_suspend = omap_sram_push(omap7xx_cpu_suspend, |
673 | omap730_cpu_suspend_sz); | 673 | omap7xx_cpu_suspend_sz); |
674 | } else if (cpu_is_omap15xx()) { | 674 | } else if (cpu_is_omap15xx()) { |
675 | omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend, | 675 | omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend, |
676 | omap1510_cpu_suspend_sz); | 676 | omap1510_cpu_suspend_sz); |
@@ -686,8 +686,8 @@ static int __init omap_pm_init(void) | |||
686 | 686 | ||
687 | pm_idle = omap1_pm_idle; | 687 | pm_idle = omap1_pm_idle; |
688 | 688 | ||
689 | if (cpu_is_omap730()) | 689 | if (cpu_is_omap7xx()) |
690 | setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq); | 690 | setup_irq(INT_7XX_WAKE_UP_REQ, &omap_wakeup_irq); |
691 | else if (cpu_is_omap16xx()) | 691 | else if (cpu_is_omap16xx()) |
692 | setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq); | 692 | setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq); |
693 | 693 | ||
@@ -700,8 +700,8 @@ static int __init omap_pm_init(void) | |||
700 | omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL); | 700 | omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL); |
701 | 701 | ||
702 | /* Configure IDLECT3 */ | 702 | /* Configure IDLECT3 */ |
703 | if (cpu_is_omap730()) | 703 | if (cpu_is_omap7xx()) |
704 | omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3); | 704 | omap_writel(OMAP7XX_IDLECT3_VAL, OMAP7XX_IDLECT3); |
705 | else if (cpu_is_omap16xx()) | 705 | else if (cpu_is_omap16xx()) |
706 | omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3); | 706 | omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3); |
707 | 707 | ||
diff --git a/arch/arm/mach-omap1/pm.h b/arch/arm/mach-omap1/pm.h index c4f05bdcf8a6..56a647986ae9 100644 --- a/arch/arm/mach-omap1/pm.h +++ b/arch/arm/mach-omap1/pm.h | |||
@@ -98,13 +98,14 @@ | |||
98 | #define OMAP1610_IDLECT3 0xfffece24 | 98 | #define OMAP1610_IDLECT3 0xfffece24 |
99 | #define OMAP1610_IDLE_LOOP_REQUEST 0x0400 | 99 | #define OMAP1610_IDLE_LOOP_REQUEST 0x0400 |
100 | 100 | ||
101 | #define OMAP730_IDLECT1_SLEEP_VAL 0x16c7 | 101 | #define OMAP7XX_IDLECT1_SLEEP_VAL 0x16c7 |
102 | #define OMAP730_IDLECT2_SLEEP_VAL 0x09c7 | 102 | #define OMAP7XX_IDLECT2_SLEEP_VAL 0x09c7 |
103 | #define OMAP730_IDLECT3_VAL 0x3f | 103 | #define OMAP7XX_IDLECT3_VAL 0x3f |
104 | #define OMAP730_IDLECT3 0xfffece24 | 104 | #define OMAP7XX_IDLECT3 0xfffece24 |
105 | #define OMAP730_IDLE_LOOP_REQUEST 0x0C00 | 105 | #define OMAP7XX_IDLE_LOOP_REQUEST 0x0C00 |
106 | 106 | ||
107 | #if !defined(CONFIG_ARCH_OMAP730) && \ | 107 | #if !defined(CONFIG_ARCH_OMAP730) && \ |
108 | !defined(CONFIG_ARCH_OMAP850) && \ | ||
108 | !defined(CONFIG_ARCH_OMAP15XX) && \ | 109 | !defined(CONFIG_ARCH_OMAP15XX) && \ |
109 | !defined(CONFIG_ARCH_OMAP16XX) | 110 | !defined(CONFIG_ARCH_OMAP16XX) |
110 | #warning "Power management for this processor not implemented yet" | 111 | #warning "Power management for this processor not implemented yet" |
@@ -122,17 +123,17 @@ extern void allow_idle_sleep(void); | |||
122 | extern void omap1_pm_idle(void); | 123 | extern void omap1_pm_idle(void); |
123 | extern void omap1_pm_suspend(void); | 124 | extern void omap1_pm_suspend(void); |
124 | 125 | ||
125 | extern void omap730_cpu_suspend(unsigned short, unsigned short); | 126 | extern void omap7xx_cpu_suspend(unsigned short, unsigned short); |
126 | extern void omap1510_cpu_suspend(unsigned short, unsigned short); | 127 | extern void omap1510_cpu_suspend(unsigned short, unsigned short); |
127 | extern void omap1610_cpu_suspend(unsigned short, unsigned short); | 128 | extern void omap1610_cpu_suspend(unsigned short, unsigned short); |
128 | extern void omap730_idle_loop_suspend(void); | 129 | extern void omap7xx_idle_loop_suspend(void); |
129 | extern void omap1510_idle_loop_suspend(void); | 130 | extern void omap1510_idle_loop_suspend(void); |
130 | extern void omap1610_idle_loop_suspend(void); | 131 | extern void omap1610_idle_loop_suspend(void); |
131 | 132 | ||
132 | extern unsigned int omap730_cpu_suspend_sz; | 133 | extern unsigned int omap7xx_cpu_suspend_sz; |
133 | extern unsigned int omap1510_cpu_suspend_sz; | 134 | extern unsigned int omap1510_cpu_suspend_sz; |
134 | extern unsigned int omap1610_cpu_suspend_sz; | 135 | extern unsigned int omap1610_cpu_suspend_sz; |
135 | extern unsigned int omap730_idle_loop_suspend_sz; | 136 | extern unsigned int omap7xx_idle_loop_suspend_sz; |
136 | extern unsigned int omap1510_idle_loop_suspend_sz; | 137 | extern unsigned int omap1510_idle_loop_suspend_sz; |
137 | extern unsigned int omap1610_idle_loop_suspend_sz; | 138 | extern unsigned int omap1610_idle_loop_suspend_sz; |
138 | 139 | ||
@@ -155,9 +156,9 @@ extern void omap_serial_wake_trigger(int enable); | |||
155 | #define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x)) | 156 | #define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x)) |
156 | #define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] | 157 | #define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] |
157 | 158 | ||
158 | #define MPUI730_SAVE(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] = omap_readl(x) | 159 | #define MPUI7XX_SAVE(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x] = omap_readl(x) |
159 | #define MPUI730_RESTORE(x) omap_writel((mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]), (x)) | 160 | #define MPUI7XX_RESTORE(x) omap_writel((mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x]), (x)) |
160 | #define MPUI730_SHOW(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] | 161 | #define MPUI7XX_SHOW(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x] |
161 | 162 | ||
162 | #define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x) | 163 | #define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x) |
163 | #define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x)) | 164 | #define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x)) |
@@ -232,24 +233,24 @@ enum mpui1510_save_state { | |||
232 | #endif | 233 | #endif |
233 | }; | 234 | }; |
234 | 235 | ||
235 | enum mpui730_save_state { | 236 | enum mpui7xx_save_state { |
236 | MPUI730_SLEEP_SAVE_START = 0, | 237 | MPUI7XX_SLEEP_SAVE_START = 0, |
237 | /* | 238 | /* |
238 | * MPUI registers 32 bits | 239 | * MPUI registers 32 bits |
239 | */ | 240 | */ |
240 | MPUI730_SLEEP_SAVE_MPUI_CTRL, | 241 | MPUI7XX_SLEEP_SAVE_MPUI_CTRL, |
241 | MPUI730_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG, | 242 | MPUI7XX_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG, |
242 | MPUI730_SLEEP_SAVE_MPUI_DSP_API_CONFIG, | 243 | MPUI7XX_SLEEP_SAVE_MPUI_DSP_API_CONFIG, |
243 | MPUI730_SLEEP_SAVE_MPUI_DSP_STATUS, | 244 | MPUI7XX_SLEEP_SAVE_MPUI_DSP_STATUS, |
244 | MPUI730_SLEEP_SAVE_EMIFF_SDRAM_CONFIG, | 245 | MPUI7XX_SLEEP_SAVE_EMIFF_SDRAM_CONFIG, |
245 | MPUI730_SLEEP_SAVE_EMIFS_CONFIG, | 246 | MPUI7XX_SLEEP_SAVE_EMIFS_CONFIG, |
246 | MPUI730_SLEEP_SAVE_OMAP_IH1_MIR, | 247 | MPUI7XX_SLEEP_SAVE_OMAP_IH1_MIR, |
247 | MPUI730_SLEEP_SAVE_OMAP_IH2_0_MIR, | 248 | MPUI7XX_SLEEP_SAVE_OMAP_IH2_0_MIR, |
248 | MPUI730_SLEEP_SAVE_OMAP_IH2_1_MIR, | 249 | MPUI7XX_SLEEP_SAVE_OMAP_IH2_1_MIR, |
249 | #if defined(CONFIG_ARCH_OMAP730) | 250 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
250 | MPUI730_SLEEP_SAVE_SIZE | 251 | MPUI7XX_SLEEP_SAVE_SIZE |
251 | #else | 252 | #else |
252 | MPUI730_SLEEP_SAVE_SIZE = 0 | 253 | MPUI7XX_SLEEP_SAVE_SIZE = 0 |
253 | #endif | 254 | #endif |
254 | }; | 255 | }; |
255 | 256 | ||
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c index d23979bc0fd5..5ebf0946c76a 100644 --- a/arch/arm/mach-omap1/serial.c +++ b/arch/arm/mach-omap1/serial.c | |||
@@ -22,10 +22,10 @@ | |||
22 | 22 | ||
23 | #include <asm/mach-types.h> | 23 | #include <asm/mach-types.h> |
24 | 24 | ||
25 | #include <mach/board.h> | 25 | #include <plat/board.h> |
26 | #include <mach/mux.h> | 26 | #include <plat/mux.h> |
27 | #include <mach/gpio.h> | 27 | #include <mach/gpio.h> |
28 | #include <mach/fpga.h> | 28 | #include <plat/fpga.h> |
29 | 29 | ||
30 | static struct clk * uart1_ck; | 30 | static struct clk * uart1_ck; |
31 | static struct clk * uart2_ck; | 31 | static struct clk * uart2_ck; |
@@ -64,7 +64,6 @@ static void __init omap_serial_reset(struct plat_serial8250_port *p) | |||
64 | 64 | ||
65 | static struct plat_serial8250_port serial_platform_data[] = { | 65 | static struct plat_serial8250_port serial_platform_data[] = { |
66 | { | 66 | { |
67 | .membase = OMAP1_IO_ADDRESS(OMAP_UART1_BASE), | ||
68 | .mapbase = OMAP_UART1_BASE, | 67 | .mapbase = OMAP_UART1_BASE, |
69 | .irq = INT_UART1, | 68 | .irq = INT_UART1, |
70 | .flags = UPF_BOOT_AUTOCONF, | 69 | .flags = UPF_BOOT_AUTOCONF, |
@@ -73,7 +72,6 @@ static struct plat_serial8250_port serial_platform_data[] = { | |||
73 | .uartclk = OMAP16XX_BASE_BAUD * 16, | 72 | .uartclk = OMAP16XX_BASE_BAUD * 16, |
74 | }, | 73 | }, |
75 | { | 74 | { |
76 | .membase = OMAP1_IO_ADDRESS(OMAP_UART2_BASE), | ||
77 | .mapbase = OMAP_UART2_BASE, | 75 | .mapbase = OMAP_UART2_BASE, |
78 | .irq = INT_UART2, | 76 | .irq = INT_UART2, |
79 | .flags = UPF_BOOT_AUTOCONF, | 77 | .flags = UPF_BOOT_AUTOCONF, |
@@ -82,7 +80,6 @@ static struct plat_serial8250_port serial_platform_data[] = { | |||
82 | .uartclk = OMAP16XX_BASE_BAUD * 16, | 80 | .uartclk = OMAP16XX_BASE_BAUD * 16, |
83 | }, | 81 | }, |
84 | { | 82 | { |
85 | .membase = OMAP1_IO_ADDRESS(OMAP_UART3_BASE), | ||
86 | .mapbase = OMAP_UART3_BASE, | 83 | .mapbase = OMAP_UART3_BASE, |
87 | .irq = INT_UART3, | 84 | .irq = INT_UART3, |
88 | .flags = UPF_BOOT_AUTOCONF, | 85 | .flags = UPF_BOOT_AUTOCONF, |
@@ -110,18 +107,11 @@ void __init omap_serial_init(void) | |||
110 | { | 107 | { |
111 | int i; | 108 | int i; |
112 | 109 | ||
113 | if (cpu_is_omap730()) { | 110 | if (cpu_is_omap7xx()) { |
114 | serial_platform_data[0].regshift = 0; | 111 | serial_platform_data[0].regshift = 0; |
115 | serial_platform_data[1].regshift = 0; | 112 | serial_platform_data[1].regshift = 0; |
116 | serial_platform_data[0].irq = INT_730_UART_MODEM_1; | 113 | serial_platform_data[0].irq = INT_7XX_UART_MODEM_1; |
117 | serial_platform_data[1].irq = INT_730_UART_MODEM_IRDA_2; | 114 | serial_platform_data[1].irq = INT_7XX_UART_MODEM_IRDA_2; |
118 | } | ||
119 | |||
120 | if (cpu_is_omap850()) { | ||
121 | serial_platform_data[0].regshift = 0; | ||
122 | serial_platform_data[1].regshift = 0; | ||
123 | serial_platform_data[0].irq = INT_850_UART_MODEM_1; | ||
124 | serial_platform_data[1].irq = INT_850_UART_MODEM_IRDA_2; | ||
125 | } | 115 | } |
126 | 116 | ||
127 | if (cpu_is_omap15xx()) { | 117 | if (cpu_is_omap15xx()) { |
@@ -131,6 +121,14 @@ void __init omap_serial_init(void) | |||
131 | } | 121 | } |
132 | 122 | ||
133 | for (i = 0; i < OMAP_MAX_NR_PORTS; i++) { | 123 | for (i = 0; i < OMAP_MAX_NR_PORTS; i++) { |
124 | |||
125 | /* Static mapping, never released */ | ||
126 | serial_platform_data[i].membase = | ||
127 | ioremap(serial_platform_data[i].mapbase, SZ_2K); | ||
128 | if (!serial_platform_data[i].membase) { | ||
129 | printk(KERN_ERR "Could not ioremap uart%i\n", i); | ||
130 | continue; | ||
131 | } | ||
134 | switch (i) { | 132 | switch (i) { |
135 | case 0: | 133 | case 0: |
136 | uart1_ck = clk_get(NULL, "uart1_ck"); | 134 | uart1_ck = clk_get(NULL, "uart1_ck"); |
diff --git a/arch/arm/mach-omap1/sleep.S b/arch/arm/mach-omap1/sleep.S index 22e8568339b0..ef771ce8b030 100644 --- a/arch/arm/mach-omap1/sleep.S +++ b/arch/arm/mach-omap1/sleep.S | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * linux/arch/arm/mach-omap1/sleep.S | 2 | * linux/arch/arm/mach-omap1/sleep.S |
3 | * | 3 | * |
4 | * Low-level OMAP730/1510/1610 sleep/wakeUp support | 4 | * Low-level OMAP7XX/1510/1610 sleep/wakeUp support |
5 | * | 5 | * |
6 | * Initial SA1110 code: | 6 | * Initial SA1110 code: |
7 | * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com> | 7 | * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com> |
@@ -57,8 +57,8 @@ | |||
57 | * | 57 | * |
58 | */ | 58 | */ |
59 | 59 | ||
60 | #if defined(CONFIG_ARCH_OMAP730) | 60 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
61 | ENTRY(omap730_cpu_suspend) | 61 | ENTRY(omap7xx_cpu_suspend) |
62 | 62 | ||
63 | @ save registers on stack | 63 | @ save registers on stack |
64 | stmfd sp!, {r0 - r12, lr} | 64 | stmfd sp!, {r0 - r12, lr} |
@@ -91,13 +91,13 @@ ENTRY(omap730_cpu_suspend) | |||
91 | 91 | ||
92 | @ turn off clock domains | 92 | @ turn off clock domains |
93 | @ do not disable PERCK (0x04) | 93 | @ do not disable PERCK (0x04) |
94 | mov r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff | 94 | mov r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff |
95 | orr r5, r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff00 | 95 | orr r5, r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff00 |
96 | strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] | 96 | strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] |
97 | 97 | ||
98 | @ request ARM idle | 98 | @ request ARM idle |
99 | mov r3, #OMAP730_IDLECT1_SLEEP_VAL & 0xff | 99 | mov r3, #OMAP7XX_IDLECT1_SLEEP_VAL & 0xff |
100 | orr r3, r3, #OMAP730_IDLECT1_SLEEP_VAL & 0xff00 | 100 | orr r3, r3, #OMAP7XX_IDLECT1_SLEEP_VAL & 0xff00 |
101 | strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff] | 101 | strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff] |
102 | 102 | ||
103 | @ disable instruction cache | 103 | @ disable instruction cache |
@@ -113,7 +113,7 @@ ENTRY(omap730_cpu_suspend) | |||
113 | mov r2, #0 | 113 | mov r2, #0 |
114 | mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt | 114 | mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt |
115 | /* | 115 | /* |
116 | * omap730_cpu_suspend()'s resume point. | 116 | * omap7xx_cpu_suspend()'s resume point. |
117 | * | 117 | * |
118 | * It will just start executing here, so we'll restore stuff from the | 118 | * It will just start executing here, so we'll restore stuff from the |
119 | * stack. | 119 | * stack. |
@@ -132,9 +132,9 @@ ENTRY(omap730_cpu_suspend) | |||
132 | @ restore regs and return | 132 | @ restore regs and return |
133 | ldmfd sp!, {r0 - r12, pc} | 133 | ldmfd sp!, {r0 - r12, pc} |
134 | 134 | ||
135 | ENTRY(omap730_cpu_suspend_sz) | 135 | ENTRY(omap7xx_cpu_suspend_sz) |
136 | .word . - omap730_cpu_suspend | 136 | .word . - omap7xx_cpu_suspend |
137 | #endif /* CONFIG_ARCH_OMAP730 */ | 137 | #endif /* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */ |
138 | 138 | ||
139 | #ifdef CONFIG_ARCH_OMAP15XX | 139 | #ifdef CONFIG_ARCH_OMAP15XX |
140 | ENTRY(omap1510_cpu_suspend) | 140 | ENTRY(omap1510_cpu_suspend) |
diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c index fd3f7396e162..9ad118563f7d 100644 --- a/arch/arm/mach-omap1/timer32k.c +++ b/arch/arm/mach-omap1/timer32k.c | |||
@@ -52,7 +52,7 @@ | |||
52 | #include <asm/irq.h> | 52 | #include <asm/irq.h> |
53 | #include <asm/mach/irq.h> | 53 | #include <asm/mach/irq.h> |
54 | #include <asm/mach/time.h> | 54 | #include <asm/mach/time.h> |
55 | #include <mach/dmtimer.h> | 55 | #include <plat/dmtimer.h> |
56 | 56 | ||
57 | struct sys_timer omap_timer; | 57 | struct sys_timer omap_timer; |
58 | 58 | ||
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 8cb16777661a..1d54ad349bfd 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile | |||
@@ -31,7 +31,7 @@ obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o | |||
31 | ifeq ($(CONFIG_PM),y) | 31 | ifeq ($(CONFIG_PM),y) |
32 | obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o | 32 | obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o |
33 | obj-$(CONFIG_ARCH_OMAP24XX) += sleep24xx.o | 33 | obj-$(CONFIG_ARCH_OMAP24XX) += sleep24xx.o |
34 | obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o | 34 | obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o |
35 | obj-$(CONFIG_PM_DEBUG) += pm-debug.o | 35 | obj-$(CONFIG_PM_DEBUG) += pm-debug.o |
36 | endif | 36 | endif |
37 | 37 | ||
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index 42217b32f835..db9374bc528b 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c | |||
@@ -31,12 +31,12 @@ | |||
31 | #include <asm/mach/flash.h> | 31 | #include <asm/mach/flash.h> |
32 | 32 | ||
33 | #include <mach/gpio.h> | 33 | #include <mach/gpio.h> |
34 | #include <mach/mux.h> | 34 | #include <plat/mux.h> |
35 | #include <mach/board.h> | 35 | #include <plat/board.h> |
36 | #include <mach/common.h> | 36 | #include <plat/common.h> |
37 | #include <mach/gpmc.h> | 37 | #include <plat/gpmc.h> |
38 | #include <mach/usb.h> | 38 | #include <plat/usb.h> |
39 | #include <mach/gpmc-smc91x.h> | 39 | #include <plat/gpmc-smc91x.h> |
40 | 40 | ||
41 | #include "mmc-twl4030.h" | 41 | #include "mmc-twl4030.h" |
42 | 42 | ||
@@ -221,7 +221,7 @@ static void __init omap_2430sdp_map_io(void) | |||
221 | MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board") | 221 | MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board") |
222 | /* Maintainer: Syed Khasim - Texas Instruments Inc */ | 222 | /* Maintainer: Syed Khasim - Texas Instruments Inc */ |
223 | .phys_io = 0x48000000, | 223 | .phys_io = 0x48000000, |
224 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, | 224 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, |
225 | .boot_params = 0x80000100, | 225 | .boot_params = 0x80000100, |
226 | .map_io = omap_2430sdp_map_io, | 226 | .map_io = omap_2430sdp_map_io, |
227 | .init_irq = omap_2430sdp_init_irq, | 227 | .init_irq = omap_2430sdp_init_irq, |
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 0acb5560229c..a2abac98c569 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c | |||
@@ -30,16 +30,16 @@ | |||
30 | #include <asm/mach/arch.h> | 30 | #include <asm/mach/arch.h> |
31 | #include <asm/mach/map.h> | 31 | #include <asm/mach/map.h> |
32 | 32 | ||
33 | #include <mach/mcspi.h> | 33 | #include <plat/mcspi.h> |
34 | #include <mach/mux.h> | 34 | #include <plat/mux.h> |
35 | #include <mach/board.h> | 35 | #include <plat/board.h> |
36 | #include <mach/usb.h> | 36 | #include <plat/usb.h> |
37 | #include <mach/common.h> | 37 | #include <plat/common.h> |
38 | #include <mach/dma.h> | 38 | #include <plat/dma.h> |
39 | #include <mach/gpmc.h> | 39 | #include <plat/gpmc.h> |
40 | 40 | ||
41 | #include <mach/control.h> | 41 | #include <plat/control.h> |
42 | #include <mach/gpmc-smc91x.h> | 42 | #include <plat/gpmc-smc91x.h> |
43 | 43 | ||
44 | #include "sdram-qimonda-hyb18m512160af-6.h" | 44 | #include "sdram-qimonda-hyb18m512160af-6.h" |
45 | #include "mmc-twl4030.h" | 45 | #include "mmc-twl4030.h" |
@@ -511,7 +511,7 @@ static void __init omap_3430sdp_map_io(void) | |||
511 | MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") | 511 | MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") |
512 | /* Maintainer: Syed Khasim - Texas Instruments Inc */ | 512 | /* Maintainer: Syed Khasim - Texas Instruments Inc */ |
513 | .phys_io = 0x48000000, | 513 | .phys_io = 0x48000000, |
514 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, | 514 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, |
515 | .boot_params = 0x80000100, | 515 | .boot_params = 0x80000100, |
516 | .map_io = omap_3430sdp_map_io, | 516 | .map_io = omap_3430sdp_map_io, |
517 | .init_irq = omap_3430sdp_init_irq, | 517 | .init_irq = omap_3430sdp_init_irq, |
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 609a5a4a7e29..0c6be6b4a7e2 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c | |||
@@ -23,10 +23,10 @@ | |||
23 | #include <asm/mach/arch.h> | 23 | #include <asm/mach/arch.h> |
24 | #include <asm/mach/map.h> | 24 | #include <asm/mach/map.h> |
25 | 25 | ||
26 | #include <mach/board.h> | 26 | #include <plat/board.h> |
27 | #include <mach/common.h> | 27 | #include <plat/common.h> |
28 | #include <mach/control.h> | 28 | #include <plat/control.h> |
29 | #include <mach/timer-gp.h> | 29 | #include <plat/timer-gp.h> |
30 | #include <asm/hardware/gic.h> | 30 | #include <asm/hardware/gic.h> |
31 | 31 | ||
32 | static struct platform_device sdp4430_lcd_device = { | 32 | static struct platform_device sdp4430_lcd_device = { |
@@ -52,8 +52,17 @@ static struct omap_board_config_kernel sdp4430_config[] __initdata = { | |||
52 | 52 | ||
53 | static void __init gic_init_irq(void) | 53 | static void __init gic_init_irq(void) |
54 | { | 54 | { |
55 | gic_dist_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_DIST_BASE), 29); | 55 | void __iomem *base; |
56 | gic_cpu_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)); | 56 | |
57 | /* Static mapping, never released */ | ||
58 | base = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K); | ||
59 | BUG_ON(!base); | ||
60 | gic_dist_init(0, base, 29); | ||
61 | |||
62 | /* Static mapping, never released */ | ||
63 | gic_cpu_base_addr = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512); | ||
64 | BUG_ON(!gic_cpu_base_addr); | ||
65 | gic_cpu_init(0, gic_cpu_base_addr); | ||
57 | } | 66 | } |
58 | 67 | ||
59 | static void __init omap_4430sdp_init_irq(void) | 68 | static void __init omap_4430sdp_init_irq(void) |
@@ -84,7 +93,7 @@ static void __init omap_4430sdp_map_io(void) | |||
84 | MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board") | 93 | MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board") |
85 | /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */ | 94 | /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */ |
86 | .phys_io = 0x48000000, | 95 | .phys_io = 0x48000000, |
87 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, | 96 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, |
88 | .boot_params = 0x80000100, | 97 | .boot_params = 0x80000100, |
89 | .map_io = omap_4430sdp_map_io, | 98 | .map_io = omap_4430sdp_map_io, |
90 | .init_irq = omap_4430sdp_init_irq, | 99 | .init_irq = omap_4430sdp_init_irq, |
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index a1132288c701..8a2ce77a02ec 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c | |||
@@ -33,13 +33,13 @@ | |||
33 | #include <asm/mach/flash.h> | 33 | #include <asm/mach/flash.h> |
34 | 34 | ||
35 | #include <mach/gpio.h> | 35 | #include <mach/gpio.h> |
36 | #include <mach/led.h> | 36 | #include <plat/led.h> |
37 | #include <mach/mux.h> | 37 | #include <plat/mux.h> |
38 | #include <mach/usb.h> | 38 | #include <plat/usb.h> |
39 | #include <mach/board.h> | 39 | #include <plat/board.h> |
40 | #include <mach/common.h> | 40 | #include <plat/common.h> |
41 | #include <mach/gpmc.h> | 41 | #include <plat/gpmc.h> |
42 | #include <mach/control.h> | 42 | #include <plat/control.h> |
43 | 43 | ||
44 | /* LED & Switch macros */ | 44 | /* LED & Switch macros */ |
45 | #define LED0_GPIO13 13 | 45 | #define LED0_GPIO13 13 |
@@ -333,7 +333,7 @@ static void __init omap_apollon_map_io(void) | |||
333 | MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon") | 333 | MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon") |
334 | /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */ | 334 | /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */ |
335 | .phys_io = 0x48000000, | 335 | .phys_io = 0x48000000, |
336 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, | 336 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, |
337 | .boot_params = 0x80000100, | 337 | .boot_params = 0x80000100, |
338 | .map_io = omap_apollon_map_io, | 338 | .map_io = omap_apollon_map_io, |
339 | .init_irq = omap_apollon_init_irq, | 339 | .init_irq = omap_apollon_init_irq, |
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 2e09a1c444cb..7e6e6ca88be5 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c | |||
@@ -26,10 +26,10 @@ | |||
26 | #include <asm/mach/map.h> | 26 | #include <asm/mach/map.h> |
27 | 27 | ||
28 | #include <mach/gpio.h> | 28 | #include <mach/gpio.h> |
29 | #include <mach/mux.h> | 29 | #include <plat/mux.h> |
30 | #include <mach/usb.h> | 30 | #include <plat/usb.h> |
31 | #include <mach/board.h> | 31 | #include <plat/board.h> |
32 | #include <mach/common.h> | 32 | #include <plat/common.h> |
33 | 33 | ||
34 | static struct omap_board_config_kernel generic_config[] = { | 34 | static struct omap_board_config_kernel generic_config[] = { |
35 | }; | 35 | }; |
@@ -56,7 +56,7 @@ static void __init omap_generic_map_io(void) | |||
56 | MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx") | 56 | MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx") |
57 | /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */ | 57 | /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */ |
58 | .phys_io = 0x48000000, | 58 | .phys_io = 0x48000000, |
59 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, | 59 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, |
60 | .boot_params = 0x80000100, | 60 | .boot_params = 0x80000100, |
61 | .map_io = omap_generic_map_io, | 61 | .map_io = omap_generic_map_io, |
62 | .init_irq = omap_generic_init_irq, | 62 | .init_irq = omap_generic_init_irq, |
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index eaa02d012c5c..cfb7f1257d20 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c | |||
@@ -31,16 +31,16 @@ | |||
31 | #include <asm/mach/map.h> | 31 | #include <asm/mach/map.h> |
32 | #include <asm/mach/flash.h> | 32 | #include <asm/mach/flash.h> |
33 | 33 | ||
34 | #include <mach/control.h> | 34 | #include <plat/control.h> |
35 | #include <mach/gpio.h> | 35 | #include <mach/gpio.h> |
36 | #include <mach/mux.h> | 36 | #include <plat/mux.h> |
37 | #include <mach/usb.h> | 37 | #include <plat/usb.h> |
38 | #include <mach/board.h> | 38 | #include <plat/board.h> |
39 | #include <mach/common.h> | 39 | #include <plat/common.h> |
40 | #include <mach/keypad.h> | 40 | #include <plat/keypad.h> |
41 | #include <mach/menelaus.h> | 41 | #include <plat/menelaus.h> |
42 | #include <mach/dma.h> | 42 | #include <plat/dma.h> |
43 | #include <mach/gpmc.h> | 43 | #include <plat/gpmc.h> |
44 | 44 | ||
45 | #define H4_FLASH_CS 0 | 45 | #define H4_FLASH_CS 0 |
46 | #define H4_SMC91X_CS 1 | 46 | #define H4_SMC91X_CS 1 |
@@ -376,7 +376,7 @@ static void __init omap_h4_map_io(void) | |||
376 | MACHINE_START(OMAP_H4, "OMAP2420 H4 board") | 376 | MACHINE_START(OMAP_H4, "OMAP2420 H4 board") |
377 | /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */ | 377 | /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */ |
378 | .phys_io = 0x48000000, | 378 | .phys_io = 0x48000000, |
379 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, | 379 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, |
380 | .boot_params = 0x80000100, | 380 | .boot_params = 0x80000100, |
381 | .map_io = omap_h4_map_io, | 381 | .map_io = omap_h4_map_io, |
382 | .init_irq = omap_h4_init_irq, | 382 | .init_irq = omap_h4_init_irq, |
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index d57ec2f4d0a9..c062238fe881 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c | |||
@@ -33,15 +33,15 @@ | |||
33 | #include <asm/mach/arch.h> | 33 | #include <asm/mach/arch.h> |
34 | #include <asm/mach/map.h> | 34 | #include <asm/mach/map.h> |
35 | 35 | ||
36 | #include <mach/mcspi.h> | 36 | #include <plat/mcspi.h> |
37 | #include <mach/gpio.h> | 37 | #include <mach/gpio.h> |
38 | #include <mach/board.h> | 38 | #include <plat/board.h> |
39 | #include <mach/common.h> | 39 | #include <plat/common.h> |
40 | #include <mach/gpmc.h> | 40 | #include <plat/gpmc.h> |
41 | 41 | ||
42 | #include <asm/delay.h> | 42 | #include <asm/delay.h> |
43 | #include <mach/control.h> | 43 | #include <plat/control.h> |
44 | #include <mach/usb.h> | 44 | #include <plat/usb.h> |
45 | 45 | ||
46 | #include "mmc-twl4030.h" | 46 | #include "mmc-twl4030.h" |
47 | 47 | ||
@@ -399,7 +399,7 @@ static void __init omap_ldp_map_io(void) | |||
399 | 399 | ||
400 | MACHINE_START(OMAP_LDP, "OMAP LDP board") | 400 | MACHINE_START(OMAP_LDP, "OMAP LDP board") |
401 | .phys_io = 0x48000000, | 401 | .phys_io = 0x48000000, |
402 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, | 402 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, |
403 | .boot_params = 0x80000100, | 403 | .boot_params = 0x80000100, |
404 | .map_io = omap_ldp_map_io, | 404 | .map_io = omap_ldp_map_io, |
405 | .init_irq = omap_ldp_init_irq, | 405 | .init_irq = omap_ldp_init_irq, |
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index 8341632d260b..764ab1ed576d 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c | |||
@@ -23,12 +23,12 @@ | |||
23 | #include <asm/mach/arch.h> | 23 | #include <asm/mach/arch.h> |
24 | #include <asm/mach-types.h> | 24 | #include <asm/mach-types.h> |
25 | 25 | ||
26 | #include <mach/board.h> | 26 | #include <plat/board.h> |
27 | #include <mach/common.h> | 27 | #include <plat/common.h> |
28 | #include <mach/irqs.h> | 28 | #include <mach/irqs.h> |
29 | #include <mach/mcspi.h> | 29 | #include <plat/mcspi.h> |
30 | #include <mach/onenand.h> | 30 | #include <plat/onenand.h> |
31 | #include <mach/serial.h> | 31 | #include <plat/serial.h> |
32 | 32 | ||
33 | static struct omap2_mcspi_device_config p54spi_mcspi_config = { | 33 | static struct omap2_mcspi_device_config p54spi_mcspi_config = { |
34 | .turbo_mode = 0, | 34 | .turbo_mode = 0, |
@@ -121,7 +121,7 @@ static void __init n8x0_init_machine(void) | |||
121 | 121 | ||
122 | MACHINE_START(NOKIA_N800, "Nokia N800") | 122 | MACHINE_START(NOKIA_N800, "Nokia N800") |
123 | .phys_io = 0x48000000, | 123 | .phys_io = 0x48000000, |
124 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, | 124 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, |
125 | .boot_params = 0x80000100, | 125 | .boot_params = 0x80000100, |
126 | .map_io = n8x0_map_io, | 126 | .map_io = n8x0_map_io, |
127 | .init_irq = n8x0_init_irq, | 127 | .init_irq = n8x0_init_irq, |
@@ -131,7 +131,7 @@ MACHINE_END | |||
131 | 131 | ||
132 | MACHINE_START(NOKIA_N810, "Nokia N810") | 132 | MACHINE_START(NOKIA_N810, "Nokia N810") |
133 | .phys_io = 0x48000000, | 133 | .phys_io = 0x48000000, |
134 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, | 134 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, |
135 | .boot_params = 0x80000100, | 135 | .boot_params = 0x80000100, |
136 | .map_io = n8x0_map_io, | 136 | .map_io = n8x0_map_io, |
137 | .init_irq = n8x0_init_irq, | 137 | .init_irq = n8x0_init_irq, |
@@ -141,7 +141,7 @@ MACHINE_END | |||
141 | 141 | ||
142 | MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX") | 142 | MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX") |
143 | .phys_io = 0x48000000, | 143 | .phys_io = 0x48000000, |
144 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, | 144 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, |
145 | .boot_params = 0x80000100, | 145 | .boot_params = 0x80000100, |
146 | .map_io = n8x0_map_io, | 146 | .map_io = n8x0_map_io, |
147 | .init_irq = n8x0_init_irq, | 147 | .init_irq = n8x0_init_irq, |
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 08b0816afa61..76c727ed8da5 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c | |||
@@ -37,13 +37,13 @@ | |||
37 | #include <asm/mach/map.h> | 37 | #include <asm/mach/map.h> |
38 | #include <asm/mach/flash.h> | 38 | #include <asm/mach/flash.h> |
39 | 39 | ||
40 | #include <mach/board.h> | 40 | #include <plat/board.h> |
41 | #include <mach/common.h> | 41 | #include <plat/common.h> |
42 | #include <mach/gpmc.h> | 42 | #include <plat/gpmc.h> |
43 | #include <mach/nand.h> | 43 | #include <plat/nand.h> |
44 | #include <mach/mux.h> | 44 | #include <plat/mux.h> |
45 | #include <mach/usb.h> | 45 | #include <plat/usb.h> |
46 | #include <mach/timer-gp.h> | 46 | #include <plat/timer-gp.h> |
47 | 47 | ||
48 | #include "mmc-twl4030.h" | 48 | #include "mmc-twl4030.h" |
49 | 49 | ||
@@ -429,7 +429,7 @@ static void __init omap3_beagle_map_io(void) | |||
429 | MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board") | 429 | MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board") |
430 | /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */ | 430 | /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */ |
431 | .phys_io = 0x48000000, | 431 | .phys_io = 0x48000000, |
432 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, | 432 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, |
433 | .boot_params = 0x80000100, | 433 | .boot_params = 0x80000100, |
434 | .map_io = omap3_beagle_map_io, | 434 | .map_io = omap3_beagle_map_io, |
435 | .init_irq = omap3_beagle_init_irq, | 435 | .init_irq = omap3_beagle_init_irq, |
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 4c4d7f8dbd72..522ff6288c6f 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c | |||
@@ -33,11 +33,11 @@ | |||
33 | #include <asm/mach/arch.h> | 33 | #include <asm/mach/arch.h> |
34 | #include <asm/mach/map.h> | 34 | #include <asm/mach/map.h> |
35 | 35 | ||
36 | #include <mach/board.h> | 36 | #include <plat/board.h> |
37 | #include <mach/mux.h> | 37 | #include <plat/mux.h> |
38 | #include <mach/usb.h> | 38 | #include <plat/usb.h> |
39 | #include <mach/common.h> | 39 | #include <plat/common.h> |
40 | #include <mach/mcspi.h> | 40 | #include <plat/mcspi.h> |
41 | 41 | ||
42 | #include "sdram-micron-mt46h32m32lf-6.h" | 42 | #include "sdram-micron-mt46h32m32lf-6.h" |
43 | #include "mmc-twl4030.h" | 43 | #include "mmc-twl4030.h" |
@@ -324,7 +324,7 @@ static void __init omap3_evm_map_io(void) | |||
324 | MACHINE_START(OMAP3EVM, "OMAP3 EVM") | 324 | MACHINE_START(OMAP3EVM, "OMAP3 EVM") |
325 | /* Maintainer: Syed Mohammed Khasim - Texas Instruments */ | 325 | /* Maintainer: Syed Mohammed Khasim - Texas Instruments */ |
326 | .phys_io = 0x48000000, | 326 | .phys_io = 0x48000000, |
327 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, | 327 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, |
328 | .boot_params = 0x80000100, | 328 | .boot_params = 0x80000100, |
329 | .map_io = omap3_evm_map_io, | 329 | .map_io = omap3_evm_map_io, |
330 | .init_irq = omap3_evm_init_irq, | 330 | .init_irq = omap3_evm_init_irq, |
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index 7519edb69155..7fb9023b4239 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c | |||
@@ -34,13 +34,13 @@ | |||
34 | #include <asm/mach/arch.h> | 34 | #include <asm/mach/arch.h> |
35 | #include <asm/mach/map.h> | 35 | #include <asm/mach/map.h> |
36 | 36 | ||
37 | #include <mach/board.h> | 37 | #include <plat/board.h> |
38 | #include <mach/common.h> | 38 | #include <plat/common.h> |
39 | #include <mach/gpio.h> | 39 | #include <mach/gpio.h> |
40 | #include <mach/hardware.h> | 40 | #include <mach/hardware.h> |
41 | #include <mach/mcspi.h> | 41 | #include <plat/mcspi.h> |
42 | #include <mach/usb.h> | 42 | #include <plat/usb.h> |
43 | #include <mach/mux.h> | 43 | #include <plat/mux.h> |
44 | 44 | ||
45 | #include "sdram-micron-mt46h32m32lf-6.h" | 45 | #include "sdram-micron-mt46h32m32lf-6.h" |
46 | #include "mmc-twl4030.h" | 46 | #include "mmc-twl4030.h" |
@@ -412,7 +412,7 @@ static void __init omap3pandora_map_io(void) | |||
412 | 412 | ||
413 | MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console") | 413 | MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console") |
414 | .phys_io = 0x48000000, | 414 | .phys_io = 0x48000000, |
415 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, | 415 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, |
416 | .boot_params = 0x80000100, | 416 | .boot_params = 0x80000100, |
417 | .map_io = omap3pandora_map_io, | 417 | .map_io = omap3pandora_map_io, |
418 | .init_irq = omap3pandora_init_irq, | 418 | .init_irq = omap3pandora_init_irq, |
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 9917d2fddc2f..461522c1bced 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c | |||
@@ -38,14 +38,14 @@ | |||
38 | #include <asm/mach/flash.h> | 38 | #include <asm/mach/flash.h> |
39 | #include <asm/mach/map.h> | 39 | #include <asm/mach/map.h> |
40 | 40 | ||
41 | #include <mach/board.h> | 41 | #include <plat/board.h> |
42 | #include <mach/common.h> | 42 | #include <plat/common.h> |
43 | #include <mach/gpio.h> | 43 | #include <mach/gpio.h> |
44 | #include <mach/gpmc.h> | 44 | #include <plat/gpmc.h> |
45 | #include <mach/hardware.h> | 45 | #include <mach/hardware.h> |
46 | #include <mach/nand.h> | 46 | #include <plat/nand.h> |
47 | #include <mach/mux.h> | 47 | #include <plat/mux.h> |
48 | #include <mach/usb.h> | 48 | #include <plat/usb.h> |
49 | 49 | ||
50 | #include "sdram-micron-mt46h32m32lf-6.h" | 50 | #include "sdram-micron-mt46h32m32lf-6.h" |
51 | #include "mmc-twl4030.h" | 51 | #include "mmc-twl4030.h" |
@@ -67,7 +67,7 @@ | |||
67 | #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ | 67 | #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ |
68 | defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) | 68 | defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) |
69 | 69 | ||
70 | #include <mach/mcspi.h> | 70 | #include <plat/mcspi.h> |
71 | #include <linux/spi/spi.h> | 71 | #include <linux/spi/spi.h> |
72 | #include <linux/spi/ads7846.h> | 72 | #include <linux/spi/ads7846.h> |
73 | 73 | ||
@@ -451,7 +451,7 @@ static void __init overo_map_io(void) | |||
451 | 451 | ||
452 | MACHINE_START(OVERO, "Gumstix Overo") | 452 | MACHINE_START(OVERO, "Gumstix Overo") |
453 | .phys_io = 0x48000000, | 453 | .phys_io = 0x48000000, |
454 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, | 454 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, |
455 | .boot_params = 0x80000100, | 455 | .boot_params = 0x80000100, |
456 | .map_io = overo_map_io, | 456 | .map_io = overo_map_io, |
457 | .init_irq = overo_init_irq, | 457 | .init_irq = overo_init_irq, |
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index e34d96a825e3..cf4583a5d284 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c | |||
@@ -22,14 +22,14 @@ | |||
22 | #include <linux/gpio.h> | 22 | #include <linux/gpio.h> |
23 | #include <linux/mmc/host.h> | 23 | #include <linux/mmc/host.h> |
24 | 24 | ||
25 | #include <mach/mcspi.h> | 25 | #include <plat/mcspi.h> |
26 | #include <mach/mux.h> | 26 | #include <plat/mux.h> |
27 | #include <mach/board.h> | 27 | #include <plat/board.h> |
28 | #include <mach/common.h> | 28 | #include <plat/common.h> |
29 | #include <mach/dma.h> | 29 | #include <plat/dma.h> |
30 | #include <mach/gpmc.h> | 30 | #include <plat/gpmc.h> |
31 | #include <mach/onenand.h> | 31 | #include <plat/onenand.h> |
32 | #include <mach/gpmc-smc91x.h> | 32 | #include <plat/gpmc-smc91x.h> |
33 | 33 | ||
34 | #include "mmc-twl4030.h" | 34 | #include "mmc-twl4030.h" |
35 | 35 | ||
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index 78869a9a1cc2..f1e7e5bbf985 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c | |||
@@ -22,13 +22,13 @@ | |||
22 | #include <asm/mach/arch.h> | 22 | #include <asm/mach/arch.h> |
23 | #include <asm/mach/map.h> | 23 | #include <asm/mach/map.h> |
24 | 24 | ||
25 | #include <mach/mcspi.h> | 25 | #include <plat/mcspi.h> |
26 | #include <mach/mux.h> | 26 | #include <plat/mux.h> |
27 | #include <mach/board.h> | 27 | #include <plat/board.h> |
28 | #include <mach/common.h> | 28 | #include <plat/common.h> |
29 | #include <mach/dma.h> | 29 | #include <plat/dma.h> |
30 | #include <mach/gpmc.h> | 30 | #include <plat/gpmc.h> |
31 | #include <mach/usb.h> | 31 | #include <plat/usb.h> |
32 | 32 | ||
33 | static struct omap_lcd_config rx51_lcd_config = { | 33 | static struct omap_lcd_config rx51_lcd_config = { |
34 | .ctrl_name = "internal", | 34 | .ctrl_name = "internal", |
@@ -84,7 +84,7 @@ static void __init rx51_map_io(void) | |||
84 | MACHINE_START(NOKIA_RX51, "Nokia RX-51 board") | 84 | MACHINE_START(NOKIA_RX51, "Nokia RX-51 board") |
85 | /* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */ | 85 | /* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */ |
86 | .phys_io = 0x48000000, | 86 | .phys_io = 0x48000000, |
87 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, | 87 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, |
88 | .boot_params = 0x80000100, | 88 | .boot_params = 0x80000100, |
89 | .map_io = rx51_map_io, | 89 | .map_io = rx51_map_io, |
90 | .init_irq = rx51_init_irq, | 90 | .init_irq = rx51_init_irq, |
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c index 1f13e2a1f322..91ecddc9057a 100644 --- a/arch/arm/mach-omap2/board-zoom-debugboard.c +++ b/arch/arm/mach-omap2/board-zoom-debugboard.c | |||
@@ -14,7 +14,7 @@ | |||
14 | #include <linux/smsc911x.h> | 14 | #include <linux/smsc911x.h> |
15 | #include <linux/interrupt.h> | 15 | #include <linux/interrupt.h> |
16 | 16 | ||
17 | #include <mach/gpmc.h> | 17 | #include <plat/gpmc.h> |
18 | 18 | ||
19 | #define ZOOM2_SMSC911X_CS 7 | 19 | #define ZOOM2_SMSC911X_CS 7 |
20 | #define ZOOM2_SMSC911X_GPIO 158 | 20 | #define ZOOM2_SMSC911X_GPIO 158 |
diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c index 51e0b3ba5f3a..ea01a0fa07fb 100644 --- a/arch/arm/mach-omap2/board-zoom2.c +++ b/arch/arm/mach-omap2/board-zoom2.c | |||
@@ -21,8 +21,8 @@ | |||
21 | #include <asm/mach-types.h> | 21 | #include <asm/mach-types.h> |
22 | #include <asm/mach/arch.h> | 22 | #include <asm/mach/arch.h> |
23 | 23 | ||
24 | #include <mach/common.h> | 24 | #include <plat/common.h> |
25 | #include <mach/usb.h> | 25 | #include <plat/usb.h> |
26 | 26 | ||
27 | #include "mmc-twl4030.h" | 27 | #include "mmc-twl4030.h" |
28 | #include "sdram-micron-mt46h32m32lf-6.h" | 28 | #include "sdram-micron-mt46h32m32lf-6.h" |
@@ -282,7 +282,7 @@ static void __init omap_zoom2_map_io(void) | |||
282 | 282 | ||
283 | MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") | 283 | MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") |
284 | .phys_io = 0x48000000, | 284 | .phys_io = 0x48000000, |
285 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, | 285 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, |
286 | .boot_params = 0x80000100, | 286 | .boot_params = 0x80000100, |
287 | .map_io = omap_zoom2_map_io, | 287 | .map_io = omap_zoom2_map_io, |
288 | .init_irq = omap_zoom2_init_irq, | 288 | .init_irq = omap_zoom2_init_irq, |
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index f2a92d614f0f..4716206547ac 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c | |||
@@ -24,13 +24,13 @@ | |||
24 | #include <linux/io.h> | 24 | #include <linux/io.h> |
25 | #include <linux/bitops.h> | 25 | #include <linux/bitops.h> |
26 | 26 | ||
27 | #include <mach/clock.h> | 27 | #include <plat/clock.h> |
28 | #include <mach/clockdomain.h> | 28 | #include <plat/clockdomain.h> |
29 | #include <mach/cpu.h> | 29 | #include <plat/cpu.h> |
30 | #include <mach/prcm.h> | 30 | #include <plat/prcm.h> |
31 | #include <asm/div64.h> | 31 | #include <asm/div64.h> |
32 | 32 | ||
33 | #include <mach/sdrc.h> | 33 | #include <plat/sdrc.h> |
34 | #include "sdrc.h" | 34 | #include "sdrc.h" |
35 | #include "clock.h" | 35 | #include "clock.h" |
36 | #include "prm.h" | 36 | #include "prm.h" |
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 9ae7540f8af2..43b6bedaafd6 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h | |||
@@ -16,7 +16,7 @@ | |||
16 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H | 16 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H |
17 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_H | 17 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_H |
18 | 18 | ||
19 | #include <mach/clock.h> | 19 | #include <plat/clock.h> |
20 | 20 | ||
21 | /* The maximum error between a target DPLL rate and the rounded rate in Hz */ | 21 | /* The maximum error between a target DPLL rate and the rounded rate in Hz */ |
22 | #define DEFAULT_DPLL_RATE_TOLERANCE 50000 | 22 | #define DEFAULT_DPLL_RATE_TOLERANCE 50000 |
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c index e2dbedd581e8..e70e7e000eaa 100644 --- a/arch/arm/mach-omap2/clock24xx.c +++ b/arch/arm/mach-omap2/clock24xx.c | |||
@@ -28,13 +28,13 @@ | |||
28 | #include <linux/cpufreq.h> | 28 | #include <linux/cpufreq.h> |
29 | #include <linux/bitops.h> | 29 | #include <linux/bitops.h> |
30 | 30 | ||
31 | #include <mach/clock.h> | 31 | #include <plat/clock.h> |
32 | #include <mach/sram.h> | 32 | #include <plat/sram.h> |
33 | #include <mach/prcm.h> | 33 | #include <plat/prcm.h> |
34 | #include <asm/div64.h> | 34 | #include <asm/div64.h> |
35 | #include <asm/clkdev.h> | 35 | #include <asm/clkdev.h> |
36 | 36 | ||
37 | #include <mach/sdrc.h> | 37 | #include <plat/sdrc.h> |
38 | #include "clock.h" | 38 | #include "clock.h" |
39 | #include "prm.h" | 39 | #include "prm.h" |
40 | #include "prm-regbits-24xx.h" | 40 | #include "prm-regbits-24xx.h" |
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 7c5c00df3c70..225c1a7385ee 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c | |||
@@ -27,13 +27,13 @@ | |||
27 | #include <linux/limits.h> | 27 | #include <linux/limits.h> |
28 | #include <linux/bitops.h> | 28 | #include <linux/bitops.h> |
29 | 29 | ||
30 | #include <mach/cpu.h> | 30 | #include <plat/cpu.h> |
31 | #include <mach/clock.h> | 31 | #include <plat/clock.h> |
32 | #include <mach/sram.h> | 32 | #include <plat/sram.h> |
33 | #include <asm/div64.h> | 33 | #include <asm/div64.h> |
34 | #include <asm/clkdev.h> | 34 | #include <asm/clkdev.h> |
35 | 35 | ||
36 | #include <mach/sdrc.h> | 36 | #include <plat/sdrc.h> |
37 | #include "clock.h" | 37 | #include "clock.h" |
38 | #include "prm.h" | 38 | #include "prm.h" |
39 | #include "prm-regbits-34xx.h" | 39 | #include "prm-regbits-34xx.h" |
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 9565c05bebd2..8fe1bcb23dd9 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h | |||
@@ -19,7 +19,7 @@ | |||
19 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H | 19 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H |
20 | #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H | 20 | #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H |
21 | 21 | ||
22 | #include <mach/control.h> | 22 | #include <plat/control.h> |
23 | 23 | ||
24 | #include "clock.h" | 24 | #include "clock.h" |
25 | #include "cm.h" | 25 | #include "cm.h" |
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 58aff8485df9..fcd82320a6a3 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c | |||
@@ -28,14 +28,14 @@ | |||
28 | 28 | ||
29 | #include <linux/bitops.h> | 29 | #include <linux/bitops.h> |
30 | 30 | ||
31 | #include <mach/clock.h> | 31 | #include <plat/clock.h> |
32 | 32 | ||
33 | #include "prm.h" | 33 | #include "prm.h" |
34 | #include "prm-regbits-24xx.h" | 34 | #include "prm-regbits-24xx.h" |
35 | #include "cm.h" | 35 | #include "cm.h" |
36 | 36 | ||
37 | #include <mach/powerdomain.h> | 37 | #include <plat/powerdomain.h> |
38 | #include <mach/clockdomain.h> | 38 | #include <plat/clockdomain.h> |
39 | 39 | ||
40 | /* clkdm_list contains all registered struct clockdomains */ | 40 | /* clkdm_list contains all registered struct clockdomains */ |
41 | static LIST_HEAD(clkdm_list); | 41 | static LIST_HEAD(clkdm_list); |
diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h index fe319ae4ca0a..c4ee0761d908 100644 --- a/arch/arm/mach-omap2/clockdomains.h +++ b/arch/arm/mach-omap2/clockdomains.h | |||
@@ -10,7 +10,7 @@ | |||
10 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H | 10 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H |
11 | #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H | 11 | #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H |
12 | 12 | ||
13 | #include <mach/clockdomain.h> | 13 | #include <plat/clockdomain.h> |
14 | 14 | ||
15 | /* | 15 | /* |
16 | * OMAP2/3-common clockdomains | 16 | * OMAP2/3-common clockdomains |
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h index cfd0b726ba44..a2fcfcc253cc 100644 --- a/arch/arm/mach-omap2/cm.h +++ b/arch/arm/mach-omap2/cm.h | |||
@@ -17,11 +17,11 @@ | |||
17 | #include "prcm-common.h" | 17 | #include "prcm-common.h" |
18 | 18 | ||
19 | #define OMAP2420_CM_REGADDR(module, reg) \ | 19 | #define OMAP2420_CM_REGADDR(module, reg) \ |
20 | OMAP2_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) | 20 | OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) |
21 | #define OMAP2430_CM_REGADDR(module, reg) \ | 21 | #define OMAP2430_CM_REGADDR(module, reg) \ |
22 | OMAP2_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) | 22 | OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) |
23 | #define OMAP34XX_CM_REGADDR(module, reg) \ | 23 | #define OMAP34XX_CM_REGADDR(module, reg) \ |
24 | OMAP2_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) | 24 | OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) |
25 | 25 | ||
26 | /* | 26 | /* |
27 | * Architecture-specific global CM registers | 27 | * Architecture-specific global CM registers |
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 5f3aad977842..cdd1f35636dd 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c | |||
@@ -15,11 +15,127 @@ | |||
15 | #include <linux/kernel.h> | 15 | #include <linux/kernel.h> |
16 | #include <linux/io.h> | 16 | #include <linux/io.h> |
17 | 17 | ||
18 | #include <mach/common.h> | 18 | #include <plat/common.h> |
19 | #include <mach/control.h> | 19 | #include <plat/control.h> |
20 | #include <plat/sdrc.h> | ||
21 | #include "cm-regbits-34xx.h" | ||
22 | #include "prm-regbits-34xx.h" | ||
23 | #include "cm.h" | ||
24 | #include "prm.h" | ||
25 | #include "sdrc.h" | ||
20 | 26 | ||
21 | static void __iomem *omap2_ctrl_base; | 27 | static void __iomem *omap2_ctrl_base; |
22 | 28 | ||
29 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) | ||
30 | struct omap3_scratchpad { | ||
31 | u32 boot_config_ptr; | ||
32 | u32 public_restore_ptr; | ||
33 | u32 secure_ram_restore_ptr; | ||
34 | u32 sdrc_module_semaphore; | ||
35 | u32 prcm_block_offset; | ||
36 | u32 sdrc_block_offset; | ||
37 | }; | ||
38 | |||
39 | struct omap3_scratchpad_prcm_block { | ||
40 | u32 prm_clksrc_ctrl; | ||
41 | u32 prm_clksel; | ||
42 | u32 cm_clksel_core; | ||
43 | u32 cm_clksel_wkup; | ||
44 | u32 cm_clken_pll; | ||
45 | u32 cm_autoidle_pll; | ||
46 | u32 cm_clksel1_pll; | ||
47 | u32 cm_clksel2_pll; | ||
48 | u32 cm_clksel3_pll; | ||
49 | u32 cm_clken_pll_mpu; | ||
50 | u32 cm_autoidle_pll_mpu; | ||
51 | u32 cm_clksel1_pll_mpu; | ||
52 | u32 cm_clksel2_pll_mpu; | ||
53 | u32 prcm_block_size; | ||
54 | }; | ||
55 | |||
56 | struct omap3_scratchpad_sdrc_block { | ||
57 | u16 sysconfig; | ||
58 | u16 cs_cfg; | ||
59 | u16 sharing; | ||
60 | u16 err_type; | ||
61 | u32 dll_a_ctrl; | ||
62 | u32 dll_b_ctrl; | ||
63 | u32 power; | ||
64 | u32 cs_0; | ||
65 | u32 mcfg_0; | ||
66 | u16 mr_0; | ||
67 | u16 emr_1_0; | ||
68 | u16 emr_2_0; | ||
69 | u16 emr_3_0; | ||
70 | u32 actim_ctrla_0; | ||
71 | u32 actim_ctrlb_0; | ||
72 | u32 rfr_ctrl_0; | ||
73 | u32 cs_1; | ||
74 | u32 mcfg_1; | ||
75 | u16 mr_1; | ||
76 | u16 emr_1_1; | ||
77 | u16 emr_2_1; | ||
78 | u16 emr_3_1; | ||
79 | u32 actim_ctrla_1; | ||
80 | u32 actim_ctrlb_1; | ||
81 | u32 rfr_ctrl_1; | ||
82 | u16 dcdl_1_ctrl; | ||
83 | u16 dcdl_2_ctrl; | ||
84 | u32 flags; | ||
85 | u32 block_size; | ||
86 | }; | ||
87 | |||
88 | void *omap3_secure_ram_storage; | ||
89 | |||
90 | /* | ||
91 | * This is used to store ARM registers in SDRAM before attempting | ||
92 | * an MPU OFF. The save and restore happens from the SRAM sleep code. | ||
93 | * The address is stored in scratchpad, so that it can be used | ||
94 | * during the restore path. | ||
95 | */ | ||
96 | u32 omap3_arm_context[128]; | ||
97 | |||
98 | struct omap3_control_regs { | ||
99 | u32 sysconfig; | ||
100 | u32 devconf0; | ||
101 | u32 mem_dftrw0; | ||
102 | u32 mem_dftrw1; | ||
103 | u32 msuspendmux_0; | ||
104 | u32 msuspendmux_1; | ||
105 | u32 msuspendmux_2; | ||
106 | u32 msuspendmux_3; | ||
107 | u32 msuspendmux_4; | ||
108 | u32 msuspendmux_5; | ||
109 | u32 sec_ctrl; | ||
110 | u32 devconf1; | ||
111 | u32 csirxfe; | ||
112 | u32 iva2_bootaddr; | ||
113 | u32 iva2_bootmod; | ||
114 | u32 debobs_0; | ||
115 | u32 debobs_1; | ||
116 | u32 debobs_2; | ||
117 | u32 debobs_3; | ||
118 | u32 debobs_4; | ||
119 | u32 debobs_5; | ||
120 | u32 debobs_6; | ||
121 | u32 debobs_7; | ||
122 | u32 debobs_8; | ||
123 | u32 prog_io0; | ||
124 | u32 prog_io1; | ||
125 | u32 dss_dpll_spreading; | ||
126 | u32 core_dpll_spreading; | ||
127 | u32 per_dpll_spreading; | ||
128 | u32 usbhost_dpll_spreading; | ||
129 | u32 pbias_lite; | ||
130 | u32 temp_sensor; | ||
131 | u32 sramldo4; | ||
132 | u32 sramldo5; | ||
133 | u32 csi; | ||
134 | }; | ||
135 | |||
136 | static struct omap3_control_regs control_context; | ||
137 | #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ | ||
138 | |||
23 | #define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg)) | 139 | #define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg)) |
24 | 140 | ||
25 | void __init omap2_set_globals_control(struct omap_globals *omap2_globals) | 141 | void __init omap2_set_globals_control(struct omap_globals *omap2_globals) |
@@ -62,3 +178,268 @@ void omap_ctrl_writel(u32 val, u16 offset) | |||
62 | __raw_writel(val, OMAP_CTRL_REGADDR(offset)); | 178 | __raw_writel(val, OMAP_CTRL_REGADDR(offset)); |
63 | } | 179 | } |
64 | 180 | ||
181 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) | ||
182 | /* | ||
183 | * Clears the scratchpad contents in case of cold boot- | ||
184 | * called during bootup | ||
185 | */ | ||
186 | void omap3_clear_scratchpad_contents(void) | ||
187 | { | ||
188 | u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET; | ||
189 | u32 *v_addr; | ||
190 | u32 offset = 0; | ||
191 | v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); | ||
192 | if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & | ||
193 | OMAP3430_GLOBAL_COLD_RST) { | ||
194 | for ( ; offset <= max_offset; offset += 0x4) | ||
195 | __raw_writel(0x0, (v_addr + offset)); | ||
196 | prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST, OMAP3430_GR_MOD, | ||
197 | OMAP3_PRM_RSTST_OFFSET); | ||
198 | } | ||
199 | } | ||
200 | |||
201 | /* Populate the scratchpad structure with restore structure */ | ||
202 | void omap3_save_scratchpad_contents(void) | ||
203 | { | ||
204 | void * __iomem scratchpad_address; | ||
205 | u32 arm_context_addr; | ||
206 | struct omap3_scratchpad scratchpad_contents; | ||
207 | struct omap3_scratchpad_prcm_block prcm_block_contents; | ||
208 | struct omap3_scratchpad_sdrc_block sdrc_block_contents; | ||
209 | |||
210 | /* Populate the Scratchpad contents */ | ||
211 | scratchpad_contents.boot_config_ptr = 0x0; | ||
212 | if (omap_rev() != OMAP3430_REV_ES3_0 && | ||
213 | omap_rev() != OMAP3430_REV_ES3_1) | ||
214 | scratchpad_contents.public_restore_ptr = | ||
215 | virt_to_phys(get_restore_pointer()); | ||
216 | else | ||
217 | scratchpad_contents.public_restore_ptr = | ||
218 | virt_to_phys(get_es3_restore_pointer()); | ||
219 | if (omap_type() == OMAP2_DEVICE_TYPE_GP) | ||
220 | scratchpad_contents.secure_ram_restore_ptr = 0x0; | ||
221 | else | ||
222 | scratchpad_contents.secure_ram_restore_ptr = | ||
223 | (u32) __pa(omap3_secure_ram_storage); | ||
224 | scratchpad_contents.sdrc_module_semaphore = 0x0; | ||
225 | scratchpad_contents.prcm_block_offset = 0x2C; | ||
226 | scratchpad_contents.sdrc_block_offset = 0x64; | ||
227 | |||
228 | /* Populate the PRCM block contents */ | ||
229 | prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD, | ||
230 | OMAP3_PRM_CLKSRC_CTRL_OFFSET); | ||
231 | prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD, | ||
232 | OMAP3_PRM_CLKSEL_OFFSET); | ||
233 | prcm_block_contents.cm_clksel_core = | ||
234 | cm_read_mod_reg(CORE_MOD, CM_CLKSEL); | ||
235 | prcm_block_contents.cm_clksel_wkup = | ||
236 | cm_read_mod_reg(WKUP_MOD, CM_CLKSEL); | ||
237 | prcm_block_contents.cm_clken_pll = | ||
238 | cm_read_mod_reg(PLL_MOD, CM_CLKEN); | ||
239 | prcm_block_contents.cm_autoidle_pll = | ||
240 | cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL); | ||
241 | prcm_block_contents.cm_clksel1_pll = | ||
242 | cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL); | ||
243 | prcm_block_contents.cm_clksel2_pll = | ||
244 | cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL); | ||
245 | prcm_block_contents.cm_clksel3_pll = | ||
246 | cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3); | ||
247 | prcm_block_contents.cm_clken_pll_mpu = | ||
248 | cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL); | ||
249 | prcm_block_contents.cm_autoidle_pll_mpu = | ||
250 | cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL); | ||
251 | prcm_block_contents.cm_clksel1_pll_mpu = | ||
252 | cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL); | ||
253 | prcm_block_contents.cm_clksel2_pll_mpu = | ||
254 | cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL); | ||
255 | prcm_block_contents.prcm_block_size = 0x0; | ||
256 | |||
257 | /* Populate the SDRC block contents */ | ||
258 | sdrc_block_contents.sysconfig = | ||
259 | (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF); | ||
260 | sdrc_block_contents.cs_cfg = | ||
261 | (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF); | ||
262 | sdrc_block_contents.sharing = | ||
263 | (sdrc_read_reg(SDRC_SHARING) & 0xFFFF); | ||
264 | sdrc_block_contents.err_type = | ||
265 | (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF); | ||
266 | sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL); | ||
267 | sdrc_block_contents.dll_b_ctrl = 0x0; | ||
268 | /* | ||
269 | * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should | ||
270 | * be programed to issue automatic self refresh on timeout | ||
271 | * of AUTO_CNT = 1 prior to any transition to OFF mode. | ||
272 | */ | ||
273 | if ((omap_type() != OMAP2_DEVICE_TYPE_GP) | ||
274 | && (omap_rev() >= OMAP3430_REV_ES3_0)) | ||
275 | sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) & | ||
276 | ~(SDRC_POWER_AUTOCOUNT_MASK| | ||
277 | SDRC_POWER_CLKCTRL_MASK)) | | ||
278 | (1 << SDRC_POWER_AUTOCOUNT_SHIFT) | | ||
279 | SDRC_SELF_REFRESH_ON_AUTOCOUNT; | ||
280 | else | ||
281 | sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER); | ||
282 | |||
283 | sdrc_block_contents.cs_0 = 0x0; | ||
284 | sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0); | ||
285 | sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF); | ||
286 | sdrc_block_contents.emr_1_0 = 0x0; | ||
287 | sdrc_block_contents.emr_2_0 = 0x0; | ||
288 | sdrc_block_contents.emr_3_0 = 0x0; | ||
289 | sdrc_block_contents.actim_ctrla_0 = | ||
290 | sdrc_read_reg(SDRC_ACTIM_CTRL_A_0); | ||
291 | sdrc_block_contents.actim_ctrlb_0 = | ||
292 | sdrc_read_reg(SDRC_ACTIM_CTRL_B_0); | ||
293 | sdrc_block_contents.rfr_ctrl_0 = | ||
294 | sdrc_read_reg(SDRC_RFR_CTRL_0); | ||
295 | sdrc_block_contents.cs_1 = 0x0; | ||
296 | sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1); | ||
297 | sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF; | ||
298 | sdrc_block_contents.emr_1_1 = 0x0; | ||
299 | sdrc_block_contents.emr_2_1 = 0x0; | ||
300 | sdrc_block_contents.emr_3_1 = 0x0; | ||
301 | sdrc_block_contents.actim_ctrla_1 = | ||
302 | sdrc_read_reg(SDRC_ACTIM_CTRL_A_1); | ||
303 | sdrc_block_contents.actim_ctrlb_1 = | ||
304 | sdrc_read_reg(SDRC_ACTIM_CTRL_B_1); | ||
305 | sdrc_block_contents.rfr_ctrl_1 = | ||
306 | sdrc_read_reg(SDRC_RFR_CTRL_1); | ||
307 | sdrc_block_contents.dcdl_1_ctrl = 0x0; | ||
308 | sdrc_block_contents.dcdl_2_ctrl = 0x0; | ||
309 | sdrc_block_contents.flags = 0x0; | ||
310 | sdrc_block_contents.block_size = 0x0; | ||
311 | |||
312 | arm_context_addr = virt_to_phys(omap3_arm_context); | ||
313 | |||
314 | /* Copy all the contents to the scratchpad location */ | ||
315 | scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); | ||
316 | memcpy_toio(scratchpad_address, &scratchpad_contents, | ||
317 | sizeof(scratchpad_contents)); | ||
318 | /* Scratchpad contents being 32 bits, a divide by 4 done here */ | ||
319 | memcpy_toio(scratchpad_address + | ||
320 | scratchpad_contents.prcm_block_offset, | ||
321 | &prcm_block_contents, sizeof(prcm_block_contents)); | ||
322 | memcpy_toio(scratchpad_address + | ||
323 | scratchpad_contents.sdrc_block_offset, | ||
324 | &sdrc_block_contents, sizeof(sdrc_block_contents)); | ||
325 | /* | ||
326 | * Copies the address of the location in SDRAM where ARM | ||
327 | * registers get saved during a MPU OFF transition. | ||
328 | */ | ||
329 | memcpy_toio(scratchpad_address + | ||
330 | scratchpad_contents.sdrc_block_offset + | ||
331 | sizeof(sdrc_block_contents), &arm_context_addr, 4); | ||
332 | } | ||
333 | |||
334 | void omap3_control_save_context(void) | ||
335 | { | ||
336 | control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG); | ||
337 | control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | ||
338 | control_context.mem_dftrw0 = | ||
339 | omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0); | ||
340 | control_context.mem_dftrw1 = | ||
341 | omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1); | ||
342 | control_context.msuspendmux_0 = | ||
343 | omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0); | ||
344 | control_context.msuspendmux_1 = | ||
345 | omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1); | ||
346 | control_context.msuspendmux_2 = | ||
347 | omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2); | ||
348 | control_context.msuspendmux_3 = | ||
349 | omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3); | ||
350 | control_context.msuspendmux_4 = | ||
351 | omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4); | ||
352 | control_context.msuspendmux_5 = | ||
353 | omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5); | ||
354 | control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL); | ||
355 | control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1); | ||
356 | control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE); | ||
357 | control_context.iva2_bootaddr = | ||
358 | omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR); | ||
359 | control_context.iva2_bootmod = | ||
360 | omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD); | ||
361 | control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0)); | ||
362 | control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1)); | ||
363 | control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2)); | ||
364 | control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3)); | ||
365 | control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4)); | ||
366 | control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5)); | ||
367 | control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6)); | ||
368 | control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7)); | ||
369 | control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8)); | ||
370 | control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0); | ||
371 | control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1); | ||
372 | control_context.dss_dpll_spreading = | ||
373 | omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING); | ||
374 | control_context.core_dpll_spreading = | ||
375 | omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING); | ||
376 | control_context.per_dpll_spreading = | ||
377 | omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING); | ||
378 | control_context.usbhost_dpll_spreading = | ||
379 | omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); | ||
380 | control_context.pbias_lite = | ||
381 | omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE); | ||
382 | control_context.temp_sensor = | ||
383 | omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR); | ||
384 | control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4); | ||
385 | control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5); | ||
386 | control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI); | ||
387 | return; | ||
388 | } | ||
389 | |||
390 | void omap3_control_restore_context(void) | ||
391 | { | ||
392 | omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG); | ||
393 | omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0); | ||
394 | omap_ctrl_writel(control_context.mem_dftrw0, | ||
395 | OMAP343X_CONTROL_MEM_DFTRW0); | ||
396 | omap_ctrl_writel(control_context.mem_dftrw1, | ||
397 | OMAP343X_CONTROL_MEM_DFTRW1); | ||
398 | omap_ctrl_writel(control_context.msuspendmux_0, | ||
399 | OMAP2_CONTROL_MSUSPENDMUX_0); | ||
400 | omap_ctrl_writel(control_context.msuspendmux_1, | ||
401 | OMAP2_CONTROL_MSUSPENDMUX_1); | ||
402 | omap_ctrl_writel(control_context.msuspendmux_2, | ||
403 | OMAP2_CONTROL_MSUSPENDMUX_2); | ||
404 | omap_ctrl_writel(control_context.msuspendmux_3, | ||
405 | OMAP2_CONTROL_MSUSPENDMUX_3); | ||
406 | omap_ctrl_writel(control_context.msuspendmux_4, | ||
407 | OMAP2_CONTROL_MSUSPENDMUX_4); | ||
408 | omap_ctrl_writel(control_context.msuspendmux_5, | ||
409 | OMAP2_CONTROL_MSUSPENDMUX_5); | ||
410 | omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL); | ||
411 | omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1); | ||
412 | omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE); | ||
413 | omap_ctrl_writel(control_context.iva2_bootaddr, | ||
414 | OMAP343X_CONTROL_IVA2_BOOTADDR); | ||
415 | omap_ctrl_writel(control_context.iva2_bootmod, | ||
416 | OMAP343X_CONTROL_IVA2_BOOTMOD); | ||
417 | omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0)); | ||
418 | omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1)); | ||
419 | omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2)); | ||
420 | omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3)); | ||
421 | omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4)); | ||
422 | omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5)); | ||
423 | omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6)); | ||
424 | omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7)); | ||
425 | omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8)); | ||
426 | omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0); | ||
427 | omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1); | ||
428 | omap_ctrl_writel(control_context.dss_dpll_spreading, | ||
429 | OMAP343X_CONTROL_DSS_DPLL_SPREADING); | ||
430 | omap_ctrl_writel(control_context.core_dpll_spreading, | ||
431 | OMAP343X_CONTROL_CORE_DPLL_SPREADING); | ||
432 | omap_ctrl_writel(control_context.per_dpll_spreading, | ||
433 | OMAP343X_CONTROL_PER_DPLL_SPREADING); | ||
434 | omap_ctrl_writel(control_context.usbhost_dpll_spreading, | ||
435 | OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); | ||
436 | omap_ctrl_writel(control_context.pbias_lite, | ||
437 | OMAP343X_CONTROL_PBIAS_LITE); | ||
438 | omap_ctrl_writel(control_context.temp_sensor, | ||
439 | OMAP343X_CONTROL_TEMP_SENSOR); | ||
440 | omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4); | ||
441 | omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5); | ||
442 | omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI); | ||
443 | return; | ||
444 | } | ||
445 | #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ | ||
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c new file mode 100644 index 000000000000..a26d6a08ae3f --- /dev/null +++ b/arch/arm/mach-omap2/cpuidle34xx.c | |||
@@ -0,0 +1,318 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-omap2/cpuidle34xx.c | ||
3 | * | ||
4 | * OMAP3 CPU IDLE Routines | ||
5 | * | ||
6 | * Copyright (C) 2008 Texas Instruments, Inc. | ||
7 | * Rajendra Nayak <rnayak@ti.com> | ||
8 | * | ||
9 | * Copyright (C) 2007 Texas Instruments, Inc. | ||
10 | * Karthik Dasu <karthik-dp@ti.com> | ||
11 | * | ||
12 | * Copyright (C) 2006 Nokia Corporation | ||
13 | * Tony Lindgren <tony@atomide.com> | ||
14 | * | ||
15 | * Copyright (C) 2005 Texas Instruments, Inc. | ||
16 | * Richard Woodruff <r-woodruff2@ti.com> | ||
17 | * | ||
18 | * Based on pm.c for omap2 | ||
19 | * | ||
20 | * This program is free software; you can redistribute it and/or modify | ||
21 | * it under the terms of the GNU General Public License version 2 as | ||
22 | * published by the Free Software Foundation. | ||
23 | */ | ||
24 | |||
25 | #include <linux/sched.h> | ||
26 | #include <linux/cpuidle.h> | ||
27 | |||
28 | #include <plat/prcm.h> | ||
29 | #include <plat/irqs.h> | ||
30 | #include <plat/powerdomain.h> | ||
31 | #include <plat/clockdomain.h> | ||
32 | #include <plat/control.h> | ||
33 | #include <plat/serial.h> | ||
34 | |||
35 | #include "pm.h" | ||
36 | |||
37 | #ifdef CONFIG_CPU_IDLE | ||
38 | |||
39 | #define OMAP3_MAX_STATES 7 | ||
40 | #define OMAP3_STATE_C1 0 /* C1 - MPU WFI + Core active */ | ||
41 | #define OMAP3_STATE_C2 1 /* C2 - MPU WFI + Core inactive */ | ||
42 | #define OMAP3_STATE_C3 2 /* C3 - MPU CSWR + Core inactive */ | ||
43 | #define OMAP3_STATE_C4 3 /* C4 - MPU OFF + Core iactive */ | ||
44 | #define OMAP3_STATE_C5 4 /* C5 - MPU RET + Core RET */ | ||
45 | #define OMAP3_STATE_C6 5 /* C6 - MPU OFF + Core RET */ | ||
46 | #define OMAP3_STATE_C7 6 /* C7 - MPU OFF + Core OFF */ | ||
47 | |||
48 | struct omap3_processor_cx { | ||
49 | u8 valid; | ||
50 | u8 type; | ||
51 | u32 sleep_latency; | ||
52 | u32 wakeup_latency; | ||
53 | u32 mpu_state; | ||
54 | u32 core_state; | ||
55 | u32 threshold; | ||
56 | u32 flags; | ||
57 | }; | ||
58 | |||
59 | struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES]; | ||
60 | struct omap3_processor_cx current_cx_state; | ||
61 | struct powerdomain *mpu_pd, *core_pd; | ||
62 | |||
63 | static int omap3_idle_bm_check(void) | ||
64 | { | ||
65 | if (!omap3_can_sleep()) | ||
66 | return 1; | ||
67 | return 0; | ||
68 | } | ||
69 | |||
70 | static int _cpuidle_allow_idle(struct powerdomain *pwrdm, | ||
71 | struct clockdomain *clkdm) | ||
72 | { | ||
73 | omap2_clkdm_allow_idle(clkdm); | ||
74 | return 0; | ||
75 | } | ||
76 | |||
77 | static int _cpuidle_deny_idle(struct powerdomain *pwrdm, | ||
78 | struct clockdomain *clkdm) | ||
79 | { | ||
80 | omap2_clkdm_deny_idle(clkdm); | ||
81 | return 0; | ||
82 | } | ||
83 | |||
84 | /** | ||
85 | * omap3_enter_idle - Programs OMAP3 to enter the specified state | ||
86 | * @dev: cpuidle device | ||
87 | * @state: The target state to be programmed | ||
88 | * | ||
89 | * Called from the CPUidle framework to program the device to the | ||
90 | * specified target state selected by the governor. | ||
91 | */ | ||
92 | static int omap3_enter_idle(struct cpuidle_device *dev, | ||
93 | struct cpuidle_state *state) | ||
94 | { | ||
95 | struct omap3_processor_cx *cx = cpuidle_get_statedata(state); | ||
96 | struct timespec ts_preidle, ts_postidle, ts_idle; | ||
97 | u32 mpu_state = cx->mpu_state, core_state = cx->core_state; | ||
98 | |||
99 | current_cx_state = *cx; | ||
100 | |||
101 | /* Used to keep track of the total time in idle */ | ||
102 | getnstimeofday(&ts_preidle); | ||
103 | |||
104 | local_irq_disable(); | ||
105 | local_fiq_disable(); | ||
106 | |||
107 | if (!enable_off_mode) { | ||
108 | if (mpu_state < PWRDM_POWER_RET) | ||
109 | mpu_state = PWRDM_POWER_RET; | ||
110 | if (core_state < PWRDM_POWER_RET) | ||
111 | core_state = PWRDM_POWER_RET; | ||
112 | } | ||
113 | |||
114 | pwrdm_set_next_pwrst(mpu_pd, mpu_state); | ||
115 | pwrdm_set_next_pwrst(core_pd, core_state); | ||
116 | |||
117 | if (omap_irq_pending() || need_resched()) | ||
118 | goto return_sleep_time; | ||
119 | |||
120 | if (cx->type == OMAP3_STATE_C1) { | ||
121 | pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle); | ||
122 | pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle); | ||
123 | } | ||
124 | |||
125 | /* Execute ARM wfi */ | ||
126 | omap_sram_idle(); | ||
127 | |||
128 | if (cx->type == OMAP3_STATE_C1) { | ||
129 | pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle); | ||
130 | pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle); | ||
131 | } | ||
132 | |||
133 | return_sleep_time: | ||
134 | getnstimeofday(&ts_postidle); | ||
135 | ts_idle = timespec_sub(ts_postidle, ts_preidle); | ||
136 | |||
137 | local_irq_enable(); | ||
138 | local_fiq_enable(); | ||
139 | |||
140 | return (u32)timespec_to_ns(&ts_idle)/1000; | ||
141 | } | ||
142 | |||
143 | /** | ||
144 | * omap3_enter_idle_bm - Checks for any bus activity | ||
145 | * @dev: cpuidle device | ||
146 | * @state: The target state to be programmed | ||
147 | * | ||
148 | * Used for C states with CPUIDLE_FLAG_CHECK_BM flag set. This | ||
149 | * function checks for any pending activity and then programs the | ||
150 | * device to the specified or a safer state. | ||
151 | */ | ||
152 | static int omap3_enter_idle_bm(struct cpuidle_device *dev, | ||
153 | struct cpuidle_state *state) | ||
154 | { | ||
155 | struct cpuidle_state *new_state = state; | ||
156 | |||
157 | if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) { | ||
158 | BUG_ON(!dev->safe_state); | ||
159 | new_state = dev->safe_state; | ||
160 | } | ||
161 | |||
162 | dev->last_state = new_state; | ||
163 | return omap3_enter_idle(dev, new_state); | ||
164 | } | ||
165 | |||
166 | DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); | ||
167 | |||
168 | /* omap3_init_power_states - Initialises the OMAP3 specific C states. | ||
169 | * | ||
170 | * Below is the desciption of each C state. | ||
171 | * C1 . MPU WFI + Core active | ||
172 | * C2 . MPU WFI + Core inactive | ||
173 | * C3 . MPU CSWR + Core inactive | ||
174 | * C4 . MPU OFF + Core inactive | ||
175 | * C5 . MPU CSWR + Core CSWR | ||
176 | * C6 . MPU OFF + Core CSWR | ||
177 | * C7 . MPU OFF + Core OFF | ||
178 | */ | ||
179 | void omap_init_power_states(void) | ||
180 | { | ||
181 | /* C1 . MPU WFI + Core active */ | ||
182 | omap3_power_states[OMAP3_STATE_C1].valid = 1; | ||
183 | omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1; | ||
184 | omap3_power_states[OMAP3_STATE_C1].sleep_latency = 2; | ||
185 | omap3_power_states[OMAP3_STATE_C1].wakeup_latency = 2; | ||
186 | omap3_power_states[OMAP3_STATE_C1].threshold = 5; | ||
187 | omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON; | ||
188 | omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON; | ||
189 | omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID; | ||
190 | |||
191 | /* C2 . MPU WFI + Core inactive */ | ||
192 | omap3_power_states[OMAP3_STATE_C2].valid = 1; | ||
193 | omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2; | ||
194 | omap3_power_states[OMAP3_STATE_C2].sleep_latency = 10; | ||
195 | omap3_power_states[OMAP3_STATE_C2].wakeup_latency = 10; | ||
196 | omap3_power_states[OMAP3_STATE_C2].threshold = 30; | ||
197 | omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON; | ||
198 | omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON; | ||
199 | omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID; | ||
200 | |||
201 | /* C3 . MPU CSWR + Core inactive */ | ||
202 | omap3_power_states[OMAP3_STATE_C3].valid = 1; | ||
203 | omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3; | ||
204 | omap3_power_states[OMAP3_STATE_C3].sleep_latency = 50; | ||
205 | omap3_power_states[OMAP3_STATE_C3].wakeup_latency = 50; | ||
206 | omap3_power_states[OMAP3_STATE_C3].threshold = 300; | ||
207 | omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_RET; | ||
208 | omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON; | ||
209 | omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID | | ||
210 | CPUIDLE_FLAG_CHECK_BM; | ||
211 | |||
212 | /* C4 . MPU OFF + Core inactive */ | ||
213 | omap3_power_states[OMAP3_STATE_C4].valid = 1; | ||
214 | omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4; | ||
215 | omap3_power_states[OMAP3_STATE_C4].sleep_latency = 1500; | ||
216 | omap3_power_states[OMAP3_STATE_C4].wakeup_latency = 1800; | ||
217 | omap3_power_states[OMAP3_STATE_C4].threshold = 4000; | ||
218 | omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_OFF; | ||
219 | omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON; | ||
220 | omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID | | ||
221 | CPUIDLE_FLAG_CHECK_BM; | ||
222 | |||
223 | /* C5 . MPU CSWR + Core CSWR*/ | ||
224 | omap3_power_states[OMAP3_STATE_C5].valid = 1; | ||
225 | omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5; | ||
226 | omap3_power_states[OMAP3_STATE_C5].sleep_latency = 2500; | ||
227 | omap3_power_states[OMAP3_STATE_C5].wakeup_latency = 7500; | ||
228 | omap3_power_states[OMAP3_STATE_C5].threshold = 12000; | ||
229 | omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_RET; | ||
230 | omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET; | ||
231 | omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID | | ||
232 | CPUIDLE_FLAG_CHECK_BM; | ||
233 | |||
234 | /* C6 . MPU OFF + Core CSWR */ | ||
235 | omap3_power_states[OMAP3_STATE_C6].valid = 1; | ||
236 | omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6; | ||
237 | omap3_power_states[OMAP3_STATE_C6].sleep_latency = 3000; | ||
238 | omap3_power_states[OMAP3_STATE_C6].wakeup_latency = 8500; | ||
239 | omap3_power_states[OMAP3_STATE_C6].threshold = 15000; | ||
240 | omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF; | ||
241 | omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET; | ||
242 | omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID | | ||
243 | CPUIDLE_FLAG_CHECK_BM; | ||
244 | |||
245 | /* C7 . MPU OFF + Core OFF */ | ||
246 | omap3_power_states[OMAP3_STATE_C7].valid = 1; | ||
247 | omap3_power_states[OMAP3_STATE_C7].type = OMAP3_STATE_C7; | ||
248 | omap3_power_states[OMAP3_STATE_C7].sleep_latency = 10000; | ||
249 | omap3_power_states[OMAP3_STATE_C7].wakeup_latency = 30000; | ||
250 | omap3_power_states[OMAP3_STATE_C7].threshold = 300000; | ||
251 | omap3_power_states[OMAP3_STATE_C7].mpu_state = PWRDM_POWER_OFF; | ||
252 | omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF; | ||
253 | omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID | | ||
254 | CPUIDLE_FLAG_CHECK_BM; | ||
255 | } | ||
256 | |||
257 | struct cpuidle_driver omap3_idle_driver = { | ||
258 | .name = "omap3_idle", | ||
259 | .owner = THIS_MODULE, | ||
260 | }; | ||
261 | |||
262 | /** | ||
263 | * omap3_idle_init - Init routine for OMAP3 idle | ||
264 | * | ||
265 | * Registers the OMAP3 specific cpuidle driver with the cpuidle | ||
266 | * framework with the valid set of states. | ||
267 | */ | ||
268 | int __init omap3_idle_init(void) | ||
269 | { | ||
270 | int i, count = 0; | ||
271 | struct omap3_processor_cx *cx; | ||
272 | struct cpuidle_state *state; | ||
273 | struct cpuidle_device *dev; | ||
274 | |||
275 | mpu_pd = pwrdm_lookup("mpu_pwrdm"); | ||
276 | core_pd = pwrdm_lookup("core_pwrdm"); | ||
277 | |||
278 | omap_init_power_states(); | ||
279 | cpuidle_register_driver(&omap3_idle_driver); | ||
280 | |||
281 | dev = &per_cpu(omap3_idle_dev, smp_processor_id()); | ||
282 | |||
283 | for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) { | ||
284 | cx = &omap3_power_states[i]; | ||
285 | state = &dev->states[count]; | ||
286 | |||
287 | if (!cx->valid) | ||
288 | continue; | ||
289 | cpuidle_set_statedata(state, cx); | ||
290 | state->exit_latency = cx->sleep_latency + cx->wakeup_latency; | ||
291 | state->target_residency = cx->threshold; | ||
292 | state->flags = cx->flags; | ||
293 | state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ? | ||
294 | omap3_enter_idle_bm : omap3_enter_idle; | ||
295 | if (cx->type == OMAP3_STATE_C1) | ||
296 | dev->safe_state = state; | ||
297 | sprintf(state->name, "C%d", count+1); | ||
298 | count++; | ||
299 | } | ||
300 | |||
301 | if (!count) | ||
302 | return -EINVAL; | ||
303 | dev->state_count = count; | ||
304 | |||
305 | if (cpuidle_register_device(dev)) { | ||
306 | printk(KERN_ERR "%s: CPUidle register device failed\n", | ||
307 | __func__); | ||
308 | return -EIO; | ||
309 | } | ||
310 | |||
311 | return 0; | ||
312 | } | ||
313 | #else | ||
314 | int __init omap3_idle_init(void) | ||
315 | { | ||
316 | return 0; | ||
317 | } | ||
318 | #endif /* CONFIG_CPU_IDLE */ | ||
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index faf7a1e0c525..7d4513b619f2 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c | |||
@@ -20,12 +20,12 @@ | |||
20 | #include <asm/mach-types.h> | 20 | #include <asm/mach-types.h> |
21 | #include <asm/mach/map.h> | 21 | #include <asm/mach/map.h> |
22 | 22 | ||
23 | #include <mach/control.h> | 23 | #include <plat/control.h> |
24 | #include <mach/tc.h> | 24 | #include <plat/tc.h> |
25 | #include <mach/board.h> | 25 | #include <plat/board.h> |
26 | #include <mach/mux.h> | 26 | #include <plat/mux.h> |
27 | #include <mach/gpio.h> | 27 | #include <mach/gpio.h> |
28 | #include <mach/mmc.h> | 28 | #include <plat/mmc.h> |
29 | 29 | ||
30 | #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) | 30 | #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) |
31 | 31 | ||
@@ -250,7 +250,7 @@ static inline void omap_init_sti(void) {} | |||
250 | 250 | ||
251 | #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) | 251 | #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) |
252 | 252 | ||
253 | #include <mach/mcspi.h> | 253 | #include <plat/mcspi.h> |
254 | 254 | ||
255 | #define OMAP2_MCSPI1_BASE 0x48098000 | 255 | #define OMAP2_MCSPI1_BASE 0x48098000 |
256 | #define OMAP2_MCSPI2_BASE 0x4809a000 | 256 | #define OMAP2_MCSPI2_BASE 0x4809a000 |
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c index 54fec53a48e7..7bb69220adfa 100644 --- a/arch/arm/mach-omap2/gpmc-onenand.c +++ b/arch/arm/mach-omap2/gpmc-onenand.c | |||
@@ -17,9 +17,9 @@ | |||
17 | 17 | ||
18 | #include <asm/mach/flash.h> | 18 | #include <asm/mach/flash.h> |
19 | 19 | ||
20 | #include <mach/onenand.h> | 20 | #include <plat/onenand.h> |
21 | #include <mach/board.h> | 21 | #include <plat/board.h> |
22 | #include <mach/gpmc.h> | 22 | #include <plat/gpmc.h> |
23 | 23 | ||
24 | static struct omap_onenand_platform_data *gpmc_onenand_data; | 24 | static struct omap_onenand_platform_data *gpmc_onenand_data; |
25 | 25 | ||
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c index df99d31d8b64..6083e21b3be6 100644 --- a/arch/arm/mach-omap2/gpmc-smc91x.c +++ b/arch/arm/mach-omap2/gpmc-smc91x.c | |||
@@ -17,9 +17,9 @@ | |||
17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
18 | #include <linux/smc91x.h> | 18 | #include <linux/smc91x.h> |
19 | 19 | ||
20 | #include <mach/board.h> | 20 | #include <plat/board.h> |
21 | #include <mach/gpmc.h> | 21 | #include <plat/gpmc.h> |
22 | #include <mach/gpmc-smc91x.h> | 22 | #include <plat/gpmc-smc91x.h> |
23 | 23 | ||
24 | static struct omap_smc91x_platform_data *gpmc_cfg; | 24 | static struct omap_smc91x_platform_data *gpmc_cfg; |
25 | 25 | ||
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index f3c992e29651..e86f5ca180ea 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c | |||
@@ -24,9 +24,9 @@ | |||
24 | #include <linux/module.h> | 24 | #include <linux/module.h> |
25 | 25 | ||
26 | #include <asm/mach-types.h> | 26 | #include <asm/mach-types.h> |
27 | #include <mach/gpmc.h> | 27 | #include <plat/gpmc.h> |
28 | 28 | ||
29 | #include <mach/sdrc.h> | 29 | #include <plat/sdrc.h> |
30 | 30 | ||
31 | /* GPMC register offsets */ | 31 | /* GPMC register offsets */ |
32 | #define GPMC_REVISION 0x00 | 32 | #define GPMC_REVISION 0x00 |
@@ -62,6 +62,33 @@ | |||
62 | #define ENABLE_PREFETCH (0x1 << 7) | 62 | #define ENABLE_PREFETCH (0x1 << 7) |
63 | #define DMA_MPU_MODE 2 | 63 | #define DMA_MPU_MODE 2 |
64 | 64 | ||
65 | /* Structure to save gpmc cs context */ | ||
66 | struct gpmc_cs_config { | ||
67 | u32 config1; | ||
68 | u32 config2; | ||
69 | u32 config3; | ||
70 | u32 config4; | ||
71 | u32 config5; | ||
72 | u32 config6; | ||
73 | u32 config7; | ||
74 | int is_valid; | ||
75 | }; | ||
76 | |||
77 | /* | ||
78 | * Structure to save/restore gpmc context | ||
79 | * to support core off on OMAP3 | ||
80 | */ | ||
81 | struct omap3_gpmc_regs { | ||
82 | u32 sysconfig; | ||
83 | u32 irqenable; | ||
84 | u32 timeout_ctrl; | ||
85 | u32 config; | ||
86 | u32 prefetch_config1; | ||
87 | u32 prefetch_config2; | ||
88 | u32 prefetch_control; | ||
89 | struct gpmc_cs_config cs_context[GPMC_CS_NUM]; | ||
90 | }; | ||
91 | |||
65 | static struct resource gpmc_mem_root; | 92 | static struct resource gpmc_mem_root; |
66 | static struct resource gpmc_cs_mem[GPMC_CS_NUM]; | 93 | static struct resource gpmc_cs_mem[GPMC_CS_NUM]; |
67 | static DEFINE_SPINLOCK(gpmc_mem_lock); | 94 | static DEFINE_SPINLOCK(gpmc_mem_lock); |
@@ -261,7 +288,7 @@ static void gpmc_cs_enable_mem(int cs, u32 base, u32 size) | |||
261 | l = (base >> GPMC_CHUNK_SHIFT) & 0x3f; | 288 | l = (base >> GPMC_CHUNK_SHIFT) & 0x3f; |
262 | l &= ~(0x0f << 8); | 289 | l &= ~(0x0f << 8); |
263 | l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8; | 290 | l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8; |
264 | l |= 1 << 6; /* CSVALID */ | 291 | l |= GPMC_CONFIG7_CSVALID; |
265 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); | 292 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); |
266 | } | 293 | } |
267 | 294 | ||
@@ -270,7 +297,7 @@ static void gpmc_cs_disable_mem(int cs) | |||
270 | u32 l; | 297 | u32 l; |
271 | 298 | ||
272 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | 299 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); |
273 | l &= ~(1 << 6); /* CSVALID */ | 300 | l &= ~GPMC_CONFIG7_CSVALID; |
274 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); | 301 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); |
275 | } | 302 | } |
276 | 303 | ||
@@ -290,7 +317,7 @@ static int gpmc_cs_mem_enabled(int cs) | |||
290 | u32 l; | 317 | u32 l; |
291 | 318 | ||
292 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | 319 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); |
293 | return l & (1 << 6); | 320 | return l & GPMC_CONFIG7_CSVALID; |
294 | } | 321 | } |
295 | 322 | ||
296 | int gpmc_cs_set_reserved(int cs, int reserved) | 323 | int gpmc_cs_set_reserved(int cs, int reserved) |
@@ -516,3 +543,68 @@ void __init gpmc_init(void) | |||
516 | gpmc_write_reg(GPMC_SYSCONFIG, l); | 543 | gpmc_write_reg(GPMC_SYSCONFIG, l); |
517 | gpmc_mem_init(); | 544 | gpmc_mem_init(); |
518 | } | 545 | } |
546 | |||
547 | #ifdef CONFIG_ARCH_OMAP3 | ||
548 | static struct omap3_gpmc_regs gpmc_context; | ||
549 | |||
550 | void omap3_gpmc_save_context() | ||
551 | { | ||
552 | int i; | ||
553 | gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG); | ||
554 | gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE); | ||
555 | gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL); | ||
556 | gpmc_context.config = gpmc_read_reg(GPMC_CONFIG); | ||
557 | gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); | ||
558 | gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2); | ||
559 | gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL); | ||
560 | for (i = 0; i < GPMC_CS_NUM; i++) { | ||
561 | gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i); | ||
562 | if (gpmc_context.cs_context[i].is_valid) { | ||
563 | gpmc_context.cs_context[i].config1 = | ||
564 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG1); | ||
565 | gpmc_context.cs_context[i].config2 = | ||
566 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG2); | ||
567 | gpmc_context.cs_context[i].config3 = | ||
568 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG3); | ||
569 | gpmc_context.cs_context[i].config4 = | ||
570 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG4); | ||
571 | gpmc_context.cs_context[i].config5 = | ||
572 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG5); | ||
573 | gpmc_context.cs_context[i].config6 = | ||
574 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG6); | ||
575 | gpmc_context.cs_context[i].config7 = | ||
576 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG7); | ||
577 | } | ||
578 | } | ||
579 | } | ||
580 | |||
581 | void omap3_gpmc_restore_context() | ||
582 | { | ||
583 | int i; | ||
584 | gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig); | ||
585 | gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable); | ||
586 | gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl); | ||
587 | gpmc_write_reg(GPMC_CONFIG, gpmc_context.config); | ||
588 | gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1); | ||
589 | gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2); | ||
590 | gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control); | ||
591 | for (i = 0; i < GPMC_CS_NUM; i++) { | ||
592 | if (gpmc_context.cs_context[i].is_valid) { | ||
593 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG1, | ||
594 | gpmc_context.cs_context[i].config1); | ||
595 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG2, | ||
596 | gpmc_context.cs_context[i].config2); | ||
597 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG3, | ||
598 | gpmc_context.cs_context[i].config3); | ||
599 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG4, | ||
600 | gpmc_context.cs_context[i].config4); | ||
601 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG5, | ||
602 | gpmc_context.cs_context[i].config5); | ||
603 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG6, | ||
604 | gpmc_context.cs_context[i].config6); | ||
605 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG7, | ||
606 | gpmc_context.cs_context[i].config7); | ||
607 | } | ||
608 | } | ||
609 | } | ||
610 | #endif /* CONFIG_ARCH_OMAP3 */ | ||
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index a98201cc265c..d28e6fec7e47 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c | |||
@@ -21,9 +21,9 @@ | |||
21 | 21 | ||
22 | #include <asm/cputype.h> | 22 | #include <asm/cputype.h> |
23 | 23 | ||
24 | #include <mach/common.h> | 24 | #include <plat/common.h> |
25 | #include <mach/control.h> | 25 | #include <plat/control.h> |
26 | #include <mach/cpu.h> | 26 | #include <plat/cpu.h> |
27 | 27 | ||
28 | static struct omap_chip_id omap_chip; | 28 | static struct omap_chip_id omap_chip; |
29 | static unsigned int omap_revision; | 29 | static unsigned int omap_revision; |
diff --git a/arch/arm/mach-omap2/include/mach/clkdev.h b/arch/arm/mach-omap2/include/mach/clkdev.h new file mode 100644 index 000000000000..53b027441c56 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/clkdev.h | |||
@@ -0,0 +1,5 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-omap2/include/mach/clkdev.h | ||
3 | */ | ||
4 | |||
5 | #include <plat/clkdev.h> | ||
diff --git a/arch/arm/plat-omap/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S index ac24050e3416..e9f255df9163 100644 --- a/arch/arm/plat-omap/include/mach/debug-macro.S +++ b/arch/arm/mach-omap2/include/mach/debug-macro.S | |||
@@ -1,4 +1,4 @@ | |||
1 | /* arch/arm/plat-omap/include/mach/debug-macro.S | 1 | /* arch/arm/mach-omap2/include/mach/debug-macro.S |
2 | * | 2 | * |
3 | * Debugging macro include header | 3 | * Debugging macro include header |
4 | * | 4 | * |
@@ -14,20 +14,9 @@ | |||
14 | .macro addruart,rx | 14 | .macro addruart,rx |
15 | mrc p15, 0, \rx, c1, c0 | 15 | mrc p15, 0, \rx, c1, c0 |
16 | tst \rx, #1 @ MMU enabled? | 16 | tst \rx, #1 @ MMU enabled? |
17 | #ifdef CONFIG_ARCH_OMAP1 | 17 | #ifdef CONFIG_ARCH_OMAP2 |
18 | moveq \rx, #0xff000000 @ physical base address | ||
19 | movne \rx, #0xfe000000 @ virtual base | ||
20 | orr \rx, \rx, #0x00fb0000 | ||
21 | #ifdef CONFIG_OMAP_LL_DEBUG_UART3 | ||
22 | orr \rx, \rx, #0x00009000 @ UART 3 | ||
23 | #endif | ||
24 | #if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3) | ||
25 | orr \rx, \rx, #0x00000800 @ UART 2 & 3 | ||
26 | #endif | ||
27 | |||
28 | #elif CONFIG_ARCH_OMAP2 | ||
29 | moveq \rx, #0x48000000 @ physical base address | 18 | moveq \rx, #0x48000000 @ physical base address |
30 | movne \rx, #0xd8000000 @ virtual base | 19 | movne \rx, #0xfa000000 @ virtual base |
31 | orr \rx, \rx, #0x0006a000 | 20 | orr \rx, \rx, #0x0006a000 |
32 | #ifdef CONFIG_OMAP_LL_DEBUG_UART2 | 21 | #ifdef CONFIG_OMAP_LL_DEBUG_UART2 |
33 | add \rx, \rx, #0x00002000 @ UART 2 | 22 | add \rx, \rx, #0x00002000 @ UART 2 |
@@ -38,7 +27,7 @@ | |||
38 | 27 | ||
39 | #elif defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) | 28 | #elif defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
40 | moveq \rx, #0x48000000 @ physical base address | 29 | moveq \rx, #0x48000000 @ physical base address |
41 | movne \rx, #0xd8000000 @ virtual base | 30 | movne \rx, #0xfa000000 @ virtual base |
42 | orr \rx, \rx, #0x0006a000 | 31 | orr \rx, \rx, #0x0006a000 |
43 | #ifdef CONFIG_OMAP_LL_DEBUG_UART2 | 32 | #ifdef CONFIG_OMAP_LL_DEBUG_UART2 |
44 | add \rx, \rx, #0x00002000 @ UART 2 | 33 | add \rx, \rx, #0x00002000 @ UART 2 |
diff --git a/arch/arm/plat-omap/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S index a5592991634d..c7f1720bf282 100644 --- a/arch/arm/plat-omap/include/mach/entry-macro.S +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S | |||
@@ -15,65 +15,17 @@ | |||
15 | #include <mach/irqs.h> | 15 | #include <mach/irqs.h> |
16 | #include <asm/hardware/gic.h> | 16 | #include <asm/hardware/gic.h> |
17 | 17 | ||
18 | #if defined(CONFIG_ARCH_OMAP1) | 18 | #include <plat/omap24xx.h> |
19 | 19 | #include <plat/omap34xx.h> | |
20 | #if defined(CONFIG_ARCH_OMAP730) && \ | ||
21 | (defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)) | ||
22 | #error "FIXME: OMAP730 doesn't support multiple-OMAP" | ||
23 | #elif defined(CONFIG_ARCH_OMAP730) | ||
24 | #define INT_IH2_IRQ INT_730_IH2_IRQ | ||
25 | #elif defined(CONFIG_ARCH_OMAP15XX) | ||
26 | #define INT_IH2_IRQ INT_1510_IH2_IRQ | ||
27 | #elif defined(CONFIG_ARCH_OMAP16XX) | ||
28 | #define INT_IH2_IRQ INT_1610_IH2_IRQ | ||
29 | #else | ||
30 | #warning "IH2 IRQ defaulted" | ||
31 | #define INT_IH2_IRQ INT_1510_IH2_IRQ | ||
32 | #endif | ||
33 | |||
34 | .macro disable_fiq | ||
35 | .endm | ||
36 | |||
37 | .macro get_irqnr_preamble, base, tmp | ||
38 | .endm | ||
39 | |||
40 | .macro arch_ret_to_user, tmp1, tmp2 | ||
41 | .endm | ||
42 | |||
43 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
44 | ldr \base, =OMAP1_IO_ADDRESS(OMAP_IH1_BASE) | ||
45 | ldr \irqnr, [\base, #IRQ_ITR_REG_OFFSET] | ||
46 | ldr \tmp, [\base, #IRQ_MIR_REG_OFFSET] | ||
47 | mov \irqstat, #0xffffffff | ||
48 | bic \tmp, \irqstat, \tmp | ||
49 | tst \irqnr, \tmp | ||
50 | beq 1510f | ||
51 | |||
52 | ldr \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET] | ||
53 | cmp \irqnr, #0 | ||
54 | ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET] | ||
55 | cmpeq \irqnr, #INT_IH2_IRQ | ||
56 | ldreq \base, =OMAP1_IO_ADDRESS(OMAP_IH2_BASE) | ||
57 | ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET] | ||
58 | addeqs \irqnr, \irqnr, #32 | ||
59 | 1510: | ||
60 | .endm | ||
61 | |||
62 | #endif | ||
63 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ | ||
64 | defined(CONFIG_ARCH_OMAP4) | ||
65 | |||
66 | #include <mach/omap24xx.h> | ||
67 | #include <mach/omap34xx.h> | ||
68 | 20 | ||
69 | /* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */ | 21 | /* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */ |
70 | #if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430) | 22 | #if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430) |
71 | #define OMAP2_VA_IC_BASE OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE) | 23 | #define OMAP2_VA_IC_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE) |
72 | #elif defined(CONFIG_ARCH_OMAP34XX) | 24 | #elif defined(CONFIG_ARCH_OMAP34XX) |
73 | #define OMAP2_VA_IC_BASE OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE) | 25 | #define OMAP2_VA_IC_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE) |
74 | #endif | 26 | #endif |
75 | #if defined(CONFIG_ARCH_OMAP4) | 27 | #if defined(CONFIG_ARCH_OMAP4) |
76 | #include <mach/omap44xx.h> | 28 | #include <plat/omap44xx.h> |
77 | #endif | 29 | #endif |
78 | #define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */ | 30 | #define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */ |
79 | #define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */ | 31 | #define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */ |
@@ -104,6 +56,8 @@ | |||
104 | 56 | ||
105 | .endm | 57 | .endm |
106 | #else | 58 | #else |
59 | #define OMAP44XX_VA_GIC_CPU_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE) | ||
60 | |||
107 | /* | 61 | /* |
108 | * The interrupt numbering scheme is defined in the | 62 | * The interrupt numbering scheme is defined in the |
109 | * interrupt controller spec. To wit: | 63 | * interrupt controller spec. To wit: |
@@ -168,5 +122,3 @@ | |||
168 | 122 | ||
169 | .macro irq_prio_table | 123 | .macro irq_prio_table |
170 | .endm | 124 | .endm |
171 | |||
172 | #endif | ||
diff --git a/arch/arm/mach-omap2/include/mach/gpio.h b/arch/arm/mach-omap2/include/mach/gpio.h new file mode 100644 index 000000000000..be4d290d57ee --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/gpio.h | |||
@@ -0,0 +1,5 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-omap2/include/mach/gpio.h | ||
3 | */ | ||
4 | |||
5 | #include <plat/gpio.h> | ||
diff --git a/arch/arm/mach-omap2/include/mach/hardware.h b/arch/arm/mach-omap2/include/mach/hardware.h new file mode 100644 index 000000000000..78edf9d33f71 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/hardware.h | |||
@@ -0,0 +1,5 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-omap2/include/mach/hardware.h | ||
3 | */ | ||
4 | |||
5 | #include <plat/hardware.h> | ||
diff --git a/arch/arm/mach-omap2/include/mach/io.h b/arch/arm/mach-omap2/include/mach/io.h new file mode 100644 index 000000000000..fd78f31aa1ad --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/io.h | |||
@@ -0,0 +1,5 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-omap2/include/mach/io.h | ||
3 | */ | ||
4 | |||
5 | #include <plat/io.h> | ||
diff --git a/arch/arm/mach-omap2/include/mach/irqs.h b/arch/arm/mach-omap2/include/mach/irqs.h new file mode 100644 index 000000000000..44dab7725696 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/irqs.h | |||
@@ -0,0 +1,5 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-omap2/include/mach/irqs.h | ||
3 | */ | ||
4 | |||
5 | #include <plat/irqs.h> | ||
diff --git a/arch/arm/mach-omap2/include/mach/memory.h b/arch/arm/mach-omap2/include/mach/memory.h new file mode 100644 index 000000000000..ca6d32a917dd --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/memory.h | |||
@@ -0,0 +1,5 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-omap2/include/mach/memory.h | ||
3 | */ | ||
4 | |||
5 | #include <plat/memory.h> | ||
diff --git a/arch/arm/mach-omap2/include/mach/smp.h b/arch/arm/mach-omap2/include/mach/smp.h new file mode 100644 index 000000000000..323675f21b69 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/smp.h | |||
@@ -0,0 +1,5 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-omap2/include/mach/smp.h | ||
3 | */ | ||
4 | |||
5 | #include <plat/smp.h> | ||
diff --git a/arch/arm/mach-omap2/include/mach/system.h b/arch/arm/mach-omap2/include/mach/system.h new file mode 100644 index 000000000000..d488721ab90b --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/system.h | |||
@@ -0,0 +1,5 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-omap2/include/mach/system.h | ||
3 | */ | ||
4 | |||
5 | #include <plat/system.h> | ||
diff --git a/arch/arm/mach-omap2/include/mach/timex.h b/arch/arm/mach-omap2/include/mach/timex.h new file mode 100644 index 000000000000..de9f8fc40e7c --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/timex.h | |||
@@ -0,0 +1,5 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-omap2/include/mach/timex.h | ||
3 | */ | ||
4 | |||
5 | #include <plat/timex.h> | ||
diff --git a/arch/arm/mach-omap2/include/mach/uncompress.h b/arch/arm/mach-omap2/include/mach/uncompress.h new file mode 100644 index 000000000000..78e0557bfd4e --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/uncompress.h | |||
@@ -0,0 +1,5 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-omap2/include/mach/uncompress.h | ||
3 | */ | ||
4 | |||
5 | #include <plat/uncompress.h> | ||
diff --git a/arch/arm/plat-omap/include/mach/vmalloc.h b/arch/arm/mach-omap2/include/mach/vmalloc.h index b97dfafeebda..9ce9b6e8ad23 100644 --- a/arch/arm/plat-omap/include/mach/vmalloc.h +++ b/arch/arm/mach-omap2/include/mach/vmalloc.h | |||
@@ -17,5 +17,4 @@ | |||
17 | * along with this program; if not, write to the Free Software | 17 | * along with this program; if not, write to the Free Software |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
19 | */ | 19 | */ |
20 | #define VMALLOC_END (PAGE_OFFSET + 0x18000000) | 20 | #define VMALLOC_END (PAGE_OFFSET + 0x38000000) |
21 | |||
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 56be87d13edb..59d28b2fd8c5 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c | |||
@@ -27,24 +27,24 @@ | |||
27 | 27 | ||
28 | #include <asm/mach/map.h> | 28 | #include <asm/mach/map.h> |
29 | 29 | ||
30 | #include <mach/mux.h> | 30 | #include <plat/mux.h> |
31 | #include <mach/omapfb.h> | 31 | #include <plat/omapfb.h> |
32 | #include <mach/sram.h> | 32 | #include <plat/sram.h> |
33 | #include <mach/sdrc.h> | 33 | #include <plat/sdrc.h> |
34 | #include <mach/gpmc.h> | 34 | #include <plat/gpmc.h> |
35 | #include <mach/serial.h> | 35 | #include <plat/serial.h> |
36 | 36 | ||
37 | #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdev is ready */ | 37 | #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdev is ready */ |
38 | #include "clock.h" | 38 | #include "clock.h" |
39 | 39 | ||
40 | #include <mach/omap-pm.h> | 40 | #include <plat/omap-pm.h> |
41 | #include <mach/powerdomain.h> | 41 | #include <plat/powerdomain.h> |
42 | #include "powerdomains.h" | 42 | #include "powerdomains.h" |
43 | 43 | ||
44 | #include <mach/clockdomain.h> | 44 | #include <plat/clockdomain.h> |
45 | #include "clockdomains.h" | 45 | #include "clockdomains.h" |
46 | #endif | 46 | #endif |
47 | #include <mach/omap_hwmod.h> | 47 | #include <plat/omap_hwmod.h> |
48 | #include "omap_hwmod_2420.h" | 48 | #include "omap_hwmod_2420.h" |
49 | #include "omap_hwmod_2430.h" | 49 | #include "omap_hwmod_2430.h" |
50 | #include "omap_hwmod_34xx.h" | 50 | #include "omap_hwmod_34xx.h" |
@@ -203,6 +203,24 @@ static struct map_desc omap44xx_io_desc[] __initdata = { | |||
203 | .type = MT_DEVICE, | 203 | .type = MT_DEVICE, |
204 | }, | 204 | }, |
205 | { | 205 | { |
206 | .virtual = OMAP44XX_EMIF1_VIRT, | ||
207 | .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS), | ||
208 | .length = OMAP44XX_EMIF1_SIZE, | ||
209 | .type = MT_DEVICE, | ||
210 | }, | ||
211 | { | ||
212 | .virtual = OMAP44XX_EMIF2_VIRT, | ||
213 | .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS), | ||
214 | .length = OMAP44XX_EMIF2_SIZE, | ||
215 | .type = MT_DEVICE, | ||
216 | }, | ||
217 | { | ||
218 | .virtual = OMAP44XX_DMM_VIRT, | ||
219 | .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS), | ||
220 | .length = OMAP44XX_DMM_SIZE, | ||
221 | .type = MT_DEVICE, | ||
222 | }, | ||
223 | { | ||
206 | .virtual = L4_PER_44XX_VIRT, | 224 | .virtual = L4_PER_44XX_VIRT, |
207 | .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), | 225 | .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), |
208 | .length = L4_PER_44XX_SIZE, | 226 | .length = L4_PER_44XX_SIZE, |
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c index 4a0e1cd5c1f4..6f4b7cc8f4d1 100644 --- a/arch/arm/mach-omap2/iommu2.c +++ b/arch/arm/mach-omap2/iommu2.c | |||
@@ -17,7 +17,7 @@ | |||
17 | #include <linux/module.h> | 17 | #include <linux/module.h> |
18 | #include <linux/stringify.h> | 18 | #include <linux/stringify.h> |
19 | 19 | ||
20 | #include <mach/iommu.h> | 20 | #include <plat/iommu.h> |
21 | 21 | ||
22 | /* | 22 | /* |
23 | * omap2 architecture specific register bit definitions | 23 | * omap2 architecture specific register bit definitions |
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index b82863887f10..e9bc782fa414 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c | |||
@@ -25,6 +25,10 @@ | |||
25 | #define INTC_SYSSTATUS 0x0014 | 25 | #define INTC_SYSSTATUS 0x0014 |
26 | #define INTC_SIR 0x0040 | 26 | #define INTC_SIR 0x0040 |
27 | #define INTC_CONTROL 0x0048 | 27 | #define INTC_CONTROL 0x0048 |
28 | #define INTC_PROTECTION 0x004C | ||
29 | #define INTC_IDLE 0x0050 | ||
30 | #define INTC_THRESHOLD 0x0068 | ||
31 | #define INTC_MIR0 0x0084 | ||
28 | #define INTC_MIR_CLEAR0 0x0088 | 32 | #define INTC_MIR_CLEAR0 0x0088 |
29 | #define INTC_MIR_SET0 0x008c | 33 | #define INTC_MIR_SET0 0x008c |
30 | #define INTC_PENDING_IRQ0 0x0098 | 34 | #define INTC_PENDING_IRQ0 0x0098 |
@@ -48,6 +52,18 @@ static struct omap_irq_bank { | |||
48 | }, | 52 | }, |
49 | }; | 53 | }; |
50 | 54 | ||
55 | /* Structure to save interrupt controller context */ | ||
56 | struct omap3_intc_regs { | ||
57 | u32 sysconfig; | ||
58 | u32 protection; | ||
59 | u32 idle; | ||
60 | u32 threshold; | ||
61 | u32 ilr[INTCPS_NR_IRQS]; | ||
62 | u32 mir[INTCPS_NR_MIR_REGS]; | ||
63 | }; | ||
64 | |||
65 | static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)]; | ||
66 | |||
51 | /* INTC bank register get/set */ | 67 | /* INTC bank register get/set */ |
52 | 68 | ||
53 | static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg) | 69 | static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg) |
@@ -178,12 +194,20 @@ void __init omap_init_irq(void) | |||
178 | int i; | 194 | int i; |
179 | 195 | ||
180 | for (i = 0; i < ARRAY_SIZE(irq_banks); i++) { | 196 | for (i = 0; i < ARRAY_SIZE(irq_banks); i++) { |
197 | unsigned long base; | ||
181 | struct omap_irq_bank *bank = irq_banks + i; | 198 | struct omap_irq_bank *bank = irq_banks + i; |
182 | 199 | ||
183 | if (cpu_is_omap24xx()) | 200 | if (cpu_is_omap24xx()) |
184 | bank->base_reg = OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE); | 201 | base = OMAP24XX_IC_BASE; |
185 | else if (cpu_is_omap34xx()) | 202 | else if (cpu_is_omap34xx()) |
186 | bank->base_reg = OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE); | 203 | base = OMAP34XX_IC_BASE; |
204 | |||
205 | /* Static mapping, never released */ | ||
206 | bank->base_reg = ioremap(base, SZ_4K); | ||
207 | if (!bank->base_reg) { | ||
208 | printk(KERN_ERR "Could not ioremap irq bank%i\n", i); | ||
209 | continue; | ||
210 | } | ||
187 | 211 | ||
188 | omap_irq_bank_init_one(bank); | 212 | omap_irq_bank_init_one(bank); |
189 | 213 | ||
@@ -201,3 +225,53 @@ void __init omap_init_irq(void) | |||
201 | } | 225 | } |
202 | } | 226 | } |
203 | 227 | ||
228 | #ifdef CONFIG_ARCH_OMAP3 | ||
229 | void omap_intc_save_context(void) | ||
230 | { | ||
231 | int ind = 0, i = 0; | ||
232 | for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) { | ||
233 | struct omap_irq_bank *bank = irq_banks + ind; | ||
234 | intc_context[ind].sysconfig = | ||
235 | intc_bank_read_reg(bank, INTC_SYSCONFIG); | ||
236 | intc_context[ind].protection = | ||
237 | intc_bank_read_reg(bank, INTC_PROTECTION); | ||
238 | intc_context[ind].idle = | ||
239 | intc_bank_read_reg(bank, INTC_IDLE); | ||
240 | intc_context[ind].threshold = | ||
241 | intc_bank_read_reg(bank, INTC_THRESHOLD); | ||
242 | for (i = 0; i < INTCPS_NR_IRQS; i++) | ||
243 | intc_context[ind].ilr[i] = | ||
244 | intc_bank_read_reg(bank, (0x100 + 0x4*i)); | ||
245 | for (i = 0; i < INTCPS_NR_MIR_REGS; i++) | ||
246 | intc_context[ind].mir[i] = | ||
247 | intc_bank_read_reg(&irq_banks[0], INTC_MIR0 + | ||
248 | (0x20 * i)); | ||
249 | } | ||
250 | } | ||
251 | |||
252 | void omap_intc_restore_context(void) | ||
253 | { | ||
254 | int ind = 0, i = 0; | ||
255 | |||
256 | for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) { | ||
257 | struct omap_irq_bank *bank = irq_banks + ind; | ||
258 | intc_bank_write_reg(intc_context[ind].sysconfig, | ||
259 | bank, INTC_SYSCONFIG); | ||
260 | intc_bank_write_reg(intc_context[ind].sysconfig, | ||
261 | bank, INTC_SYSCONFIG); | ||
262 | intc_bank_write_reg(intc_context[ind].protection, | ||
263 | bank, INTC_PROTECTION); | ||
264 | intc_bank_write_reg(intc_context[ind].idle, | ||
265 | bank, INTC_IDLE); | ||
266 | intc_bank_write_reg(intc_context[ind].threshold, | ||
267 | bank, INTC_THRESHOLD); | ||
268 | for (i = 0; i < INTCPS_NR_IRQS; i++) | ||
269 | intc_bank_write_reg(intc_context[ind].ilr[i], | ||
270 | bank, (0x100 + 0x4*i)); | ||
271 | for (i = 0; i < INTCPS_NR_MIR_REGS; i++) | ||
272 | intc_bank_write_reg(intc_context[ind].mir[i], | ||
273 | &irq_banks[0], INTC_MIR0 + (0x20 * i)); | ||
274 | } | ||
275 | /* MIRs are saved and restore with other PRCM registers */ | ||
276 | } | ||
277 | #endif /* CONFIG_ARCH_OMAP3 */ | ||
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index ef57b38a56a4..5ba3aa69465e 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c | |||
@@ -15,7 +15,7 @@ | |||
15 | #include <linux/err.h> | 15 | #include <linux/err.h> |
16 | #include <linux/platform_device.h> | 16 | #include <linux/platform_device.h> |
17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
18 | #include <mach/mailbox.h> | 18 | #include <plat/mailbox.h> |
19 | #include <mach/irqs.h> | 19 | #include <mach/irqs.h> |
20 | 20 | ||
21 | #define MAILBOX_REVISION 0x000 | 21 | #define MAILBOX_REVISION 0x000 |
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index a846aa1ebb4d..baa451733850 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c | |||
@@ -18,10 +18,10 @@ | |||
18 | #include <linux/platform_device.h> | 18 | #include <linux/platform_device.h> |
19 | 19 | ||
20 | #include <mach/irqs.h> | 20 | #include <mach/irqs.h> |
21 | #include <mach/dma.h> | 21 | #include <plat/dma.h> |
22 | #include <mach/mux.h> | 22 | #include <plat/mux.h> |
23 | #include <mach/cpu.h> | 23 | #include <plat/cpu.h> |
24 | #include <mach/mcbsp.h> | 24 | #include <plat/mcbsp.h> |
25 | 25 | ||
26 | static void omap2_mcbsp2_mux_setup(void) | 26 | static void omap2_mcbsp2_mux_setup(void) |
27 | { | 27 | { |
diff --git a/arch/arm/mach-omap2/mmc-twl4030.c b/arch/arm/mach-omap2/mmc-twl4030.c index c9c59a2db4e2..340391468909 100644 --- a/arch/arm/mach-omap2/mmc-twl4030.c +++ b/arch/arm/mach-omap2/mmc-twl4030.c | |||
@@ -20,9 +20,9 @@ | |||
20 | #include <linux/regulator/consumer.h> | 20 | #include <linux/regulator/consumer.h> |
21 | 21 | ||
22 | #include <mach/hardware.h> | 22 | #include <mach/hardware.h> |
23 | #include <mach/control.h> | 23 | #include <plat/control.h> |
24 | #include <mach/mmc.h> | 24 | #include <plat/mmc.h> |
25 | #include <mach/board.h> | 25 | #include <plat/board.h> |
26 | 26 | ||
27 | #include "mmc-twl4030.h" | 27 | #include "mmc-twl4030.h" |
28 | 28 | ||
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index b5fac32aae70..32c953e608db 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c | |||
@@ -30,8 +30,8 @@ | |||
30 | 30 | ||
31 | #include <asm/system.h> | 31 | #include <asm/system.h> |
32 | 32 | ||
33 | #include <mach/control.h> | 33 | #include <plat/control.h> |
34 | #include <mach/mux.h> | 34 | #include <plat/mux.h> |
35 | 35 | ||
36 | #ifdef CONFIG_OMAP_MUX | 36 | #ifdef CONFIG_OMAP_MUX |
37 | 37 | ||
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 48ee295db275..4890bcf4dadd 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c | |||
@@ -24,13 +24,14 @@ | |||
24 | #include <asm/localtimer.h> | 24 | #include <asm/localtimer.h> |
25 | #include <asm/smp_scu.h> | 25 | #include <asm/smp_scu.h> |
26 | #include <mach/hardware.h> | 26 | #include <mach/hardware.h> |
27 | #include <plat/common.h> | ||
27 | 28 | ||
28 | /* Registers used for communicating startup information */ | 29 | /* Registers used for communicating startup information */ |
29 | #define OMAP4_AUXCOREBOOT_REG0 (OMAP44XX_VA_WKUPGEN_BASE + 0x800) | 30 | static void __iomem *omap4_auxcoreboot_reg0; |
30 | #define OMAP4_AUXCOREBOOT_REG1 (OMAP44XX_VA_WKUPGEN_BASE + 0x804) | 31 | static void __iomem *omap4_auxcoreboot_reg1; |
31 | 32 | ||
32 | /* SCU base address */ | 33 | /* SCU base address */ |
33 | static void __iomem *scu_base = OMAP44XX_VA_SCU_BASE; | 34 | static void __iomem *scu_base; |
34 | 35 | ||
35 | /* | 36 | /* |
36 | * Use SCU config register to count number of cores | 37 | * Use SCU config register to count number of cores |
@@ -53,8 +54,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu) | |||
53 | * core (e.g. timer irq), then they will not have been enabled | 54 | * core (e.g. timer irq), then they will not have been enabled |
54 | * for us: do so | 55 | * for us: do so |
55 | */ | 56 | */ |
56 | 57 | gic_cpu_init(0, gic_cpu_base_addr); | |
57 | gic_cpu_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)); | ||
58 | 58 | ||
59 | /* | 59 | /* |
60 | * Synchronise with the boot thread. | 60 | * Synchronise with the boot thread. |
@@ -79,7 +79,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | |||
79 | * the AuxCoreBoot1 register is updated with cpu state | 79 | * the AuxCoreBoot1 register is updated with cpu state |
80 | * A barrier is added to ensure that write buffer is drained | 80 | * A barrier is added to ensure that write buffer is drained |
81 | */ | 81 | */ |
82 | __raw_writel(cpu, OMAP4_AUXCOREBOOT_REG1); | 82 | __raw_writel(cpu, omap4_auxcoreboot_reg1); |
83 | smp_wmb(); | 83 | smp_wmb(); |
84 | 84 | ||
85 | timeout = jiffies + (1 * HZ); | 85 | timeout = jiffies + (1 * HZ); |
@@ -104,7 +104,7 @@ static void __init wakeup_secondary(void) | |||
104 | * A barrier is added to ensure that write buffer is drained | 104 | * A barrier is added to ensure that write buffer is drained |
105 | */ | 105 | */ |
106 | __raw_writel(virt_to_phys(omap_secondary_startup), \ | 106 | __raw_writel(virt_to_phys(omap_secondary_startup), \ |
107 | OMAP4_AUXCOREBOOT_REG0); | 107 | omap4_auxcoreboot_reg0); |
108 | smp_wmb(); | 108 | smp_wmb(); |
109 | 109 | ||
110 | /* | 110 | /* |
@@ -120,7 +120,13 @@ static void __init wakeup_secondary(void) | |||
120 | */ | 120 | */ |
121 | void __init smp_init_cpus(void) | 121 | void __init smp_init_cpus(void) |
122 | { | 122 | { |
123 | unsigned int i, ncores = get_core_count(); | 123 | unsigned int i, ncores; |
124 | |||
125 | /* Never released */ | ||
126 | scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256); | ||
127 | BUG_ON(!scu_base); | ||
128 | |||
129 | ncores = get_core_count(); | ||
124 | 130 | ||
125 | for (i = 0; i < ncores; i++) | 131 | for (i = 0; i < ncores; i++) |
126 | set_cpu_possible(i, true); | 132 | set_cpu_possible(i, true); |
@@ -130,6 +136,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus) | |||
130 | { | 136 | { |
131 | unsigned int ncores = get_core_count(); | 137 | unsigned int ncores = get_core_count(); |
132 | unsigned int cpu = smp_processor_id(); | 138 | unsigned int cpu = smp_processor_id(); |
139 | void __iomem *omap4_wkupgen_base; | ||
133 | int i; | 140 | int i; |
134 | 141 | ||
135 | /* sanity check */ | 142 | /* sanity check */ |
@@ -161,6 +168,12 @@ void __init smp_prepare_cpus(unsigned int max_cpus) | |||
161 | for (i = 0; i < max_cpus; i++) | 168 | for (i = 0; i < max_cpus; i++) |
162 | set_cpu_present(i, true); | 169 | set_cpu_present(i, true); |
163 | 170 | ||
171 | /* Never released */ | ||
172 | omap4_wkupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K); | ||
173 | BUG_ON(!omap4_wkupgen_base); | ||
174 | omap4_auxcoreboot_reg0 = omap4_wkupgen_base + 0x800; | ||
175 | omap4_auxcoreboot_reg1 = omap4_wkupgen_base + 0x804; | ||
176 | |||
164 | if (max_cpus > 1) { | 177 | if (max_cpus > 1) { |
165 | /* | 178 | /* |
166 | * Enable the local timer or broadcast device for the | 179 | * Enable the local timer or broadcast device for the |
diff --git a/arch/arm/mach-omap2/omap3-iommu.c b/arch/arm/mach-omap2/omap3-iommu.c index 194189c746c2..6a9bf4f59d8a 100644 --- a/arch/arm/mach-omap2/omap3-iommu.c +++ b/arch/arm/mach-omap2/omap3-iommu.c | |||
@@ -12,7 +12,7 @@ | |||
12 | 12 | ||
13 | #include <linux/platform_device.h> | 13 | #include <linux/platform_device.h> |
14 | 14 | ||
15 | #include <mach/iommu.h> | 15 | #include <plat/iommu.h> |
16 | 16 | ||
17 | #define OMAP3_MMU1_BASE 0x480bd400 | 17 | #define OMAP3_MMU1_BASE 0x480bd400 |
18 | #define OMAP3_MMU2_BASE 0x5d000000 | 18 | #define OMAP3_MMU2_BASE 0x5d000000 |
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index d2e0f1c95961..633b216a8b26 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c | |||
@@ -45,11 +45,11 @@ | |||
45 | #include <linux/mutex.h> | 45 | #include <linux/mutex.h> |
46 | #include <linux/bootmem.h> | 46 | #include <linux/bootmem.h> |
47 | 47 | ||
48 | #include <mach/cpu.h> | 48 | #include <plat/cpu.h> |
49 | #include <mach/clockdomain.h> | 49 | #include <plat/clockdomain.h> |
50 | #include <mach/powerdomain.h> | 50 | #include <plat/powerdomain.h> |
51 | #include <mach/clock.h> | 51 | #include <plat/clock.h> |
52 | #include <mach/omap_hwmod.h> | 52 | #include <plat/omap_hwmod.h> |
53 | 53 | ||
54 | #include "cm.h" | 54 | #include "cm.h" |
55 | 55 | ||
@@ -496,6 +496,7 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index) | |||
496 | struct omap_hwmod_addr_space *mem; | 496 | struct omap_hwmod_addr_space *mem; |
497 | int i; | 497 | int i; |
498 | int found = 0; | 498 | int found = 0; |
499 | void __iomem *va_start; | ||
499 | 500 | ||
500 | if (!oh || oh->slaves_cnt == 0) | 501 | if (!oh || oh->slaves_cnt == 0) |
501 | return NULL; | 502 | return NULL; |
@@ -509,16 +510,20 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index) | |||
509 | } | 510 | } |
510 | } | 511 | } |
511 | 512 | ||
512 | /* XXX use ioremap() instead? */ | 513 | if (found) { |
513 | 514 | va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); | |
514 | if (found) | 515 | if (!va_start) { |
516 | pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); | ||
517 | return NULL; | ||
518 | } | ||
515 | pr_debug("omap_hwmod: %s: MPU register target at va %p\n", | 519 | pr_debug("omap_hwmod: %s: MPU register target at va %p\n", |
516 | oh->name, OMAP2_IO_ADDRESS(mem->pa_start)); | 520 | oh->name, va_start); |
517 | else | 521 | } else { |
518 | pr_debug("omap_hwmod: %s: no MPU register target found\n", | 522 | pr_debug("omap_hwmod: %s: no MPU register target found\n", |
519 | oh->name); | 523 | oh->name); |
524 | } | ||
520 | 525 | ||
521 | return (found) ? OMAP2_IO_ADDRESS(mem->pa_start) : NULL; | 526 | return (found) ? va_start : NULL; |
522 | } | 527 | } |
523 | 528 | ||
524 | /** | 529 | /** |
@@ -1148,6 +1153,7 @@ int omap_hwmod_unregister(struct omap_hwmod *oh) | |||
1148 | pr_debug("omap_hwmod: %s: unregistering\n", oh->name); | 1153 | pr_debug("omap_hwmod: %s: unregistering\n", oh->name); |
1149 | 1154 | ||
1150 | mutex_lock(&omap_hwmod_mutex); | 1155 | mutex_lock(&omap_hwmod_mutex); |
1156 | iounmap(oh->_rt_va); | ||
1151 | list_del(&oh->node); | 1157 | list_del(&oh->node); |
1152 | mutex_unlock(&omap_hwmod_mutex); | 1158 | mutex_unlock(&omap_hwmod_mutex); |
1153 | 1159 | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420.h b/arch/arm/mach-omap2/omap_hwmod_2420.h index 767e4965ac4e..a9ca1b99a301 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420.h +++ b/arch/arm/mach-omap2/omap_hwmod_2420.h | |||
@@ -16,10 +16,10 @@ | |||
16 | 16 | ||
17 | #ifdef CONFIG_ARCH_OMAP2420 | 17 | #ifdef CONFIG_ARCH_OMAP2420 |
18 | 18 | ||
19 | #include <mach/omap_hwmod.h> | 19 | #include <plat/omap_hwmod.h> |
20 | #include <mach/irqs.h> | 20 | #include <mach/irqs.h> |
21 | #include <mach/cpu.h> | 21 | #include <plat/cpu.h> |
22 | #include <mach/dma.h> | 22 | #include <plat/dma.h> |
23 | 23 | ||
24 | #include "prm-regbits-24xx.h" | 24 | #include "prm-regbits-24xx.h" |
25 | 25 | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430.h b/arch/arm/mach-omap2/omap_hwmod_2430.h index a412be6420ec..59a208bea6c2 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430.h +++ b/arch/arm/mach-omap2/omap_hwmod_2430.h | |||
@@ -16,10 +16,10 @@ | |||
16 | 16 | ||
17 | #ifdef CONFIG_ARCH_OMAP2430 | 17 | #ifdef CONFIG_ARCH_OMAP2430 |
18 | 18 | ||
19 | #include <mach/omap_hwmod.h> | 19 | #include <plat/omap_hwmod.h> |
20 | #include <mach/irqs.h> | 20 | #include <mach/irqs.h> |
21 | #include <mach/cpu.h> | 21 | #include <plat/cpu.h> |
22 | #include <mach/dma.h> | 22 | #include <plat/dma.h> |
23 | 23 | ||
24 | #include "prm-regbits-24xx.h" | 24 | #include "prm-regbits-24xx.h" |
25 | 25 | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_34xx.h b/arch/arm/mach-omap2/omap_hwmod_34xx.h index 1e069f831575..b6076b9c364e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_34xx.h +++ b/arch/arm/mach-omap2/omap_hwmod_34xx.h | |||
@@ -14,10 +14,10 @@ | |||
14 | 14 | ||
15 | #ifdef CONFIG_ARCH_OMAP34XX | 15 | #ifdef CONFIG_ARCH_OMAP34XX |
16 | 16 | ||
17 | #include <mach/omap_hwmod.h> | 17 | #include <plat/omap_hwmod.h> |
18 | #include <mach/irqs.h> | 18 | #include <mach/irqs.h> |
19 | #include <mach/cpu.h> | 19 | #include <plat/cpu.h> |
20 | #include <mach/dma.h> | 20 | #include <plat/dma.h> |
21 | 21 | ||
22 | #include "prm-regbits-34xx.h" | 22 | #include "prm-regbits-34xx.h" |
23 | 23 | ||
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index 2fc4d6abbd0a..8baa30d2acfb 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c | |||
@@ -26,10 +26,10 @@ | |||
26 | #include <linux/io.h> | 26 | #include <linux/io.h> |
27 | #include <linux/module.h> | 27 | #include <linux/module.h> |
28 | 28 | ||
29 | #include <mach/clock.h> | 29 | #include <plat/clock.h> |
30 | #include <mach/board.h> | 30 | #include <plat/board.h> |
31 | #include <mach/powerdomain.h> | 31 | #include <plat/powerdomain.h> |
32 | #include <mach/clockdomain.h> | 32 | #include <plat/clockdomain.h> |
33 | 33 | ||
34 | #include "prm.h" | 34 | #include "prm.h" |
35 | #include "cm.h" | 35 | #include "cm.h" |
@@ -51,7 +51,8 @@ int omap2_pm_debug; | |||
51 | regs[reg_count++].val = __raw_readl(reg) | 51 | regs[reg_count++].val = __raw_readl(reg) |
52 | #define DUMP_INTC_REG(reg, off) \ | 52 | #define DUMP_INTC_REG(reg, off) \ |
53 | regs[reg_count].name = #reg; \ | 53 | regs[reg_count].name = #reg; \ |
54 | regs[reg_count++].val = __raw_readl(OMAP2_IO_ADDRESS(0x480fe000 + (off))) | 54 | regs[reg_count++].val = \ |
55 | __raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off))) | ||
55 | 56 | ||
56 | static int __init pm_dbg_init(void); | 57 | static int __init pm_dbg_init(void); |
57 | 58 | ||
@@ -526,6 +527,29 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *dir) | |||
526 | return 0; | 527 | return 0; |
527 | } | 528 | } |
528 | 529 | ||
530 | static int option_get(void *data, u64 *val) | ||
531 | { | ||
532 | u32 *option = data; | ||
533 | |||
534 | *val = *option; | ||
535 | |||
536 | return 0; | ||
537 | } | ||
538 | |||
539 | static int option_set(void *data, u64 val) | ||
540 | { | ||
541 | u32 *option = data; | ||
542 | |||
543 | *option = val; | ||
544 | |||
545 | if (option == &enable_off_mode) | ||
546 | omap3_pm_off_mode_enable(val); | ||
547 | |||
548 | return 0; | ||
549 | } | ||
550 | |||
551 | DEFINE_SIMPLE_ATTRIBUTE(pm_dbg_option_fops, option_get, option_set, "%llu\n"); | ||
552 | |||
529 | static int __init pm_dbg_init(void) | 553 | static int __init pm_dbg_init(void) |
530 | { | 554 | { |
531 | int i; | 555 | int i; |
@@ -568,6 +592,12 @@ static int __init pm_dbg_init(void) | |||
568 | 592 | ||
569 | } | 593 | } |
570 | 594 | ||
595 | (void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUGO, d, | ||
596 | &enable_off_mode, &pm_dbg_option_fops); | ||
597 | (void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUGO, d, | ||
598 | &sleep_while_idle, &pm_dbg_option_fops); | ||
599 | (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUGO, d, | ||
600 | &wakeup_timer_seconds, &pm_dbg_option_fops); | ||
571 | pm_dbg_init_done = 1; | 601 | pm_dbg_init_done = 1; |
572 | 602 | ||
573 | return 0; | 603 | return 0; |
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 8400f5768923..0bf345db7147 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h | |||
@@ -11,11 +11,24 @@ | |||
11 | #ifndef __ARCH_ARM_MACH_OMAP2_PM_H | 11 | #ifndef __ARCH_ARM_MACH_OMAP2_PM_H |
12 | #define __ARCH_ARM_MACH_OMAP2_PM_H | 12 | #define __ARCH_ARM_MACH_OMAP2_PM_H |
13 | 13 | ||
14 | #include <mach/powerdomain.h> | 14 | #include <plat/powerdomain.h> |
15 | |||
16 | extern u32 enable_off_mode; | ||
17 | extern u32 sleep_while_idle; | ||
18 | |||
19 | extern void *omap3_secure_ram_storage; | ||
20 | extern void omap3_pm_off_mode_enable(int); | ||
21 | extern void omap_sram_idle(void); | ||
22 | extern int omap3_can_sleep(void); | ||
23 | extern int set_pwrdm_state(struct powerdomain *pwrdm, u32 state); | ||
24 | extern int omap3_idle_init(void); | ||
15 | 25 | ||
16 | extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm); | 26 | extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm); |
17 | extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state); | 27 | extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state); |
18 | 28 | ||
29 | extern u32 wakeup_timer_seconds; | ||
30 | extern struct omap_dm_timer *gptimer_wakeup; | ||
31 | |||
19 | #ifdef CONFIG_PM_DEBUG | 32 | #ifdef CONFIG_PM_DEBUG |
20 | extern void omap2_pm_dump(int mode, int resume, unsigned int us); | 33 | extern void omap2_pm_dump(int mode, int resume, unsigned int us); |
21 | extern int omap2_pm_debug; | 34 | extern int omap2_pm_debug; |
@@ -36,6 +49,7 @@ extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl, | |||
36 | void __iomem *sdrc_power); | 49 | void __iomem *sdrc_power); |
37 | extern void omap34xx_cpu_suspend(u32 *addr, int save_state); | 50 | extern void omap34xx_cpu_suspend(u32 *addr, int save_state); |
38 | extern void save_secure_ram_context(u32 *addr); | 51 | extern void save_secure_ram_context(u32 *addr); |
52 | extern void omap3_save_scratchpad_contents(void); | ||
39 | 53 | ||
40 | extern unsigned int omap24xx_idle_loop_suspend_sz; | 54 | extern unsigned int omap24xx_idle_loop_suspend_sz; |
41 | extern unsigned int omap34xx_suspend_sz; | 55 | extern unsigned int omap34xx_suspend_sz; |
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index bff5c4e89742..cba05b9f041f 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c | |||
@@ -36,12 +36,12 @@ | |||
36 | #include <asm/mach-types.h> | 36 | #include <asm/mach-types.h> |
37 | 37 | ||
38 | #include <mach/irqs.h> | 38 | #include <mach/irqs.h> |
39 | #include <mach/clock.h> | 39 | #include <plat/clock.h> |
40 | #include <mach/sram.h> | 40 | #include <plat/sram.h> |
41 | #include <mach/control.h> | 41 | #include <plat/control.h> |
42 | #include <mach/mux.h> | 42 | #include <plat/mux.h> |
43 | #include <mach/dma.h> | 43 | #include <plat/dma.h> |
44 | #include <mach/board.h> | 44 | #include <plat/board.h> |
45 | 45 | ||
46 | #include "prm.h" | 46 | #include "prm.h" |
47 | #include "prm-regbits-24xx.h" | 47 | #include "prm-regbits-24xx.h" |
@@ -50,8 +50,8 @@ | |||
50 | #include "sdrc.h" | 50 | #include "sdrc.h" |
51 | #include "pm.h" | 51 | #include "pm.h" |
52 | 52 | ||
53 | #include <mach/powerdomain.h> | 53 | #include <plat/powerdomain.h> |
54 | #include <mach/clockdomain.h> | 54 | #include <plat/clockdomain.h> |
55 | 55 | ||
56 | static void (*omap2_sram_idle)(void); | 56 | static void (*omap2_sram_idle)(void); |
57 | static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl, | 57 | static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl, |
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 89463190923a..81ed252a0f8a 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c | |||
@@ -5,6 +5,9 @@ | |||
5 | * Tony Lindgren <tony@atomide.com> | 5 | * Tony Lindgren <tony@atomide.com> |
6 | * Jouni Hogander | 6 | * Jouni Hogander |
7 | * | 7 | * |
8 | * Copyright (C) 2007 Texas Instruments, Inc. | ||
9 | * Rajendra Nayak <rnayak@ti.com> | ||
10 | * | ||
8 | * Copyright (C) 2005 Texas Instruments, Inc. | 11 | * Copyright (C) 2005 Texas Instruments, Inc. |
9 | * Richard Woodruff <r-woodruff2@ti.com> | 12 | * Richard Woodruff <r-woodruff2@ti.com> |
10 | * | 13 | * |
@@ -22,12 +25,20 @@ | |||
22 | #include <linux/list.h> | 25 | #include <linux/list.h> |
23 | #include <linux/err.h> | 26 | #include <linux/err.h> |
24 | #include <linux/gpio.h> | 27 | #include <linux/gpio.h> |
28 | #include <linux/clk.h> | ||
29 | |||
30 | #include <plat/sram.h> | ||
31 | #include <plat/clockdomain.h> | ||
32 | #include <plat/powerdomain.h> | ||
33 | #include <plat/control.h> | ||
34 | #include <plat/serial.h> | ||
35 | #include <plat/sdrc.h> | ||
36 | #include <plat/prcm.h> | ||
37 | #include <plat/gpmc.h> | ||
38 | #include <plat/dma.h> | ||
39 | #include <plat/dmtimer.h> | ||
25 | 40 | ||
26 | #include <mach/sram.h> | 41 | #include <asm/tlbflush.h> |
27 | #include <mach/clockdomain.h> | ||
28 | #include <mach/powerdomain.h> | ||
29 | #include <mach/control.h> | ||
30 | #include <mach/serial.h> | ||
31 | 42 | ||
32 | #include "cm.h" | 43 | #include "cm.h" |
33 | #include "cm-regbits-34xx.h" | 44 | #include "cm-regbits-34xx.h" |
@@ -35,6 +46,16 @@ | |||
35 | 46 | ||
36 | #include "prm.h" | 47 | #include "prm.h" |
37 | #include "pm.h" | 48 | #include "pm.h" |
49 | #include "sdrc.h" | ||
50 | |||
51 | /* Scratchpad offsets */ | ||
52 | #define OMAP343X_TABLE_ADDRESS_OFFSET 0x31 | ||
53 | #define OMAP343X_TABLE_VALUE_OFFSET 0x30 | ||
54 | #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32 | ||
55 | |||
56 | u32 enable_off_mode; | ||
57 | u32 sleep_while_idle; | ||
58 | u32 wakeup_timer_seconds; | ||
38 | 59 | ||
39 | struct power_state { | 60 | struct power_state { |
40 | struct powerdomain *pwrdm; | 61 | struct powerdomain *pwrdm; |
@@ -49,7 +70,112 @@ static LIST_HEAD(pwrst_list); | |||
49 | 70 | ||
50 | static void (*_omap_sram_idle)(u32 *addr, int save_state); | 71 | static void (*_omap_sram_idle)(u32 *addr, int save_state); |
51 | 72 | ||
52 | static struct powerdomain *mpu_pwrdm; | 73 | static int (*_omap_save_secure_sram)(u32 *addr); |
74 | |||
75 | static struct powerdomain *mpu_pwrdm, *neon_pwrdm; | ||
76 | static struct powerdomain *core_pwrdm, *per_pwrdm; | ||
77 | static struct powerdomain *cam_pwrdm; | ||
78 | |||
79 | static inline void omap3_per_save_context(void) | ||
80 | { | ||
81 | omap_gpio_save_context(); | ||
82 | } | ||
83 | |||
84 | static inline void omap3_per_restore_context(void) | ||
85 | { | ||
86 | omap_gpio_restore_context(); | ||
87 | } | ||
88 | |||
89 | static void omap3_enable_io_chain(void) | ||
90 | { | ||
91 | int timeout = 0; | ||
92 | |||
93 | if (omap_rev() >= OMAP3430_REV_ES3_1) { | ||
94 | prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN); | ||
95 | /* Do a readback to assure write has been done */ | ||
96 | prm_read_mod_reg(WKUP_MOD, PM_WKEN); | ||
97 | |||
98 | while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) & | ||
99 | OMAP3430_ST_IO_CHAIN)) { | ||
100 | timeout++; | ||
101 | if (timeout > 1000) { | ||
102 | printk(KERN_ERR "Wake up daisy chain " | ||
103 | "activation failed.\n"); | ||
104 | return; | ||
105 | } | ||
106 | prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN, | ||
107 | WKUP_MOD, PM_WKST); | ||
108 | } | ||
109 | } | ||
110 | } | ||
111 | |||
112 | static void omap3_disable_io_chain(void) | ||
113 | { | ||
114 | if (omap_rev() >= OMAP3430_REV_ES3_1) | ||
115 | prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN); | ||
116 | } | ||
117 | |||
118 | static void omap3_core_save_context(void) | ||
119 | { | ||
120 | u32 control_padconf_off; | ||
121 | |||
122 | /* Save the padconf registers */ | ||
123 | control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF); | ||
124 | control_padconf_off |= START_PADCONF_SAVE; | ||
125 | omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF); | ||
126 | /* wait for the save to complete */ | ||
127 | while (!omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) | ||
128 | & PADCONF_SAVE_DONE) | ||
129 | ; | ||
130 | /* Save the Interrupt controller context */ | ||
131 | omap_intc_save_context(); | ||
132 | /* Save the GPMC context */ | ||
133 | omap3_gpmc_save_context(); | ||
134 | /* Save the system control module context, padconf already save above*/ | ||
135 | omap3_control_save_context(); | ||
136 | omap_dma_global_context_save(); | ||
137 | } | ||
138 | |||
139 | static void omap3_core_restore_context(void) | ||
140 | { | ||
141 | /* Restore the control module context, padconf restored by h/w */ | ||
142 | omap3_control_restore_context(); | ||
143 | /* Restore the GPMC context */ | ||
144 | omap3_gpmc_restore_context(); | ||
145 | /* Restore the interrupt controller context */ | ||
146 | omap_intc_restore_context(); | ||
147 | omap_dma_global_context_restore(); | ||
148 | } | ||
149 | |||
150 | /* | ||
151 | * FIXME: This function should be called before entering off-mode after | ||
152 | * OMAP3 secure services have been accessed. Currently it is only called | ||
153 | * once during boot sequence, but this works as we are not using secure | ||
154 | * services. | ||
155 | */ | ||
156 | static void omap3_save_secure_ram_context(u32 target_mpu_state) | ||
157 | { | ||
158 | u32 ret; | ||
159 | |||
160 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { | ||
161 | /* | ||
162 | * MPU next state must be set to POWER_ON temporarily, | ||
163 | * otherwise the WFI executed inside the ROM code | ||
164 | * will hang the system. | ||
165 | */ | ||
166 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); | ||
167 | ret = _omap_save_secure_sram((u32 *) | ||
168 | __pa(omap3_secure_ram_storage)); | ||
169 | pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state); | ||
170 | /* Following is for error tracking, it should not happen */ | ||
171 | if (ret) { | ||
172 | printk(KERN_ERR "save_secure_sram() returns %08x\n", | ||
173 | ret); | ||
174 | while (1) | ||
175 | ; | ||
176 | } | ||
177 | } | ||
178 | } | ||
53 | 179 | ||
54 | /* | 180 | /* |
55 | * PRCM Interrupt Handler Helper Function | 181 | * PRCM Interrupt Handler Helper Function |
@@ -161,7 +287,36 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) | |||
161 | return IRQ_HANDLED; | 287 | return IRQ_HANDLED; |
162 | } | 288 | } |
163 | 289 | ||
164 | static void omap_sram_idle(void) | 290 | static void restore_control_register(u32 val) |
291 | { | ||
292 | __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val)); | ||
293 | } | ||
294 | |||
295 | /* Function to restore the table entry that was modified for enabling MMU */ | ||
296 | static void restore_table_entry(void) | ||
297 | { | ||
298 | u32 *scratchpad_address; | ||
299 | u32 previous_value, control_reg_value; | ||
300 | u32 *address; | ||
301 | |||
302 | scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); | ||
303 | |||
304 | /* Get address of entry that was modified */ | ||
305 | address = (u32 *)__raw_readl(scratchpad_address + | ||
306 | OMAP343X_TABLE_ADDRESS_OFFSET); | ||
307 | /* Get the previous value which needs to be restored */ | ||
308 | previous_value = __raw_readl(scratchpad_address + | ||
309 | OMAP343X_TABLE_VALUE_OFFSET); | ||
310 | address = __va(address); | ||
311 | *address = previous_value; | ||
312 | flush_tlb_all(); | ||
313 | control_reg_value = __raw_readl(scratchpad_address | ||
314 | + OMAP343X_CONTROL_REG_VALUE_OFFSET); | ||
315 | /* This will enable caches and prediction */ | ||
316 | restore_control_register(control_reg_value); | ||
317 | } | ||
318 | |||
319 | void omap_sram_idle(void) | ||
165 | { | 320 | { |
166 | /* Variable to tell what needs to be saved and restored | 321 | /* Variable to tell what needs to be saved and restored |
167 | * in omap_sram_idle*/ | 322 | * in omap_sram_idle*/ |
@@ -169,17 +324,32 @@ static void omap_sram_idle(void) | |||
169 | /* save_state = 1 => Only L1 and logic lost */ | 324 | /* save_state = 1 => Only L1 and logic lost */ |
170 | /* save_state = 2 => Only L2 lost */ | 325 | /* save_state = 2 => Only L2 lost */ |
171 | /* save_state = 3 => L1, L2 and logic lost */ | 326 | /* save_state = 3 => L1, L2 and logic lost */ |
172 | int save_state = 0, mpu_next_state; | 327 | int save_state = 0; |
328 | int mpu_next_state = PWRDM_POWER_ON; | ||
329 | int per_next_state = PWRDM_POWER_ON; | ||
330 | int core_next_state = PWRDM_POWER_ON; | ||
331 | int core_prev_state, per_prev_state; | ||
332 | u32 sdrc_pwr = 0; | ||
333 | int per_state_modified = 0; | ||
173 | 334 | ||
174 | if (!_omap_sram_idle) | 335 | if (!_omap_sram_idle) |
175 | return; | 336 | return; |
176 | 337 | ||
338 | pwrdm_clear_all_prev_pwrst(mpu_pwrdm); | ||
339 | pwrdm_clear_all_prev_pwrst(neon_pwrdm); | ||
340 | pwrdm_clear_all_prev_pwrst(core_pwrdm); | ||
341 | pwrdm_clear_all_prev_pwrst(per_pwrdm); | ||
342 | |||
177 | mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); | 343 | mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); |
178 | switch (mpu_next_state) { | 344 | switch (mpu_next_state) { |
345 | case PWRDM_POWER_ON: | ||
179 | case PWRDM_POWER_RET: | 346 | case PWRDM_POWER_RET: |
180 | /* No need to save context */ | 347 | /* No need to save context */ |
181 | save_state = 0; | 348 | save_state = 0; |
182 | break; | 349 | break; |
350 | case PWRDM_POWER_OFF: | ||
351 | save_state = 3; | ||
352 | break; | ||
183 | default: | 353 | default: |
184 | /* Invalid state */ | 354 | /* Invalid state */ |
185 | printk(KERN_ERR "Invalid mpu state in sram_idle\n"); | 355 | printk(KERN_ERR "Invalid mpu state in sram_idle\n"); |
@@ -187,68 +357,115 @@ static void omap_sram_idle(void) | |||
187 | } | 357 | } |
188 | pwrdm_pre_transition(); | 358 | pwrdm_pre_transition(); |
189 | 359 | ||
190 | omap2_gpio_prepare_for_retention(); | 360 | /* NEON control */ |
191 | omap_uart_prepare_idle(0); | 361 | if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) |
192 | omap_uart_prepare_idle(1); | 362 | pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); |
193 | omap_uart_prepare_idle(2); | 363 | |
364 | /* PER */ | ||
365 | per_next_state = pwrdm_read_next_pwrst(per_pwrdm); | ||
366 | core_next_state = pwrdm_read_next_pwrst(core_pwrdm); | ||
367 | if (per_next_state < PWRDM_POWER_ON) { | ||
368 | omap_uart_prepare_idle(2); | ||
369 | omap2_gpio_prepare_for_retention(); | ||
370 | if (per_next_state == PWRDM_POWER_OFF) { | ||
371 | if (core_next_state == PWRDM_POWER_ON) { | ||
372 | per_next_state = PWRDM_POWER_RET; | ||
373 | pwrdm_set_next_pwrst(per_pwrdm, per_next_state); | ||
374 | per_state_modified = 1; | ||
375 | } else | ||
376 | omap3_per_save_context(); | ||
377 | } | ||
378 | } | ||
379 | |||
380 | if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON) | ||
381 | omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]); | ||
382 | |||
383 | /* CORE */ | ||
384 | if (core_next_state < PWRDM_POWER_ON) { | ||
385 | omap_uart_prepare_idle(0); | ||
386 | omap_uart_prepare_idle(1); | ||
387 | if (core_next_state == PWRDM_POWER_OFF) { | ||
388 | omap3_core_save_context(); | ||
389 | omap3_prcm_save_context(); | ||
390 | } | ||
391 | /* Enable IO-PAD and IO-CHAIN wakeups */ | ||
392 | prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN); | ||
393 | omap3_enable_io_chain(); | ||
394 | } | ||
395 | |||
396 | /* | ||
397 | * On EMU/HS devices ROM code restores a SRDC value | ||
398 | * from scratchpad which has automatic self refresh on timeout | ||
399 | * of AUTO_CNT = 1 enabled. This takes care of errata 1.142. | ||
400 | * Hence store/restore the SDRC_POWER register here. | ||
401 | */ | ||
402 | if (omap_rev() >= OMAP3430_REV_ES3_0 && | ||
403 | omap_type() != OMAP2_DEVICE_TYPE_GP && | ||
404 | core_next_state == PWRDM_POWER_OFF) | ||
405 | sdrc_pwr = sdrc_read_reg(SDRC_POWER); | ||
194 | 406 | ||
195 | _omap_sram_idle(NULL, save_state); | 407 | /* |
408 | * omap3_arm_context is the location where ARM registers | ||
409 | * get saved. The restore path then reads from this | ||
410 | * location and restores them back. | ||
411 | */ | ||
412 | _omap_sram_idle(omap3_arm_context, save_state); | ||
196 | cpu_init(); | 413 | cpu_init(); |
197 | 414 | ||
198 | omap_uart_resume_idle(2); | 415 | /* Restore normal SDRC POWER settings */ |
199 | omap_uart_resume_idle(1); | 416 | if (omap_rev() >= OMAP3430_REV_ES3_0 && |
200 | omap_uart_resume_idle(0); | 417 | omap_type() != OMAP2_DEVICE_TYPE_GP && |
201 | omap2_gpio_resume_after_retention(); | 418 | core_next_state == PWRDM_POWER_OFF) |
419 | sdrc_write_reg(sdrc_pwr, SDRC_POWER); | ||
420 | |||
421 | /* Restore table entry modified during MMU restoration */ | ||
422 | if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF) | ||
423 | restore_table_entry(); | ||
424 | |||
425 | /* CORE */ | ||
426 | if (core_next_state < PWRDM_POWER_ON) { | ||
427 | core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); | ||
428 | if (core_prev_state == PWRDM_POWER_OFF) { | ||
429 | omap3_core_restore_context(); | ||
430 | omap3_prcm_restore_context(); | ||
431 | omap3_sram_restore_context(); | ||
432 | omap2_sms_restore_context(); | ||
433 | } | ||
434 | omap_uart_resume_idle(0); | ||
435 | omap_uart_resume_idle(1); | ||
436 | if (core_next_state == PWRDM_POWER_OFF) | ||
437 | prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF, | ||
438 | OMAP3430_GR_MOD, | ||
439 | OMAP3_PRM_VOLTCTRL_OFFSET); | ||
440 | } | ||
202 | 441 | ||
203 | pwrdm_post_transition(); | 442 | /* PER */ |
443 | if (per_next_state < PWRDM_POWER_ON) { | ||
444 | per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); | ||
445 | if (per_prev_state == PWRDM_POWER_OFF) | ||
446 | omap3_per_restore_context(); | ||
447 | omap2_gpio_resume_after_retention(); | ||
448 | omap_uart_resume_idle(2); | ||
449 | if (per_state_modified) | ||
450 | pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF); | ||
451 | } | ||
204 | 452 | ||
205 | } | 453 | /* Disable IO-PAD and IO-CHAIN wakeup */ |
454 | if (core_next_state < PWRDM_POWER_ON) { | ||
455 | prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN); | ||
456 | omap3_disable_io_chain(); | ||
457 | } | ||
206 | 458 | ||
207 | /* | 459 | pwrdm_post_transition(); |
208 | * Check if functional clocks are enabled before entering | ||
209 | * sleep. This function could be behind CONFIG_PM_DEBUG | ||
210 | * when all drivers are configuring their sysconfig registers | ||
211 | * properly and using their clocks properly. | ||
212 | */ | ||
213 | static int omap3_fclks_active(void) | ||
214 | { | ||
215 | u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0, | ||
216 | fck_cam = 0, fck_per = 0, fck_usbhost = 0; | ||
217 | 460 | ||
218 | fck_core1 = cm_read_mod_reg(CORE_MOD, | 461 | omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); |
219 | CM_FCLKEN1); | ||
220 | if (omap_rev() > OMAP3430_REV_ES1_0) { | ||
221 | fck_core3 = cm_read_mod_reg(CORE_MOD, | ||
222 | OMAP3430ES2_CM_FCLKEN3); | ||
223 | fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD, | ||
224 | CM_FCLKEN); | ||
225 | fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, | ||
226 | CM_FCLKEN); | ||
227 | } else | ||
228 | fck_sgx = cm_read_mod_reg(GFX_MOD, | ||
229 | OMAP3430ES2_CM_FCLKEN3); | ||
230 | fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD, | ||
231 | CM_FCLKEN); | ||
232 | fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD, | ||
233 | CM_FCLKEN); | ||
234 | fck_per = cm_read_mod_reg(OMAP3430_PER_MOD, | ||
235 | CM_FCLKEN); | ||
236 | |||
237 | /* Ignore UART clocks. These are handled by UART core (serial.c) */ | ||
238 | fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2); | ||
239 | fck_per &= ~OMAP3430_EN_UART3; | ||
240 | |||
241 | if (fck_core1 | fck_core3 | fck_sgx | fck_dss | | ||
242 | fck_cam | fck_per | fck_usbhost) | ||
243 | return 1; | ||
244 | return 0; | ||
245 | } | 462 | } |
246 | 463 | ||
247 | static int omap3_can_sleep(void) | 464 | int omap3_can_sleep(void) |
248 | { | 465 | { |
249 | if (!omap_uart_can_sleep()) | 466 | if (!sleep_while_idle) |
250 | return 0; | 467 | return 0; |
251 | if (omap3_fclks_active()) | 468 | if (!omap_uart_can_sleep()) |
252 | return 0; | 469 | return 0; |
253 | return 1; | 470 | return 1; |
254 | } | 471 | } |
@@ -256,7 +473,7 @@ static int omap3_can_sleep(void) | |||
256 | /* This sets pwrdm state (other than mpu & core. Currently only ON & | 473 | /* This sets pwrdm state (other than mpu & core. Currently only ON & |
257 | * RET are supported. Function is assuming that clkdm doesn't have | 474 | * RET are supported. Function is assuming that clkdm doesn't have |
258 | * hw_sup mode enabled. */ | 475 | * hw_sup mode enabled. */ |
259 | static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state) | 476 | int set_pwrdm_state(struct powerdomain *pwrdm, u32 state) |
260 | { | 477 | { |
261 | u32 cur_state; | 478 | u32 cur_state; |
262 | int sleep_switch = 0; | 479 | int sleep_switch = 0; |
@@ -306,7 +523,7 @@ static void omap3_pm_idle(void) | |||
306 | if (!omap3_can_sleep()) | 523 | if (!omap3_can_sleep()) |
307 | goto out; | 524 | goto out; |
308 | 525 | ||
309 | if (omap_irq_pending()) | 526 | if (omap_irq_pending() || need_resched()) |
310 | goto out; | 527 | goto out; |
311 | 528 | ||
312 | omap_sram_idle(); | 529 | omap_sram_idle(); |
@@ -319,6 +536,22 @@ out: | |||
319 | #ifdef CONFIG_SUSPEND | 536 | #ifdef CONFIG_SUSPEND |
320 | static suspend_state_t suspend_state; | 537 | static suspend_state_t suspend_state; |
321 | 538 | ||
539 | static void omap2_pm_wakeup_on_timer(u32 seconds) | ||
540 | { | ||
541 | u32 tick_rate, cycles; | ||
542 | |||
543 | if (!seconds) | ||
544 | return; | ||
545 | |||
546 | tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup)); | ||
547 | cycles = tick_rate * seconds; | ||
548 | omap_dm_timer_stop(gptimer_wakeup); | ||
549 | omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles); | ||
550 | |||
551 | pr_info("PM: Resume timer in %d secs (%d ticks at %d ticks/sec.)\n", | ||
552 | seconds, cycles, tick_rate); | ||
553 | } | ||
554 | |||
322 | static int omap3_pm_prepare(void) | 555 | static int omap3_pm_prepare(void) |
323 | { | 556 | { |
324 | disable_hlt(); | 557 | disable_hlt(); |
@@ -330,6 +563,9 @@ static int omap3_pm_suspend(void) | |||
330 | struct power_state *pwrst; | 563 | struct power_state *pwrst; |
331 | int state, ret = 0; | 564 | int state, ret = 0; |
332 | 565 | ||
566 | if (wakeup_timer_seconds) | ||
567 | omap2_pm_wakeup_on_timer(wakeup_timer_seconds); | ||
568 | |||
333 | /* Read current next_pwrsts */ | 569 | /* Read current next_pwrsts */ |
334 | list_for_each_entry(pwrst, &pwrst_list, node) | 570 | list_for_each_entry(pwrst, &pwrst_list, node) |
335 | pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); | 571 | pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); |
@@ -690,6 +926,22 @@ static void __init prcm_setup_regs(void) | |||
690 | omap3_d2d_idle(); | 926 | omap3_d2d_idle(); |
691 | } | 927 | } |
692 | 928 | ||
929 | void omap3_pm_off_mode_enable(int enable) | ||
930 | { | ||
931 | struct power_state *pwrst; | ||
932 | u32 state; | ||
933 | |||
934 | if (enable) | ||
935 | state = PWRDM_POWER_OFF; | ||
936 | else | ||
937 | state = PWRDM_POWER_RET; | ||
938 | |||
939 | list_for_each_entry(pwrst, &pwrst_list, node) { | ||
940 | pwrst->next_state = state; | ||
941 | set_pwrdm_state(pwrst->pwrdm, state); | ||
942 | } | ||
943 | } | ||
944 | |||
693 | int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) | 945 | int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) |
694 | { | 946 | { |
695 | struct power_state *pwrst; | 947 | struct power_state *pwrst; |
@@ -749,6 +1001,15 @@ static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) | |||
749 | return 0; | 1001 | return 0; |
750 | } | 1002 | } |
751 | 1003 | ||
1004 | void omap_push_sram_idle(void) | ||
1005 | { | ||
1006 | _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, | ||
1007 | omap34xx_cpu_suspend_sz); | ||
1008 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) | ||
1009 | _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, | ||
1010 | save_secure_ram_context_sz); | ||
1011 | } | ||
1012 | |||
752 | static int __init omap3_pm_init(void) | 1013 | static int __init omap3_pm_init(void) |
753 | { | 1014 | { |
754 | struct power_state *pwrst, *tmp; | 1015 | struct power_state *pwrst, *tmp; |
@@ -786,15 +1047,47 @@ static int __init omap3_pm_init(void) | |||
786 | goto err2; | 1047 | goto err2; |
787 | } | 1048 | } |
788 | 1049 | ||
789 | _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, | 1050 | neon_pwrdm = pwrdm_lookup("neon_pwrdm"); |
790 | omap34xx_cpu_suspend_sz); | 1051 | per_pwrdm = pwrdm_lookup("per_pwrdm"); |
1052 | core_pwrdm = pwrdm_lookup("core_pwrdm"); | ||
1053 | cam_pwrdm = pwrdm_lookup("cam_pwrdm"); | ||
791 | 1054 | ||
1055 | omap_push_sram_idle(); | ||
792 | #ifdef CONFIG_SUSPEND | 1056 | #ifdef CONFIG_SUSPEND |
793 | suspend_set_ops(&omap_pm_ops); | 1057 | suspend_set_ops(&omap_pm_ops); |
794 | #endif /* CONFIG_SUSPEND */ | 1058 | #endif /* CONFIG_SUSPEND */ |
795 | 1059 | ||
796 | pm_idle = omap3_pm_idle; | 1060 | pm_idle = omap3_pm_idle; |
1061 | omap3_idle_init(); | ||
1062 | |||
1063 | pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm); | ||
1064 | /* | ||
1065 | * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for | ||
1066 | * IO-pad wakeup. Otherwise it will unnecessarily waste power | ||
1067 | * waking up PER with every CORE wakeup - see | ||
1068 | * http://marc.info/?l=linux-omap&m=121852150710062&w=2 | ||
1069 | */ | ||
1070 | pwrdm_add_wkdep(per_pwrdm, core_pwrdm); | ||
1071 | |||
1072 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { | ||
1073 | omap3_secure_ram_storage = | ||
1074 | kmalloc(0x803F, GFP_KERNEL); | ||
1075 | if (!omap3_secure_ram_storage) | ||
1076 | printk(KERN_ERR "Memory allocation failed when" | ||
1077 | "allocating for secure sram context\n"); | ||
1078 | |||
1079 | local_irq_disable(); | ||
1080 | local_fiq_disable(); | ||
1081 | |||
1082 | omap_dma_global_context_save(); | ||
1083 | omap3_save_secure_ram_context(PWRDM_POWER_ON); | ||
1084 | omap_dma_global_context_restore(); | ||
1085 | |||
1086 | local_irq_enable(); | ||
1087 | local_fiq_enable(); | ||
1088 | } | ||
797 | 1089 | ||
1090 | omap3_save_scratchpad_contents(); | ||
798 | err1: | 1091 | err1: |
799 | return ret; | 1092 | return ret; |
800 | err2: | 1093 | err2: |
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index f00289abd30f..b6990e377783 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c | |||
@@ -31,9 +31,9 @@ | |||
31 | #include "prm.h" | 31 | #include "prm.h" |
32 | #include "prm-regbits-34xx.h" | 32 | #include "prm-regbits-34xx.h" |
33 | 33 | ||
34 | #include <mach/cpu.h> | 34 | #include <plat/cpu.h> |
35 | #include <mach/powerdomain.h> | 35 | #include <plat/powerdomain.h> |
36 | #include <mach/clockdomain.h> | 36 | #include <plat/clockdomain.h> |
37 | 37 | ||
38 | #include "pm.h" | 38 | #include "pm.h" |
39 | 39 | ||
diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains.h index 691470ea4c6a..057b2e3e2c35 100644 --- a/arch/arm/mach-omap2/powerdomains.h +++ b/arch/arm/mach-omap2/powerdomains.h | |||
@@ -63,7 +63,7 @@ | |||
63 | * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE | 63 | * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE |
64 | */ | 64 | */ |
65 | 65 | ||
66 | #include <mach/powerdomain.h> | 66 | #include <plat/powerdomain.h> |
67 | 67 | ||
68 | #include "prcm-common.h" | 68 | #include "prcm-common.h" |
69 | #include "prm.h" | 69 | #include "prm.h" |
diff --git a/arch/arm/mach-omap2/powerdomains24xx.h b/arch/arm/mach-omap2/powerdomains24xx.h index 9f08dc3f7fd2..bd249a495aa9 100644 --- a/arch/arm/mach-omap2/powerdomains24xx.h +++ b/arch/arm/mach-omap2/powerdomains24xx.h | |||
@@ -20,7 +20,7 @@ | |||
20 | * the array in mach-omap2/powerdomains.h. | 20 | * the array in mach-omap2/powerdomains.h. |
21 | */ | 21 | */ |
22 | 22 | ||
23 | #include <mach/powerdomain.h> | 23 | #include <plat/powerdomain.h> |
24 | 24 | ||
25 | #include "prcm-common.h" | 25 | #include "prcm-common.h" |
26 | #include "prm.h" | 26 | #include "prm.h" |
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h index 4dcf94b800ab..fd09b0827df0 100644 --- a/arch/arm/mach-omap2/powerdomains34xx.h +++ b/arch/arm/mach-omap2/powerdomains34xx.h | |||
@@ -20,7 +20,7 @@ | |||
20 | * the array in mach-omap2/powerdomains.h. | 20 | * the array in mach-omap2/powerdomains.h. |
21 | */ | 21 | */ |
22 | 22 | ||
23 | #include <mach/powerdomain.h> | 23 | #include <plat/powerdomain.h> |
24 | 24 | ||
25 | #include "prcm-common.h" | 25 | #include "prcm-common.h" |
26 | #include "prm.h" | 26 | #include "prm.h" |
@@ -338,7 +338,13 @@ static struct powerdomain usbhost_pwrdm = { | |||
338 | .sleepdep_srcs = dss_per_usbhost_sleepdeps, | 338 | .sleepdep_srcs = dss_per_usbhost_sleepdeps, |
339 | .pwrsts = PWRSTS_OFF_RET_ON, | 339 | .pwrsts = PWRSTS_OFF_RET_ON, |
340 | .pwrsts_logic_ret = PWRDM_POWER_RET, | 340 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
341 | .flags = PWRDM_HAS_HDWR_SAR, /* for USBHOST ctrlr only */ | 341 | /* |
342 | * REVISIT: Enabling usb host save and restore mechanism seems to | ||
343 | * leave the usb host domain permanently in ACTIVE mode after | ||
344 | * changing the usb host power domain state from OFF to active once. | ||
345 | * Disabling for now. | ||
346 | */ | ||
347 | /*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */ | ||
342 | .banks = 1, | 348 | .banks = 1, |
343 | .pwrsts_mem_ret = { | 349 | .pwrsts_mem_ret = { |
344 | [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ | 350 | [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ |
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index ced555a4cd1a..029d376198d4 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c | |||
@@ -7,6 +7,9 @@ | |||
7 | * | 7 | * |
8 | * Written by Tony Lindgren <tony.lindgren@nokia.com> | 8 | * Written by Tony Lindgren <tony.lindgren@nokia.com> |
9 | * | 9 | * |
10 | * Copyright (C) 2007 Texas Instruments, Inc. | ||
11 | * Rajendra Nayak <rnayak@ti.com> | ||
12 | * | ||
10 | * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc. | 13 | * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc. |
11 | * | 14 | * |
12 | * This program is free software; you can redistribute it and/or modify | 15 | * This program is free software; you can redistribute it and/or modify |
@@ -19,10 +22,13 @@ | |||
19 | #include <linux/io.h> | 22 | #include <linux/io.h> |
20 | #include <linux/delay.h> | 23 | #include <linux/delay.h> |
21 | 24 | ||
22 | #include <mach/common.h> | 25 | #include <plat/common.h> |
23 | #include <mach/prcm.h> | 26 | #include <plat/prcm.h> |
27 | #include <plat/irqs.h> | ||
28 | #include <plat/control.h> | ||
24 | 29 | ||
25 | #include "clock.h" | 30 | #include "clock.h" |
31 | #include "cm.h" | ||
26 | #include "prm.h" | 32 | #include "prm.h" |
27 | #include "prm-regbits-24xx.h" | 33 | #include "prm-regbits-24xx.h" |
28 | 34 | ||
@@ -31,6 +37,89 @@ static void __iomem *cm_base; | |||
31 | 37 | ||
32 | #define MAX_MODULE_ENABLE_WAIT 100000 | 38 | #define MAX_MODULE_ENABLE_WAIT 100000 |
33 | 39 | ||
40 | struct omap3_prcm_regs { | ||
41 | u32 control_padconf_sys_nirq; | ||
42 | u32 iva2_cm_clksel1; | ||
43 | u32 iva2_cm_clksel2; | ||
44 | u32 cm_sysconfig; | ||
45 | u32 sgx_cm_clksel; | ||
46 | u32 wkup_cm_clksel; | ||
47 | u32 dss_cm_clksel; | ||
48 | u32 cam_cm_clksel; | ||
49 | u32 per_cm_clksel; | ||
50 | u32 emu_cm_clksel; | ||
51 | u32 emu_cm_clkstctrl; | ||
52 | u32 pll_cm_autoidle2; | ||
53 | u32 pll_cm_clksel4; | ||
54 | u32 pll_cm_clksel5; | ||
55 | u32 pll_cm_clken; | ||
56 | u32 pll_cm_clken2; | ||
57 | u32 cm_polctrl; | ||
58 | u32 iva2_cm_fclken; | ||
59 | u32 iva2_cm_clken_pll; | ||
60 | u32 core_cm_fclken1; | ||
61 | u32 core_cm_fclken3; | ||
62 | u32 sgx_cm_fclken; | ||
63 | u32 wkup_cm_fclken; | ||
64 | u32 dss_cm_fclken; | ||
65 | u32 cam_cm_fclken; | ||
66 | u32 per_cm_fclken; | ||
67 | u32 usbhost_cm_fclken; | ||
68 | u32 core_cm_iclken1; | ||
69 | u32 core_cm_iclken2; | ||
70 | u32 core_cm_iclken3; | ||
71 | u32 sgx_cm_iclken; | ||
72 | u32 wkup_cm_iclken; | ||
73 | u32 dss_cm_iclken; | ||
74 | u32 cam_cm_iclken; | ||
75 | u32 per_cm_iclken; | ||
76 | u32 usbhost_cm_iclken; | ||
77 | u32 iva2_cm_autiidle2; | ||
78 | u32 mpu_cm_autoidle2; | ||
79 | u32 pll_cm_autoidle; | ||
80 | u32 iva2_cm_clkstctrl; | ||
81 | u32 mpu_cm_clkstctrl; | ||
82 | u32 core_cm_clkstctrl; | ||
83 | u32 sgx_cm_clkstctrl; | ||
84 | u32 dss_cm_clkstctrl; | ||
85 | u32 cam_cm_clkstctrl; | ||
86 | u32 per_cm_clkstctrl; | ||
87 | u32 neon_cm_clkstctrl; | ||
88 | u32 usbhost_cm_clkstctrl; | ||
89 | u32 core_cm_autoidle1; | ||
90 | u32 core_cm_autoidle2; | ||
91 | u32 core_cm_autoidle3; | ||
92 | u32 wkup_cm_autoidle; | ||
93 | u32 dss_cm_autoidle; | ||
94 | u32 cam_cm_autoidle; | ||
95 | u32 per_cm_autoidle; | ||
96 | u32 usbhost_cm_autoidle; | ||
97 | u32 sgx_cm_sleepdep; | ||
98 | u32 dss_cm_sleepdep; | ||
99 | u32 cam_cm_sleepdep; | ||
100 | u32 per_cm_sleepdep; | ||
101 | u32 usbhost_cm_sleepdep; | ||
102 | u32 cm_clkout_ctrl; | ||
103 | u32 prm_clkout_ctrl; | ||
104 | u32 sgx_pm_wkdep; | ||
105 | u32 dss_pm_wkdep; | ||
106 | u32 cam_pm_wkdep; | ||
107 | u32 per_pm_wkdep; | ||
108 | u32 neon_pm_wkdep; | ||
109 | u32 usbhost_pm_wkdep; | ||
110 | u32 core_pm_mpugrpsel1; | ||
111 | u32 iva2_pm_ivagrpsel1; | ||
112 | u32 core_pm_mpugrpsel3; | ||
113 | u32 core_pm_ivagrpsel3; | ||
114 | u32 wkup_pm_mpugrpsel; | ||
115 | u32 wkup_pm_ivagrpsel; | ||
116 | u32 per_pm_mpugrpsel; | ||
117 | u32 per_pm_ivagrpsel; | ||
118 | u32 wkup_pm_wken; | ||
119 | }; | ||
120 | |||
121 | struct omap3_prcm_regs prcm_context; | ||
122 | |||
34 | u32 omap_prcm_get_reset_sources(void) | 123 | u32 omap_prcm_get_reset_sources(void) |
35 | { | 124 | { |
36 | /* XXX This presumably needs modification for 34XX */ | 125 | /* XXX This presumably needs modification for 34XX */ |
@@ -46,9 +135,18 @@ void omap_prcm_arch_reset(char mode) | |||
46 | 135 | ||
47 | if (cpu_is_omap24xx()) | 136 | if (cpu_is_omap24xx()) |
48 | prcm_offs = WKUP_MOD; | 137 | prcm_offs = WKUP_MOD; |
49 | else if (cpu_is_omap34xx()) | 138 | else if (cpu_is_omap34xx()) { |
139 | u32 l; | ||
140 | |||
50 | prcm_offs = OMAP3430_GR_MOD; | 141 | prcm_offs = OMAP3430_GR_MOD; |
51 | else | 142 | l = ('B' << 24) | ('M' << 16) | mode; |
143 | /* Reserve the first word in scratchpad for communicating | ||
144 | * with the boot ROM. A pointer to a data structure | ||
145 | * describing the boot process can be stored there, | ||
146 | * cf. OMAP34xx TRM, Initialization / Software Booting | ||
147 | * Configuration. */ | ||
148 | omap_writel(l, OMAP343X_SCRATCHPAD + 4); | ||
149 | } else | ||
52 | WARN_ON(1); | 150 | WARN_ON(1); |
53 | 151 | ||
54 | prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL); | 152 | prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL); |
@@ -168,3 +266,308 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals) | |||
168 | prm_base = omap2_globals->prm; | 266 | prm_base = omap2_globals->prm; |
169 | cm_base = omap2_globals->cm; | 267 | cm_base = omap2_globals->cm; |
170 | } | 268 | } |
269 | |||
270 | #ifdef CONFIG_ARCH_OMAP3 | ||
271 | void omap3_prcm_save_context(void) | ||
272 | { | ||
273 | prcm_context.control_padconf_sys_nirq = | ||
274 | omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ); | ||
275 | prcm_context.iva2_cm_clksel1 = | ||
276 | cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1); | ||
277 | prcm_context.iva2_cm_clksel2 = | ||
278 | cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2); | ||
279 | prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG); | ||
280 | prcm_context.sgx_cm_clksel = | ||
281 | cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL); | ||
282 | prcm_context.wkup_cm_clksel = cm_read_mod_reg(WKUP_MOD, CM_CLKSEL); | ||
283 | prcm_context.dss_cm_clksel = | ||
284 | cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL); | ||
285 | prcm_context.cam_cm_clksel = | ||
286 | cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL); | ||
287 | prcm_context.per_cm_clksel = | ||
288 | cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL); | ||
289 | prcm_context.emu_cm_clksel = | ||
290 | cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1); | ||
291 | prcm_context.emu_cm_clkstctrl = | ||
292 | cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSTCTRL); | ||
293 | prcm_context.pll_cm_autoidle2 = | ||
294 | cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2); | ||
295 | prcm_context.pll_cm_clksel4 = | ||
296 | cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4); | ||
297 | prcm_context.pll_cm_clksel5 = | ||
298 | cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5); | ||
299 | prcm_context.pll_cm_clken = | ||
300 | cm_read_mod_reg(PLL_MOD, CM_CLKEN); | ||
301 | prcm_context.pll_cm_clken2 = | ||
302 | cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2); | ||
303 | prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL); | ||
304 | prcm_context.iva2_cm_fclken = | ||
305 | cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN); | ||
306 | prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD, | ||
307 | OMAP3430_CM_CLKEN_PLL); | ||
308 | prcm_context.core_cm_fclken1 = | ||
309 | cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); | ||
310 | prcm_context.core_cm_fclken3 = | ||
311 | cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3); | ||
312 | prcm_context.sgx_cm_fclken = | ||
313 | cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN); | ||
314 | prcm_context.wkup_cm_fclken = | ||
315 | cm_read_mod_reg(WKUP_MOD, CM_FCLKEN); | ||
316 | prcm_context.dss_cm_fclken = | ||
317 | cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN); | ||
318 | prcm_context.cam_cm_fclken = | ||
319 | cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN); | ||
320 | prcm_context.per_cm_fclken = | ||
321 | cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN); | ||
322 | prcm_context.usbhost_cm_fclken = | ||
323 | cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); | ||
324 | prcm_context.core_cm_iclken1 = | ||
325 | cm_read_mod_reg(CORE_MOD, CM_ICLKEN1); | ||
326 | prcm_context.core_cm_iclken2 = | ||
327 | cm_read_mod_reg(CORE_MOD, CM_ICLKEN2); | ||
328 | prcm_context.core_cm_iclken3 = | ||
329 | cm_read_mod_reg(CORE_MOD, CM_ICLKEN3); | ||
330 | prcm_context.sgx_cm_iclken = | ||
331 | cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN); | ||
332 | prcm_context.wkup_cm_iclken = | ||
333 | cm_read_mod_reg(WKUP_MOD, CM_ICLKEN); | ||
334 | prcm_context.dss_cm_iclken = | ||
335 | cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN); | ||
336 | prcm_context.cam_cm_iclken = | ||
337 | cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN); | ||
338 | prcm_context.per_cm_iclken = | ||
339 | cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN); | ||
340 | prcm_context.usbhost_cm_iclken = | ||
341 | cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); | ||
342 | prcm_context.iva2_cm_autiidle2 = | ||
343 | cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2); | ||
344 | prcm_context.mpu_cm_autoidle2 = | ||
345 | cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2); | ||
346 | prcm_context.pll_cm_autoidle = | ||
347 | cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); | ||
348 | prcm_context.iva2_cm_clkstctrl = | ||
349 | cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSTCTRL); | ||
350 | prcm_context.mpu_cm_clkstctrl = | ||
351 | cm_read_mod_reg(MPU_MOD, CM_CLKSTCTRL); | ||
352 | prcm_context.core_cm_clkstctrl = | ||
353 | cm_read_mod_reg(CORE_MOD, CM_CLKSTCTRL); | ||
354 | prcm_context.sgx_cm_clkstctrl = | ||
355 | cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSTCTRL); | ||
356 | prcm_context.dss_cm_clkstctrl = | ||
357 | cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSTCTRL); | ||
358 | prcm_context.cam_cm_clkstctrl = | ||
359 | cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSTCTRL); | ||
360 | prcm_context.per_cm_clkstctrl = | ||
361 | cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSTCTRL); | ||
362 | prcm_context.neon_cm_clkstctrl = | ||
363 | cm_read_mod_reg(OMAP3430_NEON_MOD, CM_CLKSTCTRL); | ||
364 | prcm_context.usbhost_cm_clkstctrl = | ||
365 | cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL); | ||
366 | prcm_context.core_cm_autoidle1 = | ||
367 | cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1); | ||
368 | prcm_context.core_cm_autoidle2 = | ||
369 | cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2); | ||
370 | prcm_context.core_cm_autoidle3 = | ||
371 | cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3); | ||
372 | prcm_context.wkup_cm_autoidle = | ||
373 | cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE); | ||
374 | prcm_context.dss_cm_autoidle = | ||
375 | cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE); | ||
376 | prcm_context.cam_cm_autoidle = | ||
377 | cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE); | ||
378 | prcm_context.per_cm_autoidle = | ||
379 | cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); | ||
380 | prcm_context.usbhost_cm_autoidle = | ||
381 | cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); | ||
382 | prcm_context.sgx_cm_sleepdep = | ||
383 | cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP); | ||
384 | prcm_context.dss_cm_sleepdep = | ||
385 | cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP); | ||
386 | prcm_context.cam_cm_sleepdep = | ||
387 | cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP); | ||
388 | prcm_context.per_cm_sleepdep = | ||
389 | cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP); | ||
390 | prcm_context.usbhost_cm_sleepdep = | ||
391 | cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP); | ||
392 | prcm_context.cm_clkout_ctrl = cm_read_mod_reg(OMAP3430_CCR_MOD, | ||
393 | OMAP3_CM_CLKOUT_CTRL_OFFSET); | ||
394 | prcm_context.prm_clkout_ctrl = prm_read_mod_reg(OMAP3430_CCR_MOD, | ||
395 | OMAP3_PRM_CLKOUT_CTRL_OFFSET); | ||
396 | prcm_context.sgx_pm_wkdep = | ||
397 | prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP); | ||
398 | prcm_context.dss_pm_wkdep = | ||
399 | prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP); | ||
400 | prcm_context.cam_pm_wkdep = | ||
401 | prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP); | ||
402 | prcm_context.per_pm_wkdep = | ||
403 | prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP); | ||
404 | prcm_context.neon_pm_wkdep = | ||
405 | prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP); | ||
406 | prcm_context.usbhost_pm_wkdep = | ||
407 | prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKDEP); | ||
408 | prcm_context.core_pm_mpugrpsel1 = | ||
409 | prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL1); | ||
410 | prcm_context.iva2_pm_ivagrpsel1 = | ||
411 | prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1); | ||
412 | prcm_context.core_pm_mpugrpsel3 = | ||
413 | prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_MPUGRPSEL3); | ||
414 | prcm_context.core_pm_ivagrpsel3 = | ||
415 | prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); | ||
416 | prcm_context.wkup_pm_mpugrpsel = | ||
417 | prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL); | ||
418 | prcm_context.wkup_pm_ivagrpsel = | ||
419 | prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_IVAGRPSEL); | ||
420 | prcm_context.per_pm_mpugrpsel = | ||
421 | prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); | ||
422 | prcm_context.per_pm_ivagrpsel = | ||
423 | prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); | ||
424 | prcm_context.wkup_pm_wken = prm_read_mod_reg(WKUP_MOD, PM_WKEN); | ||
425 | return; | ||
426 | } | ||
427 | |||
428 | void omap3_prcm_restore_context(void) | ||
429 | { | ||
430 | omap_ctrl_writel(prcm_context.control_padconf_sys_nirq, | ||
431 | OMAP343X_CONTROL_PADCONF_SYSNIRQ); | ||
432 | cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD, | ||
433 | CM_CLKSEL1); | ||
434 | cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD, | ||
435 | CM_CLKSEL2); | ||
436 | __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG); | ||
437 | cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD, | ||
438 | CM_CLKSEL); | ||
439 | cm_write_mod_reg(prcm_context.wkup_cm_clksel, WKUP_MOD, CM_CLKSEL); | ||
440 | cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD, | ||
441 | CM_CLKSEL); | ||
442 | cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD, | ||
443 | CM_CLKSEL); | ||
444 | cm_write_mod_reg(prcm_context.per_cm_clksel, OMAP3430_PER_MOD, | ||
445 | CM_CLKSEL); | ||
446 | cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD, | ||
447 | CM_CLKSEL1); | ||
448 | cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD, | ||
449 | CM_CLKSTCTRL); | ||
450 | cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD, | ||
451 | CM_AUTOIDLE2); | ||
452 | cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD, | ||
453 | OMAP3430ES2_CM_CLKSEL4); | ||
454 | cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD, | ||
455 | OMAP3430ES2_CM_CLKSEL5); | ||
456 | cm_write_mod_reg(prcm_context.pll_cm_clken, PLL_MOD, CM_CLKEN); | ||
457 | cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD, | ||
458 | OMAP3430ES2_CM_CLKEN2); | ||
459 | __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL); | ||
460 | cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD, | ||
461 | CM_FCLKEN); | ||
462 | cm_write_mod_reg(prcm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD, | ||
463 | OMAP3430_CM_CLKEN_PLL); | ||
464 | cm_write_mod_reg(prcm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1); | ||
465 | cm_write_mod_reg(prcm_context.core_cm_fclken3, CORE_MOD, | ||
466 | OMAP3430ES2_CM_FCLKEN3); | ||
467 | cm_write_mod_reg(prcm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD, | ||
468 | CM_FCLKEN); | ||
469 | cm_write_mod_reg(prcm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN); | ||
470 | cm_write_mod_reg(prcm_context.dss_cm_fclken, OMAP3430_DSS_MOD, | ||
471 | CM_FCLKEN); | ||
472 | cm_write_mod_reg(prcm_context.cam_cm_fclken, OMAP3430_CAM_MOD, | ||
473 | CM_FCLKEN); | ||
474 | cm_write_mod_reg(prcm_context.per_cm_fclken, OMAP3430_PER_MOD, | ||
475 | CM_FCLKEN); | ||
476 | cm_write_mod_reg(prcm_context.usbhost_cm_fclken, | ||
477 | OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); | ||
478 | cm_write_mod_reg(prcm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1); | ||
479 | cm_write_mod_reg(prcm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2); | ||
480 | cm_write_mod_reg(prcm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3); | ||
481 | cm_write_mod_reg(prcm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD, | ||
482 | CM_ICLKEN); | ||
483 | cm_write_mod_reg(prcm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN); | ||
484 | cm_write_mod_reg(prcm_context.dss_cm_iclken, OMAP3430_DSS_MOD, | ||
485 | CM_ICLKEN); | ||
486 | cm_write_mod_reg(prcm_context.cam_cm_iclken, OMAP3430_CAM_MOD, | ||
487 | CM_ICLKEN); | ||
488 | cm_write_mod_reg(prcm_context.per_cm_iclken, OMAP3430_PER_MOD, | ||
489 | CM_ICLKEN); | ||
490 | cm_write_mod_reg(prcm_context.usbhost_cm_iclken, | ||
491 | OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); | ||
492 | cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD, | ||
493 | CM_AUTOIDLE2); | ||
494 | cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2); | ||
495 | cm_write_mod_reg(prcm_context.pll_cm_autoidle, PLL_MOD, CM_AUTOIDLE); | ||
496 | cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD, | ||
497 | CM_CLKSTCTRL); | ||
498 | cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, CM_CLKSTCTRL); | ||
499 | cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD, | ||
500 | CM_CLKSTCTRL); | ||
501 | cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD, | ||
502 | CM_CLKSTCTRL); | ||
503 | cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD, | ||
504 | CM_CLKSTCTRL); | ||
505 | cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD, | ||
506 | CM_CLKSTCTRL); | ||
507 | cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD, | ||
508 | CM_CLKSTCTRL); | ||
509 | cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD, | ||
510 | CM_CLKSTCTRL); | ||
511 | cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl, | ||
512 | OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL); | ||
513 | cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD, | ||
514 | CM_AUTOIDLE1); | ||
515 | cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD, | ||
516 | CM_AUTOIDLE2); | ||
517 | cm_write_mod_reg(prcm_context.core_cm_autoidle3, CORE_MOD, | ||
518 | CM_AUTOIDLE3); | ||
519 | cm_write_mod_reg(prcm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE); | ||
520 | cm_write_mod_reg(prcm_context.dss_cm_autoidle, OMAP3430_DSS_MOD, | ||
521 | CM_AUTOIDLE); | ||
522 | cm_write_mod_reg(prcm_context.cam_cm_autoidle, OMAP3430_CAM_MOD, | ||
523 | CM_AUTOIDLE); | ||
524 | cm_write_mod_reg(prcm_context.per_cm_autoidle, OMAP3430_PER_MOD, | ||
525 | CM_AUTOIDLE); | ||
526 | cm_write_mod_reg(prcm_context.usbhost_cm_autoidle, | ||
527 | OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); | ||
528 | cm_write_mod_reg(prcm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD, | ||
529 | OMAP3430_CM_SLEEPDEP); | ||
530 | cm_write_mod_reg(prcm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD, | ||
531 | OMAP3430_CM_SLEEPDEP); | ||
532 | cm_write_mod_reg(prcm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD, | ||
533 | OMAP3430_CM_SLEEPDEP); | ||
534 | cm_write_mod_reg(prcm_context.per_cm_sleepdep, OMAP3430_PER_MOD, | ||
535 | OMAP3430_CM_SLEEPDEP); | ||
536 | cm_write_mod_reg(prcm_context.usbhost_cm_sleepdep, | ||
537 | OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP); | ||
538 | cm_write_mod_reg(prcm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD, | ||
539 | OMAP3_CM_CLKOUT_CTRL_OFFSET); | ||
540 | prm_write_mod_reg(prcm_context.prm_clkout_ctrl, OMAP3430_CCR_MOD, | ||
541 | OMAP3_PRM_CLKOUT_CTRL_OFFSET); | ||
542 | prm_write_mod_reg(prcm_context.sgx_pm_wkdep, OMAP3430ES2_SGX_MOD, | ||
543 | PM_WKDEP); | ||
544 | prm_write_mod_reg(prcm_context.dss_pm_wkdep, OMAP3430_DSS_MOD, | ||
545 | PM_WKDEP); | ||
546 | prm_write_mod_reg(prcm_context.cam_pm_wkdep, OMAP3430_CAM_MOD, | ||
547 | PM_WKDEP); | ||
548 | prm_write_mod_reg(prcm_context.per_pm_wkdep, OMAP3430_PER_MOD, | ||
549 | PM_WKDEP); | ||
550 | prm_write_mod_reg(prcm_context.neon_pm_wkdep, OMAP3430_NEON_MOD, | ||
551 | PM_WKDEP); | ||
552 | prm_write_mod_reg(prcm_context.usbhost_pm_wkdep, | ||
553 | OMAP3430ES2_USBHOST_MOD, PM_WKDEP); | ||
554 | prm_write_mod_reg(prcm_context.core_pm_mpugrpsel1, CORE_MOD, | ||
555 | OMAP3430_PM_MPUGRPSEL1); | ||
556 | prm_write_mod_reg(prcm_context.iva2_pm_ivagrpsel1, OMAP3430_IVA2_MOD, | ||
557 | OMAP3430_PM_IVAGRPSEL1); | ||
558 | prm_write_mod_reg(prcm_context.core_pm_mpugrpsel3, CORE_MOD, | ||
559 | OMAP3430ES2_PM_MPUGRPSEL3); | ||
560 | prm_write_mod_reg(prcm_context.core_pm_ivagrpsel3, CORE_MOD, | ||
561 | OMAP3430ES2_PM_IVAGRPSEL3); | ||
562 | prm_write_mod_reg(prcm_context.wkup_pm_mpugrpsel, WKUP_MOD, | ||
563 | OMAP3430_PM_MPUGRPSEL); | ||
564 | prm_write_mod_reg(prcm_context.wkup_pm_ivagrpsel, WKUP_MOD, | ||
565 | OMAP3430_PM_IVAGRPSEL); | ||
566 | prm_write_mod_reg(prcm_context.per_pm_mpugrpsel, OMAP3430_PER_MOD, | ||
567 | OMAP3430_PM_MPUGRPSEL); | ||
568 | prm_write_mod_reg(prcm_context.per_pm_ivagrpsel, OMAP3430_PER_MOD, | ||
569 | OMAP3430_PM_IVAGRPSEL); | ||
570 | prm_write_mod_reg(prcm_context.wkup_pm_wken, WKUP_MOD, PM_WKEN); | ||
571 | return; | ||
572 | } | ||
573 | #endif | ||
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index 9fd03a2ec95c..8f21bae6dc1c 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h | |||
@@ -365,6 +365,7 @@ | |||
365 | /* PM_PREPWSTST_GFX specific bits */ | 365 | /* PM_PREPWSTST_GFX specific bits */ |
366 | 366 | ||
367 | /* PM_WKEN_WKUP specific bits */ | 367 | /* PM_WKEN_WKUP specific bits */ |
368 | #define OMAP3430_EN_IO_CHAIN (1 << 16) | ||
368 | #define OMAP3430_EN_IO (1 << 8) | 369 | #define OMAP3430_EN_IO (1 << 8) |
369 | #define OMAP3430_EN_GPIO1 (1 << 3) | 370 | #define OMAP3430_EN_GPIO1 (1 << 3) |
370 | 371 | ||
@@ -373,6 +374,7 @@ | |||
373 | /* PM_IVA2GRPSEL_WKUP specific bits */ | 374 | /* PM_IVA2GRPSEL_WKUP specific bits */ |
374 | 375 | ||
375 | /* PM_WKST_WKUP specific bits */ | 376 | /* PM_WKST_WKUP specific bits */ |
377 | #define OMAP3430_ST_IO_CHAIN (1 << 16) | ||
376 | #define OMAP3430_ST_IO (1 << 8) | 378 | #define OMAP3430_ST_IO (1 << 8) |
377 | 379 | ||
378 | /* PRM_CLKSEL */ | 380 | /* PRM_CLKSEL */ |
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index 03c467c35f54..a117f853ea39 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h | |||
@@ -17,11 +17,11 @@ | |||
17 | #include "prcm-common.h" | 17 | #include "prcm-common.h" |
18 | 18 | ||
19 | #define OMAP2420_PRM_REGADDR(module, reg) \ | 19 | #define OMAP2420_PRM_REGADDR(module, reg) \ |
20 | OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) | 20 | OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) |
21 | #define OMAP2430_PRM_REGADDR(module, reg) \ | 21 | #define OMAP2430_PRM_REGADDR(module, reg) \ |
22 | OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) | 22 | OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) |
23 | #define OMAP34XX_PRM_REGADDR(module, reg) \ | 23 | #define OMAP34XX_PRM_REGADDR(module, reg) \ |
24 | OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) | 24 | OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) |
25 | 25 | ||
26 | /* | 26 | /* |
27 | * Architecture-specific global PRM registers | 27 | * Architecture-specific global PRM registers |
diff --git a/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h index 02e1c2d4705f..a391b4939f74 100644 --- a/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h +++ b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h | |||
@@ -14,7 +14,7 @@ | |||
14 | #ifndef ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF | 14 | #ifndef ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF |
15 | #define ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF | 15 | #define ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF |
16 | 16 | ||
17 | #include <mach/sdrc.h> | 17 | #include <plat/sdrc.h> |
18 | 18 | ||
19 | /* Micron MT46H32M32LF-6 */ | 19 | /* Micron MT46H32M32LF-6 */ |
20 | /* XXX Using ARE = 0x1 (no autorefresh burst) -- can this be changed? */ | 20 | /* XXX Using ARE = 0x1 (no autorefresh burst) -- can this be changed? */ |
diff --git a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h index 3751d293cb1f..0e518a72831f 100644 --- a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h +++ b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h | |||
@@ -14,7 +14,7 @@ | |||
14 | #ifndef ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6 | 14 | #ifndef ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6 |
15 | #define ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6 | 15 | #define ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6 |
16 | 16 | ||
17 | #include <mach/sdrc.h> | 17 | #include <plat/sdrc.h> |
18 | 18 | ||
19 | /* Qimonda HYB18M512160AF-6 */ | 19 | /* Qimonda HYB18M512160AF-6 */ |
20 | static struct omap_sdrc_params hyb18m512160af6_sdrc_params[] = { | 20 | static struct omap_sdrc_params hyb18m512160af6_sdrc_params[] = { |
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c index 9e3bd4fa7810..9a592199321c 100644 --- a/arch/arm/mach-omap2/sdrc.c +++ b/arch/arm/mach-omap2/sdrc.c | |||
@@ -23,13 +23,13 @@ | |||
23 | #include <linux/clk.h> | 23 | #include <linux/clk.h> |
24 | #include <linux/io.h> | 24 | #include <linux/io.h> |
25 | 25 | ||
26 | #include <mach/common.h> | 26 | #include <plat/common.h> |
27 | #include <mach/clock.h> | 27 | #include <plat/clock.h> |
28 | #include <mach/sram.h> | 28 | #include <plat/sram.h> |
29 | 29 | ||
30 | #include "prm.h" | 30 | #include "prm.h" |
31 | 31 | ||
32 | #include <mach/sdrc.h> | 32 | #include <plat/sdrc.h> |
33 | #include "sdrc.h" | 33 | #include "sdrc.h" |
34 | 34 | ||
35 | static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1; | 35 | static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1; |
@@ -37,12 +37,38 @@ static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1; | |||
37 | void __iomem *omap2_sdrc_base; | 37 | void __iomem *omap2_sdrc_base; |
38 | void __iomem *omap2_sms_base; | 38 | void __iomem *omap2_sms_base; |
39 | 39 | ||
40 | struct omap2_sms_regs { | ||
41 | u32 sms_sysconfig; | ||
42 | }; | ||
43 | |||
44 | static struct omap2_sms_regs sms_context; | ||
45 | |||
40 | /* SDRC_POWER register bits */ | 46 | /* SDRC_POWER register bits */ |
41 | #define SDRC_POWER_EXTCLKDIS_SHIFT 3 | 47 | #define SDRC_POWER_EXTCLKDIS_SHIFT 3 |
42 | #define SDRC_POWER_PWDENA_SHIFT 2 | 48 | #define SDRC_POWER_PWDENA_SHIFT 2 |
43 | #define SDRC_POWER_PAGEPOLICY_SHIFT 0 | 49 | #define SDRC_POWER_PAGEPOLICY_SHIFT 0 |
44 | 50 | ||
45 | /** | 51 | /** |
52 | * omap2_sms_save_context - Save SMS registers | ||
53 | * | ||
54 | * Save SMS registers that need to be restored after off mode. | ||
55 | */ | ||
56 | void omap2_sms_save_context(void) | ||
57 | { | ||
58 | sms_context.sms_sysconfig = sms_read_reg(SMS_SYSCONFIG); | ||
59 | } | ||
60 | |||
61 | /** | ||
62 | * omap2_sms_restore_context - Restore SMS registers | ||
63 | * | ||
64 | * Restore SMS registers that need to be Restored after off mode. | ||
65 | */ | ||
66 | void omap2_sms_restore_context(void) | ||
67 | { | ||
68 | sms_write_reg(sms_context.sms_sysconfig, SMS_SYSCONFIG); | ||
69 | } | ||
70 | |||
71 | /** | ||
46 | * omap2_sdrc_get_params - return SDRC register values for a given clock rate | 72 | * omap2_sdrc_get_params - return SDRC register values for a given clock rate |
47 | * @r: SDRC clock rate (in Hz) | 73 | * @r: SDRC clock rate (in Hz) |
48 | * @sdrc_cs0: chip select 0 ram timings ** | 74 | * @sdrc_cs0: chip select 0 ram timings ** |
@@ -132,4 +158,5 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, | |||
132 | l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) | | 158 | l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) | |
133 | (1 << SDRC_POWER_PAGEPOLICY_SHIFT); | 159 | (1 << SDRC_POWER_PAGEPOLICY_SHIFT); |
134 | sdrc_write_reg(l, SDRC_POWER); | 160 | sdrc_write_reg(l, SDRC_POWER); |
161 | omap2_sms_save_context(); | ||
135 | } | 162 | } |
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h index 0837eda5f2b6..48207b018989 100644 --- a/arch/arm/mach-omap2/sdrc.h +++ b/arch/arm/mach-omap2/sdrc.h | |||
@@ -15,7 +15,7 @@ | |||
15 | */ | 15 | */ |
16 | #undef DEBUG | 16 | #undef DEBUG |
17 | 17 | ||
18 | #include <mach/sdrc.h> | 18 | #include <plat/sdrc.h> |
19 | 19 | ||
20 | #ifndef __ASSEMBLER__ | 20 | #ifndef __ASSEMBLER__ |
21 | extern void __iomem *omap2_sdrc_base; | 21 | extern void __iomem *omap2_sdrc_base; |
@@ -48,9 +48,12 @@ static inline u32 sms_read_reg(u16 reg) | |||
48 | return __raw_readl(OMAP_SMS_REGADDR(reg)); | 48 | return __raw_readl(OMAP_SMS_REGADDR(reg)); |
49 | } | 49 | } |
50 | #else | 50 | #else |
51 | #define OMAP242X_SDRC_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg)) | 51 | #define OMAP242X_SDRC_REGADDR(reg) \ |
52 | #define OMAP243X_SDRC_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg)) | 52 | OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg)) |
53 | #define OMAP34XX_SDRC_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg)) | 53 | #define OMAP243X_SDRC_REGADDR(reg) \ |
54 | OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg)) | ||
55 | #define OMAP34XX_SDRC_REGADDR(reg) \ | ||
56 | OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg)) | ||
54 | #endif /* __ASSEMBLER__ */ | 57 | #endif /* __ASSEMBLER__ */ |
55 | 58 | ||
56 | #endif | 59 | #endif |
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c index feaec7eaf6bd..0f4d27aef44d 100644 --- a/arch/arm/mach-omap2/sdrc2xxx.c +++ b/arch/arm/mach-omap2/sdrc2xxx.c | |||
@@ -24,13 +24,13 @@ | |||
24 | #include <linux/clk.h> | 24 | #include <linux/clk.h> |
25 | #include <linux/io.h> | 25 | #include <linux/io.h> |
26 | 26 | ||
27 | #include <mach/common.h> | 27 | #include <plat/common.h> |
28 | #include <mach/clock.h> | 28 | #include <plat/clock.h> |
29 | #include <mach/sram.h> | 29 | #include <plat/sram.h> |
30 | 30 | ||
31 | #include "prm.h" | 31 | #include "prm.h" |
32 | #include "clock.h" | 32 | #include "clock.h" |
33 | #include <mach/sdrc.h> | 33 | #include <plat/sdrc.h> |
34 | #include "sdrc.h" | 34 | #include "sdrc.h" |
35 | 35 | ||
36 | /* Memory timing, DLL mode flags */ | 36 | /* Memory timing, DLL mode flags */ |
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 54dfeb5d5667..72df1b188135 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c | |||
@@ -24,10 +24,10 @@ | |||
24 | #include <linux/clk.h> | 24 | #include <linux/clk.h> |
25 | #include <linux/io.h> | 25 | #include <linux/io.h> |
26 | 26 | ||
27 | #include <mach/common.h> | 27 | #include <plat/common.h> |
28 | #include <mach/board.h> | 28 | #include <plat/board.h> |
29 | #include <mach/clock.h> | 29 | #include <plat/clock.h> |
30 | #include <mach/control.h> | 30 | #include <plat/control.h> |
31 | 31 | ||
32 | #include "prm.h" | 32 | #include "prm.h" |
33 | #include "pm.h" | 33 | #include "pm.h" |
@@ -73,7 +73,6 @@ static LIST_HEAD(uart_list); | |||
73 | 73 | ||
74 | static struct plat_serial8250_port serial_platform_data0[] = { | 74 | static struct plat_serial8250_port serial_platform_data0[] = { |
75 | { | 75 | { |
76 | .membase = OMAP2_IO_ADDRESS(OMAP_UART1_BASE), | ||
77 | .mapbase = OMAP_UART1_BASE, | 76 | .mapbase = OMAP_UART1_BASE, |
78 | .irq = 72, | 77 | .irq = 72, |
79 | .flags = UPF_BOOT_AUTOCONF, | 78 | .flags = UPF_BOOT_AUTOCONF, |
@@ -87,7 +86,6 @@ static struct plat_serial8250_port serial_platform_data0[] = { | |||
87 | 86 | ||
88 | static struct plat_serial8250_port serial_platform_data1[] = { | 87 | static struct plat_serial8250_port serial_platform_data1[] = { |
89 | { | 88 | { |
90 | .membase = OMAP2_IO_ADDRESS(OMAP_UART2_BASE), | ||
91 | .mapbase = OMAP_UART2_BASE, | 89 | .mapbase = OMAP_UART2_BASE, |
92 | .irq = 73, | 90 | .irq = 73, |
93 | .flags = UPF_BOOT_AUTOCONF, | 91 | .flags = UPF_BOOT_AUTOCONF, |
@@ -101,7 +99,6 @@ static struct plat_serial8250_port serial_platform_data1[] = { | |||
101 | 99 | ||
102 | static struct plat_serial8250_port serial_platform_data2[] = { | 100 | static struct plat_serial8250_port serial_platform_data2[] = { |
103 | { | 101 | { |
104 | .membase = OMAP2_IO_ADDRESS(OMAP_UART3_BASE), | ||
105 | .mapbase = OMAP_UART3_BASE, | 102 | .mapbase = OMAP_UART3_BASE, |
106 | .irq = 74, | 103 | .irq = 74, |
107 | .flags = UPF_BOOT_AUTOCONF, | 104 | .flags = UPF_BOOT_AUTOCONF, |
@@ -116,7 +113,6 @@ static struct plat_serial8250_port serial_platform_data2[] = { | |||
116 | #ifdef CONFIG_ARCH_OMAP4 | 113 | #ifdef CONFIG_ARCH_OMAP4 |
117 | static struct plat_serial8250_port serial_platform_data3[] = { | 114 | static struct plat_serial8250_port serial_platform_data3[] = { |
118 | { | 115 | { |
119 | .membase = OMAP2_IO_ADDRESS(OMAP_UART4_BASE), | ||
120 | .mapbase = OMAP_UART4_BASE, | 116 | .mapbase = OMAP_UART4_BASE, |
121 | .irq = 70, | 117 | .irq = 70, |
122 | .flags = UPF_BOOT_AUTOCONF, | 118 | .flags = UPF_BOOT_AUTOCONF, |
@@ -159,8 +155,6 @@ static inline void __init omap_uart_reset(struct omap_uart_state *uart) | |||
159 | 155 | ||
160 | #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) | 156 | #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) |
161 | 157 | ||
162 | static int enable_off_mode; /* to be removed by full off-mode patches */ | ||
163 | |||
164 | static void omap_uart_save_context(struct omap_uart_state *uart) | 158 | static void omap_uart_save_context(struct omap_uart_state *uart) |
165 | { | 159 | { |
166 | u16 lcr = 0; | 160 | u16 lcr = 0; |
@@ -595,6 +589,16 @@ void __init omap_serial_early_init(void) | |||
595 | struct device *dev = &pdev->dev; | 589 | struct device *dev = &pdev->dev; |
596 | struct plat_serial8250_port *p = dev->platform_data; | 590 | struct plat_serial8250_port *p = dev->platform_data; |
597 | 591 | ||
592 | /* | ||
593 | * Module 4KB + L4 interconnect 4KB | ||
594 | * Static mapping, never released | ||
595 | */ | ||
596 | p->membase = ioremap(p->mapbase, SZ_8K); | ||
597 | if (!p->membase) { | ||
598 | printk(KERN_ERR "ioremap failed for uart%i\n", i + 1); | ||
599 | continue; | ||
600 | } | ||
601 | |||
598 | sprintf(name, "uart%d_ick", i+1); | 602 | sprintf(name, "uart%d_ick", i+1); |
599 | uart->ick = clk_get(NULL, name); | 603 | uart->ick = clk_get(NULL, name); |
600 | if (IS_ERR(uart->ick)) { | 604 | if (IS_ERR(uart->ick)) { |
diff --git a/arch/arm/mach-omap2/sleep24xx.S b/arch/arm/mach-omap2/sleep24xx.S index 130aadbfa083..c7780cc8d919 100644 --- a/arch/arm/mach-omap2/sleep24xx.S +++ b/arch/arm/mach-omap2/sleep24xx.S | |||
@@ -29,7 +29,7 @@ | |||
29 | #include <asm/assembler.h> | 29 | #include <asm/assembler.h> |
30 | #include <mach/io.h> | 30 | #include <mach/io.h> |
31 | 31 | ||
32 | #include <mach/omap24xx.h> | 32 | #include <plat/omap24xx.h> |
33 | 33 | ||
34 | #include "sdrc.h" | 34 | #include "sdrc.h" |
35 | 35 | ||
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index e5e2553e79a6..15268f8b61de 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S | |||
@@ -27,22 +27,35 @@ | |||
27 | #include <linux/linkage.h> | 27 | #include <linux/linkage.h> |
28 | #include <asm/assembler.h> | 28 | #include <asm/assembler.h> |
29 | #include <mach/io.h> | 29 | #include <mach/io.h> |
30 | #include <mach/control.h> | 30 | #include <plat/control.h> |
31 | 31 | ||
32 | #include "cm.h" | ||
32 | #include "prm.h" | 33 | #include "prm.h" |
33 | #include "sdrc.h" | 34 | #include "sdrc.h" |
34 | 35 | ||
35 | #define PM_PREPWSTST_CORE_V OMAP34XX_PRM_REGADDR(CORE_MOD, \ | 36 | #define PM_PREPWSTST_CORE_V OMAP34XX_PRM_REGADDR(CORE_MOD, \ |
36 | OMAP3430_PM_PREPWSTST) | 37 | OMAP3430_PM_PREPWSTST) |
38 | #define PM_PREPWSTST_CORE_P 0x48306AE8 | ||
37 | #define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \ | 39 | #define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \ |
38 | OMAP3430_PM_PREPWSTST) | 40 | OMAP3430_PM_PREPWSTST) |
39 | #define PM_PWSTCTRL_MPU_P OMAP34XX_PRM_REGADDR(MPU_MOD, PM_PWSTCTRL) | 41 | #define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + PM_PWSTCTRL |
42 | #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) | ||
43 | #define SRAM_BASE_P 0x40200000 | ||
44 | #define CONTROL_STAT 0x480022F0 | ||
40 | #define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is | 45 | #define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is |
41 | * available */ | 46 | * available */ |
42 | #define SCRATCHPAD_BASE_P OMAP343X_CTRL_REGADDR(\ | 47 | #define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\ |
43 | OMAP343X_CONTROL_MEM_WKUP +\ | 48 | + SCRATCHPAD_MEM_OFFS) |
44 | SCRATCHPAD_MEM_OFFS) | ||
45 | #define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER) | 49 | #define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER) |
50 | #define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG) | ||
51 | #define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0) | ||
52 | #define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0) | ||
53 | #define SDRC_MANUAL_0_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_0) | ||
54 | #define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1) | ||
55 | #define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1) | ||
56 | #define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1) | ||
57 | #define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) | ||
58 | #define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) | ||
46 | 59 | ||
47 | .text | 60 | .text |
48 | /* Function call to get the restore pointer for resume from OFF */ | 61 | /* Function call to get the restore pointer for resume from OFF */ |
@@ -51,7 +64,93 @@ ENTRY(get_restore_pointer) | |||
51 | adr r0, restore | 64 | adr r0, restore |
52 | ldmfd sp!, {pc} @ restore regs and return | 65 | ldmfd sp!, {pc} @ restore regs and return |
53 | ENTRY(get_restore_pointer_sz) | 66 | ENTRY(get_restore_pointer_sz) |
54 | .word . - get_restore_pointer_sz | 67 | .word . - get_restore_pointer |
68 | |||
69 | .text | ||
70 | /* Function call to get the restore pointer for for ES3 to resume from OFF */ | ||
71 | ENTRY(get_es3_restore_pointer) | ||
72 | stmfd sp!, {lr} @ save registers on stack | ||
73 | adr r0, restore_es3 | ||
74 | ldmfd sp!, {pc} @ restore regs and return | ||
75 | ENTRY(get_es3_restore_pointer_sz) | ||
76 | .word . - get_es3_restore_pointer | ||
77 | |||
78 | ENTRY(es3_sdrc_fix) | ||
79 | ldr r4, sdrc_syscfg @ get config addr | ||
80 | ldr r5, [r4] @ get value | ||
81 | tst r5, #0x100 @ is part access blocked | ||
82 | it eq | ||
83 | biceq r5, r5, #0x100 @ clear bit if set | ||
84 | str r5, [r4] @ write back change | ||
85 | ldr r4, sdrc_mr_0 @ get config addr | ||
86 | ldr r5, [r4] @ get value | ||
87 | str r5, [r4] @ write back change | ||
88 | ldr r4, sdrc_emr2_0 @ get config addr | ||
89 | ldr r5, [r4] @ get value | ||
90 | str r5, [r4] @ write back change | ||
91 | ldr r4, sdrc_manual_0 @ get config addr | ||
92 | mov r5, #0x2 @ autorefresh command | ||
93 | str r5, [r4] @ kick off refreshes | ||
94 | ldr r4, sdrc_mr_1 @ get config addr | ||
95 | ldr r5, [r4] @ get value | ||
96 | str r5, [r4] @ write back change | ||
97 | ldr r4, sdrc_emr2_1 @ get config addr | ||
98 | ldr r5, [r4] @ get value | ||
99 | str r5, [r4] @ write back change | ||
100 | ldr r4, sdrc_manual_1 @ get config addr | ||
101 | mov r5, #0x2 @ autorefresh command | ||
102 | str r5, [r4] @ kick off refreshes | ||
103 | bx lr | ||
104 | sdrc_syscfg: | ||
105 | .word SDRC_SYSCONFIG_P | ||
106 | sdrc_mr_0: | ||
107 | .word SDRC_MR_0_P | ||
108 | sdrc_emr2_0: | ||
109 | .word SDRC_EMR2_0_P | ||
110 | sdrc_manual_0: | ||
111 | .word SDRC_MANUAL_0_P | ||
112 | sdrc_mr_1: | ||
113 | .word SDRC_MR_1_P | ||
114 | sdrc_emr2_1: | ||
115 | .word SDRC_EMR2_1_P | ||
116 | sdrc_manual_1: | ||
117 | .word SDRC_MANUAL_1_P | ||
118 | ENTRY(es3_sdrc_fix_sz) | ||
119 | .word . - es3_sdrc_fix | ||
120 | |||
121 | /* Function to call rom code to save secure ram context */ | ||
122 | ENTRY(save_secure_ram_context) | ||
123 | stmfd sp!, {r1-r12, lr} @ save registers on stack | ||
124 | save_secure_ram_debug: | ||
125 | /* b save_secure_ram_debug */ @ enable to debug save code | ||
126 | adr r3, api_params @ r3 points to parameters | ||
127 | str r0, [r3,#0x4] @ r0 has sdram address | ||
128 | ldr r12, high_mask | ||
129 | and r3, r3, r12 | ||
130 | ldr r12, sram_phy_addr_mask | ||
131 | orr r3, r3, r12 | ||
132 | mov r0, #25 @ set service ID for PPA | ||
133 | mov r12, r0 @ copy secure service ID in r12 | ||
134 | mov r1, #0 @ set task id for ROM code in r1 | ||
135 | mov r2, #4 @ set some flags in r2, r6 | ||
136 | mov r6, #0xff | ||
137 | mcr p15, 0, r0, c7, c10, 4 @ data write barrier | ||
138 | mcr p15, 0, r0, c7, c10, 5 @ data memory barrier | ||
139 | .word 0xE1600071 @ call SMI monitor (smi #1) | ||
140 | nop | ||
141 | nop | ||
142 | nop | ||
143 | nop | ||
144 | ldmfd sp!, {r1-r12, pc} | ||
145 | sram_phy_addr_mask: | ||
146 | .word SRAM_BASE_P | ||
147 | high_mask: | ||
148 | .word 0xffff | ||
149 | api_params: | ||
150 | .word 0x4, 0x0, 0x0, 0x1, 0x1 | ||
151 | ENTRY(save_secure_ram_context_sz) | ||
152 | .word . - save_secure_ram_context | ||
153 | |||
55 | /* | 154 | /* |
56 | * Forces OMAP into idle state | 155 | * Forces OMAP into idle state |
57 | * | 156 | * |
@@ -92,11 +191,29 @@ loop: | |||
92 | nop | 191 | nop |
93 | nop | 192 | nop |
94 | nop | 193 | nop |
95 | bl i_dll_wait | 194 | bl wait_sdrc_ok |
96 | 195 | ||
97 | ldmfd sp!, {r0-r12, pc} @ restore regs and return | 196 | ldmfd sp!, {r0-r12, pc} @ restore regs and return |
197 | restore_es3: | ||
198 | /*b restore_es3*/ @ Enable to debug restore code | ||
199 | ldr r5, pm_prepwstst_core_p | ||
200 | ldr r4, [r5] | ||
201 | and r4, r4, #0x3 | ||
202 | cmp r4, #0x0 @ Check if previous power state of CORE is OFF | ||
203 | bne restore | ||
204 | adr r0, es3_sdrc_fix | ||
205 | ldr r1, sram_base | ||
206 | ldr r2, es3_sdrc_fix_sz | ||
207 | mov r2, r2, ror #2 | ||
208 | copy_to_sram: | ||
209 | ldmia r0!, {r3} @ val = *src | ||
210 | stmia r1!, {r3} @ *dst = val | ||
211 | subs r2, r2, #0x1 @ num_words-- | ||
212 | bne copy_to_sram | ||
213 | ldr r1, sram_base | ||
214 | blx r1 | ||
98 | restore: | 215 | restore: |
99 | /* b restore*/ @ Enable to debug restore code | 216 | /* b restore*/ @ Enable to debug restore code |
100 | /* Check what was the reason for mpu reset and store the reason in r9*/ | 217 | /* Check what was the reason for mpu reset and store the reason in r9*/ |
101 | /* 1 - Only L1 and logic lost */ | 218 | /* 1 - Only L1 and logic lost */ |
102 | /* 2 - Only L2 lost - In this case, we wont be here */ | 219 | /* 2 - Only L2 lost - In this case, we wont be here */ |
@@ -108,9 +225,44 @@ restore: | |||
108 | moveq r9, #0x3 @ MPU OFF => L1 and L2 lost | 225 | moveq r9, #0x3 @ MPU OFF => L1 and L2 lost |
109 | movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation | 226 | movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation |
110 | bne logic_l1_restore | 227 | bne logic_l1_restore |
228 | ldr r0, control_stat | ||
229 | ldr r1, [r0] | ||
230 | and r1, #0x700 | ||
231 | cmp r1, #0x300 | ||
232 | beq l2_inv_gp | ||
233 | mov r0, #40 @ set service ID for PPA | ||
234 | mov r12, r0 @ copy secure Service ID in r12 | ||
235 | mov r1, #0 @ set task id for ROM code in r1 | ||
236 | mov r2, #4 @ set some flags in r2, r6 | ||
237 | mov r6, #0xff | ||
238 | adr r3, l2_inv_api_params @ r3 points to dummy parameters | ||
239 | mcr p15, 0, r0, c7, c10, 4 @ data write barrier | ||
240 | mcr p15, 0, r0, c7, c10, 5 @ data memory barrier | ||
241 | .word 0xE1600071 @ call SMI monitor (smi #1) | ||
242 | /* Write to Aux control register to set some bits */ | ||
243 | mov r0, #42 @ set service ID for PPA | ||
244 | mov r12, r0 @ copy secure Service ID in r12 | ||
245 | mov r1, #0 @ set task id for ROM code in r1 | ||
246 | mov r2, #4 @ set some flags in r2, r6 | ||
247 | mov r6, #0xff | ||
248 | adr r3, write_aux_control_params @ r3 points to parameters | ||
249 | mcr p15, 0, r0, c7, c10, 4 @ data write barrier | ||
250 | mcr p15, 0, r0, c7, c10, 5 @ data memory barrier | ||
251 | .word 0xE1600071 @ call SMI monitor (smi #1) | ||
252 | |||
253 | b logic_l1_restore | ||
254 | l2_inv_api_params: | ||
255 | .word 0x1, 0x00 | ||
256 | write_aux_control_params: | ||
257 | .word 0x1, 0x72 | ||
258 | l2_inv_gp: | ||
111 | /* Execute smi to invalidate L2 cache */ | 259 | /* Execute smi to invalidate L2 cache */ |
112 | mov r12, #0x1 @ set up to invalide L2 | 260 | mov r12, #0x1 @ set up to invalide L2 |
113 | smi: .word 0xE1600070 @ Call SMI monitor (smieq) | 261 | smi: .word 0xE1600070 @ Call SMI monitor (smieq) |
262 | /* Write to Aux control register to set some bits */ | ||
263 | mov r0, #0x72 | ||
264 | mov r12, #0x3 | ||
265 | .word 0xE1600070 @ Call SMI monitor (smieq) | ||
114 | logic_l1_restore: | 266 | logic_l1_restore: |
115 | mov r1, #0 | 267 | mov r1, #0 |
116 | /* Invalidate all instruction caches to PoU | 268 | /* Invalidate all instruction caches to PoU |
@@ -391,33 +543,55 @@ skip_l2_inval: | |||
391 | nop | 543 | nop |
392 | nop | 544 | nop |
393 | nop | 545 | nop |
394 | bl i_dll_wait | 546 | bl wait_sdrc_ok |
395 | /* restore regs and return */ | 547 | /* restore regs and return */ |
396 | ldmfd sp!, {r0-r12, pc} | 548 | ldmfd sp!, {r0-r12, pc} |
397 | 549 | ||
398 | i_dll_wait: | 550 | /* Make sure SDRC accesses are ok */ |
399 | ldr r4, clk_stabilize_delay | 551 | wait_sdrc_ok: |
552 | ldr r4, cm_idlest1_core | ||
553 | ldr r5, [r4] | ||
554 | and r5, r5, #0x2 | ||
555 | cmp r5, #0 | ||
556 | bne wait_sdrc_ok | ||
557 | ldr r4, sdrc_power | ||
558 | ldr r5, [r4] | ||
559 | bic r5, r5, #0x40 | ||
560 | str r5, [r4] | ||
561 | wait_dll_lock: | ||
562 | /* Is dll in lock mode? */ | ||
563 | ldr r4, sdrc_dlla_ctrl | ||
564 | ldr r5, [r4] | ||
565 | tst r5, #0x4 | ||
566 | bxne lr | ||
567 | /* wait till dll locks */ | ||
568 | ldr r4, sdrc_dlla_status | ||
569 | ldr r5, [r4] | ||
570 | and r5, r5, #0x4 | ||
571 | cmp r5, #0x4 | ||
572 | bne wait_dll_lock | ||
573 | bx lr | ||
400 | 574 | ||
401 | i_dll_delay: | 575 | cm_idlest1_core: |
402 | subs r4, r4, #0x1 | 576 | .word CM_IDLEST1_CORE_V |
403 | bne i_dll_delay | 577 | sdrc_dlla_status: |
404 | ldr r4, sdrc_power | 578 | .word SDRC_DLLA_STATUS_V |
405 | ldr r5, [r4] | 579 | sdrc_dlla_ctrl: |
406 | bic r5, r5, #0x40 | 580 | .word SDRC_DLLA_CTRL_V |
407 | str r5, [r4] | ||
408 | bx lr | ||
409 | pm_prepwstst_core: | 581 | pm_prepwstst_core: |
410 | .word PM_PREPWSTST_CORE_V | 582 | .word PM_PREPWSTST_CORE_V |
583 | pm_prepwstst_core_p: | ||
584 | .word PM_PREPWSTST_CORE_P | ||
411 | pm_prepwstst_mpu: | 585 | pm_prepwstst_mpu: |
412 | .word PM_PREPWSTST_MPU_V | 586 | .word PM_PREPWSTST_MPU_V |
413 | pm_pwstctrl_mpu: | 587 | pm_pwstctrl_mpu: |
414 | .word PM_PWSTCTRL_MPU_P | 588 | .word PM_PWSTCTRL_MPU_P |
415 | scratchpad_base: | 589 | scratchpad_base: |
416 | .word SCRATCHPAD_BASE_P | 590 | .word SCRATCHPAD_BASE_P |
591 | sram_base: | ||
592 | .word SRAM_BASE_P + 0x8000 | ||
417 | sdrc_power: | 593 | sdrc_power: |
418 | .word SDRC_POWER_V | 594 | .word SDRC_POWER_V |
419 | context_mem: | ||
420 | .word 0x803E3E14 | ||
421 | clk_stabilize_delay: | 595 | clk_stabilize_delay: |
422 | .word 0x000001FF | 596 | .word 0x000001FF |
423 | assoc_mask: | 597 | assoc_mask: |
@@ -432,5 +606,7 @@ table_entry: | |||
432 | .word 0x00000C02 | 606 | .word 0x00000C02 |
433 | cache_pred_disable_mask: | 607 | cache_pred_disable_mask: |
434 | .word 0xFFFFE7FB | 608 | .word 0xFFFFE7FB |
609 | control_stat: | ||
610 | .word CONTROL_STAT | ||
435 | ENTRY(omap34xx_cpu_suspend_sz) | 611 | ENTRY(omap34xx_cpu_suspend_sz) |
436 | .word . - omap34xx_cpu_suspend | 612 | .word . - omap34xx_cpu_suspend |
diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S index 9b62208658bc..92e6e1a12af8 100644 --- a/arch/arm/mach-omap2/sram242x.S +++ b/arch/arm/mach-omap2/sram242x.S | |||
@@ -128,7 +128,7 @@ omap242x_sdi_prcm_voltctrl: | |||
128 | prcm_mask_val: | 128 | prcm_mask_val: |
129 | .word 0xFFFF3FFC | 129 | .word 0xFFFF3FFC |
130 | omap242x_sdi_timer_32ksynct_cr: | 130 | omap242x_sdi_timer_32ksynct_cr: |
131 | .word OMAP2_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010) | 131 | .word OMAP2_L4_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010) |
132 | ENTRY(omap242x_sram_ddr_init_sz) | 132 | ENTRY(omap242x_sram_ddr_init_sz) |
133 | .word . - omap242x_sram_ddr_init | 133 | .word . - omap242x_sram_ddr_init |
134 | 134 | ||
@@ -224,7 +224,7 @@ omap242x_srs_prcm_voltctrl: | |||
224 | ddr_prcm_mask_val: | 224 | ddr_prcm_mask_val: |
225 | .word 0xFFFF3FFC | 225 | .word 0xFFFF3FFC |
226 | omap242x_srs_timer_32ksynct: | 226 | omap242x_srs_timer_32ksynct: |
227 | .word OMAP2_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010) | 227 | .word OMAP2_L4_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010) |
228 | 228 | ||
229 | ENTRY(omap242x_sram_reprogram_sdrc_sz) | 229 | ENTRY(omap242x_sram_reprogram_sdrc_sz) |
230 | .word . - omap242x_sram_reprogram_sdrc | 230 | .word . - omap242x_sram_reprogram_sdrc |
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S index df2cd9277c00..ab4973695c71 100644 --- a/arch/arm/mach-omap2/sram243x.S +++ b/arch/arm/mach-omap2/sram243x.S | |||
@@ -128,7 +128,7 @@ omap243x_sdi_prcm_voltctrl: | |||
128 | prcm_mask_val: | 128 | prcm_mask_val: |
129 | .word 0xFFFF3FFC | 129 | .word 0xFFFF3FFC |
130 | omap243x_sdi_timer_32ksynct_cr: | 130 | omap243x_sdi_timer_32ksynct_cr: |
131 | .word OMAP2_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010) | 131 | .word OMAP2_L4_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010) |
132 | ENTRY(omap243x_sram_ddr_init_sz) | 132 | ENTRY(omap243x_sram_ddr_init_sz) |
133 | .word . - omap243x_sram_ddr_init | 133 | .word . - omap243x_sram_ddr_init |
134 | 134 | ||
@@ -224,7 +224,7 @@ omap243x_srs_prcm_voltctrl: | |||
224 | ddr_prcm_mask_val: | 224 | ddr_prcm_mask_val: |
225 | .word 0xFFFF3FFC | 225 | .word 0xFFFF3FFC |
226 | omap243x_srs_timer_32ksynct: | 226 | omap243x_srs_timer_32ksynct: |
227 | .word OMAP2_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010) | 227 | .word OMAP2_L4_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010) |
228 | 228 | ||
229 | ENTRY(omap243x_sram_reprogram_sdrc_sz) | 229 | ENTRY(omap243x_sram_reprogram_sdrc_sz) |
230 | .word . - omap243x_sram_reprogram_sdrc | 230 | .word . - omap243x_sram_reprogram_sdrc |
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c index e2338c0aebcf..cd04deaa88c5 100644 --- a/arch/arm/mach-omap2/timer-gp.c +++ b/arch/arm/mach-omap2/timer-gp.c | |||
@@ -37,7 +37,7 @@ | |||
37 | #include <linux/clockchips.h> | 37 | #include <linux/clockchips.h> |
38 | 38 | ||
39 | #include <asm/mach/time.h> | 39 | #include <asm/mach/time.h> |
40 | #include <mach/dmtimer.h> | 40 | #include <plat/dmtimer.h> |
41 | #include <asm/localtimer.h> | 41 | #include <asm/localtimer.h> |
42 | 42 | ||
43 | /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ | 43 | /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ |
@@ -47,6 +47,7 @@ static struct omap_dm_timer *gptimer; | |||
47 | static struct clock_event_device clockevent_gpt; | 47 | static struct clock_event_device clockevent_gpt; |
48 | static u8 __initdata gptimer_id = 1; | 48 | static u8 __initdata gptimer_id = 1; |
49 | static u8 __initdata inited; | 49 | static u8 __initdata inited; |
50 | struct omap_dm_timer *gptimer_wakeup; | ||
50 | 51 | ||
51 | static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) | 52 | static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) |
52 | { | 53 | { |
@@ -134,6 +135,7 @@ static void __init omap2_gp_clockevent_init(void) | |||
134 | 135 | ||
135 | gptimer = omap_dm_timer_request_specific(gptimer_id); | 136 | gptimer = omap_dm_timer_request_specific(gptimer_id); |
136 | BUG_ON(gptimer == NULL); | 137 | BUG_ON(gptimer == NULL); |
138 | gptimer_wakeup = gptimer; | ||
137 | 139 | ||
138 | #if defined(CONFIG_OMAP_32K_TIMER) | 140 | #if defined(CONFIG_OMAP_32K_TIMER) |
139 | src = OMAP_TIMER_SRC_32_KHZ; | 141 | src = OMAP_TIMER_SRC_32_KHZ; |
@@ -231,7 +233,8 @@ static void __init omap2_gp_clocksource_init(void) | |||
231 | static void __init omap2_gp_timer_init(void) | 233 | static void __init omap2_gp_timer_init(void) |
232 | { | 234 | { |
233 | #ifdef CONFIG_LOCAL_TIMERS | 235 | #ifdef CONFIG_LOCAL_TIMERS |
234 | twd_base = OMAP2_IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE); | 236 | twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256); |
237 | BUG_ON(!twd_base); | ||
235 | #endif | 238 | #endif |
236 | omap_dm_timer_init(); | 239 | omap_dm_timer_init(); |
237 | 240 | ||
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index 1145a2562b0f..a80441dd19b8 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c | |||
@@ -28,8 +28,8 @@ | |||
28 | 28 | ||
29 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
30 | #include <mach/irqs.h> | 30 | #include <mach/irqs.h> |
31 | #include <mach/mux.h> | 31 | #include <plat/mux.h> |
32 | #include <mach/usb.h> | 32 | #include <plat/usb.h> |
33 | 33 | ||
34 | #ifdef CONFIG_USB_MUSB_SOC | 34 | #ifdef CONFIG_USB_MUSB_SOC |
35 | 35 | ||
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c index 8622c24cd270..10a2013c1104 100644 --- a/arch/arm/mach-omap2/usb-tusb6010.c +++ b/arch/arm/mach-omap2/usb-tusb6010.c | |||
@@ -16,8 +16,8 @@ | |||
16 | 16 | ||
17 | #include <linux/usb/musb.h> | 17 | #include <linux/usb/musb.h> |
18 | 18 | ||
19 | #include <mach/gpmc.h> | 19 | #include <plat/gpmc.h> |
20 | #include <mach/mux.h> | 20 | #include <plat/mux.h> |
21 | 21 | ||
22 | 22 | ||
23 | static u8 async_cs, sync_cs; | 23 | static u8 async_cs, sync_cs; |
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index bf880e966d3b..681bfc37ebb2 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c | |||
@@ -24,7 +24,7 @@ | |||
24 | #include <linux/debugfs.h> | 24 | #include <linux/debugfs.h> |
25 | #include <linux/io.h> | 25 | #include <linux/io.h> |
26 | 26 | ||
27 | #include <mach/clock.h> | 27 | #include <plat/clock.h> |
28 | 28 | ||
29 | static LIST_HEAD(clocks); | 29 | static LIST_HEAD(clocks); |
30 | static DEFINE_MUTEX(clocks_mutex); | 30 | static DEFINE_MUTEX(clocks_mutex); |
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index 3a4768d55895..cc050b3313bd 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c | |||
@@ -29,13 +29,13 @@ | |||
29 | #include <asm/mach/map.h> | 29 | #include <asm/mach/map.h> |
30 | #include <asm/setup.h> | 30 | #include <asm/setup.h> |
31 | 31 | ||
32 | #include <mach/common.h> | 32 | #include <plat/common.h> |
33 | #include <mach/board.h> | 33 | #include <plat/board.h> |
34 | #include <mach/control.h> | 34 | #include <plat/control.h> |
35 | #include <mach/mux.h> | 35 | #include <plat/mux.h> |
36 | #include <mach/fpga.h> | 36 | #include <plat/fpga.h> |
37 | 37 | ||
38 | #include <mach/clock.h> | 38 | #include <plat/clock.h> |
39 | 39 | ||
40 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) | 40 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
41 | # include "../mach-omap2/sdrc.h" | 41 | # include "../mach-omap2/sdrc.h" |
@@ -49,6 +49,9 @@ int omap_bootloader_tag_len; | |||
49 | struct omap_board_config_kernel *omap_board_config; | 49 | struct omap_board_config_kernel *omap_board_config; |
50 | int omap_board_config_size; | 50 | int omap_board_config_size; |
51 | 51 | ||
52 | /* used by omap-smp.c and board-4430sdp.c */ | ||
53 | void __iomem *gic_cpu_base_addr; | ||
54 | |||
52 | static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out) | 55 | static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out) |
53 | { | 56 | { |
54 | struct omap_board_config_kernel *kinfo = NULL; | 57 | struct omap_board_config_kernel *kinfo = NULL; |
@@ -224,12 +227,12 @@ static void __init __omap2_set_globals(struct omap_globals *omap2_globals) | |||
224 | 227 | ||
225 | static struct omap_globals omap242x_globals = { | 228 | static struct omap_globals omap242x_globals = { |
226 | .class = OMAP242X_CLASS, | 229 | .class = OMAP242X_CLASS, |
227 | .tap = OMAP2_IO_ADDRESS(0x48014000), | 230 | .tap = OMAP2_L4_IO_ADDRESS(0x48014000), |
228 | .sdrc = OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE), | 231 | .sdrc = OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE), |
229 | .sms = OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE), | 232 | .sms = OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE), |
230 | .ctrl = OMAP2_IO_ADDRESS(OMAP2420_CTRL_BASE), | 233 | .ctrl = OMAP2_L4_IO_ADDRESS(OMAP2420_CTRL_BASE), |
231 | .prm = OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE), | 234 | .prm = OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE), |
232 | .cm = OMAP2_IO_ADDRESS(OMAP2420_CM_BASE), | 235 | .cm = OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), |
233 | }; | 236 | }; |
234 | 237 | ||
235 | void __init omap2_set_globals_242x(void) | 238 | void __init omap2_set_globals_242x(void) |
@@ -242,12 +245,12 @@ void __init omap2_set_globals_242x(void) | |||
242 | 245 | ||
243 | static struct omap_globals omap243x_globals = { | 246 | static struct omap_globals omap243x_globals = { |
244 | .class = OMAP243X_CLASS, | 247 | .class = OMAP243X_CLASS, |
245 | .tap = OMAP2_IO_ADDRESS(0x4900a000), | 248 | .tap = OMAP2_L4_IO_ADDRESS(0x4900a000), |
246 | .sdrc = OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE), | 249 | .sdrc = OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE), |
247 | .sms = OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE), | 250 | .sms = OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE), |
248 | .ctrl = OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE), | 251 | .ctrl = OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE), |
249 | .prm = OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE), | 252 | .prm = OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE), |
250 | .cm = OMAP2_IO_ADDRESS(OMAP2430_CM_BASE), | 253 | .cm = OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), |
251 | }; | 254 | }; |
252 | 255 | ||
253 | void __init omap2_set_globals_243x(void) | 256 | void __init omap2_set_globals_243x(void) |
@@ -260,12 +263,12 @@ void __init omap2_set_globals_243x(void) | |||
260 | 263 | ||
261 | static struct omap_globals omap343x_globals = { | 264 | static struct omap_globals omap343x_globals = { |
262 | .class = OMAP343X_CLASS, | 265 | .class = OMAP343X_CLASS, |
263 | .tap = OMAP2_IO_ADDRESS(0x4830A000), | 266 | .tap = OMAP2_L4_IO_ADDRESS(0x4830A000), |
264 | .sdrc = OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE), | 267 | .sdrc = OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), |
265 | .sms = OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE), | 268 | .sms = OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE), |
266 | .ctrl = OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE), | 269 | .ctrl = OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE), |
267 | .prm = OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE), | 270 | .prm = OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE), |
268 | .cm = OMAP2_IO_ADDRESS(OMAP3430_CM_BASE), | 271 | .cm = OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), |
269 | }; | 272 | }; |
270 | 273 | ||
271 | void __init omap2_set_globals_343x(void) | 274 | void __init omap2_set_globals_343x(void) |
@@ -277,10 +280,10 @@ void __init omap2_set_globals_343x(void) | |||
277 | #if defined(CONFIG_ARCH_OMAP4) | 280 | #if defined(CONFIG_ARCH_OMAP4) |
278 | static struct omap_globals omap4_globals = { | 281 | static struct omap_globals omap4_globals = { |
279 | .class = OMAP443X_CLASS, | 282 | .class = OMAP443X_CLASS, |
280 | .tap = OMAP2_IO_ADDRESS(0x4830a000), | 283 | .tap = OMAP2_L4_IO_ADDRESS(0x4830a000), |
281 | .ctrl = OMAP2_IO_ADDRESS(OMAP443X_CTRL_BASE), | 284 | .ctrl = OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE), |
282 | .prm = OMAP2_IO_ADDRESS(OMAP4430_PRM_BASE), | 285 | .prm = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE), |
283 | .cm = OMAP2_IO_ADDRESS(OMAP4430_CM_BASE), | 286 | .cm = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE), |
284 | }; | 287 | }; |
285 | 288 | ||
286 | void __init omap2_set_globals_443x(void) | 289 | void __init omap2_set_globals_443x(void) |
diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c index 341235c278ac..f8ddbdd8b076 100644 --- a/arch/arm/plat-omap/cpu-omap.c +++ b/arch/arm/plat-omap/cpu-omap.c | |||
@@ -23,7 +23,7 @@ | |||
23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
24 | 24 | ||
25 | #include <mach/hardware.h> | 25 | #include <mach/hardware.h> |
26 | #include <mach/clock.h> | 26 | #include <plat/clock.h> |
27 | #include <asm/system.h> | 27 | #include <asm/system.h> |
28 | 28 | ||
29 | #define VERY_HI_RATE 900000000 | 29 | #define VERY_HI_RATE 900000000 |
diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c index f6684832ca8f..09c1107637f6 100644 --- a/arch/arm/plat-omap/debug-devices.c +++ b/arch/arm/plat-omap/debug-devices.c | |||
@@ -16,7 +16,7 @@ | |||
16 | 16 | ||
17 | #include <mach/hardware.h> | 17 | #include <mach/hardware.h> |
18 | 18 | ||
19 | #include <mach/board.h> | 19 | #include <plat/board.h> |
20 | #include <mach/gpio.h> | 20 | #include <mach/gpio.h> |
21 | 21 | ||
22 | 22 | ||
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c index 9395898dd49a..6c768b71ad64 100644 --- a/arch/arm/plat-omap/debug-leds.c +++ b/arch/arm/plat-omap/debug-leds.c | |||
@@ -18,7 +18,7 @@ | |||
18 | #include <asm/system.h> | 18 | #include <asm/system.h> |
19 | #include <asm/mach-types.h> | 19 | #include <asm/mach-types.h> |
20 | 20 | ||
21 | #include <mach/fpga.h> | 21 | #include <plat/fpga.h> |
22 | #include <mach/gpio.h> | 22 | #include <mach/gpio.h> |
23 | 23 | ||
24 | 24 | ||
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c index a64b692a1bfe..f86617869b38 100644 --- a/arch/arm/plat-omap/devices.c +++ b/arch/arm/plat-omap/devices.c | |||
@@ -19,15 +19,15 @@ | |||
19 | #include <asm/mach-types.h> | 19 | #include <asm/mach-types.h> |
20 | #include <asm/mach/map.h> | 20 | #include <asm/mach/map.h> |
21 | 21 | ||
22 | #include <mach/tc.h> | 22 | #include <plat/tc.h> |
23 | #include <mach/control.h> | 23 | #include <plat/control.h> |
24 | #include <mach/board.h> | 24 | #include <plat/board.h> |
25 | #include <mach/mmc.h> | 25 | #include <plat/mmc.h> |
26 | #include <mach/mux.h> | 26 | #include <plat/mux.h> |
27 | #include <mach/gpio.h> | 27 | #include <mach/gpio.h> |
28 | #include <mach/menelaus.h> | 28 | #include <plat/menelaus.h> |
29 | #include <mach/mcbsp.h> | 29 | #include <plat/mcbsp.h> |
30 | #include <mach/dsp_common.h> | 30 | #include <plat/dsp_common.h> |
31 | 31 | ||
32 | #if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) | 32 | #if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) |
33 | 33 | ||
@@ -113,17 +113,17 @@ static void omap_init_kp(void) | |||
113 | omap_cfg_reg(E19_1610_KBR4); | 113 | omap_cfg_reg(E19_1610_KBR4); |
114 | omap_cfg_reg(N19_1610_KBR5); | 114 | omap_cfg_reg(N19_1610_KBR5); |
115 | } else if (machine_is_omap_perseus2() || machine_is_omap_fsample()) { | 115 | } else if (machine_is_omap_perseus2() || machine_is_omap_fsample()) { |
116 | omap_cfg_reg(E2_730_KBR0); | 116 | omap_cfg_reg(E2_7XX_KBR0); |
117 | omap_cfg_reg(J7_730_KBR1); | 117 | omap_cfg_reg(J7_7XX_KBR1); |
118 | omap_cfg_reg(E1_730_KBR2); | 118 | omap_cfg_reg(E1_7XX_KBR2); |
119 | omap_cfg_reg(F3_730_KBR3); | 119 | omap_cfg_reg(F3_7XX_KBR3); |
120 | omap_cfg_reg(D2_730_KBR4); | 120 | omap_cfg_reg(D2_7XX_KBR4); |
121 | 121 | ||
122 | omap_cfg_reg(C2_730_KBC0); | 122 | omap_cfg_reg(C2_7XX_KBC0); |
123 | omap_cfg_reg(D3_730_KBC1); | 123 | omap_cfg_reg(D3_7XX_KBC1); |
124 | omap_cfg_reg(E4_730_KBC2); | 124 | omap_cfg_reg(E4_7XX_KBC2); |
125 | omap_cfg_reg(F4_730_KBC3); | 125 | omap_cfg_reg(F4_7XX_KBC3); |
126 | omap_cfg_reg(E3_730_KBC4); | 126 | omap_cfg_reg(E3_7XX_KBC4); |
127 | } else if (machine_is_omap_h4()) { | 127 | } else if (machine_is_omap_h4()) { |
128 | omap_cfg_reg(T19_24XX_KBR0); | 128 | omap_cfg_reg(T19_24XX_KBR0); |
129 | omap_cfg_reg(R19_24XX_KBR1); | 129 | omap_cfg_reg(R19_24XX_KBR1); |
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 68eaae324b6a..be4ce070fb4c 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c | |||
@@ -32,9 +32,9 @@ | |||
32 | 32 | ||
33 | #include <asm/system.h> | 33 | #include <asm/system.h> |
34 | #include <mach/hardware.h> | 34 | #include <mach/hardware.h> |
35 | #include <mach/dma.h> | 35 | #include <plat/dma.h> |
36 | 36 | ||
37 | #include <mach/tc.h> | 37 | #include <plat/tc.h> |
38 | 38 | ||
39 | #undef DEBUG | 39 | #undef DEBUG |
40 | 40 | ||
@@ -54,6 +54,12 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED }; | |||
54 | 54 | ||
55 | static int enable_1510_mode; | 55 | static int enable_1510_mode; |
56 | 56 | ||
57 | static struct omap_dma_global_context_registers { | ||
58 | u32 dma_irqenable_l0; | ||
59 | u32 dma_ocp_sysconfig; | ||
60 | u32 dma_gcr; | ||
61 | } omap_dma_global_context; | ||
62 | |||
57 | struct omap_dma_lch { | 63 | struct omap_dma_lch { |
58 | int next_lch; | 64 | int next_lch; |
59 | int dev_id; | 65 | int dev_id; |
@@ -2355,44 +2361,83 @@ void omap_stop_lcd_dma(void) | |||
2355 | } | 2361 | } |
2356 | EXPORT_SYMBOL(omap_stop_lcd_dma); | 2362 | EXPORT_SYMBOL(omap_stop_lcd_dma); |
2357 | 2363 | ||
2364 | void omap_dma_global_context_save(void) | ||
2365 | { | ||
2366 | omap_dma_global_context.dma_irqenable_l0 = | ||
2367 | dma_read(IRQENABLE_L0); | ||
2368 | omap_dma_global_context.dma_ocp_sysconfig = | ||
2369 | dma_read(OCP_SYSCONFIG); | ||
2370 | omap_dma_global_context.dma_gcr = dma_read(GCR); | ||
2371 | } | ||
2372 | |||
2373 | void omap_dma_global_context_restore(void) | ||
2374 | { | ||
2375 | int ch; | ||
2376 | |||
2377 | dma_write(omap_dma_global_context.dma_gcr, GCR); | ||
2378 | dma_write(omap_dma_global_context.dma_ocp_sysconfig, | ||
2379 | OCP_SYSCONFIG); | ||
2380 | dma_write(omap_dma_global_context.dma_irqenable_l0, | ||
2381 | IRQENABLE_L0); | ||
2382 | |||
2383 | /* | ||
2384 | * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared | ||
2385 | * after secure sram context save and restore. Hence we need to | ||
2386 | * manually clear those IRQs to avoid spurious interrupts. This | ||
2387 | * affects only secure devices. | ||
2388 | */ | ||
2389 | if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) | ||
2390 | dma_write(0x3 , IRQSTATUS_L0); | ||
2391 | |||
2392 | for (ch = 0; ch < dma_chan_count; ch++) | ||
2393 | if (dma_chan[ch].dev_id != -1) | ||
2394 | omap_clear_dma(ch); | ||
2395 | } | ||
2396 | |||
2358 | /*----------------------------------------------------------------------------*/ | 2397 | /*----------------------------------------------------------------------------*/ |
2359 | 2398 | ||
2360 | static int __init omap_init_dma(void) | 2399 | static int __init omap_init_dma(void) |
2361 | { | 2400 | { |
2401 | unsigned long base; | ||
2362 | int ch, r; | 2402 | int ch, r; |
2363 | 2403 | ||
2364 | if (cpu_class_is_omap1()) { | 2404 | if (cpu_class_is_omap1()) { |
2365 | omap_dma_base = OMAP1_IO_ADDRESS(OMAP1_DMA_BASE); | 2405 | base = OMAP1_DMA_BASE; |
2366 | dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT; | 2406 | dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT; |
2367 | } else if (cpu_is_omap24xx()) { | 2407 | } else if (cpu_is_omap24xx()) { |
2368 | omap_dma_base = OMAP2_IO_ADDRESS(OMAP24XX_DMA4_BASE); | 2408 | base = OMAP24XX_DMA4_BASE; |
2369 | dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; | 2409 | dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; |
2370 | } else if (cpu_is_omap34xx()) { | 2410 | } else if (cpu_is_omap34xx()) { |
2371 | omap_dma_base = OMAP2_IO_ADDRESS(OMAP34XX_DMA4_BASE); | 2411 | base = OMAP34XX_DMA4_BASE; |
2372 | dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; | 2412 | dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; |
2373 | } else if (cpu_is_omap44xx()) { | 2413 | } else if (cpu_is_omap44xx()) { |
2374 | omap_dma_base = OMAP2_IO_ADDRESS(OMAP44XX_DMA4_BASE); | 2414 | base = OMAP44XX_DMA4_BASE; |
2375 | dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; | 2415 | dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; |
2376 | } else { | 2416 | } else { |
2377 | pr_err("DMA init failed for unsupported omap\n"); | 2417 | pr_err("DMA init failed for unsupported omap\n"); |
2378 | return -ENODEV; | 2418 | return -ENODEV; |
2379 | } | 2419 | } |
2380 | 2420 | ||
2421 | omap_dma_base = ioremap(base, SZ_4K); | ||
2422 | BUG_ON(!omap_dma_base); | ||
2423 | |||
2381 | if (cpu_class_is_omap2() && omap_dma_reserve_channels | 2424 | if (cpu_class_is_omap2() && omap_dma_reserve_channels |
2382 | && (omap_dma_reserve_channels <= dma_lch_count)) | 2425 | && (omap_dma_reserve_channels <= dma_lch_count)) |
2383 | dma_lch_count = omap_dma_reserve_channels; | 2426 | dma_lch_count = omap_dma_reserve_channels; |
2384 | 2427 | ||
2385 | dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count, | 2428 | dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count, |
2386 | GFP_KERNEL); | 2429 | GFP_KERNEL); |
2387 | if (!dma_chan) | 2430 | if (!dma_chan) { |
2388 | return -ENOMEM; | 2431 | r = -ENOMEM; |
2432 | goto out_unmap; | ||
2433 | } | ||
2389 | 2434 | ||
2390 | if (cpu_class_is_omap2()) { | 2435 | if (cpu_class_is_omap2()) { |
2391 | dma_linked_lch = kzalloc(sizeof(struct dma_link_info) * | 2436 | dma_linked_lch = kzalloc(sizeof(struct dma_link_info) * |
2392 | dma_lch_count, GFP_KERNEL); | 2437 | dma_lch_count, GFP_KERNEL); |
2393 | if (!dma_linked_lch) { | 2438 | if (!dma_linked_lch) { |
2394 | kfree(dma_chan); | 2439 | r = -ENOMEM; |
2395 | return -ENOMEM; | 2440 | goto out_free; |
2396 | } | 2441 | } |
2397 | } | 2442 | } |
2398 | 2443 | ||
@@ -2466,7 +2511,7 @@ static int __init omap_init_dma(void) | |||
2466 | for (i = 0; i < ch; i++) | 2511 | for (i = 0; i < ch; i++) |
2467 | free_irq(omap1_dma_irq[i], | 2512 | free_irq(omap1_dma_irq[i], |
2468 | (void *) (i + 1)); | 2513 | (void *) (i + 1)); |
2469 | return r; | 2514 | goto out_free; |
2470 | } | 2515 | } |
2471 | } | 2516 | } |
2472 | } | 2517 | } |
@@ -2484,8 +2529,8 @@ static int __init omap_init_dma(void) | |||
2484 | setup_irq(irq, &omap24xx_dma_irq); | 2529 | setup_irq(irq, &omap24xx_dma_irq); |
2485 | } | 2530 | } |
2486 | 2531 | ||
2487 | /* Enable smartidle idlemodes and autoidle */ | ||
2488 | if (cpu_is_omap34xx()) { | 2532 | if (cpu_is_omap34xx()) { |
2533 | /* Enable smartidle idlemodes and autoidle */ | ||
2489 | u32 v = dma_read(OCP_SYSCONFIG); | 2534 | u32 v = dma_read(OCP_SYSCONFIG); |
2490 | v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK | | 2535 | v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK | |
2491 | DMA_SYSCONFIG_SIDLEMODE_MASK | | 2536 | DMA_SYSCONFIG_SIDLEMODE_MASK | |
@@ -2494,6 +2539,13 @@ static int __init omap_init_dma(void) | |||
2494 | DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) | | 2539 | DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) | |
2495 | DMA_SYSCONFIG_AUTOIDLE); | 2540 | DMA_SYSCONFIG_AUTOIDLE); |
2496 | dma_write(v , OCP_SYSCONFIG); | 2541 | dma_write(v , OCP_SYSCONFIG); |
2542 | /* reserve dma channels 0 and 1 in high security devices */ | ||
2543 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { | ||
2544 | printk(KERN_INFO "Reserving DMA channels 0 and 1 for " | ||
2545 | "HS ROM code\n"); | ||
2546 | dma_chan[0].dev_id = 0; | ||
2547 | dma_chan[1].dev_id = 1; | ||
2548 | } | ||
2497 | } | 2549 | } |
2498 | 2550 | ||
2499 | 2551 | ||
@@ -2508,11 +2560,19 @@ static int __init omap_init_dma(void) | |||
2508 | "(error %d)\n", r); | 2560 | "(error %d)\n", r); |
2509 | for (i = 0; i < dma_chan_count; i++) | 2561 | for (i = 0; i < dma_chan_count; i++) |
2510 | free_irq(omap1_dma_irq[i], (void *) (i + 1)); | 2562 | free_irq(omap1_dma_irq[i], (void *) (i + 1)); |
2511 | return r; | 2563 | goto out_free; |
2512 | } | 2564 | } |
2513 | } | 2565 | } |
2514 | 2566 | ||
2515 | return 0; | 2567 | return 0; |
2568 | |||
2569 | out_free: | ||
2570 | kfree(dma_chan); | ||
2571 | |||
2572 | out_unmap: | ||
2573 | iounmap(omap_dma_base); | ||
2574 | |||
2575 | return r; | ||
2516 | } | 2576 | } |
2517 | 2577 | ||
2518 | arch_initcall(omap_init_dma); | 2578 | arch_initcall(omap_init_dma); |
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index d325b54daeb5..64f407ee0f4e 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c | |||
@@ -38,7 +38,7 @@ | |||
38 | #include <linux/io.h> | 38 | #include <linux/io.h> |
39 | #include <linux/module.h> | 39 | #include <linux/module.h> |
40 | #include <mach/hardware.h> | 40 | #include <mach/hardware.h> |
41 | #include <mach/dmtimer.h> | 41 | #include <plat/dmtimer.h> |
42 | #include <mach/irqs.h> | 42 | #include <mach/irqs.h> |
43 | 43 | ||
44 | /* register offsets */ | 44 | /* register offsets */ |
@@ -742,16 +742,17 @@ EXPORT_SYMBOL_GPL(omap_dm_timers_active); | |||
742 | int __init omap_dm_timer_init(void) | 742 | int __init omap_dm_timer_init(void) |
743 | { | 743 | { |
744 | struct omap_dm_timer *timer; | 744 | struct omap_dm_timer *timer; |
745 | int i; | 745 | int i, map_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */ |
746 | 746 | ||
747 | if (!(cpu_is_omap16xx() || cpu_class_is_omap2())) | 747 | if (!(cpu_is_omap16xx() || cpu_class_is_omap2())) |
748 | return -ENODEV; | 748 | return -ENODEV; |
749 | 749 | ||
750 | spin_lock_init(&dm_timer_lock); | 750 | spin_lock_init(&dm_timer_lock); |
751 | 751 | ||
752 | if (cpu_class_is_omap1()) | 752 | if (cpu_class_is_omap1()) { |
753 | dm_timers = omap1_dm_timers; | 753 | dm_timers = omap1_dm_timers; |
754 | else if (cpu_is_omap24xx()) { | 754 | map_size = SZ_2K; |
755 | } else if (cpu_is_omap24xx()) { | ||
755 | dm_timers = omap2_dm_timers; | 756 | dm_timers = omap2_dm_timers; |
756 | dm_source_names = omap2_dm_source_names; | 757 | dm_source_names = omap2_dm_source_names; |
757 | dm_source_clocks = omap2_dm_source_clocks; | 758 | dm_source_clocks = omap2_dm_source_clocks; |
@@ -774,10 +775,11 @@ int __init omap_dm_timer_init(void) | |||
774 | 775 | ||
775 | for (i = 0; i < dm_timer_count; i++) { | 776 | for (i = 0; i < dm_timer_count; i++) { |
776 | timer = &dm_timers[i]; | 777 | timer = &dm_timers[i]; |
777 | if (cpu_class_is_omap1()) | 778 | |
778 | timer->io_base = OMAP1_IO_ADDRESS(timer->phys_base); | 779 | /* Static mapping, never released */ |
779 | else | 780 | timer->io_base = ioremap(timer->phys_base, map_size); |
780 | timer->io_base = OMAP2_IO_ADDRESS(timer->phys_base); | 781 | BUG_ON(!timer->io_base); |
782 | |||
781 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ | 783 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ |
782 | defined(CONFIG_ARCH_OMAP4) | 784 | defined(CONFIG_ARCH_OMAP4) |
783 | if (cpu_class_is_omap2()) { | 785 | if (cpu_class_is_omap2()) { |
diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c index 3746222bed10..78a4ce538dbd 100644 --- a/arch/arm/plat-omap/fb.c +++ b/arch/arm/plat-omap/fb.c | |||
@@ -32,9 +32,9 @@ | |||
32 | #include <mach/hardware.h> | 32 | #include <mach/hardware.h> |
33 | #include <asm/mach/map.h> | 33 | #include <asm/mach/map.h> |
34 | 34 | ||
35 | #include <mach/board.h> | 35 | #include <plat/board.h> |
36 | #include <mach/sram.h> | 36 | #include <plat/sram.h> |
37 | #include <mach/omapfb.h> | 37 | #include <plat/omapfb.h> |
38 | 38 | ||
39 | #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE) | 39 | #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE) |
40 | 40 | ||
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 7c345b757df1..4f81ea35b733 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c | |||
@@ -31,7 +31,7 @@ | |||
31 | /* | 31 | /* |
32 | * OMAP1510 GPIO registers | 32 | * OMAP1510 GPIO registers |
33 | */ | 33 | */ |
34 | #define OMAP1510_GPIO_BASE OMAP1_IO_ADDRESS(0xfffce000) | 34 | #define OMAP1510_GPIO_BASE 0xfffce000 |
35 | #define OMAP1510_GPIO_DATA_INPUT 0x00 | 35 | #define OMAP1510_GPIO_DATA_INPUT 0x00 |
36 | #define OMAP1510_GPIO_DATA_OUTPUT 0x04 | 36 | #define OMAP1510_GPIO_DATA_OUTPUT 0x04 |
37 | #define OMAP1510_GPIO_DIR_CONTROL 0x08 | 37 | #define OMAP1510_GPIO_DIR_CONTROL 0x08 |
@@ -45,10 +45,10 @@ | |||
45 | /* | 45 | /* |
46 | * OMAP1610 specific GPIO registers | 46 | * OMAP1610 specific GPIO registers |
47 | */ | 47 | */ |
48 | #define OMAP1610_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbe400) | 48 | #define OMAP1610_GPIO1_BASE 0xfffbe400 |
49 | #define OMAP1610_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbec00) | 49 | #define OMAP1610_GPIO2_BASE 0xfffbec00 |
50 | #define OMAP1610_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbb400) | 50 | #define OMAP1610_GPIO3_BASE 0xfffbb400 |
51 | #define OMAP1610_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbbc00) | 51 | #define OMAP1610_GPIO4_BASE 0xfffbbc00 |
52 | #define OMAP1610_GPIO_REVISION 0x0000 | 52 | #define OMAP1610_GPIO_REVISION 0x0000 |
53 | #define OMAP1610_GPIO_SYSCONFIG 0x0010 | 53 | #define OMAP1610_GPIO_SYSCONFIG 0x0010 |
54 | #define OMAP1610_GPIO_SYSSTATUS 0x0014 | 54 | #define OMAP1610_GPIO_SYSSTATUS 0x0014 |
@@ -68,52 +68,36 @@ | |||
68 | #define OMAP1610_GPIO_SET_DATAOUT 0x00f0 | 68 | #define OMAP1610_GPIO_SET_DATAOUT 0x00f0 |
69 | 69 | ||
70 | /* | 70 | /* |
71 | * OMAP730 specific GPIO registers | 71 | * OMAP7XX specific GPIO registers |
72 | */ | 72 | */ |
73 | #define OMAP730_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000) | 73 | #define OMAP7XX_GPIO1_BASE 0xfffbc000 |
74 | #define OMAP730_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800) | 74 | #define OMAP7XX_GPIO2_BASE 0xfffbc800 |
75 | #define OMAP730_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000) | 75 | #define OMAP7XX_GPIO3_BASE 0xfffbd000 |
76 | #define OMAP730_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800) | 76 | #define OMAP7XX_GPIO4_BASE 0xfffbd800 |
77 | #define OMAP730_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000) | 77 | #define OMAP7XX_GPIO5_BASE 0xfffbe000 |
78 | #define OMAP730_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800) | 78 | #define OMAP7XX_GPIO6_BASE 0xfffbe800 |
79 | #define OMAP730_GPIO_DATA_INPUT 0x00 | 79 | #define OMAP7XX_GPIO_DATA_INPUT 0x00 |
80 | #define OMAP730_GPIO_DATA_OUTPUT 0x04 | 80 | #define OMAP7XX_GPIO_DATA_OUTPUT 0x04 |
81 | #define OMAP730_GPIO_DIR_CONTROL 0x08 | 81 | #define OMAP7XX_GPIO_DIR_CONTROL 0x08 |
82 | #define OMAP730_GPIO_INT_CONTROL 0x0c | 82 | #define OMAP7XX_GPIO_INT_CONTROL 0x0c |
83 | #define OMAP730_GPIO_INT_MASK 0x10 | 83 | #define OMAP7XX_GPIO_INT_MASK 0x10 |
84 | #define OMAP730_GPIO_INT_STATUS 0x14 | 84 | #define OMAP7XX_GPIO_INT_STATUS 0x14 |
85 | 85 | ||
86 | /* | 86 | #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE |
87 | * OMAP850 specific GPIO registers | ||
88 | */ | ||
89 | #define OMAP850_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000) | ||
90 | #define OMAP850_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800) | ||
91 | #define OMAP850_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000) | ||
92 | #define OMAP850_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800) | ||
93 | #define OMAP850_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000) | ||
94 | #define OMAP850_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800) | ||
95 | #define OMAP850_GPIO_DATA_INPUT 0x00 | ||
96 | #define OMAP850_GPIO_DATA_OUTPUT 0x04 | ||
97 | #define OMAP850_GPIO_DIR_CONTROL 0x08 | ||
98 | #define OMAP850_GPIO_INT_CONTROL 0x0c | ||
99 | #define OMAP850_GPIO_INT_MASK 0x10 | ||
100 | #define OMAP850_GPIO_INT_STATUS 0x14 | ||
101 | |||
102 | #define OMAP1_MPUIO_VBASE OMAP1_IO_ADDRESS(OMAP1_MPUIO_BASE) | ||
103 | 87 | ||
104 | /* | 88 | /* |
105 | * omap24xx specific GPIO registers | 89 | * omap24xx specific GPIO registers |
106 | */ | 90 | */ |
107 | #define OMAP242X_GPIO1_BASE OMAP2_IO_ADDRESS(0x48018000) | 91 | #define OMAP242X_GPIO1_BASE 0x48018000 |
108 | #define OMAP242X_GPIO2_BASE OMAP2_IO_ADDRESS(0x4801a000) | 92 | #define OMAP242X_GPIO2_BASE 0x4801a000 |
109 | #define OMAP242X_GPIO3_BASE OMAP2_IO_ADDRESS(0x4801c000) | 93 | #define OMAP242X_GPIO3_BASE 0x4801c000 |
110 | #define OMAP242X_GPIO4_BASE OMAP2_IO_ADDRESS(0x4801e000) | 94 | #define OMAP242X_GPIO4_BASE 0x4801e000 |
111 | 95 | ||
112 | #define OMAP243X_GPIO1_BASE OMAP2_IO_ADDRESS(0x4900C000) | 96 | #define OMAP243X_GPIO1_BASE 0x4900C000 |
113 | #define OMAP243X_GPIO2_BASE OMAP2_IO_ADDRESS(0x4900E000) | 97 | #define OMAP243X_GPIO2_BASE 0x4900E000 |
114 | #define OMAP243X_GPIO3_BASE OMAP2_IO_ADDRESS(0x49010000) | 98 | #define OMAP243X_GPIO3_BASE 0x49010000 |
115 | #define OMAP243X_GPIO4_BASE OMAP2_IO_ADDRESS(0x49012000) | 99 | #define OMAP243X_GPIO4_BASE 0x49012000 |
116 | #define OMAP243X_GPIO5_BASE OMAP2_IO_ADDRESS(0x480B6000) | 100 | #define OMAP243X_GPIO5_BASE 0x480B6000 |
117 | 101 | ||
118 | #define OMAP24XX_GPIO_REVISION 0x0000 | 102 | #define OMAP24XX_GPIO_REVISION 0x0000 |
119 | #define OMAP24XX_GPIO_SYSCONFIG 0x0010 | 103 | #define OMAP24XX_GPIO_SYSCONFIG 0x0010 |
@@ -170,24 +154,25 @@ | |||
170 | * omap34xx specific GPIO registers | 154 | * omap34xx specific GPIO registers |
171 | */ | 155 | */ |
172 | 156 | ||
173 | #define OMAP34XX_GPIO1_BASE OMAP2_IO_ADDRESS(0x48310000) | 157 | #define OMAP34XX_GPIO1_BASE 0x48310000 |
174 | #define OMAP34XX_GPIO2_BASE OMAP2_IO_ADDRESS(0x49050000) | 158 | #define OMAP34XX_GPIO2_BASE 0x49050000 |
175 | #define OMAP34XX_GPIO3_BASE OMAP2_IO_ADDRESS(0x49052000) | 159 | #define OMAP34XX_GPIO3_BASE 0x49052000 |
176 | #define OMAP34XX_GPIO4_BASE OMAP2_IO_ADDRESS(0x49054000) | 160 | #define OMAP34XX_GPIO4_BASE 0x49054000 |
177 | #define OMAP34XX_GPIO5_BASE OMAP2_IO_ADDRESS(0x49056000) | 161 | #define OMAP34XX_GPIO5_BASE 0x49056000 |
178 | #define OMAP34XX_GPIO6_BASE OMAP2_IO_ADDRESS(0x49058000) | 162 | #define OMAP34XX_GPIO6_BASE 0x49058000 |
179 | 163 | ||
180 | /* | 164 | /* |
181 | * OMAP44XX specific GPIO registers | 165 | * OMAP44XX specific GPIO registers |
182 | */ | 166 | */ |
183 | #define OMAP44XX_GPIO1_BASE OMAP2_IO_ADDRESS(0x4a310000) | 167 | #define OMAP44XX_GPIO1_BASE 0x4a310000 |
184 | #define OMAP44XX_GPIO2_BASE OMAP2_IO_ADDRESS(0x48055000) | 168 | #define OMAP44XX_GPIO2_BASE 0x48055000 |
185 | #define OMAP44XX_GPIO3_BASE OMAP2_IO_ADDRESS(0x48057000) | 169 | #define OMAP44XX_GPIO3_BASE 0x48057000 |
186 | #define OMAP44XX_GPIO4_BASE OMAP2_IO_ADDRESS(0x48059000) | 170 | #define OMAP44XX_GPIO4_BASE 0x48059000 |
187 | #define OMAP44XX_GPIO5_BASE OMAP2_IO_ADDRESS(0x4805B000) | 171 | #define OMAP44XX_GPIO5_BASE 0x4805B000 |
188 | #define OMAP44XX_GPIO6_BASE OMAP2_IO_ADDRESS(0x4805D000) | 172 | #define OMAP44XX_GPIO6_BASE 0x4805D000 |
189 | 173 | ||
190 | struct gpio_bank { | 174 | struct gpio_bank { |
175 | unsigned long pbase; | ||
191 | void __iomem *base; | 176 | void __iomem *base; |
192 | u16 irq; | 177 | u16 irq; |
193 | u16 virtual_irq_start; | 178 | u16 virtual_irq_start; |
@@ -215,96 +200,128 @@ struct gpio_bank { | |||
215 | #define METHOD_MPUIO 0 | 200 | #define METHOD_MPUIO 0 |
216 | #define METHOD_GPIO_1510 1 | 201 | #define METHOD_GPIO_1510 1 |
217 | #define METHOD_GPIO_1610 2 | 202 | #define METHOD_GPIO_1610 2 |
218 | #define METHOD_GPIO_730 3 | 203 | #define METHOD_GPIO_7XX 3 |
219 | #define METHOD_GPIO_850 4 | ||
220 | #define METHOD_GPIO_24XX 5 | 204 | #define METHOD_GPIO_24XX 5 |
221 | 205 | ||
222 | #ifdef CONFIG_ARCH_OMAP16XX | 206 | #ifdef CONFIG_ARCH_OMAP16XX |
223 | static struct gpio_bank gpio_bank_1610[5] = { | 207 | static struct gpio_bank gpio_bank_1610[5] = { |
224 | { OMAP1_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO}, | 208 | { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE, |
225 | { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 }, | 209 | METHOD_MPUIO }, |
226 | { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 }, | 210 | { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE, |
227 | { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 }, | 211 | METHOD_GPIO_1610 }, |
228 | { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 }, | 212 | { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, |
213 | METHOD_GPIO_1610 }, | ||
214 | { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, | ||
215 | METHOD_GPIO_1610 }, | ||
216 | { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, | ||
217 | METHOD_GPIO_1610 }, | ||
229 | }; | 218 | }; |
230 | #endif | 219 | #endif |
231 | 220 | ||
232 | #ifdef CONFIG_ARCH_OMAP15XX | 221 | #ifdef CONFIG_ARCH_OMAP15XX |
233 | static struct gpio_bank gpio_bank_1510[2] = { | 222 | static struct gpio_bank gpio_bank_1510[2] = { |
234 | { OMAP1_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, | 223 | { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE, |
235 | { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 } | 224 | METHOD_MPUIO }, |
225 | { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE, | ||
226 | METHOD_GPIO_1510 } | ||
236 | }; | 227 | }; |
237 | #endif | 228 | #endif |
238 | 229 | ||
239 | #ifdef CONFIG_ARCH_OMAP730 | 230 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
240 | static struct gpio_bank gpio_bank_730[7] = { | 231 | static struct gpio_bank gpio_bank_7xx[7] = { |
241 | { OMAP1_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, | 232 | { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE, |
242 | { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 }, | 233 | METHOD_MPUIO }, |
243 | { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 }, | 234 | { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE, |
244 | { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 }, | 235 | METHOD_GPIO_7XX }, |
245 | { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 }, | 236 | { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32, |
246 | { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 }, | 237 | METHOD_GPIO_7XX }, |
247 | { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 }, | 238 | { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64, |
239 | METHOD_GPIO_7XX }, | ||
240 | { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96, | ||
241 | METHOD_GPIO_7XX }, | ||
242 | { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128, | ||
243 | METHOD_GPIO_7XX }, | ||
244 | { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160, | ||
245 | METHOD_GPIO_7XX }, | ||
248 | }; | 246 | }; |
249 | #endif | 247 | #endif |
250 | 248 | ||
251 | #ifdef CONFIG_ARCH_OMAP850 | ||
252 | static struct gpio_bank gpio_bank_850[7] = { | ||
253 | { OMAP1_MPUIO_VBASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, | ||
254 | { OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_850 }, | ||
255 | { OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_850 }, | ||
256 | { OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_850 }, | ||
257 | { OMAP850_GPIO4_BASE, INT_850_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_850 }, | ||
258 | { OMAP850_GPIO5_BASE, INT_850_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_850 }, | ||
259 | { OMAP850_GPIO6_BASE, INT_850_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_850 }, | ||
260 | }; | ||
261 | #endif | ||
262 | |||
263 | |||
264 | #ifdef CONFIG_ARCH_OMAP24XX | 249 | #ifdef CONFIG_ARCH_OMAP24XX |
265 | 250 | ||
266 | static struct gpio_bank gpio_bank_242x[4] = { | 251 | static struct gpio_bank gpio_bank_242x[4] = { |
267 | { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, | 252 | { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, |
268 | { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, | 253 | METHOD_GPIO_24XX }, |
269 | { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, | 254 | { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, |
270 | { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, | 255 | METHOD_GPIO_24XX }, |
256 | { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, | ||
257 | METHOD_GPIO_24XX }, | ||
258 | { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, | ||
259 | METHOD_GPIO_24XX }, | ||
271 | }; | 260 | }; |
272 | 261 | ||
273 | static struct gpio_bank gpio_bank_243x[5] = { | 262 | static struct gpio_bank gpio_bank_243x[5] = { |
274 | { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, | 263 | { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, |
275 | { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, | 264 | METHOD_GPIO_24XX }, |
276 | { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, | 265 | { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, |
277 | { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, | 266 | METHOD_GPIO_24XX }, |
278 | { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX }, | 267 | { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, |
268 | METHOD_GPIO_24XX }, | ||
269 | { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, | ||
270 | METHOD_GPIO_24XX }, | ||
271 | { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, | ||
272 | METHOD_GPIO_24XX }, | ||
279 | }; | 273 | }; |
280 | 274 | ||
281 | #endif | 275 | #endif |
282 | 276 | ||
283 | #ifdef CONFIG_ARCH_OMAP34XX | 277 | #ifdef CONFIG_ARCH_OMAP34XX |
284 | static struct gpio_bank gpio_bank_34xx[6] = { | 278 | static struct gpio_bank gpio_bank_34xx[6] = { |
285 | { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, | 279 | { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, |
286 | { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, | 280 | METHOD_GPIO_24XX }, |
287 | { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, | 281 | { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, |
288 | { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, | 282 | METHOD_GPIO_24XX }, |
289 | { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX }, | 283 | { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, |
290 | { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX }, | 284 | METHOD_GPIO_24XX }, |
285 | { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, | ||
286 | METHOD_GPIO_24XX }, | ||
287 | { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, | ||
288 | METHOD_GPIO_24XX }, | ||
289 | { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, | ||
290 | METHOD_GPIO_24XX }, | ||
291 | }; | ||
292 | |||
293 | struct omap3_gpio_regs { | ||
294 | u32 sysconfig; | ||
295 | u32 irqenable1; | ||
296 | u32 irqenable2; | ||
297 | u32 wake_en; | ||
298 | u32 ctrl; | ||
299 | u32 oe; | ||
300 | u32 leveldetect0; | ||
301 | u32 leveldetect1; | ||
302 | u32 risingdetect; | ||
303 | u32 fallingdetect; | ||
304 | u32 dataout; | ||
305 | u32 setwkuena; | ||
306 | u32 setdataout; | ||
291 | }; | 307 | }; |
292 | 308 | ||
309 | static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS]; | ||
293 | #endif | 310 | #endif |
294 | 311 | ||
295 | #ifdef CONFIG_ARCH_OMAP4 | 312 | #ifdef CONFIG_ARCH_OMAP4 |
296 | static struct gpio_bank gpio_bank_44xx[6] = { | 313 | static struct gpio_bank gpio_bank_44xx[6] = { |
297 | { OMAP44XX_GPIO1_BASE, INT_44XX_GPIO_BANK1, IH_GPIO_BASE, \ | 314 | { OMAP44XX_GPIO1_BASE, NULL, INT_44XX_GPIO_BANK1, IH_GPIO_BASE, |
298 | METHOD_GPIO_24XX }, | 315 | METHOD_GPIO_24XX }, |
299 | { OMAP44XX_GPIO2_BASE, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32, \ | 316 | { OMAP44XX_GPIO2_BASE, NULL, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32, |
300 | METHOD_GPIO_24XX }, | 317 | METHOD_GPIO_24XX }, |
301 | { OMAP44XX_GPIO3_BASE, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64, \ | 318 | { OMAP44XX_GPIO3_BASE, NULL, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64, |
302 | METHOD_GPIO_24XX }, | 319 | METHOD_GPIO_24XX }, |
303 | { OMAP44XX_GPIO4_BASE, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96, \ | 320 | { OMAP44XX_GPIO4_BASE, NULL, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96, |
304 | METHOD_GPIO_24XX }, | 321 | METHOD_GPIO_24XX }, |
305 | { OMAP44XX_GPIO5_BASE, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128, \ | 322 | { OMAP44XX_GPIO5_BASE, NULL, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128, |
306 | METHOD_GPIO_24XX }, | 323 | METHOD_GPIO_24XX }, |
307 | { OMAP44XX_GPIO6_BASE, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160, \ | 324 | { OMAP44XX_GPIO6_BASE, NULL, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160, |
308 | METHOD_GPIO_24XX }, | 325 | METHOD_GPIO_24XX }, |
309 | }; | 326 | }; |
310 | 327 | ||
@@ -402,14 +419,9 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |||
402 | reg += OMAP1610_GPIO_DIRECTION; | 419 | reg += OMAP1610_GPIO_DIRECTION; |
403 | break; | 420 | break; |
404 | #endif | 421 | #endif |
405 | #ifdef CONFIG_ARCH_OMAP730 | 422 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
406 | case METHOD_GPIO_730: | 423 | case METHOD_GPIO_7XX: |
407 | reg += OMAP730_GPIO_DIR_CONTROL; | 424 | reg += OMAP7XX_GPIO_DIR_CONTROL; |
408 | break; | ||
409 | #endif | ||
410 | #ifdef CONFIG_ARCH_OMAP850 | ||
411 | case METHOD_GPIO_850: | ||
412 | reg += OMAP850_GPIO_DIR_CONTROL; | ||
413 | break; | 425 | break; |
414 | #endif | 426 | #endif |
415 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 427 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
@@ -469,19 +481,9 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) | |||
469 | l = 1 << gpio; | 481 | l = 1 << gpio; |
470 | break; | 482 | break; |
471 | #endif | 483 | #endif |
472 | #ifdef CONFIG_ARCH_OMAP730 | 484 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
473 | case METHOD_GPIO_730: | 485 | case METHOD_GPIO_7XX: |
474 | reg += OMAP730_GPIO_DATA_OUTPUT; | 486 | reg += OMAP7XX_GPIO_DATA_OUTPUT; |
475 | l = __raw_readl(reg); | ||
476 | if (enable) | ||
477 | l |= 1 << gpio; | ||
478 | else | ||
479 | l &= ~(1 << gpio); | ||
480 | break; | ||
481 | #endif | ||
482 | #ifdef CONFIG_ARCH_OMAP850 | ||
483 | case METHOD_GPIO_850: | ||
484 | reg += OMAP850_GPIO_DATA_OUTPUT; | ||
485 | l = __raw_readl(reg); | 487 | l = __raw_readl(reg); |
486 | if (enable) | 488 | if (enable) |
487 | l |= 1 << gpio; | 489 | l |= 1 << gpio; |
@@ -537,14 +539,9 @@ static int _get_gpio_datain(struct gpio_bank *bank, int gpio) | |||
537 | reg += OMAP1610_GPIO_DATAIN; | 539 | reg += OMAP1610_GPIO_DATAIN; |
538 | break; | 540 | break; |
539 | #endif | 541 | #endif |
540 | #ifdef CONFIG_ARCH_OMAP730 | 542 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
541 | case METHOD_GPIO_730: | 543 | case METHOD_GPIO_7XX: |
542 | reg += OMAP730_GPIO_DATA_INPUT; | 544 | reg += OMAP7XX_GPIO_DATA_INPUT; |
543 | break; | ||
544 | #endif | ||
545 | #ifdef CONFIG_ARCH_OMAP850 | ||
546 | case METHOD_GPIO_850: | ||
547 | reg += OMAP850_GPIO_DATA_INPUT; | ||
548 | break; | 545 | break; |
549 | #endif | 546 | #endif |
550 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 547 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
@@ -588,14 +585,9 @@ static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) | |||
588 | reg += OMAP1610_GPIO_DATAOUT; | 585 | reg += OMAP1610_GPIO_DATAOUT; |
589 | break; | 586 | break; |
590 | #endif | 587 | #endif |
591 | #ifdef CONFIG_ARCH_OMAP730 | 588 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
592 | case METHOD_GPIO_730: | 589 | case METHOD_GPIO_7XX: |
593 | reg += OMAP730_GPIO_DATA_OUTPUT; | 590 | reg += OMAP7XX_GPIO_DATA_OUTPUT; |
594 | break; | ||
595 | #endif | ||
596 | #ifdef CONFIG_ARCH_OMAP850 | ||
597 | case METHOD_GPIO_850: | ||
598 | reg += OMAP850_GPIO_DATA_OUTPUT; | ||
599 | break; | 591 | break; |
600 | #endif | 592 | #endif |
601 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ | 593 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
@@ -797,21 +789,9 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) | |||
797 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); | 789 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); |
798 | break; | 790 | break; |
799 | #endif | 791 | #endif |
800 | #ifdef CONFIG_ARCH_OMAP730 | 792 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
801 | case METHOD_GPIO_730: | 793 | case METHOD_GPIO_7XX: |
802 | reg += OMAP730_GPIO_INT_CONTROL; | 794 | reg += OMAP7XX_GPIO_INT_CONTROL; |
803 | l = __raw_readl(reg); | ||
804 | if (trigger & IRQ_TYPE_EDGE_RISING) | ||
805 | l |= 1 << gpio; | ||
806 | else if (trigger & IRQ_TYPE_EDGE_FALLING) | ||
807 | l &= ~(1 << gpio); | ||
808 | else | ||
809 | goto bad; | ||
810 | break; | ||
811 | #endif | ||
812 | #ifdef CONFIG_ARCH_OMAP850 | ||
813 | case METHOD_GPIO_850: | ||
814 | reg += OMAP850_GPIO_INT_CONTROL; | ||
815 | l = __raw_readl(reg); | 795 | l = __raw_readl(reg); |
816 | if (trigger & IRQ_TYPE_EDGE_RISING) | 796 | if (trigger & IRQ_TYPE_EDGE_RISING) |
817 | l |= 1 << gpio; | 797 | l |= 1 << gpio; |
@@ -897,14 +877,9 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |||
897 | reg += OMAP1610_GPIO_IRQSTATUS1; | 877 | reg += OMAP1610_GPIO_IRQSTATUS1; |
898 | break; | 878 | break; |
899 | #endif | 879 | #endif |
900 | #ifdef CONFIG_ARCH_OMAP730 | 880 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
901 | case METHOD_GPIO_730: | 881 | case METHOD_GPIO_7XX: |
902 | reg += OMAP730_GPIO_INT_STATUS; | 882 | reg += OMAP7XX_GPIO_INT_STATUS; |
903 | break; | ||
904 | #endif | ||
905 | #ifdef CONFIG_ARCH_OMAP850 | ||
906 | case METHOD_GPIO_850: | ||
907 | reg += OMAP850_GPIO_INT_STATUS; | ||
908 | break; | 883 | break; |
909 | #endif | 884 | #endif |
910 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 885 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
@@ -971,16 +946,9 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) | |||
971 | mask = 0xffff; | 946 | mask = 0xffff; |
972 | break; | 947 | break; |
973 | #endif | 948 | #endif |
974 | #ifdef CONFIG_ARCH_OMAP730 | 949 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
975 | case METHOD_GPIO_730: | 950 | case METHOD_GPIO_7XX: |
976 | reg += OMAP730_GPIO_INT_MASK; | 951 | reg += OMAP7XX_GPIO_INT_MASK; |
977 | mask = 0xffffffff; | ||
978 | inv = 1; | ||
979 | break; | ||
980 | #endif | ||
981 | #ifdef CONFIG_ARCH_OMAP850 | ||
982 | case METHOD_GPIO_850: | ||
983 | reg += OMAP850_GPIO_INT_MASK; | ||
984 | mask = 0xffffffff; | 952 | mask = 0xffffffff; |
985 | inv = 1; | 953 | inv = 1; |
986 | break; | 954 | break; |
@@ -1044,19 +1012,9 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab | |||
1044 | l = gpio_mask; | 1012 | l = gpio_mask; |
1045 | break; | 1013 | break; |
1046 | #endif | 1014 | #endif |
1047 | #ifdef CONFIG_ARCH_OMAP730 | 1015 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
1048 | case METHOD_GPIO_730: | 1016 | case METHOD_GPIO_7XX: |
1049 | reg += OMAP730_GPIO_INT_MASK; | 1017 | reg += OMAP7XX_GPIO_INT_MASK; |
1050 | l = __raw_readl(reg); | ||
1051 | if (enable) | ||
1052 | l &= ~(gpio_mask); | ||
1053 | else | ||
1054 | l |= gpio_mask; | ||
1055 | break; | ||
1056 | #endif | ||
1057 | #ifdef CONFIG_ARCH_OMAP850 | ||
1058 | case METHOD_GPIO_850: | ||
1059 | reg += OMAP850_GPIO_INT_MASK; | ||
1060 | l = __raw_readl(reg); | 1018 | l = __raw_readl(reg); |
1061 | if (enable) | 1019 | if (enable) |
1062 | l &= ~(gpio_mask); | 1020 | l &= ~(gpio_mask); |
@@ -1249,13 +1207,9 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
1249 | if (bank->method == METHOD_GPIO_1610) | 1207 | if (bank->method == METHOD_GPIO_1610) |
1250 | isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1; | 1208 | isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1; |
1251 | #endif | 1209 | #endif |
1252 | #ifdef CONFIG_ARCH_OMAP730 | 1210 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
1253 | if (bank->method == METHOD_GPIO_730) | 1211 | if (bank->method == METHOD_GPIO_7XX) |
1254 | isr_reg = bank->base + OMAP730_GPIO_INT_STATUS; | 1212 | isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS; |
1255 | #endif | ||
1256 | #ifdef CONFIG_ARCH_OMAP850 | ||
1257 | if (bank->method == METHOD_GPIO_850) | ||
1258 | isr_reg = bank->base + OMAP850_GPIO_INT_STATUS; | ||
1259 | #endif | 1213 | #endif |
1260 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 1214 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
1261 | if (bank->method == METHOD_GPIO_24XX) | 1215 | if (bank->method == METHOD_GPIO_24XX) |
@@ -1524,11 +1478,8 @@ static int gpio_is_input(struct gpio_bank *bank, int mask) | |||
1524 | case METHOD_GPIO_1610: | 1478 | case METHOD_GPIO_1610: |
1525 | reg += OMAP1610_GPIO_DIRECTION; | 1479 | reg += OMAP1610_GPIO_DIRECTION; |
1526 | break; | 1480 | break; |
1527 | case METHOD_GPIO_730: | 1481 | case METHOD_GPIO_7XX: |
1528 | reg += OMAP730_GPIO_DIR_CONTROL; | 1482 | reg += OMAP7XX_GPIO_DIR_CONTROL; |
1529 | break; | ||
1530 | case METHOD_GPIO_850: | ||
1531 | reg += OMAP850_GPIO_DIR_CONTROL; | ||
1532 | break; | 1483 | break; |
1533 | case METHOD_GPIO_24XX: | 1484 | case METHOD_GPIO_24XX: |
1534 | reg += OMAP24XX_GPIO_OE; | 1485 | reg += OMAP24XX_GPIO_OE; |
@@ -1607,6 +1558,23 @@ static struct clk * gpio5_fck; | |||
1607 | static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS]; | 1558 | static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS]; |
1608 | #endif | 1559 | #endif |
1609 | 1560 | ||
1561 | static void __init omap_gpio_show_rev(void) | ||
1562 | { | ||
1563 | u32 rev; | ||
1564 | |||
1565 | if (cpu_is_omap16xx()) | ||
1566 | rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); | ||
1567 | else if (cpu_is_omap24xx() || cpu_is_omap34xx()) | ||
1568 | rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); | ||
1569 | else if (cpu_is_omap44xx()) | ||
1570 | rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION); | ||
1571 | else | ||
1572 | return; | ||
1573 | |||
1574 | printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", | ||
1575 | (rev >> 4) & 0x0f, rev & 0x0f); | ||
1576 | } | ||
1577 | |||
1610 | /* This lock class tells lockdep that GPIO irqs are in a different | 1578 | /* This lock class tells lockdep that GPIO irqs are in a different |
1611 | * category than their parents, so it won't report false recursion. | 1579 | * category than their parents, so it won't report false recursion. |
1612 | */ | 1580 | */ |
@@ -1617,6 +1585,7 @@ static int __init _omap_gpio_init(void) | |||
1617 | int i; | 1585 | int i; |
1618 | int gpio = 0; | 1586 | int gpio = 0; |
1619 | struct gpio_bank *bank; | 1587 | struct gpio_bank *bank; |
1588 | int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */ | ||
1620 | char clk_name[11]; | 1589 | char clk_name[11]; |
1621 | 1590 | ||
1622 | initialized = 1; | 1591 | initialized = 1; |
@@ -1679,77 +1648,45 @@ static int __init _omap_gpio_init(void) | |||
1679 | 1648 | ||
1680 | #ifdef CONFIG_ARCH_OMAP15XX | 1649 | #ifdef CONFIG_ARCH_OMAP15XX |
1681 | if (cpu_is_omap15xx()) { | 1650 | if (cpu_is_omap15xx()) { |
1682 | printk(KERN_INFO "OMAP1510 GPIO hardware\n"); | ||
1683 | gpio_bank_count = 2; | 1651 | gpio_bank_count = 2; |
1684 | gpio_bank = gpio_bank_1510; | 1652 | gpio_bank = gpio_bank_1510; |
1653 | bank_size = SZ_2K; | ||
1685 | } | 1654 | } |
1686 | #endif | 1655 | #endif |
1687 | #if defined(CONFIG_ARCH_OMAP16XX) | 1656 | #if defined(CONFIG_ARCH_OMAP16XX) |
1688 | if (cpu_is_omap16xx()) { | 1657 | if (cpu_is_omap16xx()) { |
1689 | u32 rev; | ||
1690 | |||
1691 | gpio_bank_count = 5; | 1658 | gpio_bank_count = 5; |
1692 | gpio_bank = gpio_bank_1610; | 1659 | gpio_bank = gpio_bank_1610; |
1693 | rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); | 1660 | bank_size = SZ_2K; |
1694 | printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", | ||
1695 | (rev >> 4) & 0x0f, rev & 0x0f); | ||
1696 | } | 1661 | } |
1697 | #endif | 1662 | #endif |
1698 | #ifdef CONFIG_ARCH_OMAP730 | 1663 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
1699 | if (cpu_is_omap730()) { | 1664 | if (cpu_is_omap7xx()) { |
1700 | printk(KERN_INFO "OMAP730 GPIO hardware\n"); | ||
1701 | gpio_bank_count = 7; | ||
1702 | gpio_bank = gpio_bank_730; | ||
1703 | } | ||
1704 | #endif | ||
1705 | #ifdef CONFIG_ARCH_OMAP850 | ||
1706 | if (cpu_is_omap850()) { | ||
1707 | printk(KERN_INFO "OMAP850 GPIO hardware\n"); | ||
1708 | gpio_bank_count = 7; | 1665 | gpio_bank_count = 7; |
1709 | gpio_bank = gpio_bank_850; | 1666 | gpio_bank = gpio_bank_7xx; |
1667 | bank_size = SZ_2K; | ||
1710 | } | 1668 | } |
1711 | #endif | 1669 | #endif |
1712 | |||
1713 | #ifdef CONFIG_ARCH_OMAP24XX | 1670 | #ifdef CONFIG_ARCH_OMAP24XX |
1714 | if (cpu_is_omap242x()) { | 1671 | if (cpu_is_omap242x()) { |
1715 | int rev; | ||
1716 | |||
1717 | gpio_bank_count = 4; | 1672 | gpio_bank_count = 4; |
1718 | gpio_bank = gpio_bank_242x; | 1673 | gpio_bank = gpio_bank_242x; |
1719 | rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); | ||
1720 | printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n", | ||
1721 | (rev >> 4) & 0x0f, rev & 0x0f); | ||
1722 | } | 1674 | } |
1723 | if (cpu_is_omap243x()) { | 1675 | if (cpu_is_omap243x()) { |
1724 | int rev; | ||
1725 | |||
1726 | gpio_bank_count = 5; | 1676 | gpio_bank_count = 5; |
1727 | gpio_bank = gpio_bank_243x; | 1677 | gpio_bank = gpio_bank_243x; |
1728 | rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); | ||
1729 | printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n", | ||
1730 | (rev >> 4) & 0x0f, rev & 0x0f); | ||
1731 | } | 1678 | } |
1732 | #endif | 1679 | #endif |
1733 | #ifdef CONFIG_ARCH_OMAP34XX | 1680 | #ifdef CONFIG_ARCH_OMAP34XX |
1734 | if (cpu_is_omap34xx()) { | 1681 | if (cpu_is_omap34xx()) { |
1735 | int rev; | ||
1736 | |||
1737 | gpio_bank_count = OMAP34XX_NR_GPIOS; | 1682 | gpio_bank_count = OMAP34XX_NR_GPIOS; |
1738 | gpio_bank = gpio_bank_34xx; | 1683 | gpio_bank = gpio_bank_34xx; |
1739 | rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); | ||
1740 | printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n", | ||
1741 | (rev >> 4) & 0x0f, rev & 0x0f); | ||
1742 | } | 1684 | } |
1743 | #endif | 1685 | #endif |
1744 | #ifdef CONFIG_ARCH_OMAP4 | 1686 | #ifdef CONFIG_ARCH_OMAP4 |
1745 | if (cpu_is_omap44xx()) { | 1687 | if (cpu_is_omap44xx()) { |
1746 | int rev; | ||
1747 | |||
1748 | gpio_bank_count = OMAP34XX_NR_GPIOS; | 1688 | gpio_bank_count = OMAP34XX_NR_GPIOS; |
1749 | gpio_bank = gpio_bank_44xx; | 1689 | gpio_bank = gpio_bank_44xx; |
1750 | rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION); | ||
1751 | printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n", | ||
1752 | (rev >> 4) & 0x0f, rev & 0x0f); | ||
1753 | } | 1690 | } |
1754 | #endif | 1691 | #endif |
1755 | for (i = 0; i < gpio_bank_count; i++) { | 1692 | for (i = 0; i < gpio_bank_count; i++) { |
@@ -1757,6 +1694,14 @@ static int __init _omap_gpio_init(void) | |||
1757 | 1694 | ||
1758 | bank = &gpio_bank[i]; | 1695 | bank = &gpio_bank[i]; |
1759 | spin_lock_init(&bank->lock); | 1696 | spin_lock_init(&bank->lock); |
1697 | |||
1698 | /* Static mapping, never released */ | ||
1699 | bank->base = ioremap(bank->pbase, bank_size); | ||
1700 | if (!bank->base) { | ||
1701 | printk(KERN_ERR "Could not ioremap gpio bank%i\n", i); | ||
1702 | continue; | ||
1703 | } | ||
1704 | |||
1760 | if (bank_is_mpuio(bank)) | 1705 | if (bank_is_mpuio(bank)) |
1761 | __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT); | 1706 | __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT); |
1762 | if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { | 1707 | if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { |
@@ -1768,11 +1713,11 @@ static int __init _omap_gpio_init(void) | |||
1768 | __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); | 1713 | __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); |
1769 | __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); | 1714 | __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); |
1770 | } | 1715 | } |
1771 | if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_730) { | 1716 | if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) { |
1772 | __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK); | 1717 | __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK); |
1773 | __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS); | 1718 | __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS); |
1774 | 1719 | ||
1775 | gpio_count = 32; /* 730 has 32-bit GPIOs */ | 1720 | gpio_count = 32; /* 7xx has 32-bit GPIOs */ |
1776 | } | 1721 | } |
1777 | 1722 | ||
1778 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ | 1723 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
@@ -1862,6 +1807,8 @@ static int __init _omap_gpio_init(void) | |||
1862 | if (cpu_is_omap34xx()) | 1807 | if (cpu_is_omap34xx()) |
1863 | omap_writel(1 << 0, 0x48306814); | 1808 | omap_writel(1 << 0, 0x48306814); |
1864 | 1809 | ||
1810 | omap_gpio_show_rev(); | ||
1811 | |||
1865 | return 0; | 1812 | return 0; |
1866 | } | 1813 | } |
1867 | 1814 | ||
@@ -2106,6 +2053,81 @@ void omap2_gpio_resume_after_retention(void) | |||
2106 | 2053 | ||
2107 | #endif | 2054 | #endif |
2108 | 2055 | ||
2056 | #ifdef CONFIG_ARCH_OMAP34XX | ||
2057 | /* save the registers of bank 2-6 */ | ||
2058 | void omap_gpio_save_context(void) | ||
2059 | { | ||
2060 | int i; | ||
2061 | |||
2062 | /* saving banks from 2-6 only since GPIO1 is in WKUP */ | ||
2063 | for (i = 1; i < gpio_bank_count; i++) { | ||
2064 | struct gpio_bank *bank = &gpio_bank[i]; | ||
2065 | gpio_context[i].sysconfig = | ||
2066 | __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG); | ||
2067 | gpio_context[i].irqenable1 = | ||
2068 | __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1); | ||
2069 | gpio_context[i].irqenable2 = | ||
2070 | __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2); | ||
2071 | gpio_context[i].wake_en = | ||
2072 | __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN); | ||
2073 | gpio_context[i].ctrl = | ||
2074 | __raw_readl(bank->base + OMAP24XX_GPIO_CTRL); | ||
2075 | gpio_context[i].oe = | ||
2076 | __raw_readl(bank->base + OMAP24XX_GPIO_OE); | ||
2077 | gpio_context[i].leveldetect0 = | ||
2078 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); | ||
2079 | gpio_context[i].leveldetect1 = | ||
2080 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | ||
2081 | gpio_context[i].risingdetect = | ||
2082 | __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); | ||
2083 | gpio_context[i].fallingdetect = | ||
2084 | __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); | ||
2085 | gpio_context[i].dataout = | ||
2086 | __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT); | ||
2087 | gpio_context[i].setwkuena = | ||
2088 | __raw_readl(bank->base + OMAP24XX_GPIO_SETWKUENA); | ||
2089 | gpio_context[i].setdataout = | ||
2090 | __raw_readl(bank->base + OMAP24XX_GPIO_SETDATAOUT); | ||
2091 | } | ||
2092 | } | ||
2093 | |||
2094 | /* restore the required registers of bank 2-6 */ | ||
2095 | void omap_gpio_restore_context(void) | ||
2096 | { | ||
2097 | int i; | ||
2098 | |||
2099 | for (i = 1; i < gpio_bank_count; i++) { | ||
2100 | struct gpio_bank *bank = &gpio_bank[i]; | ||
2101 | __raw_writel(gpio_context[i].sysconfig, | ||
2102 | bank->base + OMAP24XX_GPIO_SYSCONFIG); | ||
2103 | __raw_writel(gpio_context[i].irqenable1, | ||
2104 | bank->base + OMAP24XX_GPIO_IRQENABLE1); | ||
2105 | __raw_writel(gpio_context[i].irqenable2, | ||
2106 | bank->base + OMAP24XX_GPIO_IRQENABLE2); | ||
2107 | __raw_writel(gpio_context[i].wake_en, | ||
2108 | bank->base + OMAP24XX_GPIO_WAKE_EN); | ||
2109 | __raw_writel(gpio_context[i].ctrl, | ||
2110 | bank->base + OMAP24XX_GPIO_CTRL); | ||
2111 | __raw_writel(gpio_context[i].oe, | ||
2112 | bank->base + OMAP24XX_GPIO_OE); | ||
2113 | __raw_writel(gpio_context[i].leveldetect0, | ||
2114 | bank->base + OMAP24XX_GPIO_LEVELDETECT0); | ||
2115 | __raw_writel(gpio_context[i].leveldetect1, | ||
2116 | bank->base + OMAP24XX_GPIO_LEVELDETECT1); | ||
2117 | __raw_writel(gpio_context[i].risingdetect, | ||
2118 | bank->base + OMAP24XX_GPIO_RISINGDETECT); | ||
2119 | __raw_writel(gpio_context[i].fallingdetect, | ||
2120 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); | ||
2121 | __raw_writel(gpio_context[i].dataout, | ||
2122 | bank->base + OMAP24XX_GPIO_DATAOUT); | ||
2123 | __raw_writel(gpio_context[i].setwkuena, | ||
2124 | bank->base + OMAP24XX_GPIO_SETWKUENA); | ||
2125 | __raw_writel(gpio_context[i].setdataout, | ||
2126 | bank->base + OMAP24XX_GPIO_SETDATAOUT); | ||
2127 | } | ||
2128 | } | ||
2129 | #endif | ||
2130 | |||
2109 | /* | 2131 | /* |
2110 | * This may get called early from board specific init | 2132 | * This may get called early from board specific init |
2111 | * for boards that have interrupts routed via FPGA. | 2133 | * for boards that have interrupts routed via FPGA. |
@@ -2160,8 +2182,7 @@ static int dbg_gpio_show(struct seq_file *s, void *unused) | |||
2160 | 2182 | ||
2161 | if (bank_is_mpuio(bank)) | 2183 | if (bank_is_mpuio(bank)) |
2162 | gpio = OMAP_MPUIO(0); | 2184 | gpio = OMAP_MPUIO(0); |
2163 | else if (cpu_class_is_omap2() || cpu_is_omap730() || | 2185 | else if (cpu_class_is_omap2() || cpu_is_omap7xx()) |
2164 | cpu_is_omap850()) | ||
2165 | bankwidth = 32; | 2186 | bankwidth = 32; |
2166 | 2187 | ||
2167 | for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { | 2188 | for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { |
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c index 8b848391f0c8..c08362dbb8ed 100644 --- a/arch/arm/plat-omap/i2c.c +++ b/arch/arm/plat-omap/i2c.c | |||
@@ -27,7 +27,7 @@ | |||
27 | #include <linux/platform_device.h> | 27 | #include <linux/platform_device.h> |
28 | #include <linux/i2c.h> | 28 | #include <linux/i2c.h> |
29 | #include <mach/irqs.h> | 29 | #include <mach/irqs.h> |
30 | #include <mach/mux.h> | 30 | #include <plat/mux.h> |
31 | 31 | ||
32 | #define OMAP_I2C_SIZE 0x3f | 32 | #define OMAP_I2C_SIZE 0x3f |
33 | #define OMAP1_I2C_BASE 0xfffb3800 | 33 | #define OMAP1_I2C_BASE 0xfffb3800 |
diff --git a/arch/arm/plat-omap/include/mach/blizzard.h b/arch/arm/plat-omap/include/plat/blizzard.h index 8d160f171372..8d160f171372 100644 --- a/arch/arm/plat-omap/include/mach/blizzard.h +++ b/arch/arm/plat-omap/include/plat/blizzard.h | |||
diff --git a/arch/arm/plat-omap/include/mach/board-ams-delta.h b/arch/arm/plat-omap/include/plat/board-ams-delta.h index 51b102dc906b..51b102dc906b 100644 --- a/arch/arm/plat-omap/include/mach/board-ams-delta.h +++ b/arch/arm/plat-omap/include/plat/board-ams-delta.h | |||
diff --git a/arch/arm/plat-omap/include/mach/board-sx1.h b/arch/arm/plat-omap/include/plat/board-sx1.h index 355adbdaae33..355adbdaae33 100644 --- a/arch/arm/plat-omap/include/mach/board-sx1.h +++ b/arch/arm/plat-omap/include/plat/board-sx1.h | |||
diff --git a/arch/arm/plat-omap/include/mach/board-voiceblue.h b/arch/arm/plat-omap/include/plat/board-voiceblue.h index 27916b210f57..27916b210f57 100644 --- a/arch/arm/plat-omap/include/mach/board-voiceblue.h +++ b/arch/arm/plat-omap/include/plat/board-voiceblue.h | |||
diff --git a/arch/arm/plat-omap/include/mach/board.h b/arch/arm/plat-omap/include/plat/board.h index 8e913c322810..c4fc69f09796 100644 --- a/arch/arm/plat-omap/include/mach/board.h +++ b/arch/arm/plat-omap/include/plat/board.h | |||
@@ -12,7 +12,7 @@ | |||
12 | 12 | ||
13 | #include <linux/types.h> | 13 | #include <linux/types.h> |
14 | 14 | ||
15 | #include <mach/gpio-switch.h> | 15 | #include <plat/gpio-switch.h> |
16 | 16 | ||
17 | /* Different peripheral ids */ | 17 | /* Different peripheral ids */ |
18 | #define OMAP_TAG_CLOCK 0x4f01 | 18 | #define OMAP_TAG_CLOCK 0x4f01 |
diff --git a/arch/arm/plat-omap/include/mach/clkdev.h b/arch/arm/plat-omap/include/plat/clkdev.h index 730c49d1ebd8..730c49d1ebd8 100644 --- a/arch/arm/plat-omap/include/mach/clkdev.h +++ b/arch/arm/plat-omap/include/plat/clkdev.h | |||
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/plat/clock.h index 4b8b0d65cbf2..4b8b0d65cbf2 100644 --- a/arch/arm/plat-omap/include/mach/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h | |||
diff --git a/arch/arm/plat-omap/include/mach/clockdomain.h b/arch/arm/plat-omap/include/plat/clockdomain.h index 99ebd886f134..eb734826e64e 100644 --- a/arch/arm/plat-omap/include/mach/clockdomain.h +++ b/arch/arm/plat-omap/include/plat/clockdomain.h | |||
@@ -16,9 +16,9 @@ | |||
16 | #ifndef __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H | 16 | #ifndef __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H |
17 | #define __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H | 17 | #define __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H |
18 | 18 | ||
19 | #include <mach/powerdomain.h> | 19 | #include <plat/powerdomain.h> |
20 | #include <mach/clock.h> | 20 | #include <plat/clock.h> |
21 | #include <mach/cpu.h> | 21 | #include <plat/cpu.h> |
22 | 22 | ||
23 | /* Clockdomain capability flags */ | 23 | /* Clockdomain capability flags */ |
24 | #define CLKDM_CAN_FORCE_SLEEP (1 << 0) | 24 | #define CLKDM_CAN_FORCE_SLEEP (1 << 0) |
diff --git a/arch/arm/plat-omap/include/mach/common.h b/arch/arm/plat-omap/include/plat/common.h index fdeab421b4dc..064f1730f43b 100644 --- a/arch/arm/plat-omap/include/mach/common.h +++ b/arch/arm/plat-omap/include/plat/common.h | |||
@@ -31,6 +31,9 @@ | |||
31 | 31 | ||
32 | struct sys_timer; | 32 | struct sys_timer; |
33 | 33 | ||
34 | /* used by omap-smp.c and board-4430sdp.c */ | ||
35 | extern void __iomem *gic_cpu_base_addr; | ||
36 | |||
34 | extern void omap_map_common_io(void); | 37 | extern void omap_map_common_io(void); |
35 | extern struct sys_timer omap_timer; | 38 | extern struct sys_timer omap_timer; |
36 | #if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE) | 39 | #if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE) |
diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/plat/control.h index 826d317cdbec..8237cb9e74fd 100644 --- a/arch/arm/plat-omap/include/mach/control.h +++ b/arch/arm/plat-omap/include/plat/control.h | |||
@@ -20,15 +20,18 @@ | |||
20 | 20 | ||
21 | #ifndef __ASSEMBLY__ | 21 | #ifndef __ASSEMBLY__ |
22 | #define OMAP242X_CTRL_REGADDR(reg) \ | 22 | #define OMAP242X_CTRL_REGADDR(reg) \ |
23 | OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) | 23 | OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) |
24 | #define OMAP243X_CTRL_REGADDR(reg) \ | 24 | #define OMAP243X_CTRL_REGADDR(reg) \ |
25 | OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) | 25 | OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) |
26 | #define OMAP343X_CTRL_REGADDR(reg) \ | 26 | #define OMAP343X_CTRL_REGADDR(reg) \ |
27 | OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) | 27 | OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) |
28 | #else | 28 | #else |
29 | #define OMAP242X_CTRL_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) | 29 | #define OMAP242X_CTRL_REGADDR(reg) \ |
30 | #define OMAP243X_CTRL_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) | 30 | OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) |
31 | #define OMAP343X_CTRL_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) | 31 | #define OMAP243X_CTRL_REGADDR(reg) \ |
32 | OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) | ||
33 | #define OMAP343X_CTRL_REGADDR(reg) \ | ||
34 | OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) | ||
32 | #endif /* __ASSEMBLY__ */ | 35 | #endif /* __ASSEMBLY__ */ |
33 | 36 | ||
34 | /* | 37 | /* |
@@ -109,6 +112,8 @@ | |||
109 | #define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0) | 112 | #define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0) |
110 | #define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4) | 113 | #define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4) |
111 | 114 | ||
115 | #define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0) | ||
116 | |||
112 | /* 34xx-only CONTROL_GENERAL register offsets */ | 117 | /* 34xx-only CONTROL_GENERAL register offsets */ |
113 | #define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000) | 118 | #define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000) |
114 | #define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008) | 119 | #define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008) |
@@ -141,8 +146,51 @@ | |||
141 | #define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) | 146 | #define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) |
142 | #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) | 147 | #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) |
143 | #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) | 148 | #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) |
144 | #define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02b0) | 149 | #define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \ |
145 | #define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02b4) | 150 | + ((i) >> 1) * 4 + (!(i) & 1) * 2) |
151 | #define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4) | ||
152 | #define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8) | ||
153 | #define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0) | ||
154 | #define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4) | ||
155 | #define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8) | ||
156 | #define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC) | ||
157 | #define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0) | ||
158 | #define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4) | ||
159 | #define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8) | ||
160 | #define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0) | ||
161 | #define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4) | ||
162 | |||
163 | |||
164 | /* 34xx PADCONF register offsets */ | ||
165 | #define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \ | ||
166 | (i)*2) | ||
167 | #define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0) | ||
168 | #define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1) | ||
169 | #define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2) | ||
170 | #define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3) | ||
171 | #define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4) | ||
172 | #define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5) | ||
173 | #define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6) | ||
174 | #define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7) | ||
175 | #define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8) | ||
176 | #define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9) | ||
177 | #define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10) | ||
178 | #define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11) | ||
179 | #define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12) | ||
180 | #define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13) | ||
181 | #define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14) | ||
182 | #define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15) | ||
183 | #define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16) | ||
184 | #define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17) | ||
185 | |||
186 | /* 34xx GENERAL_WKUP regist offsets */ | ||
187 | #define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \ | ||
188 | 0x008 + (i)) | ||
189 | #define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008) | ||
190 | #define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C) | ||
191 | #define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010) | ||
192 | #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014) | ||
193 | #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018) | ||
146 | 194 | ||
147 | /* 34xx D2D idle-related pins, handled by PM core */ | 195 | /* 34xx D2D idle-related pins, handled by PM core */ |
148 | #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 | 196 | #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 |
@@ -202,6 +250,10 @@ | |||
202 | #define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15) | 250 | #define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15) |
203 | #define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14) | 251 | #define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14) |
204 | 252 | ||
253 | #define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860) | ||
254 | #define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910) | ||
255 | #define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C | ||
256 | |||
205 | #ifndef __ASSEMBLY__ | 257 | #ifndef __ASSEMBLY__ |
206 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ | 258 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ |
207 | defined(CONFIG_ARCH_OMAP4) | 259 | defined(CONFIG_ARCH_OMAP4) |
@@ -212,6 +264,15 @@ extern u32 omap_ctrl_readl(u16 offset); | |||
212 | extern void omap_ctrl_writeb(u8 val, u16 offset); | 264 | extern void omap_ctrl_writeb(u8 val, u16 offset); |
213 | extern void omap_ctrl_writew(u16 val, u16 offset); | 265 | extern void omap_ctrl_writew(u16 val, u16 offset); |
214 | extern void omap_ctrl_writel(u32 val, u16 offset); | 266 | extern void omap_ctrl_writel(u32 val, u16 offset); |
267 | |||
268 | extern void omap3_save_scratchpad_contents(void); | ||
269 | extern void omap3_clear_scratchpad_contents(void); | ||
270 | extern u32 *get_restore_pointer(void); | ||
271 | extern u32 *get_es3_restore_pointer(void); | ||
272 | extern u32 omap3_arm_context[128]; | ||
273 | extern void omap3_control_save_context(void); | ||
274 | extern void omap3_control_restore_context(void); | ||
275 | |||
215 | #else | 276 | #else |
216 | #define omap_ctrl_base_get() 0 | 277 | #define omap_ctrl_base_get() 0 |
217 | #define omap_ctrl_readb(x) 0 | 278 | #define omap_ctrl_readb(x) 0 |
diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index f129efb3075e..f129efb3075e 100644 --- a/arch/arm/plat-omap/include/mach/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h | |||
diff --git a/arch/arm/plat-omap/include/mach/dma.h b/arch/arm/plat-omap/include/plat/dma.h index 72f680b7180d..1c017b29b7e9 100644 --- a/arch/arm/plat-omap/include/mach/dma.h +++ b/arch/arm/plat-omap/include/plat/dma.h | |||
@@ -633,6 +633,11 @@ extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype); | |||
633 | extern void omap_set_dma_src_endian_type(int lch, enum end_type etype); | 633 | extern void omap_set_dma_src_endian_type(int lch, enum end_type etype); |
634 | extern int omap_get_dma_index(int lch, int *ei, int *fi); | 634 | extern int omap_get_dma_index(int lch, int *ei, int *fi); |
635 | 635 | ||
636 | void omap_dma_global_context_save(void); | ||
637 | void omap_dma_global_context_restore(void); | ||
638 | |||
639 | extern void omap_dma_disable_irq(int lch); | ||
640 | |||
636 | /* Chaining APIs */ | 641 | /* Chaining APIs */ |
637 | #ifndef CONFIG_ARCH_OMAP1 | 642 | #ifndef CONFIG_ARCH_OMAP1 |
638 | extern int omap_request_dma_chain(int dev_id, const char *dev_name, | 643 | extern int omap_request_dma_chain(int dev_id, const char *dev_name, |
diff --git a/arch/arm/plat-omap/include/mach/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 20f1054c0a80..20f1054c0a80 100644 --- a/arch/arm/plat-omap/include/mach/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h | |||
diff --git a/arch/arm/plat-omap/include/mach/dsp_common.h b/arch/arm/plat-omap/include/plat/dsp_common.h index da97736f3efa..da97736f3efa 100644 --- a/arch/arm/plat-omap/include/mach/dsp_common.h +++ b/arch/arm/plat-omap/include/plat/dsp_common.h | |||
diff --git a/arch/arm/plat-omap/include/mach/fpga.h b/arch/arm/plat-omap/include/plat/fpga.h index f1864a652f7a..f1864a652f7a 100644 --- a/arch/arm/plat-omap/include/mach/fpga.h +++ b/arch/arm/plat-omap/include/plat/fpga.h | |||
diff --git a/arch/arm/plat-omap/include/mach/gpio-switch.h b/arch/arm/plat-omap/include/plat/gpio-switch.h index 10da0e07c0cf..10da0e07c0cf 100644 --- a/arch/arm/plat-omap/include/mach/gpio-switch.h +++ b/arch/arm/plat-omap/include/plat/gpio-switch.h | |||
diff --git a/arch/arm/plat-omap/include/mach/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h index 633ff688b928..de7c54731cbe 100644 --- a/arch/arm/plat-omap/include/mach/gpio.h +++ b/arch/arm/plat-omap/include/plat/gpio.h | |||
@@ -76,7 +76,8 @@ extern void omap2_gpio_prepare_for_retention(void); | |||
76 | extern void omap2_gpio_resume_after_retention(void); | 76 | extern void omap2_gpio_resume_after_retention(void); |
77 | extern void omap_set_gpio_debounce(int gpio, int enable); | 77 | extern void omap_set_gpio_debounce(int gpio, int enable); |
78 | extern void omap_set_gpio_debounce_time(int gpio, int enable); | 78 | extern void omap_set_gpio_debounce_time(int gpio, int enable); |
79 | 79 | extern void omap_gpio_save_context(void); | |
80 | extern void omap_gpio_restore_context(void); | ||
80 | /*-------------------------------------------------------------------------*/ | 81 | /*-------------------------------------------------------------------------*/ |
81 | 82 | ||
82 | /* Wrappers for "new style" GPIO calls, using the new infrastructure | 83 | /* Wrappers for "new style" GPIO calls, using the new infrastructure |
diff --git a/arch/arm/plat-omap/include/mach/gpmc-smc91x.h b/arch/arm/plat-omap/include/plat/gpmc-smc91x.h index b64fbee4d567..b64fbee4d567 100644 --- a/arch/arm/plat-omap/include/mach/gpmc-smc91x.h +++ b/arch/arm/plat-omap/include/plat/gpmc-smc91x.h | |||
diff --git a/arch/arm/plat-omap/include/mach/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h index 9c99cda77ba6..696e0ca051b7 100644 --- a/arch/arm/plat-omap/include/mach/gpmc.h +++ b/arch/arm/plat-omap/include/plat/gpmc.h | |||
@@ -52,6 +52,7 @@ | |||
52 | #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1)) | 52 | #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1)) |
53 | #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2)) | 53 | #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2)) |
54 | #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3)) | 54 | #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3)) |
55 | #define GPMC_CONFIG7_CSVALID (1 << 6) | ||
55 | 56 | ||
56 | /* | 57 | /* |
57 | * Note that all values in this struct are in nanoseconds, while | 58 | * Note that all values in this struct are in nanoseconds, while |
@@ -107,6 +108,8 @@ extern int gpmc_prefetch_enable(int cs, int dma_mode, | |||
107 | unsigned int u32_count, int is_write); | 108 | unsigned int u32_count, int is_write); |
108 | extern void gpmc_prefetch_reset(void); | 109 | extern void gpmc_prefetch_reset(void); |
109 | extern int gpmc_prefetch_status(void); | 110 | extern int gpmc_prefetch_status(void); |
111 | extern void omap3_gpmc_save_context(void); | ||
112 | extern void omap3_gpmc_restore_context(void); | ||
110 | extern void __init gpmc_init(void); | 113 | extern void __init gpmc_init(void); |
111 | 114 | ||
112 | #endif | 115 | #endif |
diff --git a/arch/arm/plat-omap/include/mach/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h index 26c1fbff08aa..d5b26adfb890 100644 --- a/arch/arm/plat-omap/include/mach/hardware.h +++ b/arch/arm/plat-omap/include/plat/hardware.h | |||
@@ -39,9 +39,9 @@ | |||
39 | #include <asm/sizes.h> | 39 | #include <asm/sizes.h> |
40 | #ifndef __ASSEMBLER__ | 40 | #ifndef __ASSEMBLER__ |
41 | #include <asm/types.h> | 41 | #include <asm/types.h> |
42 | #include <mach/cpu.h> | 42 | #include <plat/cpu.h> |
43 | #endif | 43 | #endif |
44 | #include <mach/serial.h> | 44 | #include <plat/serial.h> |
45 | 45 | ||
46 | /* | 46 | /* |
47 | * --------------------------------------------------------------------------- | 47 | * --------------------------------------------------------------------------- |
@@ -280,11 +280,11 @@ | |||
280 | * --------------------------------------------------------------------------- | 280 | * --------------------------------------------------------------------------- |
281 | */ | 281 | */ |
282 | 282 | ||
283 | #include "omap730.h" | 283 | #include <plat/omap7xx.h> |
284 | #include "omap1510.h" | 284 | #include <plat/omap1510.h> |
285 | #include "omap16xx.h" | 285 | #include <plat/omap16xx.h> |
286 | #include "omap24xx.h" | 286 | #include <plat/omap24xx.h> |
287 | #include "omap34xx.h" | 287 | #include <plat/omap34xx.h> |
288 | #include "omap44xx.h" | 288 | #include <plat/omap44xx.h> |
289 | 289 | ||
290 | #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ | 290 | #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ |
diff --git a/arch/arm/plat-omap/include/mach/hwa742.h b/arch/arm/plat-omap/include/plat/hwa742.h index 886248d32b49..886248d32b49 100644 --- a/arch/arm/plat-omap/include/mach/hwa742.h +++ b/arch/arm/plat-omap/include/plat/hwa742.h | |||
diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/plat/io.h index 8d32df32b0b1..7e5319f907d1 100644 --- a/arch/arm/plat-omap/include/mach/io.h +++ b/arch/arm/plat-omap/include/plat/io.h | |||
@@ -63,8 +63,24 @@ | |||
63 | #define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */ | 63 | #define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */ |
64 | #define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET) | 64 | #define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET) |
65 | 65 | ||
66 | #define OMAP2_IO_OFFSET 0x90000000 | 66 | #define OMAP2_L3_IO_OFFSET 0x90000000 |
67 | #define OMAP2_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_IO_OFFSET) /* L3 and L4 */ | 67 | #define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */ |
68 | |||
69 | |||
70 | #define OMAP2_L4_IO_OFFSET 0xb2000000 | ||
71 | #define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */ | ||
72 | |||
73 | #define OMAP4_L3_IO_OFFSET 0xb4000000 | ||
74 | #define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */ | ||
75 | |||
76 | #define OMAP4_L3_PER_IO_OFFSET 0xb1100000 | ||
77 | #define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET) | ||
78 | |||
79 | #define OMAP4_GPMC_IO_OFFSET 0xa9000000 | ||
80 | #define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET) | ||
81 | |||
82 | #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */ | ||
83 | #define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET) | ||
68 | 84 | ||
69 | /* | 85 | /* |
70 | * ---------------------------------------------------------------------------- | 86 | * ---------------------------------------------------------------------------- |
@@ -83,24 +99,27 @@ | |||
83 | */ | 99 | */ |
84 | 100 | ||
85 | /* We map both L3 and L4 on OMAP2 */ | 101 | /* We map both L3 and L4 on OMAP2 */ |
86 | #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 */ | 102 | #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/ |
87 | #define L3_24XX_VIRT 0xf8000000 | 103 | #define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET) |
88 | #define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ | 104 | #define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ |
89 | #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 */ | 105 | #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */ |
90 | #define L4_24XX_VIRT 0xd8000000 | 106 | #define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET) |
91 | #define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */ | 107 | #define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */ |
92 | 108 | ||
93 | #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 */ | 109 | #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */ |
94 | #define L4_WK_243X_VIRT 0xd9000000 | 110 | #define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET) |
95 | #define L4_WK_243X_SIZE SZ_1M | 111 | #define L4_WK_243X_SIZE SZ_1M |
96 | #define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE /* 0x49000000 */ | 112 | #define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE |
97 | #define OMAP243X_GPMC_VIRT 0xFE000000 | 113 | #define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET) |
114 | /* 0x6e000000 --> 0xfe000000 */ | ||
98 | #define OMAP243X_GPMC_SIZE SZ_1M | 115 | #define OMAP243X_GPMC_SIZE SZ_1M |
99 | #define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE | 116 | #define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE |
100 | #define OMAP243X_SDRC_VIRT 0xFD000000 | 117 | /* 0x6D000000 --> 0xfd000000 */ |
118 | #define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET) | ||
101 | #define OMAP243X_SDRC_SIZE SZ_1M | 119 | #define OMAP243X_SDRC_SIZE SZ_1M |
102 | #define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE | 120 | #define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE |
103 | #define OMAP243X_SMS_VIRT 0xFC000000 | 121 | /* 0x6c000000 --> 0xfc000000 */ |
122 | #define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET) | ||
104 | #define OMAP243X_SMS_SIZE SZ_1M | 123 | #define OMAP243X_SMS_SIZE SZ_1M |
105 | 124 | ||
106 | /* DSP */ | 125 | /* DSP */ |
@@ -121,12 +140,12 @@ | |||
121 | */ | 140 | */ |
122 | 141 | ||
123 | /* We map both L3 and L4 on OMAP3 */ | 142 | /* We map both L3 and L4 on OMAP3 */ |
124 | #define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 */ | 143 | #define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 --> 0xf8000000 */ |
125 | #define L3_34XX_VIRT 0xf8000000 | 144 | #define L3_34XX_VIRT (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET) |
126 | #define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ | 145 | #define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ |
127 | 146 | ||
128 | #define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 */ | 147 | #define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 --> 0xfa000000 */ |
129 | #define L4_34XX_VIRT 0xd8000000 | 148 | #define L4_34XX_VIRT (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET) |
130 | #define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */ | 149 | #define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */ |
131 | 150 | ||
132 | /* | 151 | /* |
@@ -134,28 +153,33 @@ | |||
134 | * VPOM3430 was not working for Int controller | 153 | * VPOM3430 was not working for Int controller |
135 | */ | 154 | */ |
136 | 155 | ||
137 | #define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 */ | 156 | #define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 --> 0xfa300000 */ |
138 | #define L4_WK_34XX_VIRT 0xd8300000 | 157 | #define L4_WK_34XX_VIRT (L4_WK_34XX_PHYS + OMAP2_L4_IO_OFFSET) |
139 | #define L4_WK_34XX_SIZE SZ_1M | 158 | #define L4_WK_34XX_SIZE SZ_1M |
140 | 159 | ||
141 | #define L4_PER_34XX_PHYS L4_PER_34XX_BASE /* 0x49000000 */ | 160 | #define L4_PER_34XX_PHYS L4_PER_34XX_BASE |
142 | #define L4_PER_34XX_VIRT 0xd9000000 | 161 | /* 0x49000000 --> 0xfb000000 */ |
162 | #define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET) | ||
143 | #define L4_PER_34XX_SIZE SZ_1M | 163 | #define L4_PER_34XX_SIZE SZ_1M |
144 | 164 | ||
145 | #define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE /* 0x54000000 */ | 165 | #define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE |
146 | #define L4_EMU_34XX_VIRT 0xe4000000 | 166 | /* 0x54000000 --> 0xfe800000 */ |
147 | #define L4_EMU_34XX_SIZE SZ_64M | 167 | #define L4_EMU_34XX_VIRT (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET) |
168 | #define L4_EMU_34XX_SIZE SZ_8M | ||
148 | 169 | ||
149 | #define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE /* 0x6E000000 */ | 170 | #define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE |
150 | #define OMAP34XX_GPMC_VIRT 0xFE000000 | 171 | /* 0x6e000000 --> 0xfe000000 */ |
172 | #define OMAP34XX_GPMC_VIRT (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET) | ||
151 | #define OMAP34XX_GPMC_SIZE SZ_1M | 173 | #define OMAP34XX_GPMC_SIZE SZ_1M |
152 | 174 | ||
153 | #define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE /* 0x6C000000 */ | 175 | #define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE |
154 | #define OMAP343X_SMS_VIRT 0xFC000000 | 176 | /* 0x6c000000 --> 0xfc000000 */ |
177 | #define OMAP343X_SMS_VIRT (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET) | ||
155 | #define OMAP343X_SMS_SIZE SZ_1M | 178 | #define OMAP343X_SMS_SIZE SZ_1M |
156 | 179 | ||
157 | #define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE /* 0x6D000000 */ | 180 | #define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE |
158 | #define OMAP343X_SDRC_VIRT 0xFD000000 | 181 | /* 0x6D000000 --> 0xfd000000 */ |
182 | #define OMAP343X_SDRC_VIRT (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET) | ||
159 | #define OMAP343X_SDRC_SIZE SZ_1M | 183 | #define OMAP343X_SDRC_SIZE SZ_1M |
160 | 184 | ||
161 | /* DSP */ | 185 | /* DSP */ |
@@ -176,32 +200,54 @@ | |||
176 | */ | 200 | */ |
177 | 201 | ||
178 | /* We map both L3 and L4 on OMAP4 */ | 202 | /* We map both L3 and L4 on OMAP4 */ |
179 | #define L3_44XX_PHYS L3_44XX_BASE | 203 | #define L3_44XX_PHYS L3_44XX_BASE /* 0x44000000 --> 0xf8000000 */ |
180 | #define L3_44XX_VIRT 0xd4000000 | 204 | #define L3_44XX_VIRT (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET) |
181 | #define L3_44XX_SIZE SZ_1M | 205 | #define L3_44XX_SIZE SZ_1M |
182 | 206 | ||
183 | #define L4_44XX_PHYS L4_44XX_BASE | 207 | #define L4_44XX_PHYS L4_44XX_BASE /* 0x4a000000 --> 0xfc000000 */ |
184 | #define L4_44XX_VIRT 0xda000000 | 208 | #define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET) |
185 | #define L4_44XX_SIZE SZ_4M | 209 | #define L4_44XX_SIZE SZ_4M |
186 | 210 | ||
187 | 211 | ||
188 | #define L4_WK_44XX_PHYS L4_WK_44XX_BASE | 212 | #define L4_WK_44XX_PHYS L4_WK_44XX_BASE /* 0x4a300000 --> 0xfc300000 */ |
189 | #define L4_WK_44XX_VIRT 0xda300000 | 213 | #define L4_WK_44XX_VIRT (L4_WK_44XX_PHYS + OMAP2_L4_IO_OFFSET) |
190 | #define L4_WK_44XX_SIZE SZ_1M | 214 | #define L4_WK_44XX_SIZE SZ_1M |
191 | 215 | ||
192 | #define L4_PER_44XX_PHYS L4_PER_44XX_BASE | 216 | #define L4_PER_44XX_PHYS L4_PER_44XX_BASE |
193 | #define L4_PER_44XX_VIRT 0xd8000000 | 217 | /* 0x48000000 --> 0xfa000000 */ |
218 | #define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET) | ||
194 | #define L4_PER_44XX_SIZE SZ_4M | 219 | #define L4_PER_44XX_SIZE SZ_4M |
195 | 220 | ||
221 | #define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE | ||
222 | /* 0x49000000 --> 0xfb000000 */ | ||
223 | #define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET) | ||
224 | #define L4_ABE_44XX_SIZE SZ_1M | ||
225 | |||
196 | #define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE | 226 | #define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE |
197 | #define L4_EMU_44XX_VIRT 0xe4000000 | 227 | /* 0x54000000 --> 0xfe800000 */ |
198 | #define L4_EMU_44XX_SIZE SZ_64M | 228 | #define L4_EMU_44XX_VIRT (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET) |
229 | #define L4_EMU_44XX_SIZE SZ_8M | ||
199 | 230 | ||
200 | #define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE | 231 | #define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE |
201 | #define OMAP44XX_GPMC_VIRT 0xe0000000 | 232 | /* 0x50000000 --> 0xf9000000 */ |
233 | #define OMAP44XX_GPMC_VIRT (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET) | ||
202 | #define OMAP44XX_GPMC_SIZE SZ_1M | 234 | #define OMAP44XX_GPMC_SIZE SZ_1M |
203 | 235 | ||
204 | 236 | ||
237 | #define OMAP44XX_EMIF1_PHYS OMAP44XX_EMIF1_BASE | ||
238 | /* 0x4c000000 --> 0xfd100000 */ | ||
239 | #define OMAP44XX_EMIF1_VIRT (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET) | ||
240 | #define OMAP44XX_EMIF1_SIZE SZ_1M | ||
241 | |||
242 | #define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE | ||
243 | /* 0x4d000000 --> 0xfd200000 */ | ||
244 | #define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET) | ||
245 | #define OMAP44XX_EMIF2_SIZE SZ_1M | ||
246 | |||
247 | #define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE | ||
248 | /* 0x4e000000 --> 0xfd300000 */ | ||
249 | #define OMAP44XX_DMM_VIRT (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET) | ||
250 | #define OMAP44XX_DMM_SIZE SZ_1M | ||
205 | /* | 251 | /* |
206 | * ---------------------------------------------------------------------------- | 252 | * ---------------------------------------------------------------------------- |
207 | * Omap specific register access | 253 | * Omap specific register access |
diff --git a/arch/arm/plat-omap/include/mach/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h index 46d41ac83dbf..0752af9d099e 100644 --- a/arch/arm/plat-omap/include/mach/iommu.h +++ b/arch/arm/plat-omap/include/plat/iommu.h | |||
@@ -107,7 +107,7 @@ struct iommu_platform_data { | |||
107 | #if defined(CONFIG_ARCH_OMAP1) | 107 | #if defined(CONFIG_ARCH_OMAP1) |
108 | #error "iommu for this processor not implemented yet" | 108 | #error "iommu for this processor not implemented yet" |
109 | #else | 109 | #else |
110 | #include <mach/iommu2.h> | 110 | #include <plat/iommu2.h> |
111 | #endif | 111 | #endif |
112 | 112 | ||
113 | /* | 113 | /* |
diff --git a/arch/arm/plat-omap/include/mach/iommu2.h b/arch/arm/plat-omap/include/plat/iommu2.h index 10ad05f410e9..10ad05f410e9 100644 --- a/arch/arm/plat-omap/include/mach/iommu2.h +++ b/arch/arm/plat-omap/include/plat/iommu2.h | |||
diff --git a/arch/arm/plat-omap/include/mach/iovmm.h b/arch/arm/plat-omap/include/plat/iovmm.h index bdc7ce5d7a4a..bdc7ce5d7a4a 100644 --- a/arch/arm/plat-omap/include/mach/iovmm.h +++ b/arch/arm/plat-omap/include/plat/iovmm.h | |||
diff --git a/arch/arm/plat-omap/include/mach/irda.h b/arch/arm/plat-omap/include/plat/irda.h index 40f60339d1c6..40f60339d1c6 100644 --- a/arch/arm/plat-omap/include/mach/irda.h +++ b/arch/arm/plat-omap/include/plat/irda.h | |||
diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h index 28a165058b61..ce5dd2d1dc21 100644 --- a/arch/arm/plat-omap/include/mach/irqs.h +++ b/arch/arm/plat-omap/include/plat/irqs.h | |||
@@ -86,49 +86,26 @@ | |||
86 | #define INT_1610_SSR_FIFO_0 29 | 86 | #define INT_1610_SSR_FIFO_0 29 |
87 | 87 | ||
88 | /* | 88 | /* |
89 | * OMAP-730 specific IRQ numbers for interrupt handler 1 | 89 | * OMAP-7xx specific IRQ numbers for interrupt handler 1 |
90 | */ | 90 | */ |
91 | #define INT_730_IH2_FIQ 0 | 91 | #define INT_7XX_IH2_FIQ 0 |
92 | #define INT_730_IH2_IRQ 1 | 92 | #define INT_7XX_IH2_IRQ 1 |
93 | #define INT_730_USB_NON_ISO 2 | 93 | #define INT_7XX_USB_NON_ISO 2 |
94 | #define INT_730_USB_ISO 3 | 94 | #define INT_7XX_USB_ISO 3 |
95 | #define INT_730_ICR 4 | 95 | #define INT_7XX_ICR 4 |
96 | #define INT_730_EAC 5 | 96 | #define INT_7XX_EAC 5 |
97 | #define INT_730_GPIO_BANK1 6 | 97 | #define INT_7XX_GPIO_BANK1 6 |
98 | #define INT_730_GPIO_BANK2 7 | 98 | #define INT_7XX_GPIO_BANK2 7 |
99 | #define INT_730_GPIO_BANK3 8 | 99 | #define INT_7XX_GPIO_BANK3 8 |
100 | #define INT_730_McBSP2TX 10 | 100 | #define INT_7XX_McBSP2TX 10 |
101 | #define INT_730_McBSP2RX 11 | 101 | #define INT_7XX_McBSP2RX 11 |
102 | #define INT_730_McBSP2RX_OVF 12 | 102 | #define INT_7XX_McBSP2RX_OVF 12 |
103 | #define INT_730_LCD_LINE 14 | 103 | #define INT_7XX_LCD_LINE 14 |
104 | #define INT_730_GSM_PROTECT 15 | 104 | #define INT_7XX_GSM_PROTECT 15 |
105 | #define INT_730_TIMER3 16 | 105 | #define INT_7XX_TIMER3 16 |
106 | #define INT_730_GPIO_BANK5 17 | 106 | #define INT_7XX_GPIO_BANK5 17 |
107 | #define INT_730_GPIO_BANK6 18 | 107 | #define INT_7XX_GPIO_BANK6 18 |
108 | #define INT_730_SPGIO_WR 29 | 108 | #define INT_7XX_SPGIO_WR 29 |
109 | |||
110 | /* | ||
111 | * OMAP-850 specific IRQ numbers for interrupt handler 1 | ||
112 | */ | ||
113 | #define INT_850_IH2_FIQ 0 | ||
114 | #define INT_850_IH2_IRQ 1 | ||
115 | #define INT_850_USB_NON_ISO 2 | ||
116 | #define INT_850_USB_ISO 3 | ||
117 | #define INT_850_ICR 4 | ||
118 | #define INT_850_EAC 5 | ||
119 | #define INT_850_GPIO_BANK1 6 | ||
120 | #define INT_850_GPIO_BANK2 7 | ||
121 | #define INT_850_GPIO_BANK3 8 | ||
122 | #define INT_850_McBSP2TX 10 | ||
123 | #define INT_850_McBSP2RX 11 | ||
124 | #define INT_850_McBSP2RX_OVF 12 | ||
125 | #define INT_850_LCD_LINE 14 | ||
126 | #define INT_850_GSM_PROTECT 15 | ||
127 | #define INT_850_TIMER3 16 | ||
128 | #define INT_850_GPIO_BANK5 17 | ||
129 | #define INT_850_GPIO_BANK6 18 | ||
130 | #define INT_850_SPGIO_WR 29 | ||
131 | |||
132 | 109 | ||
133 | /* | 110 | /* |
134 | * IRQ numbers for interrupt handler 2 | 111 | * IRQ numbers for interrupt handler 2 |
@@ -206,120 +183,62 @@ | |||
206 | #define INT_1610_SHA1MD5 (91 + IH2_BASE) | 183 | #define INT_1610_SHA1MD5 (91 + IH2_BASE) |
207 | 184 | ||
208 | /* | 185 | /* |
209 | * OMAP-730 specific IRQ numbers for interrupt handler 2 | 186 | * OMAP-7xx specific IRQ numbers for interrupt handler 2 |
210 | */ | 187 | */ |
211 | #define INT_730_HW_ERRORS (0 + IH2_BASE) | 188 | #define INT_7XX_HW_ERRORS (0 + IH2_BASE) |
212 | #define INT_730_NFIQ_PWR_FAIL (1 + IH2_BASE) | 189 | #define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE) |
213 | #define INT_730_CFCD (2 + IH2_BASE) | 190 | #define INT_7XX_CFCD (2 + IH2_BASE) |
214 | #define INT_730_CFIREQ (3 + IH2_BASE) | 191 | #define INT_7XX_CFIREQ (3 + IH2_BASE) |
215 | #define INT_730_I2C (4 + IH2_BASE) | 192 | #define INT_7XX_I2C (4 + IH2_BASE) |
216 | #define INT_730_PCC (5 + IH2_BASE) | 193 | #define INT_7XX_PCC (5 + IH2_BASE) |
217 | #define INT_730_MPU_EXT_NIRQ (6 + IH2_BASE) | 194 | #define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE) |
218 | #define INT_730_SPI_100K_1 (7 + IH2_BASE) | 195 | #define INT_7XX_SPI_100K_1 (7 + IH2_BASE) |
219 | #define INT_730_SYREN_SPI (8 + IH2_BASE) | 196 | #define INT_7XX_SYREN_SPI (8 + IH2_BASE) |
220 | #define INT_730_VLYNQ (9 + IH2_BASE) | 197 | #define INT_7XX_VLYNQ (9 + IH2_BASE) |
221 | #define INT_730_GPIO_BANK4 (10 + IH2_BASE) | 198 | #define INT_7XX_GPIO_BANK4 (10 + IH2_BASE) |
222 | #define INT_730_McBSP1TX (11 + IH2_BASE) | 199 | #define INT_7XX_McBSP1TX (11 + IH2_BASE) |
223 | #define INT_730_McBSP1RX (12 + IH2_BASE) | 200 | #define INT_7XX_McBSP1RX (12 + IH2_BASE) |
224 | #define INT_730_McBSP1RX_OF (13 + IH2_BASE) | 201 | #define INT_7XX_McBSP1RX_OF (13 + IH2_BASE) |
225 | #define INT_730_UART_MODEM_IRDA_2 (14 + IH2_BASE) | 202 | #define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE) |
226 | #define INT_730_UART_MODEM_1 (15 + IH2_BASE) | 203 | #define INT_7XX_UART_MODEM_1 (15 + IH2_BASE) |
227 | #define INT_730_MCSI (16 + IH2_BASE) | 204 | #define INT_7XX_MCSI (16 + IH2_BASE) |
228 | #define INT_730_uWireTX (17 + IH2_BASE) | 205 | #define INT_7XX_uWireTX (17 + IH2_BASE) |
229 | #define INT_730_uWireRX (18 + IH2_BASE) | 206 | #define INT_7XX_uWireRX (18 + IH2_BASE) |
230 | #define INT_730_SMC_CD (19 + IH2_BASE) | 207 | #define INT_7XX_SMC_CD (19 + IH2_BASE) |
231 | #define INT_730_SMC_IREQ (20 + IH2_BASE) | 208 | #define INT_7XX_SMC_IREQ (20 + IH2_BASE) |
232 | #define INT_730_HDQ_1WIRE (21 + IH2_BASE) | 209 | #define INT_7XX_HDQ_1WIRE (21 + IH2_BASE) |
233 | #define INT_730_TIMER32K (22 + IH2_BASE) | 210 | #define INT_7XX_TIMER32K (22 + IH2_BASE) |
234 | #define INT_730_MMC_SDIO (23 + IH2_BASE) | 211 | #define INT_7XX_MMC_SDIO (23 + IH2_BASE) |
235 | #define INT_730_UPLD (24 + IH2_BASE) | 212 | #define INT_7XX_UPLD (24 + IH2_BASE) |
236 | #define INT_730_USB_HHC_1 (27 + IH2_BASE) | 213 | #define INT_7XX_USB_HHC_1 (27 + IH2_BASE) |
237 | #define INT_730_USB_HHC_2 (28 + IH2_BASE) | 214 | #define INT_7XX_USB_HHC_2 (28 + IH2_BASE) |
238 | #define INT_730_USB_GENI (29 + IH2_BASE) | 215 | #define INT_7XX_USB_GENI (29 + IH2_BASE) |
239 | #define INT_730_USB_OTG (30 + IH2_BASE) | 216 | #define INT_7XX_USB_OTG (30 + IH2_BASE) |
240 | #define INT_730_CAMERA_IF (31 + IH2_BASE) | 217 | #define INT_7XX_CAMERA_IF (31 + IH2_BASE) |
241 | #define INT_730_RNG (32 + IH2_BASE) | 218 | #define INT_7XX_RNG (32 + IH2_BASE) |
242 | #define INT_730_DUAL_MODE_TIMER (33 + IH2_BASE) | 219 | #define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE) |
243 | #define INT_730_DBB_RF_EN (34 + IH2_BASE) | 220 | #define INT_7XX_DBB_RF_EN (34 + IH2_BASE) |
244 | #define INT_730_MPUIO_KEYPAD (35 + IH2_BASE) | 221 | #define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE) |
245 | #define INT_730_SHA1_MD5 (36 + IH2_BASE) | 222 | #define INT_7XX_SHA1_MD5 (36 + IH2_BASE) |
246 | #define INT_730_SPI_100K_2 (37 + IH2_BASE) | 223 | #define INT_7XX_SPI_100K_2 (37 + IH2_BASE) |
247 | #define INT_730_RNG_IDLE (38 + IH2_BASE) | 224 | #define INT_7XX_RNG_IDLE (38 + IH2_BASE) |
248 | #define INT_730_MPUIO (39 + IH2_BASE) | 225 | #define INT_7XX_MPUIO (39 + IH2_BASE) |
249 | #define INT_730_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) | 226 | #define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) |
250 | #define INT_730_LLPC_OE_FALLING (41 + IH2_BASE) | 227 | #define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE) |
251 | #define INT_730_LLPC_OE_RISING (42 + IH2_BASE) | 228 | #define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE) |
252 | #define INT_730_LLPC_VSYNC (43 + IH2_BASE) | 229 | #define INT_7XX_LLPC_VSYNC (43 + IH2_BASE) |
253 | #define INT_730_WAKE_UP_REQ (46 + IH2_BASE) | 230 | #define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE) |
254 | #define INT_730_DMA_CH6 (53 + IH2_BASE) | 231 | #define INT_7XX_DMA_CH6 (53 + IH2_BASE) |
255 | #define INT_730_DMA_CH7 (54 + IH2_BASE) | 232 | #define INT_7XX_DMA_CH7 (54 + IH2_BASE) |
256 | #define INT_730_DMA_CH8 (55 + IH2_BASE) | 233 | #define INT_7XX_DMA_CH8 (55 + IH2_BASE) |
257 | #define INT_730_DMA_CH9 (56 + IH2_BASE) | 234 | #define INT_7XX_DMA_CH9 (56 + IH2_BASE) |
258 | #define INT_730_DMA_CH10 (57 + IH2_BASE) | 235 | #define INT_7XX_DMA_CH10 (57 + IH2_BASE) |
259 | #define INT_730_DMA_CH11 (58 + IH2_BASE) | 236 | #define INT_7XX_DMA_CH11 (58 + IH2_BASE) |
260 | #define INT_730_DMA_CH12 (59 + IH2_BASE) | 237 | #define INT_7XX_DMA_CH12 (59 + IH2_BASE) |
261 | #define INT_730_DMA_CH13 (60 + IH2_BASE) | 238 | #define INT_7XX_DMA_CH13 (60 + IH2_BASE) |
262 | #define INT_730_DMA_CH14 (61 + IH2_BASE) | 239 | #define INT_7XX_DMA_CH14 (61 + IH2_BASE) |
263 | #define INT_730_DMA_CH15 (62 + IH2_BASE) | 240 | #define INT_7XX_DMA_CH15 (62 + IH2_BASE) |
264 | #define INT_730_NAND (63 + IH2_BASE) | 241 | #define INT_7XX_NAND (63 + IH2_BASE) |
265 | |||
266 | /* | ||
267 | * OMAP-850 specific IRQ numbers for interrupt handler 2 | ||
268 | */ | ||
269 | #define INT_850_HW_ERRORS (0 + IH2_BASE) | ||
270 | #define INT_850_NFIQ_PWR_FAIL (1 + IH2_BASE) | ||
271 | #define INT_850_CFCD (2 + IH2_BASE) | ||
272 | #define INT_850_CFIREQ (3 + IH2_BASE) | ||
273 | #define INT_850_I2C (4 + IH2_BASE) | ||
274 | #define INT_850_PCC (5 + IH2_BASE) | ||
275 | #define INT_850_MPU_EXT_NIRQ (6 + IH2_BASE) | ||
276 | #define INT_850_SPI_100K_1 (7 + IH2_BASE) | ||
277 | #define INT_850_SYREN_SPI (8 + IH2_BASE) | ||
278 | #define INT_850_VLYNQ (9 + IH2_BASE) | ||
279 | #define INT_850_GPIO_BANK4 (10 + IH2_BASE) | ||
280 | #define INT_850_McBSP1TX (11 + IH2_BASE) | ||
281 | #define INT_850_McBSP1RX (12 + IH2_BASE) | ||
282 | #define INT_850_McBSP1RX_OF (13 + IH2_BASE) | ||
283 | #define INT_850_UART_MODEM_IRDA_2 (14 + IH2_BASE) | ||
284 | #define INT_850_UART_MODEM_1 (15 + IH2_BASE) | ||
285 | #define INT_850_MCSI (16 + IH2_BASE) | ||
286 | #define INT_850_uWireTX (17 + IH2_BASE) | ||
287 | #define INT_850_uWireRX (18 + IH2_BASE) | ||
288 | #define INT_850_SMC_CD (19 + IH2_BASE) | ||
289 | #define INT_850_SMC_IREQ (20 + IH2_BASE) | ||
290 | #define INT_850_HDQ_1WIRE (21 + IH2_BASE) | ||
291 | #define INT_850_TIMER32K (22 + IH2_BASE) | ||
292 | #define INT_850_MMC_SDIO (23 + IH2_BASE) | ||
293 | #define INT_850_UPLD (24 + IH2_BASE) | ||
294 | #define INT_850_USB_HHC_1 (27 + IH2_BASE) | ||
295 | #define INT_850_USB_HHC_2 (28 + IH2_BASE) | ||
296 | #define INT_850_USB_GENI (29 + IH2_BASE) | ||
297 | #define INT_850_USB_OTG (30 + IH2_BASE) | ||
298 | #define INT_850_CAMERA_IF (31 + IH2_BASE) | ||
299 | #define INT_850_RNG (32 + IH2_BASE) | ||
300 | #define INT_850_DUAL_MODE_TIMER (33 + IH2_BASE) | ||
301 | #define INT_850_DBB_RF_EN (34 + IH2_BASE) | ||
302 | #define INT_850_MPUIO_KEYPAD (35 + IH2_BASE) | ||
303 | #define INT_850_SHA1_MD5 (36 + IH2_BASE) | ||
304 | #define INT_850_SPI_100K_2 (37 + IH2_BASE) | ||
305 | #define INT_850_RNG_IDLE (38 + IH2_BASE) | ||
306 | #define INT_850_MPUIO (39 + IH2_BASE) | ||
307 | #define INT_850_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) | ||
308 | #define INT_850_LLPC_OE_FALLING (41 + IH2_BASE) | ||
309 | #define INT_850_LLPC_OE_RISING (42 + IH2_BASE) | ||
310 | #define INT_850_LLPC_VSYNC (43 + IH2_BASE) | ||
311 | #define INT_850_WAKE_UP_REQ (46 + IH2_BASE) | ||
312 | #define INT_850_DMA_CH6 (53 + IH2_BASE) | ||
313 | #define INT_850_DMA_CH7 (54 + IH2_BASE) | ||
314 | #define INT_850_DMA_CH8 (55 + IH2_BASE) | ||
315 | #define INT_850_DMA_CH9 (56 + IH2_BASE) | ||
316 | #define INT_850_DMA_CH10 (57 + IH2_BASE) | ||
317 | #define INT_850_DMA_CH11 (58 + IH2_BASE) | ||
318 | #define INT_850_DMA_CH12 (59 + IH2_BASE) | ||
319 | #define INT_850_DMA_CH13 (60 + IH2_BASE) | ||
320 | #define INT_850_DMA_CH14 (61 + IH2_BASE) | ||
321 | #define INT_850_DMA_CH15 (62 + IH2_BASE) | ||
322 | #define INT_850_NAND (63 + IH2_BASE) | ||
323 | 242 | ||
324 | #define INT_24XX_SYS_NIRQ 7 | 243 | #define INT_24XX_SYS_NIRQ 7 |
325 | #define INT_24XX_SDMA_IRQ0 12 | 244 | #define INT_24XX_SDMA_IRQ0 12 |
@@ -558,9 +477,14 @@ | |||
558 | 477 | ||
559 | #define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) | 478 | #define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) |
560 | 479 | ||
480 | #define INTCPS_NR_MIR_REGS 3 | ||
481 | #define INTCPS_NR_IRQS 96 | ||
482 | |||
561 | #ifndef __ASSEMBLY__ | 483 | #ifndef __ASSEMBLY__ |
562 | extern void omap_init_irq(void); | 484 | extern void omap_init_irq(void); |
563 | extern int omap_irq_pending(void); | 485 | extern int omap_irq_pending(void); |
486 | void omap_intc_save_context(void); | ||
487 | void omap_intc_restore_context(void); | ||
564 | #endif | 488 | #endif |
565 | 489 | ||
566 | #include <mach/hardware.h> | 490 | #include <mach/hardware.h> |
diff --git a/arch/arm/plat-omap/include/mach/keypad.h b/arch/arm/plat-omap/include/plat/keypad.h index 3ae52ccc793c..3ae52ccc793c 100644 --- a/arch/arm/plat-omap/include/mach/keypad.h +++ b/arch/arm/plat-omap/include/plat/keypad.h | |||
diff --git a/arch/arm/plat-omap/include/mach/lcd_mipid.h b/arch/arm/plat-omap/include/plat/lcd_mipid.h index 8e52c6572281..8e52c6572281 100644 --- a/arch/arm/plat-omap/include/mach/lcd_mipid.h +++ b/arch/arm/plat-omap/include/plat/lcd_mipid.h | |||
diff --git a/arch/arm/plat-omap/include/mach/led.h b/arch/arm/plat-omap/include/plat/led.h index 25e451e7e2fd..25e451e7e2fd 100644 --- a/arch/arm/plat-omap/include/mach/led.h +++ b/arch/arm/plat-omap/include/plat/led.h | |||
diff --git a/arch/arm/plat-omap/include/mach/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h index b7a6991814ec..b7a6991814ec 100644 --- a/arch/arm/plat-omap/include/mach/mailbox.h +++ b/arch/arm/plat-omap/include/plat/mailbox.h | |||
diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index e0d6eca222cc..4f22e5bb7ff7 100644 --- a/arch/arm/plat-omap/include/mach/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h | |||
@@ -28,10 +28,10 @@ | |||
28 | #include <linux/spinlock.h> | 28 | #include <linux/spinlock.h> |
29 | 29 | ||
30 | #include <mach/hardware.h> | 30 | #include <mach/hardware.h> |
31 | #include <mach/clock.h> | 31 | #include <plat/clock.h> |
32 | 32 | ||
33 | #define OMAP730_MCBSP1_BASE 0xfffb1000 | 33 | #define OMAP7XX_MCBSP1_BASE 0xfffb1000 |
34 | #define OMAP730_MCBSP2_BASE 0xfffb1800 | 34 | #define OMAP7XX_MCBSP2_BASE 0xfffb1800 |
35 | 35 | ||
36 | #define OMAP1510_MCBSP1_BASE 0xe1011800 | 36 | #define OMAP1510_MCBSP1_BASE 0xe1011800 |
37 | #define OMAP1510_MCBSP2_BASE 0xfffb1000 | 37 | #define OMAP1510_MCBSP2_BASE 0xfffb1000 |
@@ -58,7 +58,7 @@ | |||
58 | #define OMAP44XX_MCBSP3_BASE 0x49026000 | 58 | #define OMAP44XX_MCBSP3_BASE 0x49026000 |
59 | #define OMAP44XX_MCBSP4_BASE 0x48074000 | 59 | #define OMAP44XX_MCBSP4_BASE 0x48074000 |
60 | 60 | ||
61 | #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) | 61 | #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
62 | 62 | ||
63 | #define OMAP_MCBSP_REG_DRR2 0x00 | 63 | #define OMAP_MCBSP_REG_DRR2 0x00 |
64 | #define OMAP_MCBSP_REG_DRR1 0x02 | 64 | #define OMAP_MCBSP_REG_DRR1 0x02 |
diff --git a/arch/arm/plat-omap/include/mach/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h index 1254e4945b6f..1254e4945b6f 100644 --- a/arch/arm/plat-omap/include/mach/mcspi.h +++ b/arch/arm/plat-omap/include/plat/mcspi.h | |||
diff --git a/arch/arm/plat-omap/include/mach/memory.h b/arch/arm/plat-omap/include/plat/memory.h index 9ad41dc484c1..9ad41dc484c1 100644 --- a/arch/arm/plat-omap/include/mach/memory.h +++ b/arch/arm/plat-omap/include/plat/memory.h | |||
diff --git a/arch/arm/plat-omap/include/mach/menelaus.h b/arch/arm/plat-omap/include/plat/menelaus.h index 3122bf68c7ce..3122bf68c7ce 100644 --- a/arch/arm/plat-omap/include/mach/menelaus.h +++ b/arch/arm/plat-omap/include/plat/menelaus.h | |||
diff --git a/arch/arm/plat-omap/include/mach/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index 7229b9593301..29937137bf3e 100644 --- a/arch/arm/plat-omap/include/mach/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h | |||
@@ -15,7 +15,7 @@ | |||
15 | #include <linux/device.h> | 15 | #include <linux/device.h> |
16 | #include <linux/mmc/host.h> | 16 | #include <linux/mmc/host.h> |
17 | 17 | ||
18 | #include <mach/board.h> | 18 | #include <plat/board.h> |
19 | 19 | ||
20 | #define OMAP15XX_NR_MMC 1 | 20 | #define OMAP15XX_NR_MMC 1 |
21 | #define OMAP16XX_NR_MMC 2 | 21 | #define OMAP16XX_NR_MMC 2 |
diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/plat/mux.h index 0f49d2d563d9..f3c1d8a90456 100644 --- a/arch/arm/plat-omap/include/mach/mux.h +++ b/arch/arm/plat-omap/include/plat/mux.h | |||
@@ -51,23 +51,13 @@ | |||
51 | .pu_pd_reg = PU_PD_SEL_##reg, \ | 51 | .pu_pd_reg = PU_PD_SEL_##reg, \ |
52 | .pu_pd_val = status, | 52 | .pu_pd_val = status, |
53 | 53 | ||
54 | #define MUX_REG_730(reg, mode_offset, mode) .mux_reg_name = "OMAP730_IO_CONF_"#reg, \ | 54 | #define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \ |
55 | .mux_reg = OMAP730_IO_CONF_##reg, \ | 55 | .mux_reg = OMAP7XX_IO_CONF_##reg, \ |
56 | .mask_offset = mode_offset, \ | 56 | .mask_offset = mode_offset, \ |
57 | .mask = mode, | 57 | .mask = mode, |
58 | 58 | ||
59 | #define PULL_REG_730(reg, bit, status) .pull_name = "OMAP730_IO_CONF_"#reg, \ | 59 | #define PULL_REG_7XX(reg, bit, status) .pull_name = "OMAP7XX_IO_CONF_"#reg, \ |
60 | .pull_reg = OMAP730_IO_CONF_##reg, \ | 60 | .pull_reg = OMAP7XX_IO_CONF_##reg, \ |
61 | .pull_bit = bit, \ | ||
62 | .pull_val = status, | ||
63 | |||
64 | #define MUX_REG_850(reg, mode_offset, mode) .mux_reg_name = "OMAP850_IO_CONF_"#reg, \ | ||
65 | .mux_reg = OMAP850_IO_CONF_##reg, \ | ||
66 | .mask_offset = mode_offset, \ | ||
67 | .mask = mode, | ||
68 | |||
69 | #define PULL_REG_850(reg, bit, status) .pull_name = "OMAP850_IO_CONF_"#reg, \ | ||
70 | .pull_reg = OMAP850_IO_CONF_##reg, \ | ||
71 | .pull_bit = bit, \ | 61 | .pull_bit = bit, \ |
72 | .pull_val = status, | 62 | .pull_val = status, |
73 | 63 | ||
@@ -84,21 +74,12 @@ | |||
84 | #define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \ | 74 | #define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \ |
85 | .pu_pd_val = status, | 75 | .pu_pd_val = status, |
86 | 76 | ||
87 | #define MUX_REG_730(reg, mode_offset, mode) \ | 77 | #define MUX_REG_7XX(reg, mode_offset, mode) \ |
88 | .mux_reg = OMAP730_IO_CONF_##reg, \ | 78 | .mux_reg = OMAP7XX_IO_CONF_##reg, \ |
89 | .mask_offset = mode_offset, \ | 79 | .mask_offset = mode_offset, \ |
90 | .mask = mode, | 80 | .mask = mode, |
91 | 81 | ||
92 | #define PULL_REG_730(reg, bit, status) .pull_reg = OMAP730_IO_CONF_##reg, \ | 82 | #define PULL_REG_7XX(reg, bit, status) .pull_reg = OMAP7XX_IO_CONF_##reg, \ |
93 | .pull_bit = bit, \ | ||
94 | .pull_val = status, | ||
95 | |||
96 | #define MUX_REG_850(reg, mode_offset, mode) \ | ||
97 | .mux_reg = OMAP850_IO_CONF_##reg, \ | ||
98 | .mask_offset = mode_offset, \ | ||
99 | .mask = mode, | ||
100 | |||
101 | #define PULL_REG_850(reg, bit, status) .pull_reg = OMAP850_IO_CONF_##reg, \ | ||
102 | .pull_bit = bit, \ | 83 | .pull_bit = bit, \ |
103 | .pull_val = status, | 84 | .pull_val = status, |
104 | 85 | ||
@@ -118,32 +99,21 @@ | |||
118 | 99 | ||
119 | /* | 100 | /* |
120 | * OMAP730/850 has a slightly different config for the pin mux. | 101 | * OMAP730/850 has a slightly different config for the pin mux. |
121 | * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and | 102 | * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and |
122 | * not the FUNC_MUX_CTRL_x regs from hardware.h | 103 | * not the FUNC_MUX_CTRL_x regs from hardware.h |
123 | * - for pull-up/down, only has one enable bit which is is in the same register | 104 | * - for pull-up/down, only has one enable bit which is is in the same register |
124 | * as mux config | 105 | * as mux config |
125 | */ | 106 | */ |
126 | #define MUX_CFG_730(desc, mux_reg, mode_offset, mode, \ | 107 | #define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \ |
127 | pull_bit, pull_status, debug_status)\ | 108 | pull_bit, pull_status, debug_status)\ |
128 | { \ | 109 | { \ |
129 | .name = desc, \ | 110 | .name = desc, \ |
130 | .debug = debug_status, \ | 111 | .debug = debug_status, \ |
131 | MUX_REG_730(mux_reg, mode_offset, mode) \ | 112 | MUX_REG_7XX(mux_reg, mode_offset, mode) \ |
132 | PULL_REG_730(mux_reg, pull_bit, pull_status) \ | 113 | PULL_REG_7XX(mux_reg, pull_bit, pull_status) \ |
133 | PU_PD_REG(NA, 0) \ | 114 | PU_PD_REG(NA, 0) \ |
134 | }, | 115 | }, |
135 | 116 | ||
136 | #define MUX_CFG_850(desc, mux_reg, mode_offset, mode, \ | ||
137 | pull_bit, pull_status, debug_status)\ | ||
138 | { \ | ||
139 | .name = desc, \ | ||
140 | .debug = debug_status, \ | ||
141 | MUX_REG_850(mux_reg, mode_offset, mode) \ | ||
142 | PULL_REG_850(mux_reg, pull_bit, pull_status) \ | ||
143 | PU_PD_REG(NA, 0) \ | ||
144 | }, | ||
145 | |||
146 | |||
147 | #define MUX_CFG_24XX(desc, reg_offset, mode, \ | 117 | #define MUX_CFG_24XX(desc, reg_offset, mode, \ |
148 | pull_en, pull_mode, dbg) \ | 118 | pull_en, pull_mode, dbg) \ |
149 | { \ | 119 | { \ |
@@ -232,45 +202,25 @@ struct pin_config { | |||
232 | 202 | ||
233 | }; | 203 | }; |
234 | 204 | ||
235 | enum omap730_index { | 205 | enum omap7xx_index { |
236 | /* OMAP 730 keyboard */ | 206 | /* OMAP 730 keyboard */ |
237 | E2_730_KBR0, | 207 | E2_7XX_KBR0, |
238 | J7_730_KBR1, | 208 | J7_7XX_KBR1, |
239 | E1_730_KBR2, | 209 | E1_7XX_KBR2, |
240 | F3_730_KBR3, | 210 | F3_7XX_KBR3, |
241 | D2_730_KBR4, | 211 | D2_7XX_KBR4, |
242 | C2_730_KBC0, | 212 | C2_7XX_KBC0, |
243 | D3_730_KBC1, | 213 | D3_7XX_KBC1, |
244 | E4_730_KBC2, | 214 | E4_7XX_KBC2, |
245 | F4_730_KBC3, | 215 | F4_7XX_KBC3, |
246 | E3_730_KBC4, | 216 | E3_7XX_KBC4, |
247 | |||
248 | /* USB */ | ||
249 | AA17_730_USB_DM, | ||
250 | W16_730_USB_PU_EN, | ||
251 | W17_730_USB_VBUSI, | ||
252 | }; | ||
253 | |||
254 | enum omap850_index { | ||
255 | /* OMAP 850 keyboard */ | ||
256 | E2_850_KBR0, | ||
257 | J7_850_KBR1, | ||
258 | E1_850_KBR2, | ||
259 | F3_850_KBR3, | ||
260 | D2_850_KBR4, | ||
261 | C2_850_KBC0, | ||
262 | D3_850_KBC1, | ||
263 | E4_850_KBC2, | ||
264 | F4_850_KBC3, | ||
265 | E3_850_KBC4, | ||
266 | 217 | ||
267 | /* USB */ | 218 | /* USB */ |
268 | AA17_850_USB_DM, | 219 | AA17_7XX_USB_DM, |
269 | W16_850_USB_PU_EN, | 220 | W16_7XX_USB_PU_EN, |
270 | W17_850_USB_VBUSI, | 221 | W17_7XX_USB_VBUSI, |
271 | }; | 222 | }; |
272 | 223 | ||
273 | |||
274 | enum omap1xxx_index { | 224 | enum omap1xxx_index { |
275 | /* UART1 (BT_UART_GATING)*/ | 225 | /* UART1 (BT_UART_GATING)*/ |
276 | UART1_TX = 0, | 226 | UART1_TX = 0, |
diff --git a/arch/arm/plat-omap/include/mach/nand.h b/arch/arm/plat-omap/include/plat/nand.h index 631a7bed1eef..631a7bed1eef 100644 --- a/arch/arm/plat-omap/include/mach/nand.h +++ b/arch/arm/plat-omap/include/plat/nand.h | |||
diff --git a/arch/arm/plat-omap/include/mach/omap-alsa.h b/arch/arm/plat-omap/include/plat/omap-alsa.h index bdf30a0f87f2..b53055b390d0 100644 --- a/arch/arm/plat-omap/include/mach/omap-alsa.h +++ b/arch/arm/plat-omap/include/plat/omap-alsa.h | |||
@@ -40,10 +40,10 @@ | |||
40 | #ifndef __OMAP_ALSA_H | 40 | #ifndef __OMAP_ALSA_H |
41 | #define __OMAP_ALSA_H | 41 | #define __OMAP_ALSA_H |
42 | 42 | ||
43 | #include <mach/dma.h> | 43 | #include <plat/dma.h> |
44 | #include <sound/core.h> | 44 | #include <sound/core.h> |
45 | #include <sound/pcm.h> | 45 | #include <sound/pcm.h> |
46 | #include <mach/mcbsp.h> | 46 | #include <plat/mcbsp.h> |
47 | #include <linux/platform_device.h> | 47 | #include <linux/platform_device.h> |
48 | 48 | ||
49 | #define DMA_BUF_SIZE (1024 * 8) | 49 | #define DMA_BUF_SIZE (1024 * 8) |
diff --git a/arch/arm/plat-omap/include/mach/omap-pm.h b/arch/arm/plat-omap/include/plat/omap-pm.h index 3ee41d711492..3ee41d711492 100644 --- a/arch/arm/plat-omap/include/mach/omap-pm.h +++ b/arch/arm/plat-omap/include/plat/omap-pm.h | |||
diff --git a/arch/arm/plat-omap/include/mach/omap1510.h b/arch/arm/plat-omap/include/plat/omap1510.h index d24004668138..d24004668138 100644 --- a/arch/arm/plat-omap/include/mach/omap1510.h +++ b/arch/arm/plat-omap/include/plat/omap1510.h | |||
diff --git a/arch/arm/plat-omap/include/mach/omap16xx.h b/arch/arm/plat-omap/include/plat/omap16xx.h index 0e69b504c25f..0e69b504c25f 100644 --- a/arch/arm/plat-omap/include/mach/omap16xx.h +++ b/arch/arm/plat-omap/include/plat/omap16xx.h | |||
diff --git a/arch/arm/plat-omap/include/mach/omap24xx.h b/arch/arm/plat-omap/include/plat/omap24xx.h index 696edfc145a6..696edfc145a6 100644 --- a/arch/arm/plat-omap/include/mach/omap24xx.h +++ b/arch/arm/plat-omap/include/plat/omap24xx.h | |||
diff --git a/arch/arm/plat-omap/include/mach/omap34xx.h b/arch/arm/plat-omap/include/plat/omap34xx.h index f8d186a73712..f8d186a73712 100644 --- a/arch/arm/plat-omap/include/mach/omap34xx.h +++ b/arch/arm/plat-omap/include/plat/omap34xx.h | |||
diff --git a/arch/arm/plat-omap/include/mach/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h index b3ba5ac7b4a4..336189753671 100644 --- a/arch/arm/plat-omap/include/mach/omap44xx.h +++ b/arch/arm/plat-omap/include/plat/omap44xx.h | |||
@@ -22,6 +22,9 @@ | |||
22 | #define L4_PER_44XX_BASE 0x48000000 | 22 | #define L4_PER_44XX_BASE 0x48000000 |
23 | #define L4_EMU_44XX_BASE 0x54000000 | 23 | #define L4_EMU_44XX_BASE 0x54000000 |
24 | #define L3_44XX_BASE 0x44000000 | 24 | #define L3_44XX_BASE 0x44000000 |
25 | #define OMAP44XX_EMIF1_BASE 0x4c000000 | ||
26 | #define OMAP44XX_EMIF2_BASE 0x4d000000 | ||
27 | #define OMAP44XX_DMM_BASE 0x4e000000 | ||
25 | #define OMAP4430_32KSYNCT_BASE 0x4a304000 | 28 | #define OMAP4430_32KSYNCT_BASE 0x4a304000 |
26 | #define OMAP4430_CM_BASE 0x4a004000 | 29 | #define OMAP4430_CM_BASE 0x4a004000 |
27 | #define OMAP4430_PRM_BASE 0x48306000 | 30 | #define OMAP4430_PRM_BASE 0x48306000 |
@@ -33,14 +36,9 @@ | |||
33 | #define IRQ_SIR_IRQ 0x0040 | 36 | #define IRQ_SIR_IRQ 0x0040 |
34 | #define OMAP44XX_GIC_DIST_BASE 0x48241000 | 37 | #define OMAP44XX_GIC_DIST_BASE 0x48241000 |
35 | #define OMAP44XX_GIC_CPU_BASE 0x48240100 | 38 | #define OMAP44XX_GIC_CPU_BASE 0x48240100 |
36 | #define OMAP44XX_VA_GIC_CPU_BASE OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE) | ||
37 | #define OMAP44XX_SCU_BASE 0x48240000 | 39 | #define OMAP44XX_SCU_BASE 0x48240000 |
38 | #define OMAP44XX_VA_SCU_BASE OMAP2_IO_ADDRESS(OMAP44XX_SCU_BASE) | ||
39 | #define OMAP44XX_LOCAL_TWD_BASE 0x48240600 | 40 | #define OMAP44XX_LOCAL_TWD_BASE 0x48240600 |
40 | #define OMAP44XX_VA_LOCAL_TWD_BASE OMAP2_IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE) | ||
41 | #define OMAP44XX_LOCAL_TWD_SIZE 0x00000100 | ||
42 | #define OMAP44XX_WKUPGEN_BASE 0x48281000 | 41 | #define OMAP44XX_WKUPGEN_BASE 0x48281000 |
43 | #define OMAP44XX_VA_WKUPGEN_BASE OMAP2_IO_ADDRESS(OMAP44XX_WKUPGEN_BASE) | ||
44 | 42 | ||
45 | #endif /* __ASM_ARCH_OMAP44XX_H */ | 43 | #endif /* __ASM_ARCH_OMAP44XX_H */ |
46 | 44 | ||
diff --git a/arch/arm/plat-omap/include/mach/omap730.h b/arch/arm/plat-omap/include/plat/omap730.h index 14272bc1a6fd..14272bc1a6fd 100644 --- a/arch/arm/plat-omap/include/mach/omap730.h +++ b/arch/arm/plat-omap/include/plat/omap730.h | |||
diff --git a/arch/arm/plat-omap/include/plat/omap7xx.h b/arch/arm/plat-omap/include/plat/omap7xx.h new file mode 100644 index 000000000000..53f52414b0e9 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/omap7xx.h | |||
@@ -0,0 +1,104 @@ | |||
1 | /* arch/arm/plat-omap/include/mach/omap7xx.h | ||
2 | * | ||
3 | * Hardware definitions for TI OMAP7XX processor. | ||
4 | * | ||
5 | * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> | ||
6 | * Adapted for omap850 by Zebediah C. McClure <zmc@lurian.net> | ||
7 | * Adapted for omap7xx by Alistair Buxton <a.j.buxton@gmail.com> | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify it | ||
10 | * under the terms of the GNU General Public License as published by the | ||
11 | * Free Software Foundation; either version 2 of the License, or (at your | ||
12 | * option) any later version. | ||
13 | * | ||
14 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
15 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
16 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
17 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
18 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
19 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
20 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
21 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
22 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
23 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
24 | * | ||
25 | * You should have received a copy of the GNU General Public License along | ||
26 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
27 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
28 | */ | ||
29 | |||
30 | #ifndef __ASM_ARCH_OMAP7XX_H | ||
31 | #define __ASM_ARCH_OMAP7XX_H | ||
32 | |||
33 | /* | ||
34 | * ---------------------------------------------------------------------------- | ||
35 | * Base addresses | ||
36 | * ---------------------------------------------------------------------------- | ||
37 | */ | ||
38 | |||
39 | /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ | ||
40 | |||
41 | #define OMAP7XX_DSP_BASE 0xE0000000 | ||
42 | #define OMAP7XX_DSP_SIZE 0x50000 | ||
43 | #define OMAP7XX_DSP_START 0xE0000000 | ||
44 | |||
45 | #define OMAP7XX_DSPREG_BASE 0xE1000000 | ||
46 | #define OMAP7XX_DSPREG_SIZE SZ_128K | ||
47 | #define OMAP7XX_DSPREG_START 0xE1000000 | ||
48 | |||
49 | /* | ||
50 | * ---------------------------------------------------------------------------- | ||
51 | * OMAP7XX specific configuration registers | ||
52 | * ---------------------------------------------------------------------------- | ||
53 | */ | ||
54 | #define OMAP7XX_CONFIG_BASE 0xfffe1000 | ||
55 | #define OMAP7XX_IO_CONF_0 0xfffe1070 | ||
56 | #define OMAP7XX_IO_CONF_1 0xfffe1074 | ||
57 | #define OMAP7XX_IO_CONF_2 0xfffe1078 | ||
58 | #define OMAP7XX_IO_CONF_3 0xfffe107c | ||
59 | #define OMAP7XX_IO_CONF_4 0xfffe1080 | ||
60 | #define OMAP7XX_IO_CONF_5 0xfffe1084 | ||
61 | #define OMAP7XX_IO_CONF_6 0xfffe1088 | ||
62 | #define OMAP7XX_IO_CONF_7 0xfffe108c | ||
63 | #define OMAP7XX_IO_CONF_8 0xfffe1090 | ||
64 | #define OMAP7XX_IO_CONF_9 0xfffe1094 | ||
65 | #define OMAP7XX_IO_CONF_10 0xfffe1098 | ||
66 | #define OMAP7XX_IO_CONF_11 0xfffe109c | ||
67 | #define OMAP7XX_IO_CONF_12 0xfffe10a0 | ||
68 | #define OMAP7XX_IO_CONF_13 0xfffe10a4 | ||
69 | |||
70 | #define OMAP7XX_MODE_1 0xfffe1010 | ||
71 | #define OMAP7XX_MODE_2 0xfffe1014 | ||
72 | |||
73 | /* CSMI specials: in terms of base + offset */ | ||
74 | #define OMAP7XX_MODE2_OFFSET 0x14 | ||
75 | |||
76 | /* | ||
77 | * ---------------------------------------------------------------------------- | ||
78 | * OMAP7XX traffic controller configuration registers | ||
79 | * ---------------------------------------------------------------------------- | ||
80 | */ | ||
81 | #define OMAP7XX_FLASH_CFG_0 0xfffecc10 | ||
82 | #define OMAP7XX_FLASH_ACFG_0 0xfffecc50 | ||
83 | #define OMAP7XX_FLASH_CFG_1 0xfffecc14 | ||
84 | #define OMAP7XX_FLASH_ACFG_1 0xfffecc54 | ||
85 | |||
86 | /* | ||
87 | * ---------------------------------------------------------------------------- | ||
88 | * OMAP7XX DSP control registers | ||
89 | * ---------------------------------------------------------------------------- | ||
90 | */ | ||
91 | #define OMAP7XX_ICR_BASE 0xfffbb800 | ||
92 | #define OMAP7XX_DSP_M_CTL 0xfffbb804 | ||
93 | #define OMAP7XX_DSP_MMU_BASE 0xfffed200 | ||
94 | |||
95 | /* | ||
96 | * ---------------------------------------------------------------------------- | ||
97 | * OMAP7XX PCC_UPLD configuration registers | ||
98 | * ---------------------------------------------------------------------------- | ||
99 | */ | ||
100 | #define OMAP7XX_PCC_UPLD_CTRL_BASE (0xfffe0900) | ||
101 | #define OMAP7XX_PCC_UPLD_CTRL (OMAP7XX_PCC_UPLD_CTRL_BASE + 0x00) | ||
102 | |||
103 | #endif /* __ASM_ARCH_OMAP7XX_H */ | ||
104 | |||
diff --git a/arch/arm/plat-omap/include/mach/omap850.h b/arch/arm/plat-omap/include/plat/omap850.h index c33f67981712..c33f67981712 100644 --- a/arch/arm/plat-omap/include/mach/omap850.h +++ b/arch/arm/plat-omap/include/plat/omap850.h | |||
diff --git a/arch/arm/plat-omap/include/mach/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h index bd0e136db337..11a9773a4e7f 100644 --- a/arch/arm/plat-omap/include/mach/omap_device.h +++ b/arch/arm/plat-omap/include/plat/omap_device.h | |||
@@ -34,7 +34,7 @@ | |||
34 | #include <linux/kernel.h> | 34 | #include <linux/kernel.h> |
35 | #include <linux/platform_device.h> | 35 | #include <linux/platform_device.h> |
36 | 36 | ||
37 | #include <mach/omap_hwmod.h> | 37 | #include <plat/omap_hwmod.h> |
38 | 38 | ||
39 | /* omap_device._state values */ | 39 | /* omap_device._state values */ |
40 | #define OMAP_DEVICE_STATE_UNKNOWN 0 | 40 | #define OMAP_DEVICE_STATE_UNKNOWN 0 |
diff --git a/arch/arm/plat-omap/include/mach/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 1f79c20e2929..dbdd123eca16 100644 --- a/arch/arm/plat-omap/include/mach/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h | |||
@@ -35,7 +35,7 @@ | |||
35 | #include <linux/kernel.h> | 35 | #include <linux/kernel.h> |
36 | #include <linux/ioport.h> | 36 | #include <linux/ioport.h> |
37 | 37 | ||
38 | #include <mach/cpu.h> | 38 | #include <plat/cpu.h> |
39 | 39 | ||
40 | struct omap_device; | 40 | struct omap_device; |
41 | 41 | ||
diff --git a/arch/arm/plat-omap/include/mach/omapfb.h b/arch/arm/plat-omap/include/plat/omapfb.h index b226bdf45739..bfef7ab95f17 100644 --- a/arch/arm/plat-omap/include/mach/omapfb.h +++ b/arch/arm/plat-omap/include/plat/omapfb.h | |||
@@ -168,7 +168,7 @@ enum omapfb_update_mode { | |||
168 | #include <linux/fb.h> | 168 | #include <linux/fb.h> |
169 | #include <linux/mutex.h> | 169 | #include <linux/mutex.h> |
170 | 170 | ||
171 | #include <mach/board.h> | 171 | #include <plat/board.h> |
172 | 172 | ||
173 | #define OMAP_LCDC_INV_VSYNC 0x0001 | 173 | #define OMAP_LCDC_INV_VSYNC 0x0001 |
174 | #define OMAP_LCDC_INV_HSYNC 0x0002 | 174 | #define OMAP_LCDC_INV_HSYNC 0x0002 |
diff --git a/arch/arm/plat-omap/include/mach/onenand.h b/arch/arm/plat-omap/include/plat/onenand.h index 72f433d7d827..72f433d7d827 100644 --- a/arch/arm/plat-omap/include/mach/onenand.h +++ b/arch/arm/plat-omap/include/plat/onenand.h | |||
diff --git a/arch/arm/plat-omap/include/mach/param.h b/arch/arm/plat-omap/include/plat/param.h index 1eb4dc326979..1eb4dc326979 100644 --- a/arch/arm/plat-omap/include/mach/param.h +++ b/arch/arm/plat-omap/include/plat/param.h | |||
diff --git a/arch/arm/plat-omap/include/mach/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h index fa6461423bd0..3d45ee1d3cf4 100644 --- a/arch/arm/plat-omap/include/mach/powerdomain.h +++ b/arch/arm/plat-omap/include/plat/powerdomain.h | |||
@@ -19,7 +19,7 @@ | |||
19 | 19 | ||
20 | #include <asm/atomic.h> | 20 | #include <asm/atomic.h> |
21 | 21 | ||
22 | #include <mach/cpu.h> | 22 | #include <plat/cpu.h> |
23 | 23 | ||
24 | 24 | ||
25 | /* Powerdomain basic power states */ | 25 | /* Powerdomain basic power states */ |
diff --git a/arch/arm/plat-omap/include/mach/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h index cda2a70397b4..e63e94e18975 100644 --- a/arch/arm/plat-omap/include/mach/prcm.h +++ b/arch/arm/plat-omap/include/plat/prcm.h | |||
@@ -27,9 +27,13 @@ u32 omap_prcm_get_reset_sources(void); | |||
27 | void omap_prcm_arch_reset(char mode); | 27 | void omap_prcm_arch_reset(char mode); |
28 | int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name); | 28 | int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name); |
29 | 29 | ||
30 | #endif | 30 | #define START_PADCONF_SAVE 0x2 |
31 | #define PADCONF_SAVE_DONE 0x1 | ||
31 | 32 | ||
33 | void omap3_prcm_save_context(void); | ||
34 | void omap3_prcm_restore_context(void); | ||
32 | 35 | ||
36 | #endif | ||
33 | 37 | ||
34 | 38 | ||
35 | 39 | ||
diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h index 1c09c78a48f2..f704030d2a70 100644 --- a/arch/arm/plat-omap/include/mach/sdrc.h +++ b/arch/arm/plat-omap/include/plat/sdrc.h | |||
@@ -44,6 +44,12 @@ | |||
44 | #define SDRC_RFR_CTRL_1 0x0D4 | 44 | #define SDRC_RFR_CTRL_1 0x0D4 |
45 | #define SDRC_MANUAL_1 0x0D8 | 45 | #define SDRC_MANUAL_1 0x0D8 |
46 | 46 | ||
47 | #define SDRC_POWER_AUTOCOUNT_SHIFT 8 | ||
48 | #define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT) | ||
49 | #define SDRC_POWER_CLKCTRL_SHIFT 4 | ||
50 | #define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT) | ||
51 | #define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT) | ||
52 | |||
47 | /* | 53 | /* |
48 | * These values represent the number of memory clock cycles between | 54 | * These values represent the number of memory clock cycles between |
49 | * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192 | 55 | * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192 |
@@ -80,11 +86,11 @@ | |||
80 | */ | 86 | */ |
81 | 87 | ||
82 | #define OMAP242X_SMS_REGADDR(reg) \ | 88 | #define OMAP242X_SMS_REGADDR(reg) \ |
83 | (void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE + reg) | 89 | (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg) |
84 | #define OMAP243X_SMS_REGADDR(reg) \ | 90 | #define OMAP243X_SMS_REGADDR(reg) \ |
85 | (void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE + reg) | 91 | (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg) |
86 | #define OMAP343X_SMS_REGADDR(reg) \ | 92 | #define OMAP343X_SMS_REGADDR(reg) \ |
87 | (void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE + reg) | 93 | (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg) |
88 | 94 | ||
89 | /* SMS register offsets - read/write with sms_{read,write}_reg() */ | 95 | /* SMS register offsets - read/write with sms_{read,write}_reg() */ |
90 | 96 | ||
@@ -120,6 +126,8 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, | |||
120 | int omap2_sdrc_get_params(unsigned long r, | 126 | int omap2_sdrc_get_params(unsigned long r, |
121 | struct omap_sdrc_params **sdrc_cs0, | 127 | struct omap_sdrc_params **sdrc_cs0, |
122 | struct omap_sdrc_params **sdrc_cs1); | 128 | struct omap_sdrc_params **sdrc_cs1); |
129 | void omap2_sms_save_context(void); | ||
130 | void omap2_sms_restore_context(void); | ||
123 | 131 | ||
124 | #ifdef CONFIG_ARCH_OMAP2 | 132 | #ifdef CONFIG_ARCH_OMAP2 |
125 | 133 | ||
diff --git a/arch/arm/plat-omap/include/mach/serial.h b/arch/arm/plat-omap/include/plat/serial.h index e249186d26e2..e249186d26e2 100644 --- a/arch/arm/plat-omap/include/mach/serial.h +++ b/arch/arm/plat-omap/include/plat/serial.h | |||
diff --git a/arch/arm/plat-omap/include/mach/smp.h b/arch/arm/plat-omap/include/plat/smp.h index dcaa8fde7063..dcaa8fde7063 100644 --- a/arch/arm/plat-omap/include/mach/smp.h +++ b/arch/arm/plat-omap/include/plat/smp.h | |||
diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/plat/sram.h index 8974e3fc2691..16a1b458d53c 100644 --- a/arch/arm/plat-omap/include/mach/sram.h +++ b/arch/arm/plat-omap/include/plat/sram.h | |||
@@ -27,6 +27,7 @@ extern u32 omap3_configure_core_dpll( | |||
27 | u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0, | 27 | u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0, |
28 | u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1, | 28 | u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1, |
29 | u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1); | 29 | u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1); |
30 | extern void omap3_sram_restore_context(void); | ||
30 | 31 | ||
31 | /* Do not use these */ | 32 | /* Do not use these */ |
32 | extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); | 33 | extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); |
@@ -68,4 +69,10 @@ extern u32 omap3_sram_configure_core_dpll( | |||
68 | u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1); | 69 | u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1); |
69 | extern unsigned long omap3_sram_configure_core_dpll_sz; | 70 | extern unsigned long omap3_sram_configure_core_dpll_sz; |
70 | 71 | ||
72 | #ifdef CONFIG_PM | ||
73 | extern void omap_push_sram_idle(void); | ||
74 | #else | ||
75 | static inline void omap_push_sram_idle(void) {} | ||
76 | #endif /* CONFIG_PM */ | ||
77 | |||
71 | #endif | 78 | #endif |
diff --git a/arch/arm/plat-omap/include/mach/system.h b/arch/arm/plat-omap/include/plat/system.h index ed8ec7477261..c58a4ef42a45 100644 --- a/arch/arm/plat-omap/include/mach/system.h +++ b/arch/arm/plat-omap/include/plat/system.h | |||
@@ -9,7 +9,7 @@ | |||
9 | #include <asm/mach-types.h> | 9 | #include <asm/mach-types.h> |
10 | #include <mach/hardware.h> | 10 | #include <mach/hardware.h> |
11 | 11 | ||
12 | #include <mach/prcm.h> | 12 | #include <plat/prcm.h> |
13 | 13 | ||
14 | #ifndef CONFIG_MACH_VOICEBLUE | 14 | #ifndef CONFIG_MACH_VOICEBLUE |
15 | #define voiceblue_reset() do {} while (0) | 15 | #define voiceblue_reset() do {} while (0) |
diff --git a/arch/arm/plat-omap/include/mach/tc.h b/arch/arm/plat-omap/include/plat/tc.h index d2fcd789bb9a..d2fcd789bb9a 100644 --- a/arch/arm/plat-omap/include/mach/tc.h +++ b/arch/arm/plat-omap/include/plat/tc.h | |||
diff --git a/arch/arm/plat-omap/include/mach/timer-gp.h b/arch/arm/plat-omap/include/plat/timer-gp.h index c88d346b59d9..c88d346b59d9 100644 --- a/arch/arm/plat-omap/include/mach/timer-gp.h +++ b/arch/arm/plat-omap/include/plat/timer-gp.h | |||
diff --git a/arch/arm/plat-omap/include/mach/timex.h b/arch/arm/plat-omap/include/plat/timex.h index 6d35767bc48f..6d35767bc48f 100644 --- a/arch/arm/plat-omap/include/mach/timex.h +++ b/arch/arm/plat-omap/include/plat/timex.h | |||
diff --git a/arch/arm/plat-omap/include/mach/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h index 0814c5f210c3..e22f57564b59 100644 --- a/arch/arm/plat-omap/include/mach/uncompress.h +++ b/arch/arm/plat-omap/include/plat/uncompress.h | |||
@@ -19,12 +19,13 @@ | |||
19 | 19 | ||
20 | #include <linux/types.h> | 20 | #include <linux/types.h> |
21 | #include <linux/serial_reg.h> | 21 | #include <linux/serial_reg.h> |
22 | #include <mach/serial.h> | 22 | #include <plat/serial.h> |
23 | 23 | ||
24 | unsigned int system_rev; | 24 | unsigned int system_rev; |
25 | 25 | ||
26 | #define UART_OMAP_MDR1 0x08 /* mode definition register */ | 26 | #define UART_OMAP_MDR1 0x08 /* mode definition register */ |
27 | #define OMAP_ID_730 0x355F | 27 | #define OMAP_ID_730 0x355F |
28 | #define OMAP_ID_850 0x362C | ||
28 | #define ID_MASK 0x7fff | 29 | #define ID_MASK 0x7fff |
29 | #define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0) | 30 | #define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0) |
30 | #define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK | 31 | #define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK |
@@ -53,7 +54,7 @@ static void putc(int c) | |||
53 | /* MMU is not on, so cpu_is_omapXXXX() won't work here */ | 54 | /* MMU is not on, so cpu_is_omapXXXX() won't work here */ |
54 | unsigned int omap_id = omap_get_id(); | 55 | unsigned int omap_id = omap_get_id(); |
55 | 56 | ||
56 | if (omap_id == OMAP_ID_730) | 57 | if (omap_id == OMAP_ID_730 || omap_id == OMAP_ID_850) |
57 | shift = 0; | 58 | shift = 0; |
58 | 59 | ||
59 | if (check_port(uart, shift)) | 60 | if (check_port(uart, shift)) |
diff --git a/arch/arm/plat-omap/include/mach/usb.h b/arch/arm/plat-omap/include/plat/usb.h index f337e1761e2c..33e72ca125d7 100644 --- a/arch/arm/plat-omap/include/mach/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h | |||
@@ -3,7 +3,7 @@ | |||
3 | #ifndef __ASM_ARCH_OMAP_USB_H | 3 | #ifndef __ASM_ARCH_OMAP_USB_H |
4 | #define __ASM_ARCH_OMAP_USB_H | 4 | #define __ASM_ARCH_OMAP_USB_H |
5 | 5 | ||
6 | #include <mach/board.h> | 6 | #include <plat/board.h> |
7 | 7 | ||
8 | /*-------------------------------------------------------------------------*/ | 8 | /*-------------------------------------------------------------------------*/ |
9 | 9 | ||
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c index b6defa23e77e..11f5d7961c73 100644 --- a/arch/arm/plat-omap/io.c +++ b/arch/arm/plat-omap/io.c | |||
@@ -13,12 +13,12 @@ | |||
13 | #include <linux/io.h> | 13 | #include <linux/io.h> |
14 | #include <linux/mm.h> | 14 | #include <linux/mm.h> |
15 | 15 | ||
16 | #include <mach/omap730.h> | 16 | #include <plat/omap7xx.h> |
17 | #include <mach/omap1510.h> | 17 | #include <plat/omap1510.h> |
18 | #include <mach/omap16xx.h> | 18 | #include <plat/omap16xx.h> |
19 | #include <mach/omap24xx.h> | 19 | #include <plat/omap24xx.h> |
20 | #include <mach/omap34xx.h> | 20 | #include <plat/omap34xx.h> |
21 | #include <mach/omap44xx.h> | 21 | #include <plat/omap44xx.h> |
22 | 22 | ||
23 | #define BETWEEN(p,st,sz) ((p) >= (st) && (p) < ((st) + (sz))) | 23 | #define BETWEEN(p,st,sz) ((p) >= (st) && (p) < ((st) + (sz))) |
24 | #define XLATE(p,pst,vst) ((void __iomem *)((p) - (pst) + (vst))) | 24 | #define XLATE(p,pst,vst) ((void __iomem *)((p) - (pst) + (vst))) |
@@ -33,13 +33,13 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type) | |||
33 | if (BETWEEN(p, OMAP1_IO_PHYS, OMAP1_IO_SIZE)) | 33 | if (BETWEEN(p, OMAP1_IO_PHYS, OMAP1_IO_SIZE)) |
34 | return XLATE(p, OMAP1_IO_PHYS, OMAP1_IO_VIRT); | 34 | return XLATE(p, OMAP1_IO_PHYS, OMAP1_IO_VIRT); |
35 | } | 35 | } |
36 | if (cpu_is_omap730()) { | 36 | if (cpu_is_omap7xx()) { |
37 | if (BETWEEN(p, OMAP730_DSP_BASE, OMAP730_DSP_SIZE)) | 37 | if (BETWEEN(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_SIZE)) |
38 | return XLATE(p, OMAP730_DSP_BASE, OMAP730_DSP_START); | 38 | return XLATE(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_START); |
39 | 39 | ||
40 | if (BETWEEN(p, OMAP730_DSPREG_BASE, OMAP730_DSPREG_SIZE)) | 40 | if (BETWEEN(p, OMAP7XX_DSPREG_BASE, OMAP7XX_DSPREG_SIZE)) |
41 | return XLATE(p, OMAP730_DSPREG_BASE, | 41 | return XLATE(p, OMAP7XX_DSPREG_BASE, |
42 | OMAP730_DSPREG_START); | 42 | OMAP7XX_DSPREG_START); |
43 | } | 43 | } |
44 | if (cpu_is_omap15xx()) { | 44 | if (cpu_is_omap15xx()) { |
45 | if (BETWEEN(p, OMAP1510_DSP_BASE, OMAP1510_DSP_SIZE)) | 45 | if (BETWEEN(p, OMAP1510_DSP_BASE, OMAP1510_DSP_SIZE)) |
@@ -114,6 +114,14 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type) | |||
114 | return XLATE(p, L4_WK_44XX_PHYS, L4_WK_44XX_VIRT); | 114 | return XLATE(p, L4_WK_44XX_PHYS, L4_WK_44XX_VIRT); |
115 | if (BETWEEN(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_SIZE)) | 115 | if (BETWEEN(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_SIZE)) |
116 | return XLATE(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_VIRT); | 116 | return XLATE(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_VIRT); |
117 | if (BETWEEN(p, OMAP44XX_EMIF1_PHYS, OMAP44XX_EMIF1_SIZE)) | ||
118 | return XLATE(p, OMAP44XX_EMIF1_PHYS, \ | ||
119 | OMAP44XX_EMIF1_VIRT); | ||
120 | if (BETWEEN(p, OMAP44XX_EMIF2_PHYS, OMAP44XX_EMIF2_SIZE)) | ||
121 | return XLATE(p, OMAP44XX_EMIF2_PHYS, \ | ||
122 | OMAP44XX_EMIF2_VIRT); | ||
123 | if (BETWEEN(p, OMAP44XX_DMM_PHYS, OMAP44XX_DMM_SIZE)) | ||
124 | return XLATE(p, OMAP44XX_DMM_PHYS, OMAP44XX_DMM_VIRT); | ||
117 | if (BETWEEN(p, L4_PER_44XX_PHYS, L4_PER_44XX_SIZE)) | 125 | if (BETWEEN(p, L4_PER_44XX_PHYS, L4_PER_44XX_SIZE)) |
118 | return XLATE(p, L4_PER_44XX_PHYS, L4_PER_44XX_VIRT); | 126 | return XLATE(p, L4_PER_44XX_PHYS, L4_PER_44XX_VIRT); |
119 | if (BETWEEN(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_SIZE)) | 127 | if (BETWEEN(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_SIZE)) |
@@ -142,7 +150,7 @@ u8 omap_readb(u32 pa) | |||
142 | if (cpu_class_is_omap1()) | 150 | if (cpu_class_is_omap1()) |
143 | return __raw_readb(OMAP1_IO_ADDRESS(pa)); | 151 | return __raw_readb(OMAP1_IO_ADDRESS(pa)); |
144 | else | 152 | else |
145 | return __raw_readb(OMAP2_IO_ADDRESS(pa)); | 153 | return __raw_readb(OMAP2_L4_IO_ADDRESS(pa)); |
146 | } | 154 | } |
147 | EXPORT_SYMBOL(omap_readb); | 155 | EXPORT_SYMBOL(omap_readb); |
148 | 156 | ||
@@ -151,7 +159,7 @@ u16 omap_readw(u32 pa) | |||
151 | if (cpu_class_is_omap1()) | 159 | if (cpu_class_is_omap1()) |
152 | return __raw_readw(OMAP1_IO_ADDRESS(pa)); | 160 | return __raw_readw(OMAP1_IO_ADDRESS(pa)); |
153 | else | 161 | else |
154 | return __raw_readw(OMAP2_IO_ADDRESS(pa)); | 162 | return __raw_readw(OMAP2_L4_IO_ADDRESS(pa)); |
155 | } | 163 | } |
156 | EXPORT_SYMBOL(omap_readw); | 164 | EXPORT_SYMBOL(omap_readw); |
157 | 165 | ||
@@ -160,7 +168,7 @@ u32 omap_readl(u32 pa) | |||
160 | if (cpu_class_is_omap1()) | 168 | if (cpu_class_is_omap1()) |
161 | return __raw_readl(OMAP1_IO_ADDRESS(pa)); | 169 | return __raw_readl(OMAP1_IO_ADDRESS(pa)); |
162 | else | 170 | else |
163 | return __raw_readl(OMAP2_IO_ADDRESS(pa)); | 171 | return __raw_readl(OMAP2_L4_IO_ADDRESS(pa)); |
164 | } | 172 | } |
165 | EXPORT_SYMBOL(omap_readl); | 173 | EXPORT_SYMBOL(omap_readl); |
166 | 174 | ||
@@ -169,7 +177,7 @@ void omap_writeb(u8 v, u32 pa) | |||
169 | if (cpu_class_is_omap1()) | 177 | if (cpu_class_is_omap1()) |
170 | __raw_writeb(v, OMAP1_IO_ADDRESS(pa)); | 178 | __raw_writeb(v, OMAP1_IO_ADDRESS(pa)); |
171 | else | 179 | else |
172 | __raw_writeb(v, OMAP2_IO_ADDRESS(pa)); | 180 | __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa)); |
173 | } | 181 | } |
174 | EXPORT_SYMBOL(omap_writeb); | 182 | EXPORT_SYMBOL(omap_writeb); |
175 | 183 | ||
@@ -178,7 +186,7 @@ void omap_writew(u16 v, u32 pa) | |||
178 | if (cpu_class_is_omap1()) | 186 | if (cpu_class_is_omap1()) |
179 | __raw_writew(v, OMAP1_IO_ADDRESS(pa)); | 187 | __raw_writew(v, OMAP1_IO_ADDRESS(pa)); |
180 | else | 188 | else |
181 | __raw_writew(v, OMAP2_IO_ADDRESS(pa)); | 189 | __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa)); |
182 | } | 190 | } |
183 | EXPORT_SYMBOL(omap_writew); | 191 | EXPORT_SYMBOL(omap_writew); |
184 | 192 | ||
@@ -187,6 +195,6 @@ void omap_writel(u32 v, u32 pa) | |||
187 | if (cpu_class_is_omap1()) | 195 | if (cpu_class_is_omap1()) |
188 | __raw_writel(v, OMAP1_IO_ADDRESS(pa)); | 196 | __raw_writel(v, OMAP1_IO_ADDRESS(pa)); |
189 | else | 197 | else |
190 | __raw_writel(v, OMAP2_IO_ADDRESS(pa)); | 198 | __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa)); |
191 | } | 199 | } |
192 | EXPORT_SYMBOL(omap_writel); | 200 | EXPORT_SYMBOL(omap_writel); |
diff --git a/arch/arm/plat-omap/iommu-debug.c b/arch/arm/plat-omap/iommu-debug.c index c799b3b0d709..afd1c27cff7c 100644 --- a/arch/arm/plat-omap/iommu-debug.c +++ b/arch/arm/plat-omap/iommu-debug.c | |||
@@ -17,8 +17,8 @@ | |||
17 | #include <linux/platform_device.h> | 17 | #include <linux/platform_device.h> |
18 | #include <linux/debugfs.h> | 18 | #include <linux/debugfs.h> |
19 | 19 | ||
20 | #include <mach/iommu.h> | 20 | #include <plat/iommu.h> |
21 | #include <mach/iovmm.h> | 21 | #include <plat/iovmm.h> |
22 | 22 | ||
23 | #include "iopgtable.h" | 23 | #include "iopgtable.h" |
24 | 24 | ||
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c index 94584f167a82..c0ff1e39d893 100644 --- a/arch/arm/plat-omap/iommu.c +++ b/arch/arm/plat-omap/iommu.c | |||
@@ -20,7 +20,7 @@ | |||
20 | 20 | ||
21 | #include <asm/cacheflush.h> | 21 | #include <asm/cacheflush.h> |
22 | 22 | ||
23 | #include <mach/iommu.h> | 23 | #include <plat/iommu.h> |
24 | 24 | ||
25 | #include "iopgtable.h" | 25 | #include "iopgtable.h" |
26 | 26 | ||
diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c index dc3fac3dd0ea..0ce36bbef9d2 100644 --- a/arch/arm/plat-omap/iovmm.c +++ b/arch/arm/plat-omap/iovmm.c | |||
@@ -18,8 +18,8 @@ | |||
18 | #include <asm/cacheflush.h> | 18 | #include <asm/cacheflush.h> |
19 | #include <asm/mach/map.h> | 19 | #include <asm/mach/map.h> |
20 | 20 | ||
21 | #include <mach/iommu.h> | 21 | #include <plat/iommu.h> |
22 | #include <mach/iovmm.h> | 22 | #include <plat/iovmm.h> |
23 | 23 | ||
24 | #include "iopgtable.h" | 24 | #include "iopgtable.h" |
25 | 25 | ||
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c index 40424edae939..734bff332c82 100644 --- a/arch/arm/plat-omap/mailbox.c +++ b/arch/arm/plat-omap/mailbox.c | |||
@@ -26,7 +26,7 @@ | |||
26 | #include <linux/device.h> | 26 | #include <linux/device.h> |
27 | #include <linux/delay.h> | 27 | #include <linux/delay.h> |
28 | 28 | ||
29 | #include <mach/mailbox.h> | 29 | #include <plat/mailbox.h> |
30 | 30 | ||
31 | static int enable_seq_bit; | 31 | static int enable_seq_bit; |
32 | module_param(enable_seq_bit, bool, 0); | 32 | module_param(enable_seq_bit, bool, 0); |
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index e664b912d7bb..92770334d728 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c | |||
@@ -24,8 +24,8 @@ | |||
24 | #include <linux/delay.h> | 24 | #include <linux/delay.h> |
25 | #include <linux/io.h> | 25 | #include <linux/io.h> |
26 | 26 | ||
27 | #include <mach/dma.h> | 27 | #include <plat/dma.h> |
28 | #include <mach/mcbsp.h> | 28 | #include <plat/mcbsp.h> |
29 | 29 | ||
30 | struct omap_mcbsp **mcbsp_ptr; | 30 | struct omap_mcbsp **mcbsp_ptr; |
31 | int omap_mcbsp_count; | 31 | int omap_mcbsp_count; |
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c index 8d329fb20740..05aebcad215b 100644 --- a/arch/arm/plat-omap/mux.c +++ b/arch/arm/plat-omap/mux.c | |||
@@ -28,7 +28,7 @@ | |||
28 | #include <linux/io.h> | 28 | #include <linux/io.h> |
29 | #include <asm/system.h> | 29 | #include <asm/system.h> |
30 | #include <linux/spinlock.h> | 30 | #include <linux/spinlock.h> |
31 | #include <mach/mux.h> | 31 | #include <plat/mux.h> |
32 | 32 | ||
33 | #ifdef CONFIG_OMAP_MUX | 33 | #ifdef CONFIG_OMAP_MUX |
34 | 34 | ||
diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c index e98f0a2a6c26..186bca82cfab 100644 --- a/arch/arm/plat-omap/omap-pm-noop.c +++ b/arch/arm/plat-omap/omap-pm-noop.c | |||
@@ -22,9 +22,9 @@ | |||
22 | #include <linux/device.h> | 22 | #include <linux/device.h> |
23 | 23 | ||
24 | /* Interface documentation is in mach/omap-pm.h */ | 24 | /* Interface documentation is in mach/omap-pm.h */ |
25 | #include <mach/omap-pm.h> | 25 | #include <plat/omap-pm.h> |
26 | 26 | ||
27 | #include <mach/powerdomain.h> | 27 | #include <plat/powerdomain.h> |
28 | 28 | ||
29 | struct omap_opp *dsp_opps; | 29 | struct omap_opp *dsp_opps; |
30 | struct omap_opp *mpu_opps; | 30 | struct omap_opp *mpu_opps; |
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c index 2c409fc6dd21..bb16e624a557 100644 --- a/arch/arm/plat-omap/omap_device.c +++ b/arch/arm/plat-omap/omap_device.c | |||
@@ -82,8 +82,8 @@ | |||
82 | #include <linux/err.h> | 82 | #include <linux/err.h> |
83 | #include <linux/io.h> | 83 | #include <linux/io.h> |
84 | 84 | ||
85 | #include <mach/omap_device.h> | 85 | #include <plat/omap_device.h> |
86 | #include <mach/omap_hwmod.h> | 86 | #include <plat/omap_hwmod.h> |
87 | 87 | ||
88 | /* These parameters are passed to _omap_device_{de,}activate() */ | 88 | /* These parameters are passed to _omap_device_{de,}activate() */ |
89 | #define USE_WAKEUP_LAT 0 | 89 | #define USE_WAKEUP_LAT 0 |
@@ -103,21 +103,6 @@ | |||
103 | /* Private functions */ | 103 | /* Private functions */ |
104 | 104 | ||
105 | /** | 105 | /** |
106 | * _read_32ksynct - read the OMAP 32K sync timer | ||
107 | * | ||
108 | * Returns the current value of the 32KiHz synchronization counter. | ||
109 | * XXX this should be generalized to simply read the system clocksource. | ||
110 | * XXX this should be moved to a separate synctimer32k.c file | ||
111 | */ | ||
112 | static u32 _read_32ksynct(void) | ||
113 | { | ||
114 | if (!cpu_class_is_omap2()) | ||
115 | BUG(); | ||
116 | |||
117 | return __raw_readl(OMAP2_IO_ADDRESS(OMAP_32KSYNCT_BASE + 0x010)); | ||
118 | } | ||
119 | |||
120 | /** | ||
121 | * _omap_device_activate - increase device readiness | 106 | * _omap_device_activate - increase device readiness |
122 | * @od: struct omap_device * | 107 | * @od: struct omap_device * |
123 | * @ignore_lat: increase to latency target (0) or full readiness (1)? | 108 | * @ignore_lat: increase to latency target (0) or full readiness (1)? |
@@ -133,13 +118,13 @@ static u32 _read_32ksynct(void) | |||
133 | */ | 118 | */ |
134 | static int _omap_device_activate(struct omap_device *od, u8 ignore_lat) | 119 | static int _omap_device_activate(struct omap_device *od, u8 ignore_lat) |
135 | { | 120 | { |
136 | u32 a, b; | 121 | struct timespec a, b, c; |
137 | 122 | ||
138 | pr_debug("omap_device: %s: activating\n", od->pdev.name); | 123 | pr_debug("omap_device: %s: activating\n", od->pdev.name); |
139 | 124 | ||
140 | while (od->pm_lat_level > 0) { | 125 | while (od->pm_lat_level > 0) { |
141 | struct omap_device_pm_latency *odpl; | 126 | struct omap_device_pm_latency *odpl; |
142 | int act_lat = 0; | 127 | unsigned long long act_lat = 0; |
143 | 128 | ||
144 | od->pm_lat_level--; | 129 | od->pm_lat_level--; |
145 | 130 | ||
@@ -149,20 +134,22 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat) | |||
149 | (od->dev_wakeup_lat <= od->_dev_wakeup_lat_limit)) | 134 | (od->dev_wakeup_lat <= od->_dev_wakeup_lat_limit)) |
150 | break; | 135 | break; |
151 | 136 | ||
152 | a = _read_32ksynct(); | 137 | getnstimeofday(&a); |
153 | 138 | ||
154 | /* XXX check return code */ | 139 | /* XXX check return code */ |
155 | odpl->activate_func(od); | 140 | odpl->activate_func(od); |
156 | 141 | ||
157 | b = _read_32ksynct(); | 142 | getnstimeofday(&b); |
158 | 143 | ||
159 | act_lat = (b - a) >> 15; /* 32KiHz cycles to microseconds */ | 144 | c = timespec_sub(b, a); |
145 | act_lat = timespec_to_ns(&c) * NSEC_PER_USEC; | ||
160 | 146 | ||
161 | pr_debug("omap_device: %s: pm_lat %d: activate: elapsed time " | 147 | pr_debug("omap_device: %s: pm_lat %d: activate: elapsed time " |
162 | "%d usec\n", od->pdev.name, od->pm_lat_level, act_lat); | 148 | "%llu usec\n", od->pdev.name, od->pm_lat_level, |
149 | act_lat); | ||
163 | 150 | ||
164 | WARN(act_lat > odpl->activate_lat, "omap_device: %s.%d: " | 151 | WARN(act_lat > odpl->activate_lat, "omap_device: %s.%d: " |
165 | "activate step %d took longer than expected (%d > %d)\n", | 152 | "activate step %d took longer than expected (%llu > %d)\n", |
166 | od->pdev.name, od->pdev.id, od->pm_lat_level, | 153 | od->pdev.name, od->pdev.id, od->pm_lat_level, |
167 | act_lat, odpl->activate_lat); | 154 | act_lat, odpl->activate_lat); |
168 | 155 | ||
@@ -188,13 +175,13 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat) | |||
188 | */ | 175 | */ |
189 | static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat) | 176 | static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat) |
190 | { | 177 | { |
191 | u32 a, b; | 178 | struct timespec a, b, c; |
192 | 179 | ||
193 | pr_debug("omap_device: %s: deactivating\n", od->pdev.name); | 180 | pr_debug("omap_device: %s: deactivating\n", od->pdev.name); |
194 | 181 | ||
195 | while (od->pm_lat_level < od->pm_lats_cnt) { | 182 | while (od->pm_lat_level < od->pm_lats_cnt) { |
196 | struct omap_device_pm_latency *odpl; | 183 | struct omap_device_pm_latency *odpl; |
197 | int deact_lat = 0; | 184 | unsigned long long deact_lat = 0; |
198 | 185 | ||
199 | odpl = od->pm_lats + od->pm_lat_level; | 186 | odpl = od->pm_lats + od->pm_lat_level; |
200 | 187 | ||
@@ -203,23 +190,24 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat) | |||
203 | od->_dev_wakeup_lat_limit)) | 190 | od->_dev_wakeup_lat_limit)) |
204 | break; | 191 | break; |
205 | 192 | ||
206 | a = _read_32ksynct(); | 193 | getnstimeofday(&a); |
207 | 194 | ||
208 | /* XXX check return code */ | 195 | /* XXX check return code */ |
209 | odpl->deactivate_func(od); | 196 | odpl->deactivate_func(od); |
210 | 197 | ||
211 | b = _read_32ksynct(); | 198 | getnstimeofday(&b); |
212 | 199 | ||
213 | deact_lat = (b - a) >> 15; /* 32KiHz cycles to microseconds */ | 200 | c = timespec_sub(b, a); |
201 | deact_lat = timespec_to_ns(&c) * NSEC_PER_USEC; | ||
214 | 202 | ||
215 | pr_debug("omap_device: %s: pm_lat %d: deactivate: elapsed time " | 203 | pr_debug("omap_device: %s: pm_lat %d: deactivate: elapsed time " |
216 | "%d usec\n", od->pdev.name, od->pm_lat_level, | 204 | "%llu usec\n", od->pdev.name, od->pm_lat_level, |
217 | deact_lat); | 205 | deact_lat); |
218 | 206 | ||
219 | WARN(deact_lat > odpl->deactivate_lat, "omap_device: %s.%d: " | 207 | WARN(deact_lat > odpl->deactivate_lat, "omap_device: %s.%d: " |
220 | "deactivate step %d took longer than expected (%d > %d)\n", | 208 | "deactivate step %d took longer than expected " |
221 | od->pdev.name, od->pdev.id, od->pm_lat_level, | 209 | "(%llu > %d)\n", od->pdev.name, od->pdev.id, |
222 | deact_lat, odpl->deactivate_lat); | 210 | od->pm_lat_level, deact_lat, odpl->deactivate_lat); |
223 | 211 | ||
224 | od->dev_wakeup_lat += odpl->activate_lat; | 212 | od->dev_wakeup_lat += odpl->activate_lat; |
225 | 213 | ||
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 75d1f26e5b17..3e923668778d 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c | |||
@@ -25,11 +25,11 @@ | |||
25 | 25 | ||
26 | #include <asm/mach/map.h> | 26 | #include <asm/mach/map.h> |
27 | 27 | ||
28 | #include <mach/sram.h> | 28 | #include <plat/sram.h> |
29 | #include <mach/board.h> | 29 | #include <plat/board.h> |
30 | #include <mach/cpu.h> | 30 | #include <plat/cpu.h> |
31 | 31 | ||
32 | #include <mach/control.h> | 32 | #include <plat/control.h> |
33 | 33 | ||
34 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) | 34 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
35 | # include "../mach-omap2/prm.h" | 35 | # include "../mach-omap2/prm.h" |
@@ -41,14 +41,14 @@ | |||
41 | #define OMAP1_SRAM_VA VMALLOC_END | 41 | #define OMAP1_SRAM_VA VMALLOC_END |
42 | #define OMAP2_SRAM_PA 0x40200000 | 42 | #define OMAP2_SRAM_PA 0x40200000 |
43 | #define OMAP2_SRAM_PUB_PA 0x4020f800 | 43 | #define OMAP2_SRAM_PUB_PA 0x4020f800 |
44 | #define OMAP2_SRAM_VA 0xe3000000 | 44 | #define OMAP2_SRAM_VA 0xfe400000 |
45 | #define OMAP2_SRAM_PUB_VA (OMAP2_SRAM_VA + 0x800) | 45 | #define OMAP2_SRAM_PUB_VA (OMAP2_SRAM_VA + 0x800) |
46 | #define OMAP3_SRAM_PA 0x40200000 | 46 | #define OMAP3_SRAM_PA 0x40200000 |
47 | #define OMAP3_SRAM_VA 0xe3000000 | 47 | #define OMAP3_SRAM_VA 0xfe400000 |
48 | #define OMAP3_SRAM_PUB_PA 0x40208000 | 48 | #define OMAP3_SRAM_PUB_PA 0x40208000 |
49 | #define OMAP3_SRAM_PUB_VA (OMAP3_SRAM_VA + 0x8000) | 49 | #define OMAP3_SRAM_PUB_VA (OMAP3_SRAM_VA + 0x8000) |
50 | #define OMAP4_SRAM_PA 0x40200000 /*0x402f0000*/ | 50 | #define OMAP4_SRAM_PA 0x40200000 /*0x402f0000*/ |
51 | #define OMAP4_SRAM_VA 0xd7000000 /*0xd70f0000*/ | 51 | #define OMAP4_SRAM_VA 0xfe400000 /*0xfe4f0000*/ |
52 | 52 | ||
53 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 53 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
54 | #define SRAM_BOOTLOADER_SZ 0x00 | 54 | #define SRAM_BOOTLOADER_SZ 0x00 |
@@ -56,16 +56,16 @@ | |||
56 | #define SRAM_BOOTLOADER_SZ 0x80 | 56 | #define SRAM_BOOTLOADER_SZ 0x80 |
57 | #endif | 57 | #endif |
58 | 58 | ||
59 | #define OMAP24XX_VA_REQINFOPERM0 OMAP2_IO_ADDRESS(0x68005048) | 59 | #define OMAP24XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68005048) |
60 | #define OMAP24XX_VA_READPERM0 OMAP2_IO_ADDRESS(0x68005050) | 60 | #define OMAP24XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68005050) |
61 | #define OMAP24XX_VA_WRITEPERM0 OMAP2_IO_ADDRESS(0x68005058) | 61 | #define OMAP24XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68005058) |
62 | 62 | ||
63 | #define OMAP34XX_VA_REQINFOPERM0 OMAP2_IO_ADDRESS(0x68012848) | 63 | #define OMAP34XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68012848) |
64 | #define OMAP34XX_VA_READPERM0 OMAP2_IO_ADDRESS(0x68012850) | 64 | #define OMAP34XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68012850) |
65 | #define OMAP34XX_VA_WRITEPERM0 OMAP2_IO_ADDRESS(0x68012858) | 65 | #define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858) |
66 | #define OMAP34XX_VA_ADDR_MATCH2 OMAP2_IO_ADDRESS(0x68012880) | 66 | #define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880) |
67 | #define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_IO_ADDRESS(0x6C000048) | 67 | #define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048) |
68 | #define OMAP34XX_VA_CONTROL_STAT OMAP2_IO_ADDRESS(0x480022F0) | 68 | #define OMAP34XX_VA_CONTROL_STAT OMAP2_L4_IO_ADDRESS(0x480022F0) |
69 | 69 | ||
70 | #define GP_DEVICE 0x300 | 70 | #define GP_DEVICE 0x300 |
71 | 71 | ||
@@ -396,22 +396,24 @@ u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc, | |||
396 | sdrc_actim_ctrl_b_1, sdrc_mr_1); | 396 | sdrc_actim_ctrl_b_1, sdrc_mr_1); |
397 | } | 397 | } |
398 | 398 | ||
399 | /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */ | 399 | #ifdef CONFIG_PM |
400 | void restore_sram_functions(void) | 400 | void omap3_sram_restore_context(void) |
401 | { | 401 | { |
402 | omap_sram_ceil = omap_sram_base + omap_sram_size; | 402 | omap_sram_ceil = omap_sram_base + omap_sram_size; |
403 | 403 | ||
404 | _omap3_sram_configure_core_dpll = | 404 | _omap3_sram_configure_core_dpll = |
405 | omap_sram_push(omap3_sram_configure_core_dpll, | 405 | omap_sram_push(omap3_sram_configure_core_dpll, |
406 | omap3_sram_configure_core_dpll_sz); | 406 | omap3_sram_configure_core_dpll_sz); |
407 | omap_push_sram_idle(); | ||
407 | } | 408 | } |
409 | #endif /* CONFIG_PM */ | ||
408 | 410 | ||
409 | int __init omap34xx_sram_init(void) | 411 | int __init omap34xx_sram_init(void) |
410 | { | 412 | { |
411 | _omap3_sram_configure_core_dpll = | 413 | _omap3_sram_configure_core_dpll = |
412 | omap_sram_push(omap3_sram_configure_core_dpll, | 414 | omap_sram_push(omap3_sram_configure_core_dpll, |
413 | omap3_sram_configure_core_dpll_sz); | 415 | omap3_sram_configure_core_dpll_sz); |
414 | 416 | omap_push_sram_idle(); | |
415 | return 0; | 417 | return 0; |
416 | } | 418 | } |
417 | #else | 419 | #else |
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c index 509f2ed99e21..0ea1e0beb455 100644 --- a/arch/arm/plat-omap/usb.c +++ b/arch/arm/plat-omap/usb.c | |||
@@ -33,10 +33,10 @@ | |||
33 | #include <asm/system.h> | 33 | #include <asm/system.h> |
34 | #include <mach/hardware.h> | 34 | #include <mach/hardware.h> |
35 | 35 | ||
36 | #include <mach/control.h> | 36 | #include <plat/control.h> |
37 | #include <mach/mux.h> | 37 | #include <plat/mux.h> |
38 | #include <mach/usb.h> | 38 | #include <plat/usb.h> |
39 | #include <mach/board.h> | 39 | #include <plat/board.h> |
40 | 40 | ||
41 | #ifdef CONFIG_ARCH_OMAP1 | 41 | #ifdef CONFIG_ARCH_OMAP1 |
42 | 42 | ||
@@ -614,8 +614,8 @@ omap_otg_init(struct omap_usb_config *config) | |||
614 | if (config->otg || config->register_host) { | 614 | if (config->otg || config->register_host) { |
615 | syscon &= ~HST_IDLE_EN; | 615 | syscon &= ~HST_IDLE_EN; |
616 | ohci_device.dev.platform_data = config; | 616 | ohci_device.dev.platform_data = config; |
617 | if (cpu_is_omap730()) | 617 | if (cpu_is_omap7xx()) |
618 | ohci_resources[1].start = INT_730_USB_HHC_1; | 618 | ohci_resources[1].start = INT_7XX_USB_HHC_1; |
619 | status = platform_device_register(&ohci_device); | 619 | status = platform_device_register(&ohci_device); |
620 | if (status) | 620 | if (status) |
621 | pr_debug("can't register OHCI device, %d\n", status); | 621 | pr_debug("can't register OHCI device, %d\n", status); |
@@ -626,8 +626,8 @@ omap_otg_init(struct omap_usb_config *config) | |||
626 | if (config->otg) { | 626 | if (config->otg) { |
627 | syscon &= ~OTG_IDLE_EN; | 627 | syscon &= ~OTG_IDLE_EN; |
628 | otg_device.dev.platform_data = config; | 628 | otg_device.dev.platform_data = config; |
629 | if (cpu_is_omap730()) | 629 | if (cpu_is_omap7xx()) |
630 | otg_resources[1].start = INT_730_USB_OTG; | 630 | otg_resources[1].start = INT_7XX_USB_OTG; |
631 | status = platform_device_register(&otg_device); | 631 | status = platform_device_register(&otg_device); |
632 | if (status) | 632 | if (status) |
633 | pr_debug("can't register OTG device, %d\n", status); | 633 | pr_debug("can't register OTG device, %d\n", status); |
@@ -731,7 +731,7 @@ static inline void omap_1510_usb_init(struct omap_usb_config *config) {} | |||
731 | 731 | ||
732 | void __init omap_usb_init(struct omap_usb_config *pdata) | 732 | void __init omap_usb_init(struct omap_usb_config *pdata) |
733 | { | 733 | { |
734 | if (cpu_is_omap730() || cpu_is_omap16xx() || cpu_is_omap24xx()) | 734 | if (cpu_is_omap7xx() || cpu_is_omap16xx() || cpu_is_omap24xx()) |
735 | omap_otg_init(pdata); | 735 | omap_otg_init(pdata); |
736 | else if (cpu_is_omap15xx()) | 736 | else if (cpu_is_omap15xx()) |
737 | omap_1510_usb_init(pdata); | 737 | omap_1510_usb_init(pdata); |