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authorGwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com>2013-11-28 02:19:31 -0500
committerShawn Guo <shawn.guo@linaro.org>2014-02-09 08:33:03 -0500
commit7672d8eb605bdd1feea5d3f85132b90154bb598d (patch)
tree49ae0ab2c1b4638bb9e0f39ca669e89013d6b0b2 /arch/arm
parent0c33f667020232fe3173c18c245f2200cbe8e4f5 (diff)
ARM: dts: imx27: imx27-apf27: add pinctrl for fec and uart1
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/imx27-apf27.dts38
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx27-apf27.dts b/arch/arm/boot/dts/imx27-apf27.dts
index ba4c6df08ece..09f57b39e3ef 100644
--- a/arch/arm/boot/dts/imx27-apf27.dts
+++ b/arch/arm/boot/dts/imx27-apf27.dts
@@ -34,11 +34,49 @@
34 }; 34 };
35}; 35};
36 36
37&iomuxc {
38 imx27-apf27 {
39 pinctrl_fec1: fec1grp {
40 fsl,pins = <
41 MX27_PAD_SD3_CMD__FEC_TXD0 0x0
42 MX27_PAD_SD3_CLK__FEC_TXD1 0x0
43 MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
44 MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
45 MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
46 MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
47 MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
48 MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
49 MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
50 MX27_PAD_ATA_DATA7__FEC_MDC 0x0
51 MX27_PAD_ATA_DATA8__FEC_CRS 0x0
52 MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
53 MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
54 MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
55 MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
56 MX27_PAD_ATA_DATA13__FEC_COL 0x0
57 MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
58 MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
59 >;
60 };
61
62 pinctrl_uart1: uart1grp {
63 fsl,pins = <
64 MX27_PAD_UART1_TXD__UART1_TXD 0x0
65 MX27_PAD_UART1_RXD__UART1_RXD 0x0
66 >;
67 };
68 };
69};
70
37&uart1 { 71&uart1 {
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_uart1>;
38 status = "okay"; 74 status = "okay";
39}; 75};
40 76
41&fec { 77&fec {
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_fec1>;
42 status = "okay"; 80 status = "okay";
43}; 81};
44 82