aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2012-03-30 20:31:56 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-03-30 20:31:56 -0400
commit623ff7739e7c00fa3d55dbfd42a492a68298fd7a (patch)
tree0b7461753a1b13b27ea2958a7d48c6efb47bba54 /arch/arm
parentc39e8ede284f469971589f2e04af78216e1a771d (diff)
parent7b0e67f604e1829e5292e1ad7743eb18dc42ea7c (diff)
Merge tag 'for-linus-3.4' of git://git.infradead.org/mtd-2.6
Pull MTD changes from David Woodhouse: - Artem's cleanup of the MTD API continues apace. - Fixes and improvements for ST FSMC and SuperH FLCTL NAND, amongst others. - More work on DiskOnChip G3, new driver for DiskOnChip G4. - Clean up debug/warning printks in JFFS2 to use pr_<level>. Fix up various trivial conflicts, largely due to changes in calling conventions for things like dmaengine_prep_slave_sg() (new inline wrapper to hide new parameter, clashing with rewrite of previously last parameter that used to be an 'append' flag, and is now a bitmap of 'unsigned long flags'). (Also some header file fallout - like so many merges this merge window - and silly conflicts with sparse fixes) * tag 'for-linus-3.4' of git://git.infradead.org/mtd-2.6: (120 commits) mtd: docg3 add protection against concurrency mtd: docg3 refactor cascade floors structure mtd: docg3 increase write/erase timeout mtd: docg3 fix inbound calculations mtd: nand: gpmi: fix function annotations mtd: phram: fix section mismatch for phram_setup mtd: unify initialization of erase_info->fail_addr mtd: support ONFI multi lun NAND mtd: sm_ftl: fix typo in major number. mtd: add device-tree support to spear_smi mtd: spear_smi: Remove default partition information from driver mtd: Add device-tree support to fsmc_nand mtd: fix section mismatch for doc_probe_device mtd: nand/fsmc: Remove sparse warnings and errors mtd: nand/fsmc: Add DMA support mtd: nand/fsmc: Access the NAND device word by word whenever possible mtd: nand/fsmc: Use dev_err to report error scenario mtd: nand/fsmc: Use devm routines mtd: nand/fsmc: Modify fsmc driver to accept nand timing parameters via platform mtd: fsmc_nand: add pm callbacks to support hibernation ...
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-mxs/include/mach/dma.h28
-rw-r--r--arch/arm/mach-omap1/flash.c20
-rw-r--r--arch/arm/mach-s3c24xx/simtec-nor.c3
-rw-r--r--arch/arm/mach-shmobile/board-mackerel.c71
-rw-r--r--arch/arm/mach-shmobile/clock-sh7372.c4
-rw-r--r--arch/arm/mach-u300/core.c2
-rw-r--r--arch/arm/mach-u300/include/mach/u300-regs.h5
7 files changed, 87 insertions, 46 deletions
diff --git a/arch/arm/mach-mxs/include/mach/dma.h b/arch/arm/mach-mxs/include/mach/dma.h
deleted file mode 100644
index 203d7c4a3e11..000000000000
--- a/arch/arm/mach-mxs/include/mach/dma.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __MACH_MXS_DMA_H__
10#define __MACH_MXS_DMA_H__
11
12#include <linux/dmaengine.h>
13
14struct mxs_dma_data {
15 int chan_irq;
16};
17
18static inline int mxs_dma_is_apbh(struct dma_chan *chan)
19{
20 return !strcmp(dev_name(chan->device->dev), "mxs-dma-apbh");
21}
22
23static inline int mxs_dma_is_apbx(struct dma_chan *chan)
24{
25 return !strcmp(dev_name(chan->device->dev), "mxs-dma-apbx");
26}
27
28#endif /* __MACH_MXS_DMA_H__ */
diff --git a/arch/arm/mach-omap1/flash.c b/arch/arm/mach-omap1/flash.c
index f9bf78d4fdfb..401eb3c080c2 100644
--- a/arch/arm/mach-omap1/flash.c
+++ b/arch/arm/mach-omap1/flash.c
@@ -17,20 +17,12 @@
17 17
18void omap1_set_vpp(struct platform_device *pdev, int enable) 18void omap1_set_vpp(struct platform_device *pdev, int enable)
19{ 19{
20 static int count;
21 u32 l; 20 u32 l;
22 21
23 if (enable) { 22 l = omap_readl(EMIFS_CONFIG);
24 if (count++ == 0) { 23 if (enable)
25 l = omap_readl(EMIFS_CONFIG); 24 l |= OMAP_EMIFS_CONFIG_WP;
26 l |= OMAP_EMIFS_CONFIG_WP; 25 else
27 omap_writel(l, EMIFS_CONFIG); 26 l &= ~OMAP_EMIFS_CONFIG_WP;
28 } 27 omap_writel(l, EMIFS_CONFIG);
29 } else {
30 if (count && (--count == 0)) {
31 l = omap_readl(EMIFS_CONFIG);
32 l &= ~OMAP_EMIFS_CONFIG_WP;
33 omap_writel(l, EMIFS_CONFIG);
34 }
35 }
36} 28}
diff --git a/arch/arm/mach-s3c24xx/simtec-nor.c b/arch/arm/mach-s3c24xx/simtec-nor.c
index 2119ca6a73bc..b9d6d4f92c03 100644
--- a/arch/arm/mach-s3c24xx/simtec-nor.c
+++ b/arch/arm/mach-s3c24xx/simtec-nor.c
@@ -35,9 +35,7 @@
35static void simtec_nor_vpp(struct platform_device *pdev, int vpp) 35static void simtec_nor_vpp(struct platform_device *pdev, int vpp)
36{ 36{
37 unsigned int val; 37 unsigned int val;
38 unsigned long flags;
39 38
40 local_irq_save(flags);
41 val = __raw_readb(BAST_VA_CTRL3); 39 val = __raw_readb(BAST_VA_CTRL3);
42 40
43 printk(KERN_DEBUG "%s(%d)\n", __func__, vpp); 41 printk(KERN_DEBUG "%s(%d)\n", __func__, vpp);
@@ -48,7 +46,6 @@ static void simtec_nor_vpp(struct platform_device *pdev, int vpp)
48 val &= ~BAST_CPLD_CTRL3_ROMWEN; 46 val &= ~BAST_CPLD_CTRL3_ROMWEN;
49 47
50 __raw_writeb(val, BAST_VA_CTRL3); 48 __raw_writeb(val, BAST_VA_CTRL3);
51 local_irq_restore(flags);
52} 49}
53 50
54static struct physmap_flash_data simtec_nor_pdata = { 51static struct physmap_flash_data simtec_nor_pdata = {
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index a125d4e114ec..f49e28abe0ab 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -39,6 +39,7 @@
39#include <linux/mtd/mtd.h> 39#include <linux/mtd/mtd.h>
40#include <linux/mtd/partitions.h> 40#include <linux/mtd/partitions.h>
41#include <linux/mtd/physmap.h> 41#include <linux/mtd/physmap.h>
42#include <linux/mtd/sh_flctl.h>
42#include <linux/pm_clock.h> 43#include <linux/pm_clock.h>
43#include <linux/smsc911x.h> 44#include <linux/smsc911x.h>
44#include <linux/sh_intc.h> 45#include <linux/sh_intc.h>
@@ -956,6 +957,50 @@ static struct platform_device fsi_ak4643_device = {
956 }, 957 },
957}; 958};
958 959
960/* FLCTL */
961static struct mtd_partition nand_partition_info[] = {
962 {
963 .name = "system",
964 .offset = 0,
965 .size = 128 * 1024 * 1024,
966 },
967 {
968 .name = "userdata",
969 .offset = MTDPART_OFS_APPEND,
970 .size = 256 * 1024 * 1024,
971 },
972 {
973 .name = "cache",
974 .offset = MTDPART_OFS_APPEND,
975 .size = 128 * 1024 * 1024,
976 },
977};
978
979static struct resource nand_flash_resources[] = {
980 [0] = {
981 .start = 0xe6a30000,
982 .end = 0xe6a3009b,
983 .flags = IORESOURCE_MEM,
984 }
985};
986
987static struct sh_flctl_platform_data nand_flash_data = {
988 .parts = nand_partition_info,
989 .nr_parts = ARRAY_SIZE(nand_partition_info),
990 .flcmncr_val = CLK_16B_12L_4H | TYPESEL_SET
991 | SHBUSSEL | SEL_16BIT | SNAND_E,
992 .use_holden = 1,
993};
994
995static struct platform_device nand_flash_device = {
996 .name = "sh_flctl",
997 .resource = nand_flash_resources,
998 .num_resources = ARRAY_SIZE(nand_flash_resources),
999 .dev = {
1000 .platform_data = &nand_flash_data,
1001 },
1002};
1003
959/* 1004/*
960 * The card detect pin of the top SD/MMC slot (CN7) is active low and is 1005 * The card detect pin of the top SD/MMC slot (CN7) is active low and is
961 * connected to GPIO A22 of SH7372 (GPIO_PORT41). 1006 * connected to GPIO A22 of SH7372 (GPIO_PORT41).
@@ -1259,6 +1304,7 @@ static struct platform_device *mackerel_devices[] __initdata = {
1259 &fsi_device, 1304 &fsi_device,
1260 &fsi_ak4643_device, 1305 &fsi_ak4643_device,
1261 &fsi_hdmi_device, 1306 &fsi_hdmi_device,
1307 &nand_flash_device,
1262 &sdhi0_device, 1308 &sdhi0_device,
1263#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) 1309#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
1264 &sdhi1_device, 1310 &sdhi1_device,
@@ -1488,6 +1534,30 @@ static void __init mackerel_init(void)
1488 gpio_request(GPIO_FN_MMCCMD0, NULL); 1534 gpio_request(GPIO_FN_MMCCMD0, NULL);
1489 gpio_request(GPIO_FN_MMCCLK0, NULL); 1535 gpio_request(GPIO_FN_MMCCLK0, NULL);
1490 1536
1537 /* FLCTL */
1538 gpio_request(GPIO_FN_D0_NAF0, NULL);
1539 gpio_request(GPIO_FN_D1_NAF1, NULL);
1540 gpio_request(GPIO_FN_D2_NAF2, NULL);
1541 gpio_request(GPIO_FN_D3_NAF3, NULL);
1542 gpio_request(GPIO_FN_D4_NAF4, NULL);
1543 gpio_request(GPIO_FN_D5_NAF5, NULL);
1544 gpio_request(GPIO_FN_D6_NAF6, NULL);
1545 gpio_request(GPIO_FN_D7_NAF7, NULL);
1546 gpio_request(GPIO_FN_D8_NAF8, NULL);
1547 gpio_request(GPIO_FN_D9_NAF9, NULL);
1548 gpio_request(GPIO_FN_D10_NAF10, NULL);
1549 gpio_request(GPIO_FN_D11_NAF11, NULL);
1550 gpio_request(GPIO_FN_D12_NAF12, NULL);
1551 gpio_request(GPIO_FN_D13_NAF13, NULL);
1552 gpio_request(GPIO_FN_D14_NAF14, NULL);
1553 gpio_request(GPIO_FN_D15_NAF15, NULL);
1554 gpio_request(GPIO_FN_FCE0, NULL);
1555 gpio_request(GPIO_FN_WE0_FWE, NULL);
1556 gpio_request(GPIO_FN_FRB, NULL);
1557 gpio_request(GPIO_FN_A4_FOE, NULL);
1558 gpio_request(GPIO_FN_A5_FCDE, NULL);
1559 gpio_request(GPIO_FN_RD_FSC, NULL);
1560
1491 /* enable GPS module (GT-720F) */ 1561 /* enable GPS module (GT-720F) */
1492 gpio_request(GPIO_FN_SCIFA2_TXD1, NULL); 1562 gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
1493 gpio_request(GPIO_FN_SCIFA2_RXD1, NULL); 1563 gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
@@ -1532,6 +1602,7 @@ static void __init mackerel_init(void)
1532 sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device); 1602 sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device);
1533 sh7372_add_device_to_domain(&sh7372_a3sp, &usbhs0_device); 1603 sh7372_add_device_to_domain(&sh7372_a3sp, &usbhs0_device);
1534 sh7372_add_device_to_domain(&sh7372_a3sp, &usbhs1_device); 1604 sh7372_add_device_to_domain(&sh7372_a3sp, &usbhs1_device);
1605 sh7372_add_device_to_domain(&sh7372_a3sp, &nand_flash_device);
1535 sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device); 1606 sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device);
1536 sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device); 1607 sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device);
1537#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) 1608#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index de243e3c8392..94d1f88246d3 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -511,7 +511,7 @@ enum { MSTP001, MSTP000,
511 MSTP223, 511 MSTP223,
512 MSTP218, MSTP217, MSTP216, MSTP214, MSTP208, MSTP207, 512 MSTP218, MSTP217, MSTP216, MSTP214, MSTP208, MSTP207,
513 MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, 513 MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
514 MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312, 514 MSTP328, MSTP323, MSTP322, MSTP315, MSTP314, MSTP313, MSTP312,
515 MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP407, MSTP406, 515 MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP407, MSTP406,
516 MSTP405, MSTP404, MSTP403, MSTP400, 516 MSTP405, MSTP404, MSTP403, MSTP400,
517 MSTP_NR }; 517 MSTP_NR };
@@ -553,6 +553,7 @@ static struct clk mstp_clks[MSTP_NR] = {
553 [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSI2 */ 553 [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSI2 */
554 [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */ 554 [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
555 [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */ 555 [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
556 [MSTP315] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 15, 0), /* FLCTL*/
556 [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */ 557 [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
557 [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */ 558 [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
558 [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */ 559 [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */
@@ -653,6 +654,7 @@ static struct clk_lookup lookups[] = {
653 CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USB0 */ 654 CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USB0 */
654 CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USB0 */ 655 CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USB0 */
655 CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[MSTP322]), /* USB0 */ 656 CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[MSTP322]), /* USB0 */
657 CLKDEV_DEV_ID("sh_flctl.0", &mstp_clks[MSTP315]), /* FLCTL */
656 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */ 658 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
657 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */ 659 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
658 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */ 660 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 8b90c44d237f..1621ad07d284 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -1544,6 +1544,8 @@ static struct fsmc_nand_platform_data nand_platform_data = {
1544 .nr_partitions = ARRAY_SIZE(u300_partitions), 1544 .nr_partitions = ARRAY_SIZE(u300_partitions),
1545 .options = NAND_SKIP_BBTSCAN, 1545 .options = NAND_SKIP_BBTSCAN,
1546 .width = FSMC_NAND_BW8, 1546 .width = FSMC_NAND_BW8,
1547 .ale_off = PLAT_NAND_ALE,
1548 .cle_off = PLAT_NAND_CLE,
1547}; 1549};
1548 1550
1549static struct platform_device nand_device = { 1551static struct platform_device nand_device = {
diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h
index 7b7cba960b69..65f87c523892 100644
--- a/arch/arm/mach-u300/include/mach/u300-regs.h
+++ b/arch/arm/mach-u300/include/mach/u300-regs.h
@@ -24,6 +24,11 @@
24/* NFIF */ 24/* NFIF */
25#define U300_NAND_IF_PHYS_BASE 0x9f800000 25#define U300_NAND_IF_PHYS_BASE 0x9f800000
26 26
27/* ALE, CLE offset for FSMC NAND */
28#define PLAT_NAND_CLE (1 << 16)
29#define PLAT_NAND_ALE (1 << 17)
30
31
27/* AHB Peripherals */ 32/* AHB Peripherals */
28#define U300_AHB_PER_PHYS_BASE 0xa0000000 33#define U300_AHB_PER_PHYS_BASE 0xa0000000
29#define U300_AHB_PER_VIRT_BASE 0xff010000 34#define U300_AHB_PER_VIRT_BASE 0xff010000