OMAP3 clock: add support for 192Mhz DPLL4M2 output

In 3630, DPLL4M2 output can be 96MHz or 192MHz (for SGX to run at
192). This patch has changes to support this feature. 96MHz clock is
generated by dividing 192Mhz clock by 2 using CM_CLKSEL_CORE register.
SGX can select Core Clock, 192MHz clock or CM_96M_FCLK as it's
functional clock. In summary changes done are:
1. Added a feature called omap3_has_192mhz_clk and enabled for 3630
2. Added a new clock node called omap_192m_alwon_ck
3. Made omap_96m_alwon_fck to derive its clock from omap_192m_alwon_ck

Signed-off-by: Vishwanath BS <Vishwanath.bs@ti.com>
[paul@pwsan.com: fixed whitespace]
Signed-off-by: Paul Walmsley <paul@pwsan.com>

4 files changed, 65 insertions, 8 deletions

diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c
index 4dd5926ad980..da71ef17cb11 100644
--- a/arch/arm/mach-omap2/clock34xx_data.c
+++ b/arch/arm/mach-omap2/clock34xx_data.c
@@ -692,18 +692,24 @@ static struct clk dpll4_m2x2_ck = {
  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
  * CM_96K_(F)CLK.
  */
-static struct clk omap_96m_alwon_fck = {
-        .name           = "omap_96m_alwon_fck",
+
+/* Adding 192MHz Clock node needed by SGX */
+static struct clk omap_192m_alwon_fck = {
+        .name           = "omap_192m_alwon_fck",
         .ops            = &clkops_null,
         .parent         = &dpll4_m2x2_ck,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk cm_96m_fck = {
-        .name           = "cm_96m_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_96m_alwon_fck,
-        .recalc         = &followparent_recalc,
+static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_36XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_36XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel omap_96m_alwon_fck_clksel[] = {
+        { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
+        { .parent = NULL }
 };
 
 static const struct clksel_rate omap_96m_dpll_rates[] = {
@@ -716,6 +722,31 @@ static const struct clksel_rate omap_96m_sys_rates[] = {
         { .div = 0 }
 };
 
+static struct clk omap_96m_alwon_fck = {
+        .name           = "omap_96m_alwon_fck",
+        .ops            = &clkops_null,
+        .parent         = &dpll4_m2x2_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk omap_96m_alwon_fck_3630 = {
+        .name           = "omap_96m_alwon_fck",
+        .parent         = &omap_192m_alwon_fck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3630_CLKSEL_96M_MASK,
+        .clksel         = omap_96m_alwon_fck_clksel
+};
+
+static struct clk cm_96m_fck = {
+        .name           = "cm_96m_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_96m_alwon_fck,
+        .recalc         = &followparent_recalc,
+};
+
 static const struct clksel omap_96m_fck_clksel[] = {
         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
@@ -1304,12 +1335,24 @@ static struct clk gfx_cg2_ck = {
 /* SGX power domain - 3430ES2 only */
 
 static const struct clksel_rate sgx_core_rates[] = {
+        { .div = 2, .val = 5, .flags = RATE_IN_36XX },
         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
         { .div = 4, .val = 1, .flags = RATE_IN_343X },
         { .div = 6, .val = 2, .flags = RATE_IN_343X },
         { .div = 0 },
 };
 
+static const struct clksel_rate sgx_192m_rates[] = {
+        { .div = 1,  .val = 4, .flags = RATE_IN_36XX | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel_rate sgx_corex2_rates[] = {
+        { .div = 3, .val = 6, .flags = RATE_IN_36XX | DEFAULT_RATE },
+        { .div = 5, .val = 7, .flags = RATE_IN_36XX },
+        { .div = 0 },
+};
+
 static const struct clksel_rate sgx_96m_rates[] = {
         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
         { .div = 0 },
@@ -1318,7 +1361,9 @@ static const struct clksel_rate sgx_96m_rates[] = {
 static const struct clksel sgx_clksel[] = {
         { .parent = &core_ck,    .rates = sgx_core_rates },
         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
-        { .parent = NULL },
+        { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
+        { .parent = &corex2_fck, .rates = sgx_corex2_rates },
+        { .parent = NULL }
 };
 
 static struct clk sgx_fck = {
@@ -1332,6 +1377,8 @@ static struct clk sgx_fck = {
         .clksel         = sgx_clksel,
         .clkdm_name     = "sgx_clkdm",
         .recalc         = &omap2_clksel_recalc,
+        .set_rate       = &omap2_clksel_set_rate,
+        .round_rate     = &omap2_clksel_round_rate
 };
 
 static struct clk sgx_ick = {
@@ -3262,6 +3309,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
         CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_3XXX),
         CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_3XXX),
+        CLK(NULL,       "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
         CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
         CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_3XXX),
         CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_3XXX),
@@ -3495,6 +3543,8 @@ int __init omap3xxx_clk_init(void)
                         cpu_clkflg |= CK_3430ES2;
                 }
         }
+        if (omap3_has_192mhz_clk())
+                omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
 
         if (cpu_is_omap3630()) {
                 cpu_mask |= RATE_IN_36XX;
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index e6a724cc63f1..a3a3ca07e383 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -346,6 +346,8 @@
 #define OMAP3430_CLKSEL_L4_MASK                         (0x3 << 2)
 #define OMAP3430_CLKSEL_L3_SHIFT                        0
 #define OMAP3430_CLKSEL_L3_MASK                         (0x3 << 0)
+#define OMAP3630_CLKSEL_96M_SHIFT                       12
+#define OMAP3630_CLKSEL_96M_MASK                        (0x3 << 12)
 
 /* CM_CLKSTCTRL_CORE */
 #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT                 4
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 9e7c4aeeae02..d2897a6fe491 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -175,6 +175,8 @@ void __init omap3_check_features(void)
         OMAP3_CHECK_FEATURE(status, SGX);
         OMAP3_CHECK_FEATURE(status, NEON);
         OMAP3_CHECK_FEATURE(status, ISP);
+        if (cpu_is_omap3630())
+                omap3_features |= OMAP3_HAS_192MHZ_CLK;
 
         /*
          * TODO: Get additional info (where applicable)
@@ -359,6 +361,7 @@ void __init omap3_cpuinfo(void)
         OMAP3_SHOW_FEATURE(sgx);
         OMAP3_SHOW_FEATURE(neon);
         OMAP3_SHOW_FEATURE(isp);
+        OMAP3_SHOW_FEATURE(192mhz_clk);
 
         printk(")\n");
 }
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index b80151c1ee61..ed8786c41df2 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -439,6 +439,7 @@ extern u32 omap3_features;
 #define OMAP3_HAS_SGX                   BIT(2)
 #define OMAP3_HAS_NEON                  BIT(3)
 #define OMAP3_HAS_ISP                   BIT(4)
+#define OMAP3_HAS_192MHZ_CLK            BIT(5)
 
 #define OMAP3_HAS_FEATURE(feat,flag)                    \
 static inline unsigned int omap3_has_ ##feat(void)      \
@@ -451,5 +452,6 @@ OMAP3_HAS_FEATURE(sgx, SGX)
 OMAP3_HAS_FEATURE(iva, IVA)
 OMAP3_HAS_FEATURE(neon, NEON)
 OMAP3_HAS_FEATURE(isp, ISP)
+OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
 
 #endif