diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2009-08-17 13:16:28 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-08-17 13:16:28 -0400 |
commit | 29c08460d472e427cec5e5dcb12ec74c923f8250 (patch) | |
tree | 9d8557fe9cf123920c3ceb023274e763e5f208b0 /arch/arm | |
parent | 9b2616c2e8cc98ca98bbb40cad83a8d3d859e840 (diff) | |
parent | baa28e3530375e0bef2c53243634a1c78f5c02f3 (diff) |
Merge branch 'next-s3c' of git://aeryn.fluff.org.uk/bjdooks/linux into devel-stable
Diffstat (limited to 'arch/arm')
98 files changed, 8339 insertions, 78 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9746667c1973..5f6d977bd3df 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -122,6 +122,13 @@ config ARCH_HAS_ILOG2_U32 | |||
122 | config ARCH_HAS_ILOG2_U64 | 122 | config ARCH_HAS_ILOG2_U64 |
123 | bool | 123 | bool |
124 | 124 | ||
125 | config ARCH_HAS_CPUFREQ | ||
126 | bool | ||
127 | help | ||
128 | Internal node to signify that the ARCH has CPUFREQ support | ||
129 | and that the relevant menu configurations are displayed for | ||
130 | it. | ||
131 | |||
125 | config GENERIC_HWEIGHT | 132 | config GENERIC_HWEIGHT |
126 | bool | 133 | bool |
127 | default y | 134 | default y |
@@ -206,6 +213,7 @@ config ARCH_AAEC2000 | |||
206 | config ARCH_INTEGRATOR | 213 | config ARCH_INTEGRATOR |
207 | bool "ARM Ltd. Integrator family" | 214 | bool "ARM Ltd. Integrator family" |
208 | select ARM_AMBA | 215 | select ARM_AMBA |
216 | select ARCH_HAS_CPUFREQ | ||
209 | select HAVE_CLK | 217 | select HAVE_CLK |
210 | select COMMON_CLKDEV | 218 | select COMMON_CLKDEV |
211 | select ICST525 | 219 | select ICST525 |
@@ -512,6 +520,7 @@ config ARCH_PXA | |||
512 | bool "PXA2xx/PXA3xx-based" | 520 | bool "PXA2xx/PXA3xx-based" |
513 | depends on MMU | 521 | depends on MMU |
514 | select ARCH_MTD_XIP | 522 | select ARCH_MTD_XIP |
523 | select ARCH_HAS_CPUFREQ | ||
515 | select GENERIC_GPIO | 524 | select GENERIC_GPIO |
516 | select HAVE_CLK | 525 | select HAVE_CLK |
517 | select COMMON_CLKDEV | 526 | select COMMON_CLKDEV |
@@ -554,6 +563,7 @@ config ARCH_SA1100 | |||
554 | select ISA | 563 | select ISA |
555 | select ARCH_SPARSEMEM_ENABLE | 564 | select ARCH_SPARSEMEM_ENABLE |
556 | select ARCH_MTD_XIP | 565 | select ARCH_MTD_XIP |
566 | select ARCH_HAS_CPUFREQ | ||
557 | select GENERIC_GPIO | 567 | select GENERIC_GPIO |
558 | select GENERIC_TIME | 568 | select GENERIC_TIME |
559 | select GENERIC_CLOCKEVENTS | 569 | select GENERIC_CLOCKEVENTS |
@@ -566,6 +576,7 @@ config ARCH_SA1100 | |||
566 | config ARCH_S3C2410 | 576 | config ARCH_S3C2410 |
567 | bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442, S3C2443" | 577 | bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442, S3C2443" |
568 | select GENERIC_GPIO | 578 | select GENERIC_GPIO |
579 | select ARCH_HAS_CPUFREQ | ||
569 | select HAVE_CLK | 580 | select HAVE_CLK |
570 | help | 581 | help |
571 | Samsung S3C2410X CPU based systems, such as the Simtec Electronics | 582 | Samsung S3C2410X CPU based systems, such as the Simtec Electronics |
@@ -576,9 +587,18 @@ config ARCH_S3C64XX | |||
576 | bool "Samsung S3C64XX" | 587 | bool "Samsung S3C64XX" |
577 | select GENERIC_GPIO | 588 | select GENERIC_GPIO |
578 | select HAVE_CLK | 589 | select HAVE_CLK |
590 | select ARCH_HAS_CPUFREQ | ||
579 | help | 591 | help |
580 | Samsung S3C64XX series based systems | 592 | Samsung S3C64XX series based systems |
581 | 593 | ||
594 | config ARCH_S5PC1XX | ||
595 | bool "Samsung S5PC1XX" | ||
596 | select GENERIC_GPIO | ||
597 | select HAVE_CLK | ||
598 | select CPU_V7 | ||
599 | help | ||
600 | Samsung S5PC1XX series based systems | ||
601 | |||
582 | config ARCH_SHARK | 602 | config ARCH_SHARK |
583 | bool "Shark" | 603 | bool "Shark" |
584 | select CPU_SA110 | 604 | select CPU_SA110 |
@@ -635,6 +655,7 @@ config ARCH_OMAP | |||
635 | select GENERIC_GPIO | 655 | select GENERIC_GPIO |
636 | select HAVE_CLK | 656 | select HAVE_CLK |
637 | select ARCH_REQUIRE_GPIOLIB | 657 | select ARCH_REQUIRE_GPIOLIB |
658 | select ARCH_HAS_CPUFREQ | ||
638 | select GENERIC_TIME | 659 | select GENERIC_TIME |
639 | select GENERIC_CLOCKEVENTS | 660 | select GENERIC_CLOCKEVENTS |
640 | help | 661 | help |
@@ -688,6 +709,7 @@ source "arch/arm/mach-kirkwood/Kconfig" | |||
688 | source "arch/arm/plat-s3c24xx/Kconfig" | 709 | source "arch/arm/plat-s3c24xx/Kconfig" |
689 | source "arch/arm/plat-s3c64xx/Kconfig" | 710 | source "arch/arm/plat-s3c64xx/Kconfig" |
690 | source "arch/arm/plat-s3c/Kconfig" | 711 | source "arch/arm/plat-s3c/Kconfig" |
712 | source "arch/arm/plat-s5pc1xx/Kconfig" | ||
691 | 713 | ||
692 | if ARCH_S3C2410 | 714 | if ARCH_S3C2410 |
693 | source "arch/arm/mach-s3c2400/Kconfig" | 715 | source "arch/arm/mach-s3c2400/Kconfig" |
@@ -705,6 +727,10 @@ endif | |||
705 | 727 | ||
706 | source "arch/arm/plat-stmp3xxx/Kconfig" | 728 | source "arch/arm/plat-stmp3xxx/Kconfig" |
707 | 729 | ||
730 | if ARCH_S5PC1XX | ||
731 | source "arch/arm/mach-s5pc100/Kconfig" | ||
732 | endif | ||
733 | |||
708 | source "arch/arm/mach-lh7a40x/Kconfig" | 734 | source "arch/arm/mach-lh7a40x/Kconfig" |
709 | 735 | ||
710 | source "arch/arm/mach-h720x/Kconfig" | 736 | source "arch/arm/mach-h720x/Kconfig" |
@@ -1248,7 +1274,7 @@ endmenu | |||
1248 | 1274 | ||
1249 | menu "CPU Power Management" | 1275 | menu "CPU Power Management" |
1250 | 1276 | ||
1251 | if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_PXA || ARCH_S3C64XX) | 1277 | if ARCH_HAS_CPUFREQ |
1252 | 1278 | ||
1253 | source "drivers/cpufreq/Kconfig" | 1279 | source "drivers/cpufreq/Kconfig" |
1254 | 1280 | ||
@@ -1283,6 +1309,52 @@ config CPU_FREQ_S3C64XX | |||
1283 | bool "CPUfreq support for Samsung S3C64XX CPUs" | 1309 | bool "CPUfreq support for Samsung S3C64XX CPUs" |
1284 | depends on CPU_FREQ && CPU_S3C6410 | 1310 | depends on CPU_FREQ && CPU_S3C6410 |
1285 | 1311 | ||
1312 | config CPU_FREQ_S3C | ||
1313 | bool | ||
1314 | help | ||
1315 | Internal configuration node for common cpufreq on Samsung SoC | ||
1316 | |||
1317 | config CPU_FREQ_S3C24XX | ||
1318 | bool "CPUfreq driver for Samsung S3C24XX series CPUs" | ||
1319 | depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL | ||
1320 | select CPU_FREQ_S3C | ||
1321 | help | ||
1322 | This enables the CPUfreq driver for the Samsung S3C24XX family | ||
1323 | of CPUs. | ||
1324 | |||
1325 | For details, take a look at <file:Documentation/cpu-freq>. | ||
1326 | |||
1327 | If in doubt, say N. | ||
1328 | |||
1329 | config CPU_FREQ_S3C24XX_PLL | ||
1330 | bool "Support CPUfreq changing of PLL frequency" | ||
1331 | depends on CPU_FREQ_S3C24XX && EXPERIMENTAL | ||
1332 | help | ||
1333 | Compile in support for changing the PLL frequency from the | ||
1334 | S3C24XX series CPUfreq driver. The PLL takes time to settle | ||
1335 | after a frequency change, so by default it is not enabled. | ||
1336 | |||
1337 | This also means that the PLL tables for the selected CPU(s) will | ||
1338 | be built which may increase the size of the kernel image. | ||
1339 | |||
1340 | config CPU_FREQ_S3C24XX_DEBUG | ||
1341 | bool "Debug CPUfreq Samsung driver core" | ||
1342 | depends on CPU_FREQ_S3C24XX | ||
1343 | help | ||
1344 | Enable s3c_freq_dbg for the Samsung S3C CPUfreq core | ||
1345 | |||
1346 | config CPU_FREQ_S3C24XX_IODEBUG | ||
1347 | bool "Debug CPUfreq Samsung driver IO timing" | ||
1348 | depends on CPU_FREQ_S3C24XX | ||
1349 | help | ||
1350 | Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core | ||
1351 | |||
1352 | config CPU_FREQ_S3C24XX_DEBUGFS | ||
1353 | bool "Export debugfs for CPUFreq" | ||
1354 | depends on CPU_FREQ_S3C24XX && DEBUG_FS | ||
1355 | help | ||
1356 | Export status information via debugfs. | ||
1357 | |||
1286 | endif | 1358 | endif |
1287 | 1359 | ||
1288 | source "drivers/cpuidle/Kconfig" | 1360 | source "drivers/cpuidle/Kconfig" |
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 8f117acd98e9..3de196e2a7a7 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
@@ -158,6 +158,7 @@ machine-$(CONFIG_ARCH_RPC) := rpc | |||
158 | machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443 | 158 | machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443 |
159 | machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 | 159 | machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 |
160 | machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410 | 160 | machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410 |
161 | machine-$(CONFIG_ARCH_S5PC1XX) := s5pc100 | ||
161 | machine-$(CONFIG_ARCH_SA1100) := sa1100 | 162 | machine-$(CONFIG_ARCH_SA1100) := sa1100 |
162 | machine-$(CONFIG_ARCH_SHARK) := shark | 163 | machine-$(CONFIG_ARCH_SHARK) := shark |
163 | machine-$(CONFIG_ARCH_STMP378X) := stmp378x | 164 | machine-$(CONFIG_ARCH_STMP378X) := stmp378x |
@@ -177,6 +178,7 @@ plat-$(CONFIG_PLAT_ORION) := orion | |||
177 | plat-$(CONFIG_PLAT_PXA) := pxa | 178 | plat-$(CONFIG_PLAT_PXA) := pxa |
178 | plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c | 179 | plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c |
179 | plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c | 180 | plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c |
181 | plat-$(CONFIG_PLAT_S5PC1XX) := s5pc1xx s3c | ||
180 | plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx | 182 | plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx |
181 | 183 | ||
182 | ifeq ($(CONFIG_ARCH_EBSA110),y) | 184 | ifeq ($(CONFIG_ARCH_EBSA110),y) |
diff --git a/arch/arm/configs/s5pc100_defconfig b/arch/arm/configs/s5pc100_defconfig new file mode 100644 index 000000000000..b0d7d3d3a5e3 --- /dev/null +++ b/arch/arm/configs/s5pc100_defconfig | |||
@@ -0,0 +1,892 @@ | |||
1 | # | ||
2 | # Automatically generated make config: don't edit | ||
3 | # Linux kernel version: 2.6.30 | ||
4 | # Wed Jul 1 15:53:07 2009 | ||
5 | # | ||
6 | CONFIG_ARM=y | ||
7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
8 | CONFIG_GENERIC_GPIO=y | ||
9 | CONFIG_MMU=y | ||
10 | CONFIG_NO_IOPORT=y | ||
11 | CONFIG_GENERIC_HARDIRQS=y | ||
12 | CONFIG_STACKTRACE_SUPPORT=y | ||
13 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
14 | CONFIG_LOCKDEP_SUPPORT=y | ||
15 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
16 | CONFIG_HARDIRQS_SW_RESEND=y | ||
17 | CONFIG_GENERIC_IRQ_PROBE=y | ||
18 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
19 | CONFIG_GENERIC_HWEIGHT=y | ||
20 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
21 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
22 | CONFIG_VECTORS_BASE=0xffff0000 | ||
23 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
24 | CONFIG_CONSTRUCTORS=y | ||
25 | |||
26 | # | ||
27 | # General setup | ||
28 | # | ||
29 | CONFIG_EXPERIMENTAL=y | ||
30 | CONFIG_BROKEN_ON_SMP=y | ||
31 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
32 | CONFIG_LOCALVERSION="" | ||
33 | CONFIG_LOCALVERSION_AUTO=y | ||
34 | CONFIG_SWAP=y | ||
35 | # CONFIG_SYSVIPC is not set | ||
36 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
37 | |||
38 | # | ||
39 | # RCU Subsystem | ||
40 | # | ||
41 | CONFIG_CLASSIC_RCU=y | ||
42 | # CONFIG_TREE_RCU is not set | ||
43 | # CONFIG_PREEMPT_RCU is not set | ||
44 | # CONFIG_TREE_RCU_TRACE is not set | ||
45 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
46 | # CONFIG_IKCONFIG is not set | ||
47 | CONFIG_LOG_BUF_SHIFT=17 | ||
48 | # CONFIG_GROUP_SCHED is not set | ||
49 | # CONFIG_CGROUPS is not set | ||
50 | CONFIG_SYSFS_DEPRECATED=y | ||
51 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
52 | # CONFIG_RELAY is not set | ||
53 | CONFIG_NAMESPACES=y | ||
54 | # CONFIG_UTS_NS is not set | ||
55 | # CONFIG_USER_NS is not set | ||
56 | # CONFIG_PID_NS is not set | ||
57 | CONFIG_BLK_DEV_INITRD=y | ||
58 | CONFIG_INITRAMFS_SOURCE="" | ||
59 | CONFIG_RD_GZIP=y | ||
60 | CONFIG_RD_BZIP2=y | ||
61 | CONFIG_RD_LZMA=y | ||
62 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
63 | CONFIG_SYSCTL=y | ||
64 | CONFIG_ANON_INODES=y | ||
65 | # CONFIG_EMBEDDED is not set | ||
66 | CONFIG_UID16=y | ||
67 | CONFIG_SYSCTL_SYSCALL=y | ||
68 | CONFIG_KALLSYMS=y | ||
69 | CONFIG_KALLSYMS_ALL=y | ||
70 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
71 | CONFIG_HOTPLUG=y | ||
72 | CONFIG_PRINTK=y | ||
73 | CONFIG_BUG=y | ||
74 | CONFIG_ELF_CORE=y | ||
75 | CONFIG_BASE_FULL=y | ||
76 | CONFIG_FUTEX=y | ||
77 | CONFIG_EPOLL=y | ||
78 | CONFIG_SIGNALFD=y | ||
79 | CONFIG_TIMERFD=y | ||
80 | CONFIG_EVENTFD=y | ||
81 | CONFIG_SHMEM=y | ||
82 | CONFIG_AIO=y | ||
83 | |||
84 | # | ||
85 | # Performance Counters | ||
86 | # | ||
87 | CONFIG_VM_EVENT_COUNTERS=y | ||
88 | CONFIG_SLUB_DEBUG=y | ||
89 | # CONFIG_STRIP_ASM_SYMS is not set | ||
90 | CONFIG_COMPAT_BRK=y | ||
91 | # CONFIG_SLAB is not set | ||
92 | CONFIG_SLUB=y | ||
93 | # CONFIG_SLOB is not set | ||
94 | # CONFIG_PROFILING is not set | ||
95 | # CONFIG_MARKERS is not set | ||
96 | CONFIG_HAVE_OPROFILE=y | ||
97 | # CONFIG_KPROBES is not set | ||
98 | CONFIG_HAVE_KPROBES=y | ||
99 | CONFIG_HAVE_KRETPROBES=y | ||
100 | CONFIG_HAVE_CLK=y | ||
101 | |||
102 | # | ||
103 | # GCOV-based kernel profiling | ||
104 | # | ||
105 | # CONFIG_SLOW_WORK is not set | ||
106 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
107 | CONFIG_SLABINFO=y | ||
108 | CONFIG_RT_MUTEXES=y | ||
109 | CONFIG_BASE_SMALL=0 | ||
110 | CONFIG_MODULES=y | ||
111 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
112 | CONFIG_MODULE_UNLOAD=y | ||
113 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
114 | # CONFIG_MODVERSIONS is not set | ||
115 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
116 | CONFIG_BLOCK=y | ||
117 | CONFIG_LBDAF=y | ||
118 | # CONFIG_BLK_DEV_BSG is not set | ||
119 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
120 | |||
121 | # | ||
122 | # IO Schedulers | ||
123 | # | ||
124 | CONFIG_IOSCHED_NOOP=y | ||
125 | CONFIG_IOSCHED_AS=y | ||
126 | CONFIG_IOSCHED_DEADLINE=y | ||
127 | CONFIG_IOSCHED_CFQ=y | ||
128 | # CONFIG_DEFAULT_AS is not set | ||
129 | # CONFIG_DEFAULT_DEADLINE is not set | ||
130 | CONFIG_DEFAULT_CFQ=y | ||
131 | # CONFIG_DEFAULT_NOOP is not set | ||
132 | CONFIG_DEFAULT_IOSCHED="cfq" | ||
133 | # CONFIG_FREEZER is not set | ||
134 | |||
135 | # | ||
136 | # System Type | ||
137 | # | ||
138 | # CONFIG_ARCH_AAEC2000 is not set | ||
139 | # CONFIG_ARCH_INTEGRATOR is not set | ||
140 | # CONFIG_ARCH_REALVIEW is not set | ||
141 | # CONFIG_ARCH_VERSATILE is not set | ||
142 | # CONFIG_ARCH_AT91 is not set | ||
143 | # CONFIG_ARCH_CLPS711X is not set | ||
144 | # CONFIG_ARCH_GEMINI is not set | ||
145 | # CONFIG_ARCH_EBSA110 is not set | ||
146 | # CONFIG_ARCH_EP93XX is not set | ||
147 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
148 | # CONFIG_ARCH_MXC is not set | ||
149 | # CONFIG_ARCH_STMP3XXX is not set | ||
150 | # CONFIG_ARCH_NETX is not set | ||
151 | # CONFIG_ARCH_H720X is not set | ||
152 | # CONFIG_ARCH_IOP13XX is not set | ||
153 | # CONFIG_ARCH_IOP32X is not set | ||
154 | # CONFIG_ARCH_IOP33X is not set | ||
155 | # CONFIG_ARCH_IXP23XX is not set | ||
156 | # CONFIG_ARCH_IXP2000 is not set | ||
157 | # CONFIG_ARCH_IXP4XX is not set | ||
158 | # CONFIG_ARCH_L7200 is not set | ||
159 | # CONFIG_ARCH_KIRKWOOD is not set | ||
160 | # CONFIG_ARCH_LOKI is not set | ||
161 | # CONFIG_ARCH_MV78XX0 is not set | ||
162 | # CONFIG_ARCH_ORION5X is not set | ||
163 | # CONFIG_ARCH_MMP is not set | ||
164 | # CONFIG_ARCH_KS8695 is not set | ||
165 | # CONFIG_ARCH_NS9XXX is not set | ||
166 | # CONFIG_ARCH_W90X900 is not set | ||
167 | # CONFIG_ARCH_PNX4008 is not set | ||
168 | # CONFIG_ARCH_PXA is not set | ||
169 | # CONFIG_ARCH_MSM is not set | ||
170 | # CONFIG_ARCH_RPC is not set | ||
171 | # CONFIG_ARCH_SA1100 is not set | ||
172 | # CONFIG_ARCH_S3C2410 is not set | ||
173 | # CONFIG_ARCH_S3C64XX is not set | ||
174 | CONFIG_ARCH_S5PC1XX=y | ||
175 | # CONFIG_ARCH_SHARK is not set | ||
176 | # CONFIG_ARCH_LH7A40X is not set | ||
177 | # CONFIG_ARCH_U300 is not set | ||
178 | # CONFIG_ARCH_DAVINCI is not set | ||
179 | # CONFIG_ARCH_OMAP is not set | ||
180 | CONFIG_PLAT_S3C=y | ||
181 | |||
182 | # | ||
183 | # Boot options | ||
184 | # | ||
185 | # CONFIG_S3C_BOOT_ERROR_RESET is not set | ||
186 | CONFIG_S3C_BOOT_UART_FORCE_FIFO=y | ||
187 | |||
188 | # | ||
189 | # Power management | ||
190 | # | ||
191 | CONFIG_S3C_LOWLEVEL_UART_PORT=0 | ||
192 | CONFIG_S3C_GPIO_SPACE=0 | ||
193 | CONFIG_S3C_GPIO_TRACK=y | ||
194 | CONFIG_S3C_GPIO_PULL_UPDOWN=y | ||
195 | CONFIG_PLAT_S5PC1XX=y | ||
196 | CONFIG_CPU_S5PC100_INIT=y | ||
197 | CONFIG_CPU_S5PC100_CLOCK=y | ||
198 | CONFIG_S5PC100_SETUP_I2C0=y | ||
199 | CONFIG_CPU_S5PC100=y | ||
200 | CONFIG_MACH_SMDKC100=y | ||
201 | |||
202 | # | ||
203 | # Processor Type | ||
204 | # | ||
205 | CONFIG_CPU_32=y | ||
206 | CONFIG_CPU_32v6K=y | ||
207 | CONFIG_CPU_V7=y | ||
208 | CONFIG_CPU_32v7=y | ||
209 | CONFIG_CPU_ABRT_EV7=y | ||
210 | CONFIG_CPU_PABRT_IFAR=y | ||
211 | CONFIG_CPU_CACHE_V7=y | ||
212 | CONFIG_CPU_CACHE_VIPT=y | ||
213 | CONFIG_CPU_COPY_V6=y | ||
214 | CONFIG_CPU_TLB_V7=y | ||
215 | CONFIG_CPU_HAS_ASID=y | ||
216 | CONFIG_CPU_CP15=y | ||
217 | CONFIG_CPU_CP15_MMU=y | ||
218 | |||
219 | # | ||
220 | # Processor Features | ||
221 | # | ||
222 | CONFIG_ARM_THUMB=y | ||
223 | # CONFIG_ARM_THUMBEE is not set | ||
224 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
225 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
226 | # CONFIG_CPU_BPREDICT_DISABLE is not set | ||
227 | CONFIG_HAS_TLS_REG=y | ||
228 | # CONFIG_ARM_ERRATA_430973 is not set | ||
229 | # CONFIG_ARM_ERRATA_458693 is not set | ||
230 | # CONFIG_ARM_ERRATA_460075 is not set | ||
231 | CONFIG_ARM_VIC=y | ||
232 | CONFIG_ARM_VIC_NR=2 | ||
233 | |||
234 | # | ||
235 | # Bus support | ||
236 | # | ||
237 | # CONFIG_PCI_SYSCALL is not set | ||
238 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
239 | # CONFIG_PCCARD is not set | ||
240 | |||
241 | # | ||
242 | # Kernel Features | ||
243 | # | ||
244 | CONFIG_VMSPLIT_3G=y | ||
245 | # CONFIG_VMSPLIT_2G is not set | ||
246 | # CONFIG_VMSPLIT_1G is not set | ||
247 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
248 | # CONFIG_PREEMPT is not set | ||
249 | CONFIG_HZ=100 | ||
250 | CONFIG_AEABI=y | ||
251 | CONFIG_OABI_COMPAT=y | ||
252 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
253 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
254 | # CONFIG_HIGHMEM is not set | ||
255 | CONFIG_SELECT_MEMORY_MODEL=y | ||
256 | CONFIG_FLATMEM_MANUAL=y | ||
257 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
258 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
259 | CONFIG_FLATMEM=y | ||
260 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
261 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
262 | CONFIG_SPLIT_PTLOCK_CPUS=4 | ||
263 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
264 | CONFIG_ZONE_DMA_FLAG=0 | ||
265 | CONFIG_VIRT_TO_BUS=y | ||
266 | CONFIG_HAVE_MLOCK=y | ||
267 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y | ||
268 | CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 | ||
269 | CONFIG_ALIGNMENT_TRAP=y | ||
270 | # CONFIG_UACCESS_WITH_MEMCPY is not set | ||
271 | |||
272 | # | ||
273 | # Boot options | ||
274 | # | ||
275 | CONFIG_ZBOOT_ROM_TEXT=0 | ||
276 | CONFIG_ZBOOT_ROM_BSS=0 | ||
277 | CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=cramfs init=/linuxrc console=ttySAC2,115200 mem=128M" | ||
278 | # CONFIG_XIP_KERNEL is not set | ||
279 | # CONFIG_KEXEC is not set | ||
280 | |||
281 | # | ||
282 | # CPU Power Management | ||
283 | # | ||
284 | # CONFIG_CPU_IDLE is not set | ||
285 | |||
286 | # | ||
287 | # Floating point emulation | ||
288 | # | ||
289 | |||
290 | # | ||
291 | # At least one emulation must be selected | ||
292 | # | ||
293 | # CONFIG_FPE_NWFPE is not set | ||
294 | # CONFIG_FPE_FASTFPE is not set | ||
295 | # CONFIG_VFP is not set | ||
296 | |||
297 | # | ||
298 | # Userspace binary formats | ||
299 | # | ||
300 | CONFIG_BINFMT_ELF=y | ||
301 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
302 | CONFIG_HAVE_AOUT=y | ||
303 | # CONFIG_BINFMT_AOUT is not set | ||
304 | # CONFIG_BINFMT_MISC is not set | ||
305 | |||
306 | # | ||
307 | # Power management options | ||
308 | # | ||
309 | # CONFIG_PM is not set | ||
310 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
311 | # CONFIG_NET is not set | ||
312 | |||
313 | # | ||
314 | # Device Drivers | ||
315 | # | ||
316 | |||
317 | # | ||
318 | # Generic Driver Options | ||
319 | # | ||
320 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
321 | CONFIG_STANDALONE=y | ||
322 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
323 | CONFIG_FW_LOADER=y | ||
324 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
325 | CONFIG_EXTRA_FIRMWARE="" | ||
326 | # CONFIG_DEBUG_DRIVER is not set | ||
327 | # CONFIG_DEBUG_DEVRES is not set | ||
328 | # CONFIG_SYS_HYPERVISOR is not set | ||
329 | # CONFIG_MTD is not set | ||
330 | # CONFIG_PARPORT is not set | ||
331 | CONFIG_BLK_DEV=y | ||
332 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
333 | CONFIG_BLK_DEV_LOOP=y | ||
334 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | ||
335 | CONFIG_BLK_DEV_RAM=y | ||
336 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
337 | CONFIG_BLK_DEV_RAM_SIZE=8192 | ||
338 | # CONFIG_BLK_DEV_XIP is not set | ||
339 | # CONFIG_CDROM_PKTCDVD is not set | ||
340 | # CONFIG_MG_DISK is not set | ||
341 | CONFIG_MISC_DEVICES=y | ||
342 | # CONFIG_ICS932S401 is not set | ||
343 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
344 | # CONFIG_ISL29003 is not set | ||
345 | # CONFIG_C2PORT is not set | ||
346 | |||
347 | # | ||
348 | # EEPROM support | ||
349 | # | ||
350 | CONFIG_EEPROM_AT24=y | ||
351 | # CONFIG_EEPROM_LEGACY is not set | ||
352 | # CONFIG_EEPROM_MAX6875 is not set | ||
353 | # CONFIG_EEPROM_93CX6 is not set | ||
354 | CONFIG_HAVE_IDE=y | ||
355 | # CONFIG_IDE is not set | ||
356 | |||
357 | # | ||
358 | # SCSI device support | ||
359 | # | ||
360 | # CONFIG_RAID_ATTRS is not set | ||
361 | # CONFIG_SCSI is not set | ||
362 | # CONFIG_SCSI_DMA is not set | ||
363 | # CONFIG_SCSI_NETLINK is not set | ||
364 | # CONFIG_ATA is not set | ||
365 | # CONFIG_MD is not set | ||
366 | |||
367 | # | ||
368 | # Input device support | ||
369 | # | ||
370 | CONFIG_INPUT=y | ||
371 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
372 | # CONFIG_INPUT_POLLDEV is not set | ||
373 | |||
374 | # | ||
375 | # Userland interfaces | ||
376 | # | ||
377 | CONFIG_INPUT_MOUSEDEV=y | ||
378 | CONFIG_INPUT_MOUSEDEV_PSAUX=y | ||
379 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
380 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
381 | # CONFIG_INPUT_JOYDEV is not set | ||
382 | # CONFIG_INPUT_EVDEV is not set | ||
383 | # CONFIG_INPUT_EVBUG is not set | ||
384 | |||
385 | # | ||
386 | # Input Device Drivers | ||
387 | # | ||
388 | CONFIG_INPUT_KEYBOARD=y | ||
389 | CONFIG_KEYBOARD_ATKBD=y | ||
390 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
391 | # CONFIG_KEYBOARD_LKKBD is not set | ||
392 | # CONFIG_KEYBOARD_XTKBD is not set | ||
393 | # CONFIG_KEYBOARD_NEWTON is not set | ||
394 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
395 | # CONFIG_KEYBOARD_GPIO is not set | ||
396 | CONFIG_INPUT_MOUSE=y | ||
397 | CONFIG_MOUSE_PS2=y | ||
398 | CONFIG_MOUSE_PS2_ALPS=y | ||
399 | CONFIG_MOUSE_PS2_LOGIPS2PP=y | ||
400 | CONFIG_MOUSE_PS2_SYNAPTICS=y | ||
401 | CONFIG_MOUSE_PS2_TRACKPOINT=y | ||
402 | # CONFIG_MOUSE_PS2_ELANTECH is not set | ||
403 | # CONFIG_MOUSE_PS2_TOUCHKIT is not set | ||
404 | # CONFIG_MOUSE_SERIAL is not set | ||
405 | # CONFIG_MOUSE_APPLETOUCH is not set | ||
406 | # CONFIG_MOUSE_BCM5974 is not set | ||
407 | # CONFIG_MOUSE_VSXXXAA is not set | ||
408 | # CONFIG_MOUSE_GPIO is not set | ||
409 | # CONFIG_MOUSE_SYNAPTICS_I2C is not set | ||
410 | # CONFIG_INPUT_JOYSTICK is not set | ||
411 | # CONFIG_INPUT_TABLET is not set | ||
412 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
413 | # CONFIG_INPUT_MISC is not set | ||
414 | |||
415 | # | ||
416 | # Hardware I/O ports | ||
417 | # | ||
418 | CONFIG_SERIO=y | ||
419 | CONFIG_SERIO_SERPORT=y | ||
420 | CONFIG_SERIO_LIBPS2=y | ||
421 | # CONFIG_SERIO_RAW is not set | ||
422 | # CONFIG_GAMEPORT is not set | ||
423 | |||
424 | # | ||
425 | # Character devices | ||
426 | # | ||
427 | CONFIG_VT=y | ||
428 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
429 | CONFIG_VT_CONSOLE=y | ||
430 | CONFIG_HW_CONSOLE=y | ||
431 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
432 | CONFIG_DEVKMEM=y | ||
433 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
434 | |||
435 | # | ||
436 | # Serial drivers | ||
437 | # | ||
438 | CONFIG_SERIAL_8250=y | ||
439 | # CONFIG_SERIAL_8250_CONSOLE is not set | ||
440 | CONFIG_SERIAL_8250_NR_UARTS=4 | ||
441 | CONFIG_SERIAL_8250_RUNTIME_UARTS=4 | ||
442 | # CONFIG_SERIAL_8250_EXTENDED is not set | ||
443 | |||
444 | # | ||
445 | # Non-8250 serial port support | ||
446 | # | ||
447 | CONFIG_SERIAL_SAMSUNG=y | ||
448 | CONFIG_SERIAL_SAMSUNG_UARTS=3 | ||
449 | # CONFIG_SERIAL_SAMSUNG_DEBUG is not set | ||
450 | CONFIG_SERIAL_SAMSUNG_CONSOLE=y | ||
451 | CONFIG_SERIAL_CORE=y | ||
452 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
453 | CONFIG_UNIX98_PTYS=y | ||
454 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
455 | CONFIG_LEGACY_PTYS=y | ||
456 | CONFIG_LEGACY_PTY_COUNT=256 | ||
457 | # CONFIG_IPMI_HANDLER is not set | ||
458 | CONFIG_HW_RANDOM=y | ||
459 | # CONFIG_HW_RANDOM_TIMERIOMEM is not set | ||
460 | # CONFIG_R3964 is not set | ||
461 | # CONFIG_RAW_DRIVER is not set | ||
462 | # CONFIG_TCG_TPM is not set | ||
463 | CONFIG_I2C=y | ||
464 | CONFIG_I2C_BOARDINFO=y | ||
465 | CONFIG_I2C_CHARDEV=y | ||
466 | CONFIG_I2C_HELPER_AUTO=y | ||
467 | |||
468 | # | ||
469 | # I2C Hardware Bus support | ||
470 | # | ||
471 | |||
472 | # | ||
473 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
474 | # | ||
475 | # CONFIG_I2C_GPIO is not set | ||
476 | # CONFIG_I2C_OCORES is not set | ||
477 | # CONFIG_I2C_SIMTEC is not set | ||
478 | |||
479 | # | ||
480 | # External I2C/SMBus adapter drivers | ||
481 | # | ||
482 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
483 | # CONFIG_I2C_TAOS_EVM is not set | ||
484 | |||
485 | # | ||
486 | # Other I2C/SMBus bus drivers | ||
487 | # | ||
488 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
489 | # CONFIG_I2C_STUB is not set | ||
490 | |||
491 | # | ||
492 | # Miscellaneous I2C Chip support | ||
493 | # | ||
494 | # CONFIG_DS1682 is not set | ||
495 | # CONFIG_SENSORS_PCF8574 is not set | ||
496 | # CONFIG_PCF8575 is not set | ||
497 | # CONFIG_SENSORS_PCA9539 is not set | ||
498 | # CONFIG_SENSORS_TSL2550 is not set | ||
499 | # CONFIG_I2C_DEBUG_CORE is not set | ||
500 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
501 | # CONFIG_I2C_DEBUG_BUS is not set | ||
502 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
503 | # CONFIG_SPI is not set | ||
504 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
505 | CONFIG_GPIOLIB=y | ||
506 | # CONFIG_DEBUG_GPIO is not set | ||
507 | # CONFIG_GPIO_SYSFS is not set | ||
508 | |||
509 | # | ||
510 | # Memory mapped GPIO expanders: | ||
511 | # | ||
512 | |||
513 | # | ||
514 | # I2C GPIO expanders: | ||
515 | # | ||
516 | # CONFIG_GPIO_MAX732X is not set | ||
517 | # CONFIG_GPIO_PCA953X is not set | ||
518 | # CONFIG_GPIO_PCF857X is not set | ||
519 | |||
520 | # | ||
521 | # PCI GPIO expanders: | ||
522 | # | ||
523 | |||
524 | # | ||
525 | # SPI GPIO expanders: | ||
526 | # | ||
527 | # CONFIG_W1 is not set | ||
528 | # CONFIG_POWER_SUPPLY is not set | ||
529 | CONFIG_HWMON=y | ||
530 | # CONFIG_HWMON_VID is not set | ||
531 | # CONFIG_SENSORS_AD7414 is not set | ||
532 | # CONFIG_SENSORS_AD7418 is not set | ||
533 | # CONFIG_SENSORS_ADM1021 is not set | ||
534 | # CONFIG_SENSORS_ADM1025 is not set | ||
535 | # CONFIG_SENSORS_ADM1026 is not set | ||
536 | # CONFIG_SENSORS_ADM1029 is not set | ||
537 | # CONFIG_SENSORS_ADM1031 is not set | ||
538 | # CONFIG_SENSORS_ADM9240 is not set | ||
539 | # CONFIG_SENSORS_ADT7462 is not set | ||
540 | # CONFIG_SENSORS_ADT7470 is not set | ||
541 | # CONFIG_SENSORS_ADT7473 is not set | ||
542 | # CONFIG_SENSORS_ADT7475 is not set | ||
543 | # CONFIG_SENSORS_ATXP1 is not set | ||
544 | # CONFIG_SENSORS_DS1621 is not set | ||
545 | # CONFIG_SENSORS_F71805F is not set | ||
546 | # CONFIG_SENSORS_F71882FG is not set | ||
547 | # CONFIG_SENSORS_F75375S is not set | ||
548 | # CONFIG_SENSORS_G760A is not set | ||
549 | # CONFIG_SENSORS_GL518SM is not set | ||
550 | # CONFIG_SENSORS_GL520SM is not set | ||
551 | # CONFIG_SENSORS_IT87 is not set | ||
552 | # CONFIG_SENSORS_LM63 is not set | ||
553 | # CONFIG_SENSORS_LM75 is not set | ||
554 | # CONFIG_SENSORS_LM77 is not set | ||
555 | # CONFIG_SENSORS_LM78 is not set | ||
556 | # CONFIG_SENSORS_LM80 is not set | ||
557 | # CONFIG_SENSORS_LM83 is not set | ||
558 | # CONFIG_SENSORS_LM85 is not set | ||
559 | # CONFIG_SENSORS_LM87 is not set | ||
560 | # CONFIG_SENSORS_LM90 is not set | ||
561 | # CONFIG_SENSORS_LM92 is not set | ||
562 | # CONFIG_SENSORS_LM93 is not set | ||
563 | # CONFIG_SENSORS_LTC4215 is not set | ||
564 | # CONFIG_SENSORS_LTC4245 is not set | ||
565 | # CONFIG_SENSORS_LM95241 is not set | ||
566 | # CONFIG_SENSORS_MAX1619 is not set | ||
567 | # CONFIG_SENSORS_MAX6650 is not set | ||
568 | # CONFIG_SENSORS_PC87360 is not set | ||
569 | # CONFIG_SENSORS_PC87427 is not set | ||
570 | # CONFIG_SENSORS_PCF8591 is not set | ||
571 | # CONFIG_SENSORS_SHT15 is not set | ||
572 | # CONFIG_SENSORS_DME1737 is not set | ||
573 | # CONFIG_SENSORS_SMSC47M1 is not set | ||
574 | # CONFIG_SENSORS_SMSC47M192 is not set | ||
575 | # CONFIG_SENSORS_SMSC47B397 is not set | ||
576 | # CONFIG_SENSORS_ADS7828 is not set | ||
577 | # CONFIG_SENSORS_THMC50 is not set | ||
578 | # CONFIG_SENSORS_TMP401 is not set | ||
579 | # CONFIG_SENSORS_VT1211 is not set | ||
580 | # CONFIG_SENSORS_W83781D is not set | ||
581 | # CONFIG_SENSORS_W83791D is not set | ||
582 | # CONFIG_SENSORS_W83792D is not set | ||
583 | # CONFIG_SENSORS_W83793 is not set | ||
584 | # CONFIG_SENSORS_W83L785TS is not set | ||
585 | # CONFIG_SENSORS_W83L786NG is not set | ||
586 | # CONFIG_SENSORS_W83627HF is not set | ||
587 | # CONFIG_SENSORS_W83627EHF is not set | ||
588 | # CONFIG_HWMON_DEBUG_CHIP is not set | ||
589 | # CONFIG_THERMAL is not set | ||
590 | # CONFIG_THERMAL_HWMON is not set | ||
591 | # CONFIG_WATCHDOG is not set | ||
592 | CONFIG_SSB_POSSIBLE=y | ||
593 | |||
594 | # | ||
595 | # Sonics Silicon Backplane | ||
596 | # | ||
597 | # CONFIG_SSB is not set | ||
598 | |||
599 | # | ||
600 | # Multifunction device drivers | ||
601 | # | ||
602 | # CONFIG_MFD_CORE is not set | ||
603 | # CONFIG_MFD_SM501 is not set | ||
604 | # CONFIG_MFD_ASIC3 is not set | ||
605 | # CONFIG_HTC_EGPIO is not set | ||
606 | # CONFIG_HTC_PASIC3 is not set | ||
607 | # CONFIG_TPS65010 is not set | ||
608 | # CONFIG_TWL4030_CORE is not set | ||
609 | # CONFIG_MFD_TMIO is not set | ||
610 | # CONFIG_MFD_T7L66XB is not set | ||
611 | # CONFIG_MFD_TC6387XB is not set | ||
612 | # CONFIG_MFD_TC6393XB is not set | ||
613 | # CONFIG_PMIC_DA903X is not set | ||
614 | # CONFIG_MFD_WM8400 is not set | ||
615 | # CONFIG_MFD_WM8350_I2C is not set | ||
616 | # CONFIG_MFD_PCF50633 is not set | ||
617 | # CONFIG_AB3100_CORE is not set | ||
618 | # CONFIG_MEDIA_SUPPORT is not set | ||
619 | |||
620 | # | ||
621 | # Graphics support | ||
622 | # | ||
623 | # CONFIG_VGASTATE is not set | ||
624 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
625 | # CONFIG_FB is not set | ||
626 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
627 | |||
628 | # | ||
629 | # Display device support | ||
630 | # | ||
631 | # CONFIG_DISPLAY_SUPPORT is not set | ||
632 | |||
633 | # | ||
634 | # Console display driver support | ||
635 | # | ||
636 | # CONFIG_VGA_CONSOLE is not set | ||
637 | CONFIG_DUMMY_CONSOLE=y | ||
638 | # CONFIG_SOUND is not set | ||
639 | CONFIG_HID_SUPPORT=y | ||
640 | CONFIG_HID=y | ||
641 | CONFIG_HID_DEBUG=y | ||
642 | # CONFIG_HIDRAW is not set | ||
643 | # CONFIG_HID_PID is not set | ||
644 | |||
645 | # | ||
646 | # Special HID drivers | ||
647 | # | ||
648 | CONFIG_USB_SUPPORT=y | ||
649 | CONFIG_USB_ARCH_HAS_HCD=y | ||
650 | # CONFIG_USB_ARCH_HAS_OHCI is not set | ||
651 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
652 | # CONFIG_USB is not set | ||
653 | |||
654 | # | ||
655 | # Enable Host or Gadget support to see Inventra options | ||
656 | # | ||
657 | |||
658 | # | ||
659 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may | ||
660 | # | ||
661 | # CONFIG_USB_GADGET is not set | ||
662 | |||
663 | # | ||
664 | # OTG and related infrastructure | ||
665 | # | ||
666 | CONFIG_MMC=y | ||
667 | CONFIG_MMC_DEBUG=y | ||
668 | CONFIG_MMC_UNSAFE_RESUME=y | ||
669 | |||
670 | # | ||
671 | # MMC/SD/SDIO Card Drivers | ||
672 | # | ||
673 | CONFIG_MMC_BLOCK=y | ||
674 | CONFIG_MMC_BLOCK_BOUNCE=y | ||
675 | CONFIG_SDIO_UART=y | ||
676 | # CONFIG_MMC_TEST is not set | ||
677 | |||
678 | # | ||
679 | # MMC/SD/SDIO Host Controller Drivers | ||
680 | # | ||
681 | CONFIG_MMC_SDHCI=y | ||
682 | # CONFIG_MMC_SDHCI_PLTFM is not set | ||
683 | # CONFIG_MEMSTICK is not set | ||
684 | # CONFIG_ACCESSIBILITY is not set | ||
685 | # CONFIG_NEW_LEDS is not set | ||
686 | CONFIG_RTC_LIB=y | ||
687 | # CONFIG_RTC_CLASS is not set | ||
688 | # CONFIG_DMADEVICES is not set | ||
689 | # CONFIG_AUXDISPLAY is not set | ||
690 | # CONFIG_REGULATOR is not set | ||
691 | # CONFIG_UIO is not set | ||
692 | # CONFIG_STAGING is not set | ||
693 | |||
694 | # | ||
695 | # File systems | ||
696 | # | ||
697 | CONFIG_EXT2_FS=y | ||
698 | # CONFIG_EXT2_FS_XATTR is not set | ||
699 | # CONFIG_EXT2_FS_XIP is not set | ||
700 | CONFIG_EXT3_FS=y | ||
701 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | ||
702 | CONFIG_EXT3_FS_XATTR=y | ||
703 | CONFIG_EXT3_FS_POSIX_ACL=y | ||
704 | CONFIG_EXT3_FS_SECURITY=y | ||
705 | # CONFIG_EXT4_FS is not set | ||
706 | CONFIG_JBD=y | ||
707 | CONFIG_FS_MBCACHE=y | ||
708 | # CONFIG_REISERFS_FS is not set | ||
709 | # CONFIG_JFS_FS is not set | ||
710 | CONFIG_FS_POSIX_ACL=y | ||
711 | # CONFIG_XFS_FS is not set | ||
712 | # CONFIG_GFS2_FS is not set | ||
713 | # CONFIG_BTRFS_FS is not set | ||
714 | CONFIG_FILE_LOCKING=y | ||
715 | CONFIG_FSNOTIFY=y | ||
716 | CONFIG_DNOTIFY=y | ||
717 | CONFIG_INOTIFY=y | ||
718 | CONFIG_INOTIFY_USER=y | ||
719 | # CONFIG_QUOTA is not set | ||
720 | # CONFIG_AUTOFS_FS is not set | ||
721 | # CONFIG_AUTOFS4_FS is not set | ||
722 | # CONFIG_FUSE_FS is not set | ||
723 | CONFIG_GENERIC_ACL=y | ||
724 | |||
725 | # | ||
726 | # Caches | ||
727 | # | ||
728 | # CONFIG_FSCACHE is not set | ||
729 | |||
730 | # | ||
731 | # CD-ROM/DVD Filesystems | ||
732 | # | ||
733 | # CONFIG_ISO9660_FS is not set | ||
734 | # CONFIG_UDF_FS is not set | ||
735 | |||
736 | # | ||
737 | # DOS/FAT/NT Filesystems | ||
738 | # | ||
739 | # CONFIG_MSDOS_FS is not set | ||
740 | # CONFIG_VFAT_FS is not set | ||
741 | # CONFIG_NTFS_FS is not set | ||
742 | |||
743 | # | ||
744 | # Pseudo filesystems | ||
745 | # | ||
746 | CONFIG_PROC_FS=y | ||
747 | CONFIG_PROC_SYSCTL=y | ||
748 | CONFIG_PROC_PAGE_MONITOR=y | ||
749 | CONFIG_SYSFS=y | ||
750 | CONFIG_TMPFS=y | ||
751 | CONFIG_TMPFS_POSIX_ACL=y | ||
752 | # CONFIG_HUGETLB_PAGE is not set | ||
753 | # CONFIG_CONFIGFS_FS is not set | ||
754 | CONFIG_MISC_FILESYSTEMS=y | ||
755 | # CONFIG_ADFS_FS is not set | ||
756 | # CONFIG_AFFS_FS is not set | ||
757 | # CONFIG_HFS_FS is not set | ||
758 | # CONFIG_HFSPLUS_FS is not set | ||
759 | # CONFIG_BEFS_FS is not set | ||
760 | # CONFIG_BFS_FS is not set | ||
761 | # CONFIG_EFS_FS is not set | ||
762 | CONFIG_CRAMFS=y | ||
763 | # CONFIG_SQUASHFS is not set | ||
764 | # CONFIG_VXFS_FS is not set | ||
765 | # CONFIG_MINIX_FS is not set | ||
766 | # CONFIG_OMFS_FS is not set | ||
767 | # CONFIG_HPFS_FS is not set | ||
768 | # CONFIG_QNX4FS_FS is not set | ||
769 | CONFIG_ROMFS_FS=y | ||
770 | CONFIG_ROMFS_BACKED_BY_BLOCK=y | ||
771 | # CONFIG_ROMFS_BACKED_BY_MTD is not set | ||
772 | # CONFIG_ROMFS_BACKED_BY_BOTH is not set | ||
773 | CONFIG_ROMFS_ON_BLOCK=y | ||
774 | # CONFIG_SYSV_FS is not set | ||
775 | # CONFIG_UFS_FS is not set | ||
776 | # CONFIG_NILFS2_FS is not set | ||
777 | |||
778 | # | ||
779 | # Partition Types | ||
780 | # | ||
781 | # CONFIG_PARTITION_ADVANCED is not set | ||
782 | CONFIG_MSDOS_PARTITION=y | ||
783 | # CONFIG_NLS is not set | ||
784 | |||
785 | # | ||
786 | # Kernel hacking | ||
787 | # | ||
788 | # CONFIG_PRINTK_TIME is not set | ||
789 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
790 | CONFIG_ENABLE_MUST_CHECK=y | ||
791 | CONFIG_FRAME_WARN=1024 | ||
792 | CONFIG_MAGIC_SYSRQ=y | ||
793 | # CONFIG_UNUSED_SYMBOLS is not set | ||
794 | # CONFIG_DEBUG_FS is not set | ||
795 | # CONFIG_HEADERS_CHECK is not set | ||
796 | CONFIG_DEBUG_KERNEL=y | ||
797 | # CONFIG_DEBUG_SHIRQ is not set | ||
798 | CONFIG_DETECT_SOFTLOCKUP=y | ||
799 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
800 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
801 | CONFIG_DETECT_HUNG_TASK=y | ||
802 | # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set | ||
803 | CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 | ||
804 | CONFIG_SCHED_DEBUG=y | ||
805 | # CONFIG_SCHEDSTATS is not set | ||
806 | # CONFIG_TIMER_STATS is not set | ||
807 | # CONFIG_DEBUG_OBJECTS is not set | ||
808 | # CONFIG_SLUB_DEBUG_ON is not set | ||
809 | # CONFIG_SLUB_STATS is not set | ||
810 | # CONFIG_DEBUG_KMEMLEAK is not set | ||
811 | CONFIG_DEBUG_RT_MUTEXES=y | ||
812 | CONFIG_DEBUG_PI_LIST=y | ||
813 | # CONFIG_RT_MUTEX_TESTER is not set | ||
814 | CONFIG_DEBUG_SPINLOCK=y | ||
815 | CONFIG_DEBUG_MUTEXES=y | ||
816 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
817 | # CONFIG_PROVE_LOCKING is not set | ||
818 | # CONFIG_LOCK_STAT is not set | ||
819 | CONFIG_DEBUG_SPINLOCK_SLEEP=y | ||
820 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
821 | # CONFIG_DEBUG_KOBJECT is not set | ||
822 | CONFIG_DEBUG_BUGVERBOSE=y | ||
823 | CONFIG_DEBUG_INFO=y | ||
824 | # CONFIG_DEBUG_VM is not set | ||
825 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
826 | CONFIG_DEBUG_MEMORY_INIT=y | ||
827 | # CONFIG_DEBUG_LIST is not set | ||
828 | # CONFIG_DEBUG_SG is not set | ||
829 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
830 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
831 | # CONFIG_RCU_TORTURE_TEST is not set | ||
832 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
833 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
834 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
835 | # CONFIG_FAULT_INJECTION is not set | ||
836 | # CONFIG_LATENCYTOP is not set | ||
837 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
838 | # CONFIG_PAGE_POISONING is not set | ||
839 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
840 | CONFIG_TRACING_SUPPORT=y | ||
841 | CONFIG_FTRACE=y | ||
842 | # CONFIG_FUNCTION_TRACER is not set | ||
843 | # CONFIG_SCHED_TRACER is not set | ||
844 | # CONFIG_ENABLE_DEFAULT_TRACERS is not set | ||
845 | # CONFIG_BOOT_TRACER is not set | ||
846 | CONFIG_BRANCH_PROFILE_NONE=y | ||
847 | # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set | ||
848 | # CONFIG_PROFILE_ALL_BRANCHES is not set | ||
849 | # CONFIG_STACK_TRACER is not set | ||
850 | # CONFIG_KMEMTRACE is not set | ||
851 | # CONFIG_WORKQUEUE_TRACER is not set | ||
852 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
853 | # CONFIG_SAMPLES is not set | ||
854 | CONFIG_HAVE_ARCH_KGDB=y | ||
855 | # CONFIG_KGDB is not set | ||
856 | CONFIG_ARM_UNWIND=y | ||
857 | CONFIG_DEBUG_USER=y | ||
858 | CONFIG_DEBUG_ERRORS=y | ||
859 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
860 | CONFIG_DEBUG_LL=y | ||
861 | # CONFIG_DEBUG_ICEDCC is not set | ||
862 | CONFIG_DEBUG_S3C_PORT=y | ||
863 | CONFIG_DEBUG_S3C_UART=0 | ||
864 | |||
865 | # | ||
866 | # Security options | ||
867 | # | ||
868 | # CONFIG_KEYS is not set | ||
869 | # CONFIG_SECURITY is not set | ||
870 | # CONFIG_SECURITYFS is not set | ||
871 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
872 | # CONFIG_CRYPTO is not set | ||
873 | # CONFIG_BINARY_PRINTF is not set | ||
874 | |||
875 | # | ||
876 | # Library routines | ||
877 | # | ||
878 | CONFIG_BITREVERSE=y | ||
879 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
880 | # CONFIG_CRC_CCITT is not set | ||
881 | # CONFIG_CRC16 is not set | ||
882 | # CONFIG_CRC_T10DIF is not set | ||
883 | # CONFIG_CRC_ITU_T is not set | ||
884 | CONFIG_CRC32=y | ||
885 | # CONFIG_CRC7 is not set | ||
886 | # CONFIG_LIBCRC32C is not set | ||
887 | CONFIG_ZLIB_INFLATE=y | ||
888 | CONFIG_DECOMPRESS_GZIP=y | ||
889 | CONFIG_DECOMPRESS_BZIP2=y | ||
890 | CONFIG_DECOMPRESS_LZMA=y | ||
891 | CONFIG_HAS_IOMEM=y | ||
892 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index b7c3490eaa24..c9a8619f3856 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c | |||
@@ -86,7 +86,7 @@ int show_interrupts(struct seq_file *p, void *v) | |||
86 | unlock: | 86 | unlock: |
87 | spin_unlock_irqrestore(&irq_desc[i].lock, flags); | 87 | spin_unlock_irqrestore(&irq_desc[i].lock, flags); |
88 | } else if (i == NR_IRQS) { | 88 | } else if (i == NR_IRQS) { |
89 | #ifdef CONFIG_ARCH_ACORN | 89 | #ifdef CONFIG_FIQ |
90 | show_fiq_list(p, v); | 90 | show_fiq_list(p, v); |
91 | #endif | 91 | #endif |
92 | #ifdef CONFIG_SMP | 92 | #ifdef CONFIG_SMP |
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig index 41bb65d5b91f..d8c023d4df30 100644 --- a/arch/arm/mach-s3c2410/Kconfig +++ b/arch/arm/mach-s3c2410/Kconfig | |||
@@ -12,6 +12,7 @@ config CPU_S3C2410 | |||
12 | select S3C2410_GPIO | 12 | select S3C2410_GPIO |
13 | select CPU_LLSERIAL_S3C2410 | 13 | select CPU_LLSERIAL_S3C2410 |
14 | select S3C2410_PM if PM | 14 | select S3C2410_PM if PM |
15 | select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX | ||
15 | help | 16 | help |
16 | Support for S3C2410 and S3C2410A family from the S3C24XX line | 17 | Support for S3C2410 and S3C2410A family from the S3C24XX line |
17 | of Samsung Mobile CPUs. | 18 | of Samsung Mobile CPUs. |
@@ -45,6 +46,22 @@ config MACH_BAST_IDE | |||
45 | Internal node for machines with an BAST style IDE | 46 | Internal node for machines with an BAST style IDE |
46 | interface | 47 | interface |
47 | 48 | ||
49 | # cpu frequency scaling support | ||
50 | |||
51 | config S3C2410_CPUFREQ | ||
52 | bool | ||
53 | depends on CPU_FREQ_S3C24XX && CPU_S3C2410 | ||
54 | select S3C2410_CPUFREQ_UTILS | ||
55 | help | ||
56 | CPU Frequency scaling support for S3C2410 | ||
57 | |||
58 | config S3C2410_PLLTABLE | ||
59 | bool | ||
60 | depends on S3C2410_CPUFREQ && CPU_FREQ_S3C24XX_PLL | ||
61 | default y | ||
62 | help | ||
63 | Select the PLL table for the S3C2410 | ||
64 | |||
48 | menu "S3C2410 Machines" | 65 | menu "S3C2410 Machines" |
49 | 66 | ||
50 | config ARCH_SMDK2410 | 67 | config ARCH_SMDK2410 |
@@ -79,6 +96,7 @@ config MACH_N30 | |||
79 | config ARCH_BAST | 96 | config ARCH_BAST |
80 | bool "Simtec Electronics BAST (EB2410ITX)" | 97 | bool "Simtec Electronics BAST (EB2410ITX)" |
81 | select CPU_S3C2410 | 98 | select CPU_S3C2410 |
99 | select S3C2410_IOTIMING if S3C2410_CPUFREQ | ||
82 | select PM_SIMTEC if PM | 100 | select PM_SIMTEC if PM |
83 | select SIMTEC_NOR | 101 | select SIMTEC_NOR |
84 | select MACH_BAST_IDE | 102 | select MACH_BAST_IDE |
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile index fca02f82711c..2ab5ba4b266f 100644 --- a/arch/arm/mach-s3c2410/Makefile +++ b/arch/arm/mach-s3c2410/Makefile | |||
@@ -15,6 +15,8 @@ obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o | |||
15 | obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o | 15 | obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o |
16 | obj-$(CONFIG_S3C2410_PM) += pm.o sleep.o | 16 | obj-$(CONFIG_S3C2410_PM) += pm.o sleep.o |
17 | obj-$(CONFIG_S3C2410_GPIO) += gpio.o | 17 | obj-$(CONFIG_S3C2410_GPIO) += gpio.o |
18 | obj-$(CONFIG_S3C2410_CPUFREQ) += cpu-freq.o | ||
19 | obj-$(CONFIG_S3C2410_PLLTABLE) += pll.o | ||
18 | 20 | ||
19 | # Machine support | 21 | # Machine support |
20 | 22 | ||
diff --git a/arch/arm/mach-s3c2410/cpu-freq.c b/arch/arm/mach-s3c2410/cpu-freq.c new file mode 100644 index 000000000000..9d1186877d08 --- /dev/null +++ b/arch/arm/mach-s3c2410/cpu-freq.c | |||
@@ -0,0 +1,159 @@ | |||
1 | /* linux/arch/arm/mach-s3c2410/cpu-freq.c | ||
2 | * | ||
3 | * Copyright (c) 2006,2008 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C2410 CPU Frequency scaling | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <linux/init.h> | ||
15 | #include <linux/module.h> | ||
16 | #include <linux/interrupt.h> | ||
17 | #include <linux/ioport.h> | ||
18 | #include <linux/cpufreq.h> | ||
19 | #include <linux/sysdev.h> | ||
20 | #include <linux/clk.h> | ||
21 | #include <linux/err.h> | ||
22 | #include <linux/io.h> | ||
23 | |||
24 | #include <asm/mach/arch.h> | ||
25 | #include <asm/mach/map.h> | ||
26 | |||
27 | #include <mach/regs-clock.h> | ||
28 | |||
29 | #include <plat/cpu.h> | ||
30 | #include <plat/clock.h> | ||
31 | #include <plat/cpu-freq-core.h> | ||
32 | |||
33 | /* Note, 2410A has an extra mode for 1:4:4 ratio, bit 2 of CLKDIV */ | ||
34 | |||
35 | static void s3c2410_cpufreq_setdivs(struct s3c_cpufreq_config *cfg) | ||
36 | { | ||
37 | u32 clkdiv = 0; | ||
38 | |||
39 | if (cfg->divs.h_divisor == 2) | ||
40 | clkdiv |= S3C2410_CLKDIVN_HDIVN; | ||
41 | |||
42 | if (cfg->divs.p_divisor != cfg->divs.h_divisor) | ||
43 | clkdiv |= S3C2410_CLKDIVN_PDIVN; | ||
44 | |||
45 | __raw_writel(clkdiv, S3C2410_CLKDIVN); | ||
46 | } | ||
47 | |||
48 | static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) | ||
49 | { | ||
50 | unsigned long hclk, fclk, pclk; | ||
51 | unsigned int hdiv, pdiv; | ||
52 | unsigned long hclk_max; | ||
53 | |||
54 | fclk = cfg->freq.fclk; | ||
55 | hclk_max = cfg->max.hclk; | ||
56 | |||
57 | cfg->freq.armclk = fclk; | ||
58 | |||
59 | s3c_freq_dbg("%s: fclk is %lu, max hclk %lu\n", | ||
60 | __func__, fclk, hclk_max); | ||
61 | |||
62 | hdiv = (fclk > cfg->max.hclk) ? 2 : 1; | ||
63 | hclk = fclk / hdiv; | ||
64 | |||
65 | if (hclk > cfg->max.hclk) { | ||
66 | s3c_freq_dbg("%s: hclk too big\n", __func__); | ||
67 | return -EINVAL; | ||
68 | } | ||
69 | |||
70 | pdiv = (hclk > cfg->max.pclk) ? 2 : 1; | ||
71 | pclk = hclk / pdiv; | ||
72 | |||
73 | if (pclk > cfg->max.pclk) { | ||
74 | s3c_freq_dbg("%s: pclk too big\n", __func__); | ||
75 | return -EINVAL; | ||
76 | } | ||
77 | |||
78 | pdiv *= hdiv; | ||
79 | |||
80 | /* record the result */ | ||
81 | cfg->divs.p_divisor = pdiv; | ||
82 | cfg->divs.h_divisor = hdiv; | ||
83 | |||
84 | return 0 ; | ||
85 | } | ||
86 | |||
87 | static struct s3c_cpufreq_info s3c2410_cpufreq_info = { | ||
88 | .max = { | ||
89 | .fclk = 200000000, | ||
90 | .hclk = 100000000, | ||
91 | .pclk = 50000000, | ||
92 | }, | ||
93 | |||
94 | /* transition latency is about 5ms worst-case, so | ||
95 | * set 10ms to be sure */ | ||
96 | .latency = 10000000, | ||
97 | |||
98 | .locktime_m = 150, | ||
99 | .locktime_u = 150, | ||
100 | .locktime_bits = 12, | ||
101 | |||
102 | .need_pll = 1, | ||
103 | |||
104 | .name = "s3c2410", | ||
105 | .calc_iotiming = s3c2410_iotiming_calc, | ||
106 | .set_iotiming = s3c2410_iotiming_set, | ||
107 | .get_iotiming = s3c2410_iotiming_get, | ||
108 | .resume_clocks = s3c2410_setup_clocks, | ||
109 | |||
110 | .set_fvco = s3c2410_set_fvco, | ||
111 | .set_refresh = s3c2410_cpufreq_setrefresh, | ||
112 | .set_divs = s3c2410_cpufreq_setdivs, | ||
113 | .calc_divs = s3c2410_cpufreq_calcdivs, | ||
114 | |||
115 | .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), | ||
116 | }; | ||
117 | |||
118 | static int s3c2410_cpufreq_add(struct sys_device *sysdev) | ||
119 | { | ||
120 | return s3c_cpufreq_register(&s3c2410_cpufreq_info); | ||
121 | } | ||
122 | |||
123 | static struct sysdev_driver s3c2410_cpufreq_driver = { | ||
124 | .add = s3c2410_cpufreq_add, | ||
125 | }; | ||
126 | |||
127 | static int __init s3c2410_cpufreq_init(void) | ||
128 | { | ||
129 | return sysdev_driver_register(&s3c2410_sysclass, | ||
130 | &s3c2410_cpufreq_driver); | ||
131 | } | ||
132 | |||
133 | arch_initcall(s3c2410_cpufreq_init); | ||
134 | |||
135 | static int s3c2410a_cpufreq_add(struct sys_device *sysdev) | ||
136 | { | ||
137 | /* alter the maximum freq settings for S3C2410A. If a board knows | ||
138 | * it only has a maximum of 200, then it should register its own | ||
139 | * limits. */ | ||
140 | |||
141 | s3c2410_cpufreq_info.max.fclk = 266000000; | ||
142 | s3c2410_cpufreq_info.max.hclk = 133000000; | ||
143 | s3c2410_cpufreq_info.max.pclk = 66500000; | ||
144 | s3c2410_cpufreq_info.name = "s3c2410a"; | ||
145 | |||
146 | return s3c2410_cpufreq_add(sysdev); | ||
147 | } | ||
148 | |||
149 | static struct sysdev_driver s3c2410a_cpufreq_driver = { | ||
150 | .add = s3c2410a_cpufreq_add, | ||
151 | }; | ||
152 | |||
153 | static int __init s3c2410a_cpufreq_init(void) | ||
154 | { | ||
155 | return sysdev_driver_register(&s3c2410a_sysclass, | ||
156 | &s3c2410a_cpufreq_driver); | ||
157 | } | ||
158 | |||
159 | arch_initcall(s3c2410a_cpufreq_init); | ||
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c index dbf96e60d992..63b753f56c64 100644 --- a/arch/arm/mach-s3c2410/dma.c +++ b/arch/arm/mach-s3c2410/dma.c | |||
@@ -164,6 +164,17 @@ static int __init s3c2410_dma_drvinit(void) | |||
164 | } | 164 | } |
165 | 165 | ||
166 | arch_initcall(s3c2410_dma_drvinit); | 166 | arch_initcall(s3c2410_dma_drvinit); |
167 | |||
168 | static struct sysdev_driver s3c2410a_dma_driver = { | ||
169 | .add = s3c2410_dma_add, | ||
170 | }; | ||
171 | |||
172 | static int __init s3c2410a_dma_drvinit(void) | ||
173 | { | ||
174 | return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_dma_driver); | ||
175 | } | ||
176 | |||
177 | arch_initcall(s3c2410a_dma_drvinit); | ||
167 | #endif | 178 | #endif |
168 | 179 | ||
169 | #if defined(CONFIG_CPU_S3C2442) | 180 | #if defined(CONFIG_CPU_S3C2442) |
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-core.h b/arch/arm/mach-s3c2410/include/mach/gpio-core.h index 8fe192081d3a..f8b879a7973c 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio-core.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio-core.h | |||
@@ -28,7 +28,7 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin) | |||
28 | return NULL; | 28 | return NULL; |
29 | 29 | ||
30 | chip = &s3c24xx_gpios[pin/32]; | 30 | chip = &s3c24xx_gpios[pin/32]; |
31 | return (S3C2410_GPIO_OFFSET(pin) > chip->chip.ngpio) ? chip : NULL; | 31 | return (S3C2410_GPIO_OFFSET(pin) < chip->chip.ngpio) ? chip : NULL; |
32 | } | 32 | } |
33 | 33 | ||
34 | #endif /* __ASM_ARCH_GPIO_CORE_H */ | 34 | #endif /* __ASM_ARCH_GPIO_CORE_H */ |
diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h index 2a2384ffa7b1..6c12c6312ad8 100644 --- a/arch/arm/mach-s3c2410/include/mach/irqs.h +++ b/arch/arm/mach-s3c2410/include/mach/irqs.h | |||
@@ -164,6 +164,12 @@ | |||
164 | #define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3 | 164 | #define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3 |
165 | #define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3 | 165 | #define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3 |
166 | 166 | ||
167 | #ifdef CONFIG_CPU_S3C2440 | ||
168 | #define IRQ_S3C244x_AC97 IRQ_S3C2440_AC97 | ||
169 | #else | ||
170 | #define IRQ_S3C244x_AC97 IRQ_S3C2443_AC97 | ||
171 | #endif | ||
172 | |||
167 | /* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */ | 173 | /* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */ |
168 | #define FIQ_START IRQ_EINT0 | 174 | #define FIQ_START IRQ_EINT0 |
169 | 175 | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h index e99b212cb1ca..b049e61460b6 100644 --- a/arch/arm/mach-s3c2410/include/mach/map.h +++ b/arch/arm/mach-s3c2410/include/mach/map.h | |||
@@ -67,6 +67,13 @@ | |||
67 | #define S3C2443_PA_HSMMC (0x4A800000) | 67 | #define S3C2443_PA_HSMMC (0x4A800000) |
68 | #define S3C2443_SZ_HSMMC (256) | 68 | #define S3C2443_SZ_HSMMC (256) |
69 | 69 | ||
70 | /* S3C2412 memory and IO controls */ | ||
71 | #define S3C2412_PA_SSMC (0x4F000000) | ||
72 | #define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000) | ||
73 | |||
74 | #define S3C2412_PA_EBI (0x48800000) | ||
75 | #define S3C2412_VA_EBI S3C_ADDR_CPU(0x00010000) | ||
76 | |||
70 | /* physical addresses of all the chip-select areas */ | 77 | /* physical addresses of all the chip-select areas */ |
71 | 78 | ||
72 | #define S3C2410_CS0 (0x00000000) | 79 | #define S3C2410_CS0 (0x00000000) |
@@ -103,5 +110,6 @@ | |||
103 | #define S3C_PA_UART S3C24XX_PA_UART | 110 | #define S3C_PA_UART S3C24XX_PA_UART |
104 | #define S3C_PA_USBHOST S3C2410_PA_USBHOST | 111 | #define S3C_PA_USBHOST S3C2410_PA_USBHOST |
105 | #define S3C_PA_HSMMC0 S3C2443_PA_HSMMC | 112 | #define S3C_PA_HSMMC0 S3C2443_PA_HSMMC |
113 | #define S3C_PA_NAND S3C24XX_PA_NAND | ||
106 | 114 | ||
107 | #endif /* __ASM_ARCH_MAP_H */ | 115 | #endif /* __ASM_ARCH_MAP_H */ |
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h index b278d0c45ccf..f6e8eec879c8 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h | |||
@@ -328,13 +328,15 @@ | |||
328 | 328 | ||
329 | #define S3C2410_GPD8_VD16 (0x02 << 16) | 329 | #define S3C2410_GPD8_VD16 (0x02 << 16) |
330 | #define S3C2400_GPD8_TOUT3 (0x02 << 16) | 330 | #define S3C2400_GPD8_TOUT3 (0x02 << 16) |
331 | #define S3C2440_GPD8_SPIMISO1 (0x03 << 16) | ||
331 | 332 | ||
332 | #define S3C2410_GPD9_VD17 (0x02 << 18) | 333 | #define S3C2410_GPD9_VD17 (0x02 << 18) |
333 | #define S3C2400_GPD9_TCLK0 (0x02 << 18) | 334 | #define S3C2400_GPD9_TCLK0 (0x02 << 18) |
334 | #define S3C2410_GPD9_MASK (0x03 << 18) | 335 | #define S3C2440_GPD9_SPIMOSI1 (0x03 << 18) |
335 | 336 | ||
336 | #define S3C2410_GPD10_VD18 (0x02 << 20) | 337 | #define S3C2410_GPD10_VD18 (0x02 << 20) |
337 | #define S3C2400_GPD10_nWAIT (0x02 << 20) | 338 | #define S3C2400_GPD10_nWAIT (0x02 << 20) |
339 | #define S3C2440_GPD10_SPICLK1 (0x03 << 20) | ||
338 | 340 | ||
339 | #define S3C2410_GPD11_VD19 (0x02 << 22) | 341 | #define S3C2410_GPD11_VD19 (0x02 << 22) |
340 | 342 | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-mem.h index 57759804e2fa..7f7c52947963 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-mem.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-mem.h | |||
@@ -73,6 +73,16 @@ | |||
73 | #define S3C2410_BWSCON_WS7 (1<<30) | 73 | #define S3C2410_BWSCON_WS7 (1<<30) |
74 | #define S3C2410_BWSCON_ST7 (1<<31) | 74 | #define S3C2410_BWSCON_ST7 (1<<31) |
75 | 75 | ||
76 | /* accesor functions for getting BANK(n) configuration. (n != 0) */ | ||
77 | |||
78 | #define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf) | ||
79 | |||
80 | #define S3C2410_BWSCON_DW8 (0) | ||
81 | #define S3C2410_BWSCON_DW16 (1) | ||
82 | #define S3C2410_BWSCON_DW32 (2) | ||
83 | #define S3C2410_BWSCON_WS (1 << 2) | ||
84 | #define S3C2410_BWSCON_ST (1 << 3) | ||
85 | |||
76 | /* memory set (rom, ram) */ | 86 | /* memory set (rom, ram) */ |
77 | #define S3C2410_BANKCON0 S3C2410_MEMREG(0x0004) | 87 | #define S3C2410_BANKCON0 S3C2410_MEMREG(0x0004) |
78 | #define S3C2410_BANKCON1 S3C2410_MEMREG(0x0008) | 88 | #define S3C2410_BANKCON1 S3C2410_MEMREG(0x0008) |
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h index a4bf27123170..fb6352515090 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h | |||
@@ -14,9 +14,11 @@ | |||
14 | #ifndef __ASM_ARM_REGS_S3C2412_MEM | 14 | #ifndef __ASM_ARM_REGS_S3C2412_MEM |
15 | #define __ASM_ARM_REGS_S3C2412_MEM | 15 | #define __ASM_ARM_REGS_S3C2412_MEM |
16 | 16 | ||
17 | #ifndef S3C2412_MEMREG | ||
18 | #define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) | 17 | #define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) |
19 | #endif | 18 | #define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x)) |
19 | |||
20 | #define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x)) | ||
21 | #define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o))) | ||
20 | 22 | ||
21 | #define S3C2412_BANKCFG S3C2412_MEMREG(0x00) | 23 | #define S3C2412_BANKCFG S3C2412_MEMREG(0x00) |
22 | #define S3C2412_BANKCON1 S3C2412_MEMREG(0x04) | 24 | #define S3C2412_BANKCON1 S3C2412_MEMREG(0x04) |
@@ -26,4 +28,21 @@ | |||
26 | #define S3C2412_REFRESH S3C2412_MEMREG(0x10) | 28 | #define S3C2412_REFRESH S3C2412_MEMREG(0x10) |
27 | #define S3C2412_TIMEOUT S3C2412_MEMREG(0x14) | 29 | #define S3C2412_TIMEOUT S3C2412_MEMREG(0x14) |
28 | 30 | ||
31 | /* EBI control registers */ | ||
32 | |||
33 | #define S3C2412_EBI_PR S3C2412_EBIREG(0x00) | ||
34 | #define S3C2412_EBI_BANKCFG S3C2412_EBIREG(0x04) | ||
35 | |||
36 | /* SSMC control registers */ | ||
37 | |||
38 | #define S3C2412_SSMC_BANK(x) S3C2412_SSMC(x, 0x00) | ||
39 | #define S3C2412_SMIDCYR(x) S3C2412_SSMC(x, 0x00) | ||
40 | #define S3C2412_SMBWSTRD(x) S3C2412_SSMC(x, 0x04) | ||
41 | #define S3C2412_SMBWSTWRR(x) S3C2412_SSMC(x, 0x08) | ||
42 | #define S3C2412_SMBWSTOENR(x) S3C2412_SSMC(x, 0x0C) | ||
43 | #define S3C2412_SMBWSTWENR(x) S3C2412_SSMC(x, 0x10) | ||
44 | #define S3C2412_SMBCR(x) S3C2412_SSMC(x, 0x14) | ||
45 | #define S3C2412_SMBSR(x) S3C2412_SSMC(x, 0x18) | ||
46 | #define S3C2412_SMBWSTBRDR(x) S3C2412_SSMC(x, 0x1C) | ||
47 | |||
29 | #endif /* __ASM_ARM_REGS_S3C2412_MEM */ | 48 | #endif /* __ASM_ARM_REGS_S3C2412_MEM */ |
diff --git a/arch/arm/mach-s3c2410/include/mach/spi.h b/arch/arm/mach-s3c2410/include/mach/spi.h index 1d300fb112b1..193b39d654ed 100644 --- a/arch/arm/mach-s3c2410/include/mach/spi.h +++ b/arch/arm/mach-s3c2410/include/mach/spi.h | |||
@@ -30,4 +30,7 @@ extern void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi, | |||
30 | extern void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi, | 30 | extern void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi, |
31 | int enable); | 31 | int enable); |
32 | 32 | ||
33 | extern void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi, | ||
34 | int enable); | ||
35 | |||
33 | #endif /* __ASM_ARCH_SPI_H */ | 36 | #endif /* __ASM_ARCH_SPI_H */ |
diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c index 92150399563b..5e2f35332056 100644 --- a/arch/arm/mach-s3c2410/irq.c +++ b/arch/arm/mach-s3c2410/irq.c | |||
@@ -39,9 +39,22 @@ static struct sysdev_driver s3c2410_irq_driver = { | |||
39 | .resume = s3c24xx_irq_resume, | 39 | .resume = s3c24xx_irq_resume, |
40 | }; | 40 | }; |
41 | 41 | ||
42 | static int s3c2410_irq_init(void) | 42 | static int __init s3c2410_irq_init(void) |
43 | { | 43 | { |
44 | return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_irq_driver); | 44 | return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_irq_driver); |
45 | } | 45 | } |
46 | 46 | ||
47 | arch_initcall(s3c2410_irq_init); | 47 | arch_initcall(s3c2410_irq_init); |
48 | |||
49 | static struct sysdev_driver s3c2410a_irq_driver = { | ||
50 | .add = s3c2410_irq_add, | ||
51 | .suspend = s3c24xx_irq_suspend, | ||
52 | .resume = s3c24xx_irq_resume, | ||
53 | }; | ||
54 | |||
55 | static int __init s3c2410a_irq_init(void) | ||
56 | { | ||
57 | return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_irq_driver); | ||
58 | } | ||
59 | |||
60 | arch_initcall(s3c2410a_irq_init); | ||
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c index ce3baba2cd7f..647c9adb018f 100644 --- a/arch/arm/mach-s3c2410/mach-bast.c +++ b/arch/arm/mach-s3c2410/mach-bast.c | |||
@@ -45,6 +45,7 @@ | |||
45 | #include <mach/regs-mem.h> | 45 | #include <mach/regs-mem.h> |
46 | #include <mach/regs-lcd.h> | 46 | #include <mach/regs-lcd.h> |
47 | 47 | ||
48 | #include <plat/hwmon.h> | ||
48 | #include <plat/nand.h> | 49 | #include <plat/nand.h> |
49 | #include <plat/iic.h> | 50 | #include <plat/iic.h> |
50 | #include <mach/fb.h> | 51 | #include <mach/fb.h> |
@@ -59,6 +60,7 @@ | |||
59 | #include <plat/clock.h> | 60 | #include <plat/clock.h> |
60 | #include <plat/devs.h> | 61 | #include <plat/devs.h> |
61 | #include <plat/cpu.h> | 62 | #include <plat/cpu.h> |
63 | #include <plat/cpu-freq.h> | ||
62 | 64 | ||
63 | #include "usb-simtec.h" | 65 | #include "usb-simtec.h" |
64 | #include "nor-simtec.h" | 66 | #include "nor-simtec.h" |
@@ -547,7 +549,35 @@ static struct i2c_board_info bast_i2c_devs[] __initdata = { | |||
547 | }, | 549 | }, |
548 | }; | 550 | }; |
549 | 551 | ||
552 | static struct s3c_hwmon_pdata bast_hwmon_info = { | ||
553 | /* LCD contrast (0-6.6V) */ | ||
554 | .in[0] = &(struct s3c_hwmon_chcfg) { | ||
555 | .name = "lcd-contrast", | ||
556 | .mult = 3300, | ||
557 | .div = 512, | ||
558 | }, | ||
559 | /* LED current feedback */ | ||
560 | .in[1] = &(struct s3c_hwmon_chcfg) { | ||
561 | .name = "led-feedback", | ||
562 | .mult = 3300, | ||
563 | .div = 1024, | ||
564 | }, | ||
565 | /* LCD feedback (0-6.6V) */ | ||
566 | .in[2] = &(struct s3c_hwmon_chcfg) { | ||
567 | .name = "lcd-feedback", | ||
568 | .mult = 3300, | ||
569 | .div = 512, | ||
570 | }, | ||
571 | /* Vcore (1.8-2.0V), Vref 3.3V */ | ||
572 | .in[3] = &(struct s3c_hwmon_chcfg) { | ||
573 | .name = "vcore", | ||
574 | .mult = 3300, | ||
575 | .div = 1024, | ||
576 | }, | ||
577 | }; | ||
578 | |||
550 | /* Standard BAST devices */ | 579 | /* Standard BAST devices */ |
580 | // cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0 | ||
551 | 581 | ||
552 | static struct platform_device *bast_devices[] __initdata = { | 582 | static struct platform_device *bast_devices[] __initdata = { |
553 | &s3c_device_usb, | 583 | &s3c_device_usb, |
@@ -556,6 +586,8 @@ static struct platform_device *bast_devices[] __initdata = { | |||
556 | &s3c_device_i2c0, | 586 | &s3c_device_i2c0, |
557 | &s3c_device_rtc, | 587 | &s3c_device_rtc, |
558 | &s3c_device_nand, | 588 | &s3c_device_nand, |
589 | &s3c_device_adc, | ||
590 | &s3c_device_hwmon, | ||
559 | &bast_device_dm9k, | 591 | &bast_device_dm9k, |
560 | &bast_device_asix, | 592 | &bast_device_asix, |
561 | &bast_device_axpp, | 593 | &bast_device_axpp, |
@@ -570,6 +602,12 @@ static struct clk *bast_clocks[] __initdata = { | |||
570 | &s3c24xx_uclk, | 602 | &s3c24xx_uclk, |
571 | }; | 603 | }; |
572 | 604 | ||
605 | static struct s3c_cpufreq_board __initdata bast_cpufreq = { | ||
606 | .refresh = 7800, /* 7.8usec */ | ||
607 | .auto_io = 1, | ||
608 | .need_io = 1, | ||
609 | }; | ||
610 | |||
573 | static void __init bast_map_io(void) | 611 | static void __init bast_map_io(void) |
574 | { | 612 | { |
575 | /* initialise the clocks */ | 613 | /* initialise the clocks */ |
@@ -588,6 +626,7 @@ static void __init bast_map_io(void) | |||
588 | s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks)); | 626 | s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks)); |
589 | 627 | ||
590 | s3c_device_nand.dev.platform_data = &bast_nand_info; | 628 | s3c_device_nand.dev.platform_data = &bast_nand_info; |
629 | s3c_device_hwmon.dev.platform_data = &bast_hwmon_info; | ||
591 | 630 | ||
592 | s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); | 631 | s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); |
593 | s3c24xx_init_clocks(0); | 632 | s3c24xx_init_clocks(0); |
@@ -608,6 +647,8 @@ static void __init bast_init(void) | |||
608 | 647 | ||
609 | usb_simtec_init(); | 648 | usb_simtec_init(); |
610 | nor_simtec_init(); | 649 | nor_simtec_init(); |
650 | |||
651 | s3c_cpufreq_setboard(&bast_cpufreq); | ||
611 | } | 652 | } |
612 | 653 | ||
613 | MACHINE_START(BAST, "Simtec-BAST") | 654 | MACHINE_START(BAST, "Simtec-BAST") |
diff --git a/arch/arm/mach-s3c2410/pll.c b/arch/arm/mach-s3c2410/pll.c new file mode 100644 index 000000000000..f178c2fd9d85 --- /dev/null +++ b/arch/arm/mach-s3c2410/pll.c | |||
@@ -0,0 +1,95 @@ | |||
1 | /* arch/arm/mach-s3c2410/pll.c | ||
2 | * | ||
3 | * Copyright (c) 2006,2007 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * Vincent Sanders <vince@arm.linux.org.uk> | ||
7 | * | ||
8 | * S3C2410 CPU PLL tables | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License as published by | ||
12 | * the Free Software Foundation; either version 2 of the License, or | ||
13 | * (at your option) any later version. | ||
14 | * | ||
15 | * This program is distributed in the hope that it will be useful, | ||
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
18 | * GNU General Public License for more details. | ||
19 | * | ||
20 | * You should have received a copy of the GNU General Public License | ||
21 | * along with this program; if not, write to the Free Software | ||
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
23 | */ | ||
24 | |||
25 | #include <linux/types.h> | ||
26 | #include <linux/kernel.h> | ||
27 | #include <linux/module.h> | ||
28 | #include <linux/sysdev.h> | ||
29 | #include <linux/list.h> | ||
30 | #include <linux/clk.h> | ||
31 | #include <linux/err.h> | ||
32 | |||
33 | #include <plat/cpu.h> | ||
34 | #include <plat/cpu-freq-core.h> | ||
35 | |||
36 | static struct cpufreq_frequency_table pll_vals_12MHz[] = { | ||
37 | { .frequency = 34000000, .index = PLLVAL(82, 2, 3), }, | ||
38 | { .frequency = 45000000, .index = PLLVAL(82, 1, 3), }, | ||
39 | { .frequency = 51000000, .index = PLLVAL(161, 3, 3), }, | ||
40 | { .frequency = 48000000, .index = PLLVAL(120, 2, 3), }, | ||
41 | { .frequency = 56000000, .index = PLLVAL(142, 2, 3), }, | ||
42 | { .frequency = 68000000, .index = PLLVAL(82, 2, 2), }, | ||
43 | { .frequency = 79000000, .index = PLLVAL(71, 1, 2), }, | ||
44 | { .frequency = 85000000, .index = PLLVAL(105, 2, 2), }, | ||
45 | { .frequency = 90000000, .index = PLLVAL(112, 2, 2), }, | ||
46 | { .frequency = 101000000, .index = PLLVAL(127, 2, 2), }, | ||
47 | { .frequency = 113000000, .index = PLLVAL(105, 1, 2), }, | ||
48 | { .frequency = 118000000, .index = PLLVAL(150, 2, 2), }, | ||
49 | { .frequency = 124000000, .index = PLLVAL(116, 1, 2), }, | ||
50 | { .frequency = 135000000, .index = PLLVAL(82, 2, 1), }, | ||
51 | { .frequency = 147000000, .index = PLLVAL(90, 2, 1), }, | ||
52 | { .frequency = 152000000, .index = PLLVAL(68, 1, 1), }, | ||
53 | { .frequency = 158000000, .index = PLLVAL(71, 1, 1), }, | ||
54 | { .frequency = 170000000, .index = PLLVAL(77, 1, 1), }, | ||
55 | { .frequency = 180000000, .index = PLLVAL(82, 1, 1), }, | ||
56 | { .frequency = 186000000, .index = PLLVAL(85, 1, 1), }, | ||
57 | { .frequency = 192000000, .index = PLLVAL(88, 1, 1), }, | ||
58 | { .frequency = 203000000, .index = PLLVAL(161, 3, 1), }, | ||
59 | |||
60 | /* 2410A extras */ | ||
61 | |||
62 | { .frequency = 210000000, .index = PLLVAL(132, 2, 1), }, | ||
63 | { .frequency = 226000000, .index = PLLVAL(105, 1, 1), }, | ||
64 | { .frequency = 266000000, .index = PLLVAL(125, 1, 1), }, | ||
65 | { .frequency = 268000000, .index = PLLVAL(126, 1, 1), }, | ||
66 | { .frequency = 270000000, .index = PLLVAL(127, 1, 1), }, | ||
67 | }; | ||
68 | |||
69 | static int s3c2410_plls_add(struct sys_device *dev) | ||
70 | { | ||
71 | return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz)); | ||
72 | } | ||
73 | |||
74 | static struct sysdev_driver s3c2410_plls_drv = { | ||
75 | .add = s3c2410_plls_add, | ||
76 | }; | ||
77 | |||
78 | static int __init s3c2410_pll_init(void) | ||
79 | { | ||
80 | return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_plls_drv); | ||
81 | |||
82 | } | ||
83 | |||
84 | arch_initcall(s3c2410_pll_init); | ||
85 | |||
86 | static struct sysdev_driver s3c2410a_plls_drv = { | ||
87 | .add = s3c2410_plls_add, | ||
88 | }; | ||
89 | |||
90 | static int __init s3c2410a_pll_init(void) | ||
91 | { | ||
92 | return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_plls_drv); | ||
93 | } | ||
94 | |||
95 | arch_initcall(s3c2410a_pll_init); | ||
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c index 143e08a599d4..966119c8efee 100644 --- a/arch/arm/mach-s3c2410/pm.c +++ b/arch/arm/mach-s3c2410/pm.c | |||
@@ -119,6 +119,18 @@ static int __init s3c2410_pm_drvinit(void) | |||
119 | } | 119 | } |
120 | 120 | ||
121 | arch_initcall(s3c2410_pm_drvinit); | 121 | arch_initcall(s3c2410_pm_drvinit); |
122 | |||
123 | static struct sysdev_driver s3c2410a_pm_driver = { | ||
124 | .add = s3c2410_pm_add, | ||
125 | .resume = s3c2410_pm_resume, | ||
126 | }; | ||
127 | |||
128 | static int __init s3c2410a_pm_drvinit(void) | ||
129 | { | ||
130 | return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_pm_driver); | ||
131 | } | ||
132 | |||
133 | arch_initcall(s3c2410a_pm_drvinit); | ||
122 | #endif | 134 | #endif |
123 | 135 | ||
124 | #if defined(CONFIG_CPU_S3C2440) | 136 | #if defined(CONFIG_CPU_S3C2440) |
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c index feb141b1f915..91ba42f688ac 100644 --- a/arch/arm/mach-s3c2410/s3c2410.c +++ b/arch/arm/mach-s3c2410/s3c2410.c | |||
@@ -105,17 +105,33 @@ void __init_or_cpufreq s3c2410_setup_clocks(void) | |||
105 | s3c24xx_setup_clocks(fclk, hclk, pclk); | 105 | s3c24xx_setup_clocks(fclk, hclk, pclk); |
106 | } | 106 | } |
107 | 107 | ||
108 | /* fake ARMCLK for use with cpufreq, etc. */ | ||
109 | |||
110 | static struct clk s3c2410_armclk = { | ||
111 | .name = "armclk", | ||
112 | .parent = &clk_f, | ||
113 | .id = -1, | ||
114 | }; | ||
115 | |||
108 | void __init s3c2410_init_clocks(int xtal) | 116 | void __init s3c2410_init_clocks(int xtal) |
109 | { | 117 | { |
110 | s3c24xx_register_baseclocks(xtal); | 118 | s3c24xx_register_baseclocks(xtal); |
111 | s3c2410_setup_clocks(); | 119 | s3c2410_setup_clocks(); |
112 | s3c2410_baseclk_add(); | 120 | s3c2410_baseclk_add(); |
121 | s3c24xx_register_clock(&s3c2410_armclk); | ||
113 | } | 122 | } |
114 | 123 | ||
115 | struct sysdev_class s3c2410_sysclass = { | 124 | struct sysdev_class s3c2410_sysclass = { |
116 | .name = "s3c2410-core", | 125 | .name = "s3c2410-core", |
117 | }; | 126 | }; |
118 | 127 | ||
128 | /* Note, we would have liked to name this s3c2410-core, but we cannot | ||
129 | * register two sysdev_class with the same name. | ||
130 | */ | ||
131 | struct sysdev_class s3c2410a_sysclass = { | ||
132 | .name = "s3c2410a-core", | ||
133 | }; | ||
134 | |||
119 | static struct sys_device s3c2410_sysdev = { | 135 | static struct sys_device s3c2410_sysdev = { |
120 | .cls = &s3c2410_sysclass, | 136 | .cls = &s3c2410_sysclass, |
121 | }; | 137 | }; |
@@ -133,9 +149,22 @@ static int __init s3c2410_core_init(void) | |||
133 | 149 | ||
134 | core_initcall(s3c2410_core_init); | 150 | core_initcall(s3c2410_core_init); |
135 | 151 | ||
152 | static int __init s3c2410a_core_init(void) | ||
153 | { | ||
154 | return sysdev_class_register(&s3c2410a_sysclass); | ||
155 | } | ||
156 | |||
157 | core_initcall(s3c2410a_core_init); | ||
158 | |||
136 | int __init s3c2410_init(void) | 159 | int __init s3c2410_init(void) |
137 | { | 160 | { |
138 | printk("S3C2410: Initialising architecture\n"); | 161 | printk("S3C2410: Initialising architecture\n"); |
139 | 162 | ||
140 | return sysdev_register(&s3c2410_sysdev); | 163 | return sysdev_register(&s3c2410_sysdev); |
141 | } | 164 | } |
165 | |||
166 | int __init s3c2410a_init(void) | ||
167 | { | ||
168 | s3c2410_sysdev.cls = &s3c2410a_sysclass; | ||
169 | return s3c2410_init(); | ||
170 | } | ||
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig index 63586ffd0ae7..35c1bde89cf2 100644 --- a/arch/arm/mach-s3c2412/Kconfig +++ b/arch/arm/mach-s3c2412/Kconfig | |||
@@ -32,6 +32,15 @@ config S3C2412_PM | |||
32 | help | 32 | help |
33 | Internal config node to apply S3C2412 power management | 33 | Internal config node to apply S3C2412 power management |
34 | 34 | ||
35 | # Note, the S3C2412 IOtiming support is in plat-s3c24xx | ||
36 | |||
37 | config S3C2412_CPUFREQ | ||
38 | bool | ||
39 | depends on CPU_FREQ_S3C24XX && CPU_S3C2412 | ||
40 | select S3C2412_IOTIMING | ||
41 | default y | ||
42 | help | ||
43 | CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs. | ||
35 | 44 | ||
36 | menu "S3C2412 Machines" | 45 | menu "S3C2412 Machines" |
37 | 46 | ||
diff --git a/arch/arm/mach-s3c2412/Makefile b/arch/arm/mach-s3c2412/Makefile index 20918d5dc6a9..530ec46cbaea 100644 --- a/arch/arm/mach-s3c2412/Makefile +++ b/arch/arm/mach-s3c2412/Makefile | |||
@@ -15,6 +15,7 @@ obj-$(CONFIG_CPU_S3C2412) += clock.o | |||
15 | obj-$(CONFIG_CPU_S3C2412) += gpio.o | 15 | obj-$(CONFIG_CPU_S3C2412) += gpio.o |
16 | obj-$(CONFIG_S3C2412_DMA) += dma.o | 16 | obj-$(CONFIG_S3C2412_DMA) += dma.o |
17 | obj-$(CONFIG_S3C2412_PM) += pm.o sleep.o | 17 | obj-$(CONFIG_S3C2412_PM) += pm.o sleep.o |
18 | obj-$(CONFIG_S3C2412_CPUFREQ) += cpu-freq.o | ||
18 | 19 | ||
19 | # Machine support | 20 | # Machine support |
20 | 21 | ||
diff --git a/arch/arm/mach-s3c2412/cpu-freq.c b/arch/arm/mach-s3c2412/cpu-freq.c new file mode 100644 index 000000000000..eb3ea1721335 --- /dev/null +++ b/arch/arm/mach-s3c2412/cpu-freq.c | |||
@@ -0,0 +1,257 @@ | |||
1 | /* linux/arch/arm/mach-s3c2412/cpu-freq.c | ||
2 | * | ||
3 | * Copyright 2008 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C2412 CPU Frequency scalling | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <linux/init.h> | ||
15 | #include <linux/module.h> | ||
16 | #include <linux/interrupt.h> | ||
17 | #include <linux/ioport.h> | ||
18 | #include <linux/cpufreq.h> | ||
19 | #include <linux/sysdev.h> | ||
20 | #include <linux/delay.h> | ||
21 | #include <linux/clk.h> | ||
22 | #include <linux/err.h> | ||
23 | #include <linux/io.h> | ||
24 | |||
25 | #include <asm/mach/arch.h> | ||
26 | #include <asm/mach/map.h> | ||
27 | |||
28 | #include <mach/regs-clock.h> | ||
29 | #include <mach/regs-s3c2412-mem.h> | ||
30 | |||
31 | #include <plat/cpu.h> | ||
32 | #include <plat/clock.h> | ||
33 | #include <plat/cpu-freq-core.h> | ||
34 | |||
35 | /* our clock resources. */ | ||
36 | static struct clk *xtal; | ||
37 | static struct clk *fclk; | ||
38 | static struct clk *hclk; | ||
39 | static struct clk *armclk; | ||
40 | |||
41 | /* HDIV: 1, 2, 3, 4, 6, 8 */ | ||
42 | |||
43 | static int s3c2412_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) | ||
44 | { | ||
45 | unsigned int hdiv, pdiv, armdiv, dvs; | ||
46 | unsigned long hclk, fclk, armclk, armdiv_clk; | ||
47 | unsigned long hclk_max; | ||
48 | |||
49 | fclk = cfg->freq.fclk; | ||
50 | armclk = cfg->freq.armclk; | ||
51 | hclk_max = cfg->max.hclk; | ||
52 | |||
53 | /* We can't run hclk above armclk as at the best we have to | ||
54 | * have armclk and hclk in dvs mode. */ | ||
55 | |||
56 | if (hclk_max > armclk) | ||
57 | hclk_max = armclk; | ||
58 | |||
59 | s3c_freq_dbg("%s: fclk=%lu, armclk=%lu, hclk_max=%lu\n", | ||
60 | __func__, fclk, armclk, hclk_max); | ||
61 | s3c_freq_dbg("%s: want f=%lu, arm=%lu, h=%lu, p=%lu\n", | ||
62 | __func__, cfg->freq.fclk, cfg->freq.armclk, | ||
63 | cfg->freq.hclk, cfg->freq.pclk); | ||
64 | |||
65 | armdiv = fclk / armclk; | ||
66 | |||
67 | if (armdiv < 1) | ||
68 | armdiv = 1; | ||
69 | if (armdiv > 2) | ||
70 | armdiv = 2; | ||
71 | |||
72 | cfg->divs.arm_divisor = armdiv; | ||
73 | armdiv_clk = fclk / armdiv; | ||
74 | |||
75 | hdiv = armdiv_clk / hclk_max; | ||
76 | if (hdiv < 1) | ||
77 | hdiv = 1; | ||
78 | |||
79 | cfg->freq.hclk = hclk = armdiv_clk / hdiv; | ||
80 | |||
81 | /* set dvs depending on whether we reached armclk or not. */ | ||
82 | cfg->divs.dvs = dvs = armclk < armdiv_clk; | ||
83 | |||
84 | /* update the actual armclk we achieved. */ | ||
85 | cfg->freq.armclk = dvs ? hclk : armdiv_clk; | ||
86 | |||
87 | s3c_freq_dbg("%s: armclk %lu, hclk %lu, armdiv %d, hdiv %d, dvs %d\n", | ||
88 | __func__, armclk, hclk, armdiv, hdiv, cfg->divs.dvs); | ||
89 | |||
90 | if (hdiv > 4) | ||
91 | goto invalid; | ||
92 | |||
93 | pdiv = (hclk > cfg->max.pclk) ? 2 : 1; | ||
94 | |||
95 | if ((hclk / pdiv) > cfg->max.pclk) | ||
96 | pdiv++; | ||
97 | |||
98 | cfg->freq.pclk = hclk / pdiv; | ||
99 | |||
100 | s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv); | ||
101 | |||
102 | if (pdiv > 2) | ||
103 | goto invalid; | ||
104 | |||
105 | pdiv *= hdiv; | ||
106 | |||
107 | /* store the result, and then return */ | ||
108 | |||
109 | cfg->divs.h_divisor = hdiv * armdiv; | ||
110 | cfg->divs.p_divisor = pdiv * armdiv; | ||
111 | |||
112 | return 0; | ||
113 | |||
114 | invalid: | ||
115 | return -EINVAL; | ||
116 | } | ||
117 | |||
118 | static void s3c2412_cpufreq_setdivs(struct s3c_cpufreq_config *cfg) | ||
119 | { | ||
120 | unsigned long clkdiv; | ||
121 | unsigned long olddiv; | ||
122 | |||
123 | olddiv = clkdiv = __raw_readl(S3C2410_CLKDIVN); | ||
124 | |||
125 | /* clear off current clock info */ | ||
126 | |||
127 | clkdiv &= ~S3C2412_CLKDIVN_ARMDIVN; | ||
128 | clkdiv &= ~S3C2412_CLKDIVN_HDIVN_MASK; | ||
129 | clkdiv &= ~S3C2412_CLKDIVN_PDIVN; | ||
130 | |||
131 | if (cfg->divs.arm_divisor == 2) | ||
132 | clkdiv |= S3C2412_CLKDIVN_ARMDIVN; | ||
133 | |||
134 | clkdiv |= ((cfg->divs.h_divisor / cfg->divs.arm_divisor) - 1); | ||
135 | |||
136 | if (cfg->divs.p_divisor != cfg->divs.h_divisor) | ||
137 | clkdiv |= S3C2412_CLKDIVN_PDIVN; | ||
138 | |||
139 | s3c_freq_dbg("%s: div %08lx => %08lx\n", __func__, olddiv, clkdiv); | ||
140 | __raw_writel(clkdiv, S3C2410_CLKDIVN); | ||
141 | |||
142 | clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk); | ||
143 | } | ||
144 | |||
145 | static void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg) | ||
146 | { | ||
147 | struct s3c_cpufreq_board *board = cfg->board; | ||
148 | unsigned long refresh; | ||
149 | |||
150 | s3c_freq_dbg("%s: refresh %u ns, hclk %lu\n", __func__, | ||
151 | board->refresh, cfg->freq.hclk); | ||
152 | |||
153 | /* Reduce both the refresh time (in ns) and the frequency (in MHz) | ||
154 | * by 10 each to ensure that we do not overflow 32 bit numbers. This | ||
155 | * should work for HCLK up to 133MHz and refresh period up to 30usec. | ||
156 | */ | ||
157 | |||
158 | refresh = (board->refresh / 10); | ||
159 | refresh *= (cfg->freq.hclk / 100); | ||
160 | refresh /= (1 * 1000 * 1000); /* 10^6 */ | ||
161 | |||
162 | s3c_freq_dbg("%s: setting refresh 0x%08lx\n", __func__, refresh); | ||
163 | __raw_writel(refresh, S3C2412_REFRESH); | ||
164 | } | ||
165 | |||
166 | /* set the default cpu frequency information, based on an 200MHz part | ||
167 | * as we have no other way of detecting the speed rating in software. | ||
168 | */ | ||
169 | |||
170 | static struct s3c_cpufreq_info s3c2412_cpufreq_info = { | ||
171 | .max = { | ||
172 | .fclk = 200000000, | ||
173 | .hclk = 100000000, | ||
174 | .pclk = 50000000, | ||
175 | }, | ||
176 | |||
177 | .latency = 5000000, /* 5ms */ | ||
178 | |||
179 | .locktime_m = 150, | ||
180 | .locktime_u = 150, | ||
181 | .locktime_bits = 16, | ||
182 | |||
183 | .name = "s3c2412", | ||
184 | .set_refresh = s3c2412_cpufreq_setrefresh, | ||
185 | .set_divs = s3c2412_cpufreq_setdivs, | ||
186 | .calc_divs = s3c2412_cpufreq_calcdivs, | ||
187 | |||
188 | .calc_iotiming = s3c2412_iotiming_calc, | ||
189 | .set_iotiming = s3c2412_iotiming_set, | ||
190 | .get_iotiming = s3c2412_iotiming_get, | ||
191 | |||
192 | .resume_clocks = s3c2412_setup_clocks, | ||
193 | |||
194 | .debug_io_show = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs), | ||
195 | }; | ||
196 | |||
197 | static int s3c2412_cpufreq_add(struct sys_device *sysdev) | ||
198 | { | ||
199 | unsigned long fclk_rate; | ||
200 | |||
201 | hclk = clk_get(NULL, "hclk"); | ||
202 | if (IS_ERR(hclk)) { | ||
203 | printk(KERN_ERR "%s: cannot find hclk clock\n", __func__); | ||
204 | return -ENOENT; | ||
205 | } | ||
206 | |||
207 | fclk = clk_get(NULL, "fclk"); | ||
208 | if (IS_ERR(fclk)) { | ||
209 | printk(KERN_ERR "%s: cannot find fclk clock\n", __func__); | ||
210 | goto err_fclk; | ||
211 | } | ||
212 | |||
213 | fclk_rate = clk_get_rate(fclk); | ||
214 | if (fclk_rate > 200000000) { | ||
215 | printk(KERN_INFO | ||
216 | "%s: fclk %ld MHz, assuming 266MHz capable part\n", | ||
217 | __func__, fclk_rate / 1000000); | ||
218 | s3c2412_cpufreq_info.max.fclk = 266000000; | ||
219 | s3c2412_cpufreq_info.max.hclk = 133000000; | ||
220 | s3c2412_cpufreq_info.max.pclk = 66000000; | ||
221 | } | ||
222 | |||
223 | armclk = clk_get(NULL, "armclk"); | ||
224 | if (IS_ERR(armclk)) { | ||
225 | printk(KERN_ERR "%s: cannot find arm clock\n", __func__); | ||
226 | goto err_armclk; | ||
227 | } | ||
228 | |||
229 | xtal = clk_get(NULL, "xtal"); | ||
230 | if (IS_ERR(xtal)) { | ||
231 | printk(KERN_ERR "%s: cannot find xtal clock\n", __func__); | ||
232 | goto err_xtal; | ||
233 | } | ||
234 | |||
235 | return s3c_cpufreq_register(&s3c2412_cpufreq_info); | ||
236 | |||
237 | err_xtal: | ||
238 | clk_put(armclk); | ||
239 | err_armclk: | ||
240 | clk_put(fclk); | ||
241 | err_fclk: | ||
242 | clk_put(hclk); | ||
243 | |||
244 | return -ENOENT; | ||
245 | } | ||
246 | |||
247 | static struct sysdev_driver s3c2412_cpufreq_driver = { | ||
248 | .add = s3c2412_cpufreq_add, | ||
249 | }; | ||
250 | |||
251 | static int s3c2412_cpufreq_init(void) | ||
252 | { | ||
253 | return sysdev_driver_register(&s3c2412_sysclass, | ||
254 | &s3c2412_cpufreq_driver); | ||
255 | } | ||
256 | |||
257 | arch_initcall(s3c2412_cpufreq_init); | ||
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c index 5b5aba69ec3f..bef39f77729d 100644 --- a/arch/arm/mach-s3c2412/s3c2412.c +++ b/arch/arm/mach-s3c2412/s3c2412.c | |||
@@ -69,6 +69,18 @@ static struct map_desc s3c2412_iodesc[] __initdata = { | |||
69 | IODESC_ENT(CLKPWR), | 69 | IODESC_ENT(CLKPWR), |
70 | IODESC_ENT(TIMER), | 70 | IODESC_ENT(TIMER), |
71 | IODESC_ENT(WATCHDOG), | 71 | IODESC_ENT(WATCHDOG), |
72 | { | ||
73 | .virtual = (unsigned long)S3C2412_VA_SSMC, | ||
74 | .pfn = __phys_to_pfn(S3C2412_PA_SSMC), | ||
75 | .length = SZ_1M, | ||
76 | .type = MT_DEVICE, | ||
77 | }, | ||
78 | { | ||
79 | .virtual = (unsigned long)S3C2412_VA_EBI, | ||
80 | .pfn = __phys_to_pfn(S3C2412_PA_EBI), | ||
81 | .length = SZ_1M, | ||
82 | .type = MT_DEVICE, | ||
83 | }, | ||
72 | }; | 84 | }; |
73 | 85 | ||
74 | /* uart registration process */ | 86 | /* uart registration process */ |
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig index 8cfeaec37306..8ae1b288f7fa 100644 --- a/arch/arm/mach-s3c2440/Kconfig +++ b/arch/arm/mach-s3c2440/Kconfig | |||
@@ -33,6 +33,7 @@ config MACH_ANUBIS | |||
33 | select PM_SIMTEC if PM | 33 | select PM_SIMTEC if PM |
34 | select HAVE_PATA_PLATFORM | 34 | select HAVE_PATA_PLATFORM |
35 | select S3C24XX_GPIO_EXTRA64 | 35 | select S3C24XX_GPIO_EXTRA64 |
36 | select S3C2440_XTAL_12000000 | ||
36 | select S3C_DEV_USB_HOST | 37 | select S3C_DEV_USB_HOST |
37 | help | 38 | help |
38 | Say Y here if you are using the Simtec Electronics ANUBIS | 39 | Say Y here if you are using the Simtec Electronics ANUBIS |
@@ -44,6 +45,8 @@ config MACH_OSIRIS | |||
44 | select S3C24XX_DCLK | 45 | select S3C24XX_DCLK |
45 | select PM_SIMTEC if PM | 46 | select PM_SIMTEC if PM |
46 | select S3C24XX_GPIO_EXTRA128 | 47 | select S3C24XX_GPIO_EXTRA128 |
48 | select S3C2440_XTAL_12000000 | ||
49 | select S3C2410_IOTIMING if S3C2440_CPUFREQ | ||
47 | select S3C_DEV_USB_HOST | 50 | select S3C_DEV_USB_HOST |
48 | help | 51 | help |
49 | Say Y here if you are using the Simtec IM2440D20 module, also | 52 | Say Y here if you are using the Simtec IM2440D20 module, also |
@@ -52,6 +55,7 @@ config MACH_OSIRIS | |||
52 | config MACH_RX3715 | 55 | config MACH_RX3715 |
53 | bool "HP iPAQ rx3715" | 56 | bool "HP iPAQ rx3715" |
54 | select CPU_S3C2440 | 57 | select CPU_S3C2440 |
58 | select S3C2440_XTAL_16934400 | ||
55 | select PM_H1940 if PM | 59 | select PM_H1940 if PM |
56 | help | 60 | help |
57 | Say Y here if you are using the HP iPAQ rx3715. | 61 | Say Y here if you are using the HP iPAQ rx3715. |
@@ -59,6 +63,7 @@ config MACH_RX3715 | |||
59 | config ARCH_S3C2440 | 63 | config ARCH_S3C2440 |
60 | bool "SMDK2440" | 64 | bool "SMDK2440" |
61 | select CPU_S3C2440 | 65 | select CPU_S3C2440 |
66 | select S3C2440_XTAL_16934400 | ||
62 | select MACH_SMDK | 67 | select MACH_SMDK |
63 | select S3C_DEV_USB_HOST | 68 | select S3C_DEV_USB_HOST |
64 | help | 69 | help |
@@ -67,6 +72,7 @@ config ARCH_S3C2440 | |||
67 | config MACH_NEXCODER_2440 | 72 | config MACH_NEXCODER_2440 |
68 | bool "NexVision NEXCODER 2440 Light Board" | 73 | bool "NexVision NEXCODER 2440 Light Board" |
69 | select CPU_S3C2440 | 74 | select CPU_S3C2440 |
75 | select S3C2440_XTAL_12000000 | ||
70 | select S3C_DEV_USB_HOST | 76 | select S3C_DEV_USB_HOST |
71 | help | 77 | help |
72 | Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board | 78 | Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board |
@@ -75,6 +81,7 @@ config SMDK2440_CPU2440 | |||
75 | bool "SMDK2440 with S3C2440 CPU module" | 81 | bool "SMDK2440 with S3C2440 CPU module" |
76 | depends on ARCH_S3C2440 | 82 | depends on ARCH_S3C2440 |
77 | default y if ARCH_S3C2440 | 83 | default y if ARCH_S3C2440 |
84 | select S3C2440_XTAL_16934400 | ||
78 | select CPU_S3C2440 | 85 | select CPU_S3C2440 |
79 | 86 | ||
80 | config MACH_AT2440EVB | 87 | config MACH_AT2440EVB |
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c index cba064b49a64..2105a41281a4 100644 --- a/arch/arm/mach-s3c2440/mach-osiris.c +++ b/arch/arm/mach-s3c2440/mach-osiris.c | |||
@@ -34,6 +34,7 @@ | |||
34 | #include <asm/irq.h> | 34 | #include <asm/irq.h> |
35 | #include <asm/mach-types.h> | 35 | #include <asm/mach-types.h> |
36 | 36 | ||
37 | #include <plat/cpu-freq.h> | ||
37 | #include <plat/regs-serial.h> | 38 | #include <plat/regs-serial.h> |
38 | #include <mach/regs-gpio.h> | 39 | #include <mach/regs-gpio.h> |
39 | #include <mach/regs-mem.h> | 40 | #include <mach/regs-mem.h> |
@@ -351,6 +352,12 @@ static struct clk *osiris_clocks[] __initdata = { | |||
351 | &s3c24xx_uclk, | 352 | &s3c24xx_uclk, |
352 | }; | 353 | }; |
353 | 354 | ||
355 | static struct s3c_cpufreq_board __initdata osiris_cpufreq = { | ||
356 | .refresh = 7800, /* refresh period is 7.8usec */ | ||
357 | .auto_io = 1, | ||
358 | .need_io = 1, | ||
359 | }; | ||
360 | |||
354 | static void __init osiris_map_io(void) | 361 | static void __init osiris_map_io(void) |
355 | { | 362 | { |
356 | unsigned long flags; | 363 | unsigned long flags; |
@@ -402,6 +409,8 @@ static void __init osiris_init(void) | |||
402 | 409 | ||
403 | s3c_i2c0_set_platdata(NULL); | 410 | s3c_i2c0_set_platdata(NULL); |
404 | 411 | ||
412 | s3c_cpufreq_setboard(&osiris_cpufreq); | ||
413 | |||
405 | i2c_register_board_info(0, osiris_i2c_devs, | 414 | i2c_register_board_info(0, osiris_i2c_devs, |
406 | ARRAY_SIZE(osiris_i2c_devs)); | 415 | ARRAY_SIZE(osiris_i2c_devs)); |
407 | 416 | ||
diff --git a/arch/arm/mach-s3c24a0/include/mach/map.h b/arch/arm/mach-s3c24a0/include/mach/map.h index a01132717e34..79e4d93ea2b6 100644 --- a/arch/arm/mach-s3c24a0/include/mach/map.h +++ b/arch/arm/mach-s3c24a0/include/mach/map.h | |||
@@ -81,5 +81,6 @@ | |||
81 | 81 | ||
82 | #define S3C_PA_UART S3C24A0_PA_UART | 82 | #define S3C_PA_UART S3C24A0_PA_UART |
83 | #define S3C_PA_IIC S3C24A0_PA_IIC | 83 | #define S3C_PA_IIC S3C24A0_PA_IIC |
84 | #define S3C_PA_NAND S3C24XX_PA_NAND | ||
84 | 85 | ||
85 | #endif /* __ASM_ARCH_24A0_MAP_H */ | 86 | #endif /* __ASM_ARCH_24A0_MAP_H */ |
diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h index 5057d9948d35..fc8b223bad4f 100644 --- a/arch/arm/mach-s3c6400/include/mach/map.h +++ b/arch/arm/mach-s3c6400/include/mach/map.h | |||
@@ -38,18 +38,21 @@ | |||
38 | #define S3C_VA_UART2 S3C_VA_UARTx(2) | 38 | #define S3C_VA_UART2 S3C_VA_UARTx(2) |
39 | #define S3C_VA_UART3 S3C_VA_UARTx(3) | 39 | #define S3C_VA_UART3 S3C_VA_UARTx(3) |
40 | 40 | ||
41 | #define S3C64XX_PA_NAND (0x70200000) | ||
41 | #define S3C64XX_PA_FB (0x77100000) | 42 | #define S3C64XX_PA_FB (0x77100000) |
42 | #define S3C64XX_PA_USB_HSOTG (0x7C000000) | 43 | #define S3C64XX_PA_USB_HSOTG (0x7C000000) |
43 | #define S3C64XX_PA_WATCHDOG (0x7E004000) | 44 | #define S3C64XX_PA_WATCHDOG (0x7E004000) |
44 | #define S3C64XX_PA_SYSCON (0x7E00F000) | 45 | #define S3C64XX_PA_SYSCON (0x7E00F000) |
46 | #define S3C64XX_PA_AC97 (0x7F001000) | ||
45 | #define S3C64XX_PA_IIS0 (0x7F002000) | 47 | #define S3C64XX_PA_IIS0 (0x7F002000) |
46 | #define S3C64XX_PA_IIS1 (0x7F003000) | 48 | #define S3C64XX_PA_IIS1 (0x7F003000) |
47 | #define S3C64XX_PA_TIMER (0x7F006000) | 49 | #define S3C64XX_PA_TIMER (0x7F006000) |
48 | #define S3C64XX_PA_IIC0 (0x7F004000) | 50 | #define S3C64XX_PA_IIC0 (0x7F004000) |
51 | #define S3C64XX_PA_IISV4 (0x7F00D000) | ||
49 | #define S3C64XX_PA_IIC1 (0x7F00F000) | 52 | #define S3C64XX_PA_IIC1 (0x7F00F000) |
50 | 53 | ||
51 | #define S3C64XX_PA_GPIO (0x7F008000) | 54 | #define S3C64XX_PA_GPIO (0x7F008000) |
52 | #define S3C64XX_VA_GPIO S3C_ADDR(0x00500000) | 55 | #define S3C64XX_VA_GPIO S3C_ADDR_CPU(0x00000000) |
53 | #define S3C64XX_SZ_GPIO SZ_4K | 56 | #define S3C64XX_SZ_GPIO SZ_4K |
54 | 57 | ||
55 | #define S3C64XX_PA_SDRAM (0x50000000) | 58 | #define S3C64XX_PA_SDRAM (0x50000000) |
@@ -57,7 +60,7 @@ | |||
57 | #define S3C64XX_PA_VIC1 (0x71300000) | 60 | #define S3C64XX_PA_VIC1 (0x71300000) |
58 | 61 | ||
59 | #define S3C64XX_PA_MODEM (0x74108000) | 62 | #define S3C64XX_PA_MODEM (0x74108000) |
60 | #define S3C64XX_VA_MODEM S3C_ADDR(0x00600000) | 63 | #define S3C64XX_VA_MODEM S3C_ADDR_CPU(0x00100000) |
61 | 64 | ||
62 | #define S3C64XX_PA_USBHOST (0x74300000) | 65 | #define S3C64XX_PA_USBHOST (0x74300000) |
63 | 66 | ||
@@ -72,6 +75,7 @@ | |||
72 | #define S3C_PA_HSMMC2 S3C64XX_PA_HSMMC2 | 75 | #define S3C_PA_HSMMC2 S3C64XX_PA_HSMMC2 |
73 | #define S3C_PA_IIC S3C64XX_PA_IIC0 | 76 | #define S3C_PA_IIC S3C64XX_PA_IIC0 |
74 | #define S3C_PA_IIC1 S3C64XX_PA_IIC1 | 77 | #define S3C_PA_IIC1 S3C64XX_PA_IIC1 |
78 | #define S3C_PA_NAND S3C64XX_PA_NAND | ||
75 | #define S3C_PA_FB S3C64XX_PA_FB | 79 | #define S3C_PA_FB S3C64XX_PA_FB |
76 | #define S3C_PA_USBHOST S3C64XX_PA_USBHOST | 80 | #define S3C_PA_USBHOST S3C64XX_PA_USBHOST |
77 | #define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG | 81 | #define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG |
diff --git a/arch/arm/mach-s3c6400/s3c6400.c b/arch/arm/mach-s3c6400/s3c6400.c index 1ece887d90bb..b42bdd0f2138 100644 --- a/arch/arm/mach-s3c6400/s3c6400.c +++ b/arch/arm/mach-s3c6400/s3c6400.c | |||
@@ -48,6 +48,8 @@ void __init s3c6400_map_io(void) | |||
48 | 48 | ||
49 | /* the i2c devices are directly compatible with s3c2440 */ | 49 | /* the i2c devices are directly compatible with s3c2440 */ |
50 | s3c_i2c0_setname("s3c2440-i2c"); | 50 | s3c_i2c0_setname("s3c2440-i2c"); |
51 | |||
52 | s3c_device_nand.name = "s3c6400-nand"; | ||
51 | } | 53 | } |
52 | 54 | ||
53 | void __init s3c6400_init_clocks(int xtal) | 55 | void __init s3c6400_init_clocks(int xtal) |
diff --git a/arch/arm/mach-s3c6410/Kconfig b/arch/arm/mach-s3c6410/Kconfig index e63aac7f4e5a..f9d0f09f9761 100644 --- a/arch/arm/mach-s3c6410/Kconfig +++ b/arch/arm/mach-s3c6410/Kconfig | |||
@@ -97,3 +97,13 @@ config MACH_NCP | |||
97 | select S3C64XX_SETUP_I2C1 | 97 | select S3C64XX_SETUP_I2C1 |
98 | help | 98 | help |
99 | Machine support for the Samsung NCP | 99 | Machine support for the Samsung NCP |
100 | |||
101 | config MACH_HMT | ||
102 | bool "Airgoo HMT" | ||
103 | select CPU_S3C6410 | ||
104 | select S3C_DEV_FB | ||
105 | select S3C_DEV_USB_HOST | ||
106 | select S3C64XX_SETUP_FB_24BPP | ||
107 | select HAVE_PWM | ||
108 | help | ||
109 | Machine support for the Airgoo HMT | ||
diff --git a/arch/arm/mach-s3c6410/Makefile b/arch/arm/mach-s3c6410/Makefile index 6f9deac88612..3e48c3dbf973 100644 --- a/arch/arm/mach-s3c6410/Makefile +++ b/arch/arm/mach-s3c6410/Makefile | |||
@@ -23,5 +23,4 @@ obj-$(CONFIG_S3C6410_SETUP_SDHCI) += setup-sdhci.o | |||
23 | obj-$(CONFIG_MACH_ANW6410) += mach-anw6410.o | 23 | obj-$(CONFIG_MACH_ANW6410) += mach-anw6410.o |
24 | obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o | 24 | obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o |
25 | obj-$(CONFIG_MACH_NCP) += mach-ncp.o | 25 | obj-$(CONFIG_MACH_NCP) += mach-ncp.o |
26 | 26 | obj-$(CONFIG_MACH_HMT) += mach-hmt.o | |
27 | |||
diff --git a/arch/arm/mach-s3c6410/cpu.c b/arch/arm/mach-s3c6410/cpu.c index ade904de8895..9b67c663d9d8 100644 --- a/arch/arm/mach-s3c6410/cpu.c +++ b/arch/arm/mach-s3c6410/cpu.c | |||
@@ -62,6 +62,8 @@ void __init s3c6410_map_io(void) | |||
62 | /* the i2c devices are directly compatible with s3c2440 */ | 62 | /* the i2c devices are directly compatible with s3c2440 */ |
63 | s3c_i2c0_setname("s3c2440-i2c"); | 63 | s3c_i2c0_setname("s3c2440-i2c"); |
64 | s3c_i2c1_setname("s3c2440-i2c"); | 64 | s3c_i2c1_setname("s3c2440-i2c"); |
65 | |||
66 | s3c_device_nand.name = "s3c6400-nand"; | ||
65 | } | 67 | } |
66 | 68 | ||
67 | void __init s3c6410_init_clocks(int xtal) | 69 | void __init s3c6410_init_clocks(int xtal) |
diff --git a/arch/arm/mach-s3c6410/mach-hmt.c b/arch/arm/mach-s3c6410/mach-hmt.c new file mode 100644 index 000000000000..c5741056193f --- /dev/null +++ b/arch/arm/mach-s3c6410/mach-hmt.c | |||
@@ -0,0 +1,276 @@ | |||
1 | /* mach-hmt.c - Platform code for Airgoo HMT | ||
2 | * | ||
3 | * Copyright 2009 Peter Korsgaard <jacmet@sunsite.dk> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License version 2 as | ||
7 | * published by the Free Software Foundation. | ||
8 | * | ||
9 | */ | ||
10 | |||
11 | #include <linux/kernel.h> | ||
12 | #include <linux/init.h> | ||
13 | #include <linux/serial_core.h> | ||
14 | #include <linux/platform_device.h> | ||
15 | #include <linux/io.h> | ||
16 | #include <linux/i2c.h> | ||
17 | #include <linux/fb.h> | ||
18 | #include <linux/gpio.h> | ||
19 | #include <linux/delay.h> | ||
20 | #include <linux/leds.h> | ||
21 | #include <linux/pwm_backlight.h> | ||
22 | #include <linux/mtd/mtd.h> | ||
23 | #include <linux/mtd/partitions.h> | ||
24 | |||
25 | #include <asm/mach/arch.h> | ||
26 | #include <asm/mach/map.h> | ||
27 | #include <asm/mach/irq.h> | ||
28 | |||
29 | #include <mach/hardware.h> | ||
30 | #include <mach/regs-fb.h> | ||
31 | #include <mach/map.h> | ||
32 | |||
33 | #include <asm/irq.h> | ||
34 | #include <asm/mach-types.h> | ||
35 | |||
36 | #include <plat/regs-serial.h> | ||
37 | #include <plat/iic.h> | ||
38 | #include <plat/fb.h> | ||
39 | #include <plat/nand.h> | ||
40 | |||
41 | #include <plat/s3c6410.h> | ||
42 | #include <plat/clock.h> | ||
43 | #include <plat/devs.h> | ||
44 | #include <plat/cpu.h> | ||
45 | |||
46 | #define UCON S3C2410_UCON_DEFAULT | ||
47 | #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE) | ||
48 | #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) | ||
49 | |||
50 | static struct s3c2410_uartcfg hmt_uartcfgs[] __initdata = { | ||
51 | [0] = { | ||
52 | .hwport = 0, | ||
53 | .flags = 0, | ||
54 | .ucon = UCON, | ||
55 | .ulcon = ULCON, | ||
56 | .ufcon = UFCON, | ||
57 | }, | ||
58 | [1] = { | ||
59 | .hwport = 1, | ||
60 | .flags = 0, | ||
61 | .ucon = UCON, | ||
62 | .ulcon = ULCON, | ||
63 | .ufcon = UFCON, | ||
64 | }, | ||
65 | [2] = { | ||
66 | .hwport = 2, | ||
67 | .flags = 0, | ||
68 | .ucon = UCON, | ||
69 | .ulcon = ULCON, | ||
70 | .ufcon = UFCON, | ||
71 | }, | ||
72 | }; | ||
73 | |||
74 | static int hmt_bl_init(struct device *dev) | ||
75 | { | ||
76 | int ret; | ||
77 | |||
78 | ret = gpio_request(S3C64XX_GPB(4), "lcd backlight enable"); | ||
79 | if (!ret) | ||
80 | ret = gpio_direction_output(S3C64XX_GPB(4), 0); | ||
81 | |||
82 | return ret; | ||
83 | } | ||
84 | |||
85 | static int hmt_bl_notify(int brightness) | ||
86 | { | ||
87 | /* | ||
88 | * translate from CIELUV/CIELAB L*->brightness, E.G. from | ||
89 | * perceived luminance to light output. Assumes range 0..25600 | ||
90 | */ | ||
91 | if (brightness < 0x800) { | ||
92 | /* Y = Yn * L / 903.3 */ | ||
93 | brightness = (100*256 * brightness + 231245/2) / 231245; | ||
94 | } else { | ||
95 | /* Y = Yn * ((L + 16) / 116 )^3 */ | ||
96 | int t = (brightness*4 + 16*1024 + 58)/116; | ||
97 | brightness = 25 * ((t * t * t + 0x100000/2) / 0x100000); | ||
98 | } | ||
99 | |||
100 | gpio_set_value(S3C64XX_GPB(4), brightness); | ||
101 | |||
102 | return brightness; | ||
103 | } | ||
104 | |||
105 | static void hmt_bl_exit(struct device *dev) | ||
106 | { | ||
107 | gpio_free(S3C64XX_GPB(4)); | ||
108 | } | ||
109 | |||
110 | static struct platform_pwm_backlight_data hmt_backlight_data = { | ||
111 | .pwm_id = 1, | ||
112 | .max_brightness = 100 * 256, | ||
113 | .dft_brightness = 40 * 256, | ||
114 | .pwm_period_ns = 1000000000 / (100 * 256 * 20), | ||
115 | .init = hmt_bl_init, | ||
116 | .notify = hmt_bl_notify, | ||
117 | .exit = hmt_bl_exit, | ||
118 | |||
119 | }; | ||
120 | |||
121 | static struct platform_device hmt_backlight_device = { | ||
122 | .name = "pwm-backlight", | ||
123 | .dev = { | ||
124 | .parent = &s3c_device_timer[1].dev, | ||
125 | .platform_data = &hmt_backlight_data, | ||
126 | }, | ||
127 | }; | ||
128 | |||
129 | static struct s3c_fb_pd_win hmt_fb_win0 = { | ||
130 | .win_mode = { | ||
131 | .pixclock = 41094, | ||
132 | .left_margin = 8, | ||
133 | .right_margin = 13, | ||
134 | .upper_margin = 7, | ||
135 | .lower_margin = 5, | ||
136 | .hsync_len = 3, | ||
137 | .vsync_len = 1, | ||
138 | .xres = 800, | ||
139 | .yres = 480, | ||
140 | }, | ||
141 | .max_bpp = 32, | ||
142 | .default_bpp = 16, | ||
143 | }; | ||
144 | |||
145 | /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */ | ||
146 | static struct s3c_fb_platdata hmt_lcd_pdata __initdata = { | ||
147 | .setup_gpio = s3c64xx_fb_gpio_setup_24bpp, | ||
148 | .win[0] = &hmt_fb_win0, | ||
149 | .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, | ||
150 | .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, | ||
151 | }; | ||
152 | |||
153 | static struct mtd_partition hmt_nand_part[] = { | ||
154 | [0] = { | ||
155 | .name = "uboot", | ||
156 | .size = SZ_512K, | ||
157 | .offset = 0, | ||
158 | }, | ||
159 | [1] = { | ||
160 | .name = "uboot-env1", | ||
161 | .size = SZ_256K, | ||
162 | .offset = SZ_512K, | ||
163 | }, | ||
164 | [2] = { | ||
165 | .name = "uboot-env2", | ||
166 | .size = SZ_256K, | ||
167 | .offset = SZ_512K + SZ_256K, | ||
168 | }, | ||
169 | [3] = { | ||
170 | .name = "kernel", | ||
171 | .size = SZ_2M, | ||
172 | .offset = SZ_1M, | ||
173 | }, | ||
174 | [4] = { | ||
175 | .name = "rootfs", | ||
176 | .size = MTDPART_SIZ_FULL, | ||
177 | .offset = SZ_1M + SZ_2M, | ||
178 | }, | ||
179 | }; | ||
180 | |||
181 | static struct s3c2410_nand_set hmt_nand_sets[] = { | ||
182 | [0] = { | ||
183 | .name = "nand", | ||
184 | .nr_chips = 1, | ||
185 | .nr_partitions = ARRAY_SIZE(hmt_nand_part), | ||
186 | .partitions = hmt_nand_part, | ||
187 | }, | ||
188 | }; | ||
189 | |||
190 | static struct s3c2410_platform_nand hmt_nand_info = { | ||
191 | .tacls = 25, | ||
192 | .twrph0 = 55, | ||
193 | .twrph1 = 40, | ||
194 | .nr_sets = ARRAY_SIZE(hmt_nand_sets), | ||
195 | .sets = hmt_nand_sets, | ||
196 | }; | ||
197 | |||
198 | static struct gpio_led hmt_leds[] = { | ||
199 | { /* left function keys */ | ||
200 | .name = "left:blue", | ||
201 | .gpio = S3C64XX_GPO(12), | ||
202 | .default_trigger = "default-on", | ||
203 | }, | ||
204 | { /* right function keys - red */ | ||
205 | .name = "right:red", | ||
206 | .gpio = S3C64XX_GPO(13), | ||
207 | }, | ||
208 | { /* right function keys - green */ | ||
209 | .name = "right:green", | ||
210 | .gpio = S3C64XX_GPO(14), | ||
211 | }, | ||
212 | { /* right function keys - blue */ | ||
213 | .name = "right:blue", | ||
214 | .gpio = S3C64XX_GPO(15), | ||
215 | .default_trigger = "default-on", | ||
216 | }, | ||
217 | }; | ||
218 | |||
219 | static struct gpio_led_platform_data hmt_led_data = { | ||
220 | .num_leds = ARRAY_SIZE(hmt_leds), | ||
221 | .leds = hmt_leds, | ||
222 | }; | ||
223 | |||
224 | static struct platform_device hmt_leds_device = { | ||
225 | .name = "leds-gpio", | ||
226 | .id = -1, | ||
227 | .dev.platform_data = &hmt_led_data, | ||
228 | }; | ||
229 | |||
230 | static struct map_desc hmt_iodesc[] = {}; | ||
231 | |||
232 | static struct platform_device *hmt_devices[] __initdata = { | ||
233 | &s3c_device_i2c0, | ||
234 | &s3c_device_nand, | ||
235 | &s3c_device_fb, | ||
236 | &s3c_device_usb, | ||
237 | &s3c_device_timer[1], | ||
238 | &hmt_backlight_device, | ||
239 | &hmt_leds_device, | ||
240 | }; | ||
241 | |||
242 | static void __init hmt_map_io(void) | ||
243 | { | ||
244 | s3c64xx_init_io(hmt_iodesc, ARRAY_SIZE(hmt_iodesc)); | ||
245 | s3c24xx_init_clocks(12000000); | ||
246 | s3c24xx_init_uarts(hmt_uartcfgs, ARRAY_SIZE(hmt_uartcfgs)); | ||
247 | } | ||
248 | |||
249 | static void __init hmt_machine_init(void) | ||
250 | { | ||
251 | s3c_i2c0_set_platdata(NULL); | ||
252 | s3c_fb_set_platdata(&hmt_lcd_pdata); | ||
253 | s3c_device_nand.dev.platform_data = &hmt_nand_info; | ||
254 | |||
255 | gpio_request(S3C64XX_GPC(7), "usb power"); | ||
256 | gpio_direction_output(S3C64XX_GPC(7), 0); | ||
257 | gpio_request(S3C64XX_GPM(0), "usb power"); | ||
258 | gpio_direction_output(S3C64XX_GPM(0), 1); | ||
259 | gpio_request(S3C64XX_GPK(7), "usb power"); | ||
260 | gpio_direction_output(S3C64XX_GPK(7), 1); | ||
261 | gpio_request(S3C64XX_GPF(13), "usb power"); | ||
262 | gpio_direction_output(S3C64XX_GPF(13), 1); | ||
263 | |||
264 | platform_add_devices(hmt_devices, ARRAY_SIZE(hmt_devices)); | ||
265 | } | ||
266 | |||
267 | MACHINE_START(HMT, "Airgoo-HMT") | ||
268 | /* Maintainer: Peter Korsgaard <jacmet@sunsite.dk> */ | ||
269 | .phys_io = S3C_PA_UART & 0xfff00000, | ||
270 | .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, | ||
271 | .boot_params = S3C64XX_PA_SDRAM + 0x100, | ||
272 | .init_irq = s3c6410_init_irq, | ||
273 | .map_io = hmt_map_io, | ||
274 | .init_machine = hmt_machine_init, | ||
275 | .timer = &s3c24xx_timer, | ||
276 | MACHINE_END | ||
diff --git a/arch/arm/mach-s3c6410/mach-ncp.c b/arch/arm/mach-s3c6410/mach-ncp.c index 6030636f8548..55e9bbfaf68b 100644 --- a/arch/arm/mach-s3c6410/mach-ncp.c +++ b/arch/arm/mach-s3c6410/mach-ncp.c | |||
@@ -79,7 +79,7 @@ static struct platform_device *ncp_devices[] __initdata = { | |||
79 | &s3c_device_i2c0, | 79 | &s3c_device_i2c0, |
80 | }; | 80 | }; |
81 | 81 | ||
82 | struct map_desc ncp_iodesc[] = {}; | 82 | static struct map_desc ncp_iodesc[] __initdata = {}; |
83 | 83 | ||
84 | static void __init ncp_map_io(void) | 84 | static void __init ncp_map_io(void) |
85 | { | 85 | { |
diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c index bc9a7dea567f..ea51dbe76e3e 100644 --- a/arch/arm/mach-s3c6410/mach-smdk6410.c +++ b/arch/arm/mach-s3c6410/mach-smdk6410.c | |||
@@ -65,16 +65,30 @@ static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = { | |||
65 | [0] = { | 65 | [0] = { |
66 | .hwport = 0, | 66 | .hwport = 0, |
67 | .flags = 0, | 67 | .flags = 0, |
68 | .ucon = 0x3c5, | 68 | .ucon = UCON, |
69 | .ulcon = 0x03, | 69 | .ulcon = ULCON, |
70 | .ufcon = 0x51, | 70 | .ufcon = UFCON, |
71 | }, | 71 | }, |
72 | [1] = { | 72 | [1] = { |
73 | .hwport = 1, | 73 | .hwport = 1, |
74 | .flags = 0, | 74 | .flags = 0, |
75 | .ucon = 0x3c5, | 75 | .ucon = UCON, |
76 | .ulcon = 0x03, | 76 | .ulcon = ULCON, |
77 | .ufcon = 0x51, | 77 | .ufcon = UFCON, |
78 | }, | ||
79 | [2] = { | ||
80 | .hwport = 2, | ||
81 | .flags = 0, | ||
82 | .ucon = UCON, | ||
83 | .ulcon = ULCON, | ||
84 | .ufcon = UFCON, | ||
85 | }, | ||
86 | [3] = { | ||
87 | .hwport = 3, | ||
88 | .flags = 0, | ||
89 | .ucon = UCON, | ||
90 | .ulcon = ULCON, | ||
91 | .ufcon = UFCON, | ||
78 | }, | 92 | }, |
79 | }; | 93 | }; |
80 | 94 | ||
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig new file mode 100644 index 000000000000..b1a4ba504416 --- /dev/null +++ b/arch/arm/mach-s5pc100/Kconfig | |||
@@ -0,0 +1,22 @@ | |||
1 | # arch/arm/mach-s5pc100/Kconfig | ||
2 | # | ||
3 | # Copyright 2009 Samsung Electronics Co. | ||
4 | # Byungho Min <bhmin@samsung.com> | ||
5 | # | ||
6 | # Licensed under GPLv2 | ||
7 | |||
8 | # Configuration options for the S5PC100 CPU | ||
9 | |||
10 | config CPU_S5PC100 | ||
11 | bool | ||
12 | select CPU_S5PC100_INIT | ||
13 | select CPU_S5PC100_CLOCK | ||
14 | help | ||
15 | Enable S5PC100 CPU support | ||
16 | |||
17 | config MACH_SMDKC100 | ||
18 | bool "SMDKC100" | ||
19 | select CPU_S5PC100 | ||
20 | select S5PC1XX_SETUP_I2C1 | ||
21 | help | ||
22 | Machine support for the Samsung SMDKC100 | ||
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile new file mode 100644 index 000000000000..afc89b381d7a --- /dev/null +++ b/arch/arm/mach-s5pc100/Makefile | |||
@@ -0,0 +1,17 @@ | |||
1 | # arch/arm/mach-s5pc100/Makefile | ||
2 | # | ||
3 | # Copyright 2009 Samsung Electronics Co. | ||
4 | # | ||
5 | # Licensed under GPLv2 | ||
6 | |||
7 | obj-y := | ||
8 | obj-m := | ||
9 | obj-n := | ||
10 | obj- := | ||
11 | |||
12 | # Core support for S5PC100 system | ||
13 | |||
14 | obj-$(CONFIG_CPU_S5PC100) += cpu.o | ||
15 | |||
16 | # machine support | ||
17 | obj-$(CONFIG_MACH_SMDKC100) += mach-smdkc100.o | ||
diff --git a/arch/arm/mach-s5pc100/Makefile.boot b/arch/arm/mach-s5pc100/Makefile.boot new file mode 100644 index 000000000000..ff90aa13bd67 --- /dev/null +++ b/arch/arm/mach-s5pc100/Makefile.boot | |||
@@ -0,0 +1,2 @@ | |||
1 | zreladdr-y := 0x20008000 | ||
2 | params_phys-y := 0x20000100 | ||
diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c new file mode 100644 index 000000000000..0e718890da32 --- /dev/null +++ b/arch/arm/mach-s5pc100/cpu.c | |||
@@ -0,0 +1,97 @@ | |||
1 | /* linux/arch/arm/mach-s5pc100/cpu.c | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * Based on mach-s3c6410/cpu.c | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/kernel.h> | ||
14 | #include <linux/types.h> | ||
15 | #include <linux/interrupt.h> | ||
16 | #include <linux/list.h> | ||
17 | #include <linux/timer.h> | ||
18 | #include <linux/init.h> | ||
19 | #include <linux/clk.h> | ||
20 | #include <linux/io.h> | ||
21 | #include <linux/sysdev.h> | ||
22 | #include <linux/serial_core.h> | ||
23 | #include <linux/platform_device.h> | ||
24 | |||
25 | #include <asm/mach/arch.h> | ||
26 | #include <asm/mach/map.h> | ||
27 | #include <asm/mach/irq.h> | ||
28 | |||
29 | #include <mach/hardware.h> | ||
30 | #include <mach/map.h> | ||
31 | #include <asm/irq.h> | ||
32 | |||
33 | #include <plat/cpu-freq.h> | ||
34 | #include <plat/regs-serial.h> | ||
35 | |||
36 | #include <plat/cpu.h> | ||
37 | #include <plat/devs.h> | ||
38 | #include <plat/clock.h> | ||
39 | #include <plat/sdhci.h> | ||
40 | #include <plat/iic-core.h> | ||
41 | #include <plat/s5pc100.h> | ||
42 | |||
43 | /* Initial IO mappings */ | ||
44 | |||
45 | static struct map_desc s5pc100_iodesc[] __initdata = { | ||
46 | }; | ||
47 | |||
48 | /* s5pc100_map_io | ||
49 | * | ||
50 | * register the standard cpu IO areas | ||
51 | */ | ||
52 | |||
53 | void __init s5pc100_map_io(void) | ||
54 | { | ||
55 | iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc)); | ||
56 | |||
57 | /* initialise device information early */ | ||
58 | } | ||
59 | |||
60 | void __init s5pc100_init_clocks(int xtal) | ||
61 | { | ||
62 | printk(KERN_DEBUG "%s: initialising clocks\n", __func__); | ||
63 | s3c24xx_register_baseclocks(xtal); | ||
64 | s5pc1xx_register_clocks(); | ||
65 | s5pc100_register_clocks(); | ||
66 | s5pc100_setup_clocks(); | ||
67 | } | ||
68 | |||
69 | void __init s5pc100_init_irq(void) | ||
70 | { | ||
71 | u32 vic_valid[] = {~0, ~0, ~0}; | ||
72 | |||
73 | /* VIC0, VIC1, and VIC2 are fully populated. */ | ||
74 | s5pc1xx_init_irq(vic_valid, ARRAY_SIZE(vic_valid)); | ||
75 | } | ||
76 | |||
77 | struct sysdev_class s5pc100_sysclass = { | ||
78 | .name = "s5pc100-core", | ||
79 | }; | ||
80 | |||
81 | static struct sys_device s5pc100_sysdev = { | ||
82 | .cls = &s5pc100_sysclass, | ||
83 | }; | ||
84 | |||
85 | static int __init s5pc100_core_init(void) | ||
86 | { | ||
87 | return sysdev_class_register(&s5pc100_sysclass); | ||
88 | } | ||
89 | |||
90 | core_initcall(s5pc100_core_init); | ||
91 | |||
92 | int __init s5pc100_init(void) | ||
93 | { | ||
94 | printk(KERN_DEBUG "S5PC100: Initialising architecture\n"); | ||
95 | |||
96 | return sysdev_register(&s5pc100_sysdev); | ||
97 | } | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/debug-macro.S b/arch/arm/mach-s5pc100/include/mach/debug-macro.S new file mode 100644 index 000000000000..9d142ccf654b --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/debug-macro.S | |||
@@ -0,0 +1,38 @@ | |||
1 | /* arch/arm/mach-s5pc100/include/mach/debug-macro.S | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * | ||
7 | * Based on mach-s3c6400/include/mach/debug-macro.S | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | /* pull in the relevant register and map files. */ | ||
15 | |||
16 | #include <mach/map.h> | ||
17 | #include <plat/regs-serial.h> | ||
18 | |||
19 | /* note, for the boot process to work we have to keep the UART | ||
20 | * virtual address aligned to an 1MiB boundary for the L1 | ||
21 | * mapping the head code makes. We keep the UART virtual address | ||
22 | * aligned and add in the offset when we load the value here. | ||
23 | */ | ||
24 | |||
25 | .macro addruart, rx | ||
26 | mrc p15, 0, \rx, c1, c0 | ||
27 | tst \rx, #1 | ||
28 | ldreq \rx, = S3C_PA_UART | ||
29 | ldrne \rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff) | ||
30 | add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART) | ||
31 | .endm | ||
32 | |||
33 | /* include the reset of the code which will do the work, we're only | ||
34 | * compiling for a single cpu processor type so the default of s3c2440 | ||
35 | * will be fine with us. | ||
36 | */ | ||
37 | |||
38 | #include <plat/debug-macro.S> | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/entry-macro.S b/arch/arm/mach-s5pc100/include/mach/entry-macro.S new file mode 100644 index 000000000000..67131939e626 --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/entry-macro.S | |||
@@ -0,0 +1,50 @@ | |||
1 | /* arch/arm/mach-s5pc100/include/mach/entry-macro.S | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * Based on mach-s3c6400/include/mach/entry-macro.S | ||
7 | * | ||
8 | * Low-level IRQ helper macros for the Samsung S5PC1XX series | ||
9 | * | ||
10 | * This file is licensed under the terms of the GNU General Public | ||
11 | * License version 2. This program is licensed "as is" without any | ||
12 | * warranty of any kind, whether express or implied. | ||
13 | */ | ||
14 | |||
15 | #include <asm/hardware/vic.h> | ||
16 | #include <mach/map.h> | ||
17 | #include <plat/irqs.h> | ||
18 | |||
19 | .macro disable_fiq | ||
20 | .endm | ||
21 | |||
22 | .macro get_irqnr_preamble, base, tmp | ||
23 | ldr \base, =S3C_VA_VIC0 | ||
24 | .endm | ||
25 | |||
26 | .macro arch_ret_to_user, tmp1, tmp2 | ||
27 | .endm | ||
28 | |||
29 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
30 | |||
31 | @ check the vic0 | ||
32 | mov \irqnr, # S3C_IRQ_OFFSET + 31 | ||
33 | ldr \irqstat, [ \base, # VIC_IRQ_STATUS ] | ||
34 | teq \irqstat, #0 | ||
35 | |||
36 | @ otherwise try vic1 | ||
37 | addeq \tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0) | ||
38 | addeq \irqnr, \irqnr, #32 | ||
39 | ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] | ||
40 | teqeq \irqstat, #0 | ||
41 | |||
42 | @ otherwise try vic2 | ||
43 | addeq \tmp, \base, #(S3C_VA_VIC2 - S3C_VA_VIC0) | ||
44 | addeq \irqnr, \irqnr, #32 | ||
45 | ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] | ||
46 | teqeq \irqstat, #0 | ||
47 | |||
48 | clzne \irqstat, \irqstat | ||
49 | subne \irqnr, \irqnr, \irqstat | ||
50 | .endm | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/gpio-core.h b/arch/arm/mach-s5pc100/include/mach/gpio-core.h new file mode 100644 index 000000000000..ad28d8ec8a78 --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/gpio-core.h | |||
@@ -0,0 +1,21 @@ | |||
1 | /* arch/arm/mach-s5pc100/include/mach/gpio-core.h | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * S5PC100 - GPIO core support | ||
7 | * | ||
8 | * Based on mach-s3c6400/include/mach/gpio-core.h | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #ifndef __ASM_ARCH_GPIO_CORE_H | ||
16 | #define __ASM_ARCH_GPIO_CORE_H __FILE__ | ||
17 | |||
18 | /* currently we just include the platform support */ | ||
19 | #include <plat/gpio-core.h> | ||
20 | |||
21 | #endif /* __ASM_ARCH_GPIO_CORE_H */ | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h new file mode 100644 index 000000000000..c74fc93d7d15 --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/gpio.h | |||
@@ -0,0 +1,146 @@ | |||
1 | /* arch/arm/mach-s5pc100/include/mach/gpio.h | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * S5PC100 - GPIO lib support | ||
7 | * | ||
8 | * Base on mach-s3c6400/include/mach/gpio.h | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #define gpio_get_value __gpio_get_value | ||
16 | #define gpio_set_value __gpio_set_value | ||
17 | #define gpio_cansleep __gpio_cansleep | ||
18 | #define gpio_to_irq __gpio_to_irq | ||
19 | |||
20 | /* GPIO bank sizes */ | ||
21 | #define S5PC1XX_GPIO_A0_NR (8) | ||
22 | #define S5PC1XX_GPIO_A1_NR (5) | ||
23 | #define S5PC1XX_GPIO_B_NR (8) | ||
24 | #define S5PC1XX_GPIO_C_NR (5) | ||
25 | #define S5PC1XX_GPIO_D_NR (7) | ||
26 | #define S5PC1XX_GPIO_E0_NR (8) | ||
27 | #define S5PC1XX_GPIO_E1_NR (6) | ||
28 | #define S5PC1XX_GPIO_F0_NR (8) | ||
29 | #define S5PC1XX_GPIO_F1_NR (8) | ||
30 | #define S5PC1XX_GPIO_F2_NR (8) | ||
31 | #define S5PC1XX_GPIO_F3_NR (4) | ||
32 | #define S5PC1XX_GPIO_G0_NR (8) | ||
33 | #define S5PC1XX_GPIO_G1_NR (3) | ||
34 | #define S5PC1XX_GPIO_G2_NR (7) | ||
35 | #define S5PC1XX_GPIO_G3_NR (7) | ||
36 | #define S5PC1XX_GPIO_H0_NR (8) | ||
37 | #define S5PC1XX_GPIO_H1_NR (8) | ||
38 | #define S5PC1XX_GPIO_H2_NR (8) | ||
39 | #define S5PC1XX_GPIO_H3_NR (8) | ||
40 | #define S5PC1XX_GPIO_I_NR (8) | ||
41 | #define S5PC1XX_GPIO_J0_NR (8) | ||
42 | #define S5PC1XX_GPIO_J1_NR (5) | ||
43 | #define S5PC1XX_GPIO_J2_NR (8) | ||
44 | #define S5PC1XX_GPIO_J3_NR (8) | ||
45 | #define S5PC1XX_GPIO_J4_NR (4) | ||
46 | #define S5PC1XX_GPIO_K0_NR (8) | ||
47 | #define S5PC1XX_GPIO_K1_NR (6) | ||
48 | #define S5PC1XX_GPIO_K2_NR (8) | ||
49 | #define S5PC1XX_GPIO_K3_NR (8) | ||
50 | #define S5PC1XX_GPIO_MP00_NR (8) | ||
51 | #define S5PC1XX_GPIO_MP01_NR (8) | ||
52 | #define S5PC1XX_GPIO_MP02_NR (8) | ||
53 | #define S5PC1XX_GPIO_MP03_NR (8) | ||
54 | #define S5PC1XX_GPIO_MP04_NR (5) | ||
55 | |||
56 | /* GPIO bank numbes */ | ||
57 | |||
58 | /* CONFIG_S3C_GPIO_SPACE allows the user to select extra | ||
59 | * space for debugging purposes so that any accidental | ||
60 | * change from one gpio bank to another can be caught. | ||
61 | */ | ||
62 | |||
63 | #define S5PC1XX_GPIO_NEXT(__gpio) \ | ||
64 | ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) | ||
65 | |||
66 | enum s3c_gpio_number { | ||
67 | S5PC1XX_GPIO_A0_START = 0, | ||
68 | S5PC1XX_GPIO_A1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A0), | ||
69 | S5PC1XX_GPIO_B_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A1), | ||
70 | S5PC1XX_GPIO_C_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_B), | ||
71 | S5PC1XX_GPIO_D_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_C), | ||
72 | S5PC1XX_GPIO_E0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_D), | ||
73 | S5PC1XX_GPIO_E1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_E0), | ||
74 | S5PC1XX_GPIO_F0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_E1), | ||
75 | S5PC1XX_GPIO_F1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F0), | ||
76 | S5PC1XX_GPIO_F2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F1), | ||
77 | S5PC1XX_GPIO_F3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F2), | ||
78 | S5PC1XX_GPIO_G0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F3), | ||
79 | S5PC1XX_GPIO_G1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G0), | ||
80 | S5PC1XX_GPIO_G2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G1), | ||
81 | S5PC1XX_GPIO_G3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G2), | ||
82 | S5PC1XX_GPIO_H0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G3), | ||
83 | S5PC1XX_GPIO_H1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H0), | ||
84 | S5PC1XX_GPIO_H2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H1), | ||
85 | S5PC1XX_GPIO_H3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H2), | ||
86 | S5PC1XX_GPIO_I_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H3), | ||
87 | S5PC1XX_GPIO_J0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_I), | ||
88 | S5PC1XX_GPIO_J1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J0), | ||
89 | S5PC1XX_GPIO_J2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J1), | ||
90 | S5PC1XX_GPIO_J3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J2), | ||
91 | S5PC1XX_GPIO_J4_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J3), | ||
92 | S5PC1XX_GPIO_K0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J4), | ||
93 | S5PC1XX_GPIO_K1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K0), | ||
94 | S5PC1XX_GPIO_K2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K1), | ||
95 | S5PC1XX_GPIO_K3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K2), | ||
96 | S5PC1XX_GPIO_MP00_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K3), | ||
97 | S5PC1XX_GPIO_MP01_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP00), | ||
98 | S5PC1XX_GPIO_MP02_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP01), | ||
99 | S5PC1XX_GPIO_MP03_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP02), | ||
100 | S5PC1XX_GPIO_MP04_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP03), | ||
101 | }; | ||
102 | |||
103 | /* S5PC1XX GPIO number definitions. */ | ||
104 | #define S5PC1XX_GPA0(_nr) (S5PC1XX_GPIO_A0_START + (_nr)) | ||
105 | #define S5PC1XX_GPA1(_nr) (S5PC1XX_GPIO_A1_START + (_nr)) | ||
106 | #define S5PC1XX_GPB(_nr) (S5PC1XX_GPIO_B_START + (_nr)) | ||
107 | #define S5PC1XX_GPC(_nr) (S5PC1XX_GPIO_C_START + (_nr)) | ||
108 | #define S5PC1XX_GPD(_nr) (S5PC1XX_GPIO_D_START + (_nr)) | ||
109 | #define S5PC1XX_GPE0(_nr) (S5PC1XX_GPIO_E0_START + (_nr)) | ||
110 | #define S5PC1XX_GPE1(_nr) (S5PC1XX_GPIO_E1_START + (_nr)) | ||
111 | #define S5PC1XX_GPF0(_nr) (S5PC1XX_GPIO_F0_START + (_nr)) | ||
112 | #define S5PC1XX_GPF1(_nr) (S5PC1XX_GPIO_F1_START + (_nr)) | ||
113 | #define S5PC1XX_GPF2(_nr) (S5PC1XX_GPIO_F2_START + (_nr)) | ||
114 | #define S5PC1XX_GPF3(_nr) (S5PC1XX_GPIO_F3_START + (_nr)) | ||
115 | #define S5PC1XX_GPG0(_nr) (S5PC1XX_GPIO_G0_START + (_nr)) | ||
116 | #define S5PC1XX_GPG1(_nr) (S5PC1XX_GPIO_G1_START + (_nr)) | ||
117 | #define S5PC1XX_GPG2(_nr) (S5PC1XX_GPIO_G2_START + (_nr)) | ||
118 | #define S5PC1XX_GPG3(_nr) (S5PC1XX_GPIO_G3_START + (_nr)) | ||
119 | #define S5PC1XX_GPH0(_nr) (S5PC1XX_GPIO_H0_START + (_nr)) | ||
120 | #define S5PC1XX_GPH1(_nr) (S5PC1XX_GPIO_H1_START + (_nr)) | ||
121 | #define S5PC1XX_GPH2(_nr) (S5PC1XX_GPIO_H2_START + (_nr)) | ||
122 | #define S5PC1XX_GPH3(_nr) (S5PC1XX_GPIO_H3_START + (_nr)) | ||
123 | #define S5PC1XX_GPI(_nr) (S5PC1XX_GPIO_I_START + (_nr)) | ||
124 | #define S5PC1XX_GPJ0(_nr) (S5PC1XX_GPIO_J0_START + (_nr)) | ||
125 | #define S5PC1XX_GPJ1(_nr) (S5PC1XX_GPIO_J1_START + (_nr)) | ||
126 | #define S5PC1XX_GPJ2(_nr) (S5PC1XX_GPIO_J2_START + (_nr)) | ||
127 | #define S5PC1XX_GPJ3(_nr) (S5PC1XX_GPIO_J3_START + (_nr)) | ||
128 | #define S5PC1XX_GPJ4(_nr) (S5PC1XX_GPIO_J4_START + (_nr)) | ||
129 | #define S5PC1XX_GPK0(_nr) (S5PC1XX_GPIO_K0_START + (_nr)) | ||
130 | #define S5PC1XX_GPK1(_nr) (S5PC1XX_GPIO_K1_START + (_nr)) | ||
131 | #define S5PC1XX_GPK2(_nr) (S5PC1XX_GPIO_K2_START + (_nr)) | ||
132 | #define S5PC1XX_GPK3(_nr) (S5PC1XX_GPIO_K3_START + (_nr)) | ||
133 | #define S5PC1XX_MP00(_nr) (S5PC1XX_GPIO_MP00_START + (_nr)) | ||
134 | #define S5PC1XX_MP01(_nr) (S5PC1XX_GPIO_MP01_START + (_nr)) | ||
135 | #define S5PC1XX_MP02(_nr) (S5PC1XX_GPIO_MP02_START + (_nr)) | ||
136 | #define S5PC1XX_MP03(_nr) (S5PC1XX_GPIO_MP03_START + (_nr)) | ||
137 | #define S5PC1XX_MP04(_nr) (S5PC1XX_GPIO_MP04_START + (_nr)) | ||
138 | |||
139 | /* the end of the S5PC1XX specific gpios */ | ||
140 | #define S5PC1XX_GPIO_END (S5PC1XX_MP04(S5PC1XX_GPIO_MP04_NR) + 1) | ||
141 | #define S3C_GPIO_END S5PC1XX_GPIO_END | ||
142 | |||
143 | /* define the number of gpios we need to the one after the MP04() range */ | ||
144 | #define ARCH_NR_GPIOS (S5PC1XX_MP04(S5PC1XX_GPIO_MP04_NR) + 1) | ||
145 | |||
146 | #include <asm-generic/gpio.h> | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/hardware.h b/arch/arm/mach-s5pc100/include/mach/hardware.h new file mode 100644 index 000000000000..6b38618c2fd9 --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/hardware.h | |||
@@ -0,0 +1,14 @@ | |||
1 | /* linux/arch/arm/mach-s5pc100/include/mach/hardware.h | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * S5PC100 - Hardware support | ||
7 | */ | ||
8 | |||
9 | #ifndef __ASM_ARCH_HARDWARE_H | ||
10 | #define __ASM_ARCH_HARDWARE_H __FILE__ | ||
11 | |||
12 | /* currently nothing here, placeholder */ | ||
13 | |||
14 | #endif /* __ASM_ARCH_HARDWARE_H */ | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h new file mode 100644 index 000000000000..622720dba289 --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/irqs.h | |||
@@ -0,0 +1,14 @@ | |||
1 | /* linux/arch/arm/mach-s5pc100/include/mach/irqs.h | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * S5PC100 - IRQ definitions | ||
7 | */ | ||
8 | |||
9 | #ifndef __ASM_ARCH_IRQS_H | ||
10 | #define __ASM_ARCH_IRQS_H __FILE__ | ||
11 | |||
12 | #include <plat/irqs.h> | ||
13 | |||
14 | #endif /* __ASM_ARCH_IRQ_H */ | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h new file mode 100644 index 000000000000..9e9f39130b2c --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/map.h | |||
@@ -0,0 +1,75 @@ | |||
1 | /* linux/arch/arm/mach-s5pc100/include/mach/map.h | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * Based on mach-s3c6400/include/mach/map.h | ||
7 | * | ||
8 | * S5PC1XX - Memory map definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #ifndef __ASM_ARCH_MAP_H | ||
16 | #define __ASM_ARCH_MAP_H __FILE__ | ||
17 | |||
18 | #include <plat/map-base.h> | ||
19 | |||
20 | |||
21 | /* Chip ID */ | ||
22 | #define S5PC100_PA_CHIPID (0xE0000000) | ||
23 | #define S5PC1XX_PA_CHIPID S5PC100_PA_CHIPID | ||
24 | #define S5PC1XX_VA_CHIPID S3C_VA_SYS | ||
25 | |||
26 | /* System */ | ||
27 | #define S5PC100_PA_SYS (0xE0100000) | ||
28 | #define S5PC100_PA_CLK (S5PC100_PA_SYS + 0x0) | ||
29 | #define S5PC100_PA_PWR (S5PC100_PA_SYS + 0x8000) | ||
30 | #define S5PC1XX_PA_CLK S5PC100_PA_CLK | ||
31 | #define S5PC1XX_PA_PWR S5PC100_PA_PWR | ||
32 | #define S5PC1XX_VA_CLK (S3C_VA_SYS + 0x10000) | ||
33 | #define S5PC1XX_VA_PWR (S3C_VA_SYS + 0x20000) | ||
34 | |||
35 | /* Interrupt */ | ||
36 | #define S5PC100_PA_VIC (0xE4000000) | ||
37 | #define S5PC100_VA_VIC S3C_VA_IRQ | ||
38 | #define S5PC100_PA_VIC_OFFSET 0x100000 | ||
39 | #define S5PC100_VA_VIC_OFFSET 0x10000 | ||
40 | #define S5PC1XX_PA_VIC(x) (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET)) | ||
41 | #define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET)) | ||
42 | |||
43 | /* Timer */ | ||
44 | #define S5PC100_PA_TIMER (0xEA000000) | ||
45 | #define S5PC1XX_PA_TIMER S5PC100_PA_TIMER | ||
46 | #define S5PC1XX_VA_TIMER S3C_VA_TIMER | ||
47 | |||
48 | /* UART */ | ||
49 | #define S5PC100_PA_UART (0xEC000000) | ||
50 | #define S5PC1XX_PA_UART S5PC100_PA_UART | ||
51 | #define S5PC1XX_VA_UART S3C_VA_UART | ||
52 | |||
53 | /* IIC */ | ||
54 | #define S5PC100_PA_IIC (0xEC100000) | ||
55 | |||
56 | /* ETC */ | ||
57 | #define S5PC100_PA_SDRAM (0x20000000) | ||
58 | |||
59 | /* compatibility defines. */ | ||
60 | #define S3C_PA_UART S5PC100_PA_UART | ||
61 | #define S3C_PA_UART0 (S5PC100_PA_UART + 0x0) | ||
62 | #define S3C_PA_UART1 (S5PC100_PA_UART + 0x400) | ||
63 | #define S3C_PA_UART2 (S5PC100_PA_UART + 0x800) | ||
64 | #define S3C_PA_UART3 (S5PC100_PA_UART + 0xC00) | ||
65 | #define S3C_VA_UART0 (S3C_VA_UART + 0x0) | ||
66 | #define S3C_VA_UART1 (S3C_VA_UART + 0x400) | ||
67 | #define S3C_VA_UART2 (S3C_VA_UART + 0x800) | ||
68 | #define S3C_VA_UART3 (S3C_VA_UART + 0xC00) | ||
69 | #define S3C_UART_OFFSET 0x400 | ||
70 | #define S3C_VA_VIC0 (S3C_VA_IRQ + 0x0) | ||
71 | #define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) | ||
72 | #define S3C_VA_VIC2 (S3C_VA_IRQ + 0x20000) | ||
73 | #define S3C_PA_IIC S5PC100_PA_IIC | ||
74 | |||
75 | #endif /* __ASM_ARCH_C100_MAP_H */ | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/memory.h b/arch/arm/mach-s5pc100/include/mach/memory.h new file mode 100644 index 000000000000..4b60d18179f7 --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/memory.h | |||
@@ -0,0 +1,18 @@ | |||
1 | /* arch/arm/mach-s5pc100/include/mach/memory.h | ||
2 | * | ||
3 | * Copyright 2008 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * Based on mach-s3c6400/include/mach/memory.h | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_MEMORY_H | ||
14 | #define __ASM_ARCH_MEMORY_H | ||
15 | |||
16 | #define PHYS_OFFSET UL(0x20000000) | ||
17 | |||
18 | #endif | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/pwm-clock.h b/arch/arm/mach-s5pc100/include/mach/pwm-clock.h new file mode 100644 index 000000000000..b34d2f7aae52 --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/pwm-clock.h | |||
@@ -0,0 +1,56 @@ | |||
1 | /* linux/arch/arm/mach-s5pc100/include/mach/pwm-clock.h | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * S5PC100 - pwm clock and timer support | ||
7 | * | ||
8 | * Based on mach-s3c6400/include/mach/pwm-clock.h | ||
9 | */ | ||
10 | |||
11 | /** | ||
12 | * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk | ||
13 | * @tcfg: The timer TCFG1 register bits shifted down to 0. | ||
14 | * | ||
15 | * Return true if the given configuration from TCFG1 is a TCLK instead | ||
16 | * any of the TDIV clocks. | ||
17 | */ | ||
18 | static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) | ||
19 | { | ||
20 | return tcfg >= S3C64XX_TCFG1_MUX_TCLK; | ||
21 | } | ||
22 | |||
23 | /** | ||
24 | * tcfg_to_divisor() - convert tcfg1 setting to a divisor | ||
25 | * @tcfg1: The tcfg1 setting, shifted down. | ||
26 | * | ||
27 | * Get the divisor value for the given tcfg1 setting. We assume the | ||
28 | * caller has already checked to see if this is not a TCLK source. | ||
29 | */ | ||
30 | static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) | ||
31 | { | ||
32 | return 1 << tcfg1; | ||
33 | } | ||
34 | |||
35 | /** | ||
36 | * pwm_tdiv_has_div1() - does the tdiv setting have a /1 | ||
37 | * | ||
38 | * Return true if we have a /1 in the tdiv setting. | ||
39 | */ | ||
40 | static inline unsigned int pwm_tdiv_has_div1(void) | ||
41 | { | ||
42 | return 1; | ||
43 | } | ||
44 | |||
45 | /** | ||
46 | * pwm_tdiv_div_bits() - calculate TCFG1 divisor value. | ||
47 | * @div: The divisor to calculate the bit information for. | ||
48 | * | ||
49 | * Turn a divisor into the necessary bit field for TCFG1. | ||
50 | */ | ||
51 | static inline unsigned long pwm_tdiv_div_bits(unsigned int div) | ||
52 | { | ||
53 | return ilog2(div); | ||
54 | } | ||
55 | |||
56 | #define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-irq.h b/arch/arm/mach-s5pc100/include/mach/regs-irq.h new file mode 100644 index 000000000000..751ac15438c8 --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/regs-irq.h | |||
@@ -0,0 +1,24 @@ | |||
1 | /* linux/arch/arm/mach-s5pc100/include/mach/regs-irq.h | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * S5PC1XX - IRQ register definitions | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_REGS_IRQ_H | ||
14 | #define __ASM_ARCH_REGS_IRQ_H __FILE__ | ||
15 | |||
16 | #include <mach/map.h> | ||
17 | #include <asm/hardware/vic.h> | ||
18 | |||
19 | /* interrupt controller */ | ||
20 | #define S5PC1XX_VIC0REG(x) ((x) + S5PC1XX_VA_VIC(0)) | ||
21 | #define S5PC1XX_VIC1REG(x) ((x) + S5PC1XX_VA_VIC(1)) | ||
22 | #define S5PC1XX_VIC2REG(x) ((x) + S5PC1XX_VA_VIC(2)) | ||
23 | |||
24 | #endif /* __ASM_ARCH_REGS_IRQ_H */ | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/system.h b/arch/arm/mach-s5pc100/include/mach/system.h new file mode 100644 index 000000000000..e39014375470 --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/system.h | |||
@@ -0,0 +1,24 @@ | |||
1 | /* linux/arch/arm/mach-s5pc100/include/mach/system.h | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * S5PC1XX - system implementation | ||
7 | * | ||
8 | * Based on mach-s3c6400/include/mach/system.h | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_SYSTEM_H | ||
12 | #define __ASM_ARCH_SYSTEM_H __FILE__ | ||
13 | |||
14 | static void arch_idle(void) | ||
15 | { | ||
16 | /* nothing here yet */ | ||
17 | } | ||
18 | |||
19 | static void arch_reset(char mode, const char *cmd) | ||
20 | { | ||
21 | /* nothing here yet */ | ||
22 | } | ||
23 | |||
24 | #endif /* __ASM_ARCH_IRQ_H */ | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/tick.h b/arch/arm/mach-s5pc100/include/mach/tick.h new file mode 100644 index 000000000000..d3de0f3591ae --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/tick.h | |||
@@ -0,0 +1,29 @@ | |||
1 | /* linux/arch/arm/mach-s5pc100/include/mach/tick.h | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * S3C64XX - Timer tick support definitions | ||
7 | * | ||
8 | * Based on mach-s3c6400/include/mach/tick.h | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #ifndef __ASM_ARCH_TICK_H | ||
16 | #define __ASM_ARCH_TICK_H __FILE__ | ||
17 | |||
18 | /* note, the timer interrutps turn up in 2 places, the vic and then | ||
19 | * the timer block. We take the VIC as the base at the moment. | ||
20 | */ | ||
21 | static inline u32 s3c24xx_ostimer_pending(void) | ||
22 | { | ||
23 | u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS); | ||
24 | return pend & 1 << (IRQ_TIMER4 - S5PC1XX_IRQ_VIC0(0)); | ||
25 | } | ||
26 | |||
27 | #define TICK_MAX (0xffffffff) | ||
28 | |||
29 | #endif /* __ASM_ARCH_TICK_H */ | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/uncompress.h b/arch/arm/mach-s5pc100/include/mach/uncompress.h new file mode 100644 index 000000000000..01ccf535e76c --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/uncompress.h | |||
@@ -0,0 +1,28 @@ | |||
1 | /* arch/arm/mach-s5pc100/include/mach/uncompress.h | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * S5PC100 - uncompress code | ||
7 | * | ||
8 | * Based on mach-s3c6400/include/mach/uncompress.h | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #ifndef __ASM_ARCH_UNCOMPRESS_H | ||
16 | #define __ASM_ARCH_UNCOMPRESS_H | ||
17 | |||
18 | #include <mach/map.h> | ||
19 | #include <plat/uncompress.h> | ||
20 | |||
21 | static void arch_detect_cpu(void) | ||
22 | { | ||
23 | /* we do not need to do any cpu detection here at the moment. */ | ||
24 | fifo_mask = S3C2440_UFSTAT_TXMASK; | ||
25 | fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT; | ||
26 | } | ||
27 | |||
28 | #endif /* __ASM_ARCH_UNCOMPRESS_H */ | ||
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c new file mode 100644 index 000000000000..214093cd7632 --- /dev/null +++ b/arch/arm/mach-s5pc100/mach-smdkc100.c | |||
@@ -0,0 +1,103 @@ | |||
1 | /* linux/arch/arm/mach-s5pc100/mach-smdkc100.c | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Author: Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | */ | ||
11 | |||
12 | #include <linux/kernel.h> | ||
13 | #include <linux/types.h> | ||
14 | #include <linux/interrupt.h> | ||
15 | #include <linux/list.h> | ||
16 | #include <linux/timer.h> | ||
17 | #include <linux/init.h> | ||
18 | #include <linux/serial_core.h> | ||
19 | #include <linux/platform_device.h> | ||
20 | #include <linux/io.h> | ||
21 | #include <linux/gpio.h> | ||
22 | #include <linux/i2c.h> | ||
23 | #include <linux/fb.h> | ||
24 | #include <linux/delay.h> | ||
25 | |||
26 | #include <asm/mach/arch.h> | ||
27 | #include <asm/mach/map.h> | ||
28 | |||
29 | #include <mach/map.h> | ||
30 | |||
31 | #include <asm/irq.h> | ||
32 | #include <asm/mach-types.h> | ||
33 | |||
34 | #include <plat/regs-serial.h> | ||
35 | |||
36 | #include <plat/clock.h> | ||
37 | #include <plat/devs.h> | ||
38 | #include <plat/cpu.h> | ||
39 | #include <plat/s5pc100.h> | ||
40 | |||
41 | #define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK) | ||
42 | #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB) | ||
43 | #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) | ||
44 | |||
45 | static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = { | ||
46 | [0] = { | ||
47 | .hwport = 0, | ||
48 | .flags = 0, | ||
49 | .ucon = 0x3c5, | ||
50 | .ulcon = 0x03, | ||
51 | .ufcon = 0x51, | ||
52 | }, | ||
53 | [1] = { | ||
54 | .hwport = 1, | ||
55 | .flags = 0, | ||
56 | .ucon = 0x3c5, | ||
57 | .ulcon = 0x03, | ||
58 | .ufcon = 0x51, | ||
59 | }, | ||
60 | [2] = { | ||
61 | .hwport = 2, | ||
62 | .flags = 0, | ||
63 | .ucon = 0x3c5, | ||
64 | .ulcon = 0x03, | ||
65 | .ufcon = 0x51, | ||
66 | }, | ||
67 | [3] = { | ||
68 | .hwport = 3, | ||
69 | .flags = 0, | ||
70 | .ucon = 0x3c5, | ||
71 | .ulcon = 0x03, | ||
72 | .ufcon = 0x51, | ||
73 | }, | ||
74 | }; | ||
75 | |||
76 | static struct map_desc smdkc100_iodesc[] = {}; | ||
77 | |||
78 | static struct platform_device *smdkc100_devices[] __initdata = { | ||
79 | }; | ||
80 | |||
81 | static void __init smdkc100_map_io(void) | ||
82 | { | ||
83 | s5pc1xx_init_io(smdkc100_iodesc, ARRAY_SIZE(smdkc100_iodesc)); | ||
84 | s3c24xx_init_clocks(12000000); | ||
85 | s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs)); | ||
86 | } | ||
87 | |||
88 | static void __init smdkc100_machine_init(void) | ||
89 | { | ||
90 | platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices)); | ||
91 | } | ||
92 | |||
93 | MACHINE_START(SMDKC100, "SMDKC100") | ||
94 | /* Maintainer: Byungho Min <bhmin@samsung.com> */ | ||
95 | .phys_io = S5PC1XX_PA_UART & 0xfff00000, | ||
96 | .io_pg_offst = (((u32)S5PC1XX_VA_UART) >> 18) & 0xfffc, | ||
97 | .boot_params = S5PC100_PA_SDRAM + 0x100, | ||
98 | |||
99 | .init_irq = s5pc100_init_irq, | ||
100 | .map_io = smdkc100_map_io, | ||
101 | .init_machine = smdkc100_machine_init, | ||
102 | .timer = &s3c24xx_timer, | ||
103 | MACHINE_END | ||
diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig index 935c7558469b..8931c5f0e46b 100644 --- a/arch/arm/plat-s3c/Kconfig +++ b/arch/arm/plat-s3c/Kconfig | |||
@@ -198,4 +198,9 @@ config S3C_DEV_USB_HSOTG | |||
198 | help | 198 | help |
199 | Compile in platform device definition for USB high-speed OtG | 199 | Compile in platform device definition for USB high-speed OtG |
200 | 200 | ||
201 | config S3C_DEV_NAND | ||
202 | bool | ||
203 | help | ||
204 | Compile in platform device definition for NAND controller | ||
205 | |||
201 | endif | 206 | endif |
diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile index 0761766b1833..3c09109e9e84 100644 --- a/arch/arm/plat-s3c/Makefile +++ b/arch/arm/plat-s3c/Makefile | |||
@@ -28,13 +28,17 @@ obj-$(CONFIG_PM) += pm.o | |||
28 | obj-$(CONFIG_PM) += pm-gpio.o | 28 | obj-$(CONFIG_PM) += pm-gpio.o |
29 | obj-$(CONFIG_S3C2410_PM_CHECK) += pm-check.o | 29 | obj-$(CONFIG_S3C2410_PM_CHECK) += pm-check.o |
30 | 30 | ||
31 | # PWM support | ||
32 | |||
33 | obj-$(CONFIG_HAVE_PWM) += pwm.o | ||
34 | |||
31 | # devices | 35 | # devices |
32 | 36 | ||
33 | obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o | 37 | obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o |
34 | obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o | 38 | obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o |
35 | obj-y += dev-i2c0.o | 39 | obj-y += dev-i2c0.o |
36 | obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o | 40 | obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o |
37 | obj-$(CONFIG_SND_S3C64XX_SOC_I2S) += dev-audio.o | ||
38 | obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o | 41 | obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o |
39 | obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o | 42 | obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o |
40 | obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o | 43 | obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o |
44 | obj-$(CONFIG_S3C_DEV_NAND) += dev-nand.o | ||
diff --git a/arch/arm/plat-s3c/dev-nand.c b/arch/arm/plat-s3c/dev-nand.c new file mode 100644 index 000000000000..4e5323732434 --- /dev/null +++ b/arch/arm/plat-s3c/dev-nand.c | |||
@@ -0,0 +1,30 @@ | |||
1 | /* | ||
2 | * S3C series device definition for nand device | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License version 2 as | ||
6 | * published by the Free Software Foundation. | ||
7 | */ | ||
8 | |||
9 | #include <linux/kernel.h> | ||
10 | #include <linux/platform_device.h> | ||
11 | |||
12 | #include <mach/map.h> | ||
13 | #include <plat/devs.h> | ||
14 | |||
15 | static struct resource s3c_nand_resource[] = { | ||
16 | [0] = { | ||
17 | .start = S3C_PA_NAND, | ||
18 | .end = S3C_PA_NAND + SZ_1M, | ||
19 | .flags = IORESOURCE_MEM, | ||
20 | } | ||
21 | }; | ||
22 | |||
23 | struct platform_device s3c_device_nand = { | ||
24 | .name = "s3c2410-nand", | ||
25 | .id = -1, | ||
26 | .num_resources = ARRAY_SIZE(s3c_nand_resource), | ||
27 | .resource = s3c_nand_resource, | ||
28 | }; | ||
29 | |||
30 | EXPORT_SYMBOL(s3c_device_nand); | ||
diff --git a/arch/arm/plat-s3c/include/plat/adc.h b/arch/arm/plat-s3c/include/plat/adc.h index d847bd476b6c..5f3b1cd53b90 100644 --- a/arch/arm/plat-s3c/include/plat/adc.h +++ b/arch/arm/plat-s3c/include/plat/adc.h | |||
@@ -19,10 +19,14 @@ struct s3c_adc_client; | |||
19 | extern int s3c_adc_start(struct s3c_adc_client *client, | 19 | extern int s3c_adc_start(struct s3c_adc_client *client, |
20 | unsigned int channel, unsigned int nr_samples); | 20 | unsigned int channel, unsigned int nr_samples); |
21 | 21 | ||
22 | extern int s3c_adc_read(struct s3c_adc_client *client, unsigned int ch); | ||
23 | |||
22 | extern struct s3c_adc_client * | 24 | extern struct s3c_adc_client * |
23 | s3c_adc_register(struct platform_device *pdev, | 25 | s3c_adc_register(struct platform_device *pdev, |
24 | void (*select)(unsigned selected), | 26 | void (*select)(struct s3c_adc_client *client, |
25 | void (*conv)(unsigned d0, unsigned d1, | 27 | unsigned selected), |
28 | void (*conv)(struct s3c_adc_client *client, | ||
29 | unsigned d0, unsigned d1, | ||
26 | unsigned *samples_left), | 30 | unsigned *samples_left), |
27 | unsigned int is_ts); | 31 | unsigned int is_ts); |
28 | 32 | ||
diff --git a/arch/arm/plat-s3c/include/plat/cpu-freq.h b/arch/arm/plat-s3c/include/plat/cpu-freq.h index c86a13307e90..7b982b7f28cd 100644 --- a/arch/arm/plat-s3c/include/plat/cpu-freq.h +++ b/arch/arm/plat-s3c/include/plat/cpu-freq.h | |||
@@ -17,6 +17,21 @@ struct s3c_cpufreq_info; | |||
17 | struct s3c_cpufreq_board; | 17 | struct s3c_cpufreq_board; |
18 | struct s3c_iotimings; | 18 | struct s3c_iotimings; |
19 | 19 | ||
20 | /** | ||
21 | * struct s3c_freq - frequency information (mainly for core drivers) | ||
22 | * @fclk: The FCLK frequency in Hz. | ||
23 | * @armclk: The ARMCLK frequency in Hz. | ||
24 | * @hclk_tns: HCLK cycle time in 10ths of nano-seconds. | ||
25 | * @hclk: The HCLK frequency in Hz. | ||
26 | * @pclk: The PCLK frequency in Hz. | ||
27 | * | ||
28 | * This contains the frequency information about the current configuration | ||
29 | * mainly for the core drivers to ensure we do not end up passing about | ||
30 | * a large number of parameters. | ||
31 | * | ||
32 | * The @hclk_tns field is a useful cache for the parts of the drivers that | ||
33 | * need to calculate IO timings and suchlike. | ||
34 | */ | ||
20 | struct s3c_freq { | 35 | struct s3c_freq { |
21 | unsigned long fclk; | 36 | unsigned long fclk; |
22 | unsigned long armclk; | 37 | unsigned long armclk; |
@@ -25,48 +40,84 @@ struct s3c_freq { | |||
25 | unsigned long pclk; | 40 | unsigned long pclk; |
26 | }; | 41 | }; |
27 | 42 | ||
28 | /* wrapper 'struct cpufreq_freqs' so that any drivers receiving the | 43 | /** |
44 | * struct s3c_cpufreq_freqs - s3c cpufreq notification information. | ||
45 | * @freqs: The cpufreq setting information. | ||
46 | * @old: The old clock settings. | ||
47 | * @new: The new clock settings. | ||
48 | * @pll_changing: Set if the PLL is changing. | ||
49 | * | ||
50 | * Wrapper 'struct cpufreq_freqs' so that any drivers receiving the | ||
29 | * notification can use this information that is not provided by just | 51 | * notification can use this information that is not provided by just |
30 | * having the core frequency alone. | 52 | * having the core frequency alone. |
53 | * | ||
54 | * The pll_changing flag is used to indicate if the PLL itself is | ||
55 | * being set during this change. This is important as the clocks | ||
56 | * will temporarily be set to the XTAL clock during this time, so | ||
57 | * drivers may want to close down their output during this time. | ||
58 | * | ||
59 | * Note, this is not being used by any current drivers and therefore | ||
60 | * may be removed in the future. | ||
31 | */ | 61 | */ |
32 | |||
33 | struct s3c_cpufreq_freqs { | 62 | struct s3c_cpufreq_freqs { |
34 | struct cpufreq_freqs freqs; | 63 | struct cpufreq_freqs freqs; |
35 | struct s3c_freq old; | 64 | struct s3c_freq old; |
36 | struct s3c_freq new; | 65 | struct s3c_freq new; |
66 | |||
67 | unsigned int pll_changing:1; | ||
37 | }; | 68 | }; |
38 | 69 | ||
39 | #define to_s3c_cpufreq(_cf) container_of(_cf, struct s3c_cpufreq_freqs, freqs) | 70 | #define to_s3c_cpufreq(_cf) container_of(_cf, struct s3c_cpufreq_freqs, freqs) |
40 | 71 | ||
72 | /** | ||
73 | * struct s3c_clkdivs - clock divisor information | ||
74 | * @p_divisor: Divisor from FCLK to PCLK. | ||
75 | * @h_divisor: Divisor from FCLK to HCLK. | ||
76 | * @arm_divisor: Divisor from FCLK to ARMCLK (not all CPUs). | ||
77 | * @dvs: Non-zero if using DVS mode for ARMCLK. | ||
78 | * | ||
79 | * Divisor settings for the core clocks. | ||
80 | */ | ||
41 | struct s3c_clkdivs { | 81 | struct s3c_clkdivs { |
42 | int p_divisor; /* fclk / pclk */ | 82 | int p_divisor; |
43 | int h_divisor; /* fclk / hclk */ | 83 | int h_divisor; |
44 | int arm_divisor; /* not all cpus have this. */ | 84 | int arm_divisor; |
45 | unsigned char dvs; /* using dvs mode to arm. */ | 85 | unsigned char dvs; |
46 | }; | 86 | }; |
47 | 87 | ||
48 | #define PLLVAL(_m, _p, _s) (((_m) << 12) | ((_p) << 4) | (_s)) | 88 | #define PLLVAL(_m, _p, _s) (((_m) << 12) | ((_p) << 4) | (_s)) |
49 | 89 | ||
90 | /** | ||
91 | * struct s3c_pllval - PLL value entry. | ||
92 | * @freq: The frequency for this entry in Hz. | ||
93 | * @pll_reg: The PLL register setting for this PLL value. | ||
94 | */ | ||
50 | struct s3c_pllval { | 95 | struct s3c_pllval { |
51 | unsigned long freq; | 96 | unsigned long freq; |
52 | unsigned long pll_reg; | 97 | unsigned long pll_reg; |
53 | }; | 98 | }; |
54 | 99 | ||
55 | struct s3c_cpufreq_config { | 100 | /** |
56 | struct s3c_freq freq; | 101 | * struct s3c_cpufreq_board - per-board cpu frequency informatin |
57 | struct s3c_pllval pll; | 102 | * @refresh: The SDRAM refresh period in nanoseconds. |
58 | struct s3c_clkdivs divs; | 103 | * @auto_io: Set if the IO timing settings should be generated from the |
59 | struct s3c_cpufreq_info *info; /* for core, not drivers */ | 104 | * initialisation time hardware registers. |
60 | struct s3c_cpufreq_board *board; | 105 | * @need_io: Set if the board has external IO on any of the chipselect |
61 | }; | 106 | * lines that will require the hardware timing registers to be |
62 | 107 | * updated on a clock change. | |
63 | /* s3c_cpufreq_board | 108 | * @max: The maxium frequency limits for the system. Any field that |
109 | * is left at zero will use the CPU's settings. | ||
110 | * | ||
111 | * This contains the board specific settings that affect how the CPU | ||
112 | * drivers chose settings. These include the memory refresh and IO | ||
113 | * timing information. | ||
64 | * | 114 | * |
65 | * per-board configuraton information, such as memory refresh and | 115 | * Registration depends on the driver being used, the ARMCLK only |
66 | * how to initialise IO timings. | 116 | * implementation does not currently need this but the older style |
117 | * driver requires this to be available. | ||
67 | */ | 118 | */ |
68 | struct s3c_cpufreq_board { | 119 | struct s3c_cpufreq_board { |
69 | unsigned int refresh; /* refresh period in ns */ | 120 | unsigned int refresh; |
70 | unsigned int auto_io:1; /* automatically init io timings. */ | 121 | unsigned int auto_io:1; /* automatically init io timings. */ |
71 | unsigned int need_io:1; /* set if needs io timing support. */ | 122 | unsigned int need_io:1; /* set if needs io timing support. */ |
72 | 123 | ||
diff --git a/arch/arm/plat-s3c/include/plat/cpu.h b/arch/arm/plat-s3c/include/plat/cpu.h index be541cbba070..fbc3d498e02e 100644 --- a/arch/arm/plat-s3c/include/plat/cpu.h +++ b/arch/arm/plat-s3c/include/plat/cpu.h | |||
@@ -65,6 +65,7 @@ extern struct sys_timer s3c24xx_timer; | |||
65 | /* system device classes */ | 65 | /* system device classes */ |
66 | 66 | ||
67 | extern struct sysdev_class s3c2410_sysclass; | 67 | extern struct sysdev_class s3c2410_sysclass; |
68 | extern struct sysdev_class s3c2410a_sysclass; | ||
68 | extern struct sysdev_class s3c2412_sysclass; | 69 | extern struct sysdev_class s3c2412_sysclass; |
69 | extern struct sysdev_class s3c2440_sysclass; | 70 | extern struct sysdev_class s3c2440_sysclass; |
70 | extern struct sysdev_class s3c2442_sysclass; | 71 | extern struct sysdev_class s3c2442_sysclass; |
diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h index 2e170827e0b0..0f540ea1e999 100644 --- a/arch/arm/plat-s3c/include/plat/devs.h +++ b/arch/arm/plat-s3c/include/plat/devs.h | |||
@@ -46,6 +46,8 @@ extern struct platform_device s3c_device_hsmmc2; | |||
46 | extern struct platform_device s3c_device_spi0; | 46 | extern struct platform_device s3c_device_spi0; |
47 | extern struct platform_device s3c_device_spi1; | 47 | extern struct platform_device s3c_device_spi1; |
48 | 48 | ||
49 | extern struct platform_device s3c_device_hwmon; | ||
50 | |||
49 | extern struct platform_device s3c_device_nand; | 51 | extern struct platform_device s3c_device_nand; |
50 | 52 | ||
51 | extern struct platform_device s3c_device_usbgadget; | 53 | extern struct platform_device s3c_device_usbgadget; |
@@ -56,5 +58,6 @@ extern struct platform_device s3c_device_usb_hsotg; | |||
56 | #ifdef CONFIG_CPU_S3C2440 | 58 | #ifdef CONFIG_CPU_S3C2440 |
57 | 59 | ||
58 | extern struct platform_device s3c_device_camif; | 60 | extern struct platform_device s3c_device_camif; |
61 | extern struct platform_device s3c_device_ac97; | ||
59 | 62 | ||
60 | #endif | 63 | #endif |
diff --git a/arch/arm/plat-s3c/include/plat/hwmon.h b/arch/arm/plat-s3c/include/plat/hwmon.h new file mode 100644 index 000000000000..1ba88ea0aa31 --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/hwmon.h | |||
@@ -0,0 +1,41 @@ | |||
1 | /* linux/arch/arm/plat-s3c/include/plat/hwmon.h | ||
2 | * | ||
3 | * Copyright 2005 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * | ||
7 | * S3C - HWMon interface for ADC | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_ADC_HWMON_H | ||
15 | #define __ASM_ARCH_ADC_HWMON_H __FILE__ | ||
16 | |||
17 | /** | ||
18 | * s3c_hwmon_chcfg - channel configuration | ||
19 | * @name: The name to give this channel. | ||
20 | * @mult: Multiply the ADC value read by this. | ||
21 | * @div: Divide the value from the ADC by this. | ||
22 | * | ||
23 | * The value read from the ADC is converted to a value that | ||
24 | * hwmon expects (mV) by result = (value_read * @mult) / @div. | ||
25 | */ | ||
26 | struct s3c_hwmon_chcfg { | ||
27 | const char *name; | ||
28 | unsigned int mult; | ||
29 | unsigned int div; | ||
30 | }; | ||
31 | |||
32 | /** | ||
33 | * s3c_hwmon_pdata - HWMON platform data | ||
34 | * @in: One configuration for each possible channel used. | ||
35 | */ | ||
36 | struct s3c_hwmon_pdata { | ||
37 | struct s3c_hwmon_chcfg *in[8]; | ||
38 | }; | ||
39 | |||
40 | #endif /* __ASM_ARCH_ADC_HWMON_H */ | ||
41 | |||
diff --git a/arch/arm/plat-s3c/include/plat/map-base.h b/arch/arm/plat-s3c/include/plat/map-base.h index b84289d32a54..250be311c85b 100644 --- a/arch/arm/plat-s3c/include/plat/map-base.h +++ b/arch/arm/plat-s3c/include/plat/map-base.h | |||
@@ -32,9 +32,15 @@ | |||
32 | 32 | ||
33 | #define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */ | 33 | #define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */ |
34 | #define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */ | 34 | #define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */ |
35 | #define S3C_VA_MEM S3C_ADDR(0x00200000) /* system control */ | 35 | #define S3C_VA_MEM S3C_ADDR(0x00200000) /* memory control */ |
36 | #define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */ | 36 | #define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */ |
37 | #define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */ | 37 | #define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */ |
38 | #define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */ | 38 | #define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */ |
39 | 39 | ||
40 | /* This is used for the CPU specific mappings that may be needed, so that | ||
41 | * they do not need to directly used S3C_ADDR() and thus make it easier to | ||
42 | * modify the space for mapping. | ||
43 | */ | ||
44 | #define S3C_ADDR_CPU(x) S3C_ADDR(0x00500000 + (x)) | ||
45 | |||
40 | #endif /* __ASM_PLAT_MAP_H */ | 46 | #endif /* __ASM_PLAT_MAP_H */ |
diff --git a/arch/arm/plat-s3c24xx/pwm.c b/arch/arm/plat-s3c/pwm.c index 0120b760315b..f3d37ac5595b 100644 --- a/arch/arm/plat-s3c24xx/pwm.c +++ b/arch/arm/plat-s3c/pwm.c | |||
@@ -1,10 +1,10 @@ | |||
1 | /* arch/arm/plat-s3c24xx/pwm.c | 1 | /* arch/arm/plat-s3c/pwm.c |
2 | * | 2 | * |
3 | * Copyright (c) 2007 Ben Dooks | 3 | * Copyright (c) 2007 Ben Dooks |
4 | * Copyright (c) 2008 Simtec Electronics | 4 | * Copyright (c) 2008 Simtec Electronics |
5 | * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org> | 5 | * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org> |
6 | * | 6 | * |
7 | * S3C24XX PWM device core | 7 | * S3C series PWM device core |
8 | * | 8 | * |
9 | * This program is free software; you can redistribute it and/or modify | 9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License as published by | 10 | * it under the terms of the GNU General Public License as published by |
@@ -20,6 +20,7 @@ | |||
20 | #include <linux/pwm.h> | 20 | #include <linux/pwm.h> |
21 | 21 | ||
22 | #include <mach/irqs.h> | 22 | #include <mach/irqs.h> |
23 | #include <mach/map.h> | ||
23 | 24 | ||
24 | #include <plat/devs.h> | 25 | #include <plat/devs.h> |
25 | #include <plat/regs-timer.h> | 26 | #include <plat/regs-timer.h> |
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig index 5b0bc914f58e..9c7aca489643 100644 --- a/arch/arm/plat-s3c24xx/Kconfig +++ b/arch/arm/plat-s3c24xx/Kconfig | |||
@@ -10,6 +10,7 @@ config PLAT_S3C24XX | |||
10 | default y | 10 | default y |
11 | select NO_IOPORT | 11 | select NO_IOPORT |
12 | select ARCH_REQUIRE_GPIOLIB | 12 | select ARCH_REQUIRE_GPIOLIB |
13 | select S3C_DEVICE_NAND | ||
13 | help | 14 | help |
14 | Base platform code for any Samsung S3C24XX device | 15 | Base platform code for any Samsung S3C24XX device |
15 | 16 | ||
@@ -34,6 +35,40 @@ config CPU_S3C244X | |||
34 | help | 35 | help |
35 | Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems. | 36 | Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems. |
36 | 37 | ||
38 | config S3C2440_CPUFREQ | ||
39 | bool "S3C2440/S3C2442 CPU Frequency scaling support" | ||
40 | depends on CPU_FREQ_S3C24XX && (CPU_S3C2440 || CPU_S3C2442) | ||
41 | select S3C2410_CPUFREQ_UTILS | ||
42 | default y | ||
43 | help | ||
44 | CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs. | ||
45 | |||
46 | config S3C2440_XTAL_12000000 | ||
47 | bool | ||
48 | help | ||
49 | Indicate that the build needs to support 12MHz system | ||
50 | crystal. | ||
51 | |||
52 | config S3C2440_XTAL_16934400 | ||
53 | bool | ||
54 | help | ||
55 | Indicate that the build needs to support 16.9344MHz system | ||
56 | crystal. | ||
57 | |||
58 | config S3C2440_PLL_12000000 | ||
59 | bool | ||
60 | depends on S3C2440_CPUFREQ && S3C2440_XTAL_12000000 | ||
61 | default y if CPU_FREQ_S3C24XX_PLL | ||
62 | help | ||
63 | PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals. | ||
64 | |||
65 | config S3C2440_PLL_16934400 | ||
66 | bool | ||
67 | depends on S3C2440_CPUFREQ && S3C2440_XTAL_16934400 | ||
68 | default y if CPU_FREQ_S3C24XX_PLL | ||
69 | help | ||
70 | PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals. | ||
71 | |||
37 | config S3C24XX_PWM | 72 | config S3C24XX_PWM |
38 | bool "PWM device support" | 73 | bool "PWM device support" |
39 | select HAVE_PWM | 74 | select HAVE_PWM |
@@ -105,8 +140,39 @@ config S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7 | |||
105 | SPI GPIO configuration code for BUS 1 when connected to | 140 | SPI GPIO configuration code for BUS 1 when connected to |
106 | GPG5, GPG6 and GPG7. | 141 | GPG5, GPG6 and GPG7. |
107 | 142 | ||
143 | config S3C24XX_SPI_BUS1_GPD8_GPD9_GPD10 | ||
144 | bool | ||
145 | help | ||
146 | SPI GPIO configuration code for BUS 1 when connected to | ||
147 | GPD8, GPD9 and GPD10. | ||
148 | |||
108 | # common code for s3c24xx based machines, such as the SMDKs. | 149 | # common code for s3c24xx based machines, such as the SMDKs. |
109 | 150 | ||
151 | # cpu frequency items common between s3c2410 and s3c2440/s3c2442 | ||
152 | |||
153 | config S3C2410_IOTIMING | ||
154 | bool | ||
155 | depends on CPU_FREQ_S3C24XX | ||
156 | help | ||
157 | Internal node to select io timing code that is common to the s3c2410 | ||
158 | and s3c2440/s3c2442 cpu frequency support. | ||
159 | |||
160 | config S3C2410_CPUFREQ_UTILS | ||
161 | bool | ||
162 | depends on CPU_FREQ_S3C24XX | ||
163 | help | ||
164 | Internal node to select timing code that is common to the s3c2410 | ||
165 | and s3c2440/s3c244 cpu frequency support. | ||
166 | |||
167 | # cpu frequency support common to s3c2412, s3c2413 and s3c2442 | ||
168 | |||
169 | config S3C2412_IOTIMING | ||
170 | bool | ||
171 | depends on CPU_FREQ_S3C24XX && (CPU_S3C2412 || CPU_S3C2443) | ||
172 | help | ||
173 | Intel node to select io timing code that is common to the s3c2412 | ||
174 | and the s3c2443. | ||
175 | |||
110 | config MACH_SMDK | 176 | config MACH_SMDK |
111 | bool | 177 | bool |
112 | help | 178 | help |
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile index 579a165c2827..7780d2dd833a 100644 --- a/arch/arm/plat-s3c24xx/Makefile +++ b/arch/arm/plat-s3c24xx/Makefile | |||
@@ -20,19 +20,28 @@ obj-y += gpiolib.o | |||
20 | obj-y += clock.o | 20 | obj-y += clock.o |
21 | obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o | 21 | obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o |
22 | 22 | ||
23 | obj-$(CONFIG_CPU_FREQ_S3C24XX) += cpu-freq.o | ||
24 | obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpu-freq-debugfs.o | ||
25 | |||
23 | # Architecture dependant builds | 26 | # Architecture dependant builds |
24 | 27 | ||
25 | obj-$(CONFIG_CPU_S3C244X) += s3c244x.o | 28 | obj-$(CONFIG_CPU_S3C244X) += s3c244x.o |
26 | obj-$(CONFIG_CPU_S3C244X) += s3c244x-irq.o | 29 | obj-$(CONFIG_CPU_S3C244X) += s3c244x-irq.o |
27 | obj-$(CONFIG_CPU_S3C244X) += s3c244x-clock.o | 30 | obj-$(CONFIG_CPU_S3C244X) += s3c244x-clock.o |
31 | obj-$(CONFIG_S3C2440_CPUFREQ) += s3c2440-cpufreq.o | ||
32 | obj-$(CONFIG_S3C2440_PLL_12000000) += s3c2440-pll-12000000.o | ||
33 | obj-$(CONFIG_S3C2440_PLL_16934400) += s3c2440-pll-16934400.o | ||
34 | |||
28 | obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o | 35 | obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o |
29 | obj-$(CONFIG_PM) += pm.o | 36 | obj-$(CONFIG_PM) += pm.o |
30 | obj-$(CONFIG_PM) += irq-pm.o | 37 | obj-$(CONFIG_PM) += irq-pm.o |
31 | obj-$(CONFIG_PM) += sleep.o | 38 | obj-$(CONFIG_PM) += sleep.o |
32 | obj-$(CONFIG_S3C24XX_PWM) += pwm.o | ||
33 | obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o | 39 | obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o |
34 | obj-$(CONFIG_S3C2410_DMA) += dma.o | 40 | obj-$(CONFIG_S3C2410_DMA) += dma.o |
35 | obj-$(CONFIG_S3C24XX_ADC) += adc.o | 41 | obj-$(CONFIG_S3C24XX_ADC) += adc.o |
42 | obj-$(CONFIG_S3C2410_IOTIMING) += s3c2410-iotiming.o | ||
43 | obj-$(CONFIG_S3C2412_IOTIMING) += s3c2412-iotiming.o | ||
44 | obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += s3c2410-cpufreq-utils.o | ||
36 | 45 | ||
37 | # device specific setup and/or initialisation | 46 | # device specific setup and/or initialisation |
38 | obj-$(CONFIG_ARCH_S3C2410) += setup-i2c.o | 47 | obj-$(CONFIG_ARCH_S3C2410) += setup-i2c.o |
@@ -41,6 +50,7 @@ obj-$(CONFIG_ARCH_S3C2410) += setup-i2c.o | |||
41 | 50 | ||
42 | obj-$(CONFIG_S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13) += spi-bus0-gpe11_12_13.o | 51 | obj-$(CONFIG_S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13) += spi-bus0-gpe11_12_13.o |
43 | obj-$(CONFIG_S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7) += spi-bus1-gpg5_6_7.o | 52 | obj-$(CONFIG_S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7) += spi-bus1-gpg5_6_7.o |
53 | obj-$(CONFIG_S3C24XX_SPI_BUS1_GPD8_GPD9_GPD10) += spi-bus1-gpd8_9_10.o | ||
44 | 54 | ||
45 | # machine common support | 55 | # machine common support |
46 | 56 | ||
diff --git a/arch/arm/plat-s3c24xx/adc.c b/arch/arm/plat-s3c24xx/adc.c index ee1baf11ad9e..11117a7ba911 100644 --- a/arch/arm/plat-s3c24xx/adc.c +++ b/arch/arm/plat-s3c24xx/adc.c | |||
@@ -39,13 +39,16 @@ | |||
39 | struct s3c_adc_client { | 39 | struct s3c_adc_client { |
40 | struct platform_device *pdev; | 40 | struct platform_device *pdev; |
41 | struct list_head pend; | 41 | struct list_head pend; |
42 | wait_queue_head_t *wait; | ||
42 | 43 | ||
43 | unsigned int nr_samples; | 44 | unsigned int nr_samples; |
45 | int result; | ||
44 | unsigned char is_ts; | 46 | unsigned char is_ts; |
45 | unsigned char channel; | 47 | unsigned char channel; |
46 | 48 | ||
47 | void (*select_cb)(unsigned selected); | 49 | void (*select_cb)(struct s3c_adc_client *c, unsigned selected); |
48 | void (*convert_cb)(unsigned val1, unsigned val2, | 50 | void (*convert_cb)(struct s3c_adc_client *c, |
51 | unsigned val1, unsigned val2, | ||
49 | unsigned *samples_left); | 52 | unsigned *samples_left); |
50 | }; | 53 | }; |
51 | 54 | ||
@@ -81,7 +84,7 @@ static inline void s3c_adc_select(struct adc_device *adc, | |||
81 | { | 84 | { |
82 | unsigned con = readl(adc->regs + S3C2410_ADCCON); | 85 | unsigned con = readl(adc->regs + S3C2410_ADCCON); |
83 | 86 | ||
84 | client->select_cb(1); | 87 | client->select_cb(client, 1); |
85 | 88 | ||
86 | con &= ~S3C2410_ADCCON_MUXMASK; | 89 | con &= ~S3C2410_ADCCON_MUXMASK; |
87 | con &= ~S3C2410_ADCCON_STDBM; | 90 | con &= ~S3C2410_ADCCON_STDBM; |
@@ -153,25 +156,61 @@ int s3c_adc_start(struct s3c_adc_client *client, | |||
153 | } | 156 | } |
154 | EXPORT_SYMBOL_GPL(s3c_adc_start); | 157 | EXPORT_SYMBOL_GPL(s3c_adc_start); |
155 | 158 | ||
156 | static void s3c_adc_default_select(unsigned select) | 159 | static void s3c_convert_done(struct s3c_adc_client *client, |
160 | unsigned v, unsigned u, unsigned *left) | ||
161 | { | ||
162 | client->result = v; | ||
163 | wake_up(client->wait); | ||
164 | } | ||
165 | |||
166 | int s3c_adc_read(struct s3c_adc_client *client, unsigned int ch) | ||
167 | { | ||
168 | DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wake); | ||
169 | int ret; | ||
170 | |||
171 | client->convert_cb = s3c_convert_done; | ||
172 | client->wait = &wake; | ||
173 | client->result = -1; | ||
174 | |||
175 | ret = s3c_adc_start(client, ch, 1); | ||
176 | if (ret < 0) | ||
177 | goto err; | ||
178 | |||
179 | ret = wait_event_timeout(wake, client->result >= 0, HZ / 2); | ||
180 | if (client->result < 0) { | ||
181 | ret = -ETIMEDOUT; | ||
182 | goto err; | ||
183 | } | ||
184 | |||
185 | client->convert_cb = NULL; | ||
186 | return client->result; | ||
187 | |||
188 | err: | ||
189 | return ret; | ||
190 | } | ||
191 | EXPORT_SYMBOL_GPL(s3c_adc_convert); | ||
192 | |||
193 | static void s3c_adc_default_select(struct s3c_adc_client *client, | ||
194 | unsigned select) | ||
157 | { | 195 | { |
158 | } | 196 | } |
159 | 197 | ||
160 | struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev, | 198 | struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev, |
161 | void (*select)(unsigned int selected), | 199 | void (*select)(struct s3c_adc_client *client, |
162 | void (*conv)(unsigned d0, unsigned d1, | 200 | unsigned int selected), |
201 | void (*conv)(struct s3c_adc_client *client, | ||
202 | unsigned d0, unsigned d1, | ||
163 | unsigned *samples_left), | 203 | unsigned *samples_left), |
164 | unsigned int is_ts) | 204 | unsigned int is_ts) |
165 | { | 205 | { |
166 | struct s3c_adc_client *client; | 206 | struct s3c_adc_client *client; |
167 | 207 | ||
168 | WARN_ON(!pdev); | 208 | WARN_ON(!pdev); |
169 | WARN_ON(!conv); | ||
170 | 209 | ||
171 | if (!select) | 210 | if (!select) |
172 | select = s3c_adc_default_select; | 211 | select = s3c_adc_default_select; |
173 | 212 | ||
174 | if (!conv || !pdev) | 213 | if (!pdev) |
175 | return ERR_PTR(-EINVAL); | 214 | return ERR_PTR(-EINVAL); |
176 | 215 | ||
177 | client = kzalloc(sizeof(struct s3c_adc_client), GFP_KERNEL); | 216 | client = kzalloc(sizeof(struct s3c_adc_client), GFP_KERNEL); |
@@ -230,16 +269,19 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw) | |||
230 | adc_dbg(adc, "read %d: 0x%04x, 0x%04x\n", client->nr_samples, data0, data1); | 269 | adc_dbg(adc, "read %d: 0x%04x, 0x%04x\n", client->nr_samples, data0, data1); |
231 | 270 | ||
232 | client->nr_samples--; | 271 | client->nr_samples--; |
233 | (client->convert_cb)(data0 & 0x3ff, data1 & 0x3ff, &client->nr_samples); | 272 | |
273 | if (client->convert_cb) | ||
274 | (client->convert_cb)(client, data0 & 0x3ff, data1 & 0x3ff, | ||
275 | &client->nr_samples); | ||
234 | 276 | ||
235 | if (client->nr_samples > 0) { | 277 | if (client->nr_samples > 0) { |
236 | /* fire another conversion for this */ | 278 | /* fire another conversion for this */ |
237 | 279 | ||
238 | client->select_cb(1); | 280 | client->select_cb(client, 1); |
239 | s3c_adc_convert(adc); | 281 | s3c_adc_convert(adc); |
240 | } else { | 282 | } else { |
241 | local_irq_save(flags); | 283 | local_irq_save(flags); |
242 | (client->select_cb)(0); | 284 | (client->select_cb)(client, 0); |
243 | adc->cur = NULL; | 285 | adc->cur = NULL; |
244 | 286 | ||
245 | s3c_adc_try(adc); | 287 | s3c_adc_try(adc); |
diff --git a/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c b/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c new file mode 100644 index 000000000000..a9276667c2fb --- /dev/null +++ b/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c | |||
@@ -0,0 +1,199 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c | ||
2 | * | ||
3 | * Copyright (c) 2009 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C24XX CPU Frequency scaling - debugfs status support | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <linux/init.h> | ||
15 | #include <linux/module.h> | ||
16 | #include <linux/interrupt.h> | ||
17 | #include <linux/ioport.h> | ||
18 | #include <linux/cpufreq.h> | ||
19 | #include <linux/debugfs.h> | ||
20 | #include <linux/seq_file.h> | ||
21 | #include <linux/err.h> | ||
22 | |||
23 | #include <plat/cpu-freq-core.h> | ||
24 | |||
25 | static struct dentry *dbgfs_root; | ||
26 | static struct dentry *dbgfs_file_io; | ||
27 | static struct dentry *dbgfs_file_info; | ||
28 | static struct dentry *dbgfs_file_board; | ||
29 | |||
30 | #define print_ns(x) ((x) / 10), ((x) % 10) | ||
31 | |||
32 | static void show_max(struct seq_file *seq, struct s3c_freq *f) | ||
33 | { | ||
34 | seq_printf(seq, "MAX: F=%lu, H=%lu, P=%lu, A=%lu\n", | ||
35 | f->fclk, f->hclk, f->pclk, f->armclk); | ||
36 | } | ||
37 | |||
38 | static int board_show(struct seq_file *seq, void *p) | ||
39 | { | ||
40 | struct s3c_cpufreq_config *cfg; | ||
41 | struct s3c_cpufreq_board *brd; | ||
42 | |||
43 | cfg = s3c_cpufreq_getconfig(); | ||
44 | if (!cfg) { | ||
45 | seq_printf(seq, "no configuration registered\n"); | ||
46 | return 0; | ||
47 | } | ||
48 | |||
49 | brd = cfg->board; | ||
50 | if (!brd) { | ||
51 | seq_printf(seq, "no board definition set?\n"); | ||
52 | return 0; | ||
53 | } | ||
54 | |||
55 | seq_printf(seq, "SDRAM refresh %u ns\n", brd->refresh); | ||
56 | seq_printf(seq, "auto_io=%u\n", brd->auto_io); | ||
57 | seq_printf(seq, "need_io=%u\n", brd->need_io); | ||
58 | |||
59 | show_max(seq, &brd->max); | ||
60 | |||
61 | |||
62 | return 0; | ||
63 | } | ||
64 | |||
65 | static int fops_board_open(struct inode *inode, struct file *file) | ||
66 | { | ||
67 | return single_open(file, board_show, NULL); | ||
68 | } | ||
69 | |||
70 | static const struct file_operations fops_board = { | ||
71 | .open = fops_board_open, | ||
72 | .read = seq_read, | ||
73 | .llseek = seq_lseek, | ||
74 | .release = single_release, | ||
75 | .owner = THIS_MODULE, | ||
76 | }; | ||
77 | |||
78 | static int info_show(struct seq_file *seq, void *p) | ||
79 | { | ||
80 | struct s3c_cpufreq_config *cfg; | ||
81 | |||
82 | cfg = s3c_cpufreq_getconfig(); | ||
83 | if (!cfg) { | ||
84 | seq_printf(seq, "no configuration registered\n"); | ||
85 | return 0; | ||
86 | } | ||
87 | |||
88 | seq_printf(seq, " FCLK %ld Hz\n", cfg->freq.fclk); | ||
89 | seq_printf(seq, " HCLK %ld Hz (%lu.%lu ns)\n", | ||
90 | cfg->freq.hclk, print_ns(cfg->freq.hclk_tns)); | ||
91 | seq_printf(seq, " PCLK %ld Hz\n", cfg->freq.hclk); | ||
92 | seq_printf(seq, "ARMCLK %ld Hz\n", cfg->freq.armclk); | ||
93 | seq_printf(seq, "\n"); | ||
94 | |||
95 | show_max(seq, &cfg->max); | ||
96 | |||
97 | seq_printf(seq, "Divisors: P=%d, H=%d, A=%d, dvs=%s\n", | ||
98 | cfg->divs.h_divisor, cfg->divs.p_divisor, | ||
99 | cfg->divs.arm_divisor, cfg->divs.dvs ? "on" : "off"); | ||
100 | seq_printf(seq, "\n"); | ||
101 | |||
102 | seq_printf(seq, "lock_pll=%u\n", cfg->lock_pll); | ||
103 | |||
104 | return 0; | ||
105 | } | ||
106 | |||
107 | static int fops_info_open(struct inode *inode, struct file *file) | ||
108 | { | ||
109 | return single_open(file, info_show, NULL); | ||
110 | } | ||
111 | |||
112 | static const struct file_operations fops_info = { | ||
113 | .open = fops_info_open, | ||
114 | .read = seq_read, | ||
115 | .llseek = seq_lseek, | ||
116 | .release = single_release, | ||
117 | .owner = THIS_MODULE, | ||
118 | }; | ||
119 | |||
120 | static int io_show(struct seq_file *seq, void *p) | ||
121 | { | ||
122 | void (*show_bank)(struct seq_file *, struct s3c_cpufreq_config *, union s3c_iobank *); | ||
123 | struct s3c_cpufreq_config *cfg; | ||
124 | struct s3c_iotimings *iot; | ||
125 | union s3c_iobank *iob; | ||
126 | int bank; | ||
127 | |||
128 | cfg = s3c_cpufreq_getconfig(); | ||
129 | if (!cfg) { | ||
130 | seq_printf(seq, "no configuration registered\n"); | ||
131 | return 0; | ||
132 | } | ||
133 | |||
134 | show_bank = cfg->info->debug_io_show; | ||
135 | if (!show_bank) { | ||
136 | seq_printf(seq, "no code to show bank timing\n"); | ||
137 | return 0; | ||
138 | } | ||
139 | |||
140 | iot = s3c_cpufreq_getiotimings(); | ||
141 | if (!iot) { | ||
142 | seq_printf(seq, "no io timings registered\n"); | ||
143 | return 0; | ||
144 | } | ||
145 | |||
146 | seq_printf(seq, "hclk period is %lu.%lu ns\n", print_ns(cfg->freq.hclk_tns)); | ||
147 | |||
148 | for (bank = 0; bank < MAX_BANKS; bank++) { | ||
149 | iob = &iot->bank[bank]; | ||
150 | |||
151 | seq_printf(seq, "bank %d: ", bank); | ||
152 | |||
153 | if (!iob->io_2410) { | ||
154 | seq_printf(seq, "nothing set\n"); | ||
155 | continue; | ||
156 | } | ||
157 | |||
158 | show_bank(seq, cfg, iob); | ||
159 | } | ||
160 | |||
161 | return 0; | ||
162 | } | ||
163 | |||
164 | static int fops_io_open(struct inode *inode, struct file *file) | ||
165 | { | ||
166 | return single_open(file, io_show, NULL); | ||
167 | } | ||
168 | |||
169 | static const struct file_operations fops_io = { | ||
170 | .open = fops_io_open, | ||
171 | .read = seq_read, | ||
172 | .llseek = seq_lseek, | ||
173 | .release = single_release, | ||
174 | .owner = THIS_MODULE, | ||
175 | }; | ||
176 | |||
177 | |||
178 | static int __init s3c_freq_debugfs_init(void) | ||
179 | { | ||
180 | dbgfs_root = debugfs_create_dir("s3c-cpufreq", NULL); | ||
181 | if (IS_ERR(dbgfs_root)) { | ||
182 | printk(KERN_ERR "%s: error creating debugfs root\n", __func__); | ||
183 | return PTR_ERR(dbgfs_root); | ||
184 | } | ||
185 | |||
186 | dbgfs_file_io = debugfs_create_file("io-timing", S_IRUGO, dbgfs_root, | ||
187 | NULL, &fops_io); | ||
188 | |||
189 | dbgfs_file_info = debugfs_create_file("info", S_IRUGO, dbgfs_root, | ||
190 | NULL, &fops_info); | ||
191 | |||
192 | dbgfs_file_board = debugfs_create_file("board", S_IRUGO, dbgfs_root, | ||
193 | NULL, &fops_board); | ||
194 | |||
195 | return 0; | ||
196 | } | ||
197 | |||
198 | late_initcall(s3c_freq_debugfs_init); | ||
199 | |||
diff --git a/arch/arm/plat-s3c24xx/cpu-freq.c b/arch/arm/plat-s3c24xx/cpu-freq.c new file mode 100644 index 000000000000..4f1b789a1173 --- /dev/null +++ b/arch/arm/plat-s3c24xx/cpu-freq.c | |||
@@ -0,0 +1,716 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/cpu-freq.c | ||
2 | * | ||
3 | * Copyright (c) 2006,2007,2008 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C24XX CPU Frequency scaling | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <linux/init.h> | ||
15 | #include <linux/module.h> | ||
16 | #include <linux/interrupt.h> | ||
17 | #include <linux/ioport.h> | ||
18 | #include <linux/cpufreq.h> | ||
19 | #include <linux/cpu.h> | ||
20 | #include <linux/clk.h> | ||
21 | #include <linux/err.h> | ||
22 | #include <linux/io.h> | ||
23 | #include <linux/sysdev.h> | ||
24 | #include <linux/kobject.h> | ||
25 | #include <linux/sysfs.h> | ||
26 | |||
27 | #include <asm/mach/arch.h> | ||
28 | #include <asm/mach/map.h> | ||
29 | |||
30 | #include <plat/cpu.h> | ||
31 | #include <plat/clock.h> | ||
32 | #include <plat/cpu-freq-core.h> | ||
33 | |||
34 | #include <mach/regs-clock.h> | ||
35 | |||
36 | /* note, cpufreq support deals in kHz, no Hz */ | ||
37 | |||
38 | static struct cpufreq_driver s3c24xx_driver; | ||
39 | static struct s3c_cpufreq_config cpu_cur; | ||
40 | static struct s3c_iotimings s3c24xx_iotiming; | ||
41 | static struct cpufreq_frequency_table *pll_reg; | ||
42 | static unsigned int last_target = ~0; | ||
43 | static unsigned int ftab_size; | ||
44 | static struct cpufreq_frequency_table *ftab; | ||
45 | |||
46 | static struct clk *_clk_mpll; | ||
47 | static struct clk *_clk_xtal; | ||
48 | static struct clk *clk_fclk; | ||
49 | static struct clk *clk_hclk; | ||
50 | static struct clk *clk_pclk; | ||
51 | static struct clk *clk_arm; | ||
52 | |||
53 | #ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS | ||
54 | struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void) | ||
55 | { | ||
56 | return &cpu_cur; | ||
57 | } | ||
58 | |||
59 | struct s3c_iotimings *s3c_cpufreq_getiotimings(void) | ||
60 | { | ||
61 | return &s3c24xx_iotiming; | ||
62 | } | ||
63 | #endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUGFS */ | ||
64 | |||
65 | static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg) | ||
66 | { | ||
67 | unsigned long fclk, pclk, hclk, armclk; | ||
68 | |||
69 | cfg->freq.fclk = fclk = clk_get_rate(clk_fclk); | ||
70 | cfg->freq.hclk = hclk = clk_get_rate(clk_hclk); | ||
71 | cfg->freq.pclk = pclk = clk_get_rate(clk_pclk); | ||
72 | cfg->freq.armclk = armclk = clk_get_rate(clk_arm); | ||
73 | |||
74 | cfg->pll.index = __raw_readl(S3C2410_MPLLCON); | ||
75 | cfg->pll.frequency = fclk; | ||
76 | |||
77 | cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10); | ||
78 | |||
79 | cfg->divs.h_divisor = fclk / hclk; | ||
80 | cfg->divs.p_divisor = fclk / pclk; | ||
81 | } | ||
82 | |||
83 | static inline void s3c_cpufreq_calc(struct s3c_cpufreq_config *cfg) | ||
84 | { | ||
85 | unsigned long pll = cfg->pll.frequency; | ||
86 | |||
87 | cfg->freq.fclk = pll; | ||
88 | cfg->freq.hclk = pll / cfg->divs.h_divisor; | ||
89 | cfg->freq.pclk = pll / cfg->divs.p_divisor; | ||
90 | |||
91 | /* convert hclk into 10ths of nanoseconds for io calcs */ | ||
92 | cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10); | ||
93 | } | ||
94 | |||
95 | static inline int closer(unsigned int target, unsigned int n, unsigned int c) | ||
96 | { | ||
97 | int diff_cur = abs(target - c); | ||
98 | int diff_new = abs(target - n); | ||
99 | |||
100 | return (diff_new < diff_cur); | ||
101 | } | ||
102 | |||
103 | static void s3c_cpufreq_show(const char *pfx, | ||
104 | struct s3c_cpufreq_config *cfg) | ||
105 | { | ||
106 | s3c_freq_dbg("%s: Fvco=%u, F=%lu, A=%lu, H=%lu (%u), P=%lu (%u)\n", | ||
107 | pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk, | ||
108 | cfg->freq.hclk, cfg->divs.h_divisor, | ||
109 | cfg->freq.pclk, cfg->divs.p_divisor); | ||
110 | } | ||
111 | |||
112 | /* functions to wrapper the driver info calls to do the cpu specific work */ | ||
113 | |||
114 | static void s3c_cpufreq_setio(struct s3c_cpufreq_config *cfg) | ||
115 | { | ||
116 | if (cfg->info->set_iotiming) | ||
117 | (cfg->info->set_iotiming)(cfg, &s3c24xx_iotiming); | ||
118 | } | ||
119 | |||
120 | static int s3c_cpufreq_calcio(struct s3c_cpufreq_config *cfg) | ||
121 | { | ||
122 | if (cfg->info->calc_iotiming) | ||
123 | return (cfg->info->calc_iotiming)(cfg, &s3c24xx_iotiming); | ||
124 | |||
125 | return 0; | ||
126 | } | ||
127 | |||
128 | static void s3c_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg) | ||
129 | { | ||
130 | (cfg->info->set_refresh)(cfg); | ||
131 | } | ||
132 | |||
133 | static void s3c_cpufreq_setdivs(struct s3c_cpufreq_config *cfg) | ||
134 | { | ||
135 | (cfg->info->set_divs)(cfg); | ||
136 | } | ||
137 | |||
138 | static int s3c_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) | ||
139 | { | ||
140 | return (cfg->info->calc_divs)(cfg); | ||
141 | } | ||
142 | |||
143 | static void s3c_cpufreq_setfvco(struct s3c_cpufreq_config *cfg) | ||
144 | { | ||
145 | (cfg->info->set_fvco)(cfg); | ||
146 | } | ||
147 | |||
148 | static inline void s3c_cpufreq_resume_clocks(void) | ||
149 | { | ||
150 | cpu_cur.info->resume_clocks(); | ||
151 | } | ||
152 | |||
153 | static inline void s3c_cpufreq_updateclk(struct clk *clk, | ||
154 | unsigned int freq) | ||
155 | { | ||
156 | clk_set_rate(clk, freq); | ||
157 | } | ||
158 | |||
159 | static int s3c_cpufreq_settarget(struct cpufreq_policy *policy, | ||
160 | unsigned int target_freq, | ||
161 | struct cpufreq_frequency_table *pll) | ||
162 | { | ||
163 | struct s3c_cpufreq_freqs freqs; | ||
164 | struct s3c_cpufreq_config cpu_new; | ||
165 | unsigned long flags; | ||
166 | |||
167 | cpu_new = cpu_cur; /* copy new from current */ | ||
168 | |||
169 | s3c_cpufreq_show("cur", &cpu_cur); | ||
170 | |||
171 | /* TODO - check for DMA currently outstanding */ | ||
172 | |||
173 | cpu_new.pll = pll ? *pll : cpu_cur.pll; | ||
174 | |||
175 | if (pll) | ||
176 | freqs.pll_changing = 1; | ||
177 | |||
178 | /* update our frequencies */ | ||
179 | |||
180 | cpu_new.freq.armclk = target_freq; | ||
181 | cpu_new.freq.fclk = cpu_new.pll.frequency; | ||
182 | |||
183 | if (s3c_cpufreq_calcdivs(&cpu_new) < 0) { | ||
184 | printk(KERN_ERR "no divisors for %d\n", target_freq); | ||
185 | goto err_notpossible; | ||
186 | } | ||
187 | |||
188 | s3c_freq_dbg("%s: got divs\n", __func__); | ||
189 | |||
190 | s3c_cpufreq_calc(&cpu_new); | ||
191 | |||
192 | s3c_freq_dbg("%s: calculated frequencies for new\n", __func__); | ||
193 | |||
194 | if (cpu_new.freq.hclk != cpu_cur.freq.hclk) { | ||
195 | if (s3c_cpufreq_calcio(&cpu_new) < 0) { | ||
196 | printk(KERN_ERR "%s: no IO timings\n", __func__); | ||
197 | goto err_notpossible; | ||
198 | } | ||
199 | } | ||
200 | |||
201 | s3c_cpufreq_show("new", &cpu_new); | ||
202 | |||
203 | /* setup our cpufreq parameters */ | ||
204 | |||
205 | freqs.old = cpu_cur.freq; | ||
206 | freqs.new = cpu_new.freq; | ||
207 | |||
208 | freqs.freqs.cpu = 0; | ||
209 | freqs.freqs.old = cpu_cur.freq.armclk / 1000; | ||
210 | freqs.freqs.new = cpu_new.freq.armclk / 1000; | ||
211 | |||
212 | /* update f/h/p clock settings before we issue the change | ||
213 | * notification, so that drivers do not need to do anything | ||
214 | * special if they want to recalculate on CPUFREQ_PRECHANGE. */ | ||
215 | |||
216 | s3c_cpufreq_updateclk(_clk_mpll, cpu_new.pll.frequency); | ||
217 | s3c_cpufreq_updateclk(clk_fclk, cpu_new.freq.fclk); | ||
218 | s3c_cpufreq_updateclk(clk_hclk, cpu_new.freq.hclk); | ||
219 | s3c_cpufreq_updateclk(clk_pclk, cpu_new.freq.pclk); | ||
220 | |||
221 | /* start the frequency change */ | ||
222 | |||
223 | if (policy) | ||
224 | cpufreq_notify_transition(&freqs.freqs, CPUFREQ_PRECHANGE); | ||
225 | |||
226 | /* If hclk is staying the same, then we do not need to | ||
227 | * re-write the IO or the refresh timings whilst we are changing | ||
228 | * speed. */ | ||
229 | |||
230 | local_irq_save(flags); | ||
231 | |||
232 | /* is our memory clock slowing down? */ | ||
233 | if (cpu_new.freq.hclk < cpu_cur.freq.hclk) { | ||
234 | s3c_cpufreq_setrefresh(&cpu_new); | ||
235 | s3c_cpufreq_setio(&cpu_new); | ||
236 | } | ||
237 | |||
238 | if (cpu_new.freq.fclk == cpu_cur.freq.fclk) { | ||
239 | /* not changing PLL, just set the divisors */ | ||
240 | |||
241 | s3c_cpufreq_setdivs(&cpu_new); | ||
242 | } else { | ||
243 | if (cpu_new.freq.fclk < cpu_cur.freq.fclk) { | ||
244 | /* slow the cpu down, then set divisors */ | ||
245 | |||
246 | s3c_cpufreq_setfvco(&cpu_new); | ||
247 | s3c_cpufreq_setdivs(&cpu_new); | ||
248 | } else { | ||
249 | /* set the divisors, then speed up */ | ||
250 | |||
251 | s3c_cpufreq_setdivs(&cpu_new); | ||
252 | s3c_cpufreq_setfvco(&cpu_new); | ||
253 | } | ||
254 | } | ||
255 | |||
256 | /* did our memory clock speed up */ | ||
257 | if (cpu_new.freq.hclk > cpu_cur.freq.hclk) { | ||
258 | s3c_cpufreq_setrefresh(&cpu_new); | ||
259 | s3c_cpufreq_setio(&cpu_new); | ||
260 | } | ||
261 | |||
262 | /* update our current settings */ | ||
263 | cpu_cur = cpu_new; | ||
264 | |||
265 | local_irq_restore(flags); | ||
266 | |||
267 | /* notify everyone we've done this */ | ||
268 | if (policy) | ||
269 | cpufreq_notify_transition(&freqs.freqs, CPUFREQ_POSTCHANGE); | ||
270 | |||
271 | s3c_freq_dbg("%s: finished\n", __func__); | ||
272 | return 0; | ||
273 | |||
274 | err_notpossible: | ||
275 | printk(KERN_ERR "no compatible settings for %d\n", target_freq); | ||
276 | return -EINVAL; | ||
277 | } | ||
278 | |||
279 | /* s3c_cpufreq_target | ||
280 | * | ||
281 | * called by the cpufreq core to adjust the frequency that the CPU | ||
282 | * is currently running at. | ||
283 | */ | ||
284 | |||
285 | static int s3c_cpufreq_target(struct cpufreq_policy *policy, | ||
286 | unsigned int target_freq, | ||
287 | unsigned int relation) | ||
288 | { | ||
289 | struct cpufreq_frequency_table *pll; | ||
290 | unsigned int index; | ||
291 | |||
292 | /* avoid repeated calls which cause a needless amout of duplicated | ||
293 | * logging output (and CPU time as the calculation process is | ||
294 | * done) */ | ||
295 | if (target_freq == last_target) | ||
296 | return 0; | ||
297 | |||
298 | last_target = target_freq; | ||
299 | |||
300 | s3c_freq_dbg("%s: policy %p, target %u, relation %u\n", | ||
301 | __func__, policy, target_freq, relation); | ||
302 | |||
303 | if (ftab) { | ||
304 | if (cpufreq_frequency_table_target(policy, ftab, | ||
305 | target_freq, relation, | ||
306 | &index)) { | ||
307 | s3c_freq_dbg("%s: table failed\n", __func__); | ||
308 | return -EINVAL; | ||
309 | } | ||
310 | |||
311 | s3c_freq_dbg("%s: adjust %d to entry %d (%u)\n", __func__, | ||
312 | target_freq, index, ftab[index].frequency); | ||
313 | target_freq = ftab[index].frequency; | ||
314 | } | ||
315 | |||
316 | target_freq *= 1000; /* convert target to Hz */ | ||
317 | |||
318 | /* find the settings for our new frequency */ | ||
319 | |||
320 | if (!pll_reg || cpu_cur.lock_pll) { | ||
321 | /* either we've not got any PLL values, or we've locked | ||
322 | * to the current one. */ | ||
323 | pll = NULL; | ||
324 | } else { | ||
325 | struct cpufreq_policy tmp_policy; | ||
326 | int ret; | ||
327 | |||
328 | /* we keep the cpu pll table in Hz, to ensure we get an | ||
329 | * accurate value for the PLL output. */ | ||
330 | |||
331 | tmp_policy.min = policy->min * 1000; | ||
332 | tmp_policy.max = policy->max * 1000; | ||
333 | tmp_policy.cpu = policy->cpu; | ||
334 | |||
335 | /* cpufreq_frequency_table_target uses a pointer to 'index' | ||
336 | * which is the number of the table entry, not the value of | ||
337 | * the table entry's index field. */ | ||
338 | |||
339 | ret = cpufreq_frequency_table_target(&tmp_policy, pll_reg, | ||
340 | target_freq, relation, | ||
341 | &index); | ||
342 | |||
343 | if (ret < 0) { | ||
344 | printk(KERN_ERR "%s: no PLL available\n", __func__); | ||
345 | goto err_notpossible; | ||
346 | } | ||
347 | |||
348 | pll = pll_reg + index; | ||
349 | |||
350 | s3c_freq_dbg("%s: target %u => %u\n", | ||
351 | __func__, target_freq, pll->frequency); | ||
352 | |||
353 | target_freq = pll->frequency; | ||
354 | } | ||
355 | |||
356 | return s3c_cpufreq_settarget(policy, target_freq, pll); | ||
357 | |||
358 | err_notpossible: | ||
359 | printk(KERN_ERR "no compatible settings for %d\n", target_freq); | ||
360 | return -EINVAL; | ||
361 | } | ||
362 | |||
363 | static unsigned int s3c_cpufreq_get(unsigned int cpu) | ||
364 | { | ||
365 | return clk_get_rate(clk_arm) / 1000; | ||
366 | } | ||
367 | |||
368 | struct clk *s3c_cpufreq_clk_get(struct device *dev, const char *name) | ||
369 | { | ||
370 | struct clk *clk; | ||
371 | |||
372 | clk = clk_get(dev, name); | ||
373 | if (IS_ERR(clk)) | ||
374 | printk(KERN_ERR "cpufreq: failed to get clock '%s'\n", name); | ||
375 | |||
376 | return clk; | ||
377 | } | ||
378 | |||
379 | static int s3c_cpufreq_init(struct cpufreq_policy *policy) | ||
380 | { | ||
381 | printk(KERN_INFO "%s: initialising policy %p\n", __func__, policy); | ||
382 | |||
383 | if (policy->cpu != 0) | ||
384 | return -EINVAL; | ||
385 | |||
386 | policy->cur = s3c_cpufreq_get(0); | ||
387 | policy->min = policy->cpuinfo.min_freq = 0; | ||
388 | policy->max = policy->cpuinfo.max_freq = cpu_cur.info->max.fclk / 1000; | ||
389 | policy->governor = CPUFREQ_DEFAULT_GOVERNOR; | ||
390 | |||
391 | /* feed the latency information from the cpu driver */ | ||
392 | policy->cpuinfo.transition_latency = cpu_cur.info->latency; | ||
393 | |||
394 | if (ftab) | ||
395 | cpufreq_frequency_table_cpuinfo(policy, ftab); | ||
396 | |||
397 | return 0; | ||
398 | } | ||
399 | |||
400 | static __init int s3c_cpufreq_initclks(void) | ||
401 | { | ||
402 | _clk_mpll = s3c_cpufreq_clk_get(NULL, "mpll"); | ||
403 | _clk_xtal = s3c_cpufreq_clk_get(NULL, "xtal"); | ||
404 | clk_fclk = s3c_cpufreq_clk_get(NULL, "fclk"); | ||
405 | clk_hclk = s3c_cpufreq_clk_get(NULL, "hclk"); | ||
406 | clk_pclk = s3c_cpufreq_clk_get(NULL, "pclk"); | ||
407 | clk_arm = s3c_cpufreq_clk_get(NULL, "armclk"); | ||
408 | |||
409 | if (IS_ERR(clk_fclk) || IS_ERR(clk_hclk) || IS_ERR(clk_pclk) || | ||
410 | IS_ERR(_clk_mpll) || IS_ERR(clk_arm) || IS_ERR(_clk_xtal)) { | ||
411 | printk(KERN_ERR "%s: could not get clock(s)\n", __func__); | ||
412 | return -ENOENT; | ||
413 | } | ||
414 | |||
415 | printk(KERN_INFO "%s: clocks f=%lu,h=%lu,p=%lu,a=%lu\n", __func__, | ||
416 | clk_get_rate(clk_fclk) / 1000, | ||
417 | clk_get_rate(clk_hclk) / 1000, | ||
418 | clk_get_rate(clk_pclk) / 1000, | ||
419 | clk_get_rate(clk_arm) / 1000); | ||
420 | |||
421 | return 0; | ||
422 | } | ||
423 | |||
424 | static int s3c_cpufreq_verify(struct cpufreq_policy *policy) | ||
425 | { | ||
426 | if (policy->cpu != 0) | ||
427 | return -EINVAL; | ||
428 | |||
429 | return 0; | ||
430 | } | ||
431 | |||
432 | #ifdef CONFIG_PM | ||
433 | static struct cpufreq_frequency_table suspend_pll; | ||
434 | static unsigned int suspend_freq; | ||
435 | |||
436 | static int s3c_cpufreq_suspend(struct cpufreq_policy *policy, pm_message_t pmsg) | ||
437 | { | ||
438 | suspend_pll.frequency = clk_get_rate(_clk_mpll); | ||
439 | suspend_pll.index = __raw_readl(S3C2410_MPLLCON); | ||
440 | suspend_freq = s3c_cpufreq_get(0) * 1000; | ||
441 | |||
442 | return 0; | ||
443 | } | ||
444 | |||
445 | static int s3c_cpufreq_resume(struct cpufreq_policy *policy) | ||
446 | { | ||
447 | int ret; | ||
448 | |||
449 | s3c_freq_dbg("%s: resuming with policy %p\n", __func__, policy); | ||
450 | |||
451 | last_target = ~0; /* invalidate last_target setting */ | ||
452 | |||
453 | /* first, find out what speed we resumed at. */ | ||
454 | s3c_cpufreq_resume_clocks(); | ||
455 | |||
456 | /* whilst we will be called later on, we try and re-set the | ||
457 | * cpu frequencies as soon as possible so that we do not end | ||
458 | * up resuming devices and then immediatley having to re-set | ||
459 | * a number of settings once these devices have restarted. | ||
460 | * | ||
461 | * as a note, it is expected devices are not used until they | ||
462 | * have been un-suspended and at that time they should have | ||
463 | * used the updated clock settings. | ||
464 | */ | ||
465 | |||
466 | ret = s3c_cpufreq_settarget(NULL, suspend_freq, &suspend_pll); | ||
467 | if (ret) { | ||
468 | printk(KERN_ERR "%s: failed to reset pll/freq\n", __func__); | ||
469 | return ret; | ||
470 | } | ||
471 | |||
472 | return 0; | ||
473 | } | ||
474 | #else | ||
475 | #define s3c_cpufreq_resume NULL | ||
476 | #define s3c_cpufreq_suspend NULL | ||
477 | #endif | ||
478 | |||
479 | static struct cpufreq_driver s3c24xx_driver = { | ||
480 | .flags = CPUFREQ_STICKY, | ||
481 | .verify = s3c_cpufreq_verify, | ||
482 | .target = s3c_cpufreq_target, | ||
483 | .get = s3c_cpufreq_get, | ||
484 | .init = s3c_cpufreq_init, | ||
485 | .suspend = s3c_cpufreq_suspend, | ||
486 | .resume = s3c_cpufreq_resume, | ||
487 | .name = "s3c24xx", | ||
488 | }; | ||
489 | |||
490 | |||
491 | int __init s3c_cpufreq_register(struct s3c_cpufreq_info *info) | ||
492 | { | ||
493 | if (!info || !info->name) { | ||
494 | printk(KERN_ERR "%s: failed to pass valid information\n", | ||
495 | __func__); | ||
496 | return -EINVAL; | ||
497 | } | ||
498 | |||
499 | printk(KERN_INFO "S3C24XX CPU Frequency driver, %s cpu support\n", | ||
500 | info->name); | ||
501 | |||
502 | /* check our driver info has valid data */ | ||
503 | |||
504 | BUG_ON(info->set_refresh == NULL); | ||
505 | BUG_ON(info->set_divs == NULL); | ||
506 | BUG_ON(info->calc_divs == NULL); | ||
507 | |||
508 | /* info->set_fvco is optional, depending on whether there | ||
509 | * is a need to set the clock code. */ | ||
510 | |||
511 | cpu_cur.info = info; | ||
512 | |||
513 | /* Note, driver registering should probably update locktime */ | ||
514 | |||
515 | return 0; | ||
516 | } | ||
517 | |||
518 | int __init s3c_cpufreq_setboard(struct s3c_cpufreq_board *board) | ||
519 | { | ||
520 | struct s3c_cpufreq_board *ours; | ||
521 | |||
522 | if (!board) { | ||
523 | printk(KERN_INFO "%s: no board data\n", __func__); | ||
524 | return -EINVAL; | ||
525 | } | ||
526 | |||
527 | /* Copy the board information so that each board can make this | ||
528 | * initdata. */ | ||
529 | |||
530 | ours = kzalloc(sizeof(struct s3c_cpufreq_board), GFP_KERNEL); | ||
531 | if (ours == NULL) { | ||
532 | printk(KERN_ERR "%s: no memory\n", __func__); | ||
533 | return -ENOMEM; | ||
534 | } | ||
535 | |||
536 | *ours = *board; | ||
537 | cpu_cur.board = ours; | ||
538 | |||
539 | return 0; | ||
540 | } | ||
541 | |||
542 | int __init s3c_cpufreq_auto_io(void) | ||
543 | { | ||
544 | int ret; | ||
545 | |||
546 | if (!cpu_cur.info->get_iotiming) { | ||
547 | printk(KERN_ERR "%s: get_iotiming undefined\n", __func__); | ||
548 | return -ENOENT; | ||
549 | } | ||
550 | |||
551 | printk(KERN_INFO "%s: working out IO settings\n", __func__); | ||
552 | |||
553 | ret = (cpu_cur.info->get_iotiming)(&cpu_cur, &s3c24xx_iotiming); | ||
554 | if (ret) | ||
555 | printk(KERN_ERR "%s: failed to get timings\n", __func__); | ||
556 | |||
557 | return ret; | ||
558 | } | ||
559 | |||
560 | /* if one or is zero, then return the other, otherwise return the min */ | ||
561 | #define do_min(_a, _b) ((_a) == 0 ? (_b) : (_b) == 0 ? (_a) : min(_a, _b)) | ||
562 | |||
563 | /** | ||
564 | * s3c_cpufreq_freq_min - find the minimum settings for the given freq. | ||
565 | * @dst: The destination structure | ||
566 | * @a: One argument. | ||
567 | * @b: The other argument. | ||
568 | * | ||
569 | * Create a minimum of each frequency entry in the 'struct s3c_freq', | ||
570 | * unless the entry is zero when it is ignored and the non-zero argument | ||
571 | * used. | ||
572 | */ | ||
573 | static void s3c_cpufreq_freq_min(struct s3c_freq *dst, | ||
574 | struct s3c_freq *a, struct s3c_freq *b) | ||
575 | { | ||
576 | dst->fclk = do_min(a->fclk, b->fclk); | ||
577 | dst->hclk = do_min(a->hclk, b->hclk); | ||
578 | dst->pclk = do_min(a->pclk, b->pclk); | ||
579 | dst->armclk = do_min(a->armclk, b->armclk); | ||
580 | } | ||
581 | |||
582 | static inline u32 calc_locktime(u32 freq, u32 time_us) | ||
583 | { | ||
584 | u32 result; | ||
585 | |||
586 | result = freq * time_us; | ||
587 | result = DIV_ROUND_UP(result, 1000 * 1000); | ||
588 | |||
589 | return result; | ||
590 | } | ||
591 | |||
592 | static void s3c_cpufreq_update_loctkime(void) | ||
593 | { | ||
594 | unsigned int bits = cpu_cur.info->locktime_bits; | ||
595 | u32 rate = (u32)clk_get_rate(_clk_xtal); | ||
596 | u32 val; | ||
597 | |||
598 | if (bits == 0) { | ||
599 | WARN_ON(1); | ||
600 | return; | ||
601 | } | ||
602 | |||
603 | val = calc_locktime(rate, cpu_cur.info->locktime_u) << bits; | ||
604 | val |= calc_locktime(rate, cpu_cur.info->locktime_m); | ||
605 | |||
606 | printk(KERN_INFO "%s: new locktime is 0x%08x\n", __func__, val); | ||
607 | __raw_writel(val, S3C2410_LOCKTIME); | ||
608 | } | ||
609 | |||
610 | static int s3c_cpufreq_build_freq(void) | ||
611 | { | ||
612 | int size, ret; | ||
613 | |||
614 | if (!cpu_cur.info->calc_freqtable) | ||
615 | return -EINVAL; | ||
616 | |||
617 | kfree(ftab); | ||
618 | ftab = NULL; | ||
619 | |||
620 | size = cpu_cur.info->calc_freqtable(&cpu_cur, NULL, 0); | ||
621 | size++; | ||
622 | |||
623 | ftab = kmalloc(sizeof(struct cpufreq_frequency_table) * size, GFP_KERNEL); | ||
624 | if (!ftab) { | ||
625 | printk(KERN_ERR "%s: no memory for tables\n", __func__); | ||
626 | return -ENOMEM; | ||
627 | } | ||
628 | |||
629 | ftab_size = size; | ||
630 | |||
631 | ret = cpu_cur.info->calc_freqtable(&cpu_cur, ftab, size); | ||
632 | s3c_cpufreq_addfreq(ftab, ret, size, CPUFREQ_TABLE_END); | ||
633 | |||
634 | return 0; | ||
635 | } | ||
636 | |||
637 | static int __init s3c_cpufreq_initcall(void) | ||
638 | { | ||
639 | int ret = 0; | ||
640 | |||
641 | if (cpu_cur.info && cpu_cur.board) { | ||
642 | ret = s3c_cpufreq_initclks(); | ||
643 | if (ret) | ||
644 | goto out; | ||
645 | |||
646 | /* get current settings */ | ||
647 | s3c_cpufreq_getcur(&cpu_cur); | ||
648 | s3c_cpufreq_show("cur", &cpu_cur); | ||
649 | |||
650 | if (cpu_cur.board->auto_io) { | ||
651 | ret = s3c_cpufreq_auto_io(); | ||
652 | if (ret) { | ||
653 | printk(KERN_ERR "%s: failed to get io timing\n", | ||
654 | __func__); | ||
655 | goto out; | ||
656 | } | ||
657 | } | ||
658 | |||
659 | if (cpu_cur.board->need_io && !cpu_cur.info->set_iotiming) { | ||
660 | printk(KERN_ERR "%s: no IO support registered\n", | ||
661 | __func__); | ||
662 | ret = -EINVAL; | ||
663 | goto out; | ||
664 | } | ||
665 | |||
666 | if (!cpu_cur.info->need_pll) | ||
667 | cpu_cur.lock_pll = 1; | ||
668 | |||
669 | s3c_cpufreq_update_loctkime(); | ||
670 | |||
671 | s3c_cpufreq_freq_min(&cpu_cur.max, &cpu_cur.board->max, | ||
672 | &cpu_cur.info->max); | ||
673 | |||
674 | if (cpu_cur.info->calc_freqtable) | ||
675 | s3c_cpufreq_build_freq(); | ||
676 | |||
677 | ret = cpufreq_register_driver(&s3c24xx_driver); | ||
678 | } | ||
679 | |||
680 | out: | ||
681 | return ret; | ||
682 | } | ||
683 | |||
684 | late_initcall(s3c_cpufreq_initcall); | ||
685 | |||
686 | /** | ||
687 | * s3c_plltab_register - register CPU PLL table. | ||
688 | * @plls: The list of PLL entries. | ||
689 | * @plls_no: The size of the PLL entries @plls. | ||
690 | * | ||
691 | * Register the given set of PLLs with the system. | ||
692 | */ | ||
693 | int __init s3c_plltab_register(struct cpufreq_frequency_table *plls, | ||
694 | unsigned int plls_no) | ||
695 | { | ||
696 | struct cpufreq_frequency_table *vals; | ||
697 | unsigned int size; | ||
698 | |||
699 | size = sizeof(struct cpufreq_frequency_table) * (plls_no + 1); | ||
700 | |||
701 | vals = kmalloc(size, GFP_KERNEL); | ||
702 | if (vals) { | ||
703 | memcpy(vals, plls, size); | ||
704 | pll_reg = vals; | ||
705 | |||
706 | /* write a terminating entry, we don't store it in the | ||
707 | * table that is stored in the kernel */ | ||
708 | vals += plls_no; | ||
709 | vals->frequency = CPUFREQ_TABLE_END; | ||
710 | |||
711 | printk(KERN_INFO "cpufreq: %d PLL entries\n", plls_no); | ||
712 | } else | ||
713 | printk(KERN_ERR "cpufreq: no memory for PLL tables\n"); | ||
714 | |||
715 | return vals ? 0 : -ENOMEM; | ||
716 | } | ||
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c index 1932b7e0da15..5447e60f3936 100644 --- a/arch/arm/plat-s3c24xx/cpu.c +++ b/arch/arm/plat-s3c24xx/cpu.c | |||
@@ -81,7 +81,7 @@ static struct cpu_table cpu_ids[] __initdata = { | |||
81 | .map_io = s3c2410_map_io, | 81 | .map_io = s3c2410_map_io, |
82 | .init_clocks = s3c2410_init_clocks, | 82 | .init_clocks = s3c2410_init_clocks, |
83 | .init_uarts = s3c2410_init_uarts, | 83 | .init_uarts = s3c2410_init_uarts, |
84 | .init = s3c2410_init, | 84 | .init = s3c2410a_init, |
85 | .name = name_s3c2410a | 85 | .name = name_s3c2410a |
86 | }, | 86 | }, |
87 | { | 87 | { |
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c index 4eb378c89a39..f52a92ce8dda 100644 --- a/arch/arm/plat-s3c24xx/devs.c +++ b/arch/arm/plat-s3c24xx/devs.c | |||
@@ -26,6 +26,8 @@ | |||
26 | #include <asm/mach/irq.h> | 26 | #include <asm/mach/irq.h> |
27 | #include <mach/fb.h> | 27 | #include <mach/fb.h> |
28 | #include <mach/hardware.h> | 28 | #include <mach/hardware.h> |
29 | #include <mach/dma.h> | ||
30 | #include <mach/irqs.h> | ||
29 | #include <asm/irq.h> | 31 | #include <asm/irq.h> |
30 | 32 | ||
31 | #include <plat/regs-serial.h> | 33 | #include <plat/regs-serial.h> |
@@ -180,25 +182,6 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd) | |||
180 | } | 182 | } |
181 | } | 183 | } |
182 | 184 | ||
183 | /* NAND Controller */ | ||
184 | |||
185 | static struct resource s3c_nand_resource[] = { | ||
186 | [0] = { | ||
187 | .start = S3C24XX_PA_NAND, | ||
188 | .end = S3C24XX_PA_NAND + S3C24XX_SZ_NAND - 1, | ||
189 | .flags = IORESOURCE_MEM, | ||
190 | } | ||
191 | }; | ||
192 | |||
193 | struct platform_device s3c_device_nand = { | ||
194 | .name = "s3c2410-nand", | ||
195 | .id = -1, | ||
196 | .num_resources = ARRAY_SIZE(s3c_nand_resource), | ||
197 | .resource = s3c_nand_resource, | ||
198 | }; | ||
199 | |||
200 | EXPORT_SYMBOL(s3c_device_nand); | ||
201 | |||
202 | /* USB Device (Gadget)*/ | 185 | /* USB Device (Gadget)*/ |
203 | 186 | ||
204 | static struct resource s3c_usbgadget_resource[] = { | 187 | static struct resource s3c_usbgadget_resource[] = { |
@@ -348,7 +331,7 @@ struct platform_device s3c_device_adc = { | |||
348 | /* HWMON */ | 331 | /* HWMON */ |
349 | 332 | ||
350 | struct platform_device s3c_device_hwmon = { | 333 | struct platform_device s3c_device_hwmon = { |
351 | .name = "s3c24xx-hwmon", | 334 | .name = "s3c-hwmon", |
352 | .id = -1, | 335 | .id = -1, |
353 | .dev.parent = &s3c_device_adc.dev, | 336 | .dev.parent = &s3c_device_adc.dev, |
354 | }; | 337 | }; |
@@ -473,4 +456,52 @@ struct platform_device s3c_device_camif = { | |||
473 | 456 | ||
474 | EXPORT_SYMBOL(s3c_device_camif); | 457 | EXPORT_SYMBOL(s3c_device_camif); |
475 | 458 | ||
459 | /* AC97 */ | ||
460 | |||
461 | static struct resource s3c_ac97_resource[] = { | ||
462 | [0] = { | ||
463 | .start = S3C2440_PA_AC97, | ||
464 | .end = S3C2440_PA_AC97 + S3C2440_SZ_AC97 -1, | ||
465 | .flags = IORESOURCE_MEM, | ||
466 | }, | ||
467 | [1] = { | ||
468 | .start = IRQ_S3C244x_AC97, | ||
469 | .end = IRQ_S3C244x_AC97, | ||
470 | .flags = IORESOURCE_IRQ, | ||
471 | }, | ||
472 | [2] = { | ||
473 | .name = "PCM out", | ||
474 | .start = DMACH_PCM_OUT, | ||
475 | .end = DMACH_PCM_OUT, | ||
476 | .flags = IORESOURCE_DMA, | ||
477 | }, | ||
478 | [3] = { | ||
479 | .name = "PCM in", | ||
480 | .start = DMACH_PCM_IN, | ||
481 | .end = DMACH_PCM_IN, | ||
482 | .flags = IORESOURCE_DMA, | ||
483 | }, | ||
484 | [4] = { | ||
485 | .name = "Mic in", | ||
486 | .start = DMACH_MIC_IN, | ||
487 | .end = DMACH_MIC_IN, | ||
488 | .flags = IORESOURCE_DMA, | ||
489 | }, | ||
490 | }; | ||
491 | |||
492 | static u64 s3c_device_ac97_dmamask = 0xffffffffUL; | ||
493 | |||
494 | struct platform_device s3c_device_ac97 = { | ||
495 | .name = "s3c-ac97", | ||
496 | .id = -1, | ||
497 | .num_resources = ARRAY_SIZE(s3c_ac97_resource), | ||
498 | .resource = s3c_ac97_resource, | ||
499 | .dev = { | ||
500 | .dma_mask = &s3c_device_ac97_dmamask, | ||
501 | .coherent_dma_mask = 0xffffffffUL | ||
502 | } | ||
503 | }; | ||
504 | |||
505 | EXPORT_SYMBOL(s3c_device_ac97); | ||
506 | |||
476 | #endif // CONFIG_CPU_S32440 | 507 | #endif // CONFIG_CPU_S32440 |
diff --git a/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h b/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h new file mode 100644 index 000000000000..efeb025affc7 --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h | |||
@@ -0,0 +1,282 @@ | |||
1 | /* arch/arm/plat-s3c/include/plat/cpu-freq.h | ||
2 | * | ||
3 | * Copyright (c) 2006,2007,2009 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C CPU frequency scaling support - core support | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <plat/cpu-freq.h> | ||
15 | |||
16 | struct seq_file; | ||
17 | |||
18 | #define MAX_BANKS (8) | ||
19 | #define S3C2412_MAX_IO (8) | ||
20 | |||
21 | /** | ||
22 | * struct s3c2410_iobank_timing - IO bank timings for S3C2410 style timings | ||
23 | * @bankcon: The cached version of settings in this structure. | ||
24 | * @tacp: | ||
25 | * @tacs: Time from address valid to nCS asserted. | ||
26 | * @tcos: Time from nCS asserted to nOE or nWE asserted. | ||
27 | * @tacc: Time that nOE or nWE is asserted. | ||
28 | * @tcoh: Time nCS is held after nOE or nWE are released. | ||
29 | * @tcah: Time address is held for after | ||
30 | * @nwait_en: Whether nWAIT is enabled for this bank. | ||
31 | * | ||
32 | * This structure represents the IO timings for a S3C2410 style IO bank | ||
33 | * used by the CPU frequency support if it needs to change the settings | ||
34 | * of the IO. | ||
35 | */ | ||
36 | struct s3c2410_iobank_timing { | ||
37 | unsigned long bankcon; | ||
38 | unsigned int tacp; | ||
39 | unsigned int tacs; | ||
40 | unsigned int tcos; | ||
41 | unsigned int tacc; | ||
42 | unsigned int tcoh; /* nCS hold afrer nOE/nWE */ | ||
43 | unsigned int tcah; /* Address hold after nCS */ | ||
44 | unsigned char nwait_en; /* nWait enabled for bank. */ | ||
45 | }; | ||
46 | |||
47 | /** | ||
48 | * struct s3c2412_iobank_timing - io timings for PL092 (S3C2412) style IO | ||
49 | * @idcy: The idle cycle time between transactions. | ||
50 | * @wstrd: nCS release to end of read cycle. | ||
51 | * @wstwr: nCS release to end of write cycle. | ||
52 | * @wstoen: nCS assertion to nOE assertion time. | ||
53 | * @wstwen: nCS assertion to nWE assertion time. | ||
54 | * @wstbrd: Burst ready delay. | ||
55 | * @smbidcyr: Register cache for smbidcyr value. | ||
56 | * @smbwstrd: Register cache for smbwstrd value. | ||
57 | * @smbwstwr: Register cache for smbwstwr value. | ||
58 | * @smbwstoen: Register cache for smbwstoen value. | ||
59 | * @smbwstwen: Register cache for smbwstwen value. | ||
60 | * @smbwstbrd: Register cache for smbwstbrd value. | ||
61 | * | ||
62 | * Timing information for a IO bank on an S3C2412 or similar system which | ||
63 | * uses a PL093 block. | ||
64 | */ | ||
65 | struct s3c2412_iobank_timing { | ||
66 | unsigned int idcy; | ||
67 | unsigned int wstrd; | ||
68 | unsigned int wstwr; | ||
69 | unsigned int wstoen; | ||
70 | unsigned int wstwen; | ||
71 | unsigned int wstbrd; | ||
72 | |||
73 | /* register cache */ | ||
74 | unsigned char smbidcyr; | ||
75 | unsigned char smbwstrd; | ||
76 | unsigned char smbwstwr; | ||
77 | unsigned char smbwstoen; | ||
78 | unsigned char smbwstwen; | ||
79 | unsigned char smbwstbrd; | ||
80 | }; | ||
81 | |||
82 | union s3c_iobank { | ||
83 | struct s3c2410_iobank_timing *io_2410; | ||
84 | struct s3c2412_iobank_timing *io_2412; | ||
85 | }; | ||
86 | |||
87 | /** | ||
88 | * struct s3c_iotimings - Chip IO timings holder | ||
89 | * @bank: The timings for each IO bank. | ||
90 | */ | ||
91 | struct s3c_iotimings { | ||
92 | union s3c_iobank bank[MAX_BANKS]; | ||
93 | }; | ||
94 | |||
95 | /** | ||
96 | * struct s3c_plltab - PLL table information. | ||
97 | * @vals: List of PLL values. | ||
98 | * @size: Size of the PLL table @vals. | ||
99 | */ | ||
100 | struct s3c_plltab { | ||
101 | struct s3c_pllval *vals; | ||
102 | int size; | ||
103 | }; | ||
104 | |||
105 | /** | ||
106 | * struct s3c_cpufreq_config - current cpu frequency configuration | ||
107 | * @freq: The current settings for the core clocks. | ||
108 | * @max: Maxium settings, derived from core, board and user settings. | ||
109 | * @pll: The PLL table entry for the current PLL settings. | ||
110 | * @divs: The divisor settings for the core clocks. | ||
111 | * @info: The current core driver information. | ||
112 | * @board: The information for the board we are running on. | ||
113 | * @lock_pll: Set if the PLL settings cannot be changed. | ||
114 | * | ||
115 | * This is for the core drivers that need to know information about | ||
116 | * the current settings and values. It should not be needed by any | ||
117 | * device drivers. | ||
118 | */ | ||
119 | struct s3c_cpufreq_config { | ||
120 | struct s3c_freq freq; | ||
121 | struct s3c_freq max; | ||
122 | struct cpufreq_frequency_table pll; | ||
123 | struct s3c_clkdivs divs; | ||
124 | struct s3c_cpufreq_info *info; /* for core, not drivers */ | ||
125 | struct s3c_cpufreq_board *board; | ||
126 | |||
127 | unsigned int lock_pll:1; | ||
128 | }; | ||
129 | |||
130 | /** | ||
131 | * struct s3c_cpufreq_info - Information for the CPU frequency driver. | ||
132 | * @name: The name of this implementation. | ||
133 | * @max: The maximum frequencies for the system. | ||
134 | * @latency: Transition latency to give to cpufreq. | ||
135 | * @locktime_m: The lock-time in uS for the MPLL. | ||
136 | * @locktime_u: The lock-time in uS for the UPLL. | ||
137 | * @locttime_bits: The number of bits each LOCKTIME field. | ||
138 | * @need_pll: Set if this driver needs to change the PLL values to acheive | ||
139 | * any frequency changes. This is really only need by devices like the | ||
140 | * S3C2410 where there is no or limited divider between the PLL and the | ||
141 | * ARMCLK. | ||
142 | * @resume_clocks: Update the clocks on resume. | ||
143 | * @get_iotiming: Get the current IO timing data, mainly for use at start. | ||
144 | * @set_iotiming: Update the IO timings from the cached copies calculated | ||
145 | * from the @calc_iotiming entry when changing the frequency. | ||
146 | * @calc_iotiming: Calculate and update the cached copies of the IO timings | ||
147 | * from the newly calculated frequencies. | ||
148 | * @calc_freqtable: Calculate (fill in) the given frequency table from the | ||
149 | * current frequency configuration. If the table passed in is NULL, | ||
150 | * then the return is the number of elements to be filled for allocation | ||
151 | * of the table. | ||
152 | * @set_refresh: Set the memory refresh configuration. | ||
153 | * @set_fvco: Set the PLL frequencies. | ||
154 | * @set_divs: Update the clock divisors. | ||
155 | * @calc_divs: Calculate the clock divisors. | ||
156 | */ | ||
157 | struct s3c_cpufreq_info { | ||
158 | const char *name; | ||
159 | struct s3c_freq max; | ||
160 | |||
161 | unsigned int latency; | ||
162 | |||
163 | unsigned int locktime_m; | ||
164 | unsigned int locktime_u; | ||
165 | unsigned char locktime_bits; | ||
166 | |||
167 | unsigned int need_pll:1; | ||
168 | |||
169 | /* driver routines */ | ||
170 | |||
171 | void (*resume_clocks)(void); | ||
172 | |||
173 | int (*get_iotiming)(struct s3c_cpufreq_config *cfg, | ||
174 | struct s3c_iotimings *timings); | ||
175 | |||
176 | void (*set_iotiming)(struct s3c_cpufreq_config *cfg, | ||
177 | struct s3c_iotimings *timings); | ||
178 | |||
179 | int (*calc_iotiming)(struct s3c_cpufreq_config *cfg, | ||
180 | struct s3c_iotimings *timings); | ||
181 | |||
182 | int (*calc_freqtable)(struct s3c_cpufreq_config *cfg, | ||
183 | struct cpufreq_frequency_table *t, | ||
184 | size_t table_size); | ||
185 | |||
186 | void (*debug_io_show)(struct seq_file *seq, | ||
187 | struct s3c_cpufreq_config *cfg, | ||
188 | union s3c_iobank *iob); | ||
189 | |||
190 | void (*set_refresh)(struct s3c_cpufreq_config *cfg); | ||
191 | void (*set_fvco)(struct s3c_cpufreq_config *cfg); | ||
192 | void (*set_divs)(struct s3c_cpufreq_config *cfg); | ||
193 | int (*calc_divs)(struct s3c_cpufreq_config *cfg); | ||
194 | }; | ||
195 | |||
196 | extern int s3c_cpufreq_register(struct s3c_cpufreq_info *info); | ||
197 | |||
198 | extern int s3c_plltab_register(struct cpufreq_frequency_table *plls, unsigned int plls_no); | ||
199 | |||
200 | /* exports and utilities for debugfs */ | ||
201 | extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void); | ||
202 | extern struct s3c_iotimings *s3c_cpufreq_getiotimings(void); | ||
203 | |||
204 | extern void s3c2410_iotiming_debugfs(struct seq_file *seq, | ||
205 | struct s3c_cpufreq_config *cfg, | ||
206 | union s3c_iobank *iob); | ||
207 | |||
208 | extern void s3c2412_iotiming_debugfs(struct seq_file *seq, | ||
209 | struct s3c_cpufreq_config *cfg, | ||
210 | union s3c_iobank *iob); | ||
211 | |||
212 | #ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS | ||
213 | #define s3c_cpufreq_debugfs_call(x) x | ||
214 | #else | ||
215 | #define s3c_cpufreq_debugfs_call(x) NULL | ||
216 | #endif | ||
217 | |||
218 | /* Useful utility functions. */ | ||
219 | |||
220 | extern struct clk *s3c_cpufreq_clk_get(struct device *, const char *); | ||
221 | |||
222 | /* S3C2410 and compatible exported functions */ | ||
223 | |||
224 | extern void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg); | ||
225 | |||
226 | extern int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg, | ||
227 | struct s3c_iotimings *iot); | ||
228 | |||
229 | extern int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg, | ||
230 | struct s3c_iotimings *timings); | ||
231 | |||
232 | extern void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg, | ||
233 | struct s3c_iotimings *iot); | ||
234 | |||
235 | extern void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg); | ||
236 | |||
237 | /* S3C2412 compatible routines */ | ||
238 | |||
239 | extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg, | ||
240 | struct s3c_iotimings *timings); | ||
241 | |||
242 | extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg, | ||
243 | struct s3c_iotimings *timings); | ||
244 | |||
245 | extern int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg, | ||
246 | struct s3c_iotimings *iot); | ||
247 | |||
248 | extern void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg, | ||
249 | struct s3c_iotimings *iot); | ||
250 | |||
251 | #ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUG | ||
252 | #define s3c_freq_dbg(x...) printk(KERN_INFO x) | ||
253 | #else | ||
254 | #define s3c_freq_dbg(x...) do { if (0) printk(x); } while (0) | ||
255 | #endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUG */ | ||
256 | |||
257 | #ifdef CONFIG_CPU_FREQ_S3C24XX_IODEBUG | ||
258 | #define s3c_freq_iodbg(x...) printk(KERN_INFO x) | ||
259 | #else | ||
260 | #define s3c_freq_iodbg(x...) do { if (0) printk(x); } while (0) | ||
261 | #endif /* CONFIG_CPU_FREQ_S3C24XX_IODEBUG */ | ||
262 | |||
263 | static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table, | ||
264 | int index, size_t table_size, | ||
265 | unsigned int freq) | ||
266 | { | ||
267 | if (index < 0) | ||
268 | return index; | ||
269 | |||
270 | if (table) { | ||
271 | if (index >= table_size) | ||
272 | return -ENOMEM; | ||
273 | |||
274 | s3c_freq_dbg("%s: { %d = %u kHz }\n", | ||
275 | __func__, index, freq); | ||
276 | |||
277 | table[index].index = index; | ||
278 | table[index].frequency = freq; | ||
279 | } | ||
280 | |||
281 | return index + 1; | ||
282 | } | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/fiq.h b/arch/arm/plat-s3c24xx/include/plat/fiq.h new file mode 100644 index 000000000000..8521b8372c5f --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/fiq.h | |||
@@ -0,0 +1,13 @@ | |||
1 | /* linux/include/asm-arm/plat-s3c24xx/fiq.h | ||
2 | * | ||
3 | * Copyright (c) 2009 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * Header file for S3C24XX CPU FIQ support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | extern int s3c24xx_set_fiq(unsigned int irq, bool on); | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2410.h b/arch/arm/plat-s3c24xx/include/plat/s3c2410.h index a9ac9e29759e..b6deeef8f663 100644 --- a/arch/arm/plat-s3c24xx/include/plat/s3c2410.h +++ b/arch/arm/plat-s3c24xx/include/plat/s3c2410.h | |||
@@ -14,6 +14,7 @@ | |||
14 | #ifdef CONFIG_CPU_S3C2410 | 14 | #ifdef CONFIG_CPU_S3C2410 |
15 | 15 | ||
16 | extern int s3c2410_init(void); | 16 | extern int s3c2410_init(void); |
17 | extern int s3c2410a_init(void); | ||
17 | 18 | ||
18 | extern void s3c2410_map_io(void); | 19 | extern void s3c2410_map_io(void); |
19 | 20 | ||
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c index 958737775ad2..d02f5f02045e 100644 --- a/arch/arm/plat-s3c24xx/irq.c +++ b/arch/arm/plat-s3c24xx/irq.c | |||
@@ -493,6 +493,38 @@ s3c_irq_demux_extint4t7(unsigned int irq, | |||
493 | } | 493 | } |
494 | } | 494 | } |
495 | 495 | ||
496 | #ifdef CONFIG_FIQ | ||
497 | /** | ||
498 | * s3c24xx_set_fiq - set the FIQ routing | ||
499 | * @irq: IRQ number to route to FIQ on processor. | ||
500 | * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing. | ||
501 | * | ||
502 | * Change the state of the IRQ to FIQ routing depending on @irq and @on. If | ||
503 | * @on is true, the @irq is checked to see if it can be routed and the | ||
504 | * interrupt controller updated to route the IRQ. If @on is false, the FIQ | ||
505 | * routing is cleared, regardless of which @irq is specified. | ||
506 | */ | ||
507 | int s3c24xx_set_fiq(unsigned int irq, bool on) | ||
508 | { | ||
509 | u32 intmod; | ||
510 | unsigned offs; | ||
511 | |||
512 | if (on) { | ||
513 | offs = irq - FIQ_START; | ||
514 | if (offs > 31) | ||
515 | return -EINVAL; | ||
516 | |||
517 | intmod = 1 << offs; | ||
518 | } else { | ||
519 | intmod = 0; | ||
520 | } | ||
521 | |||
522 | __raw_writel(intmod, S3C2410_INTMOD); | ||
523 | return 0; | ||
524 | } | ||
525 | #endif | ||
526 | |||
527 | |||
496 | /* s3c24xx_init_irq | 528 | /* s3c24xx_init_irq |
497 | * | 529 | * |
498 | * Initialise S3C2410 IRQ system | 530 | * Initialise S3C2410 IRQ system |
@@ -505,6 +537,10 @@ void __init s3c24xx_init_irq(void) | |||
505 | int irqno; | 537 | int irqno; |
506 | int i; | 538 | int i; |
507 | 539 | ||
540 | #ifdef CONFIG_FIQ | ||
541 | init_FIQ(); | ||
542 | #endif | ||
543 | |||
508 | irqdbf("s3c2410_init_irq: clearing interrupt status flags\n"); | 544 | irqdbf("s3c2410_init_irq: clearing interrupt status flags\n"); |
509 | 545 | ||
510 | /* first, clear all interrupts pending... */ | 546 | /* first, clear all interrupts pending... */ |
diff --git a/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c b/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c new file mode 100644 index 000000000000..43ea80190d87 --- /dev/null +++ b/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c | |||
@@ -0,0 +1,64 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c | ||
2 | * | ||
3 | * Copyright (c) 2009 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C24XX CPU Frequency scaling - utils for S3C2410/S3C2440/S3C2442 | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/errno.h> | ||
16 | #include <linux/cpufreq.h> | ||
17 | #include <linux/io.h> | ||
18 | |||
19 | #include <mach/map.h> | ||
20 | #include <mach/regs-mem.h> | ||
21 | #include <mach/regs-clock.h> | ||
22 | |||
23 | #include <plat/cpu-freq-core.h> | ||
24 | |||
25 | /** | ||
26 | * s3c2410_cpufreq_setrefresh - set SDRAM refresh value | ||
27 | * @cfg: The frequency configuration | ||
28 | * | ||
29 | * Set the SDRAM refresh value appropriately for the configured | ||
30 | * frequency. | ||
31 | */ | ||
32 | void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg) | ||
33 | { | ||
34 | struct s3c_cpufreq_board *board = cfg->board; | ||
35 | unsigned long refresh; | ||
36 | unsigned long refval; | ||
37 | |||
38 | /* Reduce both the refresh time (in ns) and the frequency (in MHz) | ||
39 | * down to ensure that we do not overflow 32 bit numbers. | ||
40 | * | ||
41 | * This should work for HCLK up to 133MHz and refresh period up | ||
42 | * to 30usec. | ||
43 | */ | ||
44 | |||
45 | refresh = (cfg->freq.hclk / 100) * (board->refresh / 10); | ||
46 | refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale */ | ||
47 | refresh = (1 << 11) + 1 - refresh; | ||
48 | |||
49 | s3c_freq_dbg("%s: refresh value %lu\n", __func__, refresh); | ||
50 | |||
51 | refval = __raw_readl(S3C2410_REFRESH); | ||
52 | refval &= ~((1 << 12) - 1); | ||
53 | refval |= refresh; | ||
54 | __raw_writel(refval, S3C2410_REFRESH); | ||
55 | } | ||
56 | |||
57 | /** | ||
58 | * s3c2410_set_fvco - set the PLL value | ||
59 | * @cfg: The frequency configuration | ||
60 | */ | ||
61 | void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg) | ||
62 | { | ||
63 | __raw_writel(cfg->pll.index, S3C2410_MPLLCON); | ||
64 | } | ||
diff --git a/arch/arm/plat-s3c24xx/s3c2410-iotiming.c b/arch/arm/plat-s3c24xx/s3c2410-iotiming.c new file mode 100644 index 000000000000..d0a3a145cd4d --- /dev/null +++ b/arch/arm/plat-s3c24xx/s3c2410-iotiming.c | |||
@@ -0,0 +1,477 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/s3c2410-iotiming.c | ||
2 | * | ||
3 | * Copyright (c) 2006,2008,2009 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C24XX CPU Frequency scaling - IO timing for S3C2410/S3C2440/S3C2442 | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <linux/init.h> | ||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/errno.h> | ||
17 | #include <linux/cpufreq.h> | ||
18 | #include <linux/seq_file.h> | ||
19 | #include <linux/io.h> | ||
20 | |||
21 | #include <mach/map.h> | ||
22 | #include <mach/regs-mem.h> | ||
23 | #include <mach/regs-clock.h> | ||
24 | |||
25 | #include <plat/cpu-freq-core.h> | ||
26 | |||
27 | #define print_ns(x) ((x) / 10), ((x) % 10) | ||
28 | |||
29 | /** | ||
30 | * s3c2410_print_timing - print bank timing data for debug purposes | ||
31 | * @pfx: The prefix to put on the output | ||
32 | * @timings: The timing inforamtion to print. | ||
33 | */ | ||
34 | static void s3c2410_print_timing(const char *pfx, | ||
35 | struct s3c_iotimings *timings) | ||
36 | { | ||
37 | struct s3c2410_iobank_timing *bt; | ||
38 | int bank; | ||
39 | |||
40 | for (bank = 0; bank < MAX_BANKS; bank++) { | ||
41 | bt = timings->bank[bank].io_2410; | ||
42 | if (!bt) | ||
43 | continue; | ||
44 | |||
45 | printk(KERN_DEBUG "%s %d: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, " | ||
46 | "Tcoh=%d.%d, Tcah=%d.%d\n", pfx, bank, | ||
47 | print_ns(bt->tacs), | ||
48 | print_ns(bt->tcos), | ||
49 | print_ns(bt->tacc), | ||
50 | print_ns(bt->tcoh), | ||
51 | print_ns(bt->tcah)); | ||
52 | } | ||
53 | } | ||
54 | |||
55 | /** | ||
56 | * bank_reg - convert bank number to pointer to the control register. | ||
57 | * @bank: The IO bank number. | ||
58 | */ | ||
59 | static inline void __iomem *bank_reg(unsigned int bank) | ||
60 | { | ||
61 | return S3C2410_BANKCON0 + (bank << 2); | ||
62 | } | ||
63 | |||
64 | /** | ||
65 | * bank_is_io - test whether bank is used for IO | ||
66 | * @bankcon: The bank control register. | ||
67 | * | ||
68 | * This is a simplistic test to see if any BANKCON[x] is not an IO | ||
69 | * bank. It currently does not take into account whether BWSCON has | ||
70 | * an illegal width-setting in it, or if the pin connected to nCS[x] | ||
71 | * is actually being handled as a chip-select. | ||
72 | */ | ||
73 | static inline int bank_is_io(unsigned long bankcon) | ||
74 | { | ||
75 | return !(bankcon & S3C2410_BANKCON_SDRAM); | ||
76 | } | ||
77 | |||
78 | /** | ||
79 | * to_div - convert cycle time to divisor | ||
80 | * @cyc: The cycle time, in 10ths of nanoseconds. | ||
81 | * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds. | ||
82 | * | ||
83 | * Convert the given cycle time into the divisor to use to obtain it from | ||
84 | * HCLK. | ||
85 | */ | ||
86 | static inline unsigned int to_div(unsigned int cyc, unsigned int hclk_tns) | ||
87 | { | ||
88 | if (cyc == 0) | ||
89 | return 0; | ||
90 | |||
91 | return DIV_ROUND_UP(cyc, hclk_tns); | ||
92 | } | ||
93 | |||
94 | /** | ||
95 | * calc_0124 - calculate divisor control for divisors that do /0, /1. /2 and /4 | ||
96 | * @cyc: The cycle time, in 10ths of nanoseconds. | ||
97 | * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds. | ||
98 | * @v: Pointer to register to alter. | ||
99 | * @shift: The shift to get to the control bits. | ||
100 | * | ||
101 | * Calculate the divisor, and turn it into the correct control bits to | ||
102 | * set in the result, @v. | ||
103 | */ | ||
104 | static unsigned int calc_0124(unsigned int cyc, unsigned long hclk_tns, | ||
105 | unsigned long *v, int shift) | ||
106 | { | ||
107 | unsigned int div = to_div(cyc, hclk_tns); | ||
108 | unsigned long val; | ||
109 | |||
110 | s3c_freq_iodbg("%s: cyc=%d, hclk=%lu, shift=%d => div %d\n", | ||
111 | __func__, cyc, hclk_tns, shift, div); | ||
112 | |||
113 | switch (div) { | ||
114 | case 0: | ||
115 | val = 0; | ||
116 | break; | ||
117 | case 1: | ||
118 | val = 1; | ||
119 | break; | ||
120 | case 2: | ||
121 | val = 2; | ||
122 | break; | ||
123 | case 3: | ||
124 | case 4: | ||
125 | val = 3; | ||
126 | break; | ||
127 | default: | ||
128 | return -1; | ||
129 | } | ||
130 | |||
131 | *v |= val << shift; | ||
132 | return 0; | ||
133 | } | ||
134 | |||
135 | int calc_tacp(unsigned int cyc, unsigned long hclk, unsigned long *v) | ||
136 | { | ||
137 | /* Currently no support for Tacp calculations. */ | ||
138 | return 0; | ||
139 | } | ||
140 | |||
141 | /** | ||
142 | * calc_tacc - calculate divisor control for tacc. | ||
143 | * @cyc: The cycle time, in 10ths of nanoseconds. | ||
144 | * @nwait_en: IS nWAIT enabled for this bank. | ||
145 | * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds. | ||
146 | * @v: Pointer to register to alter. | ||
147 | * | ||
148 | * Calculate the divisor control for tACC, taking into account whether | ||
149 | * the bank has nWAIT enabled. The result is used to modify the value | ||
150 | * pointed to by @v. | ||
151 | */ | ||
152 | static int calc_tacc(unsigned int cyc, int nwait_en, | ||
153 | unsigned long hclk_tns, unsigned long *v) | ||
154 | { | ||
155 | unsigned int div = to_div(cyc, hclk_tns); | ||
156 | unsigned long val; | ||
157 | |||
158 | s3c_freq_iodbg("%s: cyc=%u, nwait=%d, hclk=%lu => div=%u\n", | ||
159 | __func__, cyc, nwait_en, hclk_tns, div); | ||
160 | |||
161 | /* if nWait enabled on an bank, Tacc must be at-least 4 cycles. */ | ||
162 | if (nwait_en && div < 4) | ||
163 | div = 4; | ||
164 | |||
165 | switch (div) { | ||
166 | case 0: | ||
167 | val = 0; | ||
168 | break; | ||
169 | |||
170 | case 1: | ||
171 | case 2: | ||
172 | case 3: | ||
173 | case 4: | ||
174 | val = div - 1; | ||
175 | break; | ||
176 | |||
177 | case 5: | ||
178 | case 6: | ||
179 | val = 4; | ||
180 | break; | ||
181 | |||
182 | case 7: | ||
183 | case 8: | ||
184 | val = 5; | ||
185 | break; | ||
186 | |||
187 | case 9: | ||
188 | case 10: | ||
189 | val = 6; | ||
190 | break; | ||
191 | |||
192 | case 11: | ||
193 | case 12: | ||
194 | case 13: | ||
195 | case 14: | ||
196 | val = 7; | ||
197 | break; | ||
198 | |||
199 | default: | ||
200 | return -1; | ||
201 | } | ||
202 | |||
203 | *v |= val << 8; | ||
204 | return 0; | ||
205 | } | ||
206 | |||
207 | /** | ||
208 | * s3c2410_calc_bank - calculate bank timing infromation | ||
209 | * @cfg: The configuration we need to calculate for. | ||
210 | * @bt: The bank timing information. | ||
211 | * | ||
212 | * Given the cycle timine for a bank @bt, calculate the new BANKCON | ||
213 | * setting for the @cfg timing. This updates the timing information | ||
214 | * ready for the cpu frequency change. | ||
215 | */ | ||
216 | static int s3c2410_calc_bank(struct s3c_cpufreq_config *cfg, | ||
217 | struct s3c2410_iobank_timing *bt) | ||
218 | { | ||
219 | unsigned long hclk = cfg->freq.hclk_tns; | ||
220 | unsigned long res; | ||
221 | int ret; | ||
222 | |||
223 | res = bt->bankcon; | ||
224 | res &= (S3C2410_BANKCON_SDRAM | S3C2410_BANKCON_PMC16); | ||
225 | |||
226 | /* tacp: 2,3,4,5 */ | ||
227 | /* tcah: 0,1,2,4 */ | ||
228 | /* tcoh: 0,1,2,4 */ | ||
229 | /* tacc: 1,2,3,4,6,7,10,14 (>4 for nwait) */ | ||
230 | /* tcos: 0,1,2,4 */ | ||
231 | /* tacs: 0,1,2,4 */ | ||
232 | |||
233 | ret = calc_0124(bt->tacs, hclk, &res, S3C2410_BANKCON_Tacs_SHIFT); | ||
234 | ret |= calc_0124(bt->tcos, hclk, &res, S3C2410_BANKCON_Tcos_SHIFT); | ||
235 | ret |= calc_0124(bt->tcah, hclk, &res, S3C2410_BANKCON_Tcah_SHIFT); | ||
236 | ret |= calc_0124(bt->tcoh, hclk, &res, S3C2410_BANKCON_Tcoh_SHIFT); | ||
237 | |||
238 | if (ret) | ||
239 | return -EINVAL; | ||
240 | |||
241 | ret |= calc_tacp(bt->tacp, hclk, &res); | ||
242 | ret |= calc_tacc(bt->tacc, bt->nwait_en, hclk, &res); | ||
243 | |||
244 | if (ret) | ||
245 | return -EINVAL; | ||
246 | |||
247 | bt->bankcon = res; | ||
248 | return 0; | ||
249 | } | ||
250 | |||
251 | static unsigned int tacc_tab[] = { | ||
252 | [0] = 1, | ||
253 | [1] = 2, | ||
254 | [2] = 3, | ||
255 | [3] = 4, | ||
256 | [4] = 6, | ||
257 | [5] = 9, | ||
258 | [6] = 10, | ||
259 | [7] = 14, | ||
260 | }; | ||
261 | |||
262 | /** | ||
263 | * get_tacc - turn tACC value into cycle time | ||
264 | * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds. | ||
265 | * @val: The bank timing register value, shifed down. | ||
266 | */ | ||
267 | static unsigned int get_tacc(unsigned long hclk_tns, | ||
268 | unsigned long val) | ||
269 | { | ||
270 | val &= 7; | ||
271 | return hclk_tns * tacc_tab[val]; | ||
272 | } | ||
273 | |||
274 | /** | ||
275 | * get_0124 - turn 0/1/2/4 divider into cycle time | ||
276 | * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds. | ||
277 | * @val: The bank timing register value, shifed down. | ||
278 | */ | ||
279 | static unsigned int get_0124(unsigned long hclk_tns, | ||
280 | unsigned long val) | ||
281 | { | ||
282 | val &= 3; | ||
283 | return hclk_tns * ((val == 3) ? 4 : val); | ||
284 | } | ||
285 | |||
286 | /** | ||
287 | * s3c2410_iotiming_getbank - turn BANKCON into cycle time information | ||
288 | * @cfg: The frequency configuration | ||
289 | * @bt: The bank timing to fill in (uses cached BANKCON) | ||
290 | * | ||
291 | * Given the BANKCON setting in @bt and the current frequency settings | ||
292 | * in @cfg, update the cycle timing information. | ||
293 | */ | ||
294 | void s3c2410_iotiming_getbank(struct s3c_cpufreq_config *cfg, | ||
295 | struct s3c2410_iobank_timing *bt) | ||
296 | { | ||
297 | unsigned long bankcon = bt->bankcon; | ||
298 | unsigned long hclk = cfg->freq.hclk_tns; | ||
299 | |||
300 | bt->tcah = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcah_SHIFT); | ||
301 | bt->tcoh = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcoh_SHIFT); | ||
302 | bt->tcos = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcos_SHIFT); | ||
303 | bt->tacs = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tacs_SHIFT); | ||
304 | bt->tacc = get_tacc(hclk, bankcon >> S3C2410_BANKCON_Tacc_SHIFT); | ||
305 | } | ||
306 | |||
307 | /** | ||
308 | * s3c2410_iotiming_debugfs - debugfs show io bank timing information | ||
309 | * @seq: The seq_file to write output to using seq_printf(). | ||
310 | * @cfg: The current configuration. | ||
311 | * @iob: The IO bank information to decode. | ||
312 | */ | ||
313 | void s3c2410_iotiming_debugfs(struct seq_file *seq, | ||
314 | struct s3c_cpufreq_config *cfg, | ||
315 | union s3c_iobank *iob) | ||
316 | { | ||
317 | struct s3c2410_iobank_timing *bt = iob->io_2410; | ||
318 | unsigned long bankcon = bt->bankcon; | ||
319 | unsigned long hclk = cfg->freq.hclk_tns; | ||
320 | unsigned int tacs; | ||
321 | unsigned int tcos; | ||
322 | unsigned int tacc; | ||
323 | unsigned int tcoh; | ||
324 | unsigned int tcah; | ||
325 | |||
326 | seq_printf(seq, "BANKCON=0x%08lx\n", bankcon); | ||
327 | |||
328 | tcah = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcah_SHIFT); | ||
329 | tcoh = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcoh_SHIFT); | ||
330 | tcos = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcos_SHIFT); | ||
331 | tacs = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tacs_SHIFT); | ||
332 | tacc = get_tacc(hclk, bankcon >> S3C2410_BANKCON_Tacc_SHIFT); | ||
333 | |||
334 | seq_printf(seq, | ||
335 | "\tRead: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, Tcoh=%d.%d, Tcah=%d.%d\n", | ||
336 | print_ns(bt->tacs), | ||
337 | print_ns(bt->tcos), | ||
338 | print_ns(bt->tacc), | ||
339 | print_ns(bt->tcoh), | ||
340 | print_ns(bt->tcah)); | ||
341 | |||
342 | seq_printf(seq, | ||
343 | "\t Set: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, Tcoh=%d.%d, Tcah=%d.%d\n", | ||
344 | print_ns(tacs), | ||
345 | print_ns(tcos), | ||
346 | print_ns(tacc), | ||
347 | print_ns(tcoh), | ||
348 | print_ns(tcah)); | ||
349 | } | ||
350 | |||
351 | /** | ||
352 | * s3c2410_iotiming_calc - Calculate bank timing for frequency change. | ||
353 | * @cfg: The frequency configuration | ||
354 | * @iot: The IO timing information to fill out. | ||
355 | * | ||
356 | * Calculate the new values for the banks in @iot based on the new | ||
357 | * frequency information in @cfg. This is then used by s3c2410_iotiming_set() | ||
358 | * to update the timing when necessary. | ||
359 | */ | ||
360 | int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg, | ||
361 | struct s3c_iotimings *iot) | ||
362 | { | ||
363 | struct s3c2410_iobank_timing *bt; | ||
364 | unsigned long bankcon; | ||
365 | int bank; | ||
366 | int ret; | ||
367 | |||
368 | for (bank = 0; bank < MAX_BANKS; bank++) { | ||
369 | bankcon = __raw_readl(bank_reg(bank)); | ||
370 | bt = iot->bank[bank].io_2410; | ||
371 | |||
372 | if (!bt) | ||
373 | continue; | ||
374 | |||
375 | bt->bankcon = bankcon; | ||
376 | |||
377 | ret = s3c2410_calc_bank(cfg, bt); | ||
378 | if (ret) { | ||
379 | printk(KERN_ERR "%s: cannot calculate bank %d io\n", | ||
380 | __func__, bank); | ||
381 | goto err; | ||
382 | } | ||
383 | |||
384 | s3c_freq_iodbg("%s: bank %d: con=%08lx\n", | ||
385 | __func__, bank, bt->bankcon); | ||
386 | } | ||
387 | |||
388 | return 0; | ||
389 | err: | ||
390 | return ret; | ||
391 | } | ||
392 | |||
393 | /** | ||
394 | * s3c2410_iotiming_set - set the IO timings from the given setup. | ||
395 | * @cfg: The frequency configuration | ||
396 | * @iot: The IO timing information to use. | ||
397 | * | ||
398 | * Set all the currently used IO bank timing information generated | ||
399 | * by s3c2410_iotiming_calc() once the core has validated that all | ||
400 | * the new values are within permitted bounds. | ||
401 | */ | ||
402 | void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg, | ||
403 | struct s3c_iotimings *iot) | ||
404 | { | ||
405 | struct s3c2410_iobank_timing *bt; | ||
406 | int bank; | ||
407 | |||
408 | /* set the io timings from the specifier */ | ||
409 | |||
410 | for (bank = 0; bank < MAX_BANKS; bank++) { | ||
411 | bt = iot->bank[bank].io_2410; | ||
412 | if (!bt) | ||
413 | continue; | ||
414 | |||
415 | __raw_writel(bt->bankcon, bank_reg(bank)); | ||
416 | } | ||
417 | } | ||
418 | |||
419 | /** | ||
420 | * s3c2410_iotiming_get - Get the timing information from current registers. | ||
421 | * @cfg: The frequency configuration | ||
422 | * @timings: The IO timing information to fill out. | ||
423 | * | ||
424 | * Calculate the @timings timing information from the current frequency | ||
425 | * information in @cfg, and the new frequency configur | ||
426 | * through all the IO banks, reading the state and then updating @iot | ||
427 | * as necessary. | ||
428 | * | ||
429 | * This is used at the moment on initialisation to get the current | ||
430 | * configuration so that boards do not have to carry their own setup | ||
431 | * if the timings are correct on initialisation. | ||
432 | */ | ||
433 | |||
434 | int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg, | ||
435 | struct s3c_iotimings *timings) | ||
436 | { | ||
437 | struct s3c2410_iobank_timing *bt; | ||
438 | unsigned long bankcon; | ||
439 | unsigned long bwscon; | ||
440 | int bank; | ||
441 | |||
442 | bwscon = __raw_readl(S3C2410_BWSCON); | ||
443 | |||
444 | /* look through all banks to see what is currently set. */ | ||
445 | |||
446 | for (bank = 0; bank < MAX_BANKS; bank++) { | ||
447 | bankcon = __raw_readl(bank_reg(bank)); | ||
448 | |||
449 | if (!bank_is_io(bankcon)) | ||
450 | continue; | ||
451 | |||
452 | s3c_freq_iodbg("%s: bank %d: con %08lx\n", | ||
453 | __func__, bank, bankcon); | ||
454 | |||
455 | bt = kzalloc(sizeof(struct s3c2410_iobank_timing), GFP_KERNEL); | ||
456 | if (!bt) { | ||
457 | printk(KERN_ERR "%s: no memory for bank\n", __func__); | ||
458 | return -ENOMEM; | ||
459 | } | ||
460 | |||
461 | /* find out in nWait is enabled for bank. */ | ||
462 | |||
463 | if (bank != 0) { | ||
464 | unsigned long tmp = S3C2410_BWSCON_GET(bwscon, bank); | ||
465 | if (tmp & S3C2410_BWSCON_WS) | ||
466 | bt->nwait_en = 1; | ||
467 | } | ||
468 | |||
469 | timings->bank[bank].io_2410 = bt; | ||
470 | bt->bankcon = bankcon; | ||
471 | |||
472 | s3c2410_iotiming_getbank(cfg, bt); | ||
473 | } | ||
474 | |||
475 | s3c2410_print_timing("get", timings); | ||
476 | return 0; | ||
477 | } | ||
diff --git a/arch/arm/plat-s3c24xx/s3c2412-iotiming.c b/arch/arm/plat-s3c24xx/s3c2412-iotiming.c new file mode 100644 index 000000000000..fd45e47facbc --- /dev/null +++ b/arch/arm/plat-s3c24xx/s3c2412-iotiming.c | |||
@@ -0,0 +1,285 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/s3c2412-iotiming.c | ||
2 | * | ||
3 | * Copyright (c) 2006,2008 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C2412/S3C2443 (PL093 based) IO timing support | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <linux/init.h> | ||
15 | #include <linux/module.h> | ||
16 | #include <linux/interrupt.h> | ||
17 | #include <linux/ioport.h> | ||
18 | #include <linux/cpufreq.h> | ||
19 | #include <linux/seq_file.h> | ||
20 | #include <linux/sysdev.h> | ||
21 | #include <linux/delay.h> | ||
22 | #include <linux/clk.h> | ||
23 | #include <linux/err.h> | ||
24 | |||
25 | #include <linux/amba/pl093.h> | ||
26 | |||
27 | #include <asm/mach/arch.h> | ||
28 | #include <asm/mach/map.h> | ||
29 | |||
30 | #include <mach/regs-s3c2412-mem.h> | ||
31 | |||
32 | #include <plat/cpu.h> | ||
33 | #include <plat/cpu-freq-core.h> | ||
34 | #include <plat/clock.h> | ||
35 | |||
36 | #define print_ns(x) ((x) / 10), ((x) % 10) | ||
37 | |||
38 | /** | ||
39 | * s3c2412_print_timing - print timing infromation via printk. | ||
40 | * @pfx: The prefix to print each line with. | ||
41 | * @iot: The IO timing information | ||
42 | */ | ||
43 | static void s3c2412_print_timing(const char *pfx, struct s3c_iotimings *iot) | ||
44 | { | ||
45 | struct s3c2412_iobank_timing *bt; | ||
46 | unsigned int bank; | ||
47 | |||
48 | for (bank = 0; bank < MAX_BANKS; bank++) { | ||
49 | bt = iot->bank[bank].io_2412; | ||
50 | if (!bt) | ||
51 | continue; | ||
52 | |||
53 | printk(KERN_DEBUG "%s: %d: idcy=%d.%d wstrd=%d.%d wstwr=%d,%d" | ||
54 | "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n", pfx, bank, | ||
55 | print_ns(bt->idcy), | ||
56 | print_ns(bt->wstrd), | ||
57 | print_ns(bt->wstwr), | ||
58 | print_ns(bt->wstoen), | ||
59 | print_ns(bt->wstwen), | ||
60 | print_ns(bt->wstbrd)); | ||
61 | } | ||
62 | } | ||
63 | |||
64 | /** | ||
65 | * to_div - turn a cycle length into a divisor setting. | ||
66 | * @cyc_tns: The cycle time in 10ths of nanoseconds. | ||
67 | * @clk_tns: The clock period in 10ths of nanoseconds. | ||
68 | */ | ||
69 | static inline unsigned int to_div(unsigned int cyc_tns, unsigned int clk_tns) | ||
70 | { | ||
71 | return cyc_tns ? DIV_ROUND_UP(cyc_tns, clk_tns) : 0; | ||
72 | } | ||
73 | |||
74 | /** | ||
75 | * calc_timing - calculate timing divisor value and check in range. | ||
76 | * @hwtm: The hardware timing in 10ths of nanoseconds. | ||
77 | * @clk_tns: The clock period in 10ths of nanoseconds. | ||
78 | * @err: Pointer to err variable to update in event of failure. | ||
79 | */ | ||
80 | static unsigned int calc_timing(unsigned int hwtm, unsigned int clk_tns, | ||
81 | unsigned int *err) | ||
82 | { | ||
83 | unsigned int ret = to_div(hwtm, clk_tns); | ||
84 | |||
85 | if (ret > 0xf) | ||
86 | *err = -EINVAL; | ||
87 | |||
88 | return ret; | ||
89 | } | ||
90 | |||
91 | /** | ||
92 | * s3c2412_calc_bank - calculate the bank divisor settings. | ||
93 | * @cfg: The current frequency configuration. | ||
94 | * @bt: The bank timing. | ||
95 | */ | ||
96 | static int s3c2412_calc_bank(struct s3c_cpufreq_config *cfg, | ||
97 | struct s3c2412_iobank_timing *bt) | ||
98 | { | ||
99 | unsigned int hclk = cfg->freq.hclk_tns; | ||
100 | int err = 0; | ||
101 | |||
102 | bt->smbidcyr = calc_timing(bt->idcy, hclk, &err); | ||
103 | bt->smbwstrd = calc_timing(bt->wstrd, hclk, &err); | ||
104 | bt->smbwstwr = calc_timing(bt->wstwr, hclk, &err); | ||
105 | bt->smbwstoen = calc_timing(bt->wstoen, hclk, &err); | ||
106 | bt->smbwstwen = calc_timing(bt->wstwen, hclk, &err); | ||
107 | bt->smbwstbrd = calc_timing(bt->wstbrd, hclk, &err); | ||
108 | |||
109 | return err; | ||
110 | } | ||
111 | |||
112 | /** | ||
113 | * s3c2412_iotiming_debugfs - debugfs show io bank timing information | ||
114 | * @seq: The seq_file to write output to using seq_printf(). | ||
115 | * @cfg: The current configuration. | ||
116 | * @iob: The IO bank information to decode. | ||
117 | */ | ||
118 | void s3c2412_iotiming_debugfs(struct seq_file *seq, | ||
119 | struct s3c_cpufreq_config *cfg, | ||
120 | union s3c_iobank *iob) | ||
121 | { | ||
122 | struct s3c2412_iobank_timing *bt = iob->io_2412; | ||
123 | |||
124 | seq_printf(seq, | ||
125 | "\tRead: idcy=%d.%d wstrd=%d.%d wstwr=%d,%d" | ||
126 | "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n", | ||
127 | print_ns(bt->idcy), | ||
128 | print_ns(bt->wstrd), | ||
129 | print_ns(bt->wstwr), | ||
130 | print_ns(bt->wstoen), | ||
131 | print_ns(bt->wstwen), | ||
132 | print_ns(bt->wstbrd)); | ||
133 | } | ||
134 | |||
135 | /** | ||
136 | * s3c2412_iotiming_calc - calculate all the bank divisor settings. | ||
137 | * @cfg: The current frequency configuration. | ||
138 | * @iot: The bank timing information. | ||
139 | * | ||
140 | * Calculate the timing information for all the banks that are | ||
141 | * configured as IO, using s3c2412_calc_bank(). | ||
142 | */ | ||
143 | int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg, | ||
144 | struct s3c_iotimings *iot) | ||
145 | { | ||
146 | struct s3c2412_iobank_timing *bt; | ||
147 | int bank; | ||
148 | int ret; | ||
149 | |||
150 | for (bank = 0; bank < MAX_BANKS; bank++) { | ||
151 | bt = iot->bank[bank].io_2412; | ||
152 | if (!bt) | ||
153 | continue; | ||
154 | |||
155 | ret = s3c2412_calc_bank(cfg, bt); | ||
156 | if (ret) { | ||
157 | printk(KERN_ERR "%s: cannot calculate bank %d io\n", | ||
158 | __func__, bank); | ||
159 | goto err; | ||
160 | } | ||
161 | } | ||
162 | |||
163 | return 0; | ||
164 | err: | ||
165 | return ret; | ||
166 | } | ||
167 | |||
168 | /** | ||
169 | * s3c2412_iotiming_set - set the timing information | ||
170 | * @cfg: The current frequency configuration. | ||
171 | * @iot: The bank timing information. | ||
172 | * | ||
173 | * Set the IO bank information from the details calculated earlier from | ||
174 | * calling s3c2412_iotiming_calc(). | ||
175 | */ | ||
176 | void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg, | ||
177 | struct s3c_iotimings *iot) | ||
178 | { | ||
179 | struct s3c2412_iobank_timing *bt; | ||
180 | void __iomem *regs; | ||
181 | int bank; | ||
182 | |||
183 | /* set the io timings from the specifier */ | ||
184 | |||
185 | for (bank = 0; bank < MAX_BANKS; bank++) { | ||
186 | bt = iot->bank[bank].io_2412; | ||
187 | if (!bt) | ||
188 | continue; | ||
189 | |||
190 | regs = S3C2412_SSMC_BANK(bank); | ||
191 | |||
192 | __raw_writel(bt->smbidcyr, regs + SMBIDCYR); | ||
193 | __raw_writel(bt->smbwstrd, regs + SMBWSTRDR); | ||
194 | __raw_writel(bt->smbwstwr, regs + SMBWSTWRR); | ||
195 | __raw_writel(bt->smbwstoen, regs + SMBWSTOENR); | ||
196 | __raw_writel(bt->smbwstwen, regs + SMBWSTWENR); | ||
197 | __raw_writel(bt->smbwstbrd, regs + SMBWSTBRDR); | ||
198 | } | ||
199 | } | ||
200 | |||
201 | static inline unsigned int s3c2412_decode_timing(unsigned int clock, u32 reg) | ||
202 | { | ||
203 | return (reg & 0xf) * clock; | ||
204 | } | ||
205 | |||
206 | static void s3c2412_iotiming_getbank(struct s3c_cpufreq_config *cfg, | ||
207 | struct s3c2412_iobank_timing *bt, | ||
208 | unsigned int bank) | ||
209 | { | ||
210 | unsigned long clk = cfg->freq.hclk_tns; /* ssmc clock??? */ | ||
211 | void __iomem *regs = S3C2412_SSMC_BANK(bank); | ||
212 | |||
213 | bt->idcy = s3c2412_decode_timing(clk, __raw_readl(regs + SMBIDCYR)); | ||
214 | bt->wstrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTRDR)); | ||
215 | bt->wstoen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTOENR)); | ||
216 | bt->wstwen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTWENR)); | ||
217 | bt->wstbrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTBRDR)); | ||
218 | } | ||
219 | |||
220 | /** | ||
221 | * bank_is_io - return true if bank is (possibly) IO. | ||
222 | * @bank: The bank number. | ||
223 | * @bankcfg: The value of S3C2412_EBI_BANKCFG. | ||
224 | */ | ||
225 | static inline bool bank_is_io(unsigned int bank, u32 bankcfg) | ||
226 | { | ||
227 | if (bank < 2) | ||
228 | return true; | ||
229 | |||
230 | return !(bankcfg & (1 << bank)); | ||
231 | } | ||
232 | |||
233 | int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg, | ||
234 | struct s3c_iotimings *timings) | ||
235 | { | ||
236 | struct s3c2412_iobank_timing *bt; | ||
237 | u32 bankcfg = __raw_readl(S3C2412_EBI_BANKCFG); | ||
238 | unsigned int bank; | ||
239 | |||
240 | /* look through all banks to see what is currently set. */ | ||
241 | |||
242 | for (bank = 0; bank < MAX_BANKS; bank++) { | ||
243 | if (!bank_is_io(bank, bankcfg)) | ||
244 | continue; | ||
245 | |||
246 | bt = kzalloc(sizeof(struct s3c2412_iobank_timing), GFP_KERNEL); | ||
247 | if (!bt) { | ||
248 | printk(KERN_ERR "%s: no memory for bank\n", __func__); | ||
249 | return -ENOMEM; | ||
250 | } | ||
251 | |||
252 | timings->bank[bank].io_2412 = bt; | ||
253 | s3c2412_iotiming_getbank(cfg, bt, bank); | ||
254 | } | ||
255 | |||
256 | s3c2412_print_timing("get", timings); | ||
257 | return 0; | ||
258 | } | ||
259 | |||
260 | /* this is in here as it is so small, it doesn't currently warrant a file | ||
261 | * to itself. We expect that any s3c24xx needing this is going to also | ||
262 | * need the iotiming support. | ||
263 | */ | ||
264 | void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg) | ||
265 | { | ||
266 | struct s3c_cpufreq_board *board = cfg->board; | ||
267 | u32 refresh; | ||
268 | |||
269 | WARN_ON(board == NULL); | ||
270 | |||
271 | /* Reduce both the refresh time (in ns) and the frequency (in MHz) | ||
272 | * down to ensure that we do not overflow 32 bit numbers. | ||
273 | * | ||
274 | * This should work for HCLK up to 133MHz and refresh period up | ||
275 | * to 30usec. | ||
276 | */ | ||
277 | |||
278 | refresh = (cfg->freq.hclk / 100) * (board->refresh / 10); | ||
279 | refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale */ | ||
280 | refresh &= ((1 << 16) - 1); | ||
281 | |||
282 | s3c_freq_dbg("%s: refresh value %u\n", __func__, (unsigned int)refresh); | ||
283 | |||
284 | __raw_writel(refresh, S3C2412_REFRESH); | ||
285 | } | ||
diff --git a/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c b/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c new file mode 100644 index 000000000000..ae2e6c604f27 --- /dev/null +++ b/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c | |||
@@ -0,0 +1,311 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c | ||
2 | * | ||
3 | * Copyright (c) 2006,2008,2009 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * Vincent Sanders <vince@simtec.co.uk> | ||
7 | * | ||
8 | * S3C2440/S3C2442 CPU Frequency scaling | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/init.h> | ||
16 | #include <linux/module.h> | ||
17 | #include <linux/interrupt.h> | ||
18 | #include <linux/ioport.h> | ||
19 | #include <linux/cpufreq.h> | ||
20 | #include <linux/sysdev.h> | ||
21 | #include <linux/delay.h> | ||
22 | #include <linux/clk.h> | ||
23 | #include <linux/err.h> | ||
24 | #include <linux/io.h> | ||
25 | |||
26 | #include <mach/hardware.h> | ||
27 | |||
28 | #include <asm/mach/arch.h> | ||
29 | #include <asm/mach/map.h> | ||
30 | |||
31 | #include <mach/regs-clock.h> | ||
32 | |||
33 | #include <plat/cpu.h> | ||
34 | #include <plat/cpu-freq-core.h> | ||
35 | #include <plat/clock.h> | ||
36 | |||
37 | static struct clk *xtal; | ||
38 | static struct clk *fclk; | ||
39 | static struct clk *hclk; | ||
40 | static struct clk *armclk; | ||
41 | |||
42 | /* HDIV: 1, 2, 3, 4, 6, 8 */ | ||
43 | |||
44 | static inline int within_khz(unsigned long a, unsigned long b) | ||
45 | { | ||
46 | long diff = a - b; | ||
47 | |||
48 | return (diff >= -1000 && diff <= 1000); | ||
49 | } | ||
50 | |||
51 | /** | ||
52 | * s3c2440_cpufreq_calcdivs - calculate divider settings | ||
53 | * @cfg: The cpu frequency settings. | ||
54 | * | ||
55 | * Calcualte the divider values for the given frequency settings | ||
56 | * specified in @cfg. The values are stored in @cfg for later use | ||
57 | * by the relevant set routine if the request settings can be reached. | ||
58 | */ | ||
59 | int s3c2440_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) | ||
60 | { | ||
61 | unsigned int hdiv, pdiv; | ||
62 | unsigned long hclk, fclk, armclk; | ||
63 | unsigned long hclk_max; | ||
64 | |||
65 | fclk = cfg->freq.fclk; | ||
66 | armclk = cfg->freq.armclk; | ||
67 | hclk_max = cfg->max.hclk; | ||
68 | |||
69 | s3c_freq_dbg("%s: fclk is %lu, armclk %lu, max hclk %lu\n", | ||
70 | __func__, fclk, armclk, hclk_max); | ||
71 | |||
72 | if (armclk > fclk) { | ||
73 | printk(KERN_WARNING "%s: armclk > fclk\n", __func__); | ||
74 | armclk = fclk; | ||
75 | } | ||
76 | |||
77 | /* if we are in DVS, we need HCLK to be <= ARMCLK */ | ||
78 | if (armclk < fclk && armclk < hclk_max) | ||
79 | hclk_max = armclk; | ||
80 | |||
81 | for (hdiv = 1; hdiv < 9; hdiv++) { | ||
82 | if (hdiv == 5 || hdiv == 7) | ||
83 | hdiv++; | ||
84 | |||
85 | hclk = (fclk / hdiv); | ||
86 | if (hclk <= hclk_max || within_khz(hclk, hclk_max)) | ||
87 | break; | ||
88 | } | ||
89 | |||
90 | s3c_freq_dbg("%s: hclk %lu, div %d\n", __func__, hclk, hdiv); | ||
91 | |||
92 | if (hdiv > 8) | ||
93 | goto invalid; | ||
94 | |||
95 | pdiv = (hclk > cfg->max.pclk) ? 2 : 1; | ||
96 | |||
97 | if ((hclk / pdiv) > cfg->max.pclk) | ||
98 | pdiv++; | ||
99 | |||
100 | s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv); | ||
101 | |||
102 | if (pdiv > 2) | ||
103 | goto invalid; | ||
104 | |||
105 | pdiv *= hdiv; | ||
106 | |||
107 | /* calculate a valid armclk */ | ||
108 | |||
109 | if (armclk < hclk) | ||
110 | armclk = hclk; | ||
111 | |||
112 | /* if we're running armclk lower than fclk, this really means | ||
113 | * that the system should go into dvs mode, which means that | ||
114 | * armclk is connected to hclk. */ | ||
115 | if (armclk < fclk) { | ||
116 | cfg->divs.dvs = 1; | ||
117 | armclk = hclk; | ||
118 | } else | ||
119 | cfg->divs.dvs = 0; | ||
120 | |||
121 | cfg->freq.armclk = armclk; | ||
122 | |||
123 | /* store the result, and then return */ | ||
124 | |||
125 | cfg->divs.h_divisor = hdiv; | ||
126 | cfg->divs.p_divisor = pdiv; | ||
127 | |||
128 | return 0; | ||
129 | |||
130 | invalid: | ||
131 | return -EINVAL; | ||
132 | } | ||
133 | |||
134 | #define CAMDIVN_HCLK_HALF (S3C2440_CAMDIVN_HCLK3_HALF | \ | ||
135 | S3C2440_CAMDIVN_HCLK4_HALF) | ||
136 | |||
137 | /** | ||
138 | * s3c2440_cpufreq_setdivs - set the cpu frequency divider settings | ||
139 | * @cfg: The cpu frequency settings. | ||
140 | * | ||
141 | * Set the divisors from the settings in @cfg, which where generated | ||
142 | * during the calculation phase by s3c2440_cpufreq_calcdivs(). | ||
143 | */ | ||
144 | static void s3c2440_cpufreq_setdivs(struct s3c_cpufreq_config *cfg) | ||
145 | { | ||
146 | unsigned long clkdiv, camdiv; | ||
147 | |||
148 | s3c_freq_dbg("%s: divsiors: h=%d, p=%d\n", __func__, | ||
149 | cfg->divs.h_divisor, cfg->divs.p_divisor); | ||
150 | |||
151 | clkdiv = __raw_readl(S3C2410_CLKDIVN); | ||
152 | camdiv = __raw_readl(S3C2440_CAMDIVN); | ||
153 | |||
154 | clkdiv &= ~(S3C2440_CLKDIVN_HDIVN_MASK | S3C2440_CLKDIVN_PDIVN); | ||
155 | camdiv &= ~CAMDIVN_HCLK_HALF; | ||
156 | |||
157 | switch (cfg->divs.h_divisor) { | ||
158 | case 1: | ||
159 | clkdiv |= S3C2440_CLKDIVN_HDIVN_1; | ||
160 | break; | ||
161 | |||
162 | case 2: | ||
163 | clkdiv |= S3C2440_CLKDIVN_HDIVN_2; | ||
164 | break; | ||
165 | |||
166 | case 6: | ||
167 | camdiv |= S3C2440_CAMDIVN_HCLK3_HALF; | ||
168 | case 3: | ||
169 | clkdiv |= S3C2440_CLKDIVN_HDIVN_3_6; | ||
170 | break; | ||
171 | |||
172 | case 8: | ||
173 | camdiv |= S3C2440_CAMDIVN_HCLK4_HALF; | ||
174 | case 4: | ||
175 | clkdiv |= S3C2440_CLKDIVN_HDIVN_4_8; | ||
176 | break; | ||
177 | |||
178 | default: | ||
179 | BUG(); /* we don't expect to get here. */ | ||
180 | } | ||
181 | |||
182 | if (cfg->divs.p_divisor != cfg->divs.h_divisor) | ||
183 | clkdiv |= S3C2440_CLKDIVN_PDIVN; | ||
184 | |||
185 | /* todo - set pclk. */ | ||
186 | |||
187 | /* Write the divisors first with hclk intentionally halved so that | ||
188 | * when we write clkdiv we will under-frequency instead of over. We | ||
189 | * then make a short delay and remove the hclk halving if necessary. | ||
190 | */ | ||
191 | |||
192 | __raw_writel(camdiv | CAMDIVN_HCLK_HALF, S3C2440_CAMDIVN); | ||
193 | __raw_writel(clkdiv, S3C2410_CLKDIVN); | ||
194 | |||
195 | ndelay(20); | ||
196 | __raw_writel(camdiv, S3C2440_CAMDIVN); | ||
197 | |||
198 | clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk); | ||
199 | } | ||
200 | |||
201 | static int run_freq_for(unsigned long max_hclk, unsigned long fclk, | ||
202 | int *divs, | ||
203 | struct cpufreq_frequency_table *table, | ||
204 | size_t table_size) | ||
205 | { | ||
206 | unsigned long freq; | ||
207 | int index = 0; | ||
208 | int div; | ||
209 | |||
210 | for (div = *divs; div > 0; div = *divs++) { | ||
211 | freq = fclk / div; | ||
212 | |||
213 | if (freq > max_hclk && div != 1) | ||
214 | continue; | ||
215 | |||
216 | freq /= 1000; /* table is in kHz */ | ||
217 | index = s3c_cpufreq_addfreq(table, index, table_size, freq); | ||
218 | if (index < 0) | ||
219 | break; | ||
220 | } | ||
221 | |||
222 | return index; | ||
223 | } | ||
224 | |||
225 | static int hclk_divs[] = { 1, 2, 3, 4, 6, 8, -1 }; | ||
226 | |||
227 | static int s3c2440_cpufreq_calctable(struct s3c_cpufreq_config *cfg, | ||
228 | struct cpufreq_frequency_table *table, | ||
229 | size_t table_size) | ||
230 | { | ||
231 | int ret; | ||
232 | |||
233 | WARN_ON(cfg->info == NULL); | ||
234 | WARN_ON(cfg->board == NULL); | ||
235 | |||
236 | ret = run_freq_for(cfg->info->max.hclk, | ||
237 | cfg->info->max.fclk, | ||
238 | hclk_divs, | ||
239 | table, table_size); | ||
240 | |||
241 | s3c_freq_dbg("%s: returning %d\n", __func__, ret); | ||
242 | |||
243 | return ret; | ||
244 | } | ||
245 | |||
246 | struct s3c_cpufreq_info s3c2440_cpufreq_info = { | ||
247 | .max = { | ||
248 | .fclk = 400000000, | ||
249 | .hclk = 133333333, | ||
250 | .pclk = 66666666, | ||
251 | }, | ||
252 | |||
253 | .locktime_m = 300, | ||
254 | .locktime_u = 300, | ||
255 | .locktime_bits = 16, | ||
256 | |||
257 | .name = "s3c244x", | ||
258 | .calc_iotiming = s3c2410_iotiming_calc, | ||
259 | .set_iotiming = s3c2410_iotiming_set, | ||
260 | .get_iotiming = s3c2410_iotiming_get, | ||
261 | .set_fvco = s3c2410_set_fvco, | ||
262 | |||
263 | .set_refresh = s3c2410_cpufreq_setrefresh, | ||
264 | .set_divs = s3c2440_cpufreq_setdivs, | ||
265 | .calc_divs = s3c2440_cpufreq_calcdivs, | ||
266 | .calc_freqtable = s3c2440_cpufreq_calctable, | ||
267 | |||
268 | .resume_clocks = s3c244x_setup_clocks, | ||
269 | |||
270 | .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), | ||
271 | }; | ||
272 | |||
273 | static int s3c2440_cpufreq_add(struct sys_device *sysdev) | ||
274 | { | ||
275 | xtal = s3c_cpufreq_clk_get(NULL, "xtal"); | ||
276 | hclk = s3c_cpufreq_clk_get(NULL, "hclk"); | ||
277 | fclk = s3c_cpufreq_clk_get(NULL, "fclk"); | ||
278 | armclk = s3c_cpufreq_clk_get(NULL, "armclk"); | ||
279 | |||
280 | if (IS_ERR(xtal) || IS_ERR(hclk) || IS_ERR(fclk) || IS_ERR(armclk)) { | ||
281 | printk(KERN_ERR "%s: failed to get clocks\n", __func__); | ||
282 | return -ENOENT; | ||
283 | } | ||
284 | |||
285 | return s3c_cpufreq_register(&s3c2440_cpufreq_info); | ||
286 | } | ||
287 | |||
288 | static struct sysdev_driver s3c2440_cpufreq_driver = { | ||
289 | .add = s3c2440_cpufreq_add, | ||
290 | }; | ||
291 | |||
292 | static int s3c2440_cpufreq_init(void) | ||
293 | { | ||
294 | return sysdev_driver_register(&s3c2440_sysclass, | ||
295 | &s3c2440_cpufreq_driver); | ||
296 | } | ||
297 | |||
298 | /* arch_initcall adds the clocks we need, so use subsys_initcall. */ | ||
299 | subsys_initcall(s3c2440_cpufreq_init); | ||
300 | |||
301 | static struct sysdev_driver s3c2442_cpufreq_driver = { | ||
302 | .add = s3c2440_cpufreq_add, | ||
303 | }; | ||
304 | |||
305 | static int s3c2442_cpufreq_init(void) | ||
306 | { | ||
307 | return sysdev_driver_register(&s3c2442_sysclass, | ||
308 | &s3c2442_cpufreq_driver); | ||
309 | } | ||
310 | |||
311 | subsys_initcall(s3c2442_cpufreq_init); | ||
diff --git a/arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c b/arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c new file mode 100644 index 000000000000..ff9443b233aa --- /dev/null +++ b/arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c | |||
@@ -0,0 +1,97 @@ | |||
1 | /* arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c | ||
2 | * | ||
3 | * Copyright (c) 2006,2007 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * Vincent Sanders <vince@arm.linux.org.uk> | ||
7 | * | ||
8 | * S3C2440/S3C2442 CPU PLL tables (12MHz Crystal) | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/types.h> | ||
16 | #include <linux/kernel.h> | ||
17 | #include <linux/sysdev.h> | ||
18 | #include <linux/clk.h> | ||
19 | #include <linux/err.h> | ||
20 | |||
21 | #include <plat/cpu.h> | ||
22 | #include <plat/cpu-freq-core.h> | ||
23 | |||
24 | static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = { | ||
25 | { .frequency = 75000000, .index = PLLVAL(0x75, 3, 3), }, /* FVco 600.000000 */ | ||
26 | { .frequency = 80000000, .index = PLLVAL(0x98, 4, 3), }, /* FVco 640.000000 */ | ||
27 | { .frequency = 90000000, .index = PLLVAL(0x70, 2, 3), }, /* FVco 720.000000 */ | ||
28 | { .frequency = 100000000, .index = PLLVAL(0x5c, 1, 3), }, /* FVco 800.000000 */ | ||
29 | { .frequency = 110000000, .index = PLLVAL(0x66, 1, 3), }, /* FVco 880.000000 */ | ||
30 | { .frequency = 120000000, .index = PLLVAL(0x70, 1, 3), }, /* FVco 960.000000 */ | ||
31 | { .frequency = 150000000, .index = PLLVAL(0x75, 3, 2), }, /* FVco 600.000000 */ | ||
32 | { .frequency = 160000000, .index = PLLVAL(0x98, 4, 2), }, /* FVco 640.000000 */ | ||
33 | { .frequency = 170000000, .index = PLLVAL(0x4d, 1, 2), }, /* FVco 680.000000 */ | ||
34 | { .frequency = 180000000, .index = PLLVAL(0x70, 2, 2), }, /* FVco 720.000000 */ | ||
35 | { .frequency = 190000000, .index = PLLVAL(0x57, 1, 2), }, /* FVco 760.000000 */ | ||
36 | { .frequency = 200000000, .index = PLLVAL(0x5c, 1, 2), }, /* FVco 800.000000 */ | ||
37 | { .frequency = 210000000, .index = PLLVAL(0x84, 2, 2), }, /* FVco 840.000000 */ | ||
38 | { .frequency = 220000000, .index = PLLVAL(0x66, 1, 2), }, /* FVco 880.000000 */ | ||
39 | { .frequency = 230000000, .index = PLLVAL(0x6b, 1, 2), }, /* FVco 920.000000 */ | ||
40 | { .frequency = 240000000, .index = PLLVAL(0x70, 1, 2), }, /* FVco 960.000000 */ | ||
41 | { .frequency = 300000000, .index = PLLVAL(0x75, 3, 1), }, /* FVco 600.000000 */ | ||
42 | { .frequency = 310000000, .index = PLLVAL(0x93, 4, 1), }, /* FVco 620.000000 */ | ||
43 | { .frequency = 320000000, .index = PLLVAL(0x98, 4, 1), }, /* FVco 640.000000 */ | ||
44 | { .frequency = 330000000, .index = PLLVAL(0x66, 2, 1), }, /* FVco 660.000000 */ | ||
45 | { .frequency = 340000000, .index = PLLVAL(0x4d, 1, 1), }, /* FVco 680.000000 */ | ||
46 | { .frequency = 350000000, .index = PLLVAL(0xa7, 4, 1), }, /* FVco 700.000000 */ | ||
47 | { .frequency = 360000000, .index = PLLVAL(0x70, 2, 1), }, /* FVco 720.000000 */ | ||
48 | { .frequency = 370000000, .index = PLLVAL(0xb1, 4, 1), }, /* FVco 740.000000 */ | ||
49 | { .frequency = 380000000, .index = PLLVAL(0x57, 1, 1), }, /* FVco 760.000000 */ | ||
50 | { .frequency = 390000000, .index = PLLVAL(0x7a, 2, 1), }, /* FVco 780.000000 */ | ||
51 | { .frequency = 400000000, .index = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */ | ||
52 | }; | ||
53 | |||
54 | static int s3c2440_plls12_add(struct sys_device *dev) | ||
55 | { | ||
56 | struct clk *xtal_clk; | ||
57 | unsigned long xtal; | ||
58 | |||
59 | xtal_clk = clk_get(NULL, "xtal"); | ||
60 | if (IS_ERR(xtal_clk)) | ||
61 | return PTR_ERR(xtal_clk); | ||
62 | |||
63 | xtal = clk_get_rate(xtal_clk); | ||
64 | clk_put(xtal_clk); | ||
65 | |||
66 | if (xtal == 12000000) { | ||
67 | printk(KERN_INFO "Using PLL table for 12MHz crystal\n"); | ||
68 | return s3c_plltab_register(s3c2440_plls_12, | ||
69 | ARRAY_SIZE(s3c2440_plls_12)); | ||
70 | } | ||
71 | |||
72 | return 0; | ||
73 | } | ||
74 | |||
75 | static struct sysdev_driver s3c2440_plls12_drv = { | ||
76 | .add = s3c2440_plls12_add, | ||
77 | }; | ||
78 | |||
79 | static int __init s3c2440_pll_12mhz(void) | ||
80 | { | ||
81 | return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_plls12_drv); | ||
82 | |||
83 | } | ||
84 | |||
85 | arch_initcall(s3c2440_pll_12mhz); | ||
86 | |||
87 | static struct sysdev_driver s3c2442_plls12_drv = { | ||
88 | .add = s3c2440_plls12_add, | ||
89 | }; | ||
90 | |||
91 | static int __init s3c2442_pll_12mhz(void) | ||
92 | { | ||
93 | return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_plls12_drv); | ||
94 | |||
95 | } | ||
96 | |||
97 | arch_initcall(s3c2442_pll_12mhz); | ||
diff --git a/arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c b/arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c new file mode 100644 index 000000000000..7679af13a94d --- /dev/null +++ b/arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c | |||
@@ -0,0 +1,127 @@ | |||
1 | /* arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c | ||
2 | * | ||
3 | * Copyright (c) 2006-2008 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * Vincent Sanders <vince@arm.linux.org.uk> | ||
7 | * | ||
8 | * S3C2440/S3C2442 CPU PLL tables (16.93444MHz Crystal) | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/types.h> | ||
16 | #include <linux/kernel.h> | ||
17 | #include <linux/sysdev.h> | ||
18 | #include <linux/clk.h> | ||
19 | #include <linux/err.h> | ||
20 | |||
21 | #include <plat/cpu.h> | ||
22 | #include <plat/cpu-freq-core.h> | ||
23 | |||
24 | static struct cpufreq_frequency_table s3c2440_plls_169344[] __initdata = { | ||
25 | { .frequency = 78019200, .index = PLLVAL(121, 5, 3), }, /* FVco 624.153600 */ | ||
26 | { .frequency = 84067200, .index = PLLVAL(131, 5, 3), }, /* FVco 672.537600 */ | ||
27 | { .frequency = 90115200, .index = PLLVAL(141, 5, 3), }, /* FVco 720.921600 */ | ||
28 | { .frequency = 96163200, .index = PLLVAL(151, 5, 3), }, /* FVco 769.305600 */ | ||
29 | { .frequency = 102135600, .index = PLLVAL(185, 6, 3), }, /* FVco 817.084800 */ | ||
30 | { .frequency = 108259200, .index = PLLVAL(171, 5, 3), }, /* FVco 866.073600 */ | ||
31 | { .frequency = 114307200, .index = PLLVAL(127, 3, 3), }, /* FVco 914.457600 */ | ||
32 | { .frequency = 120234240, .index = PLLVAL(134, 3, 3), }, /* FVco 961.873920 */ | ||
33 | { .frequency = 126161280, .index = PLLVAL(141, 3, 3), }, /* FVco 1009.290240 */ | ||
34 | { .frequency = 132088320, .index = PLLVAL(148, 3, 3), }, /* FVco 1056.706560 */ | ||
35 | { .frequency = 138015360, .index = PLLVAL(155, 3, 3), }, /* FVco 1104.122880 */ | ||
36 | { .frequency = 144789120, .index = PLLVAL(163, 3, 3), }, /* FVco 1158.312960 */ | ||
37 | { .frequency = 150100363, .index = PLLVAL(187, 9, 2), }, /* FVco 600.401454 */ | ||
38 | { .frequency = 156038400, .index = PLLVAL(121, 5, 2), }, /* FVco 624.153600 */ | ||
39 | { .frequency = 162086400, .index = PLLVAL(126, 5, 2), }, /* FVco 648.345600 */ | ||
40 | { .frequency = 168134400, .index = PLLVAL(131, 5, 2), }, /* FVco 672.537600 */ | ||
41 | { .frequency = 174048000, .index = PLLVAL(177, 7, 2), }, /* FVco 696.192000 */ | ||
42 | { .frequency = 180230400, .index = PLLVAL(141, 5, 2), }, /* FVco 720.921600 */ | ||
43 | { .frequency = 186278400, .index = PLLVAL(124, 4, 2), }, /* FVco 745.113600 */ | ||
44 | { .frequency = 192326400, .index = PLLVAL(151, 5, 2), }, /* FVco 769.305600 */ | ||
45 | { .frequency = 198132480, .index = PLLVAL(109, 3, 2), }, /* FVco 792.529920 */ | ||
46 | { .frequency = 204271200, .index = PLLVAL(185, 6, 2), }, /* FVco 817.084800 */ | ||
47 | { .frequency = 210268800, .index = PLLVAL(141, 4, 2), }, /* FVco 841.075200 */ | ||
48 | { .frequency = 216518400, .index = PLLVAL(171, 5, 2), }, /* FVco 866.073600 */ | ||
49 | { .frequency = 222264000, .index = PLLVAL(97, 2, 2), }, /* FVco 889.056000 */ | ||
50 | { .frequency = 228614400, .index = PLLVAL(127, 3, 2), }, /* FVco 914.457600 */ | ||
51 | { .frequency = 234259200, .index = PLLVAL(158, 4, 2), }, /* FVco 937.036800 */ | ||
52 | { .frequency = 240468480, .index = PLLVAL(134, 3, 2), }, /* FVco 961.873920 */ | ||
53 | { .frequency = 246960000, .index = PLLVAL(167, 4, 2), }, /* FVco 987.840000 */ | ||
54 | { .frequency = 252322560, .index = PLLVAL(141, 3, 2), }, /* FVco 1009.290240 */ | ||
55 | { .frequency = 258249600, .index = PLLVAL(114, 2, 2), }, /* FVco 1032.998400 */ | ||
56 | { .frequency = 264176640, .index = PLLVAL(148, 3, 2), }, /* FVco 1056.706560 */ | ||
57 | { .frequency = 270950400, .index = PLLVAL(120, 2, 2), }, /* FVco 1083.801600 */ | ||
58 | { .frequency = 276030720, .index = PLLVAL(155, 3, 2), }, /* FVco 1104.122880 */ | ||
59 | { .frequency = 282240000, .index = PLLVAL(92, 1, 2), }, /* FVco 1128.960000 */ | ||
60 | { .frequency = 289578240, .index = PLLVAL(163, 3, 2), }, /* FVco 1158.312960 */ | ||
61 | { .frequency = 294235200, .index = PLLVAL(131, 2, 2), }, /* FVco 1176.940800 */ | ||
62 | { .frequency = 300200727, .index = PLLVAL(187, 9, 1), }, /* FVco 600.401454 */ | ||
63 | { .frequency = 306358690, .index = PLLVAL(191, 9, 1), }, /* FVco 612.717380 */ | ||
64 | { .frequency = 312076800, .index = PLLVAL(121, 5, 1), }, /* FVco 624.153600 */ | ||
65 | { .frequency = 318366720, .index = PLLVAL(86, 3, 1), }, /* FVco 636.733440 */ | ||
66 | { .frequency = 324172800, .index = PLLVAL(126, 5, 1), }, /* FVco 648.345600 */ | ||
67 | { .frequency = 330220800, .index = PLLVAL(109, 4, 1), }, /* FVco 660.441600 */ | ||
68 | { .frequency = 336268800, .index = PLLVAL(131, 5, 1), }, /* FVco 672.537600 */ | ||
69 | { .frequency = 342074880, .index = PLLVAL(93, 3, 1), }, /* FVco 684.149760 */ | ||
70 | { .frequency = 348096000, .index = PLLVAL(177, 7, 1), }, /* FVco 696.192000 */ | ||
71 | { .frequency = 355622400, .index = PLLVAL(118, 4, 1), }, /* FVco 711.244800 */ | ||
72 | { .frequency = 360460800, .index = PLLVAL(141, 5, 1), }, /* FVco 720.921600 */ | ||
73 | { .frequency = 366206400, .index = PLLVAL(165, 6, 1), }, /* FVco 732.412800 */ | ||
74 | { .frequency = 372556800, .index = PLLVAL(124, 4, 1), }, /* FVco 745.113600 */ | ||
75 | { .frequency = 378201600, .index = PLLVAL(126, 4, 1), }, /* FVco 756.403200 */ | ||
76 | { .frequency = 384652800, .index = PLLVAL(151, 5, 1), }, /* FVco 769.305600 */ | ||
77 | { .frequency = 391608000, .index = PLLVAL(177, 6, 1), }, /* FVco 783.216000 */ | ||
78 | { .frequency = 396264960, .index = PLLVAL(109, 3, 1), }, /* FVco 792.529920 */ | ||
79 | { .frequency = 402192000, .index = PLLVAL(87, 2, 1), }, /* FVco 804.384000 */ | ||
80 | }; | ||
81 | |||
82 | static int s3c2440_plls169344_add(struct sys_device *dev) | ||
83 | { | ||
84 | struct clk *xtal_clk; | ||
85 | unsigned long xtal; | ||
86 | |||
87 | xtal_clk = clk_get(NULL, "xtal"); | ||
88 | if (IS_ERR(xtal_clk)) | ||
89 | return PTR_ERR(xtal_clk); | ||
90 | |||
91 | xtal = clk_get_rate(xtal_clk); | ||
92 | clk_put(xtal_clk); | ||
93 | |||
94 | if (xtal == 169344000) { | ||
95 | printk(KERN_INFO "Using PLL table for 16.9344MHz crystal\n"); | ||
96 | return s3c_plltab_register(s3c2440_plls_169344, | ||
97 | ARRAY_SIZE(s3c2440_plls_169344)); | ||
98 | } | ||
99 | |||
100 | return 0; | ||
101 | } | ||
102 | |||
103 | static struct sysdev_driver s3c2440_plls169344_drv = { | ||
104 | .add = s3c2440_plls169344_add, | ||
105 | }; | ||
106 | |||
107 | static int __init s3c2440_pll_16934400(void) | ||
108 | { | ||
109 | return sysdev_driver_register(&s3c2440_sysclass, | ||
110 | &s3c2440_plls169344_drv); | ||
111 | |||
112 | } | ||
113 | |||
114 | arch_initcall(s3c2440_pll_16934400); | ||
115 | |||
116 | static struct sysdev_driver s3c2442_plls169344_drv = { | ||
117 | .add = s3c2440_plls169344_add, | ||
118 | }; | ||
119 | |||
120 | static int __init s3c2442_pll_16934400(void) | ||
121 | { | ||
122 | return sysdev_driver_register(&s3c2442_sysclass, | ||
123 | &s3c2442_plls169344_drv); | ||
124 | |||
125 | } | ||
126 | |||
127 | arch_initcall(s3c2442_pll_16934400); | ||
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c b/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c new file mode 100644 index 000000000000..89fcf5308cf6 --- /dev/null +++ b/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c | |||
@@ -0,0 +1,38 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/spi-bus0-gpd8_9_10.c | ||
2 | * | ||
3 | * Copyright (c) 2008 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C24XX SPI - gpio configuration for bus 1 on gpd8,9,10 | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License. | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/gpio.h> | ||
16 | |||
17 | #include <mach/spi.h> | ||
18 | #include <mach/regs-gpio.h> | ||
19 | |||
20 | void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi, | ||
21 | int enable) | ||
22 | { | ||
23 | |||
24 | printk(KERN_INFO "%s(%d)\n", __func__, enable); | ||
25 | if (enable) { | ||
26 | s3c2410_gpio_cfgpin(S3C2410_GPD(10), S3C2440_GPD10_SPICLK1); | ||
27 | s3c2410_gpio_cfgpin(S3C2410_GPD(9), S3C2440_GPD9_SPIMOSI1); | ||
28 | s3c2410_gpio_cfgpin(S3C2410_GPD(8), S3C2440_GPD8_SPIMISO1); | ||
29 | s3c2410_gpio_pullup(S3C2410_GPD(10), 0); | ||
30 | s3c2410_gpio_pullup(S3C2410_GPD(9), 0); | ||
31 | } else { | ||
32 | s3c2410_gpio_cfgpin(S3C2410_GPD(8), S3C2410_GPIO_INPUT); | ||
33 | s3c2410_gpio_cfgpin(S3C2410_GPD(9), S3C2410_GPIO_INPUT); | ||
34 | s3c2410_gpio_pullup(S3C2410_GPD(10), 1); | ||
35 | s3c2410_gpio_pullup(S3C2410_GPD(9), 1); | ||
36 | s3c2410_gpio_pullup(S3C2410_GPD(8), 1); | ||
37 | } | ||
38 | } | ||
diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig index 5ebd8b425a54..bcfa778614d8 100644 --- a/arch/arm/plat-s3c64xx/Kconfig +++ b/arch/arm/plat-s3c64xx/Kconfig | |||
@@ -19,6 +19,7 @@ config PLAT_S3C64XX | |||
19 | select S3C_GPIO_PULL_UPDOWN | 19 | select S3C_GPIO_PULL_UPDOWN |
20 | select S3C_GPIO_CFG_S3C24XX | 20 | select S3C_GPIO_CFG_S3C24XX |
21 | select S3C_GPIO_CFG_S3C64XX | 21 | select S3C_GPIO_CFG_S3C64XX |
22 | select S3C_DEV_NAND | ||
22 | select USB_ARCH_HAS_OHCI | 23 | select USB_ARCH_HAS_OHCI |
23 | help | 24 | help |
24 | Base platform code for any Samsung S3C64XX device | 25 | Base platform code for any Samsung S3C64XX device |
diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile index 3c8882cd6268..b85b4359e935 100644 --- a/arch/arm/plat-s3c64xx/Makefile +++ b/arch/arm/plat-s3c64xx/Makefile | |||
@@ -40,4 +40,5 @@ obj-$(CONFIG_S3C64XX_DMA) += dma.o | |||
40 | obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o | 40 | obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o |
41 | obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o | 41 | obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o |
42 | obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o | 42 | obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o |
43 | obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o \ No newline at end of file | 43 | obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o |
44 | obj-$(CONFIG_SND_S3C24XX_SOC) += dev-audio.o | ||
diff --git a/arch/arm/plat-s3c/dev-audio.c b/arch/arm/plat-s3c64xx/dev-audio.c index 1322beb40dd7..1322beb40dd7 100644 --- a/arch/arm/plat-s3c/dev-audio.c +++ b/arch/arm/plat-s3c64xx/dev-audio.c | |||
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c index 1debc1f9f987..febac1950d8e 100644 --- a/arch/arm/plat-s3c64xx/s3c6400-clock.c +++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c | |||
@@ -153,7 +153,7 @@ static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk, | |||
153 | u32 div; | 153 | u32 div; |
154 | 154 | ||
155 | if (parent < rate) | 155 | if (parent < rate) |
156 | return rate; | 156 | return parent; |
157 | 157 | ||
158 | div = (parent / rate) - 1; | 158 | div = (parent / rate) - 1; |
159 | if (div > armclk_mask) | 159 | if (div > armclk_mask) |
@@ -175,7 +175,7 @@ static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate) | |||
175 | div = clk_get_rate(clk->parent) / rate; | 175 | div = clk_get_rate(clk->parent) / rate; |
176 | 176 | ||
177 | val = __raw_readl(S3C_CLK_DIV0); | 177 | val = __raw_readl(S3C_CLK_DIV0); |
178 | val &= armclk_mask; | 178 | val &= ~armclk_mask; |
179 | val |= (div - 1); | 179 | val |= (div - 1); |
180 | __raw_writel(val, S3C_CLK_DIV0); | 180 | __raw_writel(val, S3C_CLK_DIV0); |
181 | 181 | ||
diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig new file mode 100644 index 000000000000..a8a711c3c064 --- /dev/null +++ b/arch/arm/plat-s5pc1xx/Kconfig | |||
@@ -0,0 +1,50 @@ | |||
1 | # arch/arm/plat-s5pc1xx/Kconfig | ||
2 | # | ||
3 | # Copyright 2009 Samsung Electronics Co. | ||
4 | # Byungho Min <bhmin@samsung.com> | ||
5 | # | ||
6 | # Licensed under GPLv2 | ||
7 | |||
8 | config PLAT_S5PC1XX | ||
9 | bool | ||
10 | depends on ARCH_S5PC1XX | ||
11 | default y | ||
12 | select PLAT_S3C | ||
13 | select ARM_VIC | ||
14 | select NO_IOPORT | ||
15 | select ARCH_REQUIRE_GPIOLIB | ||
16 | select S3C_GPIO_TRACK | ||
17 | select S3C_GPIO_PULL_UPDOWN | ||
18 | help | ||
19 | Base platform code for any Samsung S5PC1XX device | ||
20 | |||
21 | if PLAT_S5PC1XX | ||
22 | |||
23 | # Configuration options shared by all S3C64XX implementations | ||
24 | |||
25 | config CPU_S5PC100_INIT | ||
26 | bool | ||
27 | help | ||
28 | Common initialisation code for the S5PC1XX | ||
29 | |||
30 | config CPU_S5PC100_CLOCK | ||
31 | bool | ||
32 | help | ||
33 | Common clock support code for the S5PC1XX | ||
34 | |||
35 | # platform specific device setup | ||
36 | |||
37 | config S5PC100_SETUP_I2C0 | ||
38 | bool | ||
39 | default y | ||
40 | help | ||
41 | Common setup code for i2c bus 0. | ||
42 | |||
43 | Note, currently since i2c0 is always compiled, this setup helper | ||
44 | is always compiled with it. | ||
45 | |||
46 | config S5PC100_SETUP_I2C1 | ||
47 | bool | ||
48 | help | ||
49 | Common setup code for i2c bus 1. | ||
50 | endif | ||
diff --git a/arch/arm/plat-s5pc1xx/Makefile b/arch/arm/plat-s5pc1xx/Makefile new file mode 100644 index 000000000000..f1ecb2c37ee2 --- /dev/null +++ b/arch/arm/plat-s5pc1xx/Makefile | |||
@@ -0,0 +1,26 @@ | |||
1 | # arch/arm/plat-s5pc1xx/Makefile | ||
2 | # | ||
3 | # Copyright 2009 Samsung Electronics Co. | ||
4 | # | ||
5 | # Licensed under GPLv2 | ||
6 | |||
7 | obj-y := | ||
8 | obj-m := | ||
9 | obj-n := dummy.o | ||
10 | obj- := | ||
11 | |||
12 | # Core files | ||
13 | |||
14 | obj-y += dev-uart.o | ||
15 | obj-y += cpu.o | ||
16 | obj-y += irq.o | ||
17 | |||
18 | # CPU support | ||
19 | |||
20 | obj-$(CONFIG_CPU_S5PC100_INIT) += s5pc100-init.o | ||
21 | obj-$(CONFIG_CPU_S5PC100_CLOCK) += s5pc100-clock.o | ||
22 | |||
23 | # Device setup | ||
24 | |||
25 | obj-$(CONFIG_S5PC100_SETUP_I2C0) += setup-i2c0.o | ||
26 | obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o | ||
diff --git a/arch/arm/plat-s5pc1xx/cpu.c b/arch/arm/plat-s5pc1xx/cpu.c new file mode 100644 index 000000000000..715a7330794d --- /dev/null +++ b/arch/arm/plat-s5pc1xx/cpu.c | |||
@@ -0,0 +1,112 @@ | |||
1 | /* linux/arch/arm/plat-s5pc1xx/cpu.c | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * S5PC1XX CPU Support | ||
7 | * | ||
8 | * Based on plat-s3c64xx/cpu.c | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/init.h> | ||
16 | #include <linux/module.h> | ||
17 | #include <linux/interrupt.h> | ||
18 | #include <linux/ioport.h> | ||
19 | #include <linux/serial_core.h> | ||
20 | #include <linux/platform_device.h> | ||
21 | #include <linux/io.h> | ||
22 | |||
23 | #include <mach/hardware.h> | ||
24 | #include <mach/map.h> | ||
25 | |||
26 | #include <asm/mach/map.h> | ||
27 | |||
28 | #include <plat/regs-serial.h> | ||
29 | |||
30 | #include <plat/cpu.h> | ||
31 | #include <plat/devs.h> | ||
32 | #include <plat/clock.h> | ||
33 | |||
34 | #include <plat/s5pc100.h> | ||
35 | |||
36 | /* table of supported CPUs */ | ||
37 | |||
38 | static const char name_s5pc100[] = "S5PC100"; | ||
39 | |||
40 | static struct cpu_table cpu_ids[] __initdata = { | ||
41 | { | ||
42 | .idcode = 0x43100000, | ||
43 | .idmask = 0xfffff000, | ||
44 | .map_io = s5pc100_map_io, | ||
45 | .init_clocks = s5pc100_init_clocks, | ||
46 | .init_uarts = s5pc100_init_uarts, | ||
47 | .init = s5pc100_init, | ||
48 | .name = name_s5pc100, | ||
49 | }, | ||
50 | }; | ||
51 | /* minimal IO mapping */ | ||
52 | |||
53 | /* see notes on uart map in arch/arm/mach-s5pc100/include/mach/debug-macro.S */ | ||
54 | #define UART_OFFS (S3C_PA_UART & 0xffff) | ||
55 | |||
56 | static struct map_desc s5pc1xx_iodesc[] __initdata = { | ||
57 | { | ||
58 | .virtual = (unsigned long)S5PC1XX_VA_CHIPID, | ||
59 | .pfn = __phys_to_pfn(S5PC1XX_PA_CHIPID), | ||
60 | .length = SZ_16, | ||
61 | .type = MT_DEVICE, | ||
62 | }, { | ||
63 | .virtual = (unsigned long)S5PC1XX_VA_CLK, | ||
64 | .pfn = __phys_to_pfn(S5PC1XX_PA_CLK), | ||
65 | .length = SZ_4K, | ||
66 | .type = MT_DEVICE, | ||
67 | }, { | ||
68 | .virtual = (unsigned long)S5PC1XX_VA_PWR, | ||
69 | .pfn = __phys_to_pfn(S5PC1XX_PA_PWR), | ||
70 | .length = SZ_4K, | ||
71 | .type = MT_DEVICE, | ||
72 | }, { | ||
73 | .virtual = (unsigned long)(S5PC1XX_VA_UART), | ||
74 | .pfn = __phys_to_pfn(S5PC1XX_PA_UART), | ||
75 | .length = SZ_4K, | ||
76 | .type = MT_DEVICE, | ||
77 | }, { | ||
78 | .virtual = (unsigned long)S5PC1XX_VA_VIC(0), | ||
79 | .pfn = __phys_to_pfn(S5PC1XX_PA_VIC(0)), | ||
80 | .length = SZ_4K, | ||
81 | .type = MT_DEVICE, | ||
82 | }, { | ||
83 | .virtual = (unsigned long)S5PC1XX_VA_VIC(1), | ||
84 | .pfn = __phys_to_pfn(S5PC1XX_PA_VIC(1)), | ||
85 | .length = SZ_4K, | ||
86 | .type = MT_DEVICE, | ||
87 | }, { | ||
88 | .virtual = (unsigned long)S5PC1XX_VA_VIC(2), | ||
89 | .pfn = __phys_to_pfn(S5PC1XX_PA_VIC(2)), | ||
90 | .length = SZ_4K, | ||
91 | .type = MT_DEVICE, | ||
92 | }, { | ||
93 | .virtual = (unsigned long)S5PC1XX_VA_TIMER, | ||
94 | .pfn = __phys_to_pfn(S5PC1XX_PA_TIMER), | ||
95 | .length = SZ_256, | ||
96 | .type = MT_DEVICE, | ||
97 | }, | ||
98 | }; | ||
99 | |||
100 | /* read cpu identification code */ | ||
101 | |||
102 | void __init s5pc1xx_init_io(struct map_desc *mach_desc, int size) | ||
103 | { | ||
104 | unsigned long idcode; | ||
105 | |||
106 | /* initialise the io descriptors we need for initialisation */ | ||
107 | iotable_init(s5pc1xx_iodesc, ARRAY_SIZE(s5pc1xx_iodesc)); | ||
108 | iotable_init(mach_desc, size); | ||
109 | |||
110 | idcode = __raw_readl(S5PC1XX_VA_CHIPID); | ||
111 | s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); | ||
112 | } | ||
diff --git a/arch/arm/plat-s5pc1xx/dev-uart.c b/arch/arm/plat-s5pc1xx/dev-uart.c new file mode 100644 index 000000000000..f749bc5407b5 --- /dev/null +++ b/arch/arm/plat-s5pc1xx/dev-uart.c | |||
@@ -0,0 +1,174 @@ | |||
1 | /* linux/arch/arm/plat-s5pc1xx/dev-uart.c | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * Based on plat-s3c64xx/dev-uart.c | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/types.h> | ||
16 | #include <linux/interrupt.h> | ||
17 | #include <linux/list.h> | ||
18 | #include <linux/platform_device.h> | ||
19 | |||
20 | #include <asm/mach/arch.h> | ||
21 | #include <asm/mach/irq.h> | ||
22 | #include <mach/hardware.h> | ||
23 | #include <mach/map.h> | ||
24 | |||
25 | #include <plat/devs.h> | ||
26 | |||
27 | /* Serial port registrations */ | ||
28 | |||
29 | /* 64xx uarts are closer together */ | ||
30 | |||
31 | static struct resource s5pc1xx_uart0_resource[] = { | ||
32 | [0] = { | ||
33 | .start = S3C_PA_UART0, | ||
34 | .end = S3C_PA_UART0 + 0x100, | ||
35 | .flags = IORESOURCE_MEM, | ||
36 | }, | ||
37 | [1] = { | ||
38 | .start = IRQ_S3CUART_RX0, | ||
39 | .end = IRQ_S3CUART_RX0, | ||
40 | .flags = IORESOURCE_IRQ, | ||
41 | }, | ||
42 | [2] = { | ||
43 | .start = IRQ_S3CUART_TX0, | ||
44 | .end = IRQ_S3CUART_TX0, | ||
45 | .flags = IORESOURCE_IRQ, | ||
46 | |||
47 | }, | ||
48 | [3] = { | ||
49 | .start = IRQ_S3CUART_ERR0, | ||
50 | .end = IRQ_S3CUART_ERR0, | ||
51 | .flags = IORESOURCE_IRQ, | ||
52 | } | ||
53 | }; | ||
54 | |||
55 | static struct resource s5pc1xx_uart1_resource[] = { | ||
56 | [0] = { | ||
57 | .start = S3C_PA_UART1, | ||
58 | .end = S3C_PA_UART1 + 0x100, | ||
59 | .flags = IORESOURCE_MEM, | ||
60 | }, | ||
61 | [1] = { | ||
62 | .start = IRQ_S3CUART_RX1, | ||
63 | .end = IRQ_S3CUART_RX1, | ||
64 | .flags = IORESOURCE_IRQ, | ||
65 | }, | ||
66 | [2] = { | ||
67 | .start = IRQ_S3CUART_TX1, | ||
68 | .end = IRQ_S3CUART_TX1, | ||
69 | .flags = IORESOURCE_IRQ, | ||
70 | |||
71 | }, | ||
72 | [3] = { | ||
73 | .start = IRQ_S3CUART_ERR1, | ||
74 | .end = IRQ_S3CUART_ERR1, | ||
75 | .flags = IORESOURCE_IRQ, | ||
76 | }, | ||
77 | }; | ||
78 | |||
79 | static struct resource s5pc1xx_uart2_resource[] = { | ||
80 | [0] = { | ||
81 | .start = S3C_PA_UART2, | ||
82 | .end = S3C_PA_UART2 + 0x100, | ||
83 | .flags = IORESOURCE_MEM, | ||
84 | }, | ||
85 | [1] = { | ||
86 | .start = IRQ_S3CUART_RX2, | ||
87 | .end = IRQ_S3CUART_RX2, | ||
88 | .flags = IORESOURCE_IRQ, | ||
89 | }, | ||
90 | [2] = { | ||
91 | .start = IRQ_S3CUART_TX2, | ||
92 | .end = IRQ_S3CUART_TX2, | ||
93 | .flags = IORESOURCE_IRQ, | ||
94 | |||
95 | }, | ||
96 | [3] = { | ||
97 | .start = IRQ_S3CUART_ERR2, | ||
98 | .end = IRQ_S3CUART_ERR2, | ||
99 | .flags = IORESOURCE_IRQ, | ||
100 | }, | ||
101 | }; | ||
102 | |||
103 | static struct resource s5pc1xx_uart3_resource[] = { | ||
104 | [0] = { | ||
105 | .start = S3C_PA_UART3, | ||
106 | .end = S3C_PA_UART3 + 0x100, | ||
107 | .flags = IORESOURCE_MEM, | ||
108 | }, | ||
109 | [1] = { | ||
110 | .start = IRQ_S3CUART_RX3, | ||
111 | .end = IRQ_S3CUART_RX3, | ||
112 | .flags = IORESOURCE_IRQ, | ||
113 | }, | ||
114 | [2] = { | ||
115 | .start = IRQ_S3CUART_TX3, | ||
116 | .end = IRQ_S3CUART_TX3, | ||
117 | .flags = IORESOURCE_IRQ, | ||
118 | |||
119 | }, | ||
120 | [3] = { | ||
121 | .start = IRQ_S3CUART_ERR3, | ||
122 | .end = IRQ_S3CUART_ERR3, | ||
123 | .flags = IORESOURCE_IRQ, | ||
124 | }, | ||
125 | }; | ||
126 | |||
127 | |||
128 | struct s3c24xx_uart_resources s5pc1xx_uart_resources[] __initdata = { | ||
129 | [0] = { | ||
130 | .resources = s5pc1xx_uart0_resource, | ||
131 | .nr_resources = ARRAY_SIZE(s5pc1xx_uart0_resource), | ||
132 | }, | ||
133 | [1] = { | ||
134 | .resources = s5pc1xx_uart1_resource, | ||
135 | .nr_resources = ARRAY_SIZE(s5pc1xx_uart1_resource), | ||
136 | }, | ||
137 | [2] = { | ||
138 | .resources = s5pc1xx_uart2_resource, | ||
139 | .nr_resources = ARRAY_SIZE(s5pc1xx_uart2_resource), | ||
140 | }, | ||
141 | [3] = { | ||
142 | .resources = s5pc1xx_uart3_resource, | ||
143 | .nr_resources = ARRAY_SIZE(s5pc1xx_uart3_resource), | ||
144 | }, | ||
145 | }; | ||
146 | |||
147 | /* uart devices */ | ||
148 | |||
149 | static struct platform_device s3c24xx_uart_device0 = { | ||
150 | .id = 0, | ||
151 | }; | ||
152 | |||
153 | static struct platform_device s3c24xx_uart_device1 = { | ||
154 | .id = 1, | ||
155 | }; | ||
156 | |||
157 | static struct platform_device s3c24xx_uart_device2 = { | ||
158 | .id = 2, | ||
159 | }; | ||
160 | |||
161 | static struct platform_device s3c24xx_uart_device3 = { | ||
162 | .id = 3, | ||
163 | }; | ||
164 | |||
165 | struct platform_device *s3c24xx_uart_src[4] = { | ||
166 | &s3c24xx_uart_device0, | ||
167 | &s3c24xx_uart_device1, | ||
168 | &s3c24xx_uart_device2, | ||
169 | &s3c24xx_uart_device3, | ||
170 | }; | ||
171 | |||
172 | struct platform_device *s3c24xx_uart_devs[4] = { | ||
173 | }; | ||
174 | |||
diff --git a/arch/arm/plat-s5pc1xx/include/plat/irqs.h b/arch/arm/plat-s5pc1xx/include/plat/irqs.h new file mode 100644 index 000000000000..f07d8c3b25d6 --- /dev/null +++ b/arch/arm/plat-s5pc1xx/include/plat/irqs.h | |||
@@ -0,0 +1,182 @@ | |||
1 | /* linux/arch/arm/plat-s5pc1xx/include/plat/irqs.h | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * S5PC1XX - Common IRQ support | ||
7 | * | ||
8 | * Based on plat-s3c64xx/include/plat/irqs.h | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_PLAT_S5PC1XX_IRQS_H | ||
12 | #define __ASM_PLAT_S5PC1XX_IRQS_H __FILE__ | ||
13 | |||
14 | /* we keep the first set of CPU IRQs out of the range of | ||
15 | * the ISA space, so that the PC104 has them to itself | ||
16 | * and we don't end up having to do horrible things to the | ||
17 | * standard ISA drivers.... | ||
18 | * | ||
19 | * note, since we're using the VICs, our start must be a | ||
20 | * mulitple of 32 to allow the common code to work | ||
21 | */ | ||
22 | |||
23 | #define S3C_IRQ_OFFSET (32) | ||
24 | |||
25 | #define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET) | ||
26 | |||
27 | #define S3C_VIC0_BASE S3C_IRQ(0) | ||
28 | #define S3C_VIC1_BASE S3C_IRQ(32) | ||
29 | #define S3C_VIC2_BASE S3C_IRQ(64) | ||
30 | |||
31 | /* UART interrupts, each UART has 4 intterupts per channel so | ||
32 | * use the space between the ISA and S3C main interrupts. Note, these | ||
33 | * are not in the same order as the S3C24XX series! */ | ||
34 | |||
35 | #define IRQ_S3CUART_BASE0 (16) | ||
36 | #define IRQ_S3CUART_BASE1 (20) | ||
37 | #define IRQ_S3CUART_BASE2 (24) | ||
38 | #define IRQ_S3CUART_BASE3 (28) | ||
39 | |||
40 | #define UART_IRQ_RXD (0) | ||
41 | #define UART_IRQ_ERR (1) | ||
42 | #define UART_IRQ_TXD (2) | ||
43 | #define UART_IRQ_MODEM (3) | ||
44 | |||
45 | #define IRQ_S3CUART_RX0 (IRQ_S3CUART_BASE0 + UART_IRQ_RXD) | ||
46 | #define IRQ_S3CUART_TX0 (IRQ_S3CUART_BASE0 + UART_IRQ_TXD) | ||
47 | #define IRQ_S3CUART_ERR0 (IRQ_S3CUART_BASE0 + UART_IRQ_ERR) | ||
48 | |||
49 | #define IRQ_S3CUART_RX1 (IRQ_S3CUART_BASE1 + UART_IRQ_RXD) | ||
50 | #define IRQ_S3CUART_TX1 (IRQ_S3CUART_BASE1 + UART_IRQ_TXD) | ||
51 | #define IRQ_S3CUART_ERR1 (IRQ_S3CUART_BASE1 + UART_IRQ_ERR) | ||
52 | |||
53 | #define IRQ_S3CUART_RX2 (IRQ_S3CUART_BASE2 + UART_IRQ_RXD) | ||
54 | #define IRQ_S3CUART_TX2 (IRQ_S3CUART_BASE2 + UART_IRQ_TXD) | ||
55 | #define IRQ_S3CUART_ERR2 (IRQ_S3CUART_BASE2 + UART_IRQ_ERR) | ||
56 | |||
57 | #define IRQ_S3CUART_RX3 (IRQ_S3CUART_BASE3 + UART_IRQ_RXD) | ||
58 | #define IRQ_S3CUART_TX3 (IRQ_S3CUART_BASE3 + UART_IRQ_TXD) | ||
59 | #define IRQ_S3CUART_ERR3 (IRQ_S3CUART_BASE3 + UART_IRQ_ERR) | ||
60 | |||
61 | /* VIC based IRQs */ | ||
62 | |||
63 | #define S5PC1XX_IRQ_VIC0(x) (S3C_VIC0_BASE + (x)) | ||
64 | #define S5PC1XX_IRQ_VIC1(x) (S3C_VIC1_BASE + (x)) | ||
65 | #define S5PC1XX_IRQ_VIC2(x) (S3C_VIC2_BASE + (x)) | ||
66 | |||
67 | /* | ||
68 | * VIC0: system, DMA, timer | ||
69 | */ | ||
70 | #define IRQ_EINT0 S5PC1XX_IRQ_VIC0(0) | ||
71 | #define IRQ_EINT1 S5PC1XX_IRQ_VIC0(1) | ||
72 | #define IRQ_EINT2 S5PC1XX_IRQ_VIC0(2) | ||
73 | #define IRQ_EINT3 S5PC1XX_IRQ_VIC0(3) | ||
74 | #define IRQ_EINT4 S5PC1XX_IRQ_VIC0(4) | ||
75 | #define IRQ_EINT5 S5PC1XX_IRQ_VIC0(5) | ||
76 | #define IRQ_EINT6 S5PC1XX_IRQ_VIC0(6) | ||
77 | #define IRQ_EINT7 S5PC1XX_IRQ_VIC0(7) | ||
78 | #define IRQ_EINT8 S5PC1XX_IRQ_VIC0(8) | ||
79 | #define IRQ_EINT9 S5PC1XX_IRQ_VIC0(9) | ||
80 | #define IRQ_EINT10 S5PC1XX_IRQ_VIC0(10) | ||
81 | #define IRQ_EINT11 S5PC1XX_IRQ_VIC0(11) | ||
82 | #define IRQ_EINT12 S5PC1XX_IRQ_VIC0(12) | ||
83 | #define IRQ_EINT13 S5PC1XX_IRQ_VIC0(13) | ||
84 | #define IRQ_EINT14 S5PC1XX_IRQ_VIC0(14) | ||
85 | #define IRQ_EINT15 S5PC1XX_IRQ_VIC0(15) | ||
86 | #define IRQ_EINT16_31 S5PC1XX_IRQ_VIC0(16) | ||
87 | #define IRQ_BATF S5PC1XX_IRQ_VIC0(17) | ||
88 | #define IRQ_MDMA S5PC1XX_IRQ_VIC0(18) | ||
89 | #define IRQ_PDMA0 S5PC1XX_IRQ_VIC0(19) | ||
90 | #define IRQ_PDMA1 S5PC1XX_IRQ_VIC0(20) | ||
91 | #define IRQ_TIMER0 S5PC1XX_IRQ_VIC0(21) | ||
92 | #define IRQ_TIMER1 S5PC1XX_IRQ_VIC0(22) | ||
93 | #define IRQ_TIMER2 S5PC1XX_IRQ_VIC0(23) | ||
94 | #define IRQ_TIMER3 S5PC1XX_IRQ_VIC0(24) | ||
95 | #define IRQ_TIMER4 S5PC1XX_IRQ_VIC0(25) | ||
96 | #define IRQ_SYSTIMER S5PC1XX_IRQ_VIC0(26) | ||
97 | #define IRQ_WDT S5PC1XX_IRQ_VIC0(27) | ||
98 | #define IRQ_RTC_ALARM S5PC1XX_IRQ_VIC0(28) | ||
99 | #define IRQ_RTC_TIC S5PC1XX_IRQ_VIC0(29) | ||
100 | #define IRQ_GPIOINT S5PC1XX_IRQ_VIC0(30) | ||
101 | |||
102 | /* | ||
103 | * VIC1: ARM, power, memory, connectivity | ||
104 | */ | ||
105 | #define IRQ_CORTEX0 S5PC1XX_IRQ_VIC1(0) | ||
106 | #define IRQ_CORTEX1 S5PC1XX_IRQ_VIC1(1) | ||
107 | #define IRQ_CORTEX2 S5PC1XX_IRQ_VIC1(2) | ||
108 | #define IRQ_CORTEX3 S5PC1XX_IRQ_VIC1(3) | ||
109 | #define IRQ_CORTEX4 S5PC1XX_IRQ_VIC1(4) | ||
110 | #define IRQ_IEMAPC S5PC1XX_IRQ_VIC1(5) | ||
111 | #define IRQ_IEMIEC S5PC1XX_IRQ_VIC1(6) | ||
112 | #define IRQ_ONENAND S5PC1XX_IRQ_VIC1(7) | ||
113 | #define IRQ_NFC S5PC1XX_IRQ_VIC1(8) | ||
114 | #define IRQ_CFC S5PC1XX_IRQ_VIC1(9) | ||
115 | #define IRQ_UART0 S5PC1XX_IRQ_VIC1(10) | ||
116 | #define IRQ_UART1 S5PC1XX_IRQ_VIC1(11) | ||
117 | #define IRQ_UART2 S5PC1XX_IRQ_VIC1(12) | ||
118 | #define IRQ_UART3 S5PC1XX_IRQ_VIC1(13) | ||
119 | #define IRQ_IIC S5PC1XX_IRQ_VIC1(14) | ||
120 | #define IRQ_SPI0 S5PC1XX_IRQ_VIC1(15) | ||
121 | #define IRQ_SPI1 S5PC1XX_IRQ_VIC1(16) | ||
122 | #define IRQ_SPI2 S5PC1XX_IRQ_VIC1(17) | ||
123 | #define IRQ_IRDA S5PC1XX_IRQ_VIC1(18) | ||
124 | #define IRQ_CAN0 S5PC1XX_IRQ_VIC1(19) | ||
125 | #define IRQ_CAN1 S5PC1XX_IRQ_VIC1(20) | ||
126 | #define IRQ_HSIRX S5PC1XX_IRQ_VIC1(21) | ||
127 | #define IRQ_HSITX S5PC1XX_IRQ_VIC1(22) | ||
128 | #define IRQ_UHOST S5PC1XX_IRQ_VIC1(23) | ||
129 | #define IRQ_OTG S5PC1XX_IRQ_VIC1(24) | ||
130 | #define IRQ_MSM S5PC1XX_IRQ_VIC1(25) | ||
131 | #define IRQ_HSMMC0 S5PC1XX_IRQ_VIC1(26) | ||
132 | #define IRQ_HSMMC1 S5PC1XX_IRQ_VIC1(27) | ||
133 | #define IRQ_HSMMC2 S5PC1XX_IRQ_VIC1(28) | ||
134 | #define IRQ_MIPICSI S5PC1XX_IRQ_VIC1(29) | ||
135 | #define IRQ_MIPIDSI S5PC1XX_IRQ_VIC1(30) | ||
136 | |||
137 | /* | ||
138 | * VIC2: multimedia, audio, security | ||
139 | */ | ||
140 | #define IRQ_LCD0 S5PC1XX_IRQ_VIC2(0) | ||
141 | #define IRQ_LCD1 S5PC1XX_IRQ_VIC2(1) | ||
142 | #define IRQ_LCD2 S5PC1XX_IRQ_VIC2(2) | ||
143 | #define IRQ_LCD3 S5PC1XX_IRQ_VIC2(3) | ||
144 | #define IRQ_ROTATOR S5PC1XX_IRQ_VIC2(4) | ||
145 | #define IRQ_FIMC0 S5PC1XX_IRQ_VIC2(5) | ||
146 | #define IRQ_FIMC1 S5PC1XX_IRQ_VIC2(6) | ||
147 | #define IRQ_FIMC2 S5PC1XX_IRQ_VIC2(7) | ||
148 | #define IRQ_JPEG S5PC1XX_IRQ_VIC2(8) | ||
149 | #define IRQ_2D S5PC1XX_IRQ_VIC2(9) | ||
150 | #define IRQ_3D S5PC1XX_IRQ_VIC2(10) | ||
151 | #define IRQ_MIXER S5PC1XX_IRQ_VIC2(11) | ||
152 | #define IRQ_HDMI S5PC1XX_IRQ_VIC2(12) | ||
153 | #define IRQ_IIC1 S5PC1XX_IRQ_VIC2(13) | ||
154 | #define IRQ_MFC S5PC1XX_IRQ_VIC2(14) | ||
155 | #define IRQ_TVENC S5PC1XX_IRQ_VIC2(15) | ||
156 | #define IRQ_I2S0 S5PC1XX_IRQ_VIC2(16) | ||
157 | #define IRQ_I2S1 S5PC1XX_IRQ_VIC2(17) | ||
158 | #define IRQ_I2S2 S5PC1XX_IRQ_VIC2(18) | ||
159 | #define IRQ_AC97 S5PC1XX_IRQ_VIC2(19) | ||
160 | #define IRQ_PCM0 S5PC1XX_IRQ_VIC2(20) | ||
161 | #define IRQ_PCM1 S5PC1XX_IRQ_VIC2(21) | ||
162 | #define IRQ_SPDIF S5PC1XX_IRQ_VIC2(22) | ||
163 | #define IRQ_ADC S5PC1XX_IRQ_VIC2(23) | ||
164 | #define IRQ_PENDN S5PC1XX_IRQ_VIC2(24) | ||
165 | #define IRQ_TC IRQ_PENDN | ||
166 | #define IRQ_KEYPAD S5PC1XX_IRQ_VIC2(25) | ||
167 | #define IRQ_CG S5PC1XX_IRQ_VIC2(26) | ||
168 | #define IRQ_SEC S5PC1XX_IRQ_VIC2(27) | ||
169 | #define IRQ_SECRX S5PC1XX_IRQ_VIC2(28) | ||
170 | #define IRQ_SECTX S5PC1XX_IRQ_VIC2(29) | ||
171 | #define IRQ_SDMIRQ S5PC1XX_IRQ_VIC2(30) | ||
172 | #define IRQ_SDMFIQ S5PC1XX_IRQ_VIC2(31) | ||
173 | |||
174 | #define S3C_IRQ_EINT_BASE (IRQ_SDMFIQ + 1) | ||
175 | |||
176 | #define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE) | ||
177 | #define IRQ_EINT(x) S3C_EINT(x) | ||
178 | |||
179 | #define NR_IRQS (IRQ_EINT(31)+1) | ||
180 | |||
181 | #endif /* __ASM_PLAT_S5PC1XX_IRQS_H */ | ||
182 | |||
diff --git a/arch/arm/plat-s5pc1xx/include/plat/pll.h b/arch/arm/plat-s5pc1xx/include/plat/pll.h new file mode 100644 index 000000000000..21afef1573e7 --- /dev/null +++ b/arch/arm/plat-s5pc1xx/include/plat/pll.h | |||
@@ -0,0 +1,38 @@ | |||
1 | /* arch/arm/plat-s5pc1xx/include/plat/pll.h | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * S5PC1XX PLL code | ||
7 | * | ||
8 | * Based on plat-s3c64xx/include/plat/pll.h | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #define S5P_PLL_MDIV_MASK ((1 << (25-16+1)) - 1) | ||
16 | #define S5P_PLL_PDIV_MASK ((1 << (13-8+1)) - 1) | ||
17 | #define S5P_PLL_SDIV_MASK ((1 << (2-0+1)) - 1) | ||
18 | #define S5P_PLL_MDIV_SHIFT (16) | ||
19 | #define S5P_PLL_PDIV_SHIFT (8) | ||
20 | #define S5P_PLL_SDIV_SHIFT (0) | ||
21 | |||
22 | #include <asm/div64.h> | ||
23 | |||
24 | static inline unsigned long s5pc1xx_get_pll(unsigned long baseclk, | ||
25 | u32 pllcon) | ||
26 | { | ||
27 | u32 mdiv, pdiv, sdiv; | ||
28 | u64 fvco = baseclk; | ||
29 | |||
30 | mdiv = (pllcon >> S5P_PLL_MDIV_SHIFT) & S5P_PLL_MDIV_MASK; | ||
31 | pdiv = (pllcon >> S5P_PLL_PDIV_SHIFT) & S5P_PLL_PDIV_MASK; | ||
32 | sdiv = (pllcon >> S5P_PLL_SDIV_SHIFT) & S5P_PLL_SDIV_MASK; | ||
33 | |||
34 | fvco *= mdiv; | ||
35 | do_div(fvco, (pdiv << sdiv)); | ||
36 | |||
37 | return (unsigned long)fvco; | ||
38 | } | ||
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h new file mode 100644 index 000000000000..75c8390cb827 --- /dev/null +++ b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h | |||
@@ -0,0 +1,421 @@ | |||
1 | /* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * S5PC1XX clock register definitions | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __PLAT_REGS_CLOCK_H | ||
14 | #define __PLAT_REGS_CLOCK_H __FILE__ | ||
15 | |||
16 | #define S5PC1XX_CLKREG(x) (S5PC1XX_VA_CLK + (x)) | ||
17 | |||
18 | #define S5PC1XX_APLL_LOCK S5PC1XX_CLKREG(0x00) | ||
19 | #define S5PC1XX_MPLL_LOCK S5PC1XX_CLKREG(0x04) | ||
20 | #define S5PC1XX_EPLL_LOCK S5PC1XX_CLKREG(0x08) | ||
21 | #define S5PC100_HPLL_LOCK S5PC1XX_CLKREG(0x0C) | ||
22 | |||
23 | #define S5PC1XX_APLL_CON S5PC1XX_CLKREG(0x100) | ||
24 | #define S5PC1XX_MPLL_CON S5PC1XX_CLKREG(0x104) | ||
25 | #define S5PC1XX_EPLL_CON S5PC1XX_CLKREG(0x108) | ||
26 | #define S5PC100_HPLL_CON S5PC1XX_CLKREG(0x10C) | ||
27 | |||
28 | #define S5PC1XX_CLK_SRC0 S5PC1XX_CLKREG(0x200) | ||
29 | #define S5PC1XX_CLK_SRC1 S5PC1XX_CLKREG(0x204) | ||
30 | #define S5PC1XX_CLK_SRC2 S5PC1XX_CLKREG(0x208) | ||
31 | #define S5PC1XX_CLK_SRC3 S5PC1XX_CLKREG(0x20C) | ||
32 | |||
33 | #define S5PC1XX_CLK_DIV0 S5PC1XX_CLKREG(0x300) | ||
34 | #define S5PC1XX_CLK_DIV1 S5PC1XX_CLKREG(0x304) | ||
35 | #define S5PC1XX_CLK_DIV2 S5PC1XX_CLKREG(0x308) | ||
36 | #define S5PC1XX_CLK_DIV3 S5PC1XX_CLKREG(0x30C) | ||
37 | #define S5PC1XX_CLK_DIV4 S5PC1XX_CLKREG(0x310) | ||
38 | |||
39 | #define S5PC100_CLK_OUT S5PC1XX_CLKREG(0x400) | ||
40 | |||
41 | #define S5PC100_CLKGATE_D00 S5PC1XX_CLKREG(0x500) | ||
42 | #define S5PC100_CLKGATE_D01 S5PC1XX_CLKREG(0x504) | ||
43 | #define S5PC100_CLKGATE_D02 S5PC1XX_CLKREG(0x508) | ||
44 | |||
45 | #define S5PC100_CLKGATE_D10 S5PC1XX_CLKREG(0x520) | ||
46 | #define S5PC100_CLKGATE_D11 S5PC1XX_CLKREG(0x524) | ||
47 | #define S5PC100_CLKGATE_D12 S5PC1XX_CLKREG(0x528) | ||
48 | #define S5PC100_CLKGATE_D13 S5PC1XX_CLKREG(0x52C) | ||
49 | #define S5PC100_CLKGATE_D14 S5PC1XX_CLKREG(0x530) | ||
50 | #define S5PC100_CLKGATE_D15 S5PC1XX_CLKREG(0x534) | ||
51 | |||
52 | #define S5PC100_CLKGATE_D20 S5PC1XX_CLKREG(0x540) | ||
53 | |||
54 | #define S5PC100_SCLKGATE0 S5PC1XX_CLKREG(0x560) | ||
55 | #define S5PC100_SCLKGATE1 S5PC1XX_CLKREG(0x564) | ||
56 | |||
57 | #define S5PC100_OTHERS S5PC1XX_CLKREG(0x8200) | ||
58 | |||
59 | #define S5PC1XX_EPLL_EN (1<<31) | ||
60 | #define S5PC1XX_EPLL_MASK 0xffffffff | ||
61 | #define S5PC1XX_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s))) | ||
62 | |||
63 | /* CLKSRC0 */ | ||
64 | #define S5PC1XX_CLKSRC0_APLL_MASK (0x1<<0) | ||
65 | #define S5PC1XX_CLKSRC0_APLL_SHIFT (0) | ||
66 | #define S5PC1XX_CLKSRC0_MPLL_MASK (0x1<<4) | ||
67 | #define S5PC1XX_CLKSRC0_MPLL_SHIFT (4) | ||
68 | #define S5PC1XX_CLKSRC0_EPLL_MASK (0x1<<8) | ||
69 | #define S5PC1XX_CLKSRC0_EPLL_SHIFT (8) | ||
70 | #define S5PC100_CLKSRC0_HPLL_MASK (0x1<<12) | ||
71 | #define S5PC100_CLKSRC0_HPLL_SHIFT (12) | ||
72 | #define S5PC100_CLKSRC0_AMMUX_MASK (0x1<<16) | ||
73 | #define S5PC100_CLKSRC0_AMMUX_SHIFT (16) | ||
74 | #define S5PC100_CLKSRC0_HREF_MASK (0x1<<20) | ||
75 | #define S5PC100_CLKSRC0_HREF_SHIFT (20) | ||
76 | #define S5PC1XX_CLKSRC0_ONENAND_MASK (0x1<<24) | ||
77 | #define S5PC1XX_CLKSRC0_ONENAND_SHIFT (24) | ||
78 | |||
79 | |||
80 | /* CLKSRC1 */ | ||
81 | #define S5PC100_CLKSRC1_UART_MASK (0x1<<0) | ||
82 | #define S5PC100_CLKSRC1_UART_SHIFT (0) | ||
83 | #define S5PC100_CLKSRC1_SPI0_MASK (0x3<<4) | ||
84 | #define S5PC100_CLKSRC1_SPI0_SHIFT (4) | ||
85 | #define S5PC100_CLKSRC1_SPI1_MASK (0x3<<8) | ||
86 | #define S5PC100_CLKSRC1_SPI1_SHIFT (8) | ||
87 | #define S5PC100_CLKSRC1_SPI2_MASK (0x3<<12) | ||
88 | #define S5PC100_CLKSRC1_SPI2_SHIFT (12) | ||
89 | #define S5PC100_CLKSRC1_IRDA_MASK (0x3<<16) | ||
90 | #define S5PC100_CLKSRC1_IRDA_SHIFT (16) | ||
91 | #define S5PC100_CLKSRC1_UHOST_MASK (0x3<<20) | ||
92 | #define S5PC100_CLKSRC1_UHOST_SHIFT (20) | ||
93 | #define S5PC100_CLKSRC1_CLK48M_MASK (0x1<<24) | ||
94 | #define S5PC100_CLKSRC1_CLK48M_SHIFT (24) | ||
95 | |||
96 | /* CLKSRC2 */ | ||
97 | #define S5PC100_CLKSRC2_MMC0_MASK (0x3<<0) | ||
98 | #define S5PC100_CLKSRC2_MMC0_SHIFT (0) | ||
99 | #define S5PC100_CLKSRC2_MMC1_MASK (0x3<<4) | ||
100 | #define S5PC100_CLKSRC2_MMC1_SHIFT (4) | ||
101 | #define S5PC100_CLKSRC2_MMC2_MASK (0x3<<8) | ||
102 | #define S5PC100_CLKSRC2_MMC2_SHIFT (8) | ||
103 | #define S5PC100_CLKSRC2_LCD_MASK (0x3<<12) | ||
104 | #define S5PC100_CLKSRC2_LCD_SHIFT (12) | ||
105 | #define S5PC100_CLKSRC2_FIMC0_MASK (0x3<<16) | ||
106 | #define S5PC100_CLKSRC2_FIMC0_SHIFT (16) | ||
107 | #define S5PC100_CLKSRC2_FIMC1_MASK (0x3<<20) | ||
108 | #define S5PC100_CLKSRC2_FIMC1_SHIFT (20) | ||
109 | #define S5PC100_CLKSRC2_FIMC2_MASK (0x3<<24) | ||
110 | #define S5PC100_CLKSRC2_FIMC2_SHIFT (24) | ||
111 | #define S5PC100_CLKSRC2_MIXER_MASK (0x3<<28) | ||
112 | #define S5PC100_CLKSRC2_MIXER_SHIFT (28) | ||
113 | |||
114 | /* CLKSRC3 */ | ||
115 | #define S5PC100_CLKSRC3_PWI_MASK (0x3<<0) | ||
116 | #define S5PC100_CLKSRC3_PWI_SHIFT (0) | ||
117 | #define S5PC100_CLKSRC3_HCLKD2_MASK (0x1<<4) | ||
118 | #define S5PC100_CLKSRC3_HCLKD2_SHIFT (4) | ||
119 | #define S5PC100_CLKSRC3_I2SD2_MASK (0x3<<8) | ||
120 | #define S5PC100_CLKSRC3_I2SD2_SHIFT (8) | ||
121 | #define S5PC100_CLKSRC3_AUDIO0_MASK (0x7<<12) | ||
122 | #define S5PC100_CLKSRC3_AUDIO0_SHIFT (12) | ||
123 | #define S5PC100_CLKSRC3_AUDIO1_MASK (0x7<<16) | ||
124 | #define S5PC100_CLKSRC3_AUDIO1_SHIFT (16) | ||
125 | #define S5PC100_CLKSRC3_AUDIO2_MASK (0x7<<20) | ||
126 | #define S5PC100_CLKSRC3_AUDIO2_SHIFT (20) | ||
127 | #define S5PC100_CLKSRC3_SPDIF_MASK (0x3<<24) | ||
128 | #define S5PC100_CLKSRC3_SPDIF_SHIFT (24) | ||
129 | |||
130 | |||
131 | /* CLKDIV0 */ | ||
132 | #define S5PC1XX_CLKDIV0_APLL_MASK (0x1<<0) | ||
133 | #define S5PC1XX_CLKDIV0_APLL_SHIFT (0) | ||
134 | #define S5PC100_CLKDIV0_ARM_MASK (0x7<<4) | ||
135 | #define S5PC100_CLKDIV0_ARM_SHIFT (4) | ||
136 | #define S5PC100_CLKDIV0_D0_MASK (0x7<<8) | ||
137 | #define S5PC100_CLKDIV0_D0_SHIFT (8) | ||
138 | #define S5PC100_CLKDIV0_PCLKD0_MASK (0x7<<12) | ||
139 | #define S5PC100_CLKDIV0_PCLKD0_SHIFT (12) | ||
140 | #define S5PC100_CLKDIV0_SECSS_MASK (0x7<<16) | ||
141 | #define S5PC100_CLKDIV0_SECSS_SHIFT (16) | ||
142 | |||
143 | /* CLKDIV1 */ | ||
144 | #define S5PC100_CLKDIV1_AM_MASK (0x7<<0) | ||
145 | #define S5PC100_CLKDIV1_AM_SHIFT (0) | ||
146 | #define S5PC100_CLKDIV1_MPLL_MASK (0x3<<4) | ||
147 | #define S5PC100_CLKDIV1_MPLL_SHIFT (4) | ||
148 | #define S5PC100_CLKDIV1_MPLL2_MASK (0x1<<8) | ||
149 | #define S5PC100_CLKDIV1_MPLL2_SHIFT (8) | ||
150 | #define S5PC100_CLKDIV1_D1_MASK (0x7<<12) | ||
151 | #define S5PC100_CLKDIV1_D1_SHIFT (12) | ||
152 | #define S5PC100_CLKDIV1_PCLKD1_MASK (0x7<<16) | ||
153 | #define S5PC100_CLKDIV1_PCLKD1_SHIFT (16) | ||
154 | #define S5PC100_CLKDIV1_ONENAND_MASK (0x3<<20) | ||
155 | #define S5PC100_CLKDIV1_ONENAND_SHIFT (20) | ||
156 | #define S5PC100_CLKDIV1_CAM_MASK (0x1F<<24) | ||
157 | #define S5PC100_CLKDIV1_CAM_SHIFT (24) | ||
158 | |||
159 | /* CLKDIV2 */ | ||
160 | #define S5PC100_CLKDIV2_UART_MASK (0x7<<0) | ||
161 | #define S5PC100_CLKDIV2_UART_SHIFT (0) | ||
162 | #define S5PC100_CLKDIV2_SPI0_MASK (0xf<<4) | ||
163 | #define S5PC100_CLKDIV2_SPI0_SHIFT (4) | ||
164 | #define S5PC100_CLKDIV2_SPI1_MASK (0xf<<8) | ||
165 | #define S5PC100_CLKDIV2_SPI1_SHIFT (8) | ||
166 | #define S5PC100_CLKDIV2_SPI2_MASK (0xf<<12) | ||
167 | #define S5PC100_CLKDIV2_SPI2_SHIFT (12) | ||
168 | #define S5PC100_CLKDIV2_IRDA_MASK (0xf<<16) | ||
169 | #define S5PC100_CLKDIV2_IRDA_SHIFT (16) | ||
170 | #define S5PC100_CLKDIV2_UHOST_MASK (0xf<<20) | ||
171 | #define S5PC100_CLKDIV2_UHOST_SHIFT (20) | ||
172 | |||
173 | /* CLKDIV3 */ | ||
174 | #define S5PC100_CLKDIV3_MMC0_MASK (0xf<<0) | ||
175 | #define S5PC100_CLKDIV3_MMC0_SHIFT (0) | ||
176 | #define S5PC100_CLKDIV3_MMC1_MASK (0xf<<4) | ||
177 | #define S5PC100_CLKDIV3_MMC1_SHIFT (4) | ||
178 | #define S5PC100_CLKDIV3_MMC2_MASK (0xf<<8) | ||
179 | #define S5PC100_CLKDIV3_MMC2_SHIFT (8) | ||
180 | #define S5PC100_CLKDIV3_LCD_MASK (0xf<<12) | ||
181 | #define S5PC100_CLKDIV3_LCD_SHIFT (12) | ||
182 | #define S5PC100_CLKDIV3_FIMC0_MASK (0xf<<16) | ||
183 | #define S5PC100_CLKDIV3_FIMC0_SHIFT (16) | ||
184 | #define S5PC100_CLKDIV3_FIMC1_MASK (0xf<<20) | ||
185 | #define S5PC100_CLKDIV3_FIMC1_SHIFT (20) | ||
186 | #define S5PC100_CLKDIV3_FIMC2_MASK (0xf<<24) | ||
187 | #define S5PC100_CLKDIV3_FIMC2_SHIFT (24) | ||
188 | #define S5PC100_CLKDIV3_HDMI_MASK (0xf<<28) | ||
189 | #define S5PC100_CLKDIV3_HDMI_SHIFT (28) | ||
190 | |||
191 | /* CLKDIV4 */ | ||
192 | #define S5PC100_CLKDIV4_PWI_MASK (0x7<<0) | ||
193 | #define S5PC100_CLKDIV4_PWI_SHIFT (0) | ||
194 | #define S5PC100_CLKDIV4_HCLKD2_MASK (0x7<<4) | ||
195 | #define S5PC100_CLKDIV4_HCLKD2_SHIFT (4) | ||
196 | #define S5PC100_CLKDIV4_I2SD2_MASK (0xf<<8) | ||
197 | #define S5PC100_CLKDIV4_I2SD2_SHIFT (8) | ||
198 | #define S5PC100_CLKDIV4_AUDIO0_MASK (0xf<<12) | ||
199 | #define S5PC100_CLKDIV4_AUDIO0_SHIFT (12) | ||
200 | #define S5PC100_CLKDIV4_AUDIO1_MASK (0xf<<16) | ||
201 | #define S5PC100_CLKDIV4_AUDIO1_SHIFT (16) | ||
202 | #define S5PC100_CLKDIV4_AUDIO2_MASK (0xf<<20) | ||
203 | #define S5PC100_CLKDIV4_AUDIO2_SHIFT (20) | ||
204 | |||
205 | |||
206 | /* HCLKD0/PCLKD0 Clock Gate 0 Registers */ | ||
207 | #define S5PC100_CLKGATE_D00_INTC (1<<0) | ||
208 | #define S5PC100_CLKGATE_D00_TZIC (1<<1) | ||
209 | #define S5PC100_CLKGATE_D00_CFCON (1<<2) | ||
210 | #define S5PC100_CLKGATE_D00_MDMA (1<<3) | ||
211 | #define S5PC100_CLKGATE_D00_G2D (1<<4) | ||
212 | #define S5PC100_CLKGATE_D00_SECSS (1<<5) | ||
213 | #define S5PC100_CLKGATE_D00_CSSYS (1<<6) | ||
214 | |||
215 | /* HCLKD0/PCLKD0 Clock Gate 1 Registers */ | ||
216 | #define S5PC100_CLKGATE_D01_DMC (1<<0) | ||
217 | #define S5PC100_CLKGATE_D01_SROMC (1<<1) | ||
218 | #define S5PC100_CLKGATE_D01_ONENAND (1<<2) | ||
219 | #define S5PC100_CLKGATE_D01_NFCON (1<<3) | ||
220 | #define S5PC100_CLKGATE_D01_INTMEM (1<<4) | ||
221 | #define S5PC100_CLKGATE_D01_EBI (1<<5) | ||
222 | |||
223 | /* PCLKD0 Clock Gate 2 Registers */ | ||
224 | #define S5PC100_CLKGATE_D02_SECKEY (1<<1) | ||
225 | #define S5PC100_CLKGATE_D02_SDM (1<<2) | ||
226 | |||
227 | /* HCLKD1/PCLKD1 Clock Gate 0 Registers */ | ||
228 | #define S5PC100_CLKGATE_D10_PDMA0 (1<<0) | ||
229 | #define S5PC100_CLKGATE_D10_PDMA1 (1<<1) | ||
230 | #define S5PC100_CLKGATE_D10_USBHOST (1<<2) | ||
231 | #define S5PC100_CLKGATE_D10_USBOTG (1<<3) | ||
232 | #define S5PC100_CLKGATE_D10_MODEMIF (1<<4) | ||
233 | #define S5PC100_CLKGATE_D10_HSMMC0 (1<<5) | ||
234 | #define S5PC100_CLKGATE_D10_HSMMC1 (1<<6) | ||
235 | #define S5PC100_CLKGATE_D10_HSMMC2 (1<<7) | ||
236 | |||
237 | /* HCLKD1/PCLKD1 Clock Gate 1 Registers */ | ||
238 | #define S5PC100_CLKGATE_D11_LCD (1<<0) | ||
239 | #define S5PC100_CLKGATE_D11_ROTATOR (1<<1) | ||
240 | #define S5PC100_CLKGATE_D11_FIMC0 (1<<2) | ||
241 | #define S5PC100_CLKGATE_D11_FIMC1 (1<<3) | ||
242 | #define S5PC100_CLKGATE_D11_FIMC2 (1<<4) | ||
243 | #define S5PC100_CLKGATE_D11_JPEG (1<<5) | ||
244 | #define S5PC100_CLKGATE_D11_DSI (1<<6) | ||
245 | #define S5PC100_CLKGATE_D11_CSI (1<<7) | ||
246 | #define S5PC100_CLKGATE_D11_G3D (1<<8) | ||
247 | |||
248 | /* HCLKD1/PCLKD1 Clock Gate 2 Registers */ | ||
249 | #define S5PC100_CLKGATE_D12_TV (1<<0) | ||
250 | #define S5PC100_CLKGATE_D12_VP (1<<1) | ||
251 | #define S5PC100_CLKGATE_D12_MIXER (1<<2) | ||
252 | #define S5PC100_CLKGATE_D12_HDMI (1<<3) | ||
253 | #define S5PC100_CLKGATE_D12_MFC (1<<4) | ||
254 | |||
255 | /* HCLKD1/PCLKD1 Clock Gate 3 Registers */ | ||
256 | #define S5PC100_CLKGATE_D13_CHIPID (1<<0) | ||
257 | #define S5PC100_CLKGATE_D13_GPIO (1<<1) | ||
258 | #define S5PC100_CLKGATE_D13_APC (1<<2) | ||
259 | #define S5PC100_CLKGATE_D13_IEC (1<<3) | ||
260 | #define S5PC100_CLKGATE_D13_PWM (1<<6) | ||
261 | #define S5PC100_CLKGATE_D13_SYSTIMER (1<<7) | ||
262 | #define S5PC100_CLKGATE_D13_WDT (1<<8) | ||
263 | #define S5PC100_CLKGATE_D13_RTC (1<<9) | ||
264 | |||
265 | /* HCLKD1/PCLKD1 Clock Gate 4 Registers */ | ||
266 | #define S5PC100_CLKGATE_D14_UART0 (1<<0) | ||
267 | #define S5PC100_CLKGATE_D14_UART1 (1<<1) | ||
268 | #define S5PC100_CLKGATE_D14_UART2 (1<<2) | ||
269 | #define S5PC100_CLKGATE_D14_UART3 (1<<3) | ||
270 | #define S5PC100_CLKGATE_D14_IIC (1<<4) | ||
271 | #define S5PC100_CLKGATE_D14_HDMI_IIC (1<<5) | ||
272 | #define S5PC100_CLKGATE_D14_SPI0 (1<<6) | ||
273 | #define S5PC100_CLKGATE_D14_SPI1 (1<<7) | ||
274 | #define S5PC100_CLKGATE_D14_SPI2 (1<<8) | ||
275 | #define S5PC100_CLKGATE_D14_IRDA (1<<9) | ||
276 | #define S5PC100_CLKGATE_D14_CCAN0 (1<<10) | ||
277 | #define S5PC100_CLKGATE_D14_CCAN1 (1<<11) | ||
278 | #define S5PC100_CLKGATE_D14_HSITX (1<<12) | ||
279 | #define S5PC100_CLKGATE_D14_HSIRX (1<<13) | ||
280 | |||
281 | /* HCLKD1/PCLKD1 Clock Gate 5 Registers */ | ||
282 | #define S5PC100_CLKGATE_D15_IIS0 (1<<0) | ||
283 | #define S5PC100_CLKGATE_D15_IIS1 (1<<1) | ||
284 | #define S5PC100_CLKGATE_D15_IIS2 (1<<2) | ||
285 | #define S5PC100_CLKGATE_D15_AC97 (1<<3) | ||
286 | #define S5PC100_CLKGATE_D15_PCM0 (1<<4) | ||
287 | #define S5PC100_CLKGATE_D15_PCM1 (1<<5) | ||
288 | #define S5PC100_CLKGATE_D15_SPDIF (1<<6) | ||
289 | #define S5PC100_CLKGATE_D15_TSADC (1<<7) | ||
290 | #define S5PC100_CLKGATE_D15_KEYIF (1<<8) | ||
291 | #define S5PC100_CLKGATE_D15_CG (1<<9) | ||
292 | |||
293 | /* HCLKD2 Clock Gate 0 Registers */ | ||
294 | #define S5PC100_CLKGATE_D20_HCLKD2 (1<<0) | ||
295 | #define S5PC100_CLKGATE_D20_I2SD2 (1<<1) | ||
296 | |||
297 | /* Special Clock Gate 0 Registers */ | ||
298 | #define S5PC1XX_CLKGATE_SCLK0_HPM (1<<0) | ||
299 | #define S5PC1XX_CLKGATE_SCLK0_PWI (1<<1) | ||
300 | #define S5PC100_CLKGATE_SCLK0_ONENAND (1<<2) | ||
301 | #define S5PC100_CLKGATE_SCLK0_UART (1<<3) | ||
302 | #define S5PC100_CLKGATE_SCLK0_SPI0 (1<<4) | ||
303 | #define S5PC100_CLKGATE_SCLK0_SPI1 (1<<5) | ||
304 | #define S5PC100_CLKGATE_SCLK0_SPI2 (1<<6) | ||
305 | #define S5PC100_CLKGATE_SCLK0_SPI0_48 (1<<7) | ||
306 | #define S5PC100_CLKGATE_SCLK0_SPI1_48 (1<<8) | ||
307 | #define S5PC100_CLKGATE_SCLK0_SPI2_48 (1<<9) | ||
308 | #define S5PC100_CLKGATE_SCLK0_IRDA (1<<10) | ||
309 | #define S5PC100_CLKGATE_SCLK0_USBHOST (1<<11) | ||
310 | #define S5PC100_CLKGATE_SCLK0_MMC0 (1<<12) | ||
311 | #define S5PC100_CLKGATE_SCLK0_MMC1 (1<<13) | ||
312 | #define S5PC100_CLKGATE_SCLK0_MMC2 (1<<14) | ||
313 | #define S5PC100_CLKGATE_SCLK0_MMC0_48 (1<<15) | ||
314 | #define S5PC100_CLKGATE_SCLK0_MMC1_48 (1<<16) | ||
315 | #define S5PC100_CLKGATE_SCLK0_MMC2_48 (1<<17) | ||
316 | |||
317 | /* Special Clock Gate 1 Registers */ | ||
318 | #define S5PC100_CLKGATE_SCLK1_LCD (1<<0) | ||
319 | #define S5PC100_CLKGATE_SCLK1_FIMC0 (1<<1) | ||
320 | #define S5PC100_CLKGATE_SCLK1_FIMC1 (1<<2) | ||
321 | #define S5PC100_CLKGATE_SCLK1_FIMC2 (1<<3) | ||
322 | #define S5PC100_CLKGATE_SCLK1_TV54 (1<<4) | ||
323 | #define S5PC100_CLKGATE_SCLK1_VDAC54 (1<<5) | ||
324 | #define S5PC100_CLKGATE_SCLK1_MIXER (1<<6) | ||
325 | #define S5PC100_CLKGATE_SCLK1_HDMI (1<<7) | ||
326 | #define S5PC100_CLKGATE_SCLK1_AUDIO0 (1<<8) | ||
327 | #define S5PC100_CLKGATE_SCLK1_AUDIO1 (1<<9) | ||
328 | #define S5PC100_CLKGATE_SCLK1_AUDIO2 (1<<10) | ||
329 | #define S5PC100_CLKGATE_SCLK1_SPDIF (1<<11) | ||
330 | #define S5PC100_CLKGATE_SCLK1_CAM (1<<12) | ||
331 | |||
332 | /* register for power management */ | ||
333 | #define S5PC100_PWR_CFG S5PC1XX_CLKREG(0x8000) | ||
334 | #define S5PC100_EINT_WAKEUP_MASK S5PC1XX_CLKREG(0x8004) | ||
335 | #define S5PC100_NORMAL_CFG S5PC1XX_CLKREG(0x8010) | ||
336 | #define S5PC100_STOP_CFG S5PC1XX_CLKREG(0x8014) | ||
337 | #define S5PC100_SLEEP_CFG S5PC1XX_CLKREG(0x8018) | ||
338 | #define S5PC100_STOP_MEM_CFG S5PC1XX_CLKREG(0x801C) | ||
339 | #define S5PC100_OSC_FREQ S5PC1XX_CLKREG(0x8100) | ||
340 | #define S5PC100_OSC_STABLE S5PC1XX_CLKREG(0x8104) | ||
341 | #define S5PC100_PWR_STABLE S5PC1XX_CLKREG(0x8108) | ||
342 | #define S5PC100_MTC_STABLE S5PC1XX_CLKREG(0x8110) | ||
343 | #define S5PC100_CLAMP_STABLE S5PC1XX_CLKREG(0x8114) | ||
344 | #define S5PC100_OTHERS S5PC1XX_CLKREG(0x8200) | ||
345 | #define S5PC100_RST_STAT S5PC1XX_CLKREG(0x8300) | ||
346 | #define S5PC100_WAKEUP_STAT S5PC1XX_CLKREG(0x8304) | ||
347 | #define S5PC100_BLK_PWR_STAT S5PC1XX_CLKREG(0x8308) | ||
348 | #define S5PC100_INFORM0 S5PC1XX_CLKREG(0x8400) | ||
349 | #define S5PC100_INFORM1 S5PC1XX_CLKREG(0x8404) | ||
350 | #define S5PC100_INFORM2 S5PC1XX_CLKREG(0x8408) | ||
351 | #define S5PC100_INFORM3 S5PC1XX_CLKREG(0x840C) | ||
352 | #define S5PC100_INFORM4 S5PC1XX_CLKREG(0x8410) | ||
353 | #define S5PC100_INFORM5 S5PC1XX_CLKREG(0x8414) | ||
354 | #define S5PC100_INFORM6 S5PC1XX_CLKREG(0x8418) | ||
355 | #define S5PC100_INFORM7 S5PC1XX_CLKREG(0x841C) | ||
356 | #define S5PC100_DCGIDX_MAP0 S5PC1XX_CLKREG(0x8500) | ||
357 | #define S5PC100_DCGIDX_MAP1 S5PC1XX_CLKREG(0x8504) | ||
358 | #define S5PC100_DCGIDX_MAP2 S5PC1XX_CLKREG(0x8508) | ||
359 | #define S5PC100_DCGPERF_MAP0 S5PC1XX_CLKREG(0x850C) | ||
360 | #define S5PC100_DCGPERF_MAP1 S5PC1XX_CLKREG(0x8510) | ||
361 | #define S5PC100_DVCIDX_MAP S5PC1XX_CLKREG(0x8514) | ||
362 | #define S5PC100_FREQ_CPU S5PC1XX_CLKREG(0x8518) | ||
363 | #define S5PC100_FREQ_DPM S5PC1XX_CLKREG(0x851C) | ||
364 | #define S5PC100_DVSEMCLK_EN S5PC1XX_CLKREG(0x8520) | ||
365 | #define S5PC100_APLL_CON_L8 S5PC1XX_CLKREG(0x8600) | ||
366 | #define S5PC100_APLL_CON_L7 S5PC1XX_CLKREG(0x8604) | ||
367 | #define S5PC100_APLL_CON_L6 S5PC1XX_CLKREG(0x8608) | ||
368 | #define S5PC100_APLL_CON_L5 S5PC1XX_CLKREG(0x860C) | ||
369 | #define S5PC100_APLL_CON_L4 S5PC1XX_CLKREG(0x8610) | ||
370 | #define S5PC100_APLL_CON_L3 S5PC1XX_CLKREG(0x8614) | ||
371 | #define S5PC100_APLL_CON_L2 S5PC1XX_CLKREG(0x8618) | ||
372 | #define S5PC100_APLL_CON_L1 S5PC1XX_CLKREG(0x861C) | ||
373 | #define S5PC100_IEM_CONTROL S5PC1XX_CLKREG(0x8620) | ||
374 | #define S5PC100_CLKDIV_IEM_L8 S5PC1XX_CLKREG(0x8700) | ||
375 | #define S5PC100_CLKDIV_IEM_L7 S5PC1XX_CLKREG(0x8704) | ||
376 | #define S5PC100_CLKDIV_IEM_L6 S5PC1XX_CLKREG(0x8708) | ||
377 | #define S5PC100_CLKDIV_IEM_L5 S5PC1XX_CLKREG(0x870C) | ||
378 | #define S5PC100_CLKDIV_IEM_L4 S5PC1XX_CLKREG(0x8710) | ||
379 | #define S5PC100_CLKDIV_IEM_L3 S5PC1XX_CLKREG(0x8714) | ||
380 | #define S5PC100_CLKDIV_IEM_L2 S5PC1XX_CLKREG(0x8718) | ||
381 | #define S5PC100_CLKDIV_IEM_L1 S5PC1XX_CLKREG(0x871C) | ||
382 | #define S5PC100_IEM_HPMCLK_DIV S5PC1XX_CLKREG(0x8724) | ||
383 | |||
384 | #define S5PC100_SWRESET S5PC1XX_CLKREG(0x100000) | ||
385 | #define S5PC100_OND_SWRESET S5PC1XX_CLKREG(0x100008) | ||
386 | #define S5PC100_GEN_CTRL S5PC1XX_CLKREG(0x100100) | ||
387 | #define S5PC100_GEN_STATUS S5PC1XX_CLKREG(0x100104) | ||
388 | #define S5PC100_MEM_SYS_CFG S5PC1XX_CLKREG(0x100200) | ||
389 | #define S5PC100_CAM_MUX_SEL S5PC1XX_CLKREG(0x100300) | ||
390 | #define S5PC100_MIXER_OUT_SEL S5PC1XX_CLKREG(0x100304) | ||
391 | #define S5PC100_LPMP_MODE_SEL S5PC1XX_CLKREG(0x100308) | ||
392 | #define S5PC100_MIPI_PHY_CON0 S5PC1XX_CLKREG(0x100400) | ||
393 | #define S5PC100_MIPI_PHY_CON1 S5PC1XX_CLKREG(0x100414) | ||
394 | #define S5PC100_HDMI_PHY_CON0 S5PC1XX_CLKREG(0x100420) | ||
395 | |||
396 | #define S5PC100_CFG_WFI_CLEAN (~(3<<5)) | ||
397 | #define S5PC100_CFG_WFI_IDLE (1<<5) | ||
398 | #define S5PC100_CFG_WFI_STOP (2<<5) | ||
399 | #define S5PC100_CFG_WFI_SLEEP (3<<5) | ||
400 | |||
401 | #define S5PC100_OTHER_SYS_INT 24 | ||
402 | #define S5PC100_OTHER_STA_TYPE 23 | ||
403 | #define STA_TYPE_EXPON 0 | ||
404 | #define STA_TYPE_SFR 1 | ||
405 | |||
406 | #define S5PC100_PWR_STA_EXP_SCALE 0 | ||
407 | #define S5PC100_PWR_STA_CNT 4 | ||
408 | |||
409 | #define S5PC100_PWR_STABLE_COUNT 85500 | ||
410 | |||
411 | #define S5PC100_SLEEP_CFG_OSC_EN 0 | ||
412 | |||
413 | /* OTHERS Resgister */ | ||
414 | #define S5PC100_OTHERS_USB_SIG_MASK (1 << 16) | ||
415 | #define S5PC100_OTHERS_MIPI_DPHY_EN (1 << 28) | ||
416 | |||
417 | /* MIPI D-PHY Control Register 0 */ | ||
418 | #define S5PC100_MIPI_PHY_CON0_M_RESETN (1 << 1) | ||
419 | #define S5PC100_MIPI_PHY_CON0_S_RESETN (1 << 0) | ||
420 | |||
421 | #endif /* _PLAT_REGS_CLOCK_H */ | ||
diff --git a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h b/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h new file mode 100644 index 000000000000..45e275131665 --- /dev/null +++ b/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h | |||
@@ -0,0 +1,65 @@ | |||
1 | /* arch/arm/plat-s5pc1xx/include/plat/s5pc100.h | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * Header file for s5pc100 cpu support | ||
7 | * | ||
8 | * Based on plat-s3c64xx/include/plat/s3c6400.h | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | /* Common init code for S5PC100 related SoCs */ | ||
16 | extern int s5pc100_init(void); | ||
17 | extern void s5pc100_map_io(void); | ||
18 | extern void s5pc100_init_clocks(int xtal); | ||
19 | extern int s5pc100_register_baseclocks(unsigned long xtal); | ||
20 | extern void s5pc100_init_irq(void); | ||
21 | extern void s5pc100_init_io(struct map_desc *mach_desc, int size); | ||
22 | extern void s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no); | ||
23 | extern void s5pc100_register_clocks(void); | ||
24 | extern void s5pc100_setup_clocks(void); | ||
25 | extern struct sysdev_class s5pc100_sysclass; | ||
26 | |||
27 | #define s5pc100_init_uarts s5pc100_common_init_uarts | ||
28 | |||
29 | /* Some day, belows will be moved to plat-s5pc/include/plat/cpu.h */ | ||
30 | extern void s5pc1xx_init_irq(u32 *vic_valid, int num); | ||
31 | extern void s5pc1xx_init_io(struct map_desc *mach_desc, int size); | ||
32 | |||
33 | /* Some day, belows will be moved to plat-s5pc/include/plat/clock.h */ | ||
34 | extern struct clk clk_hpll; | ||
35 | extern struct clk clk_hd0; | ||
36 | extern struct clk clk_pd0; | ||
37 | extern struct clk clk_54m; | ||
38 | extern struct clk clk_dout_mpll2; | ||
39 | extern void s5pc1xx_register_clocks(void); | ||
40 | extern int s5pc1xx_sclk0_ctrl(struct clk *clk, int enable); | ||
41 | extern int s5pc1xx_sclk1_ctrl(struct clk *clk, int enable); | ||
42 | |||
43 | /* Some day, belows will be moved to plat-s5pc/include/plat/devs.h */ | ||
44 | extern struct s3c24xx_uart_resources s5pc1xx_uart_resources[]; | ||
45 | extern struct platform_device s3c_device_g2d; | ||
46 | extern struct platform_device s3c_device_g3d; | ||
47 | extern struct platform_device s3c_device_vpp; | ||
48 | extern struct platform_device s3c_device_tvenc; | ||
49 | extern struct platform_device s3c_device_tvscaler; | ||
50 | extern struct platform_device s3c_device_rotator; | ||
51 | extern struct platform_device s3c_device_jpeg; | ||
52 | extern struct platform_device s3c_device_onenand; | ||
53 | extern struct platform_device s3c_device_usb_otghcd; | ||
54 | extern struct platform_device s3c_device_keypad; | ||
55 | extern struct platform_device s3c_device_ts; | ||
56 | extern struct platform_device s3c_device_g3d; | ||
57 | extern struct platform_device s3c_device_smc911x; | ||
58 | extern struct platform_device s3c_device_fimc0; | ||
59 | extern struct platform_device s3c_device_fimc1; | ||
60 | extern struct platform_device s3c_device_mfc; | ||
61 | extern struct platform_device s3c_device_ac97; | ||
62 | extern struct platform_device s3c_device_fimc0; | ||
63 | extern struct platform_device s3c_device_fimc1; | ||
64 | extern struct platform_device s3c_device_fimc2; | ||
65 | |||
diff --git a/arch/arm/plat-s5pc1xx/irq.c b/arch/arm/plat-s5pc1xx/irq.c new file mode 100644 index 000000000000..80d6dd942cb8 --- /dev/null +++ b/arch/arm/plat-s5pc1xx/irq.c | |||
@@ -0,0 +1,259 @@ | |||
1 | /* arch/arm/plat-s5pc1xx/irq.c | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * S5PC1XX - Interrupt handling | ||
7 | * | ||
8 | * Based on plat-s3c64xx/irq.c | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/interrupt.h> | ||
17 | #include <linux/irq.h> | ||
18 | #include <linux/io.h> | ||
19 | |||
20 | #include <asm/hardware/vic.h> | ||
21 | |||
22 | #include <mach/map.h> | ||
23 | #include <plat/regs-timer.h> | ||
24 | #include <plat/cpu.h> | ||
25 | |||
26 | /* Timer interrupt handling */ | ||
27 | |||
28 | static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq) | ||
29 | { | ||
30 | generic_handle_irq(sub_irq); | ||
31 | } | ||
32 | |||
33 | static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc) | ||
34 | { | ||
35 | s3c_irq_demux_timer(irq, IRQ_TIMER0); | ||
36 | } | ||
37 | |||
38 | static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc) | ||
39 | { | ||
40 | s3c_irq_demux_timer(irq, IRQ_TIMER1); | ||
41 | } | ||
42 | |||
43 | static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc) | ||
44 | { | ||
45 | s3c_irq_demux_timer(irq, IRQ_TIMER2); | ||
46 | } | ||
47 | |||
48 | static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc) | ||
49 | { | ||
50 | s3c_irq_demux_timer(irq, IRQ_TIMER3); | ||
51 | } | ||
52 | |||
53 | static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc) | ||
54 | { | ||
55 | s3c_irq_demux_timer(irq, IRQ_TIMER4); | ||
56 | } | ||
57 | |||
58 | /* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ | ||
59 | |||
60 | static void s3c_irq_timer_mask(unsigned int irq) | ||
61 | { | ||
62 | u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); | ||
63 | |||
64 | reg &= 0x1f; /* mask out pending interrupts */ | ||
65 | reg &= ~(1 << (irq - IRQ_TIMER0)); | ||
66 | __raw_writel(reg, S3C64XX_TINT_CSTAT); | ||
67 | } | ||
68 | |||
69 | static void s3c_irq_timer_unmask(unsigned int irq) | ||
70 | { | ||
71 | u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); | ||
72 | |||
73 | reg &= 0x1f; /* mask out pending interrupts */ | ||
74 | reg |= 1 << (irq - IRQ_TIMER0); | ||
75 | __raw_writel(reg, S3C64XX_TINT_CSTAT); | ||
76 | } | ||
77 | |||
78 | static void s3c_irq_timer_ack(unsigned int irq) | ||
79 | { | ||
80 | u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); | ||
81 | |||
82 | reg &= 0x1f; | ||
83 | reg |= (1 << 5) << (irq - IRQ_TIMER0); | ||
84 | __raw_writel(reg, S3C64XX_TINT_CSTAT); | ||
85 | } | ||
86 | |||
87 | static struct irq_chip s3c_irq_timer = { | ||
88 | .name = "s3c-timer", | ||
89 | .mask = s3c_irq_timer_mask, | ||
90 | .unmask = s3c_irq_timer_unmask, | ||
91 | .ack = s3c_irq_timer_ack, | ||
92 | }; | ||
93 | |||
94 | struct uart_irq { | ||
95 | void __iomem *regs; | ||
96 | unsigned int base_irq; | ||
97 | unsigned int parent_irq; | ||
98 | }; | ||
99 | |||
100 | /* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] | ||
101 | * are consecutive when looking up the interrupt in the demux routines. | ||
102 | */ | ||
103 | static struct uart_irq uart_irqs[] = { | ||
104 | [0] = { | ||
105 | .regs = (void *)S3C_VA_UART0, | ||
106 | .base_irq = IRQ_S3CUART_BASE0, | ||
107 | .parent_irq = IRQ_UART0, | ||
108 | }, | ||
109 | [1] = { | ||
110 | .regs = (void *)S3C_VA_UART1, | ||
111 | .base_irq = IRQ_S3CUART_BASE1, | ||
112 | .parent_irq = IRQ_UART1, | ||
113 | }, | ||
114 | [2] = { | ||
115 | .regs = (void *)S3C_VA_UART2, | ||
116 | .base_irq = IRQ_S3CUART_BASE2, | ||
117 | .parent_irq = IRQ_UART2, | ||
118 | }, | ||
119 | [3] = { | ||
120 | .regs = (void *)S3C_VA_UART3, | ||
121 | .base_irq = IRQ_S3CUART_BASE3, | ||
122 | .parent_irq = IRQ_UART3, | ||
123 | }, | ||
124 | }; | ||
125 | |||
126 | static inline void __iomem *s3c_irq_uart_base(unsigned int irq) | ||
127 | { | ||
128 | struct uart_irq *uirq = get_irq_chip_data(irq); | ||
129 | return uirq->regs; | ||
130 | } | ||
131 | |||
132 | static inline unsigned int s3c_irq_uart_bit(unsigned int irq) | ||
133 | { | ||
134 | return irq & 3; | ||
135 | } | ||
136 | |||
137 | /* UART interrupt registers, not worth adding to seperate include header */ | ||
138 | #define S3C64XX_UINTP 0x30 | ||
139 | #define S3C64XX_UINTSP 0x34 | ||
140 | #define S3C64XX_UINTM 0x38 | ||
141 | |||
142 | static void s3c_irq_uart_mask(unsigned int irq) | ||
143 | { | ||
144 | void __iomem *regs = s3c_irq_uart_base(irq); | ||
145 | unsigned int bit = s3c_irq_uart_bit(irq); | ||
146 | u32 reg; | ||
147 | |||
148 | reg = __raw_readl(regs + S3C64XX_UINTM); | ||
149 | reg |= (1 << bit); | ||
150 | __raw_writel(reg, regs + S3C64XX_UINTM); | ||
151 | } | ||
152 | |||
153 | static void s3c_irq_uart_maskack(unsigned int irq) | ||
154 | { | ||
155 | void __iomem *regs = s3c_irq_uart_base(irq); | ||
156 | unsigned int bit = s3c_irq_uart_bit(irq); | ||
157 | u32 reg; | ||
158 | |||
159 | reg = __raw_readl(regs + S3C64XX_UINTM); | ||
160 | reg |= (1 << bit); | ||
161 | __raw_writel(reg, regs + S3C64XX_UINTM); | ||
162 | __raw_writel(1 << bit, regs + S3C64XX_UINTP); | ||
163 | } | ||
164 | |||
165 | static void s3c_irq_uart_unmask(unsigned int irq) | ||
166 | { | ||
167 | void __iomem *regs = s3c_irq_uart_base(irq); | ||
168 | unsigned int bit = s3c_irq_uart_bit(irq); | ||
169 | u32 reg; | ||
170 | |||
171 | reg = __raw_readl(regs + S3C64XX_UINTM); | ||
172 | reg &= ~(1 << bit); | ||
173 | __raw_writel(reg, regs + S3C64XX_UINTM); | ||
174 | } | ||
175 | |||
176 | static void s3c_irq_uart_ack(unsigned int irq) | ||
177 | { | ||
178 | void __iomem *regs = s3c_irq_uart_base(irq); | ||
179 | unsigned int bit = s3c_irq_uart_bit(irq); | ||
180 | |||
181 | __raw_writel(1 << bit, regs + S3C64XX_UINTP); | ||
182 | } | ||
183 | |||
184 | static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) | ||
185 | { | ||
186 | struct uart_irq *uirq = &uart_irqs[irq - IRQ_UART0]; | ||
187 | u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP); | ||
188 | int base = uirq->base_irq; | ||
189 | |||
190 | if (pend & (1 << 0)) | ||
191 | generic_handle_irq(base); | ||
192 | if (pend & (1 << 1)) | ||
193 | generic_handle_irq(base + 1); | ||
194 | if (pend & (1 << 2)) | ||
195 | generic_handle_irq(base + 2); | ||
196 | if (pend & (1 << 3)) | ||
197 | generic_handle_irq(base + 3); | ||
198 | } | ||
199 | |||
200 | static struct irq_chip s3c_irq_uart = { | ||
201 | .name = "s3c-uart", | ||
202 | .mask = s3c_irq_uart_mask, | ||
203 | .unmask = s3c_irq_uart_unmask, | ||
204 | .mask_ack = s3c_irq_uart_maskack, | ||
205 | .ack = s3c_irq_uart_ack, | ||
206 | }; | ||
207 | |||
208 | static void __init s5pc1xx_uart_irq(struct uart_irq *uirq) | ||
209 | { | ||
210 | void __iomem *reg_base = uirq->regs; | ||
211 | unsigned int irq; | ||
212 | int offs; | ||
213 | |||
214 | /* mask all interrupts at the start. */ | ||
215 | __raw_writel(0xf, reg_base + S3C64XX_UINTM); | ||
216 | |||
217 | for (offs = 0; offs < 3; offs++) { | ||
218 | irq = uirq->base_irq + offs; | ||
219 | |||
220 | set_irq_chip(irq, &s3c_irq_uart); | ||
221 | set_irq_chip_data(irq, uirq); | ||
222 | set_irq_handler(irq, handle_level_irq); | ||
223 | set_irq_flags(irq, IRQF_VALID); | ||
224 | } | ||
225 | |||
226 | set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); | ||
227 | } | ||
228 | |||
229 | void __init s5pc1xx_init_irq(u32 *vic_valid, int num) | ||
230 | { | ||
231 | int i; | ||
232 | int uart, irq; | ||
233 | |||
234 | printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); | ||
235 | |||
236 | /* initialise the pair of VICs */ | ||
237 | for (i = 0; i < num; i++) | ||
238 | vic_init((void *)S5PC1XX_VA_VIC(i), S3C_IRQ(i * S3C_IRQ_OFFSET), | ||
239 | vic_valid[i], 0); | ||
240 | |||
241 | /* add the timer sub-irqs */ | ||
242 | |||
243 | set_irq_chained_handler(IRQ_TIMER0, s3c_irq_demux_timer0); | ||
244 | set_irq_chained_handler(IRQ_TIMER1, s3c_irq_demux_timer1); | ||
245 | set_irq_chained_handler(IRQ_TIMER2, s3c_irq_demux_timer2); | ||
246 | set_irq_chained_handler(IRQ_TIMER3, s3c_irq_demux_timer3); | ||
247 | set_irq_chained_handler(IRQ_TIMER4, s3c_irq_demux_timer4); | ||
248 | |||
249 | for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) { | ||
250 | set_irq_chip(irq, &s3c_irq_timer); | ||
251 | set_irq_handler(irq, handle_level_irq); | ||
252 | set_irq_flags(irq, IRQF_VALID); | ||
253 | } | ||
254 | |||
255 | for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++) | ||
256 | s5pc1xx_uart_irq(&uart_irqs[uart]); | ||
257 | } | ||
258 | |||
259 | |||
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/plat-s5pc1xx/s5pc100-clock.c new file mode 100644 index 000000000000..6b24035172fa --- /dev/null +++ b/arch/arm/plat-s5pc1xx/s5pc100-clock.c | |||
@@ -0,0 +1,1139 @@ | |||
1 | /* linux/arch/arm/plat-s5pc1xx/s5pc100-clock.c | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics, Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * S5PC100 based common clock support | ||
7 | * | ||
8 | * Based on plat-s3c64xx/s3c6400-clock.c | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/init.h> | ||
16 | #include <linux/module.h> | ||
17 | #include <linux/kernel.h> | ||
18 | #include <linux/list.h> | ||
19 | #include <linux/errno.h> | ||
20 | #include <linux/err.h> | ||
21 | #include <linux/clk.h> | ||
22 | #include <linux/sysdev.h> | ||
23 | #include <linux/io.h> | ||
24 | |||
25 | #include <mach/hardware.h> | ||
26 | #include <mach/map.h> | ||
27 | |||
28 | #include <plat/cpu-freq.h> | ||
29 | |||
30 | #include <plat/regs-clock.h> | ||
31 | #include <plat/clock.h> | ||
32 | #include <plat/cpu.h> | ||
33 | #include <plat/pll.h> | ||
34 | #include <plat/devs.h> | ||
35 | #include <plat/s5pc100.h> | ||
36 | |||
37 | /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call | ||
38 | * ext_xtal_mux for want of an actual name from the manual. | ||
39 | */ | ||
40 | |||
41 | static struct clk clk_ext_xtal_mux = { | ||
42 | .name = "ext_xtal", | ||
43 | .id = -1, | ||
44 | }; | ||
45 | |||
46 | #define clk_fin_apll clk_ext_xtal_mux | ||
47 | #define clk_fin_mpll clk_ext_xtal_mux | ||
48 | #define clk_fin_epll clk_ext_xtal_mux | ||
49 | #define clk_fin_hpll clk_ext_xtal_mux | ||
50 | |||
51 | #define clk_fout_mpll clk_mpll | ||
52 | |||
53 | struct clk_sources { | ||
54 | unsigned int nr_sources; | ||
55 | struct clk **sources; | ||
56 | }; | ||
57 | |||
58 | struct clksrc_clk { | ||
59 | struct clk clk; | ||
60 | unsigned int mask; | ||
61 | unsigned int shift; | ||
62 | |||
63 | struct clk_sources *sources; | ||
64 | |||
65 | unsigned int divider_shift; | ||
66 | void __iomem *reg_divider; | ||
67 | void __iomem *reg_source; | ||
68 | }; | ||
69 | |||
70 | static int clk_default_setrate(struct clk *clk, unsigned long rate) | ||
71 | { | ||
72 | clk->rate = rate; | ||
73 | return 1; | ||
74 | } | ||
75 | |||
76 | struct clk clk_27m = { | ||
77 | .name = "clk_27m", | ||
78 | .id = -1, | ||
79 | .rate = 27000000, | ||
80 | }; | ||
81 | |||
82 | static int clk_48m_ctrl(struct clk *clk, int enable) | ||
83 | { | ||
84 | unsigned long flags; | ||
85 | u32 val; | ||
86 | |||
87 | /* can't rely on clock lock, this register has other usages */ | ||
88 | local_irq_save(flags); | ||
89 | |||
90 | val = __raw_readl(S5PC1XX_CLK_SRC1); | ||
91 | if (enable) | ||
92 | val |= S5PC100_CLKSRC1_CLK48M_MASK; | ||
93 | else | ||
94 | val &= ~S5PC100_CLKSRC1_CLK48M_MASK; | ||
95 | |||
96 | __raw_writel(val, S5PC1XX_CLK_SRC1); | ||
97 | local_irq_restore(flags); | ||
98 | |||
99 | return 0; | ||
100 | } | ||
101 | |||
102 | struct clk clk_48m = { | ||
103 | .name = "clk_48m", | ||
104 | .id = -1, | ||
105 | .rate = 48000000, | ||
106 | .enable = clk_48m_ctrl, | ||
107 | }; | ||
108 | |||
109 | struct clk clk_54m = { | ||
110 | .name = "clk_54m", | ||
111 | .id = -1, | ||
112 | .rate = 54000000, | ||
113 | }; | ||
114 | |||
115 | struct clk clk_hpll = { | ||
116 | .name = "hpll", | ||
117 | .id = -1, | ||
118 | }; | ||
119 | |||
120 | struct clk clk_hd0 = { | ||
121 | .name = "hclkd0", | ||
122 | .id = -1, | ||
123 | .rate = 0, | ||
124 | .parent = NULL, | ||
125 | .ctrlbit = 0, | ||
126 | .set_rate = clk_default_setrate, | ||
127 | }; | ||
128 | |||
129 | struct clk clk_pd0 = { | ||
130 | .name = "pclkd0", | ||
131 | .id = -1, | ||
132 | .rate = 0, | ||
133 | .parent = NULL, | ||
134 | .ctrlbit = 0, | ||
135 | .set_rate = clk_default_setrate, | ||
136 | }; | ||
137 | |||
138 | static int s5pc1xx_clk_gate(void __iomem *reg, | ||
139 | struct clk *clk, | ||
140 | int enable) | ||
141 | { | ||
142 | unsigned int ctrlbit = clk->ctrlbit; | ||
143 | u32 con; | ||
144 | |||
145 | con = __raw_readl(reg); | ||
146 | |||
147 | if (enable) | ||
148 | con |= ctrlbit; | ||
149 | else | ||
150 | con &= ~ctrlbit; | ||
151 | |||
152 | __raw_writel(con, reg); | ||
153 | return 0; | ||
154 | } | ||
155 | |||
156 | static int s5pc1xx_clk_d00_ctrl(struct clk *clk, int enable) | ||
157 | { | ||
158 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable); | ||
159 | } | ||
160 | |||
161 | static int s5pc1xx_clk_d01_ctrl(struct clk *clk, int enable) | ||
162 | { | ||
163 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable); | ||
164 | } | ||
165 | |||
166 | static int s5pc1xx_clk_d02_ctrl(struct clk *clk, int enable) | ||
167 | { | ||
168 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable); | ||
169 | } | ||
170 | |||
171 | static int s5pc1xx_clk_d10_ctrl(struct clk *clk, int enable) | ||
172 | { | ||
173 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable); | ||
174 | } | ||
175 | |||
176 | static int s5pc1xx_clk_d11_ctrl(struct clk *clk, int enable) | ||
177 | { | ||
178 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable); | ||
179 | } | ||
180 | |||
181 | static int s5pc1xx_clk_d12_ctrl(struct clk *clk, int enable) | ||
182 | { | ||
183 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable); | ||
184 | } | ||
185 | |||
186 | static int s5pc1xx_clk_d13_ctrl(struct clk *clk, int enable) | ||
187 | { | ||
188 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable); | ||
189 | } | ||
190 | |||
191 | static int s5pc1xx_clk_d14_ctrl(struct clk *clk, int enable) | ||
192 | { | ||
193 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable); | ||
194 | } | ||
195 | |||
196 | static int s5pc1xx_clk_d15_ctrl(struct clk *clk, int enable) | ||
197 | { | ||
198 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable); | ||
199 | } | ||
200 | |||
201 | static int s5pc1xx_clk_d20_ctrl(struct clk *clk, int enable) | ||
202 | { | ||
203 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable); | ||
204 | } | ||
205 | |||
206 | int s5pc1xx_sclk0_ctrl(struct clk *clk, int enable) | ||
207 | { | ||
208 | return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable); | ||
209 | } | ||
210 | |||
211 | int s5pc1xx_sclk1_ctrl(struct clk *clk, int enable) | ||
212 | { | ||
213 | return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable); | ||
214 | } | ||
215 | |||
216 | static struct clk init_clocks_disable[] = { | ||
217 | { | ||
218 | .name = "dsi", | ||
219 | .id = -1, | ||
220 | .parent = &clk_p, | ||
221 | .enable = s5pc1xx_clk_d11_ctrl, | ||
222 | .ctrlbit = S5PC100_CLKGATE_D11_DSI, | ||
223 | }, { | ||
224 | .name = "csi", | ||
225 | .id = -1, | ||
226 | .parent = &clk_h, | ||
227 | .enable = s5pc1xx_clk_d11_ctrl, | ||
228 | .ctrlbit = S5PC100_CLKGATE_D11_CSI, | ||
229 | }, { | ||
230 | .name = "ccan0", | ||
231 | .id = 0, | ||
232 | .parent = &clk_p, | ||
233 | .enable = s5pc1xx_clk_d14_ctrl, | ||
234 | .ctrlbit = S5PC100_CLKGATE_D14_CCAN0, | ||
235 | }, { | ||
236 | .name = "ccan1", | ||
237 | .id = 1, | ||
238 | .parent = &clk_p, | ||
239 | .enable = s5pc1xx_clk_d14_ctrl, | ||
240 | .ctrlbit = S5PC100_CLKGATE_D14_CCAN1, | ||
241 | }, { | ||
242 | .name = "keypad", | ||
243 | .id = -1, | ||
244 | .parent = &clk_p, | ||
245 | .enable = s5pc1xx_clk_d15_ctrl, | ||
246 | .ctrlbit = S5PC100_CLKGATE_D15_KEYIF, | ||
247 | }, { | ||
248 | .name = "hclkd2", | ||
249 | .id = -1, | ||
250 | .parent = NULL, | ||
251 | .enable = s5pc1xx_clk_d20_ctrl, | ||
252 | .ctrlbit = S5PC100_CLKGATE_D20_HCLKD2, | ||
253 | }, { | ||
254 | .name = "iis-d2", | ||
255 | .id = -1, | ||
256 | .parent = NULL, | ||
257 | .enable = s5pc1xx_clk_d20_ctrl, | ||
258 | .ctrlbit = S5PC100_CLKGATE_D20_I2SD2, | ||
259 | }, { | ||
260 | .name = "otg", | ||
261 | .id = -1, | ||
262 | .parent = &clk_h, | ||
263 | .enable = s5pc1xx_clk_d10_ctrl, | ||
264 | .ctrlbit = S5PC100_CLKGATE_D10_USBOTG, | ||
265 | }, | ||
266 | }; | ||
267 | |||
268 | static struct clk init_clocks[] = { | ||
269 | /* System1 (D0_0) devices */ | ||
270 | { | ||
271 | .name = "intc", | ||
272 | .id = -1, | ||
273 | .parent = &clk_hd0, | ||
274 | .enable = s5pc1xx_clk_d00_ctrl, | ||
275 | .ctrlbit = S5PC100_CLKGATE_D00_INTC, | ||
276 | }, { | ||
277 | .name = "tzic", | ||
278 | .id = -1, | ||
279 | .parent = &clk_hd0, | ||
280 | .enable = s5pc1xx_clk_d00_ctrl, | ||
281 | .ctrlbit = S5PC100_CLKGATE_D00_TZIC, | ||
282 | }, { | ||
283 | .name = "cf-ata", | ||
284 | .id = -1, | ||
285 | .parent = &clk_hd0, | ||
286 | .enable = s5pc1xx_clk_d00_ctrl, | ||
287 | .ctrlbit = S5PC100_CLKGATE_D00_CFCON, | ||
288 | }, { | ||
289 | .name = "mdma", | ||
290 | .id = -1, | ||
291 | .parent = &clk_hd0, | ||
292 | .enable = s5pc1xx_clk_d00_ctrl, | ||
293 | .ctrlbit = S5PC100_CLKGATE_D00_MDMA, | ||
294 | }, { | ||
295 | .name = "g2d", | ||
296 | .id = -1, | ||
297 | .parent = &clk_hd0, | ||
298 | .enable = s5pc1xx_clk_d00_ctrl, | ||
299 | .ctrlbit = S5PC100_CLKGATE_D00_G2D, | ||
300 | }, { | ||
301 | .name = "secss", | ||
302 | .id = -1, | ||
303 | .parent = &clk_hd0, | ||
304 | .enable = s5pc1xx_clk_d00_ctrl, | ||
305 | .ctrlbit = S5PC100_CLKGATE_D00_SECSS, | ||
306 | }, { | ||
307 | .name = "cssys", | ||
308 | .id = -1, | ||
309 | .parent = &clk_hd0, | ||
310 | .enable = s5pc1xx_clk_d00_ctrl, | ||
311 | .ctrlbit = S5PC100_CLKGATE_D00_CSSYS, | ||
312 | }, | ||
313 | |||
314 | /* Memory (D0_1) devices */ | ||
315 | { | ||
316 | .name = "dmc", | ||
317 | .id = -1, | ||
318 | .parent = &clk_hd0, | ||
319 | .enable = s5pc1xx_clk_d01_ctrl, | ||
320 | .ctrlbit = S5PC100_CLKGATE_D01_DMC, | ||
321 | }, { | ||
322 | .name = "sromc", | ||
323 | .id = -1, | ||
324 | .parent = &clk_hd0, | ||
325 | .enable = s5pc1xx_clk_d01_ctrl, | ||
326 | .ctrlbit = S5PC100_CLKGATE_D01_SROMC, | ||
327 | }, { | ||
328 | .name = "onenand", | ||
329 | .id = -1, | ||
330 | .parent = &clk_hd0, | ||
331 | .enable = s5pc1xx_clk_d01_ctrl, | ||
332 | .ctrlbit = S5PC100_CLKGATE_D01_ONENAND, | ||
333 | }, { | ||
334 | .name = "nand", | ||
335 | .id = -1, | ||
336 | .parent = &clk_hd0, | ||
337 | .enable = s5pc1xx_clk_d01_ctrl, | ||
338 | .ctrlbit = S5PC100_CLKGATE_D01_NFCON, | ||
339 | }, { | ||
340 | .name = "intmem", | ||
341 | .id = -1, | ||
342 | .parent = &clk_hd0, | ||
343 | .enable = s5pc1xx_clk_d01_ctrl, | ||
344 | .ctrlbit = S5PC100_CLKGATE_D01_INTMEM, | ||
345 | }, { | ||
346 | .name = "ebi", | ||
347 | .id = -1, | ||
348 | .parent = &clk_hd0, | ||
349 | .enable = s5pc1xx_clk_d01_ctrl, | ||
350 | .ctrlbit = S5PC100_CLKGATE_D01_EBI, | ||
351 | }, | ||
352 | |||
353 | /* System2 (D0_2) devices */ | ||
354 | { | ||
355 | .name = "seckey", | ||
356 | .id = -1, | ||
357 | .parent = &clk_pd0, | ||
358 | .enable = s5pc1xx_clk_d02_ctrl, | ||
359 | .ctrlbit = S5PC100_CLKGATE_D02_SECKEY, | ||
360 | }, { | ||
361 | .name = "sdm", | ||
362 | .id = -1, | ||
363 | .parent = &clk_hd0, | ||
364 | .enable = s5pc1xx_clk_d02_ctrl, | ||
365 | .ctrlbit = S5PC100_CLKGATE_D02_SDM, | ||
366 | }, | ||
367 | |||
368 | /* File (D1_0) devices */ | ||
369 | { | ||
370 | .name = "pdma0", | ||
371 | .id = -1, | ||
372 | .parent = &clk_h, | ||
373 | .enable = s5pc1xx_clk_d10_ctrl, | ||
374 | .ctrlbit = S5PC100_CLKGATE_D10_PDMA0, | ||
375 | }, { | ||
376 | .name = "pdma1", | ||
377 | .id = -1, | ||
378 | .parent = &clk_h, | ||
379 | .enable = s5pc1xx_clk_d10_ctrl, | ||
380 | .ctrlbit = S5PC100_CLKGATE_D10_PDMA1, | ||
381 | }, { | ||
382 | .name = "usb-host", | ||
383 | .id = -1, | ||
384 | .parent = &clk_h, | ||
385 | .enable = s5pc1xx_clk_d10_ctrl, | ||
386 | .ctrlbit = S5PC100_CLKGATE_D10_USBHOST, | ||
387 | }, { | ||
388 | .name = "modem", | ||
389 | .id = -1, | ||
390 | .parent = &clk_h, | ||
391 | .enable = s5pc1xx_clk_d10_ctrl, | ||
392 | .ctrlbit = S5PC100_CLKGATE_D10_MODEMIF, | ||
393 | }, { | ||
394 | .name = "hsmmc", | ||
395 | .id = 0, | ||
396 | .parent = &clk_h, | ||
397 | .enable = s5pc1xx_clk_d10_ctrl, | ||
398 | .ctrlbit = S5PC100_CLKGATE_D10_HSMMC0, | ||
399 | }, { | ||
400 | .name = "hsmmc", | ||
401 | .id = 1, | ||
402 | .parent = &clk_h, | ||
403 | .enable = s5pc1xx_clk_d10_ctrl, | ||
404 | .ctrlbit = S5PC100_CLKGATE_D10_HSMMC1, | ||
405 | }, { | ||
406 | .name = "hsmmc", | ||
407 | .id = 2, | ||
408 | .parent = &clk_h, | ||
409 | .enable = s5pc1xx_clk_d10_ctrl, | ||
410 | .ctrlbit = S5PC100_CLKGATE_D10_HSMMC2, | ||
411 | }, | ||
412 | |||
413 | /* Multimedia1 (D1_1) devices */ | ||
414 | { | ||
415 | .name = "lcd", | ||
416 | .id = -1, | ||
417 | .parent = &clk_h, | ||
418 | .enable = s5pc1xx_clk_d11_ctrl, | ||
419 | .ctrlbit = S5PC100_CLKGATE_D11_LCD, | ||
420 | }, { | ||
421 | .name = "rotator", | ||
422 | .id = -1, | ||
423 | .parent = &clk_h, | ||
424 | .enable = s5pc1xx_clk_d11_ctrl, | ||
425 | .ctrlbit = S5PC100_CLKGATE_D11_ROTATOR, | ||
426 | }, { | ||
427 | .name = "fimc", | ||
428 | .id = 0, | ||
429 | .parent = &clk_h, | ||
430 | .enable = s5pc1xx_clk_d11_ctrl, | ||
431 | .ctrlbit = S5PC100_CLKGATE_D11_FIMC0, | ||
432 | }, { | ||
433 | .name = "fimc", | ||
434 | .id = 1, | ||
435 | .parent = &clk_h, | ||
436 | .enable = s5pc1xx_clk_d11_ctrl, | ||
437 | .ctrlbit = S5PC100_CLKGATE_D11_FIMC1, | ||
438 | }, { | ||
439 | .name = "fimc", | ||
440 | .id = 2, | ||
441 | .parent = &clk_h, | ||
442 | .enable = s5pc1xx_clk_d11_ctrl, | ||
443 | .ctrlbit = S5PC100_CLKGATE_D11_FIMC2, | ||
444 | }, { | ||
445 | .name = "jpeg", | ||
446 | .id = -1, | ||
447 | .parent = &clk_h, | ||
448 | .enable = s5pc1xx_clk_d11_ctrl, | ||
449 | .ctrlbit = S5PC100_CLKGATE_D11_JPEG, | ||
450 | }, { | ||
451 | .name = "g3d", | ||
452 | .id = -1, | ||
453 | .parent = &clk_h, | ||
454 | .enable = s5pc1xx_clk_d11_ctrl, | ||
455 | .ctrlbit = S5PC100_CLKGATE_D11_G3D, | ||
456 | }, | ||
457 | |||
458 | /* Multimedia2 (D1_2) devices */ | ||
459 | { | ||
460 | .name = "tv", | ||
461 | .id = -1, | ||
462 | .parent = &clk_h, | ||
463 | .enable = s5pc1xx_clk_d12_ctrl, | ||
464 | .ctrlbit = S5PC100_CLKGATE_D12_TV, | ||
465 | }, { | ||
466 | .name = "vp", | ||
467 | .id = -1, | ||
468 | .parent = &clk_h, | ||
469 | .enable = s5pc1xx_clk_d12_ctrl, | ||
470 | .ctrlbit = S5PC100_CLKGATE_D12_VP, | ||
471 | }, { | ||
472 | .name = "mixer", | ||
473 | .id = -1, | ||
474 | .parent = &clk_h, | ||
475 | .enable = s5pc1xx_clk_d12_ctrl, | ||
476 | .ctrlbit = S5PC100_CLKGATE_D12_MIXER, | ||
477 | }, { | ||
478 | .name = "hdmi", | ||
479 | .id = -1, | ||
480 | .parent = &clk_h, | ||
481 | .enable = s5pc1xx_clk_d12_ctrl, | ||
482 | .ctrlbit = S5PC100_CLKGATE_D12_HDMI, | ||
483 | }, { | ||
484 | .name = "mfc", | ||
485 | .id = -1, | ||
486 | .parent = &clk_h, | ||
487 | .enable = s5pc1xx_clk_d12_ctrl, | ||
488 | .ctrlbit = S5PC100_CLKGATE_D12_MFC, | ||
489 | }, | ||
490 | |||
491 | /* System (D1_3) devices */ | ||
492 | { | ||
493 | .name = "chipid", | ||
494 | .id = -1, | ||
495 | .parent = &clk_p, | ||
496 | .enable = s5pc1xx_clk_d13_ctrl, | ||
497 | .ctrlbit = S5PC100_CLKGATE_D13_CHIPID, | ||
498 | }, { | ||
499 | .name = "gpio", | ||
500 | .id = -1, | ||
501 | .parent = &clk_p, | ||
502 | .enable = s5pc1xx_clk_d13_ctrl, | ||
503 | .ctrlbit = S5PC100_CLKGATE_D13_GPIO, | ||
504 | }, { | ||
505 | .name = "apc", | ||
506 | .id = -1, | ||
507 | .parent = &clk_p, | ||
508 | .enable = s5pc1xx_clk_d13_ctrl, | ||
509 | .ctrlbit = S5PC100_CLKGATE_D13_APC, | ||
510 | }, { | ||
511 | .name = "iec", | ||
512 | .id = -1, | ||
513 | .parent = &clk_p, | ||
514 | .enable = s5pc1xx_clk_d13_ctrl, | ||
515 | .ctrlbit = S5PC100_CLKGATE_D13_IEC, | ||
516 | }, { | ||
517 | .name = "timers", | ||
518 | .id = -1, | ||
519 | .parent = &clk_p, | ||
520 | .enable = s5pc1xx_clk_d13_ctrl, | ||
521 | .ctrlbit = S5PC100_CLKGATE_D13_PWM, | ||
522 | }, { | ||
523 | .name = "systimer", | ||
524 | .id = -1, | ||
525 | .parent = &clk_p, | ||
526 | .enable = s5pc1xx_clk_d13_ctrl, | ||
527 | .ctrlbit = S5PC100_CLKGATE_D13_SYSTIMER, | ||
528 | }, { | ||
529 | .name = "watchdog", | ||
530 | .id = -1, | ||
531 | .parent = &clk_p, | ||
532 | .enable = s5pc1xx_clk_d13_ctrl, | ||
533 | .ctrlbit = S5PC100_CLKGATE_D13_WDT, | ||
534 | }, { | ||
535 | .name = "rtc", | ||
536 | .id = -1, | ||
537 | .parent = &clk_p, | ||
538 | .enable = s5pc1xx_clk_d13_ctrl, | ||
539 | .ctrlbit = S5PC100_CLKGATE_D13_RTC, | ||
540 | }, | ||
541 | |||
542 | /* Connectivity (D1_4) devices */ | ||
543 | { | ||
544 | .name = "uart", | ||
545 | .id = 0, | ||
546 | .parent = &clk_p, | ||
547 | .enable = s5pc1xx_clk_d14_ctrl, | ||
548 | .ctrlbit = S5PC100_CLKGATE_D14_UART0, | ||
549 | }, { | ||
550 | .name = "uart", | ||
551 | .id = 1, | ||
552 | .parent = &clk_p, | ||
553 | .enable = s5pc1xx_clk_d14_ctrl, | ||
554 | .ctrlbit = S5PC100_CLKGATE_D14_UART1, | ||
555 | }, { | ||
556 | .name = "uart", | ||
557 | .id = 2, | ||
558 | .parent = &clk_p, | ||
559 | .enable = s5pc1xx_clk_d14_ctrl, | ||
560 | .ctrlbit = S5PC100_CLKGATE_D14_UART2, | ||
561 | }, { | ||
562 | .name = "uart", | ||
563 | .id = 3, | ||
564 | .parent = &clk_p, | ||
565 | .enable = s5pc1xx_clk_d14_ctrl, | ||
566 | .ctrlbit = S5PC100_CLKGATE_D14_UART3, | ||
567 | }, { | ||
568 | .name = "i2c", | ||
569 | .id = -1, | ||
570 | .parent = &clk_p, | ||
571 | .enable = s5pc1xx_clk_d14_ctrl, | ||
572 | .ctrlbit = S5PC100_CLKGATE_D14_IIC, | ||
573 | }, { | ||
574 | .name = "hdmi-i2c", | ||
575 | .id = -1, | ||
576 | .parent = &clk_p, | ||
577 | .enable = s5pc1xx_clk_d14_ctrl, | ||
578 | .ctrlbit = S5PC100_CLKGATE_D14_HDMI_IIC, | ||
579 | }, { | ||
580 | .name = "spi", | ||
581 | .id = 0, | ||
582 | .parent = &clk_p, | ||
583 | .enable = s5pc1xx_clk_d14_ctrl, | ||
584 | .ctrlbit = S5PC100_CLKGATE_D14_SPI0, | ||
585 | }, { | ||
586 | .name = "spi", | ||
587 | .id = 1, | ||
588 | .parent = &clk_p, | ||
589 | .enable = s5pc1xx_clk_d14_ctrl, | ||
590 | .ctrlbit = S5PC100_CLKGATE_D14_SPI1, | ||
591 | }, { | ||
592 | .name = "spi", | ||
593 | .id = 2, | ||
594 | .parent = &clk_p, | ||
595 | .enable = s5pc1xx_clk_d14_ctrl, | ||
596 | .ctrlbit = S5PC100_CLKGATE_D14_SPI2, | ||
597 | }, { | ||
598 | .name = "irda", | ||
599 | .id = -1, | ||
600 | .parent = &clk_p, | ||
601 | .enable = s5pc1xx_clk_d14_ctrl, | ||
602 | .ctrlbit = S5PC100_CLKGATE_D14_IRDA, | ||
603 | }, { | ||
604 | .name = "hsitx", | ||
605 | .id = -1, | ||
606 | .parent = &clk_p, | ||
607 | .enable = s5pc1xx_clk_d14_ctrl, | ||
608 | .ctrlbit = S5PC100_CLKGATE_D14_HSITX, | ||
609 | }, { | ||
610 | .name = "hsirx", | ||
611 | .id = -1, | ||
612 | .parent = &clk_p, | ||
613 | .enable = s5pc1xx_clk_d14_ctrl, | ||
614 | .ctrlbit = S5PC100_CLKGATE_D14_HSIRX, | ||
615 | }, | ||
616 | |||
617 | /* Audio (D1_5) devices */ | ||
618 | { | ||
619 | .name = "iis", | ||
620 | .id = 0, | ||
621 | .parent = &clk_p, | ||
622 | .enable = s5pc1xx_clk_d15_ctrl, | ||
623 | .ctrlbit = S5PC100_CLKGATE_D15_IIS0, | ||
624 | }, { | ||
625 | .name = "iis", | ||
626 | .id = 1, | ||
627 | .parent = &clk_p, | ||
628 | .enable = s5pc1xx_clk_d15_ctrl, | ||
629 | .ctrlbit = S5PC100_CLKGATE_D15_IIS1, | ||
630 | }, { | ||
631 | .name = "iis", | ||
632 | .id = 2, | ||
633 | .parent = &clk_p, | ||
634 | .enable = s5pc1xx_clk_d15_ctrl, | ||
635 | .ctrlbit = S5PC100_CLKGATE_D15_IIS2, | ||
636 | }, { | ||
637 | .name = "ac97", | ||
638 | .id = -1, | ||
639 | .parent = &clk_p, | ||
640 | .enable = s5pc1xx_clk_d15_ctrl, | ||
641 | .ctrlbit = S5PC100_CLKGATE_D15_AC97, | ||
642 | }, { | ||
643 | .name = "pcm", | ||
644 | .id = 0, | ||
645 | .parent = &clk_p, | ||
646 | .enable = s5pc1xx_clk_d15_ctrl, | ||
647 | .ctrlbit = S5PC100_CLKGATE_D15_PCM0, | ||
648 | }, { | ||
649 | .name = "pcm", | ||
650 | .id = 1, | ||
651 | .parent = &clk_p, | ||
652 | .enable = s5pc1xx_clk_d15_ctrl, | ||
653 | .ctrlbit = S5PC100_CLKGATE_D15_PCM1, | ||
654 | }, { | ||
655 | .name = "spdif", | ||
656 | .id = -1, | ||
657 | .parent = &clk_p, | ||
658 | .enable = s5pc1xx_clk_d15_ctrl, | ||
659 | .ctrlbit = S5PC100_CLKGATE_D15_SPDIF, | ||
660 | }, { | ||
661 | .name = "adc", | ||
662 | .id = -1, | ||
663 | .parent = &clk_p, | ||
664 | .enable = s5pc1xx_clk_d15_ctrl, | ||
665 | .ctrlbit = S5PC100_CLKGATE_D15_TSADC, | ||
666 | }, { | ||
667 | .name = "keyif", | ||
668 | .id = -1, | ||
669 | .parent = &clk_p, | ||
670 | .enable = s5pc1xx_clk_d15_ctrl, | ||
671 | .ctrlbit = S5PC100_CLKGATE_D15_KEYIF, | ||
672 | }, { | ||
673 | .name = "cg", | ||
674 | .id = -1, | ||
675 | .parent = &clk_p, | ||
676 | .enable = s5pc1xx_clk_d15_ctrl, | ||
677 | .ctrlbit = S5PC100_CLKGATE_D15_CG, | ||
678 | }, | ||
679 | |||
680 | /* Audio (D2_0) devices: all disabled */ | ||
681 | |||
682 | /* Special Clocks 1 */ | ||
683 | { | ||
684 | .name = "sclk_hpm", | ||
685 | .id = -1, | ||
686 | .parent = NULL, | ||
687 | .enable = s5pc1xx_sclk0_ctrl, | ||
688 | .ctrlbit = S5PC1XX_CLKGATE_SCLK0_HPM, | ||
689 | }, { | ||
690 | .name = "sclk_onenand", | ||
691 | .id = -1, | ||
692 | .parent = NULL, | ||
693 | .enable = s5pc1xx_sclk0_ctrl, | ||
694 | .ctrlbit = S5PC100_CLKGATE_SCLK0_ONENAND, | ||
695 | }, { | ||
696 | .name = "sclk_spi_48", | ||
697 | .id = 0, | ||
698 | .parent = &clk_48m, | ||
699 | .enable = s5pc1xx_sclk0_ctrl, | ||
700 | .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0_48, | ||
701 | }, { | ||
702 | .name = "sclk_spi_48", | ||
703 | .id = 1, | ||
704 | .parent = &clk_48m, | ||
705 | .enable = s5pc1xx_sclk0_ctrl, | ||
706 | .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1_48, | ||
707 | }, { | ||
708 | .name = "sclk_spi_48", | ||
709 | .id = 2, | ||
710 | .parent = &clk_48m, | ||
711 | .enable = s5pc1xx_sclk0_ctrl, | ||
712 | .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2_48, | ||
713 | }, { | ||
714 | .name = "sclk_mmc_48", | ||
715 | .id = 0, | ||
716 | .parent = &clk_48m, | ||
717 | .enable = s5pc1xx_sclk0_ctrl, | ||
718 | .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0_48, | ||
719 | }, { | ||
720 | .name = "sclk_mmc_48", | ||
721 | .id = 1, | ||
722 | .parent = &clk_48m, | ||
723 | .enable = s5pc1xx_sclk0_ctrl, | ||
724 | .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1_48, | ||
725 | }, { | ||
726 | .name = "sclk_mmc_48", | ||
727 | .id = 2, | ||
728 | .parent = &clk_48m, | ||
729 | .enable = s5pc1xx_sclk0_ctrl, | ||
730 | .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2_48, | ||
731 | }, | ||
732 | |||
733 | /* Special Clocks 2 */ | ||
734 | { | ||
735 | .name = "sclk_tv_54", | ||
736 | .id = -1, | ||
737 | .parent = &clk_54m, | ||
738 | .enable = s5pc1xx_sclk1_ctrl, | ||
739 | .ctrlbit = S5PC100_CLKGATE_SCLK1_TV54, | ||
740 | }, { | ||
741 | .name = "sclk_vdac_54", | ||
742 | .id = -1, | ||
743 | .parent = &clk_54m, | ||
744 | .enable = s5pc1xx_sclk1_ctrl, | ||
745 | .ctrlbit = S5PC100_CLKGATE_SCLK1_VDAC54, | ||
746 | }, { | ||
747 | .name = "sclk_spdif", | ||
748 | .id = -1, | ||
749 | .parent = NULL, | ||
750 | .enable = s5pc1xx_sclk1_ctrl, | ||
751 | .ctrlbit = S5PC100_CLKGATE_SCLK1_SPDIF, | ||
752 | }, | ||
753 | }; | ||
754 | |||
755 | void __init s5pc1xx_register_clocks(void) | ||
756 | { | ||
757 | struct clk *clkp; | ||
758 | int ret; | ||
759 | int ptr; | ||
760 | |||
761 | clkp = init_clocks; | ||
762 | for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) { | ||
763 | ret = s3c24xx_register_clock(clkp); | ||
764 | if (ret < 0) { | ||
765 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | ||
766 | clkp->name, ret); | ||
767 | } | ||
768 | } | ||
769 | |||
770 | clkp = init_clocks_disable; | ||
771 | for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { | ||
772 | |||
773 | ret = s3c24xx_register_clock(clkp); | ||
774 | if (ret < 0) { | ||
775 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | ||
776 | clkp->name, ret); | ||
777 | } | ||
778 | |||
779 | (clkp->enable)(clkp, 0); | ||
780 | } | ||
781 | |||
782 | s3c_pwmclk_init(); | ||
783 | } | ||
784 | static struct clk clk_fout_apll = { | ||
785 | .name = "fout_apll", | ||
786 | .id = -1, | ||
787 | }; | ||
788 | |||
789 | static struct clk *clk_src_apll_list[] = { | ||
790 | [0] = &clk_fin_apll, | ||
791 | [1] = &clk_fout_apll, | ||
792 | }; | ||
793 | |||
794 | static struct clk_sources clk_src_apll = { | ||
795 | .sources = clk_src_apll_list, | ||
796 | .nr_sources = ARRAY_SIZE(clk_src_apll_list), | ||
797 | }; | ||
798 | |||
799 | static struct clksrc_clk clk_mout_apll = { | ||
800 | .clk = { | ||
801 | .name = "mout_apll", | ||
802 | .id = -1, | ||
803 | }, | ||
804 | .shift = S5PC1XX_CLKSRC0_APLL_SHIFT, | ||
805 | .mask = S5PC1XX_CLKSRC0_APLL_MASK, | ||
806 | .sources = &clk_src_apll, | ||
807 | .reg_source = S5PC1XX_CLK_SRC0, | ||
808 | }; | ||
809 | |||
810 | static struct clk clk_fout_epll = { | ||
811 | .name = "fout_epll", | ||
812 | .id = -1, | ||
813 | }; | ||
814 | |||
815 | static struct clk *clk_src_epll_list[] = { | ||
816 | [0] = &clk_fin_epll, | ||
817 | [1] = &clk_fout_epll, | ||
818 | }; | ||
819 | |||
820 | static struct clk_sources clk_src_epll = { | ||
821 | .sources = clk_src_epll_list, | ||
822 | .nr_sources = ARRAY_SIZE(clk_src_epll_list), | ||
823 | }; | ||
824 | |||
825 | static struct clksrc_clk clk_mout_epll = { | ||
826 | .clk = { | ||
827 | .name = "mout_epll", | ||
828 | .id = -1, | ||
829 | }, | ||
830 | .shift = S5PC1XX_CLKSRC0_EPLL_SHIFT, | ||
831 | .mask = S5PC1XX_CLKSRC0_EPLL_MASK, | ||
832 | .sources = &clk_src_epll, | ||
833 | .reg_source = S5PC1XX_CLK_SRC0, | ||
834 | }; | ||
835 | |||
836 | static struct clk *clk_src_mpll_list[] = { | ||
837 | [0] = &clk_fin_mpll, | ||
838 | [1] = &clk_fout_mpll, | ||
839 | }; | ||
840 | |||
841 | static struct clk_sources clk_src_mpll = { | ||
842 | .sources = clk_src_mpll_list, | ||
843 | .nr_sources = ARRAY_SIZE(clk_src_mpll_list), | ||
844 | }; | ||
845 | |||
846 | static struct clksrc_clk clk_mout_mpll = { | ||
847 | .clk = { | ||
848 | .name = "mout_mpll", | ||
849 | .id = -1, | ||
850 | }, | ||
851 | .shift = S5PC1XX_CLKSRC0_MPLL_SHIFT, | ||
852 | .mask = S5PC1XX_CLKSRC0_MPLL_MASK, | ||
853 | .sources = &clk_src_mpll, | ||
854 | .reg_source = S5PC1XX_CLK_SRC0, | ||
855 | }; | ||
856 | |||
857 | static unsigned long s5pc1xx_clk_doutmpll_get_rate(struct clk *clk) | ||
858 | { | ||
859 | unsigned long rate = clk_get_rate(clk->parent); | ||
860 | unsigned long clkdiv; | ||
861 | |||
862 | printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); | ||
863 | |||
864 | clkdiv = __raw_readl(S5PC1XX_CLK_DIV1) & S5PC100_CLKDIV1_MPLL_MASK; | ||
865 | rate /= (clkdiv >> S5PC100_CLKDIV1_MPLL_SHIFT) + 1; | ||
866 | |||
867 | return rate; | ||
868 | } | ||
869 | |||
870 | static struct clk clk_dout_mpll = { | ||
871 | .name = "dout_mpll", | ||
872 | .id = -1, | ||
873 | .parent = &clk_mout_mpll.clk, | ||
874 | .get_rate = s5pc1xx_clk_doutmpll_get_rate, | ||
875 | }; | ||
876 | |||
877 | static unsigned long s5pc1xx_clk_doutmpll2_get_rate(struct clk *clk) | ||
878 | { | ||
879 | unsigned long rate = clk_get_rate(clk->parent); | ||
880 | unsigned long clkdiv; | ||
881 | |||
882 | printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); | ||
883 | |||
884 | clkdiv = __raw_readl(S5PC1XX_CLK_DIV1) & S5PC100_CLKDIV1_MPLL2_MASK; | ||
885 | rate /= (clkdiv >> S5PC100_CLKDIV1_MPLL2_SHIFT) + 1; | ||
886 | |||
887 | return rate; | ||
888 | } | ||
889 | |||
890 | struct clk clk_dout_mpll2 = { | ||
891 | .name = "dout_mpll2", | ||
892 | .id = -1, | ||
893 | .parent = &clk_mout_mpll.clk, | ||
894 | .get_rate = s5pc1xx_clk_doutmpll2_get_rate, | ||
895 | }; | ||
896 | |||
897 | static struct clk *clkset_uart_list[] = { | ||
898 | &clk_mout_epll.clk, | ||
899 | &clk_dout_mpll, | ||
900 | NULL, | ||
901 | NULL | ||
902 | }; | ||
903 | |||
904 | static struct clk_sources clkset_uart = { | ||
905 | .sources = clkset_uart_list, | ||
906 | .nr_sources = ARRAY_SIZE(clkset_uart_list), | ||
907 | }; | ||
908 | |||
909 | static inline struct clksrc_clk *to_clksrc(struct clk *clk) | ||
910 | { | ||
911 | return container_of(clk, struct clksrc_clk, clk); | ||
912 | } | ||
913 | |||
914 | static unsigned long s5pc1xx_getrate_clksrc(struct clk *clk) | ||
915 | { | ||
916 | struct clksrc_clk *sclk = to_clksrc(clk); | ||
917 | unsigned long rate = clk_get_rate(clk->parent); | ||
918 | u32 clkdiv = __raw_readl(sclk->reg_divider); | ||
919 | |||
920 | clkdiv >>= sclk->divider_shift; | ||
921 | clkdiv &= 0xf; | ||
922 | clkdiv++; | ||
923 | |||
924 | rate /= clkdiv; | ||
925 | return rate; | ||
926 | } | ||
927 | |||
928 | static int s5pc1xx_setrate_clksrc(struct clk *clk, unsigned long rate) | ||
929 | { | ||
930 | struct clksrc_clk *sclk = to_clksrc(clk); | ||
931 | void __iomem *reg = sclk->reg_divider; | ||
932 | unsigned int div; | ||
933 | u32 val; | ||
934 | |||
935 | rate = clk_round_rate(clk, rate); | ||
936 | div = clk_get_rate(clk->parent) / rate; | ||
937 | if (div > 16) | ||
938 | return -EINVAL; | ||
939 | |||
940 | val = __raw_readl(reg); | ||
941 | val &= ~(0xf << sclk->shift); | ||
942 | val |= (div - 1) << sclk->shift; | ||
943 | __raw_writel(val, reg); | ||
944 | |||
945 | return 0; | ||
946 | } | ||
947 | |||
948 | static int s5pc1xx_setparent_clksrc(struct clk *clk, struct clk *parent) | ||
949 | { | ||
950 | struct clksrc_clk *sclk = to_clksrc(clk); | ||
951 | struct clk_sources *srcs = sclk->sources; | ||
952 | u32 clksrc = __raw_readl(sclk->reg_source); | ||
953 | int src_nr = -1; | ||
954 | int ptr; | ||
955 | |||
956 | for (ptr = 0; ptr < srcs->nr_sources; ptr++) | ||
957 | if (srcs->sources[ptr] == parent) { | ||
958 | src_nr = ptr; | ||
959 | break; | ||
960 | } | ||
961 | |||
962 | if (src_nr >= 0) { | ||
963 | clksrc &= ~sclk->mask; | ||
964 | clksrc |= src_nr << sclk->shift; | ||
965 | |||
966 | __raw_writel(clksrc, sclk->reg_source); | ||
967 | return 0; | ||
968 | } | ||
969 | |||
970 | return -EINVAL; | ||
971 | } | ||
972 | |||
973 | static unsigned long s5pc1xx_roundrate_clksrc(struct clk *clk, | ||
974 | unsigned long rate) | ||
975 | { | ||
976 | unsigned long parent_rate = clk_get_rate(clk->parent); | ||
977 | int div; | ||
978 | |||
979 | if (rate > parent_rate) | ||
980 | rate = parent_rate; | ||
981 | else { | ||
982 | div = rate / parent_rate; | ||
983 | |||
984 | if (div == 0) | ||
985 | div = 1; | ||
986 | if (div > 16) | ||
987 | div = 16; | ||
988 | |||
989 | rate = parent_rate / div; | ||
990 | } | ||
991 | |||
992 | return rate; | ||
993 | } | ||
994 | |||
995 | static struct clksrc_clk clk_uart_uclk1 = { | ||
996 | .clk = { | ||
997 | .name = "uclk1", | ||
998 | .id = -1, | ||
999 | .ctrlbit = S5PC100_CLKGATE_SCLK0_UART, | ||
1000 | .enable = s5pc1xx_sclk0_ctrl, | ||
1001 | .set_parent = s5pc1xx_setparent_clksrc, | ||
1002 | .get_rate = s5pc1xx_getrate_clksrc, | ||
1003 | .set_rate = s5pc1xx_setrate_clksrc, | ||
1004 | .round_rate = s5pc1xx_roundrate_clksrc, | ||
1005 | }, | ||
1006 | .shift = S5PC100_CLKSRC1_UART_SHIFT, | ||
1007 | .mask = S5PC100_CLKSRC1_UART_MASK, | ||
1008 | .sources = &clkset_uart, | ||
1009 | .divider_shift = S5PC100_CLKDIV2_UART_SHIFT, | ||
1010 | .reg_divider = S5PC1XX_CLK_DIV2, | ||
1011 | .reg_source = S5PC1XX_CLK_SRC1, | ||
1012 | }; | ||
1013 | |||
1014 | /* Clock initialisation code */ | ||
1015 | |||
1016 | static struct clksrc_clk *init_parents[] = { | ||
1017 | &clk_mout_apll, | ||
1018 | &clk_mout_epll, | ||
1019 | &clk_mout_mpll, | ||
1020 | &clk_uart_uclk1, | ||
1021 | }; | ||
1022 | |||
1023 | static void __init_or_cpufreq s5pc1xx_set_clksrc(struct clksrc_clk *clk) | ||
1024 | { | ||
1025 | struct clk_sources *srcs = clk->sources; | ||
1026 | u32 clksrc = __raw_readl(clk->reg_source); | ||
1027 | |||
1028 | clksrc &= clk->mask; | ||
1029 | clksrc >>= clk->shift; | ||
1030 | |||
1031 | if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) { | ||
1032 | printk(KERN_ERR "%s: bad source %d\n", | ||
1033 | clk->clk.name, clksrc); | ||
1034 | return; | ||
1035 | } | ||
1036 | |||
1037 | clk->clk.parent = srcs->sources[clksrc]; | ||
1038 | |||
1039 | printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n", | ||
1040 | clk->clk.name, clk->clk.parent->name, clksrc, | ||
1041 | clk_get_rate(&clk->clk)); | ||
1042 | } | ||
1043 | |||
1044 | #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) | ||
1045 | |||
1046 | void __init_or_cpufreq s5pc100_setup_clocks(void) | ||
1047 | { | ||
1048 | struct clk *xtal_clk; | ||
1049 | unsigned long xtal; | ||
1050 | unsigned long armclk; | ||
1051 | unsigned long hclkd0; | ||
1052 | unsigned long hclk; | ||
1053 | unsigned long pclkd0; | ||
1054 | unsigned long pclk; | ||
1055 | unsigned long apll; | ||
1056 | unsigned long mpll; | ||
1057 | unsigned long hpll; | ||
1058 | unsigned long epll; | ||
1059 | unsigned int ptr; | ||
1060 | u32 clkdiv0, clkdiv1; | ||
1061 | |||
1062 | printk(KERN_DEBUG "%s: registering clocks\n", __func__); | ||
1063 | |||
1064 | clkdiv0 = __raw_readl(S5PC1XX_CLK_DIV0); | ||
1065 | clkdiv1 = __raw_readl(S5PC1XX_CLK_DIV1); | ||
1066 | |||
1067 | printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n", | ||
1068 | __func__, clkdiv0, clkdiv1); | ||
1069 | |||
1070 | xtal_clk = clk_get(NULL, "xtal"); | ||
1071 | BUG_ON(IS_ERR(xtal_clk)); | ||
1072 | |||
1073 | xtal = clk_get_rate(xtal_clk); | ||
1074 | clk_put(xtal_clk); | ||
1075 | |||
1076 | printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); | ||
1077 | |||
1078 | apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_APLL_CON)); | ||
1079 | mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_MPLL_CON)); | ||
1080 | epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_EPLL_CON)); | ||
1081 | hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_HPLL_CON)); | ||
1082 | |||
1083 | printk(KERN_INFO "S5PC100: PLL settings, A=%ld, M=%ld, E=%ld, H=%ld\n", | ||
1084 | apll, mpll, epll, hpll); | ||
1085 | |||
1086 | armclk = apll / GET_DIV(clkdiv0, S5PC1XX_CLKDIV0_APLL); | ||
1087 | armclk = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_ARM); | ||
1088 | hclkd0 = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_D0); | ||
1089 | pclkd0 = hclkd0 / GET_DIV(clkdiv0, S5PC100_CLKDIV0_PCLKD0); | ||
1090 | hclk = mpll / GET_DIV(clkdiv1, S5PC100_CLKDIV1_D1); | ||
1091 | pclk = hclk / GET_DIV(clkdiv1, S5PC100_CLKDIV1_PCLKD1); | ||
1092 | |||
1093 | printk(KERN_INFO "S5PC100: ARMCLK=%ld, HCLKD0=%ld, PCLKD0=%ld, HCLK=%ld, PCLK=%ld\n", | ||
1094 | armclk, hclkd0, pclkd0, hclk, pclk); | ||
1095 | |||
1096 | clk_fout_apll.rate = apll; | ||
1097 | clk_fout_mpll.rate = mpll; | ||
1098 | clk_fout_epll.rate = epll; | ||
1099 | clk_fout_apll.rate = apll; | ||
1100 | |||
1101 | clk_h.rate = hclk; | ||
1102 | clk_p.rate = pclk; | ||
1103 | |||
1104 | for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) | ||
1105 | s5pc1xx_set_clksrc(init_parents[ptr]); | ||
1106 | } | ||
1107 | |||
1108 | static struct clk *clks[] __initdata = { | ||
1109 | &clk_ext_xtal_mux, | ||
1110 | &clk_mout_epll.clk, | ||
1111 | &clk_fout_epll, | ||
1112 | &clk_mout_mpll.clk, | ||
1113 | &clk_dout_mpll, | ||
1114 | &clk_uart_uclk1.clk, | ||
1115 | &clk_ext, | ||
1116 | &clk_epll, | ||
1117 | &clk_27m, | ||
1118 | &clk_48m, | ||
1119 | &clk_54m, | ||
1120 | }; | ||
1121 | |||
1122 | void __init s5pc100_register_clocks(void) | ||
1123 | { | ||
1124 | struct clk *clkp; | ||
1125 | int ret; | ||
1126 | int ptr; | ||
1127 | |||
1128 | for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) { | ||
1129 | clkp = clks[ptr]; | ||
1130 | ret = s3c24xx_register_clock(clkp); | ||
1131 | if (ret < 0) { | ||
1132 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | ||
1133 | clkp->name, ret); | ||
1134 | } | ||
1135 | } | ||
1136 | |||
1137 | clk_mpll.parent = &clk_mout_mpll.clk; | ||
1138 | clk_epll.parent = &clk_mout_epll.clk; | ||
1139 | } | ||
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-init.c b/arch/arm/plat-s5pc1xx/s5pc100-init.c new file mode 100644 index 000000000000..c58710884ceb --- /dev/null +++ b/arch/arm/plat-s5pc1xx/s5pc100-init.c | |||
@@ -0,0 +1,27 @@ | |||
1 | /* linux/arch/arm/plat-s5pc1xx/s5pc100-init.c | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * S5PC100 - CPU initialisation (common with other S5PC1XX chips) | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/kernel.h> | ||
14 | #include <linux/types.h> | ||
15 | #include <linux/init.h> | ||
16 | |||
17 | #include <plat/cpu.h> | ||
18 | #include <plat/devs.h> | ||
19 | #include <plat/s5pc100.h> | ||
20 | |||
21 | /* uart registration process */ | ||
22 | |||
23 | void __init s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) | ||
24 | { | ||
25 | /* The driver name is s3c6400-uart to reuse s3c6400_serial_drv */ | ||
26 | s3c24xx_init_uartdevs("s3c6400-uart", s5pc1xx_uart_resources, cfg, no); | ||
27 | } | ||
diff --git a/arch/arm/plat-s5pc1xx/setup-i2c0.c b/arch/arm/plat-s5pc1xx/setup-i2c0.c new file mode 100644 index 000000000000..3d00c025fffb --- /dev/null +++ b/arch/arm/plat-s5pc1xx/setup-i2c0.c | |||
@@ -0,0 +1,25 @@ | |||
1 | /* linux/arch/arm/plat-s5pc1xx/setup-i2c0.c | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * Base S5PC1XX I2C bus 0 gpio configuration | ||
7 | * | ||
8 | * Based on plat-s3c64xx/setup-i2c0.c | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/types.h> | ||
17 | |||
18 | struct platform_device; /* don't need the contents */ | ||
19 | |||
20 | #include <plat/iic.h> | ||
21 | |||
22 | void s3c_i2c0_cfg_gpio(struct platform_device *dev) | ||
23 | { | ||
24 | /* Pin configuration would be needed */ | ||
25 | } | ||
diff --git a/arch/arm/plat-s5pc1xx/setup-i2c1.c b/arch/arm/plat-s5pc1xx/setup-i2c1.c new file mode 100644 index 000000000000..c8f3ca42f51d --- /dev/null +++ b/arch/arm/plat-s5pc1xx/setup-i2c1.c | |||
@@ -0,0 +1,25 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/setup-i2c1.c | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * Base S5PC1XX I2C bus 1 gpio configuration | ||
7 | * | ||
8 | * Based on plat-s3c64xx/setup-i2c1.c | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/types.h> | ||
17 | |||
18 | struct platform_device; /* don't need the contents */ | ||
19 | |||
20 | #include <plat/iic.h> | ||
21 | |||
22 | void s3c_i2c1_cfg_gpio(struct platform_device *dev) | ||
23 | { | ||
24 | /* Pin configuration would be needed */ | ||
25 | } | ||