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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-09-06 12:19:08 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-10-01 11:40:52 -0400
commitda0916539d20f257dfa46784357300e49d6bfd00 (patch)
treee581749819a4a7e5aea471c242a51773a360bd1d /arch/arm
parent1ad77a876da48331451698cc4172c90ab9b6372f (diff)
[ARM] Convert set_pte_ext implementions to macros
There are actually only four separate implementations of set_pte_ext. Use assembler macros to insert code for these into the proc-*.S files. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mm/proc-arm1020.S24
-rw-r--r--arch/arm/mm/proc-arm1020e.S24
-rw-r--r--arch/arm/mm/proc-arm1022.S24
-rw-r--r--arch/arm/mm/proc-arm1026.S24
-rw-r--r--arch/arm/mm/proc-arm6_7.S25
-rw-r--r--arch/arm/mm/proc-arm720.S23
-rw-r--r--arch/arm/mm/proc-arm920.S26
-rw-r--r--arch/arm/mm/proc-arm922.S24
-rw-r--r--arch/arm/mm/proc-arm925.S24
-rw-r--r--arch/arm/mm/proc-arm926.S24
-rw-r--r--arch/arm/mm/proc-feroceon.S19
-rw-r--r--arch/arm/mm/proc-macros.S144
-rw-r--r--arch/arm/mm/proc-sa110.S19
-rw-r--r--arch/arm/mm/proc-sa1100.S19
-rw-r--r--arch/arm/mm/proc-v6.S38
-rw-r--r--arch/arm/mm/proc-v7.S38
-rw-r--r--arch/arm/mm/proc-xsc3.S30
-rw-r--r--arch/arm/mm/proc-xscale.S30
18 files changed, 177 insertions, 402 deletions
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 5673f4d6113b..453f828f1fbb 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -399,29 +399,7 @@ ENTRY(cpu_arm1020_switch_mm)
399 .align 5 399 .align 5
400ENTRY(cpu_arm1020_set_pte_ext) 400ENTRY(cpu_arm1020_set_pte_ext)
401#ifdef CONFIG_MMU 401#ifdef CONFIG_MMU
402 str r1, [r0], #-2048 @ linux version 402 armv3_set_pte_ext
403
404 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
405
406 bic r2, r1, #PTE_SMALL_AP_MASK
407 bic r2, r2, #PTE_TYPE_MASK
408 orr r2, r2, #PTE_TYPE_SMALL
409
410 tst r1, #L_PTE_USER @ User?
411 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
412
413 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
414 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
415
416 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
417 movne r2, #0
418
419#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
420 eor r3, r1, #0x0a @ C & small page?
421 tst r3, #0x0b
422 biceq r2, r2, #4
423#endif
424 str r2, [r0] @ hardware version
425 mov r0, r0 403 mov r0, r0
426#ifndef CONFIG_CPU_DCACHE_DISABLE 404#ifndef CONFIG_CPU_DCACHE_DISABLE
427 mcr p15, 0, r0, c7, c10, 4 405 mcr p15, 0, r0, c7, c10, 4
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 4343fdb0e9e5..a226dd330c2d 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -383,29 +383,7 @@ ENTRY(cpu_arm1020e_switch_mm)
383 .align 5 383 .align 5
384ENTRY(cpu_arm1020e_set_pte_ext) 384ENTRY(cpu_arm1020e_set_pte_ext)
385#ifdef CONFIG_MMU 385#ifdef CONFIG_MMU
386 str r1, [r0], #-2048 @ linux version 386 armv3_set_pte_ext
387
388 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
389
390 bic r2, r1, #PTE_SMALL_AP_MASK
391 bic r2, r2, #PTE_TYPE_MASK
392 orr r2, r2, #PTE_TYPE_SMALL
393
394 tst r1, #L_PTE_USER @ User?
395 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
396
397 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
398 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
399
400 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
401 movne r2, #0
402
403#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
404 eor r3, r1, #0x0a @ C & small page?
405 tst r3, #0x0b
406 biceq r2, r2, #4
407#endif
408 str r2, [r0] @ hardware version
409 mov r0, r0 387 mov r0, r0
410#ifndef CONFIG_CPU_DCACHE_DISABLE 388#ifndef CONFIG_CPU_DCACHE_DISABLE
411 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 389 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 2a4ea1659e96..68db8c5a4e98 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -365,29 +365,7 @@ ENTRY(cpu_arm1022_switch_mm)
365 .align 5 365 .align 5
366ENTRY(cpu_arm1022_set_pte_ext) 366ENTRY(cpu_arm1022_set_pte_ext)
367#ifdef CONFIG_MMU 367#ifdef CONFIG_MMU
368 str r1, [r0], #-2048 @ linux version 368 armv3_set_pte_ext
369
370 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
371
372 bic r2, r1, #PTE_SMALL_AP_MASK
373 bic r2, r2, #PTE_TYPE_MASK
374 orr r2, r2, #PTE_TYPE_SMALL
375
376 tst r1, #L_PTE_USER @ User?
377 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
378
379 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
380 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
381
382 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
383 movne r2, #0
384
385#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
386 eor r3, r1, #0x0a @ C & small page?
387 tst r3, #0x0b
388 biceq r2, r2, #4
389#endif
390 str r2, [r0] @ hardware version
391 mov r0, r0 369 mov r0, r0
392#ifndef CONFIG_CPU_DCACHE_DISABLE 370#ifndef CONFIG_CPU_DCACHE_DISABLE
393 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 371 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 77a1babd421c..c02f303d3add 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -354,29 +354,7 @@ ENTRY(cpu_arm1026_switch_mm)
354 .align 5 354 .align 5
355ENTRY(cpu_arm1026_set_pte_ext) 355ENTRY(cpu_arm1026_set_pte_ext)
356#ifdef CONFIG_MMU 356#ifdef CONFIG_MMU
357 str r1, [r0], #-2048 @ linux version 357 armv3_set_pte_ext
358
359 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
360
361 bic r2, r1, #PTE_SMALL_AP_MASK
362 bic r2, r2, #PTE_TYPE_MASK
363 orr r2, r2, #PTE_TYPE_SMALL
364
365 tst r1, #L_PTE_USER @ User?
366 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
367
368 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
369 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
370
371 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
372 movne r2, #0
373
374#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
375 eor r3, r1, #0x0a @ C & small page?
376 tst r3, #0x0b
377 biceq r2, r2, #4
378#endif
379 str r2, [r0] @ hardware version
380 mov r0, r0 358 mov r0, r0
381#ifndef CONFIG_CPU_DCACHE_DISABLE 359#ifndef CONFIG_CPU_DCACHE_DISABLE
382 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 360 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index c371fc87776e..5e78c483e48a 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -20,6 +20,8 @@
20#include <asm/pgtable.h> 20#include <asm/pgtable.h>
21#include <asm/ptrace.h> 21#include <asm/ptrace.h>
22 22
23#include "proc-macros.S"
24
23ENTRY(cpu_arm6_dcache_clean_area) 25ENTRY(cpu_arm6_dcache_clean_area)
24ENTRY(cpu_arm7_dcache_clean_area) 26ENTRY(cpu_arm7_dcache_clean_area)
25 mov pc, lr 27 mov pc, lr
@@ -214,30 +216,13 @@ ENTRY(cpu_arm7_switch_mm)
214 * : r1 = value to set 216 * : r1 = value to set
215 * Purpose : Set a PTE and flush it out of any WB cache 217 * Purpose : Set a PTE and flush it out of any WB cache
216 */ 218 */
217 .align 5 219 .align 5
218ENTRY(cpu_arm6_set_pte_ext) 220ENTRY(cpu_arm6_set_pte_ext)
219ENTRY(cpu_arm7_set_pte_ext) 221ENTRY(cpu_arm7_set_pte_ext)
220#ifdef CONFIG_MMU 222#ifdef CONFIG_MMU
221 str r1, [r0], #-2048 @ linux version 223 armv3_set_pte_ext wc_disable=0
222
223 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
224
225 bic r2, r1, #PTE_SMALL_AP_MASK
226 bic r2, r2, #PTE_TYPE_MASK
227 orr r2, r2, #PTE_TYPE_SMALL
228
229 tst r1, #L_PTE_USER @ User?
230 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
231
232 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
233 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
234
235 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young
236 movne r2, #0
237
238 str r2, [r0] @ hardware version
239#endif /* CONFIG_MMU */ 224#endif /* CONFIG_MMU */
240 mov pc, lr 225 mov pc, lr
241 226
242/* 227/*
243 * Function: _arm6_7_reset 228 * Function: _arm6_7_reset
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index eda733d30455..6d3e0620be71 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -93,29 +93,12 @@ ENTRY(cpu_arm720_switch_mm)
93 * : r1 = value to set 93 * : r1 = value to set
94 * Purpose : Set a PTE and flush it out of any WB cache 94 * Purpose : Set a PTE and flush it out of any WB cache
95 */ 95 */
96 .align 5 96 .align 5
97ENTRY(cpu_arm720_set_pte_ext) 97ENTRY(cpu_arm720_set_pte_ext)
98#ifdef CONFIG_MMU 98#ifdef CONFIG_MMU
99 str r1, [r0], #-2048 @ linux version 99 armv3_set_pte_ext wc_disable=0
100
101 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
102
103 bic r2, r1, #PTE_SMALL_AP_MASK
104 bic r2, r2, #PTE_TYPE_MASK
105 orr r2, r2, #PTE_TYPE_SMALL
106
107 tst r1, #L_PTE_USER @ User?
108 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
109
110 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
111 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
112
113 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young
114 movne r2, #0
115
116 str r2, [r0] @ hardware version
117#endif 100#endif
118 mov pc, lr 101 mov pc, lr
119 102
120/* 103/*
121 * Function: arm720_reset 104 * Function: arm720_reset
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 28cdb060df45..260595bc912b 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -351,33 +351,11 @@ ENTRY(cpu_arm920_switch_mm)
351 .align 5 351 .align 5
352ENTRY(cpu_arm920_set_pte_ext) 352ENTRY(cpu_arm920_set_pte_ext)
353#ifdef CONFIG_MMU 353#ifdef CONFIG_MMU
354 str r1, [r0], #-2048 @ linux version 354 armv3_set_pte_ext
355
356 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
357
358 bic r2, r1, #PTE_SMALL_AP_MASK
359 bic r2, r2, #PTE_TYPE_MASK
360 orr r2, r2, #PTE_TYPE_SMALL
361
362 tst r1, #L_PTE_USER @ User?
363 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
364
365 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
366 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
367
368 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
369 movne r2, #0
370
371#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
372 eor r3, r2, #0x0a @ C & small page?
373 tst r3, #0x0b
374 biceq r2, r2, #4
375#endif
376 str r2, [r0] @ hardware version
377 mov r0, r0 355 mov r0, r0
378 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 356 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
379 mcr p15, 0, r0, c7, c10, 4 @ drain WB 357 mcr p15, 0, r0, c7, c10, 4 @ drain WB
380#endif /* CONFIG_MMU */ 358#endif
381 mov pc, lr 359 mov pc, lr
382 360
383 __INIT 361 __INIT
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 94ddcb4a4b76..0428f77b0d72 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -355,29 +355,7 @@ ENTRY(cpu_arm922_switch_mm)
355 .align 5 355 .align 5
356ENTRY(cpu_arm922_set_pte_ext) 356ENTRY(cpu_arm922_set_pte_ext)
357#ifdef CONFIG_MMU 357#ifdef CONFIG_MMU
358 str r1, [r0], #-2048 @ linux version 358 armv3_set_pte_ext
359
360 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
361
362 bic r2, r1, #PTE_SMALL_AP_MASK
363 bic r2, r2, #PTE_TYPE_MASK
364 orr r2, r2, #PTE_TYPE_SMALL
365
366 tst r1, #L_PTE_USER @ User?
367 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
368
369 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
370 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
371
372 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
373 movne r2, #0
374
375#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
376 eor r3, r2, #0x0a @ C & small page?
377 tst r3, #0x0b
378 biceq r2, r2, #4
379#endif
380 str r2, [r0] @ hardware version
381 mov r0, r0 359 mov r0, r0
382 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 360 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
383 mcr p15, 0, r0, c7, c10, 4 @ drain WB 361 mcr p15, 0, r0, c7, c10, 4 @ drain WB
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index d045812f3399..30194781fd01 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -398,29 +398,7 @@ ENTRY(cpu_arm925_switch_mm)
398 .align 5 398 .align 5
399ENTRY(cpu_arm925_set_pte_ext) 399ENTRY(cpu_arm925_set_pte_ext)
400#ifdef CONFIG_MMU 400#ifdef CONFIG_MMU
401 str r1, [r0], #-2048 @ linux version 401 armv3_set_pte_ext
402
403 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
404
405 bic r2, r1, #PTE_SMALL_AP_MASK
406 bic r2, r2, #PTE_TYPE_MASK
407 orr r2, r2, #PTE_TYPE_SMALL
408
409 tst r1, #L_PTE_USER @ User?
410 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
411
412 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
413 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
414
415 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
416 movne r2, #0
417
418#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
419 eor r3, r2, #0x0a @ C & small page?
420 tst r3, #0x0b
421 biceq r2, r2, #4
422#endif
423 str r2, [r0] @ hardware version
424 mov r0, r0 402 mov r0, r0
425#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 403#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
426 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 404 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 4cd33169a7c9..10e6ac257892 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -359,29 +359,7 @@ ENTRY(cpu_arm926_switch_mm)
359 .align 5 359 .align 5
360ENTRY(cpu_arm926_set_pte_ext) 360ENTRY(cpu_arm926_set_pte_ext)
361#ifdef CONFIG_MMU 361#ifdef CONFIG_MMU
362 str r1, [r0], #-2048 @ linux version 362 armv3_set_pte_ext
363
364 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
365
366 bic r2, r1, #PTE_SMALL_AP_MASK
367 bic r2, r2, #PTE_TYPE_MASK
368 orr r2, r2, #PTE_TYPE_SMALL
369
370 tst r1, #L_PTE_USER @ User?
371 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
372
373 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
374 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
375
376 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
377 movne r2, #0
378
379#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
380 eor r3, r2, #0x0a @ C & small page?
381 tst r3, #0x0b
382 biceq r2, r2, #4
383#endif
384 str r2, [r0] @ hardware version
385 mov r0, r0 363 mov r0, r0
386#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 364#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
387 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 365 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index f2e5884c513a..240366ee81e8 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -446,24 +446,7 @@ ENTRY(cpu_feroceon_switch_mm)
446 .align 5 446 .align 5
447ENTRY(cpu_feroceon_set_pte_ext) 447ENTRY(cpu_feroceon_set_pte_ext)
448#ifdef CONFIG_MMU 448#ifdef CONFIG_MMU
449 str r1, [r0], #-2048 @ linux version 449 armv3_set_pte_ext wc_disable=0
450
451 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
452
453 bic r2, r1, #PTE_SMALL_AP_MASK
454 bic r2, r2, #PTE_TYPE_MASK
455 orr r2, r2, #PTE_TYPE_SMALL
456
457 tst r1, #L_PTE_USER @ User?
458 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
459
460 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
461 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
462
463 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
464 movne r2, #0
465
466 str r2, [r0] @ hardware version
467 mov r0, r0 450 mov r0, r0
468 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 451 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
469#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH) 452#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index b13150052a76..d1be25313d7b 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -71,3 +71,147 @@
71 mov \reg, #16 @ size offset 71 mov \reg, #16 @ size offset
72 mov \reg, \reg, lsl \tmp @ actual cache line size 72 mov \reg, \reg, lsl \tmp @ actual cache line size
73 .endm 73 .endm
74
75
76/*
77 * Sanity check the PTE configuration for the code below - which makes
78 * certain assumptions about how these bits are layed out.
79 */
80#if L_PTE_SHARED != PTE_EXT_SHARED
81#error PTE shared bit mismatch
82#endif
83#if L_PTE_BUFFERABLE != PTE_BUFFERABLE
84#error PTE bufferable bit mismatch
85#endif
86#if L_PTE_CACHEABLE != PTE_CACHEABLE
87#error PTE cacheable bit mismatch
88#endif
89#if (L_PTE_EXEC+L_PTE_USER+L_PTE_WRITE+L_PTE_DIRTY+L_PTE_YOUNG+\
90 L_PTE_FILE+L_PTE_PRESENT) > L_PTE_SHARED
91#error Invalid Linux PTE bit settings
92#endif
93
94/*
95 * The ARMv6 and ARMv7 set_pte_ext translation function.
96 *
97 * Permission translation:
98 * YUWD APX AP1 AP0 SVC User
99 * 0xxx 0 0 0 no acc no acc
100 * 100x 1 0 1 r/o no acc
101 * 10x0 1 0 1 r/o no acc
102 * 1011 0 0 1 r/w no acc
103 * 110x 0 1 0 r/w r/o
104 * 11x0 0 1 0 r/w r/o
105 * 1111 0 1 1 r/w r/w
106 */
107 .macro armv6_set_pte_ext
108 str r1, [r0], #-2048 @ linux version
109
110 bic r3, r1, #0x000003f0
111 bic r3, r3, #PTE_TYPE_MASK
112 orr r3, r3, r2
113 orr r3, r3, #PTE_EXT_AP0 | 2
114
115 tst r1, #L_PTE_WRITE
116 tstne r1, #L_PTE_DIRTY
117 orreq r3, r3, #PTE_EXT_APX
118
119 tst r1, #L_PTE_USER
120 orrne r3, r3, #PTE_EXT_AP1
121 tstne r3, #PTE_EXT_APX
122 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
123
124 tst r1, #L_PTE_EXEC
125 orreq r3, r3, #PTE_EXT_XN
126
127 tst r1, #L_PTE_YOUNG
128 tstne r1, #L_PTE_PRESENT
129 moveq r3, #0
130
131 str r3, [r0]
132 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
133 .endm
134
135
136/*
137 * The ARMv3, ARMv4 and ARMv5 set_pte_ext translation function,
138 * covering most CPUs except Xscale and Xscale 3.
139 *
140 * Permission translation:
141 * YUWD AP SVC User
142 * 0xxx 0x00 no acc no acc
143 * 100x 0x00 r/o no acc
144 * 10x0 0x00 r/o no acc
145 * 1011 0x55 r/w no acc
146 * 110x 0xaa r/w r/o
147 * 11x0 0xaa r/w r/o
148 * 1111 0xff r/w r/w
149 */
150 .macro armv3_set_pte_ext wc_disable=1
151 str r1, [r0], #-2048 @ linux version
152
153 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
154
155 bic r2, r1, #PTE_SMALL_AP_MASK @ keep C, B bits
156 bic r2, r2, #PTE_TYPE_MASK
157 orr r2, r2, #PTE_TYPE_SMALL
158
159 tst r3, #L_PTE_USER @ user?
160 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
161
162 tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ write and dirty?
163 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
164
165 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young?
166 movne r2, #0
167
168 .if \wc_disable
169#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
170 tst r2, #PTE_CACHEABLE
171 bicne r2, r2, #PTE_BUFFERABLE
172#endif
173 .endif
174 str r2, [r0] @ hardware version
175 .endm
176
177
178/*
179 * Xscale set_pte_ext translation, split into two halves to cope
180 * with work-arounds. r3 must be preserved by code between these
181 * two macros.
182 *
183 * Permission translation:
184 * YUWD AP SVC User
185 * 0xxx 00 no acc no acc
186 * 100x 00 r/o no acc
187 * 10x0 00 r/o no acc
188 * 1011 01 r/w no acc
189 * 110x 10 r/w r/o
190 * 11x0 10 r/w r/o
191 * 1111 11 r/w r/w
192 */
193 .macro xscale_set_pte_ext_prologue
194 str r1, [r0], #-2048 @ linux version
195
196 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
197
198 bic r2, r1, #PTE_SMALL_AP_MASK @ keep C, B bits
199 orr r2, r2, #PTE_TYPE_EXT @ extended page
200
201 tst r3, #L_PTE_USER @ user?
202 orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
203
204 tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ write and dirty?
205 orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
206 @ combined with user -> user r/w
207 .endm
208
209 .macro xscale_set_pte_ext_epilogue
210 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young?
211 movne r2, #0 @ no -> fault
212
213 str r2, [r0] @ hardware version
214 mov ip, #0
215 mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
216 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
217 .endm
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index bbe10576c861..df3aebbb55d0 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -153,24 +153,7 @@ ENTRY(cpu_sa110_switch_mm)
153 .align 5 153 .align 5
154ENTRY(cpu_sa110_set_pte_ext) 154ENTRY(cpu_sa110_set_pte_ext)
155#ifdef CONFIG_MMU 155#ifdef CONFIG_MMU
156 str r1, [r0], #-2048 @ linux version 156 armv3_set_pte_ext wc_disable=0
157
158 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
159
160 bic r2, r1, #PTE_SMALL_AP_MASK
161 bic r2, r2, #PTE_TYPE_MASK
162 orr r2, r2, #PTE_TYPE_SMALL
163
164 tst r1, #L_PTE_USER @ User?
165 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
166
167 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
168 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
169
170 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
171 movne r2, #0
172
173 str r2, [r0] @ hardware version
174 mov r0, r0 157 mov r0, r0
175 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 158 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
176 mcr p15, 0, r0, c7, c10, 4 @ drain WB 159 mcr p15, 0, r0, c7, c10, 4 @ drain WB
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 871ba018252e..8e85e7cbc82f 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -166,24 +166,7 @@ ENTRY(cpu_sa1100_switch_mm)
166 .align 5 166 .align 5
167ENTRY(cpu_sa1100_set_pte_ext) 167ENTRY(cpu_sa1100_set_pte_ext)
168#ifdef CONFIG_MMU 168#ifdef CONFIG_MMU
169 str r1, [r0], #-2048 @ linux version 169 armv3_set_pte_ext wc_disable=0
170
171 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
172
173 bic r2, r1, #PTE_SMALL_AP_MASK
174 bic r2, r2, #PTE_TYPE_MASK
175 orr r2, r2, #PTE_TYPE_SMALL
176
177 tst r1, #L_PTE_USER @ User?
178 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
179
180 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
181 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
182
183 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
184 movne r2, #0
185
186 str r2, [r0] @ hardware version
187 mov r0, r0 170 mov r0, r0
188 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 171 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
189 mcr p15, 0, r0, c7, c10, 4 @ drain WB 172 mcr p15, 0, r0, c7, c10, 4 @ drain WB
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 5702ec58b2a2..70c623534021 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -114,46 +114,10 @@ ENTRY(cpu_v6_switch_mm)
114 * (hardware version is stored at -1024 bytes) 114 * (hardware version is stored at -1024 bytes)
115 * - pte - PTE value to store 115 * - pte - PTE value to store
116 * - ext - value for extended PTE bits 116 * - ext - value for extended PTE bits
117 *
118 * Permissions:
119 * YUWD APX AP1 AP0 SVC User
120 * 0xxx 0 0 0 no acc no acc
121 * 100x 1 0 1 r/o no acc
122 * 10x0 1 0 1 r/o no acc
123 * 1011 0 0 1 r/w no acc
124 * 110x 0 1 0 r/w r/o
125 * 11x0 0 1 0 r/w r/o
126 * 1111 0 1 1 r/w r/w
127 */ 117 */
128ENTRY(cpu_v6_set_pte_ext) 118ENTRY(cpu_v6_set_pte_ext)
129#ifdef CONFIG_MMU 119#ifdef CONFIG_MMU
130 str r1, [r0], #-2048 @ linux version 120 armv6_set_pte_ext
131
132 bic r3, r1, #0x000003f0
133 bic r3, r3, #0x00000003
134 orr r3, r3, r2
135 orr r3, r3, #PTE_EXT_AP0 | 2
136
137 tst r1, #L_PTE_WRITE
138 tstne r1, #L_PTE_DIRTY
139 orreq r3, r3, #PTE_EXT_APX
140
141 tst r1, #L_PTE_USER
142 orrne r3, r3, #PTE_EXT_AP1
143 tstne r3, #PTE_EXT_APX
144 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
145
146 tst r1, #L_PTE_YOUNG
147 biceq r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK
148
149 tst r1, #L_PTE_EXEC
150 orreq r3, r3, #PTE_EXT_XN
151
152 tst r1, #L_PTE_PRESENT
153 moveq r3, #0
154
155 str r3, [r0]
156 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
157#endif 121#endif
158 mov pc, lr 122 mov pc, lr
159 123
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index b49f9a4c82c8..172e2eeb6ddb 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -99,46 +99,10 @@ ENTRY(cpu_v7_switch_mm)
99 * (hardware version is stored at -1024 bytes) 99 * (hardware version is stored at -1024 bytes)
100 * - pte - PTE value to store 100 * - pte - PTE value to store
101 * - ext - value for extended PTE bits 101 * - ext - value for extended PTE bits
102 *
103 * Permissions:
104 * YUWD APX AP1 AP0 SVC User
105 * 0xxx 0 0 0 no acc no acc
106 * 100x 1 0 1 r/o no acc
107 * 10x0 1 0 1 r/o no acc
108 * 1011 0 0 1 r/w no acc
109 * 110x 0 1 0 r/w r/o
110 * 11x0 0 1 0 r/w r/o
111 * 1111 0 1 1 r/w r/w
112 */ 102 */
113ENTRY(cpu_v7_set_pte_ext) 103ENTRY(cpu_v7_set_pte_ext)
114#ifdef CONFIG_MMU 104#ifdef CONFIG_MMU
115 str r1, [r0], #-2048 @ linux version 105 armv6_set_pte_ext
116
117 bic r3, r1, #0x000003f0
118 bic r3, r3, #0x00000003
119 orr r3, r3, r2
120 orr r3, r3, #PTE_EXT_AP0 | 2
121
122 tst r1, #L_PTE_WRITE
123 tstne r1, #L_PTE_DIRTY
124 orreq r3, r3, #PTE_EXT_APX
125
126 tst r1, #L_PTE_USER
127 orrne r3, r3, #PTE_EXT_AP1
128 tstne r3, #PTE_EXT_APX
129 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
130
131 tst r1, #L_PTE_YOUNG
132 biceq r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK
133
134 tst r1, #L_PTE_EXEC
135 orreq r3, r3, #PTE_EXT_XN
136
137 tst r1, #L_PTE_PRESENT
138 moveq r3, #0
139
140 str r3, [r0]
141 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
142#endif 106#endif
143 mov pc, lr 107 mov pc, lr
144 108
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 7bd9e7197f60..ad1ce5a89221 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -349,34 +349,16 @@ ENTRY(cpu_xsc3_switch_mm)
349 */ 349 */
350 .align 5 350 .align 5
351ENTRY(cpu_xsc3_set_pte_ext) 351ENTRY(cpu_xsc3_set_pte_ext)
352 str r1, [r0], #-2048 @ linux version 352 xscale_set_pte_ext_prologue
353
354 bic r2, r1, #0xff0 @ keep C, B bits
355 orr r2, r2, #PTE_TYPE_EXT @ extended page
356 tst r1, #L_PTE_SHARED @ shared?
357 orrne r2, r2, #0x200
358
359 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
360
361 tst r3, #L_PTE_USER @ user?
362 orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
363
364 tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ write and dirty?
365 orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
366 @ combined with user -> user r/w
367 353
368 @ If it's cacheable, it needs to be in L2 also. 354 @ If it's cacheable, it needs to be in L2 also.
369 eor ip, r1, #L_PTE_CACHEABLE 355 tst r1, #L_PTE_CACHEABLE
370 tst ip, #L_PTE_CACHEABLE 356 orrne r2, r2, #PTE_EXT_TEX(0x5)
371 orreq r2, r2, #PTE_EXT_TEX(0x5)
372 357
373 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young? 358 tst r1, #L_PTE_SHARED @ shared?
374 movne r2, #0 @ no -> fault 359 orrne r2, r2, #0x200
375 360
376 str r2, [r0] @ hardware version 361 xscale_set_pte_ext_epilogue
377 mov ip, #0
378 mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
379 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
380 mov pc, lr 362 mov pc, lr
381 363
382 .ltorg 364 .ltorg
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 2dd85273976f..8d7512f9cba7 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -433,20 +433,7 @@ ENTRY(cpu_xscale_switch_mm)
433 */ 433 */
434 .align 5 434 .align 5
435ENTRY(cpu_xscale_set_pte_ext) 435ENTRY(cpu_xscale_set_pte_ext)
436 str r1, [r0], #-2048 @ linux version 436 xscale_set_pte_ext_prologue
437
438 bic r2, r1, #0xff0
439 orr r2, r2, #PTE_TYPE_EXT @ extended page
440
441 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
442
443 tst r3, #L_PTE_USER @ User?
444 orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
445
446 tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
447 orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
448 @ combined with user -> user r/w
449
450 @ 437 @
451 @ Handle the X bit. We want to set this bit for the minicache 438 @ Handle the X bit. We want to set this bit for the minicache
452 @ (U = E = B = W = 0, C = 1) or when write allocate is enabled, 439 @ (U = E = B = W = 0, C = 1) or when write allocate is enabled,
@@ -456,11 +443,10 @@ ENTRY(cpu_xscale_set_pte_ext)
456 @ 443 @
457 @ X = (C & ~W & ~B) | (C & W & B & write_allocate) 444 @ X = (C & ~W & ~B) | (C & W & B & write_allocate)
458 @ 445 @
459 eor ip, r1, #L_PTE_CACHEABLE 446 and ip, r1, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
460 tst ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE 447 teq ip, #L_PTE_CACHEABLE
461#if PTE_CACHE_WRITE_ALLOCATE 448#if PTE_CACHE_WRITE_ALLOCATE
462 eorne ip, r1, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE 449 teqne ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
463 tstne ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
464#endif 450#endif
465 orreq r2, r2, #PTE_EXT_TEX(1) 451 orreq r2, r2, #PTE_EXT_TEX(1)
466 452
@@ -474,13 +460,7 @@ ENTRY(cpu_xscale_set_pte_ext)
474 teq ip, #L_PTE_USER | L_PTE_CACHEABLE 460 teq ip, #L_PTE_USER | L_PTE_CACHEABLE
475 biceq r2, r2, #PTE_BUFFERABLE 461 biceq r2, r2, #PTE_BUFFERABLE
476 462
477 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young? 463 xscale_set_pte_ext_epilogue
478 movne r2, #0 @ no -> fault
479
480 str r2, [r0] @ hardware version
481 mov ip, #0
482 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
483 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
484 mov pc, lr 464 mov pc, lr
485 465
486 466
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-07 08:36:08 -0500