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authorPaul Walmsley <paul@pwsan.com>2010-02-23 00:09:26 -0500
committerPaul Walmsley <paul@pwsan.com>2010-02-24 14:29:43 -0500
commit51c19541624f5588bccb9d4fb3ae518c68c8082e (patch)
tree60f7b3df59806eea7ff7bbf691bb69f8791d5cc1 /arch/arm
parent8c34974ab0ecbbcdabd343f8cd0013cd2d2b0fa8 (diff)
OMAP clock: drop RATE_FIXED clock flag
The RATE_FIXED clock flag is pointless. In the OMAP1 clock code, it simply causes the omap1_clk_round_rate() function to return the current rate of the clock. omap1_clk_round_rate(), however, should never be called for a fixed-rate clock, since none of these clocks have a .round_rate function pointer set in their struct clk records. Similarly, in the OMAP2+ clock code, the RATE_FIXED flag just causes the clock code to emit a warning if the OMAP clock maintainer was foolish enough to add a .round_rate function pointer to a fixed-rate clock. "Doctor, it hurts when I pretend that a fixed-rate clock is rate-changeable." "Then don't pretend that a fixed-rate clock is rate-changeable." It has no functional value. This patch drops the RATE_FIXED clock flag, removing it from all clocks that are so marked. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Richard Woodruff <r-woodruff2@ti.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-omap1/clock.c5
-rw-r--r--arch/arm/mach-omap1/clock_data.c25
-rw-r--r--arch/arm/mach-omap2/clkt_clksel.c4
-rw-r--r--arch/arm/mach-omap2/clock2420_data.c7
-rw-r--r--arch/arm/mach-omap2/clock2430_data.c7
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c11
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h13
7 files changed, 20 insertions, 52 deletions
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 3e052f6532b1..0ba044d80a41 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/arch/arm/mach-omap1/clock.c 2 * linux/arch/arm/mach-omap1/clock.c
3 * 3 *
4 * Copyright (C) 2004 - 2005, 2009 Nokia corporation 4 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * 6 *
7 * Modified to use omap shared clock framework by 7 * Modified to use omap shared clock framework by
@@ -571,9 +571,6 @@ const struct clkops clkops_uart = {
571 571
572long omap1_clk_round_rate(struct clk *clk, unsigned long rate) 572long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
573{ 573{
574 if (clk->flags & RATE_FIXED)
575 return clk->rate;
576
577 if (clk->round_rate != NULL) 574 if (clk->round_rate != NULL)
578 return clk->round_rate(clk, rate); 575 return clk->round_rate(clk, rate);
579 576
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index cea91cdf624d..8b1d14d1e38e 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/arch/arm/mach-omap1/clock_data.c 2 * linux/arch/arm/mach-omap1/clock_data.c
3 * 3 *
4 * Copyright (C) 2004 - 2005, 2009 Nokia corporation 4 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc 6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
7 * 7 *
@@ -31,7 +31,6 @@
31static struct clk dummy_ck = { 31static struct clk dummy_ck = {
32 .name = "dummy", 32 .name = "dummy",
33 .ops = &clkops_dummy, 33 .ops = &clkops_dummy,
34 .flags = RATE_FIXED,
35}; 34};
36 35
37static struct clk ck_ref = { 36static struct clk ck_ref = {
@@ -389,8 +388,7 @@ static struct uart_clk uart1_16xx = {
389 /* Direct from ULPD, no real parent */ 388 /* Direct from ULPD, no real parent */
390 .parent = &armper_ck.clk, 389 .parent = &armper_ck.clk,
391 .rate = 48000000, 390 .rate = 48000000,
392 .flags = RATE_FIXED | ENABLE_REG_32BIT | 391 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
393 CLOCK_NO_IDLE_PARENT,
394 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), 392 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
395 .enable_bit = 29, 393 .enable_bit = 29,
396 }, 394 },
@@ -430,8 +428,7 @@ static struct uart_clk uart3_16xx = {
430 /* Direct from ULPD, no real parent */ 428 /* Direct from ULPD, no real parent */
431 .parent = &armper_ck.clk, 429 .parent = &armper_ck.clk,
432 .rate = 48000000, 430 .rate = 48000000,
433 .flags = RATE_FIXED | ENABLE_REG_32BIT | 431 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
434 CLOCK_NO_IDLE_PARENT,
435 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), 432 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
436 .enable_bit = 31, 433 .enable_bit = 31,
437 }, 434 },
@@ -443,7 +440,7 @@ static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
443 .ops = &clkops_generic, 440 .ops = &clkops_generic,
444 /* Direct from ULPD, no parent */ 441 /* Direct from ULPD, no parent */
445 .rate = 6000000, 442 .rate = 6000000,
446 .flags = RATE_FIXED | ENABLE_REG_32BIT, 443 .flags = ENABLE_REG_32BIT,
447 .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), 444 .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
448 .enable_bit = USB_MCLK_EN_BIT, 445 .enable_bit = USB_MCLK_EN_BIT,
449}; 446};
@@ -453,7 +450,7 @@ static struct clk usb_hhc_ck1510 = {
453 .ops = &clkops_generic, 450 .ops = &clkops_generic,
454 /* Direct from ULPD, no parent */ 451 /* Direct from ULPD, no parent */
455 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ 452 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
456 .flags = RATE_FIXED | ENABLE_REG_32BIT, 453 .flags = ENABLE_REG_32BIT,
457 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), 454 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
458 .enable_bit = USB_HOST_HHC_UHOST_EN, 455 .enable_bit = USB_HOST_HHC_UHOST_EN,
459}; 456};
@@ -464,7 +461,7 @@ static struct clk usb_hhc_ck16xx = {
464 /* Direct from ULPD, no parent */ 461 /* Direct from ULPD, no parent */
465 .rate = 48000000, 462 .rate = 48000000,
466 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ 463 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
467 .flags = RATE_FIXED | ENABLE_REG_32BIT, 464 .flags = ENABLE_REG_32BIT,
468 .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ 465 .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
469 .enable_bit = 8 /* UHOST_EN */, 466 .enable_bit = 8 /* UHOST_EN */,
470}; 467};
@@ -474,7 +471,6 @@ static struct clk usb_dc_ck = {
474 .ops = &clkops_generic, 471 .ops = &clkops_generic,
475 /* Direct from ULPD, no parent */ 472 /* Direct from ULPD, no parent */
476 .rate = 48000000, 473 .rate = 48000000,
477 .flags = RATE_FIXED,
478 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), 474 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
479 .enable_bit = 4, 475 .enable_bit = 4,
480}; 476};
@@ -484,7 +480,6 @@ static struct clk usb_dc_ck7xx = {
484 .ops = &clkops_generic, 480 .ops = &clkops_generic,
485 /* Direct from ULPD, no parent */ 481 /* Direct from ULPD, no parent */
486 .rate = 48000000, 482 .rate = 48000000,
487 .flags = RATE_FIXED,
488 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), 483 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
489 .enable_bit = 8, 484 .enable_bit = 8,
490}; 485};
@@ -494,7 +489,6 @@ static struct clk mclk_1510 = {
494 .ops = &clkops_generic, 489 .ops = &clkops_generic,
495 /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 490 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
496 .rate = 12000000, 491 .rate = 12000000,
497 .flags = RATE_FIXED,
498 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), 492 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
499 .enable_bit = 6, 493 .enable_bit = 6,
500}; 494};
@@ -515,7 +509,6 @@ static struct clk bclk_1510 = {
515 .ops = &clkops_generic, 509 .ops = &clkops_generic,
516 /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 510 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
517 .rate = 12000000, 511 .rate = 12000000,
518 .flags = RATE_FIXED,
519}; 512};
520 513
521static struct clk bclk_16xx = { 514static struct clk bclk_16xx = {
@@ -535,7 +528,7 @@ static struct clk mmc1_ck = {
535 /* Functional clock is direct from ULPD, interface clock is ARMPER */ 528 /* Functional clock is direct from ULPD, interface clock is ARMPER */
536 .parent = &armper_ck.clk, 529 .parent = &armper_ck.clk,
537 .rate = 48000000, 530 .rate = 48000000,
538 .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 531 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
539 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), 532 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
540 .enable_bit = 23, 533 .enable_bit = 23,
541}; 534};
@@ -546,7 +539,7 @@ static struct clk mmc2_ck = {
546 /* Functional clock is direct from ULPD, interface clock is ARMPER */ 539 /* Functional clock is direct from ULPD, interface clock is ARMPER */
547 .parent = &armper_ck.clk, 540 .parent = &armper_ck.clk,
548 .rate = 48000000, 541 .rate = 48000000,
549 .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 542 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
550 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), 543 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
551 .enable_bit = 20, 544 .enable_bit = 20,
552}; 545};
@@ -557,7 +550,7 @@ static struct clk mmc3_ck = {
557 /* Functional clock is direct from ULPD, interface clock is ARMPER */ 550 /* Functional clock is direct from ULPD, interface clock is ARMPER */
558 .parent = &armper_ck.clk, 551 .parent = &armper_ck.clk,
559 .rate = 48000000, 552 .rate = 48000000,
560 .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 553 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
561 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), 554 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
562 .enable_bit = 12, 555 .enable_bit = 12,
563}; 556};
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index ade19f6369df..e50812dd03fd 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -258,10 +258,6 @@ long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
258 if (clk->round_rate) 258 if (clk->round_rate)
259 return clk->round_rate(clk, rate); 259 return clk->round_rate(clk, rate);
260 260
261 if (clk->flags & RATE_FIXED)
262 printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
263 "on fixed-rate clock %s\n", clk->name);
264
265 return clk->rate; 261 return clk->rate;
266} 262}
267 263
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index d5913f01e5d6..f12af95ead45 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -55,7 +55,6 @@ static struct clk func_32k_ck = {
55 .name = "func_32k_ck", 55 .name = "func_32k_ck",
56 .ops = &clkops_null, 56 .ops = &clkops_null,
57 .rate = 32000, 57 .rate = 32000,
58 .flags = RATE_FIXED,
59 .clkdm_name = "wkup_clkdm", 58 .clkdm_name = "wkup_clkdm",
60}; 59};
61 60
@@ -63,7 +62,6 @@ static struct clk secure_32k_ck = {
63 .name = "secure_32k_ck", 62 .name = "secure_32k_ck",
64 .ops = &clkops_null, 63 .ops = &clkops_null,
65 .rate = 32768, 64 .rate = 32768,
66 .flags = RATE_FIXED,
67 .clkdm_name = "wkup_clkdm", 65 .clkdm_name = "wkup_clkdm",
68}; 66};
69 67
@@ -88,7 +86,6 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
88 .name = "alt_ck", 86 .name = "alt_ck",
89 .ops = &clkops_null, 87 .ops = &clkops_null,
90 .rate = 54000000, 88 .rate = 54000000,
91 .flags = RATE_FIXED,
92 .clkdm_name = "wkup_clkdm", 89 .clkdm_name = "wkup_clkdm",
93}; 90};
94 91
@@ -134,7 +131,7 @@ static struct clk apll96_ck = {
134 .ops = &clkops_apll96, 131 .ops = &clkops_apll96,
135 .parent = &sys_ck, 132 .parent = &sys_ck,
136 .rate = 96000000, 133 .rate = 96000000,
137 .flags = RATE_FIXED | ENABLE_ON_INIT, 134 .flags = ENABLE_ON_INIT,
138 .clkdm_name = "wkup_clkdm", 135 .clkdm_name = "wkup_clkdm",
139 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 136 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
140 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, 137 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
@@ -145,7 +142,7 @@ static struct clk apll54_ck = {
145 .ops = &clkops_apll54, 142 .ops = &clkops_apll54,
146 .parent = &sys_ck, 143 .parent = &sys_ck,
147 .rate = 54000000, 144 .rate = 54000000,
148 .flags = RATE_FIXED | ENABLE_ON_INIT, 145 .flags = ENABLE_ON_INIT,
149 .clkdm_name = "wkup_clkdm", 146 .clkdm_name = "wkup_clkdm",
150 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 147 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
151 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, 148 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index b3895840dc41..0438b6e4f51a 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -55,7 +55,6 @@ static struct clk func_32k_ck = {
55 .name = "func_32k_ck", 55 .name = "func_32k_ck",
56 .ops = &clkops_null, 56 .ops = &clkops_null,
57 .rate = 32000, 57 .rate = 32000,
58 .flags = RATE_FIXED,
59 .clkdm_name = "wkup_clkdm", 58 .clkdm_name = "wkup_clkdm",
60}; 59};
61 60
@@ -63,7 +62,6 @@ static struct clk secure_32k_ck = {
63 .name = "secure_32k_ck", 62 .name = "secure_32k_ck",
64 .ops = &clkops_null, 63 .ops = &clkops_null,
65 .rate = 32768, 64 .rate = 32768,
66 .flags = RATE_FIXED,
67 .clkdm_name = "wkup_clkdm", 65 .clkdm_name = "wkup_clkdm",
68}; 66};
69 67
@@ -88,7 +86,6 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
88 .name = "alt_ck", 86 .name = "alt_ck",
89 .ops = &clkops_null, 87 .ops = &clkops_null,
90 .rate = 54000000, 88 .rate = 54000000,
91 .flags = RATE_FIXED,
92 .clkdm_name = "wkup_clkdm", 89 .clkdm_name = "wkup_clkdm",
93}; 90};
94 91
@@ -134,7 +131,7 @@ static struct clk apll96_ck = {
134 .ops = &clkops_apll96, 131 .ops = &clkops_apll96,
135 .parent = &sys_ck, 132 .parent = &sys_ck,
136 .rate = 96000000, 133 .rate = 96000000,
137 .flags = RATE_FIXED | ENABLE_ON_INIT, 134 .flags = ENABLE_ON_INIT,
138 .clkdm_name = "wkup_clkdm", 135 .clkdm_name = "wkup_clkdm",
139 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 136 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
140 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, 137 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
@@ -145,7 +142,7 @@ static struct clk apll54_ck = {
145 .ops = &clkops_apll54, 142 .ops = &clkops_apll54,
146 .parent = &sys_ck, 143 .parent = &sys_ck,
147 .rate = 54000000, 144 .rate = 54000000,
148 .flags = RATE_FIXED | ENABLE_ON_INIT, 145 .flags = ENABLE_ON_INIT,
149 .clkdm_name = "wkup_clkdm", 146 .clkdm_name = "wkup_clkdm",
150 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 147 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
151 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, 148 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index f23790297003..fd832300be32 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -64,14 +64,12 @@ static struct clk omap_32k_fck = {
64 .name = "omap_32k_fck", 64 .name = "omap_32k_fck",
65 .ops = &clkops_null, 65 .ops = &clkops_null,
66 .rate = 32768, 66 .rate = 32768,
67 .flags = RATE_FIXED,
68}; 67};
69 68
70static struct clk secure_32k_fck = { 69static struct clk secure_32k_fck = {
71 .name = "secure_32k_fck", 70 .name = "secure_32k_fck",
72 .ops = &clkops_null, 71 .ops = &clkops_null,
73 .rate = 32768, 72 .rate = 32768,
74 .flags = RATE_FIXED,
75}; 73};
76 74
77/* Virtual source clocks for osc_sys_ck */ 75/* Virtual source clocks for osc_sys_ck */
@@ -79,42 +77,36 @@ static struct clk virt_12m_ck = {
79 .name = "virt_12m_ck", 77 .name = "virt_12m_ck",
80 .ops = &clkops_null, 78 .ops = &clkops_null,
81 .rate = 12000000, 79 .rate = 12000000,
82 .flags = RATE_FIXED,
83}; 80};
84 81
85static struct clk virt_13m_ck = { 82static struct clk virt_13m_ck = {
86 .name = "virt_13m_ck", 83 .name = "virt_13m_ck",
87 .ops = &clkops_null, 84 .ops = &clkops_null,
88 .rate = 13000000, 85 .rate = 13000000,
89 .flags = RATE_FIXED,
90}; 86};
91 87
92static struct clk virt_16_8m_ck = { 88static struct clk virt_16_8m_ck = {
93 .name = "virt_16_8m_ck", 89 .name = "virt_16_8m_ck",
94 .ops = &clkops_null, 90 .ops = &clkops_null,
95 .rate = 16800000, 91 .rate = 16800000,
96 .flags = RATE_FIXED,
97}; 92};
98 93
99static struct clk virt_19_2m_ck = { 94static struct clk virt_19_2m_ck = {
100 .name = "virt_19_2m_ck", 95 .name = "virt_19_2m_ck",
101 .ops = &clkops_null, 96 .ops = &clkops_null,
102 .rate = 19200000, 97 .rate = 19200000,
103 .flags = RATE_FIXED,
104}; 98};
105 99
106static struct clk virt_26m_ck = { 100static struct clk virt_26m_ck = {
107 .name = "virt_26m_ck", 101 .name = "virt_26m_ck",
108 .ops = &clkops_null, 102 .ops = &clkops_null,
109 .rate = 26000000, 103 .rate = 26000000,
110 .flags = RATE_FIXED,
111}; 104};
112 105
113static struct clk virt_38_4m_ck = { 106static struct clk virt_38_4m_ck = {
114 .name = "virt_38_4m_ck", 107 .name = "virt_38_4m_ck",
115 .ops = &clkops_null, 108 .ops = &clkops_null,
116 .rate = 38400000, 109 .rate = 38400000,
117 .flags = RATE_FIXED,
118}; 110};
119 111
120static const struct clksel_rate osc_sys_12m_rates[] = { 112static const struct clksel_rate osc_sys_12m_rates[] = {
@@ -167,7 +159,6 @@ static struct clk osc_sys_ck = {
167 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, 159 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
168 .clksel = osc_sys_clksel, 160 .clksel = osc_sys_clksel,
169 /* REVISIT: deal with autoextclkmode? */ 161 /* REVISIT: deal with autoextclkmode? */
170 .flags = RATE_FIXED,
171 .recalc = &omap2_clksel_recalc, 162 .recalc = &omap2_clksel_recalc,
172}; 163};
173 164
@@ -3168,7 +3159,6 @@ static struct clk emac_ick = {
3168static struct clk rmii_ck = { 3159static struct clk rmii_ck = {
3169 .name = "rmii_ck", 3160 .name = "rmii_ck",
3170 .ops = &clkops_null, 3161 .ops = &clkops_null,
3171 .flags = RATE_FIXED,
3172 .rate = 50000000, 3162 .rate = 50000000,
3173}; 3163};
3174 3164
@@ -3224,7 +3214,6 @@ static struct clk vpfe_ick = {
3224static struct clk pclk_ck = { 3214static struct clk pclk_ck = {
3225 .name = "pclk_ck", 3215 .name = "pclk_ck",
3226 .ops = &clkops_null, 3216 .ops = &clkops_null,
3227 .flags = RATE_FIXED,
3228 .rate = 27000000, 3217 .rate = 27000000,
3229}; 3218};
3230 3219
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 91aa2c48cdde..47de911b0a15 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -186,13 +186,12 @@ extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
186extern const struct clkops clkops_null; 186extern const struct clkops clkops_null;
187 187
188/* Clock flags */ 188/* Clock flags */
189#define RATE_FIXED (1 << 0) /* Fixed clock rate */ 189#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
190#define ENABLE_REG_32BIT (1 << 1) /* Use 32-bit access */ 190#define CLOCK_IDLE_CONTROL (1 << 1)
191#define CLOCK_IDLE_CONTROL (1 << 2) 191#define CLOCK_NO_IDLE_PARENT (1 << 2)
192#define CLOCK_NO_IDLE_PARENT (1 << 3) 192#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
193#define ENABLE_ON_INIT (1 << 4) /* Enable upon framework init */ 193#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
194#define INVERT_ENABLE (1 << 5) /* 0 enables, 1 disables */ 194#define ALWAYS_ENABLED (1 << 5)
195#define ALWAYS_ENABLED (1 << 6)
196 195
197/* Clksel_rate flags */ 196/* Clksel_rate flags */
198#define DEFAULT_RATE (1 << 0) 197#define DEFAULT_RATE (1 << 0)