diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2009-01-02 07:18:53 -0500 |
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committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-01-02 07:18:53 -0500 |
commit | bc6447b8e4fdb3306ee6381df9650a1a8aa57c5b (patch) | |
tree | 0ba38bb6883a561bcd2febbc8e5090fc559d2de6 /arch/arm | |
parent | 5369bea7d7db1d95f63907f3470e23d32930be98 (diff) |
[ARM] dma: make DMA_MODE_xxx reflect ISA DMA settings
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/include/asm/dma.h | 13 | ||||
-rw-r--r-- | arch/arm/kernel/dma-isa.c | 13 |
2 files changed, 9 insertions, 17 deletions
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h index c5557a650d1d..59f59c6c79f7 100644 --- a/arch/arm/include/asm/dma.h +++ b/arch/arm/include/asm/dma.h | |||
@@ -26,12 +26,15 @@ | |||
26 | */ | 26 | */ |
27 | typedef unsigned int dmamode_t; | 27 | typedef unsigned int dmamode_t; |
28 | 28 | ||
29 | #define DMA_MODE_MASK 3 | 29 | /* |
30 | * The DMA modes reflect the settings for the ISA DMA controller | ||
31 | */ | ||
32 | #define DMA_MODE_MASK 0xcc | ||
30 | 33 | ||
31 | #define DMA_MODE_READ 0 | 34 | #define DMA_MODE_READ 0x44 |
32 | #define DMA_MODE_WRITE 1 | 35 | #define DMA_MODE_WRITE 0x48 |
33 | #define DMA_MODE_CASCADE 2 | 36 | #define DMA_MODE_CASCADE 0xc0 |
34 | #define DMA_AUTOINIT 4 | 37 | #define DMA_AUTOINIT 0x10 |
35 | 38 | ||
36 | extern spinlock_t dma_spin_lock; | 39 | extern spinlock_t dma_spin_lock; |
37 | 40 | ||
diff --git a/arch/arm/kernel/dma-isa.c b/arch/arm/kernel/dma-isa.c index da02a7ff3419..0e88e46fc732 100644 --- a/arch/arm/kernel/dma-isa.c +++ b/arch/arm/kernel/dma-isa.c | |||
@@ -24,11 +24,6 @@ | |||
24 | #include <asm/dma.h> | 24 | #include <asm/dma.h> |
25 | #include <asm/mach/dma.h> | 25 | #include <asm/mach/dma.h> |
26 | 26 | ||
27 | #define ISA_DMA_MODE_READ 0x44 | ||
28 | #define ISA_DMA_MODE_WRITE 0x48 | ||
29 | #define ISA_DMA_MODE_CASCADE 0xc0 | ||
30 | #define ISA_DMA_AUTOINIT 0x10 | ||
31 | |||
32 | #define ISA_DMA_MASK 0 | 27 | #define ISA_DMA_MASK 0 |
33 | #define ISA_DMA_MODE 1 | 28 | #define ISA_DMA_MODE 1 |
34 | #define ISA_DMA_CLRFF 2 | 29 | #define ISA_DMA_CLRFF 2 |
@@ -67,20 +62,17 @@ static void isa_enable_dma(unsigned int chan, dma_t *dma) | |||
67 | unsigned int mode; | 62 | unsigned int mode; |
68 | enum dma_data_direction direction; | 63 | enum dma_data_direction direction; |
69 | 64 | ||
70 | mode = chan & 3; | 65 | mode = (chan & 3) | dma->dma_mode; |
71 | switch (dma->dma_mode & DMA_MODE_MASK) { | 66 | switch (dma->dma_mode & DMA_MODE_MASK) { |
72 | case DMA_MODE_READ: | 67 | case DMA_MODE_READ: |
73 | mode |= ISA_DMA_MODE_READ; | ||
74 | direction = DMA_FROM_DEVICE; | 68 | direction = DMA_FROM_DEVICE; |
75 | break; | 69 | break; |
76 | 70 | ||
77 | case DMA_MODE_WRITE: | 71 | case DMA_MODE_WRITE: |
78 | mode |= ISA_DMA_MODE_WRITE; | ||
79 | direction = DMA_TO_DEVICE; | 72 | direction = DMA_TO_DEVICE; |
80 | break; | 73 | break; |
81 | 74 | ||
82 | case DMA_MODE_CASCADE: | 75 | case DMA_MODE_CASCADE: |
83 | mode |= ISA_DMA_MODE_CASCADE; | ||
84 | direction = DMA_BIDIRECTIONAL; | 76 | direction = DMA_BIDIRECTIONAL; |
85 | break; | 77 | break; |
86 | 78 | ||
@@ -121,9 +113,6 @@ static void isa_enable_dma(unsigned int chan, dma_t *dma) | |||
121 | outb(length, isa_dma_port[chan][ISA_DMA_COUNT]); | 113 | outb(length, isa_dma_port[chan][ISA_DMA_COUNT]); |
122 | outb(length >> 8, isa_dma_port[chan][ISA_DMA_COUNT]); | 114 | outb(length >> 8, isa_dma_port[chan][ISA_DMA_COUNT]); |
123 | 115 | ||
124 | if (dma->dma_mode & DMA_AUTOINIT) | ||
125 | mode |= ISA_DMA_AUTOINIT; | ||
126 | |||
127 | outb(mode, isa_dma_port[chan][ISA_DMA_MODE]); | 116 | outb(mode, isa_dma_port[chan][ISA_DMA_MODE]); |
128 | dma->invalid = 0; | 117 | dma->invalid = 0; |
129 | } | 118 | } |