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authorSantosh Shilimkar <santosh.shilimkar@ti.com>2010-05-20 03:33:38 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-05-20 18:52:38 -0400
commita901ff715d53c109821cbbd9d7ea1f2a311646a9 (patch)
tree0d2eaa7e5ffa29aa15d966545028a7fc47d76474 /arch/arm
parente1695307e6b85477afd2421d3b4891ca5bea8300 (diff)
ARM: 6139/1: ARMv7: Use the Inner Shareable I-cache on MP
This patch fixes the flush_cache_all for ARMv7 SMP.It was missing from commit b8349b569aae661dea9d59d7d2ee587ccea3336c Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Cc: <stable@kernel.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mm/cache-v7.S4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 06a90dcfc60a..37c8157e116e 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -91,7 +91,11 @@ ENTRY(v7_flush_kern_cache_all)
91 THUMB( stmfd sp!, {r4-r7, r9-r11, lr} ) 91 THUMB( stmfd sp!, {r4-r7, r9-r11, lr} )
92 bl v7_flush_dcache_all 92 bl v7_flush_dcache_all
93 mov r0, #0 93 mov r0, #0
94#ifdef CONFIG_SMP
95 mcr p15, 0, r0, c7, c1, 0 @ invalidate I-cache inner shareable
96#else
94 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 97 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
98#endif
95 ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} ) 99 ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
96 THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} ) 100 THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} )
97 mov pc, lr 101 mov pc, lr